# DDR3_Controller
# :construction: :construction_worker_man: :construction_worker_man:  UNDER CONSTRUCTION :construction_worker_man: :construction_worker_man: :construction: 

## Sequential Read
![image](https://user-images.githubusercontent.com/87559347/230342721-c5a575db-0518-4771-a5e6-7fa7e3044273.png)  

## Sequential Read then Sequential Write
![image](https://user-images.githubusercontent.com/87559347/230336798-619a629d-9f7d-431f-8887-a05965b1c70a.png)


## Random Access
![image](https://user-images.githubusercontent.com/87559347/230362722-256dafff-04c1-4052-b664-6b3d234d9089.png)

## Sequential Read Until Next Bank
![image](https://user-images.githubusercontent.com/87559347/230366265-a10b22b1-8113-46f7-9980-f8938a0b4a0c.png)

# PHY Interface    
## WRITE OPERATION   

![image](https://user-images.githubusercontent.com/87559347/233351111-10434e18-4c5c-4751-95c5-536288c514ed.png)

## Sequential Write


![image](https://user-images.githubusercontent.com/87559347/233395320-66a16ad8-1d56-4850-b82e-39abda92366f.png)

## BITSLIP_DQS_TRAIN STATE:

![image](https://user-images.githubusercontent.com/87559347/234852977-21656591-5a52-4916-8546-caa929f273cc.png)

## MPR_READ STATE:
![image](https://user-images.githubusercontent.com/87559347/234854161-3d8ed26a-3ddf-4cf6-a440-616361ee5715.png)

## BITSLIP_DQ_TRAIN STATE: 
![image](https://user-images.githubusercontent.com/87559347/234854620-39d95493-ecc8-4b8f-b391-0f532fff5760.png)