[*]
[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
[*] Thu Sep 14 06:23:44 2023
[*]
[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd"
[dumpfile_mtime] "Thu Sep 14 06:21:18 2023"
[dumpfile_size] 165043
[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal.gtkw"
[timestart] 0
[size] 1848 1126
[pos] -1 -1
*-4.925239 67 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] ddr3_controller.
[treeopen] ddr3_controller.wb_properties.
[sst_width] 391
[signals_width] 541
[sst_expanded] 1
[sst_vpaned_height] 743
@420
smt_step
@28
ddr3_controller.i_controller_clk
ddr3_controller.i_rst_n
ddr3_controller.reset_done
@24
ddr3_controller.instruction_address[4:0]
ddr3_controller.delay_counter[15:0]
@28
ddr3_controller.o_wb_stall_q
ddr3_controller.i_wb_cyc
@22
ddr3_controller.stage2_aux[15:0]
@28
ddr3_controller.pause_counter
@24
ddr3_controller.state_calibrate[5:0]
@28
ddr3_controller.past_sync_rst_controller
ddr3_controller.sync_rst_controller
@29
+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
@c00029
+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
@29
(0)ddr3_controller.cmd_d<1>[23:0]
(1)ddr3_controller.cmd_d<1>[23:0]
(2)ddr3_controller.cmd_d<1>[23:0]
(3)ddr3_controller.cmd_d<1>[23:0]
(4)ddr3_controller.cmd_d<1>[23:0]
(5)ddr3_controller.cmd_d<1>[23:0]
(6)ddr3_controller.cmd_d<1>[23:0]
(7)ddr3_controller.cmd_d<1>[23:0]
(8)ddr3_controller.cmd_d<1>[23:0]
(9)ddr3_controller.cmd_d<1>[23:0]
(10)ddr3_controller.cmd_d<1>[23:0]
(11)ddr3_controller.cmd_d<1>[23:0]
(12)ddr3_controller.cmd_d<1>[23:0]
(13)ddr3_controller.cmd_d<1>[23:0]
(14)ddr3_controller.cmd_d<1>[23:0]
(15)ddr3_controller.cmd_d<1>[23:0]
(16)ddr3_controller.cmd_d<1>[23:0]
(17)ddr3_controller.cmd_d<1>[23:0]
(18)ddr3_controller.cmd_d<1>[23:0]
(19)ddr3_controller.cmd_d<1>[23:0]
(20)ddr3_controller.cmd_d<1>[23:0]
(21)ddr3_controller.cmd_d<1>[23:0]
(22)ddr3_controller.cmd_d<1>[23:0]
(23)ddr3_controller.cmd_d<1>[23:0]
@1401201
-group_end
@c00029
+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
@29
(0)ddr3_controller.cmd_d<2>[23:0]
(1)ddr3_controller.cmd_d<2>[23:0]
(2)ddr3_controller.cmd_d<2>[23:0]
(3)ddr3_controller.cmd_d<2>[23:0]
(4)ddr3_controller.cmd_d<2>[23:0]
(5)ddr3_controller.cmd_d<2>[23:0]
(6)ddr3_controller.cmd_d<2>[23:0]
(7)ddr3_controller.cmd_d<2>[23:0]
(8)ddr3_controller.cmd_d<2>[23:0]
(9)ddr3_controller.cmd_d<2>[23:0]
(10)ddr3_controller.cmd_d<2>[23:0]
(11)ddr3_controller.cmd_d<2>[23:0]
(12)ddr3_controller.cmd_d<2>[23:0]
(13)ddr3_controller.cmd_d<2>[23:0]
(14)ddr3_controller.cmd_d<2>[23:0]
(15)ddr3_controller.cmd_d<2>[23:0]
(16)ddr3_controller.cmd_d<2>[23:0]
(17)ddr3_controller.cmd_d<2>[23:0]
(18)ddr3_controller.cmd_d<2>[23:0]
(19)ddr3_controller.cmd_d<2>[23:0]
(20)ddr3_controller.cmd_d<2>[23:0]
(21)ddr3_controller.cmd_d<2>[23:0]
(22)ddr3_controller.cmd_d<2>[23:0]
(23)ddr3_controller.cmd_d<2>[23:0]
@1401201
-group_end
@29
+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
@28
ddr3_controller.f_aux_ack_pipe_after_stage2<0>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<1>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<2>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<3>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<4>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<5>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<6>[16:0]
@22
ddr3_controller.o_wb_ack_read_q<0>[16:0]
ddr3_controller.o_wb_ack_read_q<1>[16:0]
ddr3_controller.o_wb_ack_read_q<2>[16:0]
ddr3_controller.o_wb_ack_read_q<3>[16:0]
ddr3_controller.o_wb_ack_read_q<4>[16:0]
ddr3_controller.o_wb_ack_read_q<5>[16:0]
ddr3_controller.o_wb_ack_read_q<6>[16:0]
ddr3_controller.o_wb_ack_read_q<7>[16:0]
ddr3_controller.o_wb_ack_read_q<8>[16:0]
ddr3_controller.o_wb_ack_read_q<9>[16:0]
ddr3_controller.o_wb_ack_read_q<a>[16:0]
ddr3_controller.o_wb_ack_read_q<b>[16:0]
ddr3_controller.o_wb_ack_read_q<c>[16:0]
ddr3_controller.o_wb_ack_read_q<d>[16:0]
ddr3_controller.o_wb_ack_read_q<e>[16:0]
ddr3_controller.o_wb_ack_read_q<f>[16:0]
@24
ddr3_controller.f_sum_of_pending_acks[15:0]
@28
ddr3_controller.stage1_pending
ddr3_controller.stage2_pending
@22
ddr3_controller.o_wb_ack_read_q<0>[16:0]
ddr3_controller.o_wb_ack_read_q<1>[16:0]
ddr3_controller.o_wb_ack_read_q<2>[16:0]
ddr3_controller.calib_addr[23:0]
ddr3_controller.calib_addr_plus_anticipate[23:0]
ddr3_controller.calib_aux[15:0]
ddr3_controller.calib_data[511:0]
ddr3_controller.calib_sel[63:0]
@28
ddr3_controller.calib_stb
ddr3_controller.calib_we
@200
-
@28
ddr3_controller.wb_properties.i_wb_cyc
@22
ddr3_controller.wb_properties.f_outstanding[3:0]
ddr3_controller.wb_properties.f_nacks[3:0]
ddr3_controller.wb_properties.f_nreqs[3:0]
@28
ddr3_controller.wb_properties.i_wb_ack
ddr3_controller.wb_properties.i_wb_err
@200
-
@28
ddr3_controller.fifo_1.empty
@24
ddr3_controller.fifo_1.fifo_reg<0>[24:0]
ddr3_controller.fifo_1.fifo_reg<1>[24:0]
@28
ddr3_controller.fifo_1.full
ddr3_controller.fifo_1.i_clk
ddr3_controller.fifo_1.i_rst_n
@22
ddr3_controller.fifo_1.read_data[24:0]
ddr3_controller.fifo_1.read_data_next[24:0]
@28
ddr3_controller.fifo_1.read_fifo
ddr3_controller.fifo_1.read_pointer
@22
ddr3_controller.fifo_1.write_data[24:0]
@28
ddr3_controller.fifo_1.write_fifo
ddr3_controller.fifo_1.write_pointer
@200
-
@28
ddr3_controller.f_read_fifo
ddr3_controller.f_write_fifo
ddr3_controller.o_wb_stall
ddr3_controller.i_wb_stb
ddr3_controller.stage1_pending
ddr3_controller.stage2_pending
@200
-
@28
ddr3_controller.f_empty
@22
ddr3_controller.calib_aux[15:0]
ddr3_controller.calib_data[511:0]
ddr3_controller.calib_sel[63:0]
@28
ddr3_controller.calib_stb
ddr3_controller.calib_we
@24
ddr3_controller.calib_addr[23:0]
@28
ddr3_controller.bank_status_q[7:0]
ddr3_controller.f_bank_status[7:0]
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<1>[3:0]
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
ddr3_controller.delay_before_write_counter_q<1>[3:0]
@200
-
@24
ddr3_controller.stage1_bank[2:0]
ddr3_controller.stage2_bank[2:0]
@c00024
ddr3_controller.stage1_next_bank[2:0]
@28
(0)ddr3_controller.stage1_next_bank[2:0]
(1)ddr3_controller.stage1_next_bank[2:0]
(2)ddr3_controller.stage1_next_bank[2:0]
@1401200
-group_end
@200
-
@24
ddr3_controller.f_sum_of_pending_acks[15:0]
ddr3_controller.wb_properties.f_ackwait_count[3:0]
@28
ddr3_controller.f_ack_pipe_after_stage2[6:0]
ddr3_controller.delay_counter_is_zero
@200
-
@28
ddr3_controller.stage1_pending
ddr3_controller.stage2_pending
ddr3_controller.shift_reg_read_pipe_q<4>[16:0]
ddr3_controller.shift_reg_read_pipe_q<3>[16:0]
@c00028
ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
@28
(0)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(1)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(2)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(3)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(4)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(5)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(6)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(7)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(8)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(9)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(10)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(11)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(12)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(13)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(14)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(15)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
(16)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
@1401200
-group_end
@c00028
ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
@28
(0)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(1)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(2)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(3)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(4)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(5)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(6)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(7)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(8)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(9)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(10)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(11)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(12)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(13)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(14)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(15)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
(16)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
@1401200
-group_end
@28
ddr3_controller.shift_reg_read_pipe_q<0>[16:0]
@22
ddr3_controller.o_wb_ack_read_q<1>[16:0]
ddr3_controller.o_wb_ack_read_q<0>[16:0]
@200
-
@28
ddr3_controller.f_bank_status[7:0]
ddr3_controller.bank_status_q[7:0]
@22
ddr3_controller.bank[31:0]
@200
-
@22
ddr3_controller.bank[31:0]
@200
-
@28
ddr3_controller.fifo_1.read_pointer
ddr3_controller.fifo_1.write_pointer
@24
ddr3_controller.wb_properties.f_outstanding[3:0]
ddr3_controller.f_sum_of_pending_acks[15:0]
@28
ddr3_controller.wb_properties.i_wb_cyc
@200
-
@28
ddr3_controller.i_wb_stb
ddr3_controller.o_wb_stall
ddr3_controller.i_wb_cyc
ddr3_controller.o_wb_ack
ddr3_controller.o_wb_stall_d
ddr3_controller.o_wb_stall_q
ddr3_controller.delay_counter_is_zero
@200
-
@28
ddr3_controller.stage1_stall
ddr3_controller.stage1_pending
ddr3_controller.stage1_we
@22
ddr3_controller.stage1_aux[15:0]
@24
ddr3_controller.stage1_bank[2:0]
@22
ddr3_controller.stage1_col[9:0]
ddr3_controller.stage1_row[13:0]
@200
-
@28
ddr3_controller.stage2_stall
ddr3_controller.stage2_pending
ddr3_controller.stage2_update
ddr3_controller.stage2_we
@c00022
ddr3_controller.stage2_aux[15:0]
@28
(0)ddr3_controller.stage2_aux[15:0]
(1)ddr3_controller.stage2_aux[15:0]
(2)ddr3_controller.stage2_aux[15:0]
(3)ddr3_controller.stage2_aux[15:0]
(4)ddr3_controller.stage2_aux[15:0]
(5)ddr3_controller.stage2_aux[15:0]
(6)ddr3_controller.stage2_aux[15:0]
(7)ddr3_controller.stage2_aux[15:0]
(8)ddr3_controller.stage2_aux[15:0]
(9)ddr3_controller.stage2_aux[15:0]
(10)ddr3_controller.stage2_aux[15:0]
(11)ddr3_controller.stage2_aux[15:0]
(12)ddr3_controller.stage2_aux[15:0]
(13)ddr3_controller.stage2_aux[15:0]
(14)ddr3_controller.stage2_aux[15:0]
(15)ddr3_controller.stage2_aux[15:0]
@1401200
-group_end
@24
ddr3_controller.stage2_bank[2:0]
@22
ddr3_controller.stage2_col[9:0]
ddr3_controller.stage2_row[13:0]
@200
-
@28
+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
@c00028
+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
@28
(0)ddr3_controller.cmd_d<1>[23:0]
(1)ddr3_controller.cmd_d<1>[23:0]
(2)ddr3_controller.cmd_d<1>[23:0]
(3)ddr3_controller.cmd_d<1>[23:0]
(4)ddr3_controller.cmd_d<1>[23:0]
(5)ddr3_controller.cmd_d<1>[23:0]
(6)ddr3_controller.cmd_d<1>[23:0]
(7)ddr3_controller.cmd_d<1>[23:0]
(8)ddr3_controller.cmd_d<1>[23:0]
(9)ddr3_controller.cmd_d<1>[23:0]
(10)ddr3_controller.cmd_d<1>[23:0]
(11)ddr3_controller.cmd_d<1>[23:0]
(12)ddr3_controller.cmd_d<1>[23:0]
(13)ddr3_controller.cmd_d<1>[23:0]
(14)ddr3_controller.cmd_d<1>[23:0]
(15)ddr3_controller.cmd_d<1>[23:0]
(16)ddr3_controller.cmd_d<1>[23:0]
(17)ddr3_controller.cmd_d<1>[23:0]
(18)ddr3_controller.cmd_d<1>[23:0]
(19)ddr3_controller.cmd_d<1>[23:0]
(20)ddr3_controller.cmd_d<1>[23:0]
(21)ddr3_controller.cmd_d<1>[23:0]
(22)ddr3_controller.cmd_d<1>[23:0]
(23)ddr3_controller.cmd_d<1>[23:0]
@1401200
-group_end
@c00028
+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
@28
(0)ddr3_controller.cmd_d<2>[23:0]
(1)ddr3_controller.cmd_d<2>[23:0]
(2)ddr3_controller.cmd_d<2>[23:0]
(3)ddr3_controller.cmd_d<2>[23:0]
(4)ddr3_controller.cmd_d<2>[23:0]
(5)ddr3_controller.cmd_d<2>[23:0]
(6)ddr3_controller.cmd_d<2>[23:0]
(7)ddr3_controller.cmd_d<2>[23:0]
(8)ddr3_controller.cmd_d<2>[23:0]
(9)ddr3_controller.cmd_d<2>[23:0]
(10)ddr3_controller.cmd_d<2>[23:0]
(11)ddr3_controller.cmd_d<2>[23:0]
(12)ddr3_controller.cmd_d<2>[23:0]
(13)ddr3_controller.cmd_d<2>[23:0]
(14)ddr3_controller.cmd_d<2>[23:0]
(15)ddr3_controller.cmd_d<2>[23:0]
(16)ddr3_controller.cmd_d<2>[23:0]
(17)ddr3_controller.cmd_d<2>[23:0]
(18)ddr3_controller.cmd_d<2>[23:0]
(19)ddr3_controller.cmd_d<2>[23:0]
(20)ddr3_controller.cmd_d<2>[23:0]
(21)ddr3_controller.cmd_d<2>[23:0]
(22)ddr3_controller.cmd_d<2>[23:0]
(23)ddr3_controller.cmd_d<2>[23:0]
@1401200
-group_end
@28
+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
@200
-
@24
ddr3_controller.wb_properties.f_nacks[3:0]
ddr3_controller.wb_properties.f_nreqs[3:0]
@28
ddr3_controller.stage2_update
@200
-
-
@22
ddr3_controller.f_aux_ack_pipe_after_stage2<0>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<1>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<2>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<3>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<4>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<5>[16:0]
ddr3_controller.f_aux_ack_pipe_after_stage2<6>[16:0]
@200
-
@22
ddr3_controller.o_wb_ack_read_q<2>[16:0]
ddr3_controller.o_wb_ack_read_q<3>[16:0]
ddr3_controller.o_wb_ack_read_q<4>[16:0]
ddr3_controller.o_wb_ack_read_q<5>[16:0]
ddr3_controller.o_wb_ack_read_q<6>[16:0]
ddr3_controller.o_wb_ack_read_q<7>[16:0]
ddr3_controller.o_wb_ack_read_q<8>[16:0]
ddr3_controller.o_wb_ack_read_q<9>[16:0]
@24
ddr3_controller.added_read_pipe_max[3:0]
@28
ddr3_controller.o_wb_ack
@200
-
@28
ddr3_controller.o_wb_ack
ddr3_controller.fifo_1.empty
ddr3_controller.fifo_1.full
ddr3_controller.fifo_1.empty
ddr3_controller.fifo_1.full
ddr3_controller.fifo_1.read_fifo
ddr3_controller.fifo_1.write_fifo
ddr3_controller.fifo_1.read_pointer
ddr3_controller.fifo_1.write_pointer
@200
-
@24
ddr3_controller.added_read_pipe_max[3:0]
@200
-
@22
ddr3_controller.i_aux[15:0]
ddr3_controller.o_aux[15:0]
@200
-
@22
ddr3_controller.stage1_aux[15:0]
ddr3_controller.stage2_aux[15:0]
ddr3_controller.write_pattern[127:0]
ddr3_controller.o_wb_ack_read_q<0>[16:0]
ddr3_controller.o_wb_ack_read_q<1>[16:0]
ddr3_controller.shift_reg_read_pipe_q<0>[16:0]
ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
ddr3_controller.shift_reg_read_pipe_q<3>[16:0]
ddr3_controller.shift_reg_read_pipe_q<4>[16:0]
ddr3_controller.shift_reg_read_pipe_d<0>[16:0]
ddr3_controller.shift_reg_read_pipe_d<1>[16:0]
ddr3_controller.shift_reg_read_pipe_d<2>[16:0]
ddr3_controller.shift_reg_read_pipe_d<3>[16:0]
@200
-
@28
ddr3_controller.fifo_1.i_rst_n
@200
-
@28
ddr3_controller.o_wb_stall
ddr3_controller.o_wb_stall_d
ddr3_controller.i_wb_cyc
ddr3_controller.i_wb_stb
ddr3_controller.i_wb_we
@24
ddr3_controller.o_wb_ack
@200
-
@24
ddr3_controller.f_activate_slot[1:0]
ddr3_controller.f_precharge_slot[1:0]
ddr3_controller.f_read_slot[1:0]
ddr3_controller.f_write_slot[1:0]
@28
ddr3_controller.f_read_fifo
ddr3_controller.f_write_fifo
ddr3_controller.i_wb_cyc
ddr3_controller.f_empty
ddr3_controller.fifo_1.empty
ddr3_controller.f_full
@200
-
@24
ddr3_controller.delay_counter[15:0]
ddr3_controller.stage1_bank[2:0]
ddr3_controller.stage2_bank[2:0]
@28
ddr3_controller.stage1_we
ddr3_controller.stage2_we
ddr3_controller.issue_read_command
ddr3_controller.issue_write_command
@200
-
@28
ddr3_controller.bank_status_q[7:0]
@22
ddr3_controller.delay_before_write_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<7>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
ddr3_controller.delay_before_activate_counter_q<7>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<0>[3:0]
ddr3_controller.delay_before_activate_counter_q<1>[3:0]
ddr3_controller.delay_before_activate_counter_q<2>[3:0]
ddr3_controller.delay_before_activate_counter_q<3>[3:0]
ddr3_controller.delay_before_activate_counter_q<4>[3:0]
ddr3_controller.delay_before_activate_counter_q<5>[3:0]
ddr3_controller.delay_before_activate_counter_q<6>[3:0]
ddr3_controller.delay_before_activate_counter_q<7>[3:0]
ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
ddr3_controller.delay_before_precharge_counter_q<3>[3:0]
ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
ddr3_controller.delay_before_precharge_counter_q<5>[3:0]
ddr3_controller.delay_before_precharge_counter_q<6>[3:0]
ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
ddr3_controller.delay_before_read_counter_q<0>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
ddr3_controller.delay_before_read_counter_q<2>[3:0]
ddr3_controller.delay_before_read_counter_q<3>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<5>[3:0]
ddr3_controller.delay_before_read_counter_q<6>[3:0]
ddr3_controller.delay_before_read_counter_q<7>[3:0]
ddr3_controller.delay_before_write_counter_q<0>[3:0]
ddr3_controller.delay_before_write_counter_q<1>[3:0]
ddr3_controller.delay_before_write_counter_q<2>[3:0]
ddr3_controller.delay_before_write_counter_q<3>[3:0]
ddr3_controller.delay_before_write_counter_q<4>[3:0]
ddr3_controller.delay_before_write_counter_q<5>[3:0]
ddr3_controller.delay_before_write_counter_q<6>[3:0]
ddr3_controller.delay_before_write_counter_q<7>[3:0]
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<4>[3:0]
ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
ddr3_controller.delay_before_write_counter_q<4>[3:0]
@200
-
@28
ddr3_controller.cmd_odt
@24
ddr3_controller.instruction_address[4:0]
@28
ddr3_controller.stage1_pending
ddr3_controller.stage1_we
ddr3_controller.stage2_pending
ddr3_controller.stage2_we
@24
ddr3_controller.stage1_bank[2:0]
ddr3_controller.stage2_bank[2:0]
@22
ddr3_controller.delay_before_write_counter_q<4>[3:0]
ddr3_controller.delay_before_read_counter_q<4>[3:0]
@28
ddr3_controller.o_wb_stall_d
@24
ddr3_controller.stage1_col[9:0]
ddr3_controller.stage1_row[13:0]
ddr3_controller.stage2_row[13:0]
ddr3_controller.stage1_next_bank[2:0]
@c00024
ddr3_controller.stage1_next_row[13:0]
@28
(0)ddr3_controller.stage1_next_row[13:0]
(1)ddr3_controller.stage1_next_row[13:0]
(2)ddr3_controller.stage1_next_row[13:0]
(3)ddr3_controller.stage1_next_row[13:0]
(4)ddr3_controller.stage1_next_row[13:0]
(5)ddr3_controller.stage1_next_row[13:0]
(6)ddr3_controller.stage1_next_row[13:0]
(7)ddr3_controller.stage1_next_row[13:0]
(8)ddr3_controller.stage1_next_row[13:0]
(9)ddr3_controller.stage1_next_row[13:0]
(10)ddr3_controller.stage1_next_row[13:0]
(11)ddr3_controller.stage1_next_row[13:0]
(12)ddr3_controller.stage1_next_row[13:0]
(13)ddr3_controller.stage1_next_row[13:0]
@1401200
-group_end
@200
-
@22
ddr3_controller.delay_before_activate_counter_q<0>[3:0]
ddr3_controller.delay_before_activate_counter_q<1>[3:0]
@200
-
@22
ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
@200
-
@22
ddr3_controller.delay_before_read_counter_q<0>[3:0]
ddr3_controller.delay_before_read_counter_q<1>[3:0]
@200
-
@24
ddr3_controller.bank_active_row_q<0>[13:0]
ddr3_controller.bank_active_row_q<1>[13:0]
ddr3_controller.bank_active_row_q<2>[13:0]
ddr3_controller.bank_active_row_q<3>[13:0]
ddr3_controller.bank_active_row_q<4>[13:0]
ddr3_controller.bank_active_row_q<5>[13:0]
ddr3_controller.bank_active_row_q<6>[13:0]
ddr3_controller.bank_active_row_q<7>[13:0]
[pattern_trace] 1
[pattern_trace] 0