ddr3_controller.v,verilog,xil_defaultlib,../../rtl/ddr3_controller.v,incdir="../../testbench"
ddr3_phy.v,verilog,xil_defaultlib,../../rtl/ddr3_phy.v,incdir="../../testbench"
ddr3_top.v,verilog,xil_defaultlib,../../rtl/ddr3_top.v,incdir="../../testbench"
ddr3.sv,systemverilog,xil_defaultlib,../../testbench/ddr3.sv,incdir="../../testbench"
ddr3_module.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_module.sv,incdir="../../testbench"
ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_dimm_micron_sim.sv,incdir="../../testbench"
glbl.v,Verilog,xil_defaultlib