## This file is a general .xdc for the Arty S7-50 Rev. E ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock Signals set_property -dict {PACKAGE_PIN R2 IOSTANDARD SSTL135} [get_ports i_clk] create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk] ## LEDs set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {led[0]}] set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {led[1]}] set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports {led[2]}] set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {led[3]}] ## Buttons set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports i_rst] ## USB-UART Interface set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports tx] set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports rx] ############## DDR3 ################## # DQ PINS set_property SLEW FAST [get_ports {ddr3_dq[0]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}] set_property PACKAGE_PIN K2 [get_ports {ddr3_dq[0]}] set_property SLEW FAST [get_ports {ddr3_dq[1]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}] set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[1]}] set_property SLEW FAST [get_ports {ddr3_dq[2]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}] set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[2]}] set_property SLEW FAST [get_ports {ddr3_dq[3]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}] set_property PACKAGE_PIN M6 [get_ports {ddr3_dq[3]}] set_property SLEW FAST [get_ports {ddr3_dq[4]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}] set_property PACKAGE_PIN K6 [get_ports {ddr3_dq[4]}] set_property SLEW FAST [get_ports {ddr3_dq[5]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}] set_property PACKAGE_PIN M4 [get_ports {ddr3_dq[5]}] set_property SLEW FAST [get_ports {ddr3_dq[6]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}] set_property PACKAGE_PIN L5 [get_ports {ddr3_dq[6]}] set_property SLEW FAST [get_ports {ddr3_dq[7]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}] set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[7]}] set_property SLEW FAST [get_ports {ddr3_dq[8]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}] set_property PACKAGE_PIN N4 [get_ports {ddr3_dq[8]}] set_property SLEW FAST [get_ports {ddr3_dq[9]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}] set_property PACKAGE_PIN R1 [get_ports {ddr3_dq[9]}] set_property SLEW FAST [get_ports {ddr3_dq[10]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}] set_property PACKAGE_PIN N1 [get_ports {ddr3_dq[10]}] set_property SLEW FAST [get_ports {ddr3_dq[11]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}] set_property PACKAGE_PIN N5 [get_ports {ddr3_dq[11]}] set_property SLEW FAST [get_ports {ddr3_dq[12]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}] set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[12]}] set_property SLEW FAST [get_ports {ddr3_dq[13]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}] set_property PACKAGE_PIN P1 [get_ports {ddr3_dq[13]}] set_property SLEW FAST [get_ports {ddr3_dq[14]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}] set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[14]}] set_property SLEW FAST [get_ports {ddr3_dq[15]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}] set_property PACKAGE_PIN P2 [get_ports {ddr3_dq[15]}] # Address Pins set_property SLEW FAST [get_ports {ddr3_addr[13]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}] set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[13]}] set_property SLEW FAST [get_ports {ddr3_addr[12]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}] set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[12]}] set_property SLEW FAST [get_ports {ddr3_addr[11]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}] set_property PACKAGE_PIN T5 [get_ports {ddr3_addr[11]}] set_property SLEW FAST [get_ports {ddr3_addr[10]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}] set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[10]}] set_property SLEW FAST [get_ports {ddr3_addr[9]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}] set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}] set_property SLEW FAST [get_ports {ddr3_addr[8]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}] set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[8]}] set_property SLEW FAST [get_ports {ddr3_addr[7]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}] set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[7]}] set_property SLEW FAST [get_ports {ddr3_addr[6]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}] set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}] set_property SLEW FAST [get_ports {ddr3_addr[5]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}] set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}] set_property SLEW FAST [get_ports {ddr3_addr[4]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}] set_property PACKAGE_PIN T3 [get_ports {ddr3_addr[4]}] set_property SLEW FAST [get_ports {ddr3_addr[3]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}] set_property PACKAGE_PIN V4 [get_ports {ddr3_addr[3]}] set_property SLEW FAST [get_ports {ddr3_addr[2]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}] set_property PACKAGE_PIN V2 [get_ports {ddr3_addr[2]}] set_property SLEW FAST [get_ports {ddr3_addr[1]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}] set_property PACKAGE_PIN R4 [get_ports {ddr3_addr[1]}] set_property SLEW FAST [get_ports {ddr3_addr[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}] set_property PACKAGE_PIN U2 [get_ports {ddr3_addr[0]}] # Bank Pins set_property SLEW FAST [get_ports {ddr3_ba[2]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}] set_property PACKAGE_PIN U3 [get_ports {ddr3_ba[2]}] set_property SLEW FAST [get_ports {ddr3_ba[1]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}] set_property PACKAGE_PIN T1 [get_ports {ddr3_ba[1]}] set_property SLEW FAST [get_ports {ddr3_ba[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}] set_property PACKAGE_PIN V5 [get_ports {ddr3_ba[0]}] # Command Pins set_property SLEW FAST [get_ports ddr3_ras_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n] set_property PACKAGE_PIN U1 [get_ports ddr3_ras_n] set_property SLEW FAST [get_ports ddr3_cas_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n] set_property PACKAGE_PIN V3 [get_ports ddr3_cas_n] set_property SLEW FAST [get_ports ddr3_we_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n] set_property PACKAGE_PIN P7 [get_ports ddr3_we_n] set_property SLEW FAST [get_ports ddr3_reset_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n] set_property PACKAGE_PIN J6 [get_ports ddr3_reset_n] set_property SLEW FAST [get_ports ddr3_cke] set_property IOSTANDARD SSTL135 [get_ports ddr3_cke] set_property PACKAGE_PIN T2 [get_ports ddr3_cke] set_property SLEW FAST [get_ports ddr3_odt] set_property IOSTANDARD SSTL135 [get_ports ddr3_odt] set_property PACKAGE_PIN P5 [get_ports ddr3_odt] set_property SLEW FAST [get_ports ddr3_cs_n] set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n] set_property PACKAGE_PIN R3 [get_ports ddr3_cs_n] # Data Mask Pins set_property SLEW FAST [get_ports {ddr3_dm[0]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}] set_property PACKAGE_PIN K4 [get_ports {ddr3_dm[0]}] set_property SLEW FAST [get_ports {ddr3_dm[1]}] set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}] set_property PACKAGE_PIN M3 [get_ports {ddr3_dm[1]}] # DQS Pins set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}] set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}] set_property PACKAGE_PIN K1 [get_ports {ddr3_dqs_p[0]}] set_property PACKAGE_PIN L1 [get_ports {ddr3_dqs_n[0]}] set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}] set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}] set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}] set_property PACKAGE_PIN N3 [get_ports {ddr3_dqs_p[1]}] set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_n[1]}] # Clock Pins set_property SLEW FAST [get_ports ddr3_clk_p] set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_p] set_property SLEW FAST [get_ports ddr3_clk_n] set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_n] set_property PACKAGE_PIN R5 [get_ports ddr3_clk_p] set_property PACKAGE_PIN T4 [get_ports ddr3_clk_n] ## Configuration options, can be used for all designs set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property CONFIG_MODE SPIx4 [current_design] ## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage ## and to be able to use this pin as an ordinary I/O the following property must ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. set_property INTERNAL_VREF 0.675 [get_iobanks 34]