verilog xil_defaultlib --include "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl" --include "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench" \
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" \
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" \
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" \

sv xil_defaultlib --include "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl" --include "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench" \
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" \
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" \
"/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" \

verilog xil_defaultlib "/home/angelo/Desktop/switch_fpga/DDR3_Controller/xsim/glbl.v"

nosort