Clocks and Reset label i_rst_n i_rst_n i_controller_clk i_controller_clk i_ddr3_clk i_ddr3_clk i_ddr3_clk_90 i_ddr3_clk_90 i_ref_clk i_ref_clk Calibration label sb_err sb_err db_err db_err initial_calibration_done initial_calibration_done calibration_state[319:0] calibration_state[319:0] ASCIIRADIX command_used[23:0] command_used[23:0] ASCIIRADIX #FFD700 true i_ddr3_clk i_ddr3_clk io_ddr3_dq[15:0] io_ddr3_dq[15:0] io_ddr3_dqs[1:0] io_ddr3_dqs[1:0] idelay_dqs[1:0] idelay_dqs[1:0] lane[0:0] lane[0:0] UNSIGNEDDECRADIX instruction_address[4:0] instruction_address[4:0] UNSIGNEDDECRADIX read_test_address_counter[25:0] read_test_address_counter[25:0] UNSIGNEDDECRADIX write_test_address_counter[31:0] write_test_address_counter[31:0] UNSIGNEDDECRADIX correct_read_data[31:0] correct_read_data[31:0] UNSIGNEDDECRADIX wrong_read_data[31:0] wrong_read_data[31:0] UNSIGNEDDECRADIX WIshbone Interface label i_controller_clk i_controller_clk calibration_state[319:0] calibration_state[319:0] ASCIIRADIX i_wb_cyc i_wb_cyc i_wb_stb i_wb_stb i_wb_we i_wb_we i_wb_addr[25:0] i_wb_addr[25:0] i_wb_data[127:0] i_wb_data[127:0] i_wb_sel[15:0] i_wb_sel[15:0] o_wb_stall o_wb_stall o_wb_ack o_wb_ack o_wb_data[127:0] o_wb_data[127:0] DDR3 Interface label o_ddr3_cke o_ddr3_cke o_ddr3_cs_n o_ddr3_cs_n o_ddr3_ras_n o_ddr3_ras_n o_ddr3_cas_n o_ddr3_cas_n o_ddr3_we_n o_ddr3_we_n o_ddr3_addr[15:0] o_ddr3_addr[15:0] o_ddr3_ba_addr[2:0] o_ddr3_ba_addr[2:0] io_ddr3_dq[15:0] io_ddr3_dq[15:0] io_ddr3_dqs[1:0] io_ddr3_dqs[1:0] io_ddr3_dqs_n[1:0] io_ddr3_dqs_n[1:0] o_ddr3_dm[1:0] o_ddr3_dm[1:0] o_ddr3_odt o_ddr3_odt