OpenIPHub DDR3_Memory_Controller uberddr3_axi 1.0 s_axi AWID s_axi_awid AWADDR s_axi_awaddr AWLEN s_axi_awlen AWSIZE s_axi_awsize AWBURST s_axi_awburst AWLOCK s_axi_awlock AWCACHE s_axi_awcache AWPROT s_axi_awprot AWQOS s_axi_awqos AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WLAST s_axi_wlast WVALID s_axi_wvalid WREADY s_axi_wready BID s_axi_bid BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARID s_axi_arid ARADDR s_axi_araddr ARLEN s_axi_arlen ARSIZE s_axi_arsize ARBURST s_axi_arburst ARLOCK s_axi_arlock ARCACHE s_axi_arcache ARPROT s_axi_arprot ARQOS s_axi_arqos ARVALID s_axi_arvalid ARREADY s_axi_arready RID s_axi_rid RDATA s_axi_rdata RRESP s_axi_rresp RLAST s_axi_rlast RVALID s_axi_rvalid RREADY s_axi_rready i_controller_clk CLK i_controller_clk ASSOCIATED_BUSIF s_axi i_ddr3_clk CLK i_ddr3_clk i_ref_clk CLK i_ref_clk i_rst_n RST i_rst_n POLARITY ACTIVE_LOW ddr3 ddr3 CS_N o_ddr3_cs_n CK_P o_ddr3_clk_p CK_N o_ddr3_clk_n DM o_ddr3_dm CAS_N o_ddr3_cas_n DQ io_ddr3_dq ADDR o_ddr3_addr DQS_N io_ddr3_dqs_n RAS_N o_ddr3_ras_n RESET_N o_ddr3_reset_n DQS_P io_ddr3_dqs WE_N o_ddr3_we_n CKE o_ddr3_cke ODT o_ddr3_odt BA o_ddr3_ba_addr i_ddr3_clk_90 CLK i_ddr3_clk_90 s_axi s_axi ddr3_mem ddr3_mem 0x0 268435456 128 memory xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis SystemVerilog ddr3_top_axi xilinx_anylanguagesynthesis_view_fileset viewChecksum e9061c47 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation SystemVerilog ddr3_top_axi xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum e9061c47 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 5c3337af xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset viewChecksum 495a496a i_controller_clk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_ddr3_clk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_ref_clk in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_ddr3_clk_90 in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_rst_n in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awid in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 27 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awlen in 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awsize in 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awburst in 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_awlock in 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awcache in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 3 s_axi_awprot in 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awqos in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wdata in 127 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 15 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wlast in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_bvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_bid out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arvalid in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arid in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 27 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arlen in 7 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arsize in 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_arburst in 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_arlock in 0 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arcache in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 3 s_axi_arprot in 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arqos in 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rvalid out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_rid out 3 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 127 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rlast out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_clk_p out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_clk_n out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_reset_n out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_cke out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_cs_n out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_ras_n out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_cas_n out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_we_n out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_addr out 13 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_ba_addr out 2 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation io_ddr3_dq inout 15 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation io_ddr3_dqs inout 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation io_ddr3_dqs_n inout 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_dm out 1 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_ddr3_odt out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_calib_complete out wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation o_debug1 out 31 0 wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_user_self_refresh in wire xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true CONTROLLER_CLK_PERIOD Controller Clk Period 12000 DDR3_CLK_PERIOD Ddr3 Clk Period 3000 ROW_BITS Row Bits 14 COL_BITS Col Bits 10 BA_BITS Ba Bits 3 BYTE_LANES Byte Lanes 2 AXI_ID_WIDTH Axi Id Width 4 WB2_ADDR_BITS Wb2 Addr Bits 7 WB2_DATA_BITS Wb2 Data Bits 32 MICRON_SIM Micron Sim false ODELAY_SUPPORTED Odelay Supported false SECOND_WISHBONE Second Wishbone false WB_ERROR Wb Error 0 ECC_ENABLE Ecc Enable 0 SELF_REFRESH Self-Refresh 0 DIC Dic "00" RTT_NOM Rtt Nom "011" DQ_BITS Dq Bits 8 serdes_ratio Serdes Ratio 4 wb_addr_bits Wb Addr Bits 24 wb_data_bits Wb Data Bits 128 wb_sel_bits Wb Sel Bits 16 wb2_sel_bits Wb2 Sel Bits 4 cmd_len Cmd Len 24 AXI_LSBS Axi Lsbs 4 AXI_ADDR_WIDTH Axi Addr Width 28 AXI_DATA_WIDTH Axi Data Width 128 BIST_MODE Bist Mode 0 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW choice_pairs_3f983004 0 1 2 choice_pairs_933dc0fc 0 1 2 3 choice_pairs_96a879b9 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset ../rtl/axi/axi_addr.v verilogSource ../rtl/axi/axim2wbsp.v verilogSource ../rtl/axi/aximrd2wbsp.v verilogSource ../rtl/axi/aximwr2wbsp.v verilogSource ../rtl/ddr3_controller.v verilogSource ../rtl/ddr3_phy.v verilogSource ../rtl/ddr3_top.v verilogSource ../rtl/axi/sfifo.v verilogSource ../rtl/axi/skidbuffer.v verilogSource ../rtl/axi/wbarbiter.v verilogSource ../rtl/ecc/ecc_dec.sv systemVerilogSource ../rtl/ecc/ecc_enc.sv systemVerilogSource ../rtl/axi/ddr3_top_axi.v verilogSource CHECKSUM_8c69a3da xilinx_anylanguagebehavioralsimulation_view_fileset ../rtl/axi/axi_addr.v verilogSource ../rtl/axi/axim2wbsp.v verilogSource ../rtl/axi/aximrd2wbsp.v verilogSource ../rtl/axi/aximwr2wbsp.v verilogSource ../rtl/ddr3_controller.v verilogSource ../rtl/ddr3_phy.v verilogSource ../rtl/ddr3_top.v verilogSource ../rtl/axi/sfifo.v verilogSource ../rtl/axi/skidbuffer.v verilogSource ../rtl/axi/wbarbiter.v verilogSource ../rtl/ecc/ecc_dec.sv systemVerilogSource ../rtl/ecc/ecc_enc.sv systemVerilogSource ../rtl/axi/ddr3_top_axi.v verilogSource xilinx_xpgui_view_fileset xgui/uberddr3_axi_v1_0.tcl tclSource CHECKSUM_5c3337af XGUI_VERSION_2 xilinx_utilityxitfiles_view_fileset gui/uberddr3_axi_v1_0.gtcl GTCL UberDDR3 is an open-source DDR3 memory controller designed for Xilinx FPGAs. It features a 4:1 memory interface with customizable parameters, allowing seamless integration with a wide range of DDR3 memory devices. The user interface is AXI4-compliant CONTROLLER_CLK_PERIOD Controller Clock Period (ps) 12000 DDR3_CLK_PERIOD DDR3 Clock Period (ps) 3000 false ROW_BITS Row Bits 14 COL_BITS Column Bits 10 BA_BITS Bank Bits 3 BYTE_LANES Byte Lanes 2 AXI_ID_WIDTH Axi Id Width 4 WB2_ADDR_BITS Wb2 Addr Bits 7 WB2_DATA_BITS Wb2 Data Bits 32 MICRON_SIM Micron Simulation false ODELAY_SUPPORTED ODELAY Supported false SECOND_WISHBONE Second Wishbone false WB_ERROR Wb Error 0 ECC_ENABLE ECC Enable 0 DIC Dic "00" RTT_NOM Rtt Nom "011" DQ_BITS Dq Bits 8 serdes_ratio Serdes Ratio 4 wb_addr_bits Wb Addr Bits 24 false wb_data_bits Wb Data Bits 128 false wb_sel_bits Wb Sel Bits 16 false wb2_sel_bits Wb2 Sel Bits 4 false cmd_len Cmd Len 24 false AXI_LSBS Axi Lsbs 4 false AXI_ADDR_WIDTH Axi Addr Width 28 false AXI_DATA_WIDTH Axi Data Width 128 false Component_Name uberddr3_axi_v1_0 SELF_REFRESH Self-Refresh 0 BIST_MODE BIST Mode 0 virtex7 qvirtex7 versal kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM kintexu /UserIP uberddr3_axi_v1_0 package_project https://github.com/AngeloJacobo/UberDDR3 13 2025-04-19T05:56:34Z 2022.1