From f0b4a15b7cfe34abb729d9007cc2eec3c66c0076 Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Sun, 18 May 2025 17:08:38 +0800 Subject: [PATCH] icarus verilog simulation now working! --- testbench/IOBUFDS_model.v | 6 ----- testbench/ODELAYE2_model.v | 6 ++++- testbench/ddr3_dimm_micron_sim.sv | 43 +++++++++++++++++-------------- testbench/sim_icarus.sh | 15 ++++++++--- testbench/xsim/file_info.txt | 13 ++++++++++ 5 files changed, 54 insertions(+), 29 deletions(-) diff --git a/testbench/IOBUFDS_model.v b/testbench/IOBUFDS_model.v index 8818cb2..1db03e0 100755 --- a/testbench/IOBUFDS_model.v +++ b/testbench/IOBUFDS_model.v @@ -46,12 +46,6 @@ module IOBUFDS_model ( .I(I), // Buffer input .T(T) // 3-state enable input, high=input, low=output ); - integer address_plus_index; - integer address_inv; - always @* begin - address_plus_index = address + index; - address_inv = ~address; - end always @* begin #1; diff --git a/testbench/ODELAYE2_model.v b/testbench/ODELAYE2_model.v index da68051..cdc4a1c 100755 --- a/testbench/ODELAYE2_model.v +++ b/testbench/ODELAYE2_model.v @@ -28,7 +28,11 @@ parameter integer ODELAY_VALUE = 0; parameter PIPE_SEL = "FALSE"; parameter real REFCLK_FREQUENCY = 200.0; parameter SIGNAL_PATTERN = "DATA"; -parameter TEST_MODEL = 1; +`ifdef NO_TEST_MODEL + parameter TEST_MODEL = 0; +`else + parameter TEST_MODEL = 1; +`endif // stop simulation if this modelfile does not support the settings initial begin diff --git a/testbench/ddr3_dimm_micron_sim.sv b/testbench/ddr3_dimm_micron_sim.sv index e7c2216..3665126 100644 --- a/testbench/ddr3_dimm_micron_sim.sv +++ b/testbench/ddr3_dimm_micron_sim.sv @@ -48,7 +48,7 @@ module ddr3_dimm_micron_sim; `ifdef TWO_LANES_x8 localparam BYTE_LANES = 2, - ODELAY_SUPPORTED = 0; + ODELAY_SUPPORTED = 1; `endif `ifdef EIGHT_LANES_x8 @@ -65,11 +65,16 @@ module ddr3_dimm_micron_sim; DUAL_RANK_DIMM = 0, TEST_SELF_REFRESH = 0, SECOND_WISHBONE = 0, - BIST_MODE = 2, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w) + BIST_MODE = 1, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w) DLL_OFF = 0; -localparam WB_DATA_BITS = 8*BYTE_LANES*4*2, - WB_SEL_BITS = WB_DATA_BITS / 8; +localparam WB_DATA_BITS = 8*BYTE_LANES*4*2, + WB_SEL_BITS = WB_DATA_BITS / 8, + WB_ADDR_BITS = ROW_BITS + COL_BITS + BA_BITS - $clog2(4*2) + DUAL_RANK_DIMM, + WB2_ADDR_BITS = 7, + WB2_DATA_BITS = 32, + WB2_SEL_BITS = WB2_DATA_BITS / 8; + reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90; reg i_rst_n; @@ -77,14 +82,14 @@ localparam WB_DATA_BITS = 8*BYTE_LANES*4*2, reg i_wb_cyc; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) reg i_wb_stb; //request a transfer reg i_wb_we; //write-enable (1 = write, 0 = read) - reg[$bits(ddr3_top.i_wb_addr)-1:0] i_wb_addr; //burst-addressable {row,bank,col} - reg[$bits(ddr3_top.i_wb_data)-1:0] i_wb_data; //write data, for a 4:1 controller data width is 8 times the number of pins on the device + reg[WB_ADDR_BITS - 1:0] i_wb_addr; //burst-addressable {row,bank,col} + reg[WB_DATA_BITS - 1:0] i_wb_data; //write data, for a 4:1 controller data width is 8 times the number of pins on the device reg[WB_SEL_BITS - 1:0] i_wb_sel; //byte strobe for write (1 = write the byte) wire o_wb_stall; //1 = busy, cannot accept requests wire o_wb_ack; //1 = read/write request has completed - wire[$bits(ddr3_top.o_wb_data)-1:0] o_wb_data; //read data, for a 4:1 controller data width is 8 times the number of pins on the device - reg[$bits(ddr3_top.i_aux)-1:0] i_aux; - wire[$bits(ddr3_top.o_aux)-1:0] o_aux; + wire[WB_DATA_BITS - 1:0] o_wb_data; //read data, for a 4:1 controller data width is 8 times the number of pins on the device + reg[AUX_WIDTH - 1:0] i_aux; + wire[AUX_WIDTH - 1:0] o_aux; // PHY Interface to DDR3 Device wire[1:0] ck_en; // CKE wire[1:0] cs_n; // chip select signal @@ -93,25 +98,25 @@ localparam WB_DATA_BITS = 8*BYTE_LANES*4*2, wire cas_n; // CAS# wire we_n; // WE# wire reset_n; - wire[$bits(ddr3_top.o_ddr3_addr)-1:0] addr; - wire[$bits(ddr3_top.o_ddr3_ba_addr)-1:0] ba_addr; - wire[$bits(ddr3_top.o_ddr3_dm)-1:0] ddr3_dm; - wire[$bits(ddr3_top.io_ddr3_dq)-1:0] dq; - wire[$bits(ddr3_top.io_ddr3_dqs)-1:0] dqs; - wire[$bits(ddr3_top.io_ddr3_dqs_n)-1:0] dqs_n; + wire[ROW_BITS-1:0] addr; + wire[BA_BITS-1:0] ba_addr; + wire[BYTE_LANES-1:0] ddr3_dm; + wire[(8*BYTE_LANES)-1:0] dq; + wire[BYTE_LANES-1:0] dqs; + wire[BYTE_LANES-1:0] dqs_n; wire[1:0] o_ddr3_clk_p, o_ddr3_clk_n; integer index; // Wishbone 2 (PHY) inputs reg i_wb2_cyc; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) reg i_wb2_stb; //request a transfer reg i_wb2_we; //write-enable (1 = write, 0 = read) - reg[$bits(ddr3_top.i_wb2_addr)-1:0] i_wb2_addr; //memory-mapped register to be accessed - reg[$bits(ddr3_top.i_wb2_data)-1:0] i_wb2_data; //write data - reg[$bits(ddr3_top.i_wb2_sel)-1:0] i_wb2_sel; //byte strobe for write (1 = write the byte) + reg[WB2_ADDR_BITS - 1:0] i_wb2_addr; //memory-mapped register to be accessed + reg[WB2_DATA_BITS - 1:0] i_wb2_data; //write data + reg[WB2_SEL_BITS - 1:0] i_wb2_sel; //byte strobe for write (1 = write the byte) // Wishbone 2 (Controller) outputs wire o_wb2_stall; //1 = busy, cannot accept requests wire o_wb2_ack; //1 = read/write request has completed - wire[$bits(ddr3_top.o_wb2_data)-1:0] o_wb2_data; //read data + wire[WB2_DATA_BITS - 1:0] o_wb2_data; //read data // User enabled self-refresh reg i_user_self_refresh; wire clk_locked; diff --git a/testbench/sim_icarus.sh b/testbench/sim_icarus.sh index 5e88520..ef75d3e 100755 --- a/testbench/sim_icarus.sh +++ b/testbench/sim_icarus.sh @@ -1,4 +1,4 @@ -rm -rf ./uberddr3_sim +rm -rf ./uberddr3_sim ./sim.log iverilog -o uberddr3_sim -g2012 \ -DNO_TEST_MODEL \ -s ddr3_dimm_micron_sim \ @@ -18,7 +18,16 @@ iverilog -o uberddr3_sim -g2012 \ ./OBUF_model.v \ ../rtl/ddr3_top.v \ ../rtl/ddr3_controller.v \ - ../rtl/ddr3_phy.v + ../rtl/ddr3_phy.v \ + ./ddr3_module.sv + +start_time=$(date +%s) + +vvp ./uberddr3_sim > sim.log + +end_time=$(date +%s) +elapsed=$((end_time - start_time)) + +echo "[INFO] Simulation completed in ${elapsed} seconds." -vvp ./uberddr3_sim diff --git a/testbench/xsim/file_info.txt b/testbench/xsim/file_info.txt index 81e40b1..a6e749c 100644 --- a/testbench/xsim/file_info.txt +++ b/testbench/xsim/file_info.txt @@ -1,7 +1,20 @@ +IDELAYCTRL_model.v,verilog,xil_defaultlib,../../testbench/IDELAYCTRL_model.v,incdir="../../testbench" +IDELAYE2_model.v,verilog,xil_defaultlib,../../testbench/IDELAYE2_model.v,incdir="../../testbench" +IOBUF_DCIEN.v,verilog,xil_defaultlib,../../testbench/IOBUF_DCIEN.v,incdir="../../testbench" +IOBUF_model.v,verilog,xil_defaultlib,../../testbench/IOBUF_model.v,incdir="../../testbench" +IOBUFDS_DCIEN_model.v,verilog,xil_defaultlib,../../testbench/IOBUFDS_DCIEN_model.v,incdir="../../testbench" +IOBUFDS_model.v,verilog,xil_defaultlib,../../testbench/IOBUFDS_model.v,incdir="../../testbench" +ISERDESE2_model.v,verilog,xil_defaultlib,../../testbench/ISERDESE2_model.v,incdir="../../testbench" +OBUFDS_model.v,verilog,xil_defaultlib,../../testbench/OBUFDS_model.v,incdir="../../testbench" +ODELAYE2_model.v,verilog,xil_defaultlib,../../testbench/ODELAYE2_model.v,incdir="../../testbench" +OSERDESE2_model.v,verilog,xil_defaultlib,../../testbench/OSERDESE2_model.v,incdir="../../testbench" +OBUF_model.v,verilog,xil_defaultlib,../../testbench/OBUF_model.v,incdir="../../testbench" + ddr3_controller.v,verilog,xil_defaultlib,../../rtl/ddr3_controller.v,incdir="../../testbench" ddr3_phy.v,verilog,xil_defaultlib,../../rtl/ddr3_phy.v,incdir="../../testbench" ddr3_top.v,verilog,xil_defaultlib,../../rtl/ddr3_top.v,incdir="../../testbench" ddr3.sv,systemverilog,xil_defaultlib,../../testbench/ddr3.sv,incdir="../../testbench" ddr3_module.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_module.sv,incdir="../../testbench" ddr3_dimm_micron_sim.sv,systemverilog,xil_defaultlib,../../testbench/ddr3_dimm_micron_sim.sv,incdir="../../testbench" + glbl.v,Verilog,xil_defaultlib