From ee3d9d4be7309ca84fc7465c76316ea612411462 Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Thu, 13 Jul 2023 18:50:56 +0800 Subject: [PATCH] moved phy to TOP and controller to MAIN, removed constraints for xdc file --- sdram_ddr3.txt | 490 ++++++++++++++++++++++--------------------------- 1 file changed, 223 insertions(+), 267 deletions(-) diff --git a/sdram_ddr3.txt b/sdram_ddr3.txt index e4b36ff..e9d4797 100644 --- a/sdram_ddr3.txt +++ b/sdram_ddr3.txt @@ -34,6 +34,7 @@ ## ## }}} @PREFIX=sdram_ddr3 +@PREFIX_WB2=sdram_ddr3_wb2 @DEVID=SDRAM_DDR3 @ACCESS=@$(DEVID)_ACCESS ## LGMEMSZ is the size of the SDRAM in bytes, 29 => 512MB @@ -49,135 +50,255 @@ @SLAVE.TYPE=MEMORY @SLAVE.BUS=wbwide @BUS=wbwide -# @CLOCK.NAME=clk -# @CLOCK.FREQUENCY = 81250000 -## @ERROR.WIRE=@$(PREFIX)_err # 8-bit byte accesses @$ABITS=@$(LGMEMSZ)-@$(UNUSED) @LD.PERM=wx @TOP.PORTLIST= // SDRAM I/O port wires - o_ddr3_reset_n, o_ddr3_cke_n, o_ddr3_clk_p, o_ddr3_clk_n, - o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n, - io_ddr3_dqs_p, io_ddr3_dqs_n, - o_ddr3_a, o_ddr3_ba, - io_ddr3_dq, o_ddr3_dm, o_ddr3_odt + o_ddr3_reset_n, o_ddr3_cke, o_ddr3_clk_p, o_ddr3_clk_n, + o_ddr3_s_n, o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n, + o_ddr3_ba, o_ddr3_a, + o_ddr3_odt, o_ddr3_dm, + io_ddr3_dqs_p, io_ddr3_dqs_n, io_ddr3_dq + + +@TOP.PARAM= + localparam real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module + DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device + localparam ROW_BITS = 14, //width of row address + BA_BITS = 3, //width of bank address + DQ_BITS = 8, //width of DQ + LANES = 8; //8 lanes of DQ + localparam serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD), + wb_data_bits = DQ_BITS*LANES*serdes_ratio*2, + //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits + cmd_len = 4 + 3 + BA_BITS + ROW_BITS; + + @TOP.IODECL= // I/O declarations for the DDR3 SDRAM // {{{ output wire o_ddr3_reset_n; - output wire [0:0] o_ddr3_cke_n; + output wire [0:0] o_ddr3_cke; output wire [0:0] o_ddr3_clk_p, o_ddr3_clk_n; - //output wire [0:0] ddr3_cs_n; // This design has no CS pin - output wire o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n; - output wire [2:0] o_ddr3_ba; - output wire [14:0] o_ddr3_a; + output wire [1:0] o_ddr3_s_n; // o_ddr3_s_n[1] is set to 0 since controller only support single rank + output wire [0:0] o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n; + output wire [BA_BITS-1:0] o_ddr3_ba; + output wire [ROW_BITS-1:0] o_ddr3_a; //set to max of 16 bits, but only ROW_BITS bits are relevant output wire [0:0] o_ddr3_odt; - output wire [7:0] o_ddr3_dm; - inout wire [7:0] io_ddr3_dqs_p, io_ddr3_dqs_n; - inout wire [63:0] io_ddr3_dq; + output wire [LANES-1:0] o_ddr3_dm; + inout wire [(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs_p, io_ddr3_dqs_n; + inout wire [(DQ_BITS*LANES)-1:0] io_ddr3_dq; // }}} + + @TOP.DEFNS= - // Wires necessary to run the SDRAM + // Wires connected to PHY interface of DDR3 controller // {{{ - wire @$(PREFIX)_cyc, @$(PREFIX)_stb, @$(PREFIX)_we, - @$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_err; - wire [(@$(LGMEMSZ)-@$(UNUSED)-1):0] @$(PREFIX)_addr; - wire [(@$(BUS.WIDTH)-1):0] @$(PREFIX)_wdata, - @$(PREFIX)_rdata; - wire [(@$(BUS.WIDTH)/8-1):0] @$(PREFIX)_sel; + wire [DQ_BITS*LANES*8-1:0] @$(PREFIX)_iserdes_data; + wire [LANES*8-1:0] @$(PREFIX)_iserdes_dqs; + wire [LANES*8-1:0] @$(PREFIX)_iserdes_bitslip_reference; + wire @$(PREFIX)_idelayctrl_rdy; + wire [cmd_len*serdes_ratio-1:0] @$(PREFIX)_cmd; + wire @$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control; + wire @$(PREFIX)_toggle_dqs; + wire [wb_data_bits-1:0] @$(PREFIX)_data; + wire [4:0] @$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein; + wire [4:0] @$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein; + wire [LANES-1:0] @$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld; + wire [LANES-1:0] @$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld; + wire [LANES-1:0] @$(PREFIX)_bitslip; // }}} + + @TOP.MAIN= - // The SDRAM interface to an toplevel AXI4 module - // - @$(PREFIX)_cyc, @$(PREFIX)_stb, @$(PREFIX)_we, - @$(PREFIX)_addr, @$(PREFIX)_wdata, @$(PREFIX)_sel, - @$(PREFIX)_stall, @$(PREFIX)_ack, @$(PREFIX)_rdata, - @$(PREFIX)_err + // DDR3 Controller-PHY Interface + @$(PREFIX)_iserdes_data, @$(PREFIX)_iserdes_dqs, + @$(PREFIX)_iserdes_bitslip_reference, + @$(PREFIX)_idelayctrl_rdy, + @$(PREFIX)_cmd, + @$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control, + @$(PREFIX)_toggle_dqs, @$(PREFIX)_data, + @$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein, + @$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein, + @$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld, + @$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld, + @$(PREFIX)_bitslip + + + @TOP.INSERT= - ddr3_top #( - .ROW_BITS(14), //width of row address - .COL_BITS(10), //width of column address - .BA_BITS(3), //width of bank address - .DQ_BITS(8), //width of DQ - .CONTROLLER_CLK_PERIOD(10), //ns, period of clock input to this DDR3 controller module - .DDR3_CLK_PERIOD(2.5), //ns, period of clock input to DDR3 RAM device - .LANES(8), //8 lanes of DQ - .OPT_LOWPOWER(1), //1 = low power, 0 = low logic - .OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction) - ) @$(PREFIX)_inst( - // {{{ - // clock and reset - .i_controller_clk(s_clk), - .i_ddr3_clk(s_clk4x), - .i_ref_clk(s_clk200), - .i_rst_n(!s_reset), - // Wishbone inputs - .i_wb_cyc(@$(PREFIX)_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) - .i_wb_stb(@$(PREFIX)_stb), //request a transfer - .i_wb_we(@$(PREFIX)_we), //write-enable (1 = write, 0 = read) - .i_wb_addr(@$(PREFIX)_addr), //burst-addressable {row,bank,col} - .i_wb_data(@$(PREFIX)_wdata), //write data, for a 4:1 controller data width is 8 times the number of pins on the device - .i_wb_sel(@$(PREFIX)_sel), //byte strobe for write (1 = write the byte) - .i_aux(), //for AXI-interface compatibility (given upon strobe) - // Wishbone outputs - .o_wb_stall(@$(PREFIX)_stall), //1 = busy, cannot accept requests - .o_wb_ack(@$(PREFIX)_ack), //1 = read/write request has completed - .o_wb_data(@$(PREFIX)_rdata), //read data, for a 4:1 controller data width is 8 times the number of pins on the device - .o_aux(), //for AXI-interface compatibility (returned upon ack) - // PHY Interface - .o_ddr3_reset_n(o_ddr3_reset_n), - .o_ddr3_cke(o_ddr3_cke_n), // CKE - .o_ddr3_cs_n(), // chip select signal - .o_ddr3_ras_n(o_ddr3_ras_n), - .o_ddr3_cas_n(o_ddr3_cas_n), - .o_ddr3_we_n(o_ddr3_we_n), - .o_ddr3_addr(o_ddr3_a), - .o_ddr3_ba_addr(o_ddr3_ba), - .io_ddr3_dq(io_ddr3_dq), - .io_ddr3_dqs(io_ddr3_dqs_p), - .io_ddr3_dqs_n(io_ddr3_dqs_n), - .o_ddr3_odt(o_ddr3_odt) // on-die termination - // }}} - ); + // DDR3 PHY Instantiation + ddr3_phy #( + .ROW_BITS(ROW_BITS), //width of row address + .BA_BITS(BA_BITS), //width of bank address + .DQ_BITS(DQ_BITS), //width of DQ + .LANES(LANES), //8 lanes of DQ + .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module + .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD) //ns, period of clock input to DDR3 RAM device + ) @$(PREFIX)_phy_inst ( + // clock and reset + .i_controller_clk(s_clk), + .i_ddr3_clk(s_clk4x), + .i_ref_clk(s_clk200), + .i_rst_n(!s_reset), + // Controller Interface + .i_controller_cmd(@$(PREFIX)_cmd), + .i_controller_dqs_tri_control(@$(PREFIX)_dqs_tri_control), + .i_controller_dq_tri_control(@$(PREFIX)_dq_tri_control), + .i_controller_toggle_dqs(@$(PREFIX)_toggle_dqs), + .i_controller_data(@$(PREFIX)_data), + .i_controller_odelay_data_cntvaluein(@$(PREFIX)_odelay_data_cntvaluein), + .i_controller_odelay_dqs_cntvaluein(@$(PREFIX)_odelay_dqs_cntvaluein), + .i_controller_idelay_data_cntvaluein(@$(PREFIX)_idelay_data_cntvaluein), + .i_controller_idelay_dqs_cntvaluein(@$(PREFIX)_idelay_dqs_cntvaluein), + .i_controller_odelay_data_ld(@$(PREFIX)_odelay_data_ld), + .i_controller_odelay_dqs_ld(@$(PREFIX)_odelay_dqs_ld), + .i_controller_idelay_data_ld(@$(PREFIX)_idelay_data_ld), + .i_controller_idelay_dqs_ld(@$(PREFIX)_idelay_dqs_ld), + .i_controller_bitslip(@$(PREFIX)_bitslip), + .o_controller_iserdes_data(@$(PREFIX)_iserdes_data), + .o_controller_iserdes_dqs(@$(PREFIX)_iserdes_dqs), + .o_controller_iserdes_bitslip_reference(@$(PREFIX)_iserdes_bitslip_reference), + .o_controller_idelayctrl_rdy(@$(PREFIX)_idelayctrl_rdy), + // DDR3 I/O Interface + .o_ddr3_clk_p(o_ddr3_clk_p), + .o_ddr3_clk_n(o_ddr3_clk_n), + .o_ddr3_reset_n(o_ddr3_reset_n), + .o_ddr3_cke(o_ddr3_cke), // CKE + .o_ddr3_cs_n(o_ddr3_s_n[0]), // chip select signal (controls rank 1 only) + .o_ddr3_ras_n(o_ddr3_ras_n), // RAS# + .o_ddr3_cas_n(o_ddr3_cas_n), // CAS# + .o_ddr3_we_n(o_ddr3_we_n), // WE# + .o_ddr3_addr(o_ddr3_a), + .o_ddr3_ba_addr(o_ddr3_ba), + .io_ddr3_dq(io_ddr3_dq), + .io_ddr3_dqs(io_ddr3_dqs_p), + .io_ddr3_dqs_n(io_ddr3_dqs_n), + .o_ddr3_dm(o_ddr3_dm), + .o_ddr3_odt(o_ddr3_odt) // on-die termination + ); + assign o_ddr3_s_n[1] = 1; // set to 1 (disabled) since controller only supports single rank + @MAIN.PORTLIST= - // SDRAM ports - o_@$(PREFIX)_cyc, o_@$(PREFIX)_stb, o_@$(PREFIX)_we, - o_@$(PREFIX)_addr, o_@$(PREFIX)_data, o_@$(PREFIX)_sel, - i_@$(PREFIX)_stall, i_@$(PREFIX)_ack, i_@$(PREFIX)_data, - i_@$(PREFIX)_err + // DDR3 Controller Interface + i_@$(PREFIX)_iserdes_data, i_@$(PREFIX)_iserdes_dqs, + i_@$(PREFIX)_iserdes_bitslip_reference, + i_@$(PREFIX)_idelayctrl_rdy, + o_@$(PREFIX)_cmd, + o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control, + o_@$(PREFIX)_toggle_dqs, o_@$(PREFIX)_data, + o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein, + o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein, + o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld, + o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld, + o_@$(PREFIX)_bitslip, + + +@MAIN.PARAM= + localparam real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module + DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device + localparam ROW_BITS = 14, //width of row address + COL_BITS = 10, //width of column address + BA_BITS = 3, //width of bank address + DQ_BITS = 8, //width of DQ + LANES = 8, //8 lanes of DQ + AUX_WIDTH = 16; + localparam serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD), + wb_data_bits = DQ_BITS*LANES*serdes_ratio*2, + //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits + cmd_len = 4 + 3 + BA_BITS + ROW_BITS; + + @MAIN.IODECL= - // SDRAM I/O declarations + // DDR3 Controller I/O declarations // {{{ - output wire o_@$(PREFIX)_cyc, - o_@$(PREFIX)_stb, o_@$(PREFIX)_we; - output wire [@$(ABITS)-1:0] o_@$(PREFIX)_addr; - output wire [(@$(BUS.WIDTH)-1):0] o_@$(PREFIX)_data; - output wire [(@$(BUS.WIDTH)/8)-1:0] o_@$(PREFIX)_sel; - // - input wire i_@$(PREFIX)_ack; - input wire i_@$(PREFIX)_stall; - input wire [(@$(BUS.WIDTH)-1):0] i_@$(PREFIX)_data; - // Verilator lint_off UNUSED - input wire i_@$(PREFIX)_err; - // Verilator lint_on UNUSED + input wire [DQ_BITS*LANES*8-1:0] i_@$(PREFIX)_iserdes_data; + input wire [LANES*8-1:0] i_@$(PREFIX)_iserdes_dqs; + input wire [LANES*8-1:0] i_@$(PREFIX)_iserdes_bitslip_reference; + input wire i_@$(PREFIX)_idelayctrl_rdy; + output wire [cmd_len*serdes_ratio-1:0] o_@$(PREFIX)_cmd; + output wire o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control; + output wire o_@$(PREFIX)_toggle_dqs; + output wire [wb_data_bits-1:0] o_@$(PREFIX)_data; + output wire [4:0] o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein; + output wire [4:0] o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein; + output wire [LANES-1:0] o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld; + output wire [LANES-1:0] o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld; + output wire [LANES-1:0] o_@$(PREFIX)_bitslip; // }}} + + @MAIN.INSERT= //////////////////////////////////////////////////////////////////////// // - // Export the @$(PREFIX) bus to the top level + // DDR3 Controller instantiation // {{{ - assign o_@$(PREFIX)_cyc = @$(SLAVE.PREFIX)_cyc; - assign o_@$(PREFIX)_stb =(@$(SLAVE.PREFIX)_stb); - assign o_@$(PREFIX)_we = @$(SLAVE.PREFIX)_we; - assign o_@$(PREFIX)_addr = @$(SLAVE.PREFIX)_addr[@$(ABITS)-1:0]; - assign o_@$(PREFIX)_data = @$(SLAVE.PREFIX)_data; - assign o_@$(PREFIX)_sel = @$(SLAVE.PREFIX)_sel; - assign @$(SLAVE.PREFIX)_ack = i_@$(PREFIX)_ack; - assign @$(SLAVE.PREFIX)_stall = i_@$(PREFIX)_stall; - assign @$(SLAVE.PREFIX)_idata = i_@$(PREFIX)_data; + ddr3_controller #( + .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module + .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device + .ROW_BITS(ROW_BITS), //width of row address + .COL_BITS(COL_BITS), //width of column address + .BA_BITS(BA_BITS), //width of bank address + .DQ_BITS(DQ_BITS), //width of DQ + .LANES(LANES), //8 lanes of DQ + .AUX_WIDTH(AUX_WIDTH), // + .OPT_LOWPOWER(1), //1 = low power, 0 = low logic + .OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction) + ) @$(PREFIX)_controller_inst ( + .i_controller_clk(i_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD + .i_rst_n(!i_reset), //200MHz input clock + // Wishbone inputs + .i_wb_cyc(@$(SLAVE.PREFIX)_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) + .i_wb_stb(@$(SLAVE.PREFIX)_stb), //request a transfer + .i_wb_we(@$(SLAVE.PREFIX)_we), //write-enable (1 = write, 0 = read) + .i_wb_addr(@$(SLAVE.PREFIX)_addr), //burst-addressable {row,bank,col} + .i_wb_data(@$(SLAVE.PREFIX)_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device + .i_wb_sel(@$(SLAVE.PREFIX)_sel), //byte strobe for write (1 = write the byte) + .i_aux(), //for AXI-interface compatibility (given upon strobe) + // Wishbone outputs + .o_wb_stall(@$(SLAVE.PREFIX)_stall), //1 = busy, cannot accept requests + .o_wb_ack(@$(SLAVE.PREFIX)_ack), //1 = read/write request has completed + .o_wb_data(@$(SLAVE.PREFIX)_idata), //read data, for a 4:1 controller data width is 8 times the number of pins on the device + .o_aux(), //for AXI-interface compatibility (returned upon ack) + // Wishbone 2 (PHY) inputs + /* + .i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) + .i_wb2_stb(), //request a transfer + .i_wb2_we(), //write-enable (1 = write, 0 = read) + .i_wb2_addr(), // memory-mapped register to be accessed + .i_wb2_data(), //write data + .i_wb2_sel(), //byte strobe for write (1 = write the byte) + // Wishbone 2 (Controller) outputs + .o_wb2_stall(), //1 = busy, cannot accept requests + .o_wb2_ack(), //1 = read/write request has completed + .o_wb2_data(), //read data + */ + // + // PHY interface + .i_phy_iserdes_data(i_@$(PREFIX)_iserdes_data), + .i_phy_iserdes_dqs(i_@$(PREFIX)_iserdes_dqs), + .i_phy_iserdes_bitslip_reference(i_@$(PREFIX)_iserdes_bitslip_reference), + .i_phy_idelayctrl_rdy(i_@$(PREFIX)_idelayctrl_rdy), + .o_phy_cmd(o_@$(PREFIX)_cmd), + .o_phy_dqs_tri_control(o_@$(PREFIX)_dqs_tri_control), + .o_phy_dq_tri_control(o_@$(PREFIX)_dq_tri_control), + .o_phy_toggle_dqs(o_@$(PREFIX)_toggle_dqs), + .o_phy_data(o_@$(PREFIX)_data), + .o_phy_odelay_data_cntvaluein(o_@$(PREFIX)_odelay_data_cntvaluein), + .o_phy_odelay_dqs_cntvaluein(o_@$(PREFIX)_odelay_dqs_cntvaluein), + .o_phy_idelay_data_cntvaluein(o_@$(PREFIX)_idelay_data_cntvaluein), + .o_phy_idelay_dqs_cntvaluein(o_@$(PREFIX)_idelay_dqs_cntvaluein), + .o_phy_odelay_data_ld(o_@$(PREFIX)_odelay_data_ld), + .o_phy_odelay_dqs_ld(o_@$(PREFIX)_odelay_dqs_ld), + .o_phy_idelay_data_ld(o_@$(PREFIX)_idelay_data_ld), + .o_phy_idelay_dqs_ld(o_@$(PREFIX)_idelay_dqs_ld), + .o_phy_bitslip(o_@$(PREFIX)_bitslip) + ); // }}} + + @REGS.N=1 @REGS.0= 0 R_@$(DEVID) @$(DEVID) @REGDEFS.H.DEFNS= @@ -216,169 +337,4 @@ #endif // @$(ACCESS) @SIM.LOAD= m_@$(PREFIX)->load(start, &buf[offset], wlen); - -@XDC.INSERT= - ## DDR3 - ## {{{ - set_property -dict {PACKAGE_PIN V11 IOSTANDARD SSTL15} [get_ports o_ddr3_reset_n] - set_property -dict {PACKAGE_PIN AB11 IOSTANDARD SSTL15} [get_ports o_ddr3_clk_p] - set_property -dict {PACKAGE_PIN AC11 IOSTANDARD SSTL15} [get_ports o_ddr3_clk_n] - #set_property -dict {PACKAGE_PIN AA9 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_p[1]] - #set_property -dict {PACKAGE_PIN AB9 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_n[1]] - set_property -dict {PACKAGE_PIN Y10 IOSTANDARD SSTL15} [get_ports o_ddr3_cke_n] - #set_property -dict {PACKAGE_PIN W9 IOSTANDARD SSTL15} [get_ports o_ddr3_cke_n[1]] - - set_property -dict {PACKAGE_PIN AA10 IOSTANDARD SSTL15} [get_ports o_ddr3_ras_n] - set_property -dict {PACKAGE_PIN AA7 IOSTANDARD SSTL15} [get_ports o_ddr3_cas_n] - set_property -dict {PACKAGE_PIN Y7 IOSTANDARD SSTL15} [get_ports o_ddr3_we_n] - #set_property -dict {PACKAGE_PIN V7 IOSTANDARD SSTL15} [get_ports o_ddr3_s[0]] - #set_property -dict {PACKAGE_PIN Y8 IOSTANDARD SSTL15} [get_ports o_ddr3_s[1]] - set_property -dict {PACKAGE_PIN AA8 IOSTANDARD SSTL15} [get_ports o_ddr3_odt] - #set_property -dict {PACKAGE_PIN V9 IOSTANDARD SSTL15} [get_ports o_ddr3_odt[1] - #set_property -dict {PACKAGE_PIN W10 IOSTANDARD SSTL15} [get_ports i_ddr3_event] - - ### Address lines - ### {{{ - set_property -dict {PACKAGE_PIN AC7 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[0]] - set_property -dict {PACKAGE_PIN V8 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[1]] - set_property -dict {PACKAGE_PIN AC13 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[2]] - - set_property -dict {PACKAGE_PIN AF7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[0]] - set_property -dict {PACKAGE_PIN AD8 IOSTANDARD SSTL15} [get_ports o_ddr3_a[1]] - set_property -dict {PACKAGE_PIN AB10 IOSTANDARD SSTL15} [get_ports o_ddr3_a[2]] - set_property -dict {PACKAGE_PIN AC8 IOSTANDARD SSTL15} [get_ports o_ddr3_a[3]] - set_property -dict {PACKAGE_PIN W11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[4]] - set_property -dict {PACKAGE_PIN AA12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[5]] - set_property -dict {PACKAGE_PIN AC12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[6]] - set_property -dict {PACKAGE_PIN AD13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[7]] - - set_property -dict {PACKAGE_PIN AB12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[8]] - set_property -dict {PACKAGE_PIN AD11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[9]] - set_property -dict {PACKAGE_PIN AE7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[10]] - set_property -dict {PACKAGE_PIN Y11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[11]] - set_property -dict {PACKAGE_PIN AA13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[12]] - set_property -dict {PACKAGE_PIN AB7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[13]] - set_property -dict {PACKAGE_PIN Y13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[14]] - #set_property -dict {PACKAGE_PIN Y12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[15]] - ### }}} - - ### Byte lane #0 - ### {{{ - set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[0]] - set_property -dict {PACKAGE_PIN AC18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[1]] - set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[2]] - set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[3]] - set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[4]] - set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[5]] - set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[6]] - set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[7]] - set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[0]] - set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[0]] - set_property -dict {PACKAGE_PIN AC19 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[0]] - ### }}} - - ### Byte lane #1 - ### {{{ - set_property -dict {PACKAGE_PIN V16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[8]] - set_property -dict {PACKAGE_PIN V18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[9]] - set_property -dict {PACKAGE_PIN AB20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[10]] - set_property -dict {PACKAGE_PIN AB19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[11]] - set_property -dict {PACKAGE_PIN W15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[12]] - set_property -dict {PACKAGE_PIN V19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[13]] - set_property -dict {PACKAGE_PIN W16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[14]] - set_property -dict {PACKAGE_PIN Y17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[15]] - set_property -dict {PACKAGE_PIN W18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[1]] - set_property -dict {PACKAGE_PIN W19 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[1]] - set_property -dict {PACKAGE_PIN V17 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[1]] - ### }}} - - ### Byte lane #2 - ### {{{ - set_property -dict {PACKAGE_PIN AF19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[16]] - set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[17]] - set_property -dict {PACKAGE_PIN AE15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[18]] - set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[19]] - set_property -dict {PACKAGE_PIN AF20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[20]] - set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[21]] - set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[22]] - set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[23]] - set_property -dict {PACKAGE_PIN AE18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[2]] - set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[2]] - set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[2]] - ### }}} - - ### Byte lane #3 - ### {{{ - set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[24]] - set_property -dict {PACKAGE_PIN AB16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[25]] - set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[26]] - set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[27]] - set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[28]] - set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[29]] - set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[30]] - set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[31]] - set_property -dict {PACKAGE_PIN Y15 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[3]] - set_property -dict {PACKAGE_PIN Y16 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[3]] - set_property -dict {PACKAGE_PIN AA14 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[3]] - ### }}} - - ### Byte lane #4 - ### {{{ - set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[32]] - set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[33]] - set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[34]] - set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[35]] - set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[36]] - set_property -dict {PACKAGE_PIN Y6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[37]] - set_property -dict {PACKAGE_PIN Y5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[38]] - set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[39]] - set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[4]] - set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[4]] - set_property -dict {PACKAGE_PIN AC4 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[4]] - ### }}} - - ### Byte lane #5 - ### {{{ - set_property -dict {PACKAGE_PIN AF3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[40]] - set_property -dict {PACKAGE_PIN AE3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[41]] - set_property -dict {PACKAGE_PIN AE2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[42]] - set_property -dict {PACKAGE_PIN AE1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[43]] - set_property -dict {PACKAGE_PIN AE6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[44]] - set_property -dict {PACKAGE_PIN AE5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[45]] - set_property -dict {PACKAGE_PIN AD4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[46]] - set_property -dict {PACKAGE_PIN AD1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[47]] - set_property -dict {PACKAGE_PIN AF5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[5]] - set_property -dict {PACKAGE_PIN AF4 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[5]] - set_property -dict {PACKAGE_PIN AF2 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[5]] - ### }}} - - ### Byte lane #6 - ### {{{ - set_property -dict {PACKAGE_PIN W3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[48]] - set_property -dict {PACKAGE_PIN V4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[49]] - set_property -dict {PACKAGE_PIN U2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[50]] - set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[51]] - set_property -dict {PACKAGE_PIN V6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[52]] - set_property -dict {PACKAGE_PIN V3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[53]] - set_property -dict {PACKAGE_PIN U1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[54]] - set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[55]] - set_property -dict {PACKAGE_PIN W6 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[6]] - set_property -dict {PACKAGE_PIN W5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[6]] - set_property -dict {PACKAGE_PIN U7 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[6]] - ### }}} - - ### Byte lane #7 - ### {{{ - set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[56]] - set_property -dict {PACKAGE_PIN AA3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[57]] - set_property -dict {PACKAGE_PIN W1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[58]] - set_property -dict {PACKAGE_PIN V2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[59]] - set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[60]] - set_property -dict {PACKAGE_PIN Y3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[61]] - set_property -dict {PACKAGE_PIN Y2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[62]] - set_property -dict {PACKAGE_PIN V1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[63]] - set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[7]] - set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[7]] - set_property -dict {PACKAGE_PIN Y1 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[7]] - ### }}}