From ec6488f68fcc6ecf4cb951dfd2a593ee0ee70c2b Mon Sep 17 00:00:00 2001
From: AngeloJacobo <jacobo.angeloECE@gmail.com>
Date: Wed, 5 Jul 2023 16:48:40 +0800
Subject: [PATCH] gtkw for testing time parameters

---
 formal_test_time.gtkw | 267 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 267 insertions(+)
 create mode 100644 formal_test_time.gtkw

diff --git a/formal_test_time.gtkw b/formal_test_time.gtkw
new file mode 100644
index 0000000..04008c2
--- /dev/null
+++ b/formal_test_time.gtkw
@@ -0,0 +1,267 @@
+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Wed Jul  5 00:16:39 2023
+[*]
+[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd"
+[dumpfile_mtime] "Wed Jul  5 00:14:12 2023"
+[dumpfile_size] 223124
+[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal_test_time.gtkw"
+[timestart] 74
+[size] 1848 1126
+[pos] -51 -51
+*-4.417290 175 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddr3_controller.
+[sst_width] 391
+[signals_width] 419
+[sst_expanded] 1
+[sst_vpaned_height] 743
+@420
+smt_step
+@28
+ddr3_controller.i_controller_clk
+ddr3_controller.i_rst_n
+ddr3_controller.reset_done
+@24
+ddr3_controller.state_calibrate[4:0]
+ddr3_controller.instruction_address[4:0]
+ddr3_controller.delay_counter[15:0]
+@28
+ddr3_controller.o_wb_stall_q
+ddr3_controller.o_wb_stall
+ddr3_controller.delay_counter_is_zero
+@29
+ddr3_controller.pause_counter
+@200
+-
+-
+@28
++{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
+@c00028
++{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
+@28
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+@1401200
+-group_end
+@c00028
++{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
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+@1401200
+-group_end
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++{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
+@200
+-
+@28
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+@200
+-
+@28
+ddr3_controller.stage1_pending
+ddr3_controller.stage2_pending
+ddr3_controller.stage2_update
+@200
+-
+@24
+ddr3_controller.f_timer[6:0]
+ddr3_controller.f_activate_time_stamp<0>[6:0]
+ddr3_controller.f_activate_time_stamp<1>[6:0]
+ddr3_controller.f_activate_time_stamp<2>[6:0]
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+ddr3_controller.f_activate_time_stamp<4>[6:0]
+ddr3_controller.f_activate_time_stamp<5>[6:0]
+ddr3_controller.f_activate_time_stamp<6>[6:0]
+ddr3_controller.f_activate_time_stamp<7>[6:0]
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+ddr3_controller.f_precharge_time_stamp<4>[6:0]
+ddr3_controller.f_precharge_time_stamp<5>[6:0]
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+ddr3_controller.f_write_time_stamp<3>[6:0]
+ddr3_controller.f_write_time_stamp<4>[6:0]
+ddr3_controller.f_write_time_stamp<5>[6:0]
+ddr3_controller.f_write_time_stamp<6>[6:0]
+ddr3_controller.f_write_time_stamp<7>[6:0]
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+ddr3_controller.o_wb_stall
+ddr3_controller.i_wb_cyc
+ddr3_controller.o_wb_ack
+ddr3_controller.o_wb_stall_d
+ddr3_controller.o_wb_stall_q
+ddr3_controller.delay_counter_is_zero
+@200
+-
+@28
+ddr3_controller.stage1_stall
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+@24
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+ddr3_controller.stage1_row[13:0]
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+-
+@28
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+ddr3_controller.stage2_pending
+ddr3_controller.stage2_update
+ddr3_controller.stage2_we
+@c00022
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+@28
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+@1401200
+-group_end
+@24
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+@22
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+ddr3_controller.stage2_row[13:0]
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+-
+@28
++{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
+@c00028
++{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
+@28
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+@1401200
+-group_end
+@c00028
++{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
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+@1401200
+-group_end
+@28
++{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
+@200
+-
+-
+[pattern_trace] 1
+[pattern_trace] 0