From e4bd0ac09c262fdc81fe73a17858b0cbffdb55aa Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Mon, 24 Jul 2023 19:46:23 +0800 Subject: [PATCH] delete| --- delete_later/rtl/Makefile | 133 - delete_later/rtl/afifo.v | 808 - delete_later/rtl/board.xdc | 506 - delete_later/rtl/builddate.v | 40 - delete_later/rtl/clkcounter.v | 118 - delete_later/rtl/cpu/busdelay.v | 611 - delete_later/rtl/cpu/cpuops.v | 395 - delete_later/rtl/cpu/dblfetch.v | 1031 - delete_later/rtl/cpu/dcache.v | 2725 --- delete_later/rtl/cpu/div.v | 611 - delete_later/rtl/cpu/icontrol.v | 382 - delete_later/rtl/cpu/idecode.v | 2181 -- delete_later/rtl/cpu/iscachable.v | 61 - delete_later/rtl/cpu/memops.v | 1018 - delete_later/rtl/cpu/mpyop.v | 428 - delete_later/rtl/cpu/pfcache.v | 1003 - delete_later/rtl/cpu/pipemem.v | 940 - delete_later/rtl/cpu/prefetch.v | 874 - delete_later/rtl/cpu/slowmpy.v | 271 - delete_later/rtl/cpu/wbarbiter.v | 380 - delete_later/rtl/cpu/wbdblpriarb.v | 531 - delete_later/rtl/cpu/wbpriarbiter.v | 296 - delete_later/rtl/cpu/wbwatchdog.v | 145 - delete_later/rtl/cpu/zipbones.v | 681 - delete_later/rtl/cpu/zipcore.v | 6118 ----- delete_later/rtl/cpu/zipcounter.v | 239 - delete_later/rtl/cpu/zipdma.v | 440 - delete_later/rtl/cpu/zipdma_ctrl.v | 343 - delete_later/rtl/cpu/zipdma_fsm.v | 221 - delete_later/rtl/cpu/zipdma_mm2s.v | 1137 - delete_later/rtl/cpu/zipdma_rxgears.v | 539 - delete_later/rtl/cpu/zipdma_s2mm.v | 975 - delete_later/rtl/cpu/zipdma_txgears.v | 757 - delete_later/rtl/cpu/zipjiffies.v | 334 - delete_later/rtl/cpu/zipsystem.v | 1847 -- delete_later/rtl/cpu/ziptimer.v | 357 - delete_later/rtl/cpu/zipwb.v | 676 - delete_later/rtl/ddr3/ddr3_controller.v | 3473 --- delete_later/rtl/ddr3/ddr3_phy.v | 926 - delete_later/rtl/genclk.v | 134 - delete_later/rtl/hdmi/axishdmi.v | 804 - delete_later/rtl/hdmi/axisvoverlay.v | 2070 -- delete_later/rtl/hdmi/cecbridge.v | 165 - delete_later/rtl/hdmi/hdmi2vga.v | 386 - delete_later/rtl/hdmi/hdmibitsync.v | 98 - delete_later/rtl/hdmi/hdmipixelsync.v | 165 - delete_later/rtl/hdmi/sync2stream.v | 364 - delete_later/rtl/hdmi/synccount.v | 119 - delete_later/rtl/hdmi/tfrstb.v | 299 - delete_later/rtl/hdmi/tfrvalue.v | 321 - delete_later/rtl/hdmi/tmdsdecode.v | 142 - delete_later/rtl/hdmi/tmdsencode.v | 246 - delete_later/rtl/hdmi/vid_empty.v | 196 - delete_later/rtl/hdmi/vid_mux.v | 411 - delete_later/rtl/hdmi/vid_wbframebuf.v | 802 - delete_later/rtl/hdmi/vidpipe.v | 955 - delete_later/rtl/hdmi/vidstream2pix.v | 1062 - delete_later/rtl/hdmi/xclksw.v | 190 - delete_later/rtl/hdmi/xhdmiin.v | 81 - delete_later/rtl/hdmi/xhdmiin_deserdes.v | 245 - delete_later/rtl/hdmi/xhdmiout.v | 183 - delete_later/rtl/hdmi/xpxclk.v | 141 - delete_later/rtl/ledbouncer.v | 120 - delete_later/rtl/main.v | 2455 -- delete_later/rtl/make.inc | 69 - delete_later/rtl/memdev.v | 280 - delete_later/rtl/micron.hex | 32 - delete_later/rtl/net/axinarbiter.v | 386 - delete_later/rtl/net/axinbroadcast.v | 463 - delete_later/rtl/net/axincdc.v | 117 - delete_later/rtl/net/axinwidth.v | 721 - delete_later/rtl/net/crc_axin.v | 503 - delete_later/rtl/net/dropshort.v | 335 - delete_later/rtl/net/mem2pkt.v | 1492 -- delete_later/rtl/net/netfifo.v | 661 - delete_later/rtl/net/netpath.v | 476 - delete_later/rtl/net/netskid.v | 201 - delete_later/rtl/net/p642pkt.v | 543 - delete_later/rtl/net/p64bscrambler.v | 130 - delete_later/rtl/net/pkt2mem.v | 1443 -- delete_later/rtl/net/pkt2p64b.v | 206 - delete_later/rtl/net/pktarbiter.v | 158 - delete_later/rtl/net/pktgate.v | 735 - delete_later/rtl/net/pktvfifo.v | 640 - delete_later/rtl/net/pktvfiford.v | 1248 - delete_later/rtl/net/pktvfifowr.v | 1151 - delete_later/rtl/net/routecore.v | 863 - delete_later/rtl/net/routetbl.v | 259 - delete_later/rtl/net/rxgetsrcmac.v | 282 - delete_later/rtl/net/txgetports.v | 206 - delete_later/rtl/net/xgtxphy.v | 839 - delete_later/rtl/netled.v | 164 - delete_later/rtl/obj_dir/Vmain.cpp | 208 - delete_later/rtl/obj_dir/Vmain.mk | 55 - .../rtl/obj_dir/Vmain__ConstPool_0.cpp | 910 - delete_later/rtl/obj_dir/Vmain__Dpi.cpp | 16 - delete_later/rtl/obj_dir/Vmain__Dpi.h | 22 - delete_later/rtl/obj_dir/Vmain__Syms.cpp | 41 - delete_later/rtl/obj_dir/Vmain__Syms.h | 46 - delete_later/rtl/obj_dir/Vmain__Trace__0.cpp | 4850 ---- .../rtl/obj_dir/Vmain__Trace__0__Slow.cpp | 11607 --------- delete_later/rtl/obj_dir/Vmain___024root.h | 3379 --- .../Vmain___024root__DepSet_h3334316c__0.cpp | 11041 --------- ...n___024root__DepSet_h3334316c__0__Slow.cpp | 10881 --------- .../Vmain___024root__DepSet_h3334316c__1.cpp | 9038 ------- ...n___024root__DepSet_h3334316c__1__Slow.cpp | 9554 -------- .../Vmain___024root__DepSet_h3334316c__2.cpp | 8737 ------- ...n___024root__DepSet_h3334316c__2__Slow.cpp | 5095 ---- .../Vmain___024root__DepSet_h3334316c__3.cpp | 8624 ------- .../Vmain___024root__DepSet_h3334316c__4.cpp | 19962 ---------------- .../Vmain___024root__DepSet_h3334316c__5.cpp | 4443 ---- .../Vmain___024root__DepSet_h8b02a3a0__0.cpp | 87 - ...n___024root__DepSet_h8b02a3a0__0__Slow.cpp | 27 - .../rtl/obj_dir/Vmain___024root__Slow.cpp | 27 - delete_later/rtl/obj_dir/Vmain_classes.mk | 65 - delete_later/rtl/qflexpress.v | 2314 -- delete_later/rtl/sdspi/llsdspi.v | 1243 - delete_later/rtl/sdspi/sdckgen.v | 257 - delete_later/rtl/sdspi/sdcmd.v | 896 - delete_later/rtl/sdspi/sdfrontend.v | 1008 - delete_later/rtl/sdspi/sdio.v | 331 - delete_later/rtl/sdspi/sdio_top.v | 197 - delete_later/rtl/sdspi/sdrxframe.v | 1258 - delete_later/rtl/sdspi/sdspi.v | 1031 - delete_later/rtl/sdspi/sdtxframe.v | 1489 -- delete_later/rtl/sdspi/sdwb.v | 1433 -- delete_later/rtl/sdspi/spicmd.v | 508 - delete_later/rtl/sdspi/spirxdata.v | 691 - delete_later/rtl/sdspi/spitxdata.v | 725 - delete_later/rtl/sdspi/xsdddr.v | 147 - delete_later/rtl/sdspi/xsdserdes8x.v | 143 - delete_later/rtl/sfifo.v | 484 - delete_later/rtl/smi/smi.v | 265 - delete_later/rtl/smi/smitest.v | 128 - delete_later/rtl/spio.v | 239 - delete_later/rtl/toplevel.v | 622 - delete_later/rtl/wb2axip/addrdecode.v | 431 - delete_later/rtl/wb2axip/axisbroadcast.v | 192 - delete_later/rtl/wb2axip/skidbuffer.v | 496 - delete_later/rtl/wb2axip/wbdown.v | 1150 - delete_later/rtl/wb2axip/wbupsz.v | 233 - delete_later/rtl/wb2axip/wbxbar.v | 1791 -- delete_later/rtl/wbfan.v | 405 - delete_later/rtl/wbgpio.v | 136 - delete_later/rtl/wbi2c/axisi2c.v | 1084 - delete_later/rtl/wbi2c/lli2cm.v | 352 - delete_later/rtl/wbi2c/wbi2ccpu.v | 1079 - delete_later/rtl/wbi2c/wbi2cdma.v | 597 - delete_later/rtl/wbi2c/wbi2cslave.v | 590 - delete_later/rtl/wbicapetwo.v | 801 - delete_later/rtl/wbmarbiter.v | 651 - delete_later/rtl/wbscope/wbscopc.v | 657 - delete_later/rtl/wbscope/wbscope.v | 590 - delete_later/rtl/wbuart/rxuart.v | 509 - delete_later/rtl/wbuart/rxuartlite.v | 744 - delete_later/rtl/wbuart/txuart.v | 1207 - delete_later/rtl/wbuart/txuartlite.v | 455 - delete_later/rtl/wbuart/ufifo.v | 472 - delete_later/rtl/wbuart/wbuart.v | 531 - delete_later/rtl/wbubus/wbconsole.v | 374 - delete_later/rtl/wbubus/wbubus.v | 329 - delete_later/rtl/wbubus/wbucompactlines.v | 352 - delete_later/rtl/wbubus/wbucompress.v | 780 - delete_later/rtl/wbubus/wbuconsole.v | 394 - delete_later/rtl/wbubus/wbudecompress.v | 401 - delete_later/rtl/wbubus/wbudeword.v | 413 - delete_later/rtl/wbubus/wbuexec.v | 1048 - delete_later/rtl/wbubus/wbufifo.v | 354 - delete_later/rtl/wbubus/wbuidleint.v | 197 - delete_later/rtl/wbubus/wbuinput.v | 137 - delete_later/rtl/wbubus/wbuoutput.v | 213 - delete_later/rtl/wbubus/wbureadcw.v | 335 - delete_later/rtl/wbubus/wbusixchar.v | 160 - delete_later/rtl/wbubus/wbutohex.v | 213 - delete_later/rtl/xgenclk.v | 137 - 175 files changed, 206422 deletions(-) delete mode 100644 delete_later/rtl/Makefile delete mode 100644 delete_later/rtl/afifo.v delete mode 100644 delete_later/rtl/board.xdc delete mode 100644 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-################################################################################ -## }}} -## Copyright (C) 2023, Gisselquist Technology, LLC -## {{{ -## This file is part of the ETH10G project. -## -## The ETH10G project contains free software and gateware, licensed under the -## Apache License, Version 2.0 (the "License"). You may not use this project, -## or this file, except in compliance with the License. You may obtain a copy -## of the License at -## }}} -## http://www.apache.org/licenses/LICENSE-2.0 -## {{{ -## Unless required by applicable law or agreed to in writing, files -## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -## License for the specific language governing permissions and limitations -## under the License. -## -################################################################################ -## -## }}} -all: test design.h -YYMMDD=`date +%Y%m%d` -CXX := g++ -FBDIR := . -VDIRFB:= $(FBDIR)/obj_dir -VOBJ := obj_dir -CPUDR := cpu -BASE := main - -.DELETE_ON_ERROR: -.PHONY: test -test: $(VOBJ)/V$(BASE)__ALL.a -SUBMAKE := $(MAKE) --no-print-directory -C $(VOBJ) -f -ifeq ($(VERILATOR_ROOT),) -VERILATOR := verilator -else -VERILATOR := $(VERILATOR_ROOT)/bin/verilator -endif -VFLAGS = -Wall -Wno-TIMESCALEMOD -Wno-SYNCASYNCNET --MMD -O3 --trace -Mdir $(VDIRFB) $(AUTOVDIRS) -y wb2axip -cc - --include make.inc - -.PHONY: main -main: $(VOBJ)/Vmain__ALL.a - -## Generic pattern(s) -## {{{ -$(VOBJ)/V$(BASE)__ALL.a: $(VOBJ)/V$(BASE).h -$(VOBJ)/V$(BASE).mk: $(VOBJ)/V$(BASE).cpp -$(VOBJ)/V$(BASE).cpp: $(VOBJ)/V$(BASE).h -builddate.v $(VOBJ)/V$(BASE).h: $(VFLIST) - perl ../mkdatev.pl > builddate.v - cp builddate.v ../$(YYMMDD)-build.v - $(VERILATOR) $(VFLAGS) $(BASE).v -## }}} - -$(VOBJ)/V%__ALL.a: $(VOBJ)/V%.mk - +$(SUBMAKE) V$*.mk - -$(VOBJ)/V%.h: $(FBDIR)/%.v - $(VERILATOR) $(VFLAGS) $*.v - -$(VOBJ)/V%.cpp: $(VOBJ)/V%.h -$(VOBJ)/V%.mk: $(VOBJ)/V%.h -$(VOBJ)/V%.h: $(FBDIR)/%.v - -## .PHONY: design.h isn't phony -## {{{ -design.h: main.v builddate.v - @echo "Building design.h" - @echo "// " > $@ - @echo "// Do not edit this file, it is automatically generated!" >> $@ - @echo "// To generate this file, \"make design.h\" in the rtl directory." >> $@ - @echo "// " >> $@ - @echo "#ifndef DESIGN_H" >> $@ - @echo "#define DESIGN_H" >> $@ - @echo >> $@ - @grep "^\`" main.v | grep -v default_nettype \ - | grep -v include \ - | grep -v timescale \ - | sed -e '{ s/^`/#/ }' \ - | sed -e ' s/^#elsif/#elif/' \ - | sed -e ' s/main.v/design.h/' >> $@ - @echo >> $@ - @grep "^\`" builddate.v | grep -v default_nettype \ - | grep -v include \ - | grep -v timescale \ - | sed -e '{ s/^`/#/ }' \ - | sed -e ' s/^#elsif/#elif/' \ - | sed -e " s/32.h/0x/" \ - | sed -e ' s/^\/\/.*$$//' >> $@ - @echo >> $@ - @echo "#endif // DESIGN_H" >> $@ -## }}} - -.PHONY: archive -## {{{ -archive: - tar --transform s,^,$(YYMMDD)-rtl/, -chjf $(YYMMDD)-rtl.tjz Makefile *.v cpu/*.v -## }}} - -.PHONY: clean -## {{{ -clean: - rm -rf $(VDIRFB)/*.mk - rm -rf $(VDIRFB)/*.cpp - rm -rf $(VDIRFB)/*.h - rm -rf $(VDIRFB)/ - rm -rf $(VOBJ)/ design.h -## }}} - -# -# Note Verilator's dependency created information, and include it here if we -# can -DEPS := $(wildcard $(VOBJ)/*.d) -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(DEPS),) -include $(DEPS) -endif -endif diff --git a/delete_later/rtl/afifo.v b/delete_later/rtl/afifo.v deleted file mode 100644 index 4233945..0000000 --- a/delete_later/rtl/afifo.v +++ /dev/null @@ -1,808 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: afifo.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A basic asynchronous FIFO. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module afifo #( - // {{{ - // LGFIFO is the log based-two of the number of entries - // in the FIFO, log_2(fifo size) - parameter LGFIFO = 3, - // - // WIDTH is the number of data bits in each entry - parameter WIDTH = 16, - // - // NFF is the number of flip flops used to cross clock domains. - // 2 is a minimum. Some applications appreciate the better - parameter NFF = 2, - // - // This core can either write on the positive edge of the clock - // or the negative edge. Set WRITE_ON_POSEDGE (the default) - // to write on the positive edge of the clock. - parameter [0:0] WRITE_ON_POSEDGE = 1'b1, - // - // Many logic elements can read from memory asynchronously. - // This burdens any following logic. By setting - // OPT_REGISTER_READS, we force all reads to be synchronous and - // not burdened by any logic. You can spare a clock of latency - // by clearing this register. - parameter [0:0] OPT_REGISTER_READS = 1'b1 -`ifdef FORMAL - // F_OPT_DATA_STB - // {{{ - // In the formal proof, F_OPT_DATA_STB includes a series of - // assumptions associated with a data strobe I/O pin--things - // like a discontinuous clock--just to make sure the core still - // works in those circumstances - , parameter [0:0] F_OPT_DATA_STB = 1'b1 - // }}} -`endif - // }}} - ) ( - // {{{ - // - // The (incoming) write data interface - input wire i_wclk, - // Verilator lint_off SYNCASYNCNET - input wire i_wr_reset_n, - // Verilator lint_on SYNCASYNCNET - input wire i_wr, - input wire [WIDTH-1:0] i_wr_data, - output reg o_wr_full, - // - // The (incoming) write data interface - input wire i_rclk, - // Verilator lint_off SYNCASYNCNET - input wire i_rd_reset_n, - // Verilator lint_on SYNCASYNCNET - input wire i_rd, - output reg [WIDTH-1:0] o_rd_data, - output reg o_rd_empty -`ifdef FORMAL - , output reg [LGFIFO:0] f_fill -`endif - // }}} - ); - - // Register/net declarations - // {{{ - // MSB = most significant bit of the FIFO address vector. It's - // just short-hand for LGFIFO, and won't work any other way. - localparam MSB = LGFIFO; - // - reg [WIDTH-1:0] mem [(1<> 1); - end - // }}} - - // Write to memory - // {{{ - always @(posedge wclk) - if (i_wr && !o_wr_full) - mem[wr_addr[LGFIFO-1:0]] <= i_wr_data; - // }}} - - // rd_addr, rgray - // {{{ - assign next_rd_addr = rd_addr + 1; - always @(posedge i_rclk or negedge i_rd_reset_n) - if (!i_rd_reset_n) - begin - rd_addr <= 0; - rgray <= 0; - end else if (lcl_read && !lcl_rd_empty) - begin - rd_addr <= next_rd_addr; - rgray <= next_rd_addr ^ (next_rd_addr >> 1); - end - // }}} - - // Read from memory - // {{{ - always @(*) - lcl_rd_data = mem[rd_addr[LGFIFO-1:0]]; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cross clock domains - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // read pointer -> wr_rgray - // {{{ - always @(posedge wclk or negedge i_wr_reset_n) - if (!i_wr_reset_n) - { wr_rgray, rgray_cross } <= 0; - else - { wr_rgray, rgray_cross } <= { rgray_cross, rgray }; - // }}} - - // write pointer -> rd_wgray - // {{{ - always @(posedge i_rclk or negedge i_rd_reset_n) - if (!i_rd_reset_n) - { rd_wgray, wgray_cross } <= 0; - else - { rd_wgray, wgray_cross } <= { wgray_cross, wgray }; - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Flag generation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - o_wr_full = (wr_rgray == { ~wgray[MSB:MSB-1], wgray[MSB-2:0] }); - - always @(*) - lcl_rd_empty = (rd_wgray == rgray); - - // o_rd_empty, o_rd_data - // {{{ - generate if (OPT_REGISTER_READS) - begin : GEN_REGISTERED_READ - // {{{ - always @(*) - lcl_read = (o_rd_empty || i_rd); - - always @(posedge i_rclk or negedge i_rd_reset_n) - if (!i_rd_reset_n) - o_rd_empty <= 1'b1; - else if (lcl_read) - o_rd_empty <= lcl_rd_empty; - - always @(posedge i_rclk) - if (lcl_read) - o_rd_data <= lcl_rd_data; - // }}} - end else begin : GEN_COMBINATORIAL_FLAGS - // {{{ - always @(*) - lcl_read = i_rd; - - always @(*) - o_rd_empty = lcl_rd_empty; - - always @(*) - o_rd_data = lcl_rd_data; - // }}} - end endgenerate - // }}} - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Start out with some register/net/macro declarations, f_past_valid,etc - // {{{ -`ifdef AFIFO -`define ASSERT assert -`define ASSUME assume -`else -`define ASSERT assert -`define ASSUME assert -`endif - - (* gclk *) reg gbl_clk; - reg f_past_valid_gbl, f_past_valid_rd, - f_rd_in_reset, f_wr_in_reset; - reg [WIDTH-1:0] past_rd_data, past_wr_data; - reg past_wr_reset_n, past_rd_reset_n, - past_rd_empty, past_wclk, past_rclk, past_rd; - reg [(LGFIFO+1)*(NFF-1)-1:0] f_wcross, f_rcross; - reg [LGFIFO:0] f_rd_waddr, f_wr_raddr; - reg [LGFIFO:0] f_rdcross_fill [NFF-1:0]; - reg [LGFIFO:0] f_wrcross_fill [NFF-1:0]; - - - initial f_past_valid_gbl = 1'b0; - always @(posedge gbl_clk) - f_past_valid_gbl <= 1'b1; - - initial f_past_valid_rd = 1'b0; - always @(posedge i_rclk) - f_past_valid_rd <= 1'b1; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Reset checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial f_wr_in_reset = 1'b1; - always @(posedge wclk or negedge i_wr_reset_n) - if (!i_wr_reset_n) - f_wr_in_reset <= 1'b1; - else - f_wr_in_reset <= 1'b0; - - initial f_rd_in_reset = 1'b1; - always @(posedge i_rclk or negedge i_rd_reset_n) - if (!i_rd_reset_n) - f_rd_in_reset <= 1'b1; - else - f_rd_in_reset <= 1'b0; - - // - // Resets are ... - // 1. Asserted always initially, and ... - always @(*) - if (!f_past_valid_gbl) - begin - `ASSUME(!i_wr_reset_n); - `ASSUME(!i_rd_reset_n); - end - - // 2. They only ever become active together - always @(*) - if (past_wr_reset_n && !i_wr_reset_n) - `ASSUME(!i_rd_reset_n); - - always @(*) - if (past_rd_reset_n && !i_rd_reset_n) - `ASSUME(!i_wr_reset_n); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Synchronous signal assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge gbl_clk) - begin - past_wr_reset_n <= i_wr_reset_n; - past_rd_reset_n <= i_rd_reset_n; - - past_wclk <= wclk; - past_rclk <= i_rclk; - - past_rd <= i_rd; - past_rd_data <= lcl_rd_data; - past_wr_data <= i_wr_data; - - past_rd_empty<= lcl_rd_empty; - end - - // - // Read side may be assumed to be synchronous - always @(*) - if (f_past_valid_gbl && i_rd_reset_n && (past_rclk || !i_rclk)) - // i.e. if (!$rose(i_rclk)) - `ASSUME(i_rd == past_rd); - - always @(*) - if (f_past_valid_rd && !f_rd_in_reset && !lcl_rd_empty - &&(past_rclk || !i_rclk)) - begin - `ASSERT(lcl_rd_data == past_rd_data); - `ASSERT(lcl_rd_empty == past_rd_empty); - end - - - generate if (F_OPT_DATA_STB) - begin - - always @(posedge gbl_clk) - `ASSUME(!o_wr_full); - - always @(posedge gbl_clk) - if (!i_wr_reset_n) - `ASSUME(!i_wclk); - - always @(posedge gbl_clk) - `ASSUME(i_wr == i_wr_reset_n); - - always @(posedge gbl_clk) - if ($changed(i_wr_reset_n)) - `ASSUME($stable(wclk)); - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Fill checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - f_fill = wr_addr - rd_addr; - - always @(*) - if (!f_wr_in_reset) - `ASSERT(f_fill <= { 1'b1, {(MSB){1'b0}} }); - - always @(*) - if (wr_addr == rd_addr) - `ASSERT(lcl_rd_empty); - - always @(*) - if ((!f_wr_in_reset && !f_rd_in_reset) - && wr_addr == { ~rd_addr[MSB], rd_addr[MSB-1:0] }) - `ASSERT(o_wr_full); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Induction checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // f_wr_in_reset -- write logic is in its reset state - // {{{ - always @(*) - if (f_wr_in_reset) - begin - `ASSERT(wr_addr == 0); - `ASSERT(wgray_cross == 0); - - `ASSERT(rd_addr == 0); - `ASSERT(rgray_cross == 0); - `ASSERT(rd_wgray == 0); - - `ASSERT(lcl_rd_empty); - `ASSERT(!o_wr_full); - end - // }}} - - // f_rd_in_reset -- read logic is in its reset state - // {{{ - always @(*) - if (f_rd_in_reset) - begin - `ASSERT(rd_addr == 0); - `ASSERT(rgray_cross == 0); - `ASSERT(rd_wgray == 0); - - `ASSERT(lcl_rd_empty); - end - // }}} - - // f_wr_raddr -- a read address to match the gray values - // {{{ - always @(posedge wclk or negedge i_wr_reset_n) - if (!i_wr_reset_n) - { f_wr_raddr, f_rcross } <= 0; - else - { f_wr_raddr, f_rcross } <= { f_rcross, rd_addr }; - // }}} - - // f_rd_waddr -- a write address to match the gray values - // {{{ - always @(posedge i_rclk or negedge i_rd_reset_n) - if (!i_rd_reset_n) - { f_rd_waddr, f_wcross } <= 0; - else - { f_rd_waddr, f_wcross } <= { f_wcross, wr_addr }; - // }}} - - integer k; - - // wgray check - // {{{ - always @(*) - `ASSERT((wr_addr ^ (wr_addr >> 1)) == wgray); - // }}} - - // wgray_cross check - // {{{ - always @(*) - for(k=0; k>1)) - == wgray_cross[k*(LGFIFO+1) +: LGFIFO+1]); - // }}} - - // rgray check - // {{{ - always @(*) - `ASSERT((rd_addr ^ (rd_addr >> 1)) == rgray); - // }}} - - // rgray_cross check - // {{{ - always @(*) - for(k=0; k>1)) - == rgray_cross[k*(LGFIFO+1) +: LGFIFO+1]); - // }}} - - // wr_rgray - // {{{ - always @(*) - `ASSERT((f_wr_raddr ^ (f_wr_raddr >> 1)) == wr_rgray); - // }}} - - // rd_wgray - // {{{ - always @(*) - `ASSERT((f_rd_waddr ^ (f_rd_waddr >> 1)) == rd_wgray); - // }}} - - // f_rdcross_fill - // {{{ - always @(*) - for(k=0; k= f_wrcross_fill[k-1]); - always @(*) - `ASSERT(f_wrcross_fill[0] >= f_fill); - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Clock generation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Here's the challenge: if we use $past with any of our clocks, such - // as to determine stability or any such, the proof takes forever, and - // we need to guarantee a minimum number of transitions within the - // depth of the proof. If, on the other hand, we build our own $past - // primitives--we can then finish much faster and be successful on - // any depth of proof. - - // pre_xclk is what the clock will become on the next global clock edge. - // By using it here, we can check things @(*) instead of - // @(posedge gbl_clk). Further, we can check $rose(pre_xclk) (or $fell) - // and essentially check things @(*) but while using @(global_clk). - // In other words, we can transition on @(posedge gbl_clk), but stay - // in sync with the data--rather than being behind by a clock. - // now_xclk is what the clock is currently. - // - (* anyseq *) reg pre_wclk, pre_rclk; - reg now_wclk, now_rclk; - always @(posedge gbl_clk) - begin - now_wclk <= pre_wclk; - now_rclk <= pre_rclk; - end - - always @(*) - begin - assume(i_wclk == now_wclk); - assume(i_rclk == now_rclk); - end - - always @(posedge gbl_clk) - assume(i_rclk == $past(pre_rclk)); - - // Assume both clocks start idle - // {{{ - always @(*) - if (!f_past_valid_gbl) - begin - assume(!pre_wclk && !wclk); - assume(!pre_rclk && !i_rclk); - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Formal contract check --- the twin write test - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Tracking register declarations - // {{{ - reg [WIDTH-1:0] f_first, f_next; - (* anyconst *) reg [LGFIFO:0] f_addr; - reg [LGFIFO:0] f_next_addr; - reg f_first_in_fifo, f_next_in_fifo; - reg [LGFIFO:0] f_to_first, f_to_next; - reg [1:0] f_state; - - always @(*) - f_next_addr = f_addr + 1; - // }}} - - // distance_to*, *_in_fifo - // {{{ - always @(*) - begin - f_to_first = f_addr - rd_addr; - - f_first_in_fifo = 1'b1; - if ((f_to_first >= f_fill)||(f_fill == 0)) - f_first_in_fifo = 1'b0; - - if (mem[f_addr] != f_first) - f_first_in_fifo = 1'b0; - - // - // Check the second item - // - - f_to_next = f_next_addr - rd_addr; - f_next_in_fifo = 1'b1; - if ((f_to_next >= f_fill)||(f_fill == 0)) - f_next_in_fifo = 1'b0; - - if (mem[f_next_addr] != f_next) - f_next_in_fifo = 1'b0; - end - // }}} - - // f_state -- generate our state variable - // {{{ - initial f_state = 0; - always @(posedge gbl_clk) - if (!i_wr_reset_n) - f_state <= 0; - else case(f_state) - 2'b00: if (($rose(pre_wclk))&& i_wr && !o_wr_full &&(wr_addr == f_addr)) - begin - f_state <= 2'b01; - f_first <= i_wr_data; - end - 2'b01: if ($rose(pre_rclk)&& lcl_read && rd_addr == f_addr) - f_state <= 2'b00; - else if ($rose(pre_wclk) && i_wr && !o_wr_full ) - begin - f_state <= 2'b10; - f_next <= i_wr_data; - end - 2'b10: if ($rose(pre_rclk) && lcl_read && !lcl_rd_empty && rd_addr == f_addr) - f_state <= 2'b11; - 2'b11: if ($rose(pre_rclk) && lcl_read && !lcl_rd_empty && rd_addr == f_next_addr) - f_state <= 2'b00; - endcase - // }}} - - // f_state invariants - // {{{ - always @(*) - if (i_wr_reset_n) case(f_state) - 2'b00: begin end - 2'b01: begin - `ASSERT(f_first_in_fifo); - `ASSERT(wr_addr == f_next_addr); - `ASSERT(f_fill >= 1); - end - 2'b10: begin - `ASSERT(f_first_in_fifo); - `ASSERT(f_next_in_fifo); - if (!lcl_rd_empty && (rd_addr == f_addr)) - `ASSERT(lcl_rd_data == f_first); - `ASSERT(f_fill >= 2); - end - 2'b11: begin - `ASSERT(rd_addr == f_next_addr); - `ASSERT(f_next_in_fifo); - `ASSERT(f_fill >= 1); - if (!lcl_rd_empty) - `ASSERT(lcl_rd_data == f_next); - end - endcase - // }}} - - generate if (OPT_REGISTER_READS) - begin - reg past_o_rd_empty; - - always @(posedge gbl_clk) - past_o_rd_empty <= o_rd_empty; - - always @(posedge gbl_clk) - if (f_past_valid_gbl && i_rd_reset_n) - begin - if ($past(!o_rd_empty && !i_rd && i_rd_reset_n)) - `ASSERT($stable(o_rd_data)); - end - - always @(posedge gbl_clk) - if (!f_rd_in_reset && i_rd_reset_n && i_rclk && !past_rclk) - begin - if (past_o_rd_empty) - `ASSERT(o_rd_data == past_rd_data); - if (past_rd) - `ASSERT(o_rd_data == past_rd_data); - end - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Prove that we can read and write the FIFO - // {{{ - always @(*) - if (i_wr_reset_n && i_rd_reset_n) - begin - cover(o_rd_empty); - cover(!o_rd_empty); - cover(f_state == 2'b01); - cover(f_state == 2'b10); - cover(f_state == 2'b11); - cover(&f_fill[MSB-1:0]); - - cover(i_rd); - cover(i_rd && !o_rd_empty); - end - // }}} - -`ifdef AFIFO - generate if (!F_OPT_DATA_STB) - begin : COVER_FULL - // {{{ - reg cvr_full; - - initial cvr_full = 1'b0; - always @(posedge gbl_clk) - if (!i_wr_reset_n) - cvr_full <= 1'b0; - else if (o_wr_full) - cvr_full <= 1'b1; - - - always @(*) - if (f_past_valid_gbl && i_wr_reset_n) - begin - cover(o_wr_full); - cover(o_rd_empty && cvr_full); - cover(o_rd_empty && f_fill == 0 && cvr_full); - end - // }}} - end else begin : COVER_NEARLY_FULL - // {{{ - reg cvr_nearly_full; - - initial cvr_nearly_full = 1'b0; - always @(posedge gbl_clk) - if (!i_wr_reset_n) - cvr_nearly_full <= 1'b0; - else if (f_fill == { 1'b0, {(LGFIFO){1'b1} }}) - cvr_nearly_full <= 1'b1; - - - always @(*) - if (f_past_valid_gbl && i_wr_reset_n) - begin - cover(f_fill == { 1'b0, {(LGFIFO){1'b1} }}); - cover(cvr_nearly_full && i_wr_reset_n); - cover(o_rd_empty && cvr_nearly_full); - cover(o_rd_empty && f_fill == 0 && cvr_nearly_full); - end - // }}} - end endgenerate -`endif - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/board.xdc b/delete_later/rtl/board.xdc deleted file mode 100644 index 838952b..0000000 --- a/delete_later/rtl/board.xdc +++ /dev/null @@ -1,506 +0,0 @@ -## Define our clocks -## {{{ -set_property -dict { PACKAGE_PIN AC9 IOSTANDARD DIFF_SSTL15 } [get_ports i_clk_200mhz_p] -set_property -dict { PACKAGE_PIN AD9 IOSTANDARD DIFF_SSTL15 } [get_ports i_clk_200mhz_n] -create_clock -period 5.0 -name SYSCLK -waveform { 0.0 2.50 } -add [get_ports i_clk_200mhz_p] - -#set_property -dict { PACKAGE_PIN F6 } [get_ports i_clk_150mhz_p] -#set_property -dict { PACKAGE_PIN F5 } [get_ports i_clk_150mhz_n] -#create_clock -period 6.6666 -name SATAREF -waveform { 0.0 3.3333 } -add [get_ports i_clk_150mhz_p] - -#set_property -dict { PACKAGE_PIN H6 } [get_ports i_clk_156mhz_p] -#set_property -dict { PACKAGE_PIN H5 } [get_ports i_clk_156mhz_n] -#create_clock -period 6.4 -name NETREF -waveform { 0.0 3.4 } -add [get_ports i_clk_156mhz_p] - -#set_property -dict { PACKAGE_PIN K6 } [get_ports i_clk_si_p] -#set_property -dict { PACKAGE_PIN K5 } [get_ports i_clk_si_n] -#create_clock -period 5.2 -name SIREF -waveform { 0.0 2.6 } -add [get_ports i_clk_si_p] - -#set_property -dict { PACKAGE_PIN B26 } [get_ports i_emcclk] -#create_clock -period 15.0 -name EMCCLK -waveform { 0.0 7.5 } -add [get_ports i_emcclk] - -#set_property -dict { PACKAGE_PIN B26 IOSTANDARD LVCMOS18 } [get_ports i_clk_66mhz_p] -#create_clock -period 15.0 -name INITREF -waveform { 0.0 7.5 } -add [get_ports i_clk_66mhz_p] - -set_property -dict { PACKAGE_PIN R21 IOSTANDARD TMDS_33 } [get_ports o_siref_clk_p] -set_property -dict { PACKAGE_PIN P21 IOSTANDARD TMDS_33 } [get_ports o_siref_clk_n] - -#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports io_siref_clk_p] -#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports io_siref_clk_n] - -## }}} - -## UART -## {{{ -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports o_wbu_uart_tx] -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports i_wbu_uart_rx] -#set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports i_wbu_uart_rts_n] -set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports o_wbu_uart_cts_n] -## }}} - -## Switches -## {{{ -set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports i_sw[0]] -set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports i_sw[1]] -set_property -dict {PACKAGE_PIN D25 IOSTANDARD LVCMOS18} [get_ports i_sw[2]] -set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports i_sw[3]] -set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports i_sw[4]] -set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports i_sw[5]] -set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports i_sw[6]] -set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS18} [get_ports i_sw[7]] -## #set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports i_sw[8]] -## }}} - -## Buttons -## {{{ -set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports i_nbtn_u] -set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports i_nbtn_l] -set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports i_nbtn_c] -set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports i_nbtn_r] -set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports i_nbtn_d] -## }}} - -## LEDs -## {{{ -set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS18} [get_ports o_led[0]] -set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18} [get_ports o_led[1]] -set_property -dict {PACKAGE_PIN G26 IOSTANDARD LVCMOS18} [get_ports o_led[2]] -set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports o_led[3]] -set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports o_led[4]] -set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS18} [get_ports o_led[5]] -set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports o_led[6]] -set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports o_led[7]] -## }}} - -## FAN control -## {{{ -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports i_fan_tach] -set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports o_fan_pwm] -set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports o_fan_sys] -## }}} - -## External resets -## {{{ -set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports i_pi_reset_n] -set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports i_soft_reset] -## }}} - -## I2C -## {{{ -set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS18} [get_ports o_i2c_mxrst_n] -set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS18} [get_ports io_i2c_scl] -set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS18} [get_ports io_i2c_sda] -set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS18} [get_ports io_temp_scl] -set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS18} [get_ports io_temp_sda] -set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS18} [get_ports i_si5324_int] -set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS18} [get_ports o_si5324_rst] -## }}} - -## ETH10G -## {{{ -## LOS -#set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports i_gnet_los[0]] -#set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports i_gnet_los[1]] -#set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports i_gnet_los[2]] -#set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports i_gnet_los[3]] - -## TX Disable -#set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports o_gnettx_disable[0]] -#set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports o_gnettx_disable[1]] -#set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports o_gnettx_disable[2]] -#set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports o_gnettx_disable[3]] - -## LinkUp LEDs -#set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports o_gnet_linkup[0]] -#set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports o_gnet_linkup[1]] -#set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports o_gnet_linkup[2]] -#set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports o_gnet_linkup[3]] - -## Activity LEDs -#set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports o_gnet_activity[0]] -#set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports o_gnet_activity[1]] -#set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports o_gnet_activity[2]] -#set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports o_gnet_activity[3]] - -## Network transmit/outputs -#set_property -dict {PACKAGE_PIN P2} [get_ports o_gnet_p[0]] -#set_property -dict {PACKAGE_PIN P1} [get_ports o_gnet_n[0]] -#set_property -dict {PACKAGE_PIN M2} [get_ports o_gnet_p[1]] -#set_property -dict {PACKAGE_PIN M1} [get_ports o_gnet_n[1]] -#set_property -dict {PACKAGE_PIN K2} [get_ports o_gnet_p[2]] -#set_property -dict {PACKAGE_PIN K1} [get_ports o_gnet_n[2]] -#set_property -dict {PACKAGE_PIN H2} [get_ports o_gnet_p[3]] -#set_property -dict {PACKAGE_PIN H1} [get_ports o_gnet_n[3]] - -## Network receive/input -#set_property -dict {PACKAGE_PIN R4} [get_ports i_gnet_p[0]] -#set_property -dict {PACKAGE_PIN R3} [get_ports i_gnet_n[0]] -#set_property -dict {PACKAGE_PIN N4} [get_ports i_gnet_p[1]] -#set_property -dict {PACKAGE_PIN N3} [get_ports i_gnet_n[1]] -#set_property -dict {PACKAGE_PIN L4} [get_ports i_gnet_p[2]] -#set_property -dict {PACKAGE_PIN L3} [get_ports i_gnet_n[2]] -#set_property -dict {PACKAGE_PIN J4} [get_ports i_gnet_p[3]] -#set_property -dict {PACKAGE_PIN J3} [get_ports i_gnet_n[3]] - -## }}} - -## SMI -## {{{ -#set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports i_smi_oen] -#set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS18} [get_ports i_smi_wen] - -#set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[0]] -#set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[1]] -#set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[2]] -#set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[3]] -#set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[4]] -#set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[5]] - -#set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[0]] -#set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[1]] -#set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[2]] -#set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[3]] -#set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[4]] -#set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[5]] -#set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[6]] -#set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[7]] -#set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[8]] -#set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[9]] -#set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[10]] -#set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[11]] -#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[12]] -#set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[13]] -#set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[14]] -#set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[15]] -#set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[16]] -#set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[17]] -## }}} - -## uSD -## {{{ -set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports i_sdcard_cd_n] -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports o_sdcard_clk] - -set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS18} [get_ports io_sdcard_cmd] -set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports io_sdcard_dat[0]] -set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports io_sdcard_dat[1]] -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports io_sdcard_dat[2]] -set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS18} [get_ports io_sdcard_dat[3]] -## }}} - -## Flash -## {{{ -#set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports o_flash_sel] -## The flash clock pin is CCLK_0 -#set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports o_flash_cs_n] - -#set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports io_flash_dat[0]] -#set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports io_flash_dat[1]] -#set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports io_flash_dat[2]] -#set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports io_flash_dat[3]] -## }}} - -## eMMC -## {{{ -#set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports o_emmc_clk] -set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports io_emmc_cmd] - -set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[0]] -set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[1]] -set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[2]] -set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[3]] -set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[4]] -set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[5]] -set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[6]] -set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[7]] -set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports i_emmc_ds] -## }}} - -## SATA -## {{{ -#set_property -dict {PACKAGE_PIN B2} [get_ports o_sata_p] -#set_property -dict {PACKAGE_PIN B1} [get_ports o_sata_n] -#set_property -dict {PACKAGE_PIN C4} [get_ports i_sata_p] -#set_property -dict {PACKAGE_PIN C3} [get_ports i_sata_n] -## }}} - -## DDR3 -## {{{ -set_property -dict {PACKAGE_PIN V11 IOSTANDARD SSTL15} [get_ports o_ddr3_reset_n] -set_property -dict {PACKAGE_PIN AB11 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_p] -set_property -dict {PACKAGE_PIN AC11 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_n] -#set_property -dict {PACKAGE_PIN AA9 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_p_1[1]] -#set_property -dict {PACKAGE_PIN AB9 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_n_1[1]] -set_property -dict {PACKAGE_PIN Y10 IOSTANDARD SSTL15} [get_ports o_ddr3_cke[0]] -set_property -dict {PACKAGE_PIN W9 IOSTANDARD SSTL15} [get_ports o_ddr3_cke[1]] - -set_property -dict {PACKAGE_PIN AA10 IOSTANDARD SSTL15} [get_ports o_ddr3_ras_n] -set_property -dict {PACKAGE_PIN AA7 IOSTANDARD SSTL15} [get_ports o_ddr3_cas_n] -set_property -dict {PACKAGE_PIN Y7 IOSTANDARD SSTL15} [get_ports o_ddr3_we_n] -set_property -dict {PACKAGE_PIN Y8 IOSTANDARD SSTL15} [get_ports o_ddr3_s_n[0]] -set_property -dict {PACKAGE_PIN V7 IOSTANDARD SSTL15} [get_ports o_ddr3_s_n[1]] -set_property -dict {PACKAGE_PIN AA8 IOSTANDARD SSTL15} [get_ports o_ddr3_odt[0]] -set_property -dict {PACKAGE_PIN V9 IOSTANDARD SSTL15} [get_ports o_ddr3_odt[1]] -#set_property -dict {PACKAGE_PIN W10 IOSTANDARD SSTL15} [get_ports i_ddr3_event] - -### Address lines -### {{{ -set_property -dict {PACKAGE_PIN AC7 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[0]] -set_property -dict {PACKAGE_PIN V8 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[1]] -set_property -dict {PACKAGE_PIN AC13 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[2]] - -set_property -dict {PACKAGE_PIN AF7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[0]] -set_property -dict {PACKAGE_PIN AD8 IOSTANDARD SSTL15} [get_ports o_ddr3_a[1]] -set_property -dict {PACKAGE_PIN AB10 IOSTANDARD SSTL15} [get_ports o_ddr3_a[2]] -set_property -dict {PACKAGE_PIN AC8 IOSTANDARD SSTL15} [get_ports o_ddr3_a[3]] -set_property -dict {PACKAGE_PIN W11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[4]] -set_property -dict {PACKAGE_PIN AA12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[5]] -set_property -dict {PACKAGE_PIN AC12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[6]] -set_property -dict {PACKAGE_PIN AD13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[7]] - -set_property -dict {PACKAGE_PIN AB12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[8]] -set_property -dict {PACKAGE_PIN AD11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[9]] -set_property -dict {PACKAGE_PIN AE7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[10]] -set_property -dict {PACKAGE_PIN Y11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[11]] -set_property -dict {PACKAGE_PIN AA13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[12]] -set_property -dict {PACKAGE_PIN AB7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[13]] -set_property -dict {PACKAGE_PIN Y13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[14]] -set_property -dict {PACKAGE_PIN Y12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[15]] -### }}} - -### Byte lane #0 -### {{{ -set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[0]] -set_property -dict {PACKAGE_PIN AC18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[1]] -set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[2]] -set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[3]] -set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[4]] -set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[5]] -set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[6]] -set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[7]] -set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[0]] -set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[0]] -set_property -dict {PACKAGE_PIN AC19 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[0]] -### }}} - -### Byte lane #1 -### {{{ -set_property -dict {PACKAGE_PIN V16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[8]] -set_property -dict {PACKAGE_PIN V18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[9]] -set_property -dict {PACKAGE_PIN AB20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[10]] -set_property -dict {PACKAGE_PIN AB19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[11]] -set_property -dict {PACKAGE_PIN W15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[12]] -set_property -dict {PACKAGE_PIN V19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[13]] -set_property -dict {PACKAGE_PIN W16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[14]] -set_property -dict {PACKAGE_PIN Y17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[15]] -set_property -dict {PACKAGE_PIN W18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[1]] -set_property -dict {PACKAGE_PIN W19 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[1]] -set_property -dict {PACKAGE_PIN V17 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[1]] -### }}} - -### Byte lane #2 -### {{{ -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[16]] -set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[17]] -set_property -dict {PACKAGE_PIN AE15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[18]] -set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[19]] -set_property -dict {PACKAGE_PIN AF20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[20]] -set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[21]] -set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[22]] -set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[23]] -set_property -dict {PACKAGE_PIN AE18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[2]] -set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[2]] -set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[2]] -### }}} - -### Byte lane #3 -### {{{ -set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[24]] -set_property -dict {PACKAGE_PIN AB16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[25]] -set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[26]] -set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[27]] -set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[28]] -set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[29]] -set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[30]] -set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[31]] -set_property -dict {PACKAGE_PIN Y15 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[3]] -set_property -dict {PACKAGE_PIN Y16 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[3]] -set_property -dict {PACKAGE_PIN AA14 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[3]] -### }}} - -### Byte lane #4 -### {{{ -set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[32]] -set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[33]] -set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[34]] -set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[35]] -set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[36]] -set_property -dict {PACKAGE_PIN Y6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[37]] -set_property -dict {PACKAGE_PIN Y5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[38]] -set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[39]] -set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[4]] -set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[4]] -set_property -dict {PACKAGE_PIN AC4 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[4]] -### }}} - -### Byte lane #5 -### {{{ -set_property -dict {PACKAGE_PIN AF3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[40]] -set_property -dict {PACKAGE_PIN AE3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[41]] -set_property -dict {PACKAGE_PIN AE2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[42]] -set_property -dict {PACKAGE_PIN AE1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[43]] -set_property -dict {PACKAGE_PIN AE6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[44]] -set_property -dict {PACKAGE_PIN AE5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[45]] -set_property -dict {PACKAGE_PIN AD4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[46]] -set_property -dict {PACKAGE_PIN AD1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[47]] -set_property -dict {PACKAGE_PIN AF5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[5]] -set_property -dict {PACKAGE_PIN AF4 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[5]] -set_property -dict {PACKAGE_PIN AF2 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[5]] -### }}} - -### Byte lane #6 -### {{{ -set_property -dict {PACKAGE_PIN W3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[48]] -set_property -dict {PACKAGE_PIN V4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[49]] -set_property -dict {PACKAGE_PIN U2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[50]] -set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[51]] -set_property -dict {PACKAGE_PIN V6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[52]] -set_property -dict {PACKAGE_PIN V3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[53]] -set_property -dict {PACKAGE_PIN U1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[54]] -set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[55]] -set_property -dict {PACKAGE_PIN W6 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[6]] -set_property -dict {PACKAGE_PIN W5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[6]] -set_property -dict {PACKAGE_PIN U7 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[6]] -### }}} - -### Byte lane #7 -### {{{ -set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[56]] -set_property -dict {PACKAGE_PIN AA3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[57]] -set_property -dict {PACKAGE_PIN W1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[58]] -set_property -dict {PACKAGE_PIN V2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[59]] -set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[60]] -set_property -dict {PACKAGE_PIN Y3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[61]] -set_property -dict {PACKAGE_PIN Y2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[62]] -set_property -dict {PACKAGE_PIN V1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[63]] -set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[7]] -set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[7]] -set_property -dict {PACKAGE_PIN Y1 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[7]] -### }}} - -## }}} - -## HDMI -## {{{ -#set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports io_hdmirx_cec] -set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports o_hdmirx_hpd_n] -#set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports io_hdmirx_scl] -#set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports io_hdmirx_sda] - -#set_property -dict {PACKAGE_PIN P24 IOSTANDARD TMDS_33} [get_ports i_hdmirx_p[0]] -#set_property -dict {PACKAGE_PIN N24 IOSTANDARD TMDS_33} [get_ports i_hdmirx_n[0]] -#set_property -dict {PACKAGE_PIN R26 IOSTANDARD TMDS_33} [get_ports i_hdmirx_p[1]] -#set_property -dict {PACKAGE_PIN P26 IOSTANDARD TMDS_33} [get_ports i_hdmirx_n[1]] -#set_property -dict {PACKAGE_PIN R25 IOSTANDARD TMDS_33} [get_ports i_hdmirx_p[2]] -#set_property -dict {PACKAGE_PIN P25 IOSTANDARD TMDS_33} [get_ports i_hdmirx_n[2]] -#set_property -dict {PACKAGE_PIN M24 IOSTANDARD TMDS_33} [get_ports i_hdmirx_clk_p] -#set_property -dict {PACKAGE_PIN L24 IOSTANDARD TMDS_33} [get_ports i_hdmirx_clk_n] - -#set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports io_hdmitx_cec] -set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports i_hdmitx_hpd_n] - -#set_property -dict {PACKAGE_PIN P19 IOSTANDARD TMDS_33} [get_ports o_hdmitx_p[0]] -#set_property -dict {PACKAGE_PIN P20 IOSTANDARD TMDS_33} [get_ports o_hdmitx_n[0]] -#set_property -dict {PACKAGE_PIN K25 IOSTANDARD TMDS_33} [get_ports o_hdmitx_p[1]] -#set_property -dict {PACKAGE_PIN K26 IOSTANDARD TMDS_33} [get_ports o_hdmitx_n[1]] -#set_property -dict {PACKAGE_PIN M25 IOSTANDARD TMDS_33} [get_ports o_hdmitx_p[2]] -#set_property -dict {PACKAGE_PIN L25 IOSTANDARD TMDS_33} [get_ports o_hdmitx_n[2]] -#set_property -dict {PACKAGE_PIN N19 IOSTANDARD TMDS_33} [get_ports o_hdmitx_clk_p] -#set_property -dict {PACKAGE_PIN M20 IOSTANDARD TMDS_33} [get_ports o_hdmitx_clk_n] -## }}} - -## PCIe -## {{{ -#set_property -dict { PACKAGE_PIN D6 IOSTANDARD DIFF_HSTL_I_10 } [get_ports o_pcie_clk_p] -#set_property -dict { PACKAGE_PIN D5 IOSTANDARD DIFF_HSTL_I_10 } [get_ports o_pcie_clk_n] -#set_property -dict { PACKAGE_PIN B16 IOSTANDARD DIFF_HSTL_I_10 } [get_ports o_pcie_perst_n] - -#set_property -dict {PACKAGE_PIN A4 IOSTANDARD DIFF_HSTL_I_10 [get_ports o_pcie_p] -#set_property -dict {PACKAGE_PIN A3 IOSTANDARD DIFF_HSTL_I_10 [get_ports o_pcie_n] -#set_property -dict {PACKAGE_PIN B6 IOSTANDARD DIFF_HSTL_I_10 [get_ports i_pcie_p] -#set_property -dict {PACKAGE_PIN B5 IOSTANDARD DIFF_HSTL_I_10 [get_ports i_pcie_n] -## }}} - -## CRUVI -## {{{ -## }}} - -## Hard test points -## {{{ -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports o_tp[0]] -set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports o_tp[1]] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports o_tp[2]] -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports o_tp[3]] -## }}} - -## Bitstream options -set_property CONFIG_MODE SPIx4 [current_design] -set_property BITSTREAM.CONFIG.CONFIGRATE 26 [current_design] -set_property CONFIG_VOLTAGE 2.5 [current_design] -set_property CFGBVS VCCO [current_design] -set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] - -## Adding in any XDC_INSERT tags - -## No XDC.INSERT tag in mem_flash_bkram -## No XDC.INSERT tag in mem_bkram_only -## No XDC.INSERT tag in emmcscope -## No XDC.INSERT tag in sdioscope -## No XDC.INSERT tag in ddr3_controller -## No XDC.INSERT tag in bkram -## No XDC.INSERT tag in zip_alt_upc -## No XDC.INSERT tag in zip_alt_uoc -## No XDC.INSERT tag in syspic -## No XDC.INSERT tag in zip_jiffies -## No XDC.INSERT tag in sirefclk -## No XDC.INSERT tag in i2cdma -## No XDC.INSERT tag in ddr3_phy -## No XDC.INSERT tag in alt -## No XDC.INSERT tag in fan -## No XDC.INSERT tag in TMA -## No XDC.INSERT tag in emmc -## No XDC.INSERT tag in zip_dmac -## No XDC.INSERT tag in zip_tmc -## No XDC.INSERT tag in zip_tmb -## No XDC.INSERT tag in wb -## No XDC.INSERT tag in KEYS -## No XDC.INSERT tag in REGISTER -## No XDC.INSERT tag in i2c -## No XDC.INSERT tag in DEFAULT -## No XDC.INSERT tag in altpic -## No XDC.INSERT tag in SIM -## No XDC.INSERT tag in wbdown -## No XDC.INSERT tag in wb32 -## No XDC.INSERT tag in sdcard -## No XDC.INSERT tag in zip_alt_mtc -## No XDC.INSERT tag in REGDEFS -## No XDC.INSERT tag in clk150 -## No XDC.INSERT tag in buildtime -## No XDC.INSERT tag in uart -## No XDC.INSERT tag in RESET_ADDRESS -## No XDC.INSERT tag in zip -## No XDC.INSERT tag in XDC -## No XDC.INSERT tag in zip_alt_mpc -## No XDC.INSERT tag in version -## No XDC.INSERT tag in i2cscope -## No XDC.INSERT tag in clk200 -## No XDC.INSERT tag in wbu -## No XDC.INSERT tag in clk -## No XDC.INSERT tag in cfg -## No XDC.INSERT tag in gpio -## No XDC.INSERT tag in spio -## No XDC.INSERT tag in zip_alt_uic -## No XDC.INSERT tag in wbu_arbiter -## No XDC.INSERT tag in zip_alt_mic -## No XDC.INSERT tag in zip_alt_moc -## No XDC.INSERT tag in zip_alt_utc diff --git a/delete_later/rtl/builddate.v b/delete_later/rtl/builddate.v deleted file mode 100644 index 8297c29..0000000 --- a/delete_later/rtl/builddate.v +++ /dev/null @@ -1,40 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: builddate.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This file records the date of the last build. Running "make" -// in the main directory will create this file. The `define found -// within it then creates a version stamp that can be used to tell which -// configuration is within an FPGA and so forth. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -`ifndef DATESTAMP -`define DATESTAMP 32'h20230723 -`define BUILDTIME 32'h00082055 -`endif -// diff --git a/delete_later/rtl/clkcounter.v b/delete_later/rtl/clkcounter.v deleted file mode 100644 index 8d775b3..0000000 --- a/delete_later/rtl/clkcounter.v +++ /dev/null @@ -1,118 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: clkcounter.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Given a clock, asynchronous to the main or system clock, and -// given a PPS strobe that is synchronous to the main clock, count -// the number of clock ticks that take place between system clocks. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module clkcounter #( - parameter LGNAVGS = 4, - BUSW=32, - parameter CLOCKFREQ_HZ = 100_000_000 - ) ( - // {{{ - input wire i_sys_clk, - i_tst_clk, - input wire i_sys_pps, - output wire [(BUSW-1):0] o_sys_counts - // }}} - ); - - // Local declarations - // {{{ - reg [(LGNAVGS-1):0] avgs; - (* ASYNC_REG = "TRUE" *) - reg q_v, qq_v; - reg tst_posedge; - - reg [(BUSW-LGNAVGS-1):0] counter; - reg [(BUSW-LGNAVGS-1):0] r_sys_counts; - wire sys_pps; - // }}} - - // Move the clock across clock domains - // {{{ - always @(posedge i_tst_clk) - avgs <= avgs + 1'b1; - - always @(posedge i_sys_clk) - { qq_v, q_v } <= { q_v, avgs[(LGNAVGS-1)] }; - - always @(posedge i_sys_clk) - tst_posedge <= (!qq_v)&&(q_v); - // }}} - - // Generate a once per second pulse - // {{{ - generate if (CLOCKFREQ_HZ > 0) - begin : GEN_PPS - localparam CWID = $clog2(CLOCKFREQ_HZ+1); - reg [CWID-1:0] pps_counter; - reg r_sys_pps; - - initial pps_counter = 0; - always @(posedge i_sys_clk) - if (pps_counter >= CLOCKFREQ_HZ-1) - begin - pps_counter <= 0; - r_sys_pps <= 1; - end else begin - pps_counter <= pps_counter + 1; - r_sys_pps <= 0; - end - - assign sys_pps = r_sys_pps; - - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_sys_pps }; - // Verilator lint_on UNUSED - end else begin : COPY_PPS - assign sys_pps = i_sys_pps; - end endgenerate - // }}} - - // Now count edges between PPS signals - // {{{ - always @(posedge i_sys_clk) - if (sys_pps) - counter <= 0; - else if (tst_posedge) - counter <= counter + 1'b1; - - always @(posedge i_sys_clk) - if (sys_pps) - r_sys_counts <= counter; - // }}} - - assign o_sys_counts = { r_sys_counts, {(LGNAVGS){1'b0}} }; -endmodule diff --git a/delete_later/rtl/cpu/busdelay.v b/delete_later/rtl/cpu/busdelay.v deleted file mode 100644 index 6ff8ce8..0000000 --- a/delete_later/rtl/cpu/busdelay.v +++ /dev/null @@ -1,611 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: busdelay.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Delay any access to the wishbone bus by a single clock. -// -// When the first Zip System would not meet the timing requirements of -// the board it was placed upon, this bus delay was added to help out. -// It may no longer be necessary, having cleaned some other problems up -// first, but it will remain here as a means of alleviating timing -// problems. -// -// The specific problem takes place on the stall line: a wishbone master -// *must* know on the first clock whether or not the bus will stall. -// -// -// After a period of time, I started a new design where the timing -// associated with this original bus clock just wasn't ... fast enough. -// I needed to delay the stall line as well. A new busdelay was then -// written and debugged whcih delays the stall line. (I know, you aren't -// supposed to delay the stall line--but what if you *have* to in order -// to meet timing?) This new logic has been merged in with the old, -// and the DELAY_STALL line can be set to non-zero to use it instead -// of the original logic. Don't use it if you don't need it: it will -// consume resources and slow your bus down more, but if you do need -// it--don't be afraid to use it. -// -// Both versions of the bus delay will maintain a single access per -// clock when pipelined, they only delay the time between the strobe -// going high and the actual command being accomplished. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module busdelay #( - // {{{ - parameter AW=32, DW=32, -`ifdef FORMAL - localparam F_LGDEPTH=4, -`endif - parameter [0:0] DELAY_STALL = 1, - parameter [0:0] OPT_LOWPOWER = 0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Input/master bus - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [(AW-1):0] i_wb_addr, - input wire [(DW-1):0] i_wb_data, - input wire [(DW/8-1):0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [(DW-1):0] o_wb_data, - output reg o_wb_err, - // }}} - // Delayed bus - // {{{ - output reg o_dly_cyc, o_dly_stb, o_dly_we, - output reg [(AW-1):0] o_dly_addr, - output reg [(DW-1):0] o_dly_data, - output reg [(DW/8-1):0] o_dly_sel, - input wire i_dly_stall, - input wire i_dly_ack, - input wire [(DW-1):0] i_dly_data, - input wire i_dly_err - // }}} - // }}} - ); - -`ifdef FORMAL - wire [2+AW+DW+DW/8-1:0] f_wpending; -`endif - - generate if (DELAY_STALL) - begin : SKIDBUFFER - // {{{ - reg r_stb, r_we; - reg [(AW-1):0] r_addr; - reg [(DW-1):0] r_data; - reg [(DW/8-1):0] r_sel; - - // o_dly_cyc - // {{{ - initial o_dly_cyc = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wb_cyc) - o_dly_cyc <= 1'b0; - else - o_dly_cyc <= (!o_wb_err)&&((!i_dly_err)||(!o_dly_cyc)); - // }}} - - // o_dly_stb - // {{{ - initial o_dly_stb = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wb_cyc || o_wb_err || (o_dly_cyc && i_dly_err)) - o_dly_stb <= 1'b0; - else if (!o_dly_stb || !i_dly_stall) - o_dly_stb <= i_wb_stb || r_stb; - // }}} - - // r_stb - // {{{ - initial r_stb = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wb_cyc || o_wb_err || i_dly_err - || !i_dly_stall || !o_dly_stb) - r_stb <= 1'b0; - else if (i_wb_stb && !o_wb_stall) // && (o_dly_stb&&i_dly_stall) - r_stb <= 1'b1; - // }}} - - // r_* - // {{{ - initial { r_we, r_addr, r_data, r_sel } = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (i_reset || !i_wb_cyc || i_dly_err - || !o_dly_stb || !i_dly_stall)) - { r_we, r_addr, r_data, r_sel } <= 0; - else if (i_wb_stb && !o_wb_stall) // && (o_dly_stb&&i_dly_stall) - { r_we, r_addr, r_data, r_sel } - <= { i_wb_we, i_wb_addr, i_wb_data, i_wb_sel }; - // }}} - - initial o_dly_we = 1'b0; - initial o_dly_addr = 0; - initial o_dly_data = 0; - initial o_dly_sel = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (i_reset || (!i_wb_cyc || o_wb_err || (o_dly_cyc && i_dly_err)))) - { o_dly_we, o_dly_addr, o_dly_data, o_dly_sel } <= 0; - else if (!o_dly_stb || !i_dly_stall) - begin - if (r_stb) - { o_dly_we, o_dly_addr, o_dly_data, o_dly_sel } <= { r_we, r_addr, r_data, r_sel }; - else if (!OPT_LOWPOWER || i_wb_stb) - { o_dly_we, o_dly_addr, o_dly_data, o_dly_sel } <= { i_wb_we, i_wb_addr, i_wb_data, i_wb_sel }; - else - { o_dly_addr, o_dly_data, o_dly_sel } <= 0; - - end - - assign o_wb_stall = r_stb; - - // o_wb_ack - // {{{ - initial o_wb_ack = 0; - always @(posedge i_clk) - if (i_reset || !i_wb_cyc || o_wb_err || !o_dly_cyc) - o_wb_ack <= 1'b0; - else - o_wb_ack <= (i_dly_ack); - // }}} - - // o_wb_data - // {{{ - initial o_wb_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (i_reset || !i_wb_cyc || !o_dly_cyc - || o_wb_err || !i_dly_ack)) - o_wb_data <= 0; - else - o_wb_data <= i_dly_data; - // }}} - - // o_wb_err - // {{{ - initial o_wb_err = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wb_cyc || !o_dly_cyc) - o_wb_err <= 1'b0; - else - o_wb_err <= i_dly_err; - // }}} - - -`ifdef FORMAL - // {{{ - assign f_wpending = { r_stb, r_we, r_addr, r_data, r_sel }; - - always @(*) - if (OPT_LOWPOWER && !r_stb) - begin - assert(r_we == 0); - assert(r_addr == 0); - assert(r_data == 0); - assert(r_sel == 0); - end else if (r_stb) - assert(r_we == o_dly_we); - // }}} -`endif - // }}} - end else begin : NO_SKIDBUFFER - // {{{ - initial o_dly_cyc = 1'b0; - initial o_dly_stb = 1'b0; - initial o_dly_we = 1'b0; - initial o_dly_addr = 0; - initial o_dly_data = 0; - initial o_dly_sel = 0; - - always @(posedge i_clk) - if (i_reset) - o_dly_cyc <= 1'b0; - else if ((i_dly_err)&&(o_dly_cyc)) - o_dly_cyc <= 1'b0; - else if ((o_wb_err)&&(i_wb_cyc)) - o_dly_cyc <= 1'b0; - else - o_dly_cyc <= i_wb_cyc; - - // Add the i_wb_cyc criteria here, so we can simplify the - // o_wb_stall criteria below, which would otherwise *and* - // these two. - always @(posedge i_clk) - if (i_reset) - o_dly_stb <= 1'b0; - else if ((i_dly_err)&&(o_dly_cyc)) - o_dly_stb <= 1'b0; - else if ((o_wb_err)&&(i_wb_cyc)) - o_dly_stb <= 1'b0; - else if (!i_wb_cyc) - o_dly_stb <= 1'b0; - else if (!o_wb_stall) - o_dly_stb <= (i_wb_stb); - - always @(posedge i_clk) - if (!o_wb_stall) - o_dly_we <= i_wb_we; - - initial o_dly_addr = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (i_reset || !i_wb_cyc || o_wb_err - || (o_dly_cyc && i_dly_err))) - { o_dly_addr, o_dly_data, o_dly_sel } <= 0; - else if (!o_dly_stb || !i_dly_stall) - begin - { o_dly_addr, o_dly_data, o_dly_sel } - <= { i_wb_addr, i_wb_data, i_wb_sel }; - if (OPT_LOWPOWER && !i_wb_stb) - { o_dly_addr, o_dly_data, o_dly_sel } <= 0; - end - - initial o_wb_ack = 0; - always @(posedge i_clk) - if (i_reset) - o_wb_ack <= 1'b0; - else - o_wb_ack <= ((i_dly_ack)&&(!i_dly_err) - &&(o_dly_cyc)&&(i_wb_cyc)) - &&(!o_wb_err); - - initial o_wb_err = 0; - always @(posedge i_clk) - if (i_reset) - o_wb_err <= 1'b0; - else if (!o_dly_cyc) - o_wb_err <= 1'b0; - else - o_wb_err <= (o_wb_err)||(i_dly_err)&&(i_wb_cyc); - - initial o_wb_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (i_reset || !i_wb_cyc || !o_dly_cyc || o_wb_err || !i_dly_ack)) - o_wb_data <= 0; - else - o_wb_data <= i_dly_data; - - // Our only non-delayed line, yet still really delayed. Perhaps - // there's a way to register this? - // o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such? - // assign o_wb_stall=((i_wb_cyc)&&(i_dly_stall)&&(o_dly_stb));//&&o_cyc - assign o_wb_stall = (i_dly_stall)&&(o_dly_stb); - -`ifdef FORMAL - // f_wpending isn't used if DELAY_STALL is zero, but we'll give - // it a seemingly useful value anyway--if for no other reason - // than to be sure we set it to the right number of bits - assign f_wpending = { i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel }; -`endif - // }}} - end endgenerate -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations - // {{{ -`ifdef BUSDELAY -`define ASSUME assume -`else -`define ASSUME assert -`endif - - localparam ACK_DELAY = 5, - STALL_DELAY = 4; - localparam STB_BIT = 2+AW+DW+DW/8-1; - - wire [(F_LGDEPTH-1):0] f_wb_nreqs,f_wb_nacks, f_wb_outstanding, - f_dly_nreqs, f_dly_nacks, f_dly_outstanding; - - wire f_wb_busy, f_dly_busy, f_wb_req, f_dly_req; - wire [STB_BIT:0] f_wb_request, f_dly_request; - reg [STB_BIT:0] f_pending; - reg [(F_LGDEPTH-1):0] f_pending_acks; - reg [(F_LGDEPTH-1):0] f_pending_reqs; - reg [(F_LGDEPTH-1):0] f_expected, f_exp_nreqs, f_exp_nacks; - - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - // }}} - - initial `ASSUME(i_reset); - always @(*) - if (!f_past_valid) - `ASSUME(i_reset); - - //////////////////////////////////////////////////////////////////////// - // - // Bus properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - fwb_slave #(.AW(AW), .DW(DW), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_STALL(STALL_DELAY+1), - .F_MAX_ACK_DELAY(ACK_DELAY+1+2*STALL_DELAY), - .F_MAX_REQUESTS((1< 0 && f_dly_outstanding > 0)) - assert(i_wb_we == o_dly_we); - - //////////////////////////////////////////////////////////////////////// - // - // The "never" property - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // -`ifdef BUSDELAY - - (* anyconst *) reg f_never; - (* anyconst *) reg [STB_BIT:0] f_nvr_request; - - always @(*) - if (f_never && i_wb_stb) - `ASSUME(f_wb_request != f_nvr_request); - - always @(*) - if (f_never && f_pending[STB_BIT]) - assert(f_pending != f_nvr_request); - - always @(*) - if (f_never && o_dly_stb) - assert(f_dly_request != f_nvr_request); -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Low power properties (if invoked) - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_LOWPOWER) - begin - - always @(*) - if (!o_dly_stb) - begin - assert(o_dly_addr == 0); - assert(o_dly_data == 0); - assert(o_dly_sel == 0); - end - - always @(*) - if (!o_wb_ack) - assert(o_wb_data == 0); - end endgenerate - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/cpuops.v b/delete_later/rtl/cpu/cpuops.v deleted file mode 100644 index 8ecff3a..0000000 --- a/delete_later/rtl/cpu/cpuops.v +++ /dev/null @@ -1,395 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: cpuops.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is the ZipCPU ALU function. It handles all of the -// instruction opcodes 0-13. (14-15 are divide opcodes). -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module cpuops #( - // {{{ - parameter OPT_MPY = 3, // == 0 (no mpy),1-4,36 - parameter [0:0] OPT_SHIFTS = 1'b1, - parameter [0:0] OPT_LOWPOWER = 1'b1 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, i_stb, - input wire [3:0] i_op, - input wire [31:0] i_a, i_b, - output reg [31:0] o_c, - output wire [3:0] o_f, - output reg o_valid, -`ifdef VMPY_TB - // {{{ - // Define some wires used to peek at internal values during - // simulation. These are *ONLY* used by the ZipCPU mpy_tb - // simulation testbench. They are *NOT* used during synthesis, - // and not intended to be used outside of the ZipCPU setup. - // - output wire [5:0] OPT_MULTIPLY, - output wire [31:0] mpy_a_input, mpy_b_input, - output wire [63:0] mpy_output, - output wire [2:0] mpy_pipe, - // }}} -`endif - output wire o_busy - // }}} - ); - - // Declarations - // {{{ - wire [31:0] w_brev_result; - wire z, n, v, vx; - reg c, pre_sign, set_ovfl, keep_sgn_on_ovfl; - - wire [32:0] w_lsr_result, w_asr_result, w_lsl_result; - - wire [63:0] mpy_result; // Where we dump the multiply result - wire mpyhi; // Return the high half of the multiply - wire mpybusy; // The multiply is busy if true - wire mpydone; // True if we'll be valid on the next clock; - wire this_is_a_multiply_op; - reg r_busy; - - genvar k; - // }}} - - // Shift register pre-logic - // {{{ - generate if (OPT_SHIFTS) - begin : IMPLEMENT_SHIFTS - wire signed [32:0] w_pre_asr_input, w_pre_asr_shifted; - assign w_pre_asr_input = { i_a, 1'b0 }; - assign w_pre_asr_shifted = w_pre_asr_input >>> i_b[4:0]; - assign w_asr_result = (|i_b[31:5])? {(33){i_a[31]}} - : w_pre_asr_shifted;// ASR - assign w_lsr_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00 - :((i_b[5])?{32'h0,i_a[31]} - - : ( { i_a, 1'b0 } >> (i_b[4:0]) ));// LSR - assign w_lsl_result = ((|i_b[31:6])||(i_b[5]&&(i_b[4:0]!=0)))? 33'h00 - :((i_b[5])?{i_a[0], 32'h0} - : ({1'b0, i_a } << i_b[4:0])); // LSL - end else begin : NO_SHIFTS - - assign w_asr_result = { i_a[31], i_a[31:0] }; - assign w_lsr_result = { 1'b0, i_a[31:0] }; - assign w_lsl_result = { i_a[31:0], 1'b0 }; - - end endgenerate - // }}} - - // - // Bit reversal pre-logic - // {{{ - generate - for(k=0; k<32; k=k+1) - begin : bit_reversal_cpuop - assign w_brev_result[k] = i_b[31-k]; - end endgenerate - // }}} - - // Prelogic for our flags registers : set_ovfl and keep_sgn_on_ovfl - // {{{ - always @(posedge i_clk) - if (i_stb) // 1 LUT - set_ovfl<=(((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP - ||((i_op==4'h2)&&(i_a[31] == i_b[31])) // ADD - ||(i_op == 4'h6) // LSL - ||(i_op == 4'h5)); // LSR - - always @(posedge i_clk) - if (i_stb) // 1 LUT - keep_sgn_on_ovfl<= - (((i_op==4'h0)&&(i_a[31] != i_b[31]))//SUB&CMP - ||((i_op==4'h2)&&(i_a[31] == i_b[31]))); // ADD - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // Multiply handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // A 4-way multiplexer can be done in one 6-LUT. - // A 16-way multiplexer can therefore be done in 4x 6-LUT's with - // the Xilinx multiplexer fabric that follows. - // Given that we wish to apply this multiplexer approach to 33-bits, - // this will cost a minimum of 132 6-LUTs. - - assign this_is_a_multiply_op = (i_stb)&&((i_op[3:1]==3'h5)||(i_op[3:0]==4'hc)); - -`ifdef FORMAL -`define MPYOP abs_mpy -`else -`define MPYOP mpyop -`endif - `MPYOP #( - // {{{ - .OPT_MPY(OPT_MPY), - .OPT_LOWPOWER(OPT_LOWPOWER) - // }}} - ) thempy( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_stb(this_is_a_multiply_op), .i_op(i_op[1:0]), - .i_a(i_a), .i_b(i_b), .o_valid(mpydone), - .o_busy(mpybusy), .o_result(mpy_result), .o_hi(mpyhi) - // }}} - ); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The master ALU case statement - // {{{ - always @(posedge i_clk) - if (i_stb) - begin - pre_sign <= (i_a[31]); - c <= 1'b0; - casez(i_op) - 4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB - 4'b0001: o_c <= i_a & i_b; // BTST/And - 4'b0010:{c,o_c } <= i_a + i_b; // Add - 4'b0011: o_c <= i_a | i_b; // Or - 4'b0100: o_c <= i_a ^ i_b; // Xor - 4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR - 4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL - 4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR - 4'b1000: o_c <= w_brev_result; // BREV - 4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO - 4'b1010: o_c <= mpy_result[63:32]; // MPYHU - 4'b1011: o_c <= mpy_result[63:32]; // MPYHS - 4'b1100: o_c <= mpy_result[31:0]; // MPY - default: o_c <= i_b; // MOV, LDI - endcase - end else if (!OPT_LOWPOWER || mpydone) - // set the output based upon the multiply result - o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0]; - // }}} - - // o_busy, r_busy - // {{{ - initial r_busy = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_busy <= 1'b0; - else if (OPT_MPY > 1) - r_busy <= ((i_stb)&&(this_is_a_multiply_op))||mpybusy; - else - r_busy <= 1'b0; - - assign o_busy = (r_busy); // ||((OPT_MPY>1)&&(this_is_a_multiply_op)); - // }}} - - // Flags assignment and determination - // {{{ - assign z = (o_c == 32'h0000); - assign n = (o_c[31]); - assign v = (set_ovfl)&&(pre_sign != o_c[31]); - assign vx = (keep_sgn_on_ovfl)&&(pre_sign != o_c[31]); - - assign o_f = { v, n^vx, c, z }; - // }}} - - // o_valid - // {{{ - initial o_valid = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_valid <= 1'b0; - else if (OPT_MPY <= 1) - o_valid <= (i_stb); - else - o_valid <=((i_stb)&&(!this_is_a_multiply_op))||(mpydone); - // }}} - -`ifdef VMPY_TB -// {{{ - assign OPT_MULTIPLY = OPT_MPY; - generate if (OPT_MPY == 0) - begin : VGEN0 - assign mpy_a_input = 0; - assign mpy_b_input = 0; - assign mpy_pipe = 1'b0; - end else if (OPT_MPY == 1) - begin : VGEN1 - assign mpy_a_input = thempy.IMPY.MPY1CK.w_mpy_a_input[31:0]; - assign mpy_b_input = thempy.IMPY.MPY1CK.w_mpy_b_input[31:0]; - assign mpy_pipe = 3'b0; - end else if (OPT_MPY == 2) - begin : VGEN2 - assign mpy_a_input = thempy.IMPY.MPN1.MPY2CK.r_mpy_a_input[31:0]; - assign mpy_b_input = thempy.IMPY.MPN1.MPY2CK.r_mpy_b_input[31:0]; - assign mpy_pipe = { 2'b0, thempy.IMPY.MPN1.MPY2CK.mpypipe }; - end else if (OPT_MPY == 3) - begin : VGEN_NORMAL - assign mpy_a_input = thempy.IMPY.MPN1.MPN2.MPY3CK.r_mpy_a_input; - assign mpy_b_input = thempy.IMPY.MPN1.MPN2.MPY3CK.r_mpy_b_input; - assign mpy_pipe = { 1'b0, thempy.IMPY.MPN1.MPN2.MPY3CK.mpypipe }; - end else if (OPT_MPY == 4) - begin : VGEN_PARTIAL - assign mpy_a_input = thempy.IMPY.MPN1.MPN2.MPN3.MPY4CK.r_mpy_a_input; - assign mpy_b_input = thempy.IMPY.MPN1.MPN2.MPN3.MPY4CK.r_mpy_b_input; - assign mpy_pipe = thempy.IMPY.MPN1.MPN2.MPN3.MPY4CK.mpypipe; - end else begin : VGEN_SLOW - assign mpy_a_input = thempy.IMPY.MPN1.MPN2.MPN3.MPYSLOW.slowmpyi.i_a[31:0]; - assign mpy_b_input = thempy.IMPY.MPN1.MPN2.MPN3.MPYSLOW.slowmpyi.i_b[31:0]; - assign mpy_pipe = {(3){mpybusy}}; - end endgenerate - - assign mpy_output = mpy_result; -// }}} -`endif -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations - // {{{ - initial assume(i_reset); - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - // }}} - -`define ASSERT assert -`ifdef CPUOPS -`define ASSUME assume -`else -`define ASSUME assert -`endif - - // No request should be given us if/while we are busy - // {{{ - always @(posedge i_clk) - if (o_busy) - `ASSUME(!i_stb); - // }}} - - // Following any request other than a multiply request, we should - // respond in the next cycle - // {{{ - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(o_busy))&&(!$past(this_is_a_multiply_op))) - `ASSERT(!o_busy); - // }}} - - // Valid and busy can never both be asserted - // {{{ - always @(posedge i_clk) - `ASSERT((!o_valid)||(!r_busy)); - // }}} - - // Following any busy, we should always become valid - // {{{ - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_busy))&&(!o_busy)) - `ASSERT($past(i_reset) || o_valid); - // }}} - - // Check the shift values - // {{{ - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_stb))) - begin - if (($past(|i_b[31:6]))||($past(i_b[5:0])>6'd32)) - begin - assert(($past(i_op)!=4'h5) - ||({o_c,c}=={(33){1'b0}})); - assert(($past(i_op)!=4'h6) - ||({c,o_c}=={(33){1'b0}})); - assert(($past(i_op)!=4'h7) - ||({o_c,c}=={(33){$past(i_a[31])}})); - end else if ($past(i_b[5:0]==6'd32)) - begin - assert(($past(i_op)!=4'h5) - ||(o_c=={(32){1'b0}})); - assert(($past(i_op)!=4'h6) - ||(o_c=={(32){1'b0}})); - assert(($past(i_op)!=4'h7) - ||(o_c=={(32){$past(i_a[31])}})); - end if ($past(i_b)==0) - begin - assert(($past(i_op)!=4'h5) - ||({o_c,c}=={$past(i_a), 1'b0})); - assert(($past(i_op)!=4'h6) - ||({c,o_c}=={1'b0, $past(i_a)})); - assert(($past(i_op)!=4'h7) - ||({o_c,c}=={$past(i_a), 1'b0})); - end if ($past(i_b)==1) - begin - assert(($past(i_op)!=4'h5) - ||({o_c,c}=={1'b0, $past(i_a)})); - assert(($past(i_op)!=4'h6) - ||({c,o_c}=={$past(i_a),1'b0})); - assert(($past(i_op)!=4'h7) - ||({o_c,c}=={$past(i_a[31]),$past(i_a)})); - end if ($past(i_b)==2) - begin - assert(($past(i_op)!=4'h5) - ||({o_c,c}=={2'b0, $past(i_a[31:1])})); - assert(($past(i_op)!=4'h6) - ||({c,o_c}=={$past(i_a[30:0]),2'b0})); - assert(($past(i_op)!=4'h7) - ||({o_c,c}=={{(2){$past(i_a[31])}},$past(i_a[31:1])})); - end if ($past(i_b)==31) - begin - assert(($past(i_op)!=4'h5) - ||({o_c,c}=={31'b0, $past(i_a[31:30])})); - assert(($past(i_op)!=4'h6) - ||({c,o_c}=={$past(i_a[1:0]),31'b0})); - assert(($past(i_op)!=4'h7) - ||({o_c,c}=={{(31){$past(i_a[31])}},$past(i_a[31:30])})); - end - end - // }}} -`endif -// }}} -endmodule -// -// iCE40 NoMPY,w/Shift NoMPY,w/o Shift -// SB_CARRY 64 64 -// SB_DFFE 3 3 -// SB_DFFESR 1 1 -// SB_DFFSR 33 33 -// SB_LUT4 748 323 diff --git a/delete_later/rtl/cpu/dblfetch.v b/delete_later/rtl/cpu/dblfetch.v deleted file mode 100644 index c61f794..0000000 --- a/delete_later/rtl/cpu/dblfetch.v +++ /dev/null @@ -1,1031 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: dblfetch.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is one step beyond the simplest instruction fetch, -// prefetch.v. dblfetch.v uses memory pipelining to fetch two -// (or more) instruction words in one bus cycle. If the CPU consumes -// either of these before the bus cycle completes, a new request will be -// made of the bus. In this way, we can keep the CPU filled in spite -// of a (potentially) slow memory operation. The bus request will end -// when both requests have been sent and both result locations are empty. -// -// This routine is designed to be a touch faster than the single -// instruction prefetch (prefetch.v), although not as fast as the -// prefetch and cache approach found elsewhere (pfcache.v). -// -// 20180222: Completely rebuilt. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module dblfetch #( - // {{{ - parameter ADDRESS_WIDTH=30, // Byte addr - parameter INSN_WIDTH=32, - parameter DATA_WIDTH = INSN_WIDTH, - localparam AW=ADDRESS_WIDTH, - DW=DATA_WIDTH, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b1 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // CPU signals--from the CPU - input wire i_new_pc, i_clear_cache,i_ready, - input wire [AW-1:0] i_pc, - // ... and in return - output reg o_valid, - output reg o_illegal, - output reg [INSN_WIDTH-1:0] o_insn, - output reg [AW-1:0] o_pc, - // Wishbone outputs - output reg o_wb_cyc, o_wb_stb, - // verilator coverage_off - output wire o_wb_we, - // verilator coverage_on - output reg [AW-$clog2(DW/8)-1:0] o_wb_addr, - // verilator coverage_off - output wire [DW-1:0] o_wb_data, - // verilator coverage_on - // And return inputs - input wire i_wb_stall, i_wb_ack, i_wb_err, - input wire [DW-1:0] i_wb_data - // }}} - ); - - // Local declarations - // {{{ - wire last_stb; - reg invalid_bus_cycle; - - reg [(DW-1):0] cache_word; - reg cache_valid; - reg [1:0] inflight; - reg cache_illegal; - - wire r_valid; - wire [DATA_WIDTH-1:0] r_insn, i_wb_shifted; - // }}} - - assign o_wb_we = 1'b0; - assign o_wb_data = {(DATA_WIDTH){1'b0}}; - - // o_wb_cyc, o_wb_stb - // {{{ - initial o_wb_cyc = 1'b0; - initial o_wb_stb = 1'b0; - always @(posedge i_clk) - if (i_reset || i_clear_cache || (o_wb_cyc && i_wb_err)) - begin : RESET_ABORT - // {{{ - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - // }}} - end else if (o_wb_cyc) - begin : END_CYCLE - // {{{ - if (!o_wb_stb || !i_wb_stall) - o_wb_stb <= (!last_stb); - - // Relase the bus on the second ack - if ((!o_wb_stb || !i_wb_stall) && last_stb - && inflight + (o_wb_stb ? 1:0) == (i_wb_ack ? 1:0)) - begin - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - end - - if (i_new_pc) // || i_clear_cache) - { o_wb_cyc, o_wb_stb } <= 2'b0; - // }}} - end else if ((i_new_pc || invalid_bus_cycle) - ||(o_valid && i_ready && !r_valid && !cache_illegal)) - begin : START_CYCLE - // {{{ - // Initiate a bus cycle if ... the last bus cycle was - // aborted (bus error or new_pc), we've been given a - // new PC to go get, or we just exhausted our one - // instruction cache - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - // }}} - end - // }}} - - // inflight - // {{{ - initial inflight = 2'b00; - always @(posedge i_clk) - if (!o_wb_cyc) - inflight <= 2'b00; - else begin - case({ (o_wb_stb && !i_wb_stall), i_wb_ack }) - 2'b01: inflight <= inflight - 1'b1; - 2'b10: inflight <= inflight + 1'b1; - // If neither ack nor request, then no change. Likewise - // if we have both an ack and a request, there's no change - // in the number of requests in flight. - default: begin end - endcase - end - // }}} - - // last_stb - // {{{ - // assign last_stb = (inflight != 2'b00)||(o_valid&& (!i_ready||r_valid)); - assign last_stb = (!o_wb_stb||!i_wb_stall)&&(inflight - + (o_wb_stb ? 1:0) - + (o_valid&&(!i_ready || r_valid)) >= 2'b10); - // }}} - - // invalid_bus_cycle - // {{{ - initial invalid_bus_cycle = 1'b0; - always @(posedge i_clk) - if (i_reset) - invalid_bus_cycle <= 1'b0; - else if (o_wb_cyc && i_new_pc) - invalid_bus_cycle <= 1'b1; - else if (!o_wb_cyc) - invalid_bus_cycle <= 1'b0; - // }}} - - // o_wb_addr - // {{{ - initial o_wb_addr = {(AW-$clog2(DATA_WIDTH/8)){1'b1}}; - always @(posedge i_clk) - if (i_new_pc) - o_wb_addr <= i_pc[AW-1:$clog2(DATA_WIDTH/8)]; - // else if (i_clear_cache) - // o_wb_addr <= o_pc[AW-1:$clog2(DATA_WIDTH/8)]; - else if (o_wb_stb && !i_wb_stall) - o_wb_addr <= o_wb_addr + 1'b1; - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // Now for the immediate output word to the CPU - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // This only applies when the bus size doesn't match the instruction - // word size. Here, we only support bus sizes greater than the - // instruction word size. -`ifdef FORMAL - wire [DATA_WIDTH-1:0] f_bus_word; -`endif - - generate if (DATA_WIDTH > INSN_WIDTH) - begin : GEN_SUBSHIFT - // {{{ - localparam NSHIFT = $clog2(DATA_WIDTH/INSN_WIDTH); - - reg rg_valid; - reg [DATA_WIDTH-1:0] rg_insn; - reg [NSHIFT:0] r_count; - reg [NSHIFT-1:0] r_shift; - - // rg_valid - // {{{ - always @(posedge i_clk) - if (i_reset || i_new_pc) // || i_clear_cache) - rg_valid <= 1'b0; - else if (r_valid) - rg_valid <= !i_ready || (r_count > 1); - else if (!o_valid || i_ready) - begin - rg_valid <= 1'b0; - if (cache_valid) - rg_valid <= 1'b1; - if (o_wb_cyc && i_wb_ack && !(&r_shift)) - rg_valid <= 1'b1; - end - // }}} - - // rg_insn - // {{{ - always @(posedge i_clk) - if (!o_valid || i_ready) - begin - if (cache_valid && !r_valid) - begin - if (OPT_LITTLE_ENDIAN) - rg_insn <= cache_word >> INSN_WIDTH; - else - rg_insn <= cache_word << INSN_WIDTH; - end else if (i_wb_ack && !r_valid) - begin - rg_insn <= i_wb_data; - if (OPT_LITTLE_ENDIAN) - rg_insn <= i_wb_shifted >> INSN_WIDTH; - else - rg_insn <= i_wb_shifted << INSN_WIDTH; - end else begin - if (OPT_LITTLE_ENDIAN) - rg_insn <= rg_insn >> INSN_WIDTH; - else - rg_insn <= rg_insn << INSN_WIDTH; - end - end - // }}} - - // r_count - // {{{ - always @(posedge i_clk) - if (i_reset || i_new_pc) // || i_clear_cache) - r_count <= 0; - else if (o_valid && i_ready && r_valid) - begin - r_count <= r_count - 1; - end else if (!o_valid || (i_ready && !r_valid)) - begin - if (cache_valid) - r_count <= { 1'b0, {(NSHIFT){1'b1}} }; - else if (o_wb_cyc && i_wb_ack) - r_count <= { 1'b0, ~r_shift }; - end -`ifdef FORMAL - always @(*) - if (!i_reset && !i_new_pc && !i_clear_cache) - begin - if (!o_valid) - assert(!r_valid); - assert(r_valid == (r_count > 0)); - assert(r_count <= (1< 0) - assert(!o_valid && !r_valid); -`endif - // }}} - - assign r_valid = rg_valid; - assign r_insn = rg_insn; - if (OPT_LITTLE_ENDIAN) - begin : GEN_LITTLE_ENDIAN_SHIFT - assign i_wb_shifted = i_wb_data >> (r_shift * INSN_WIDTH); - end else begin : GEN_BIGENDIAN_SHIFT - assign i_wb_shifted = i_wb_data << (r_shift * INSN_WIDTH); - end - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused_shift; - assign unused_shift = &{ 1'b0, - r_insn[DATA_WIDTH-1:INSN_WIDTH], - i_wb_shifted[DATA_WIDTH-1:INSN_WIDTH] }; - // Verilator lint_on UNUSED - // }}} -`ifdef FORMAL - assign f_bus_word = rg_insn << ((r_count-1)* INSN_WIDTH); - always @(*) - if (!i_reset && r_valid) - begin - assert(i_clear_cache || i_new_pc || o_valid); - assert(r_shift == 0); - assert((r_count + o_pc[$clog2(DW/8)-1:$clog2(INSN_WIDTH/8)]) - == ((1<> (f_const_addr[$clog2(DW/8)-1:$clog2(IW/8)] * IW); - always @(*) - assume(f_shifted_insn[IW-1:0] == f_const_insn); - - end else begin - assign f_shifted_insn = f_const_bus_word - << (f_const_addr[$clog2(DW/8)-1:$clog2(IW/8)] * IW); - - always @(*) - assume(f_shifted_insn[DW-1:DW-IW] - == f_const_insn); - - end - // }}} - end endgenerate - - // - // Here is a corrollary to our contract. Anything in the one-word - // cache must also match the contract as well. - // - always @(*) - if ((f_cache_addr[AW-1:$clog2(DATA_WIDTH/8)] == f_const_bus_addr) - &&(cache_valid)) - begin - if (!cache_illegal) - assert(cache_word == f_const_bus_word); - - if (f_const_illegal) - assert(cache_illegal); - else - assert(o_illegal || !cache_illegal); - end - - // always @(posedge i_clk) - // if ((f_past_valid)&&(!$past(cache_illegal))&&(!cache_valid)) - // assert(!cache_illegal); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Additional assertions necessary to pass induction - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // We have only a one word cache. Hence, we shouldn't be asking - // for more data any time we have nowhere to put it. - always @(*) - if (o_wb_stb) - assert(!cache_valid || i_ready); - - always @(*) - if (o_valid && cache_valid) - assert((f_outstanding == 0)&&(!o_wb_stb)); - - always @(*) - if (o_valid && (r_valid || !i_ready)) - assert(f_outstanding < 2); - - always @(*) - if (!o_valid || (i_ready && !r_valid)) - assert(f_outstanding <= 2); - - // always @(posedge i_clk) - // if ((f_past_valid)&&($past(o_wb_cyc && !o_wb_stb)) &&(o_wb_cyc)) - // assert(inflight != 0); - - always @(*) - if (o_wb_cyc && i_wb_ack) - assert(!cache_valid); - - always @(posedge i_clk) - if (o_wb_cyc) - assert(inflight == f_outstanding); - - // Verilator lint_off WIDTH - assign this_return_address = o_wb_addr - f_outstanding; - // Verilator lint_on WIDTH - assign next_pc_address = f_next_addr[AW-1:$clog2(DATA_WIDTH/8)]; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Address checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - begin - pc_bus_addr = o_pc[AW-1:$clog2(DW/8)]; - pc_bus_addr_next = pc_bus_addr + 1; - pc_bus_addr_dbl = pc_bus_addr + 2; - end - - always @(*) - if (i_reset || o_illegal || invalid_bus_cycle) - begin - end else if (!o_valid) - begin - if (o_wb_cyc) - begin - if (inflight == 0) - assert(o_wb_addr == pc_bus_addr); - assert(pc_bus_addr == this_return_address); - end - end else if (cache_valid || (o_wb_cyc && !o_wb_stb)) - begin - assert(o_wb_addr == pc_bus_addr_dbl); - end else if (o_valid) - assert(o_wb_addr == pc_bus_addr_next); - - always @(posedge i_clk) - if (f_past_valid &&($past(!i_reset && !i_new_pc && !i_clear_cache)) - &&(!$past(invalid_bus_cycle))) - begin - if (($past(o_wb_cyc && (i_wb_ack || i_wb_err))) - &&($past(!o_valid || (i_ready && !r_valid))) - &&(!$past(cache_valid))) - begin - assert(o_pc[AW-1:$clog2(DW/8)] == $past(this_return_address)); - end else if (cache_valid) - begin - assert(o_wb_addr == pc_bus_addr_dbl); - assert(f_outstanding == 0); - end else if (o_valid) - begin - if (f_outstanding == 0) - assert(o_illegal || o_wb_addr == pc_bus_addr_next); - else if (f_outstanding == 1) - assert(o_illegal || o_wb_addr == pc_bus_addr_dbl); - else if (f_outstanding == 2) - assert(o_wb_addr == pc_bus_addr_dbl); - end else if (o_wb_cyc) - assert(o_pc[AW-1:$clog2(DW/8)] == this_return_address); - end - - always @(posedge i_clk) - if (!i_reset && o_illegal) - begin - assert(!o_wb_cyc); - assert(cache_illegal); - end - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_wb_cyc && !i_new_pc))&&(!o_valid) - &&(o_wb_cyc)) - assert(o_pc[AW-1:$clog2(DW/8)] == this_return_address); - - always @(posedge i_clk) - if (o_valid && !o_wb_cyc && !o_illegal) - begin - if (cache_valid) - assert(f_dbl_next[AW-1:$clog2(DW/8)] == o_wb_addr); - else - assert(pc_bus_addr_next == o_wb_addr); - - end - - always @(*) - if (o_wb_cyc || o_valid) - begin - assert(o_wb_addr == pc_bus_addr - || o_wb_addr == pc_bus_addr_next - || o_wb_addr == pc_bus_addr_dbl); - end - -// always @(posedge i_clk) -// if ((f_past_valid)&& $past(o_wb_cyc && !cache_valid) && cache_valid) -// assert(next_pc_address == $past(this_return_address)); - - // - // - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_wb_cyc))&&(o_wb_cyc)) - begin - if (o_valid && !cache_valid) - begin - // assert(this_return_address == next_pc_address); - end else if (!o_valid) - assert(this_return_address == o_pc[AW-1:$clog2(DW/8)]); - end else if ((f_past_valid)&&(!invalid_bus_cycle) - &&(!o_wb_cyc)&&(o_valid)&&(!o_illegal) - &&(!cache_valid)) - assert(o_wb_addr == next_pc_address); - - - always @(*) - if (invalid_bus_cycle) - assert(!o_wb_cyc); - - always @(*) - if (cache_valid) - assert(o_valid); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover statements - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg f_cvr_aborted, f_cvr_fourth_ack; - - always @(posedge i_clk) - cover((f_past_valid)&&($past(f_nacks)==3) - &&($past(i_wb_ack))&&($past(o_wb_cyc))); - - initial f_cvr_aborted = 0; - always @(posedge i_clk) - if (i_reset) - f_cvr_aborted <= 0; - else if (!o_wb_cyc && (f_nreqs != f_nacks)) - f_cvr_aborted <= 1; - - initial f_cvr_fourth_ack = 0; - always @(posedge i_clk) - if (i_reset) - f_cvr_fourth_ack <= 0; - else if ((f_nacks == 3)&&(o_wb_cyc && i_wb_ack)) - f_cvr_fourth_ack <= 1; - - always @(posedge i_clk) - cover(!o_wb_cyc && (f_nreqs == f_nacks) - && !f_cvr_aborted && f_cvr_fourth_ack); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Temporary simplifications - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} - - // Make Verilator happy -- formal section - // {{{ - // Verilator lint_off UNUSED - wire unused_formal; - assign unused_formal = &{ f_dbl_next[1:0], f_const_addr[1:0] }; - // Verilator lint_on UNUSED - // }}} -`endif // FORMAL -// }}} -endmodule -// -// Usage: (this) (prior) (old) (S6) -// Cells 374 387 585 459 -// FDRE 135 108 203 171 -// LUT1 2 3 2 -// LUT2 9 3 4 5 -// LUT3 98 76 104 71 -// LUT4 2 0 2 2 -// LUT5 3 35 35 3 -// LUT6 6 5 10 43 -// MUXCY 58 62 93 62 -// MUXF7 1 0 2 3 -// MUXF8 0 1 1 -// RAM64X1D 0 32 32 32 -// XORCY 60 64 96 64 -// diff --git a/delete_later/rtl/cpu/dcache.v b/delete_later/rtl/cpu/dcache.v deleted file mode 100644 index 4b07bc2..0000000 --- a/delete_later/rtl/cpu/dcache.v +++ /dev/null @@ -1,2725 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: dcache.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: To provide a simple data cache for the ZipCPU. The cache is -// designed to be a drop in replacement for the pipememm memory -// unit currently existing within the ZipCPU. The goal of this unit is -// to achieve single cycle read access to any memory in the last cache line -// used, or two cycle access to any memory currently in the cache. -// -// The cache separates between four types of accesses, one write and three -// read access types. The read accesses are split between those that are -// not cacheable, those that are in the cache, and those that are not. -// -// 1. Write accesses always create writes to the bus. For these reasons, -// these may always be considered cache misses. -// -// Writes to memory locations within the cache must also update -// cache memory immediately, to keep the cache in synch. -// -// It is our goal to be able to maintain single cycle write -// accesses for memory bursts. -// -// 2. Read access to non-cacheable memory locations will also immediately -// go to the bus, just as all write accesses go to the bus. -// -// 3. Read accesses to cacheable memory locations will immediately read -// from the appropriate cache line. However, since thee valid -// line will take a second clock to read, it may take up to two -// clocks to know if the memory was in cache. For this reason, -// we bypass the test for the last validly accessed cache line. -// -// We shall design these read accesses so that reads to the cache -// may take place concurrently with other writes to the bus. -// -// Errors in cache reads will void the entire cache line. For this reason, -// cache lines must always be of a smaller in size than any associated -// virtual page size--lest in the middle of reading a page a TLB miss -// take place referencing only a part of the cacheable page. -// -// -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// -// -`ifdef FORMAL -`define ASSERT assert - -`ifdef DCACHE -`define ASSUME assume -`else -`define ASSUME assert -`endif -`endif - // }}} -module dcache #( - // {{{ - parameter LGCACHELEN = 8, - BUS_WIDTH=32, - ADDRESS_WIDTH=32-$clog2(BUS_WIDTH/8), - LGNLINES=(LGCACHELEN-3), // Log of the number of separate cache lines - NAUX=5, // # of aux d-wires to keep aligned w/memops - parameter DATA_WIDTH=32, // CPU's register width - parameter [0:0] OPT_LOCAL_BUS=1'b1, - parameter [0:0] OPT_PIPE=1'b1, - parameter [0:0] OPT_LOCK=1'b1, - parameter [0:0] OPT_DUAL_READ_PORT=1'b1, - parameter OPT_FIFO_DEPTH = 4, - localparam AW = ADDRESS_WIDTH, // Just for ease of notation below - localparam CS = LGCACHELEN, // Number of bits in a cache address - localparam LS = CS-LGNLINES, // Bits to spec position w/in cline -`ifdef FORMAL - parameter F_LGDEPTH=1 + (((!OPT_PIPE)||(LS > OPT_FIFO_DEPTH)) - ? LS : OPT_FIFO_DEPTH), -`endif - parameter [0:0] OPT_LOWPOWER = 1'b0, - // localparam DW = 32, // Bus data width - localparam DP = OPT_FIFO_DEPTH, - localparam WBLSB = $clog2(BUS_WIDTH/8), - // localparam DLSB = $clog2(DATA_WIDTH/8), - // - localparam [1:0] DC_IDLE = 2'b00, // Bus is idle - localparam [1:0] DC_WRITE = 2'b01, // Write - localparam [1:0] DC_READS = 2'b10, // Read a single value(!cachd) - localparam [1:0] DC_READC = 2'b11 // Read a whole cache line - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, i_clear, - // Interface from the CPU - // {{{ - input wire i_pipe_stb, i_lock, - input wire [2:0] i_op, - input wire [DATA_WIDTH-1:0] i_addr, - input wire [DATA_WIDTH-1:0] i_data, - input wire [(NAUX-1):0] i_oreg, // Aux data, such as reg to write to - // Outputs, going back to the CPU - output reg o_busy, o_rdbusy, - output reg o_pipe_stalled, - output reg o_valid, o_err, - output reg [(NAUX-1):0] o_wreg, - output reg [DATA_WIDTH-1:0] o_data, - // }}} - // Wishbone bus master outputs - // {{{ - output wire o_wb_cyc_gbl, o_wb_cyc_lcl, - output reg o_wb_stb_gbl, o_wb_stb_lcl, - output reg o_wb_we, - output reg [(AW-1):0] o_wb_addr, - output reg [BUS_WIDTH-1:0] o_wb_data, - output wire [BUS_WIDTH/8-1:0] o_wb_sel, - // Wishbone bus slave response inputs - input wire i_wb_stall, i_wb_ack, i_wb_err, - input wire [BUS_WIDTH-1:0] i_wb_data - // }}} - // }}} - ); - - // Declarations - // {{{ - localparam FIF_WIDTH = (NAUX-1)+2+WBLSB; - integer ik; - -`ifdef FORMAL - wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding; - wire f_pc, f_gie, f_read_cycle; - - reg f_past_valid; -`endif - // - // output reg [31:0] o_debug; - - reg cyc, stb, last_ack, end_of_line, last_line_stb; - reg r_wb_cyc_gbl, r_wb_cyc_lcl; - // npending is the number of pending non-cached operations, counted - // from the i_pipe_stb to the o_wb_ack - reg [DP:0] npending; - - - reg [((1<> (i_addr[1:0]); - else - full_sel = { pre_sel, {(BUS_WIDTH/8-4){1'b0}} } - >> (i_addr[WBLSB-1:0]); - - initial r_wb_sel = -1; - always @(posedge i_clk) - if (i_reset) - r_wb_sel <= -1; - else if (i_pipe_stb && (i_op[0] || !w_cachable)) - r_wb_sel <= full_sel; - else if (!i_wb_stall) - r_wb_sel <= -1; - - assign o_wb_sel = r_wb_sel; - // }}} - end endgenerate - // }}} - - // o_wb_data - // {{{ - generate if (DATA_WIDTH == BUS_WIDTH) - begin : GEN_SAME_BUSWIDTH - // {{{ - initial o_wb_data = 0; - always @(posedge i_clk) - if (i_reset) - o_wb_data <= 0; - else if ((!o_busy || !i_wb_stall) && (!OPT_LOWPOWER || i_pipe_stb)) - begin - if (DATA_WIDTH == 32) - begin - if (OPT_LOWPOWER) - begin : ZERO_UNUSED_DATA_BITS - casez({ i_op[2:1], i_addr[1:0] }) - 4'b0???: o_wb_data <= i_data; - 4'b100?: o_wb_data <= { i_data[15:0], 16'h0 }; - 4'b101?: o_wb_data <= { 16'h0, i_data[15:0] }; - 4'b1100: o_wb_data <= { i_data[7:0], 24'h0 }; - 4'b1101: o_wb_data <= { 8'h0, i_data[7:0], 16'h0 }; - 4'b1110: o_wb_data <= { 16'h0, i_data[7:0], 8'h0 }; - 4'b1111: o_wb_data <= { 24'h0, i_data[7:0] }; - endcase - end else begin : DUPLICATE_UNUSED_DATA_BITS - casez(i_op[2:1]) - 2'b0?: o_wb_data <= i_data; - 2'b10: o_wb_data <= { (2){i_data[15:0]} }; - 2'b11: o_wb_data <= { (4){i_data[ 7:0]} }; - endcase - end - end else begin - // Verilator coverage_off - casez(i_op[2:1]) - 2'b0?: o_wb_data <= i_data << (8*i_addr[$clog2(DATA_WIDTH)-1:0]); - 2'b10: o_wb_data <= { 16'h0, i_data[15:0] } << (8*i_addr[$clog2(DATA_WIDTH)-1:0]); - 2'b11: o_wb_data <= { 24'h0, i_data[7:0] } << (8*i_addr[$clog2(DATA_WIDTH)-1:0]); - endcase - // Verilator coverage_on - end - end else if (OPT_LOWPOWER && !i_wb_stall) - o_wb_data <= 0; - // }}} - end else begin : GEN_WIDE_BUS - // {{{ - reg [DATA_WIDTH-1:0] pre_shift; - reg [BUS_WIDTH-1:0] wide_preshift, shifted_data; - - always @(*) - begin - casez(i_op[2:1]) - 2'b0?: pre_shift = i_data; - 2'b10: pre_shift = { i_data[15:0], - {(DATA_WIDTH-16){1'b0}} }; - 2'b11: pre_shift = { i_data[ 7:0], - {(DATA_WIDTH- 8){1'b0}} }; - endcase - - if (OPT_LOCAL_BUS && (&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - begin - wide_preshift = { {(BUS_WIDTH-DATA_WIDTH){1'b0}}, pre_shift }; - - shifted_data = wide_preshift >> (8*i_addr[2-1:0]); - end else begin - wide_preshift = { pre_shift, - {(BUS_WIDTH-DATA_WIDTH){1'b0}} }; - - shifted_data = wide_preshift >> (8*i_addr[WBLSB-1:0]); - end - end - - initial o_wb_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && i_reset) - o_wb_data <= 0; - else if ((!o_busy || !i_wb_stall) - && (!OPT_LOWPOWER || (i_pipe_stb && i_op[0]))) - begin - if (!OPT_LOWPOWER) - begin - casez(i_op[2:1]) - 2'b0?: o_wb_data <= {(BUS_WIDTH/DATA_WIDTH){i_data}}; - 2'b10: o_wb_data <= {(BUS_WIDTH/16){i_data[15:0]}}; - 2'b11: o_wb_data <= {(BUS_WIDTH/ 8){i_data[ 7:0]}}; - endcase - end else begin - o_wb_data <= shifted_data; - end - end else if (OPT_LOWPOWER && !i_wb_stall) - o_wb_data <= 0; - // }}} - end endgenerate - // }}} - - // Register return FIFO - // {{{ - generate if (OPT_PIPE) - begin : OPT_PIPE_FIFO - // {{{ - reg [FIF_WIDTH-1:0] fifo_data [0:((1<= rdaddr)) - f_valid_fifo_entry[gk] = 1'b1; - else if ((rdaddr > wraddr)&&(gk >= rdaddr)) - f_valid_fifo_entry[gk] = 1'b1; - else if ((rdaddr > wraddr)&&(gk < wraddr)) - f_valid_fifo_entry[gk] = 1'b1; - end - -`ifdef INSPECT_FIFO - wire [FIF_WIDTH-1:0] fifo_data_k; - - assign fifo_data_k = fifo_data[gk[DP-1:0]]; - - always @(*) - if (f_valid_fifo_entry[gk]) - begin - if (!f_pc_pending) - begin - `ASSERT((o_wb_we)||(fifo_data_k[1+2+WBLSB +: 3] != 3'h7)); - end else if (gk != f_last_wraddr) - `ASSERT(fifo_data_k[1+2+WBLSB +: 3] != 3'h7); - end -`endif // INSPECT_FIFO - - end - -`ifndef INSPECT_FIFO - always @(posedge i_clk) - if ((r_rd_pending)&&(rdaddr[DP:0] != f_last_wraddr[DP-1])) - assume(req_data[1+2+WBLSB +: 3] != 3'h7); -`endif // INSPECT_FIFO - - // - // - // - always @(*) - begin - f_pending_addr[AW-1:0] = f_fifo_addr[rdaddr]; - f_pending_addr[AW] = r_wb_cyc_lcl; - end - - // - // - // - always @(posedge i_clk) - if (i_pipe_stb) - begin - if (OPT_LOCAL_BUS && (&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - f_fifo_addr[wraddr[DP-1:0]] <= { 1'b1, i_addr[2 +: AW] }; - else - f_fifo_addr[wraddr[DP-1:0]] <= { 1'b0, i_addr[WBLSB +: AW] }; - end - - always @(*) - begin - f_return_address[AW] = (o_wb_cyc_lcl); - f_return_address[AW-1:0] = f_fifo_addr[rdaddr]; - if (state == DC_READC) - f_return_address[LS-1:0] - = (o_wb_addr[LS-1:0] - f_outstanding[LS-1:0]); - end - -`define TWIN_WRITE_TEST -`ifdef TWIN_WRITE_TEST - reg [DP:0] f_twin_next; - // Verilator lint_off UNDRIVEN - (* anyconst *) reg [DP:0] f_twin_base; - (* anyconst *) reg [AW+FIF_WIDTH-1:0] f_twin_first, - f_twin_second; - // Verilator lint_on UNDRIVEN - reg f_twin_none, f_twin_single, f_twin_double, f_twin_last; - reg f_twin_valid_one, f_twin_valid_two; - - always @(*) - f_twin_next = f_twin_base+1; - - always @(*) - begin - f_twin_valid_one = ((f_valid_fifo_entry[f_twin_base]) - &&(f_twin_first == { f_fifo_addr[f_twin_base[DP-1:0]], - fifo_data[f_twin_base[DP-1:0]] })); - f_twin_valid_two = ((f_valid_fifo_entry[f_twin_next]) - &&(f_twin_second == { f_fifo_addr[f_twin_next[DP-1:0]], - fifo_data[f_twin_next[DP-1:0]] })); - end - - always @(*) - begin - f_twin_none =(!f_twin_valid_one)&&(!f_twin_valid_two); - f_twin_single =( f_twin_valid_one)&&(!f_twin_valid_two); - f_twin_double =( f_twin_valid_one)&&( f_twin_valid_two); - f_twin_last =(!f_twin_valid_one)&&( f_twin_valid_two); - end - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))||($past(cyc && i_wb_err))) - begin - `ASSERT(f_twin_none); - end else if ($past(f_twin_none)) - begin - `ASSERT(f_twin_none || f_twin_single || f_twin_last); - end else if ($past(f_twin_single)) - begin - `ASSERT(f_twin_none || f_twin_single || f_twin_double || f_twin_last); - end else if ($past(f_twin_double)) - begin - `ASSERT(f_twin_double || f_twin_last); - end else if ($past(f_twin_last)) - `ASSERT(f_twin_none || f_twin_single || f_twin_last); - - // f_addr_reg test - // {{{ - always @(*) - if (o_rdbusy) - begin - if (f_twin_valid_one && f_twin_base != f_last_wraddr) - `ASSERT({ gie, f_twin_first[2+WBLSB +: 4] } != f_addr_reg); - if (f_twin_valid_two && f_twin_next != f_last_wraddr) - `ASSERT({ gie, f_twin_second[2+WBLSB +: 4] } != f_addr_reg); - if ((rdaddr != f_last_wraddr)&&(rdaddr != f_twin_base) - &&(rdaddr != f_twin_next)) - assume({ gie, req_data[2+WBLSB +: 4] } != f_addr_reg); - end - // }}} - -`endif // TWIN_WRITE_TEST - - always @(*) - `ASSERT(req_data == { gie, fifo_data[rdaddr[DP-1:0]] }); - - always @(posedge i_clk) - if (r_svalid||r_dvalid || r_rd_pending) - begin - `ASSERT(f_fill == 1); - end else if (f_fill > 0) - begin - `ASSERT(cyc); - end - - always @(posedge i_clk) - if (state != 0) - begin - `ASSERT(f_fill > 0); - end else if (!r_svalid && !r_dvalid && !r_rd_pending) - `ASSERT(f_fill == 0); - -`endif // FORMAL - - always @(posedge i_clk) - o_wreg <= req_data[2+WBLSB +: NAUX]; - // }}} - end else begin : NO_FIFO - // {{{ - reg [AW-1:0] fr_last_addr; - - always @(posedge i_clk) - if (i_pipe_stb) - req_data <= { i_oreg, i_op[2:1], i_addr[WBLSB-1:0] }; - - always @(*) - o_wreg = req_data[2+WBLSB +: NAUX]; - - always @(*) - gie = o_wreg[NAUX-1]; - -`ifdef FORMAL - // f_pc_pending - // {{{ - always @(*) - begin - f_pc_pending = 0; - if ((r_rd_pending || state == DC_READS)||(o_valid)) - f_pc_pending = (o_wreg[3:1] == 3'h7); - end - // }}} - - // f_pending_addr - // {{{ - initial f_pending_addr = 0; - always @(posedge i_clk) - if (i_reset) - f_pending_addr <= 0; - else if (i_pipe_stb) - begin - if ((OPT_LOCAL_BUS)&&(&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - f_pending_addr <= { 1'b1, i_addr[2 +: AW] }; - else - f_pending_addr <= { 1'b0, i_addr[WBLSB +: AW] }; - end - // }}} - - // f_return_address - // {{{ - always @(posedge i_clk) - if (stb) - fr_last_addr <= o_wb_addr; - - always @(*) - begin - f_return_address[AW] = o_wb_cyc_lcl; - f_return_address[AW-1:LS] = o_wb_addr[AW-1:LS]; - if (OPT_LOWPOWER && !stb) - f_return_address[AW-1:LS] = fr_last_addr[AW-1:LS]; - end - always @(*) - if (state == DC_READS) - begin - f_return_address[LS-1:0] = o_wb_addr[LS-1:0]; - if (OPT_LOWPOWER && !stb) - f_return_address[LS-1:0] = fr_last_addr[LS-1:0]; - end else begin - f_return_address[LS-1:0] - = (o_wb_addr[LS-1:0] - f_outstanding[LS-1:0]); - if (OPT_LOWPOWER && !stb) - f_return_address[LS-1:0] = (fr_last_addr[LS-1:0] - f_outstanding[LS-1:0]); - end - // }}} - - // f_last_reg - // {{{ - always @(*) - if (o_rdbusy) - assert(o_wreg == f_last_reg); - // }}} - // verilator lint_off UNUSED - initial f_fill = 0; - - wire unused_no_fifo_formal; - assign unused_no_fifo_formal = &{ 1'b0, f_return_address, - f_addr_reg, f_fill }; -`endif - wire unused_no_fifo; - assign unused_no_fifo = &{ 1'b0, gie }; - // verilator lint_on UNUSED - // }}} - end endgenerate - // }}} - - // BIG STATE machine: CYC, STB, c_v, state, etc - // {{{ - initial o_wb_addr = 0; - initial r_wb_cyc_gbl = 0; - initial r_wb_cyc_lcl = 0; - initial o_wb_stb_gbl = 0; - initial o_wb_stb_lcl = 0; - initial c_v = 0; - initial cyc = 0; - initial stb = 0; - initial c_wr = 0; - initial wr_cstb = 0; - initial state = DC_IDLE; - initial set_vflag = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - c_v <= 0; - c_wr <= 1'b0; - c_wsel <= {(BUS_WIDTH/8){1'b1}}; - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - o_wb_stb_gbl <= 0; - o_wb_stb_lcl <= 0; - o_wb_addr <= 0; - wr_cstb <= 1'b0; - last_line_stb <= 1'b0; - end_of_line <= 1'b0; - state <= DC_IDLE; - cyc <= 1'b0; - stb <= 1'b0; - state <= DC_IDLE; - set_vflag <= 1'b0; - // }}} - end else begin - // By default, update the cache from the write 1-clock ago - // c_wr <= (wr_cstb)&&(wr_wtag == wr_vtag); - // c_waddr <= wr_addr[(CS-1):0]; - c_wr <= 0; - - set_vflag <= 1'b0; - if (!cyc && set_vflag) - c_v[c_waddr[(CS-1):LS]] <= 1'b1; - - wr_cstb <= 1'b0; - - // end_of_line - // {{{ - // Verilator coverage_off - if (LS <= 0) - end_of_line <= 1'b1; - // Verilator coverage_on - else if (!cyc) - end_of_line <= 1'b0; - else if (!end_of_line) - begin - if (i_wb_ack) - end_of_line - <= (c_waddr[(LS-1):0] == {{(LS-2){1'b1}},2'b01}); - else - end_of_line - <= (c_waddr[(LS-1):0]=={{(LS-1){1'b1}}, 1'b0}); - end - // }}} - - // last_line_stb - // {{{ - if (!cyc || !stb || (OPT_LOWPOWER && state != DC_READC)) - last_line_stb <= (LS <= 0); - // Verilator coverage_off - else if (!i_wb_stall && (LS <= 1)) - last_line_stb <= 1'b1; - // Verilator coverage_on - else if (!i_wb_stall) - last_line_stb <= (o_wb_addr[(LS-1):1]=={(LS-1){1'b1}}); - else - last_line_stb <= (o_wb_addr[(LS-1):0]=={(LS){1'b1}}); - // }}} - - // - // - case(state) - DC_IDLE: begin - // {{{ - o_wb_we <= 1'b0; - - cyc <= 1'b0; - stb <= 1'b0; - - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - - in_cache <= (i_op[0])&&(w_cachable); - if ((i_pipe_stb)&&(i_op[0])) - begin // Write operation - // {{{ - state <= DC_WRITE; - if (OPT_LOCAL_BUS && (&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - o_wb_addr <= i_addr[2 +: AW]; - else - o_wb_addr <= i_addr[WBLSB +: AW]; - - o_wb_we <= 1'b1; - - cyc <= 1'b1; - stb <= 1'b1; - - if (OPT_LOCAL_BUS) - begin - r_wb_cyc_gbl <= (i_addr[DATA_WIDTH-1:DATA_WIDTH-8]!=8'hff); - r_wb_cyc_lcl <= (i_addr[DATA_WIDTH-1:DATA_WIDTH-8]==8'hff); - o_wb_stb_gbl <= (i_addr[DATA_WIDTH-1:DATA_WIDTH-8]!=8'hff); - o_wb_stb_lcl <= (i_addr[DATA_WIDTH-1:DATA_WIDTH-8]==8'hff); - end else begin - r_wb_cyc_gbl <= 1'b1; - o_wb_stb_gbl <= 1'b1; - end - // }}} - end else if (r_cache_miss) - begin // Cache miss - state <= DC_READC; - o_wb_addr <= { r_ctag, {(LS){1'b0}} }; - - c_waddr <= { r_ctag[CS-LS-1:0], {(LS){1'b0}} }-1'b1; - cyc <= 1'b1; - stb <= 1'b1; - r_wb_cyc_gbl <= 1'b1; - o_wb_stb_gbl <= 1'b1; - end else if ((i_pipe_stb)&&(!w_cachable)) - begin // Read non-cachable memory area - state <= DC_READS; - - if (OPT_LOCAL_BUS && (&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - o_wb_addr <= i_addr[2 +: AW]; - else - o_wb_addr <= i_addr[WBLSB +: AW]; - - cyc <= 1'b1; - stb <= 1'b1; - if (OPT_LOCAL_BUS) - begin - r_wb_cyc_gbl <= (i_addr[DATA_WIDTH-1:DATA_WIDTH-8]!=8'hff); - r_wb_cyc_lcl <= (i_addr[DATA_WIDTH-1:DATA_WIDTH-8]==8'hff); - o_wb_stb_gbl <= (i_addr[DATA_WIDTH-1:DATA_WIDTH-8]!=8'hff); - o_wb_stb_lcl <= (i_addr[DATA_WIDTH-1:DATA_WIDTH-8]==8'hff); - end else begin - r_wb_cyc_gbl <= 1'b1; - o_wb_stb_gbl <= 1'b1; - end - end // else we stay idle - end - // }}} - DC_READC: begin - // {{{ - // We enter here once we have committed to reading - // data into a cache line. - if (stb && !i_wb_stall) - begin - stb <= (!last_line_stb); - o_wb_stb_gbl <= (!last_line_stb); - o_wb_addr[(LS-1):0] <= o_wb_addr[(LS-1):0]+1'b1; - - if (OPT_LOWPOWER && last_line_stb) - o_wb_addr <= 0; - end - - if (i_wb_ack) - c_v[r_cline] <= 1'b0; - - c_wr <= (i_wb_ack); - c_wdata <= i_wb_data; - c_waddr <= c_waddr+(i_wb_ack ? 1:0); - c_wsel <= {(BUS_WIDTH/8){1'b1}}; - - set_vflag <= !i_wb_err; - // if (i_wb_ack) - // c_vtags[r_addr[(CS-1):LS]] - // <= r_addr[(AW-1):LS]; - - if ((i_wb_ack && end_of_line)|| i_wb_err) - begin - state <= DC_IDLE; - cyc <= 1'b0; - stb <= 1'b0; - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - // - if (OPT_LOWPOWER) - o_wb_addr <= 0; - end end - // }}} - DC_READS: begin - // {{{ - // We enter here once we have committed to reading - // data that cannot go into a cache line - if ((!i_wb_stall)&&(!i_pipe_stb)) - begin - stb <= 1'b0; - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - if (OPT_LOWPOWER) - o_wb_addr <= 0; - end - - if ((!i_wb_stall)&&(i_pipe_stb)) - begin - if (OPT_LOCAL_BUS && (&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - o_wb_addr <= i_addr[2 +: AW]; - else - o_wb_addr <= i_addr[WBLSB +: AW]; - end - - c_wr <= 1'b0; - - if (((i_wb_ack)&&(last_ack))||(i_wb_err)) - begin - state <= DC_IDLE; - cyc <= 1'b0; - stb <= 1'b0; - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - if (OPT_LOWPOWER) - o_wb_addr <= 0; - end end - // }}} - DC_WRITE: begin - // {{{ - c_wr <= o_wb_stb_gbl && (c_v[o_wb_addr[CS-1:LS]]) - // &&(c_vtags[o_wb_addr[CS-1:LS]]==o_wb_addr[AW-1:LS]); - &&(r_itag==o_wb_addr[AW-1:LS]); - c_wdata <= o_wb_data; - c_waddr <= r_addr[CS-1:0]; - c_wsel <= o_wb_sel; - - if ((!i_wb_stall)&&(!i_pipe_stb)) - begin - stb <= 1'b0; - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - if (OPT_LOWPOWER) - o_wb_addr <= 0; - end - - wr_cstb <= (stb)&&(!i_wb_stall)&&(in_cache); - - if (i_pipe_stb && !i_wb_stall) - begin - if (OPT_LOCAL_BUS && (&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - o_wb_addr <= i_addr[2 +: AW]; - else - o_wb_addr <= i_addr[WBLSB +: AW]; - end - - if (((i_wb_ack)&&(last_ack) - &&((!OPT_PIPE)||(!i_pipe_stb))) - ||(i_wb_err)) - begin - state <= DC_IDLE; - cyc <= 1'b0; - stb <= 1'b0; - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - if (OPT_LOWPOWER) - o_wb_addr <= 0; - end end - // }}} - endcase - - if (i_clear) - c_v <= 0; - end - - always @(posedge i_clk) - if (state == DC_READC && i_wb_ack) - c_vtags[r_addr[(CS-1):LS]] <= r_addr[(AW-1):LS]; - // }}} - - // wr_addr - // {{{ - always @(posedge i_clk) - if (!cyc) - begin - wr_addr <= r_addr[(CS-1):0]; - if ((!i_pipe_stb || !i_op[0])&&(r_cache_miss)) - wr_addr[LS-1:0] <= 0; - end else if (i_wb_ack) - wr_addr <= wr_addr + 1'b1; - else - wr_addr <= wr_addr; - // }}} - - - // npending - // {{{ - // npending is the number of outstanding (non-cached) read or write - // requests. We only keep track of npending if we are running in a - // piped fashion, i.e. if OPT_PIPE, and so need to keep track of - // possibly multiple outstanding transactions - initial npending = 0; - always @(posedge i_clk) - if ((i_reset)||(!OPT_PIPE) - ||((cyc)&&(i_wb_err)) - ||((!cyc)&&(!i_pipe_stb)) - ||(state == DC_READC)) - npending <= 0; - else if (r_svalid) - npending <= (i_pipe_stb) ? 1:0; - else case({ (i_pipe_stb), (cyc)&&(i_wb_ack) }) - 2'b01: npending <= npending - 1'b1; - 2'b10: npending <= npending + 1'b1; - default: begin end - endcase - -`ifdef FORMAL - always @(*) - `ASSERT(npending <= { 1'b1, {(DP){1'b0}} }); -`endif - // }}} - - // last_ack - // {{{ - initial last_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - last_ack <= 1'b0; - else if (state == DC_IDLE) - begin - last_ack <= 1'b0; - if ((i_pipe_stb)&&(i_op[0])) - last_ack <= 1'b1; - else if (r_cache_miss) - last_ack <= (LS == 0); - else if ((i_pipe_stb)&&(!w_cachable)) - last_ack <= 1'b1; - end else if (state == DC_READC) - begin - if (i_wb_ack) - last_ack <= last_ack || (&wr_addr[LS-1:1]); - else - last_ack <= last_ack || (&wr_addr[LS-1:0]); - end else case({ (i_pipe_stb), (i_wb_ack) }) - 2'b01: last_ack <= (npending <= 2); - 2'b10: last_ack <= (!cyc)||(npending == 0); - default: begin end - endcase - // }}} - - // - // Writes to the cache - // {{{ - // These have been made as simple as possible. Note that the c_wr - // line has already been determined, as have the write value and address - // on the last clock. Further, this structure is defined to match the - // block RAM design of as many architectures as possible. - // - always @(posedge i_clk) - if (c_wr) - begin - for(ik=0; ik BUS_WIDTH - 8)&&(OPT_LOCAL_BUS)) - begin : UPPER_CONST_ADDR_BITS - - always @(*) - if (f_const_addr[AW]) - begin - assume(&f_const_addr[AW-1:DATA_WIDTH-8-2]); - end else - assume(!(&f_const_addr[AW-1:DATA_WIDTH-8-WBLSB])); - - end endgenerate - // }}} - - // f_const_data -- Adjust our special data word upon request - // {{{ - reg [BUS_WIDTH-1:0] f_shifted_data; - reg [BUS_WIDTH/8-1:0] f_shifted_sel; - - always @(*) - begin - casez(i_op[2:1]) - 2'b0?: begin - f_shifted_data = { i_data, {(BUS_WIDTH-DATA_WIDTH){1'b0}} } >> (8*i_addr[WBLSB-1:0]); - f_shifted_sel = { 4'b1111, {(BUS_WIDTH/8-4){1'b0}} } >> i_addr[WBLSB-1:0]; - end - 2'b10: begin - f_shifted_data = { i_data[15:0], {(BUS_WIDTH-16){1'b0}} } >> (8*i_addr[WBLSB-1:0]); - f_shifted_sel = { 2'b11, {(BUS_WIDTH/8-2){1'b0}} } >> i_addr[WBLSB-1:0]; - end - 2'b11: begin - f_shifted_data = { i_data[ 7:0], {(BUS_WIDTH-8){1'b0}} } >> (8*i_addr[WBLSB-1:0]); - f_shifted_sel = { 1'b1, {(BUS_WIDTH/8-1){1'b0}} } >> i_addr[WBLSB-1:0]; - end - endcase - end - - always @(posedge i_clk) - // Upon a request for our special address ... - if (i_pipe_stb && (!cyc || !i_wb_err) - // That matches the local or global bus address.... - && f_const_addr[AW] == ((OPT_LOCAL_BUS) - &&(&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - // and it is a write request - && i_op[0]) - begin - // Then update the chosen data word at that address - if (f_const_addr[AW] - && (&i_addr[DATA_WIDTH-1:DATA_WIDTH-8]) - && (i_addr[2 +: AW] == f_const_addr[AW-1:0])) - begin // Local bus word - // {{{ - casez({ i_op[2:1], i_addr[1:0] }) - 4'b0???: f_const_data[31: 0] <= i_data; - 4'b100?: f_const_data[31:16] <= i_data[15:0]; - 4'b101?: f_const_data[15: 0] <= i_data[15:0]; - 4'b1100: f_const_data[31:24] <= i_data[ 7:0]; - 4'b1101: f_const_data[23:16] <= i_data[ 7:0]; - 4'b1110: f_const_data[15: 8] <= i_data[ 7:0]; - 4'b1111: f_const_data[ 7: 0] <= i_data[ 7:0]; - endcase - // }}} - end else if (!f_const_addr[AW] - && (!OPT_LOCAL_BUS - || !(&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])) - && (i_addr[WBLSB +: AW] == f_const_addr[AW-1:0])) - begin // Global bus word - for(ik=0; ik f_const_addr[LS-1:0])) - begin - // We are reading the cache line containing our - // constant address f_const_addr. Make sure the data - // is correct. - if ((c_wr)&&(c_waddr[CS-1:0] == f_const_addr[CS-1:0])) - begin - `ASSERT(c_wdata == f_const_data); - end else - `ASSERT(f_cmem_here == f_const_data); - end - - if (!i_reset && f_nacks > 0) - `ASSERT(!c_v[r_cline]); - end - // }}} - - always @(posedge i_clk) - if ((state == DC_READC)&&(f_nacks > 0)) - begin - `ASSERT(c_vtags[wb_start[(CS-1):LS]] <= wb_start[(AW-1):LS]); - `ASSERT(c_vtags[wb_start[(CS-1):LS]] <= r_addr[AW-1:LS]); - end - - always @(*) - begin - // f_cache_waddr[AW-1:LS] = c_vtags[c_waddr[CS-1:CS-LS]]; - f_cache_waddr[AW-1:LS] = wb_start[AW-1:LS]; - f_cache_waddr[CS-1: 0] = c_waddr[CS-1:0]; - end - - - always @(posedge i_clk) - if ((f_past_valid)&&(state == DC_READC)) - begin - if ((c_wr)&&(c_waddr[LS-1:0] != 0)&&(f_this_cache_waddr)) - `ASSERT(c_wdata == f_const_data); - end - -// always @(posedge i_clk) -// if ((OPT_PIPE)&&(o_busy)&&(i_pipe_stb)) -// `ASSUME(i_op[0] == o_wb_we); - - initial f_pending_rd = 0; - always @(posedge i_clk) - if (i_reset) - f_pending_rd <= 0; - else if (i_pipe_stb) - f_pending_rd <= (!i_op[0]); - else if ((o_valid)&&((!OPT_PIPE) - ||((state != DC_READS)&&(!r_svalid)&&(!$past(i_pipe_stb))))) - f_pending_rd <= 1'b0; - - always @(*) - if ((state == DC_READC)&&(!f_stb)) - `ASSERT(f_nreqs == (1< 0) - begin - `ASSERT(f_nacks-1 == { 1'b0, c_waddr[LS-1:0] }); - `ASSERT(c_waddr[CS-1:LS] == r_addr[CS-1:LS]); - end else begin - `ASSERT(c_waddr[CS-1:LS] == r_addr[CS-1:LS]-1'b1); - `ASSERT(&c_waddr[LS-1:0]); - end - end - - always @(*) - if (r_rd_pending) - `ASSERT(r_addr == f_pending_addr[AW-1:0]); - - always @(*) - if (f_pending_addr[AW]) - begin - `ASSERT(state != DC_READC); - `ASSERT((!o_wb_we)||(!o_wb_cyc_gbl)); - end - - reg [BUS_WIDTH-1:0] f_shift_const_data; - - always @(posedge i_clk) - begin - if (f_const_addr[AW]) - f_shift_const_data = { f_const_data[31:0], {(BUS_WIDTH-DATA_WIDTH){1'b0}} } << (8*req_data[2-1:0]); - else - f_shift_const_data = f_const_data << (8*req_data[WBLSB-1:0]); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(o_valid)&&($past(f_pending_addr) == f_const_addr)) - begin - if (f_const_buserr) - begin - `ASSERT(o_err); - end else if (f_pending_rd) - begin - casez($past(req_data[WBLSB +: 2])) - 4'b0?: `ASSERT(o_data ==f_shift_const_data[BUS_WIDTH-1:BUS_WIDTH-32]); - 4'b10: `ASSERT(o_data =={16'h00,f_shift_const_data[BUS_WIDTH-1:BUS_WIDTH-16]}); - 4'b11: `ASSERT(o_data =={24'h00,f_shift_const_data[BUS_WIDTH-1:BUS_WIDTH- 8]}); - endcase - end - end - - // #1. Assume this return matches our chosen data - // {{{ - always @(*) - if ((f_cyc)&&( - ((state == DC_READC) - &&(f_return_address[AW-1:LS] == f_const_addr[AW-1:LS])) - ||(f_this_return))) - begin - if (f_const_buserr) - begin - assume(!i_wb_ack); - end else begin - assume(!i_wb_err); - assume(i_wb_data == f_const_data); - end - end - // }}} - - always @(posedge i_clk) - if ((f_past_valid)&&(last_tag == f_const_tag)&&(f_const_buserr) - &&(!f_const_addr[AW])) - `ASSERT(!last_tag_valid); - - // Chosen address is invalid: bus error properties - // {{{ - always @(*) - if (f_const_buserr) - begin - `ASSERT((!c_v[f_const_tag_addr])||(f_const_addr[AW]) - ||(f_ctag_here != f_const_tag)); - - if ((state == DC_READC)&&(wb_start[AW-1:LS] == f_const_tag)) - begin - `ASSERT(f_nacks <= f_const_tag[LS-1:0]); - if (f_nacks == f_const_tag[LS-1:0]) - assume(!i_wb_ack); - end - end - // }}} - - /* - // ?? why was I assuming this again? - always @(*) - if (f_cval_in_cache) - begin - assume((!i_wb_err) - ||(!i_pipe_stb) - ||(f_const_addr[AW-1:0] != i_addr[WBLSB +: AW])); - end - */ - -`endif // DCACHE - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Checking the lock - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - `ASSERT((!lock_gbl)||(!lock_lcl)); - always @(*) - if (!OPT_LOCK) - `ASSERT((!lock_gbl)&&(!lock_lcl)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // State based properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg [F_LGDEPTH-1:0] f_rdpending; - wire f_wb_cachable; - - // f_rdpending - // {{{ - initial f_rdpending = 0; - always @(posedge i_clk) - if ((i_reset)||(o_err)) - f_rdpending <= 0; - else case({ (i_pipe_stb)&&(!i_op[0]), o_valid }) - 2'b01: f_rdpending <= f_rdpending - 1'b1; - 2'b10: f_rdpending <= f_rdpending + 1'b1; - default: begin end - endcase - // }}} - - iscachable #( - // {{{ - .ADDRESS_WIDTH(AW+WBLSB) - // }}} - ) f_chkwb_addr({ r_addr, {(WBLSB){1'b0}} }, f_wb_cachable); - - - always @(*) - if (state == DC_IDLE) - begin - `ASSERT(!r_wb_cyc_gbl); - `ASSERT(!r_wb_cyc_lcl); - - `ASSERT(!cyc); - - if ((r_rd_pending)||(r_dvalid)||(r_svalid)) - `ASSERT(o_busy); - - if (!OPT_PIPE) - begin - if (r_rd_pending) - begin - `ASSERT(o_busy); - end else if (r_svalid) - begin - `ASSERT(o_busy); - end else if (o_valid) - begin - `ASSERT(!o_busy); - end else if (o_err) - begin - `ASSERT(!o_busy); - end - end - end else begin - `ASSERT(o_busy); - `ASSERT(cyc); - end - - - - always @(posedge i_clk) - if (state == DC_IDLE) - begin - if (r_svalid) - begin - `ASSERT(!r_dvalid); - `ASSERT(!r_rd_pending); - if (!OPT_PIPE) - begin - `ASSERT(!o_valid); - end else if (o_valid) - `ASSERT(f_rdpending == 2); - end - - if (r_dvalid) - begin - `ASSERT(!r_rd_pending); - `ASSERT(npending == 0); - `ASSERT(f_rdpending == 1); - end - - if (r_rd_pending) - begin - if ((OPT_PIPE)&&(o_valid)) - begin - `ASSERT(f_rdpending <= 2); - end else - `ASSERT(f_rdpending == 1); - - end else if ((OPT_PIPE)&&(o_valid)&&($past(r_dvalid|r_svalid))) - begin - `ASSERT(f_rdpending <= 2); - end else - `ASSERT(f_rdpending <= 1); - end - - always @(posedge i_clk) - if (state == DC_READC) - begin - `ASSERT( o_wb_cyc_gbl); - `ASSERT(!o_wb_cyc_lcl); - `ASSERT(!o_wb_we); - `ASSERT(f_wb_cachable); - `ASSERT(!lock_gbl); - `ASSERT(!lock_lcl); - - `ASSERT(r_rd_pending); - `ASSERT(r_cachable); - if (($past(cyc))&&(!$past(o_wb_stb_gbl))) - begin - `ASSERT(!o_wb_stb_gbl); - end - - if ((OPT_PIPE)&&(o_valid)) - begin - `ASSERT(f_rdpending == 2); - end else - `ASSERT(f_rdpending == 1); - end - - always @(*) - if (state == DC_READS) - begin - `ASSERT(!o_wb_we); - - if (OPT_PIPE) - begin - if (o_valid) - begin - `ASSERT(({ 1'b0, f_rdpending } == npending + 1) - ||({ 1'b0, f_rdpending } == npending)); - end else - `ASSERT({ 1'b0, f_rdpending } == npending); - end - end else if (state == DC_WRITE) - `ASSERT(o_wb_we); - - always @(posedge i_clk) - if ((state == DC_READS)||(state == DC_WRITE)) - begin - `ASSERT(o_wb_we == (state == DC_WRITE)); - `ASSERT(!r_rd_pending); - if (o_wb_we) - `ASSERT(f_rdpending == 0); - - if (OPT_PIPE) - begin - casez({ $past(i_pipe_stb), f_stb }) - 2'b00: `ASSERT(npending == { 1'b0, f_outstanding}); - 2'b1?: `ASSERT(npending == { 1'b0, f_outstanding} + 1); - 2'b01: `ASSERT(npending == { 1'b0, f_outstanding} + 1); - endcase - - if (state == DC_WRITE) - `ASSERT(!o_valid); - end else - `ASSERT(f_outstanding <= 1); - end - - always @(*) - if (OPT_PIPE) - begin - `ASSERT(f_rdpending <= 2); - end else - `ASSERT(f_rdpending <= 1); - - always @(posedge i_clk) - if ((!OPT_PIPE)&&(o_valid)) - begin - `ASSERT(f_rdpending == 1); - end else if (o_valid) - `ASSERT(f_rdpending >= 1); - - - always @(*) - if ((!o_busy)&&(!o_err)&&(!o_valid)) - `ASSERT(f_rdpending == 0); - - always @(*) - `ASSERT(cyc == ((r_wb_cyc_gbl)||(r_wb_cyc_lcl))); - - always @(*) - if ((!i_reset)&&(f_nreqs == f_nacks)&&(!f_stb)) - `ASSERT(!cyc); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_err))) - begin - `ASSUME(!i_lock); - end else if ((f_past_valid)&&(OPT_LOCK)&&($past(i_lock)) - &&((!$past(o_valid)) || ($past(i_pipe_stb)))) - `ASSUME($stable(i_lock)); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Ad-hoc properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if ((OPT_PIPE)&&(state == DC_WRITE)&&(!i_wb_stall)&&(stb) - &&(!npending[DP])) - `ASSERT(!o_pipe_stalled); - - always @(posedge i_clk) - if (state == DC_WRITE) - begin - `ASSERT(o_wb_we); - end else if ((state == DC_READS)||(state == DC_READC)) - `ASSERT(!o_wb_we); - - always @(*) - if (cyc) - `ASSERT(f_cyc); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(cyc))&&(!c_wr)&&(last_tag_valid) - &&(!r_rd_pending)) - `ASSERT((c_v[last_tag[(CS-LS-1):0]]) - &&(c_vtags[last_tag[(CS-LS-1):0]] == last_tag)); - - always @(*) - if (!OPT_LOCAL_BUS) - begin - `ASSERT(r_wb_cyc_lcl == 1'b0); - `ASSERT(o_wb_stb_lcl == 1'b0); - `ASSERT(lock_lcl == 1'b0); - end - - always @(posedge i_clk) - if (state == DC_READC && !stb) - begin - if (OPT_LOWPOWER) - begin - `ASSERT(o_wb_addr == 0); - end else begin - `ASSERT(o_wb_addr[LS-1:0] == 0); - `ASSERT(o_wb_addr[AW-1:CS] == r_addr[AW-1:CS]); - end - end else if ((state == DC_READC)&&(stb)) - begin - `ASSERT(o_wb_addr[AW-1:CS] == r_addr[AW-1:CS]); - `ASSERT(o_wb_addr[LS-1:0] == f_nreqs[LS-1:0]); - end - - wire [CS-1:0] f_expected_caddr; - assign f_expected_caddr = { r_ctag[CS-LS-1:0], {(LS){1'b0}} }-1 - + { {(CS-F_LGDEPTH){1'b0}}, f_nacks }; - always @(posedge i_clk) - if (state == DC_READC) - begin - if (LS == 0) - begin - `ASSERT(end_of_line); - end else if (f_nacks < (1< 1)) - begin - `ASSERT(cyc); - end else if (($past(f_outstanding == 1)) - &&((!$past(i_wb_ack)) - ||(($past(f_stb)) - &&(!$past(i_wb_stall))))) - begin - `ASSERT(cyc); - end else if (($past(f_outstanding == 0)) - &&($past(f_stb)&&(!$past(i_wb_ack)))) - `ASSERT(cyc); - end - - always @(posedge i_clk) - if ((OPT_PIPE)&&(f_past_valid)&&(!$past(i_reset))&&(state != DC_READC)) - begin - if ($past(cyc && i_wb_err)) - begin - `ASSERT(npending == 0); - end else if (($past(i_pipe_stb))||($past(i_wb_stall && stb))) - begin - `ASSERT((npending == f_outstanding+1) - ||(npending == f_outstanding+2)); - end else - `ASSERT(npending == { 1'b0, f_outstanding }); - end - - always @(posedge i_clk) - if ((OPT_PIPE)&&(state != DC_READC)&&(state != DC_IDLE)) - `ASSERT(last_ack == (npending <= 1)); - - always @(*) - `ASSERT(stb == f_stb); - - always @(*) - if (r_rd_pending) - `ASSERT(!r_svalid); - - always @(*) - if (o_err) - `ASSUME(!i_pipe_stb); - - always @(*) - if (last_tag_valid) - `ASSERT(|c_v); - - always @(posedge i_clk) - if (cyc &&(state == DC_READC)&&($past(f_nacks > 0))) - `ASSERT(!c_v[r_cline]); - - always @(*) - if (last_tag_valid) - begin - `ASSERT((!cyc)||(o_wb_we)||(state == DC_READS) - ||(o_wb_addr[AW-1:LS] != last_tag)); - end - - wire f_cachable_last_tag, f_cachable_r_addr; - - iscachable #(.ADDRESS_WIDTH(AW+WBLSB)) - fccheck_last_tag({last_tag, {(LS+WBLSB){1'b0}} }, - f_cachable_last_tag); - - iscachable #( - .ADDRESS_WIDTH(AW+WBLSB) - ) fccheck_r_cachable({ r_addr, {(WBLSB){1'b0}} }, f_cachable_r_addr); - - always @(*) - if ((r_cachable)&&(r_rd_pending)) - begin - `ASSERT(state != DC_WRITE); - // `ASSERT(state != DC_READS); - `ASSERT(f_cachable_r_addr); - if (cyc && (stb || !OPT_LOWPOWER)) - `ASSERT(o_wb_addr[AW-1:LS] == r_addr[AW-1:LS]); - end - - always @(*) - if (last_tag_valid) - begin - `ASSERT(f_cachable_last_tag); - `ASSERT(c_v[last_tag[CS-LS-1:0]]); - `ASSERT(c_vtags[last_tag[CS-LS-1:0]]==last_tag); - `ASSERT((state != DC_READC)||(last_tag != o_wb_addr[AW-1:LS])); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Low power checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - generate if (OPT_LOWPOWER) - begin : CHECK_LOWPOWER - always @(posedge i_clk) - if (!o_wb_stb_gbl && !o_wb_stb_lcl) - begin - assert($stable(o_wb_addr) || (o_wb_addr == 0)); - assert($stable(o_wb_data) || (o_wb_data == 0)); - assert($stable(o_wb_sel) || (o_wb_sel == 0) - || (&o_wb_sel)); - end - - always @(posedge i_clk) - if (!o_valid && !o_err) - begin - assert($stable(o_data) || (o_data == 0)); - end - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover statements - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - cover(o_valid); - - always @(posedge i_clk) - if (f_past_valid) - cover($past(r_svalid)); - - generate if (OPT_PIPE) - begin : PIPE_COVER - - wire recent_reset; - reg [2:0] recent_reset_sreg; - initial recent_reset_sreg = -1; - always @(posedge i_clk) - if (i_reset) - recent_reset_sreg <= -1; - else - recent_reset_sreg <= { recent_reset_sreg[1:0], 1'b0 }; - - assign recent_reset = (i_reset)||(|recent_reset_sreg); - - // - // - wire f_cvr_cread = (!recent_reset)&&(i_pipe_stb)&&(!i_op[0]) - &&(w_cachable); - - wire f_cvr_cwrite = (!recent_reset)&&(i_pipe_stb)&&(i_op[0]) - &&(!cache_miss_inow); - - wire f_cvr_writes = (!recent_reset)&&(i_pipe_stb)&&(i_op[0]) - &&(!w_cachable); - wire f_cvr_reads = (!recent_reset)&&(i_pipe_stb)&&(!i_op[0]) - &&(!w_cachable); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_valid))) - cover(o_valid); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_pipe_stb))) - cover(i_pipe_stb); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_valid))&&($past(o_valid,2))) - cover(o_valid); - - always @(posedge i_clk) - cover(($past(f_cvr_cread))&&(f_cvr_cread)); - - always @(posedge i_clk) - cover(($past(f_cvr_cwrite))&&(f_cvr_cwrite)); - - always @(posedge i_clk) - cover(($past(f_cvr_writes))&&(f_cvr_writes)); - - /* - * This cover statement will never pass. Why not? Because - * cache reads must be separated from non-cache reads. Hence, - * we can only allow a single non-cache read at a time, otherwise - * we'd bypass the cache read logic. - * - always @(posedge i_clk) - cover(($past(f_cvr_reads))&&(f_cvr_reads)); - */ - - // - // This is unrealistic, as it depends upon the Wishbone - // acknoledging the request on the same cycle - always @(posedge i_clk) - cover(($past(f_cvr_reads,2))&&(f_cvr_reads)); - - always @(posedge i_clk) - cover(($past(r_dvalid))&&(r_svalid)); - - // - // A minimum of one clock must separate two dvalid's. - // This option is rather difficult to cover, since it means - // we must first load two separate cache lines before - // this can even be tried. - always @(posedge i_clk) - cover(($past(r_dvalid,2))&&(r_dvalid)); - - // - // This is the optimal configuration we want: - // i_pipe_stb - // ##1 i_pipe_stb && r_svalid - // ##1 r_svalid && o_valid - // ##1 o_valid - // It proves that we can handle a 2 clock delay, but that - // we can also pipelin these cache accesses, so this - // 2-clock delay becomes a 1-clock delay between pipelined - // memory reads. - // - always @(posedge i_clk) - cover(($past(r_svalid))&&(r_svalid)); - - // - // While we'd never do this (it breaks the ZipCPU's pipeline - // rules), it's nice to know we could. - // i_pipe_stb && (!i_op[0]) // a read - // ##1 i_pipe_stb && (i_op[0]) && r_svalid // a write - // ##1 o_valid - always @(posedge i_clk) - cover(($past(r_svalid))&&(f_cvr_writes)); - - /* Unreachable - * - always @(posedge i_clk) - cover(($past(f_cvr_writes))&&(o_valid)); - - always @(posedge i_clk) - cover(($past(f_cvr_writes,2))&&(o_valid)); - - always @(posedge i_clk) - cover(($past(f_cvr_writes,3))&&(o_valid)); - - always @(posedge i_clk) - cover(($past(r_dvalid,3))&&(r_dvalid)); - - */ - - always @(posedge i_clk) - cover(($past(f_cvr_writes,4))&&(o_valid)); - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Carelesss assumption section - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // - // Can't jump from local to global mid lock - always @(*) - if((OPT_LOCK)&&(OPT_LOCAL_BUS)) - begin - if ((i_lock)&&(o_wb_cyc_gbl)&&(i_pipe_stb)) - begin - assume(!(&i_addr[(DATA_WIDTH-1):(DATA_WIDTH-8)])); - end else if ((i_lock)&&(o_wb_cyc_lcl)&&(i_pipe_stb)) - assume(&i_addr[(DATA_WIDTH-1):(DATA_WIDTH-8)]); - end - - always @(*) - if ((OPT_PIPE)&&(o_busy || i_lock)&&(!o_pipe_stalled)) - begin - if (i_pipe_stb) - assume((!OPT_LOCAL_BUS) - ||(f_pending_addr[AW]==(&i_addr[DATA_WIDTH-1:DATA_WIDTH-8]))); - end - - // If the bus is active, but we allow a second item in anyway 'cause - // we are piped, then assume that we don't cross from local to global - // buses - always @(posedge i_clk) - if ((OPT_PIPE)&&(o_busy)&&(i_pipe_stb)) - begin - `ASSUME(i_op[0] == o_wb_we); - if (o_wb_cyc_lcl) - begin - assume(&i_addr[DATA_WIDTH-1:DATA_WIDTH-8]); - end else - assume(!(&i_addr[DATA_WIDTH-1:DATA_WIDTH-8])); - end - - // Assume aligned accesses - always @(*) - if (i_pipe_stb) - casez(i_op[2:1]) - 2'b0?: assume(i_addr[1:0] == 2'b00); - 2'b10: assume(i_addr[ 0] == 1'b0); - 2'b11: begin end - endcase - - // always @(posedge i_clk) - // if ((f_past_valid)&&(!$past(cyc))&&(!cyc)) - // assume((!i_wb_err)&&(!i_wb_ack)); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/div.v b/delete_later/rtl/cpu/div.v deleted file mode 100644 index b746176..0000000 --- a/delete_later/rtl/cpu/div.v +++ /dev/null @@ -1,611 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: div.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Provide an Integer divide capability to the Zip CPU. Provides -// for both signed and unsigned divide. -// -// Steps: -// i_reset The DIVide unit starts in idle. It can also be placed into an -// idle by asserting the reset input. -// -// i_wr When i_reset is asserted, a divide begins. On the next clock: -// -// o_busy is set high so everyone else knows we are at work and they can -// wait for us to complete. -// -// pre_sign is set to true if we need to do a signed divide. In this -// case, we take a clock cycle to turn the divide into an unsigned -// divide. -// -// o_quotient, a place to store our result, is initialized to all zeros. -// -// r_dividend is set to the numerator -// -// r_divisor is set to 2^31 * the denominator (shift left by 31, or add -// 31 zeros to the right of the number. -// -// pre_sign When true (clock cycle after i_wr), a clock cycle is used -// to take the absolute value of the various arguments (r_dividend -// and r_divisor), and to calculate what sign the output result -// should be. -// -// -// At this point, the divide is has started. The divide works by walking -// through every shift of the -// -// DIVIDEND over the -// DIVISOR -// -// If the DIVISOR is bigger than the dividend, the divisor is shifted -// right, and nothing is done to the output quotient. -// -// DIVIDEND -// DIVISOR -// -// This repeats, until DIVISOR is less than or equal to the divident, as in -// -// DIVIDEND -// DIVISOR -// -// At this point, if the DIVISOR is less than the dividend, the -// divisor is subtracted from the dividend, and the DIVISOR is again -// shifted to the right. Further, a '1' bit gets set in the output -// quotient. -// -// Once we've done this for 32 clocks, we've accumulated our answer into -// the output quotient, and we can proceed to the next step. If the -// result will be signed, the next step negates the quotient, otherwise -// it returns the result. -// -// On the clock when we are done, o_busy is set to false, and o_valid set -// to true. (It is a violation of the ZipCPU internal protocol for both -// busy and valid to ever be true on the same clock. It is also a -// violation for busy to be false with valid true thereafter.) -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module div #( - parameter BW=32, LGBW = 5, - parameter [0:0] OPT_LOWPOWER = 1'b0 - ) ( - // {{{ - input wire i_clk, i_reset, - // Input parameters - input wire i_wr, i_signed, - input wire [(BW-1):0] i_numerator, i_denominator, - // Output parameters - output reg o_busy, o_valid, o_err, - output reg [(BW-1):0] o_quotient, - output wire [3:0] o_flags - // }}} - ); - - // Local declarations - // {{{ - // r_busy is an internal busy register. It will clear one clock - // before we are valid, so it can't be o_busy ... - // - reg r_busy; - reg [BW-1:0] r_divisor; - reg [(2*BW-2):0] r_dividend; - wire [(BW):0] diff; // , xdiff[(BW-1):0]; - assign diff = r_dividend[2*BW-2:BW-1] - r_divisor; - - reg r_sign, pre_sign, r_z, r_c, last_bit; - reg [(LGBW-1):0] r_bit; - reg zero_divisor; - wire w_n; - // }}} - - // r_busy - // {{{ - // The Divide logic begins with r_busy. We use r_busy to determine - // whether or not the divide is in progress, vs being complete. - // Here, we clear r_busy on any reset and set it on i_wr (the request - // to do a divide). The divide ends when we are on the last bit, - // or equivalently when we discover we are dividing by zero. - initial r_busy = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_busy <= 1'b0; - else if (i_wr) - r_busy <= 1'b1; - else if ((last_bit)||(zero_divisor)) - r_busy <= 1'b0; - // }}} - - // o_busy - // {{{ - // o_busy is very similar to r_busy, save for some key differences. - // Primary among them is that o_busy needs to (possibly) be true - // for an extra clock after r_busy clears. This would be that extra - // clock where we negate the result (assuming a signed divide, and that - // the result is supposed to be negative.) Otherwise, the two are - // identical. - initial o_busy = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_busy <= 1'b0; - else if (i_wr) - o_busy <= 1'b1; - else if (((last_bit)&&(!r_sign))||(zero_divisor)) - o_busy <= 1'b0; - else if (!r_busy) - o_busy <= 1'b0; - // }}} - - // zero_divisor - // {{{ - always @(posedge i_clk) - if (i_wr) - zero_divisor <= (i_denominator == 0); - // }}} - - // o_valid - // {{{ - // o_valid is part of the ZipCPU protocol. It will be set to true - // anytime our answer is valid and may be used by the calling module. - // Indeed, the ZipCPU will halt (and ignore us) once the i_wr has been - // set until o_valid gets set. - // - // Here, we clear o_valid on a reset, and any time we are on the last - // bit while busy (provided the sign is zero, or we are dividing by - // zero). Since o_valid is self-clearing, we don't need to clear - // it on an i_wr signal. - initial o_valid = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(o_valid)) - o_valid <= 1'b0; - else if ((r_busy)&&(zero_divisor)) - o_valid <= 1'b1; - else if (r_busy) - begin - if (last_bit) - o_valid <= (!r_sign); - end else if (r_sign) - begin - o_valid <= 1'b1; - end else - o_valid <= 1'b0; - // }}} - - // o_err - // {{{ - // Division by zero error reporting. Anytime we detect a zero divisor, - // we set our output error, and then hold it until we are valid and - // everything clears. - initial o_err = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_err <= 1'b0; - else if ((r_busy)&&(zero_divisor)) - o_err <= 1'b1; - else - o_err <= 1'b0; - // }}} - - // r_bit - // {{{ - // Keep track of which "bit" of our divide we are on. This number - // ranges from 31 down to zero. On any write, we set ourselves to - // 5'h1f. Otherwise, while we are busy (but not within the pre-sign - // adjustment stage), we subtract one from our value on every clock. - initial r_bit = 0; - always @(posedge i_clk) - if (i_reset) - r_bit <= 0; - else if ((r_busy)&&(!pre_sign)) - r_bit <= r_bit + 1'b1; - else - r_bit <= 0; - // }}} - - // last_bit - // {{{ - // This logic replaces a lot of logic that was inside our giant state - // machine with ... something simpler. In particular, we'll use this - // logic to determine if we are processing our last bit. The only trick - // is, this bit needs to be set whenever (r_busy) and (r_bit == -1), - // hence we need to set on (r_busy) and (r_bit == -2) so as to be set - // when (r_bit == 0). - initial last_bit = 1'b0; - always @(posedge i_clk) - if (i_reset) - last_bit <= 1'b0; - else if (r_busy) - last_bit <= (r_bit == {(LGBW){1'b1}}-1'b1); - else - last_bit <= 1'b0; - // }}} - - // pre_sign - // {{{ - // This is part of the state machine. pre_sign indicates that we need - // a extra clock to take the absolute value of our inputs. It need only - // be true for the one clock, and then it must clear itself. - initial pre_sign = 1'b0; - always @(posedge i_clk) - if (i_reset) - pre_sign <= 1'b0; - else - pre_sign <= (i_wr)&&(i_signed)&&((i_numerator[BW-1])||(i_denominator[BW-1])); - // }}} - - // r_z - // {{{ - // As a result of our operation, we need to set the flags. The most - // difficult of these is the "Z" flag indicating that the result is - // zero. Here, we'll use the same logic that sets the low-order - // bit to clear our zero flag, and leave the zero flag set in all - // other cases. - always @(posedge i_clk) - if (i_wr) - r_z <= 1'b1; - else if ((r_busy)&&(!pre_sign)&&(!diff[BW])) - r_z <= 1'b0; - // }}} - - // r_dividend - // {{{ - // This is initially the numerator. On a signed divide, it then becomes - // the absolute value of the numerator. We'll subtract from this value - // the divisor for every output bit we are looking for--just as with - // traditional long division. - always @(posedge i_clk) - if (pre_sign) - begin - // If we are doing a signed divide, then take the - // absolute value of the dividend - if (r_dividend[BW-1]) - begin - r_dividend[2*BW-2:0] <= {(2*BW-1){1'b0}}; - r_dividend[BW:0] <= -{ 1'b1, r_dividend[BW-1:0] }; - end - end else if (r_busy) - begin - r_dividend <= { r_dividend[2*BW-3:0], 1'b0 }; - if (!diff[BW]) - r_dividend[2*BW-2:BW] <= diff[(BW-2):0]; - end else if (!r_busy && (!OPT_LOWPOWER || i_wr)) - // Once we are done, and r_busy is no longer high, we'll - // always accept new values into our dividend. This - // guarantees that, when i_wr is set, the new value - // is already set as desired. - r_dividend <= { 31'h0, i_numerator }; - // }}} - - // r_divisor - // {{{ - initial r_divisor = 0; - always @(posedge i_clk) - if (i_reset) - r_divisor <= 0; - else if ((pre_sign)&&(r_busy)) - begin - if (r_divisor[BW-1]) - r_divisor <= -r_divisor; - end else if (!r_busy && (!OPT_LOWPOWER || i_wr)) - r_divisor <= i_denominator; - // }}} - - // r_sign - // {{{ - // is a flag for our state machine control(s). r_sign will be set to - // true any time we are doing a signed divide and the result must be - // negative. In that case, we take a final logic stage at the end of - // the divide to negate the output. This flag is what tells us we need - // to do that. r_busy will be true during the divide, then when r_busy - // goes low, r_sign will be checked, then the idle/reset stage will have - // been reached. For this reason, we cannot set r_sign unless we are - // up to something. - initial r_sign = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_sign <= 1'b0; - else if (pre_sign) - r_sign <= ((r_divisor[(BW-1)])^(r_dividend[(BW-1)])); - else if (r_busy) - r_sign <= (r_sign)&&(!zero_divisor); - else - r_sign <= 1'b0; - // }}} - - // o_quotient - // {{{ - initial o_quotient = 0; - always @(posedge i_clk) - if (i_reset) - o_quotient <= 0; - else if (r_busy) - begin - o_quotient <= { o_quotient[(BW-2):0], 1'b0 }; - if (!diff[BW]) - o_quotient[0] <= 1'b1; - end else if (r_sign) - o_quotient <= -o_quotient; - else - o_quotient <= 0; - // }}} - - // r_c - // {{{ - // Set Carry on an exact divide - // Perhaps nothing uses this, but ... well, I suppose we could remove - // this logic eventually, just ... not yet. - initial r_c = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_c <= 1'b0; - else - r_c <= (r_busy)&&(diff == 0); - // }}} - - // w_n - // {{{ - // The last flag: Negative. This flag is set assuming that the result - // of the divide was negative (i.e., the high order bit is set). This - // will also be true of an unsigned divide--if the high order bit is - // ever set upon completion. Indeed, you might argue that there's no - // logic involved. - assign w_n = o_quotient[(BW-1)]; - // }}} - - assign o_flags = { 1'b0, w_n, r_c, r_z }; -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - -`ifdef DIV -`define ASSUME assume -`else -`define ASSUME assert -`endif - - initial `ASSUME(i_reset); - always @(*) - if (!f_past_valid) - `ASSUME(i_reset); - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))) - begin - assert(!o_busy); - assert(!o_valid); - assert(!o_err); - // - assert(!r_busy); - // assert(!zero_divisor); - assert(r_bit==0); - assert(!last_bit); - assert(!pre_sign); - // assert(!r_z); - // assert(r_dividend==0); - assert(o_quotient==0); - assert(!r_c); - assert(r_divisor==0); - - `ASSUME(!i_wr); - end - - always @(*) - if (o_busy) - `ASSUME(!i_wr); - - always @(*) - if (r_busy) - assert(o_busy); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(o_busy))&&(!o_busy)) - begin - assert(o_valid); - end - - // A formal methods section - // - // This section isn't yet complete. For now, it is just - // a description of things I think should be in here ... not - // yet a description of what it would take to prove - // this divide (yet). - always @(*) - if (o_err) - assert(o_valid); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_wr))) - assert(!pre_sign); - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr))&&($past(i_signed)) - &&(|$past({i_numerator[BW-1],i_denominator[BW-1]}))) - assert(pre_sign); - - // always @(posedge i_clk) - // if ((f_past_valid)&&(!$past(pre_sign))) - // assert(!r_sign); - reg [BW:0] f_bits_set; - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wr))) - assert(o_busy); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_valid))) - assert(!o_valid); - - always @(*) - if ((o_valid)&&(!o_err)) - begin - assert(r_z == ((o_quotient == 0)? 1'b1:1'b0)); - end else if (o_busy) - assert(r_z == (((o_quotient&f_bits_set[BW-1:0]) == 0)? 1'b1: 1'b0)); - - always @(*) - if ((o_valid)&&(!o_err)) - assert(w_n == o_quotient[BW-1]); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(r_busy))&&(!$past(i_wr))) - assert(!o_busy); - always @(posedge i_clk) - assert((!o_busy)||(!o_valid)); - - always @(*) - if(r_busy) - assert(o_busy); - - always @(posedge i_clk) - if (i_reset) - f_bits_set <= 0; - else if (i_wr) - f_bits_set <= 0; - else if ((r_busy)&&(!pre_sign)) - f_bits_set <= { f_bits_set[BW-1:0], 1'b1 }; - - always @(posedge i_clk) - if (r_busy) - assert(((1<= $past(r_divisor[BW-1:0])) - begin - assert(o_quotient[0]); - end else - assert(!o_quotient[0]); - end - */ - - always @(*) - if (r_busy) - assert((f_bits_set & r_dividend[BW-1:0])==0); - - always @(*) - if (r_busy) - assert((r_divisor == 0) == zero_divisor); - -`ifdef VERIFIC - // {{{ - // Verify unsigned division - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_wr)&&(i_denominator != 0)&&(!i_signed) - |=> ((!o_err)&&(!o_valid)&&(o_busy)&&(!r_sign)&&(!pre_sign) - throughout (r_bit == 0) - ##1 ((r_bit == $past(r_bit)+1)&&({1'b0,r_bit}< BW-1)) - [*0:$] - ##1 ({ 1'b0, r_bit } == BW-1)) - ##1 (!o_err)&&(o_valid)); - - // Verify division by zero - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_wr)&&(i_denominator == 0) - |=> (zero_divisor throughout - (!o_err)&&(!o_valid)&&(pre_sign) [*0:1] - ##1 ((r_busy)&&(!o_err)&&(!o_valid)) - ##1 ((o_err)&&(o_valid)))); - - // }}} -`endif // VERIFIC -`endif -// }}} -endmodule -// -// How much logic will this divide use, now that it's been updated to -// a different (long division) algorithm? -// -// iCE40 stats (Updated) (Original) -// Number of cells: 700 820 -// SB_CARRY 125 125 -// SB_DFF 1 -// SB_DFFE 33 1 -// SB_DFFESR 37 -// SB_DFFESS 31 -// SB_DFFSR 40 40 -// SB_LUT4 433 553 -// -// Xilinx stats (Updated) (Original) -// Number of cells: 758 831 -// FDRE 142 142 -// LUT1 97 97 -// LUT2 69 174 -// LUT3 6 5 -// LUT4 1 6 -// LUT5 68 35 -// LUT6 94 98 -// MUXCY 129 129 -// MUXF7 12 8 -// MUXF8 6 3 -// XORCY 134 134 - diff --git a/delete_later/rtl/cpu/icontrol.v b/delete_later/rtl/cpu/icontrol.v deleted file mode 100644 index e91d6d7..0000000 --- a/delete_later/rtl/cpu/icontrol.v +++ /dev/null @@ -1,382 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: icontrol.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: An interrupt controller, for managing many interrupt sources. -// -// This interrupt controller started from the question of how best to -// design a simple interrupt controller. As such, it has a few nice -// qualities to it: -// 1. This is wishbone compliant -// 2. It sits on a 32-bit wishbone data bus -// 3. It only consumes one address on that wishbone bus. -// 4. There is no extra delays associated with reading this -// device. -// 5. Common operations can all be done in one clock. -// -// So, how shall this be used? First, the 32-bit word is broken down as -// follows: -// -// Bit 31 - This is the global interrupt enable bit. If set, interrupts -// will be generated and passed on as they come in. -// Bits 16-30 - These are specific interrupt enable lines. If set, -// interrupts from source (bit#-16) will be enabled. -// To set this line and enable interrupts from this source, write -// to the register with this bit set and the global enable set. -// To disable this line, write to this register with global enable -// bit not set, but this bit set. (Writing a zero to any of these -// bits has no effect, either setting or unsetting them.) -// Bit 15 - This is the any interrupt pin. If any interrupt is pending, -// this bit will be set. -// Bits 0-14 - These are interrupt bits. When set, an interrupt is -// pending from the corresponding source--regardless of whether -// it was enabled. (If not enabled, it won't generate an -// interrupt, but it will still register here.) To clear any -// of these bits, write a '1' to the corresponding bit. Writing -// a zero to any of these bits has no effect. -// -// The peripheral also sports a parameter, IUSED, which can be set -// to any value between 1 and (buswidth/2-1, or) 15 inclusive. This will -// be the number of interrupts handled by this routine. (Without the -// parameter, Vivado was complaining about unused bits. With it, we can -// keep the complaints down and still use the routine). -// -// To get access to more than 15 interrupts, chain these together, so -// that one interrupt controller device feeds another. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module icontrol #( - // {{{ - parameter IUSED = 12, DW=32 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [DW-1:0] i_wb_data, - input wire [DW/8-1:0] i_wb_sel, - output wire o_wb_stall, o_wb_ack, - output reg [DW-1:0] o_wb_data, - input wire [(IUSED-1):0] i_brd_ints, - output reg o_interrupt - // }}} - ); - - // Local declarations - // {{{ - reg [(IUSED-1):0] r_int_state; - reg [(IUSED-1):0] r_int_enable; - reg r_mie; - wire w_any; - - wire wb_write, enable_ints, disable_ints; - // }}} - assign wb_write = (i_wb_stb)&&(i_wb_we); - assign enable_ints = (wb_write)&&( i_wb_data[15]); - assign disable_ints = (wb_write)&&(!i_wb_data[15]); - - // r_int_state - // {{{ - // First step: figure out which interrupts have triggered. An - // interrupt "triggers" when the incoming interrupt wire is high, and - // stays triggered until cleared by the bus. - initial r_int_state = 0; - always @(posedge i_clk) - if (i_reset) - r_int_state <= 0; - else if (wb_write) - r_int_state <= i_brd_ints - | (r_int_state & (~i_wb_data[(IUSED-1):0])); - else - r_int_state <= (r_int_state | i_brd_ints); - // }}} - - // r_int_enable - // {{{ - // Second step: determine which interrupts are enabled. - // Only interrupts that are enabled will be propagated forward on - // the global interrupt line. - initial r_int_enable = 0; - always @(posedge i_clk) - if (i_reset) - r_int_enable <= 0; - else if (enable_ints) - r_int_enable <= r_int_enable | i_wb_data[16 +: IUSED]; - else if (disable_ints) - r_int_enable <= r_int_enable & (~ i_wb_data[16 +: IUSED]); - // }}} - - // r_mie - // {{{ - // Third step: The master (global) interrupt enable bit. - initial r_mie = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_mie <= 1'b0; - else if (enable_ints && i_wb_data[DW-1]) - r_mie <= 1'b1; - else if (disable_ints && i_wb_data[DW-1]) - r_mie <= 1'b0; - // }}} - - // - // Have "any" enabled interrupts triggered? - assign w_any = ((r_int_state & r_int_enable) != 0); - - // o_interrupt - // {{{ - // How then shall the interrupt wire be set? - initial o_interrupt = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_interrupt <= 1'b0; - else - o_interrupt <= (r_mie)&&(w_any); - // }}} - - // o_wb_data - // {{{ - // Create the output data. Place this into the next clock, to keep - // it synchronous with w_any. - initial o_wb_data = 0; - always @(posedge i_clk) - begin - o_wb_data <= 0; - o_wb_data[31] <= r_mie; - o_wb_data[15] <= w_any; - - o_wb_data[16 +: IUSED] <= r_int_enable; - o_wb_data[ 0 +: IUSED] <= r_int_state; - end - // }}} - - assign o_wb_ack = i_wb_stb; - assign o_wb_stall = 1'b0; - - // Make verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - generate if (IUSED < 15) - begin : UNUSED_INTS - wire unused_int; - assign unused_int = &{ 1'b0, i_wb_data[32-2:(16+IUSED)], - i_wb_data[16-2:IUSED] }; - end endgenerate - - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_wb_sel }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties section -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // {{{ -`ifdef ICONTROL -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Reset handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial `ASSUME(i_reset); - always @(*) - if (!f_past_valid) - `ASSUME(i_reset); - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))) - begin - assert(r_int_state == 0); - assert(r_int_enable == 0); - assert(w_any == 0); - assert(o_interrupt == 0); - assert(r_mie == 0); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Formal contract - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // Rule #1: An interrupt should be able to set the r_int_state bits - // - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))) - assert((r_int_state & $past(i_brd_ints))==$past(i_brd_ints)); - - // Rule #2: An interrupt should be generated if received and enabled - // - // Make sure any enabled interrupt generates an outgoing interrupt - // ... assuming the master interrupt enable is true and the - // individual interrupt enable is true as well. - always @(posedge i_clk) - if (((f_past_valid)&&(!$past(i_reset))) - &&(|$past(r_int_state & r_int_enable)) - &&($past(r_mie)) ) - assert(o_interrupt); - - // Rule #3: If the global interrupt enable bit is off, then no - // interrupts shall be asserted - // - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(r_mie))) - assert(!o_interrupt); - - // Rule #4: If no active interrupts are enabled, then no outgoing - // interrupt shall be asserted either - always @(posedge i_clk) - if ((f_past_valid)&&(0 == |$past(r_int_state & r_int_enable))) - assert(!o_interrupt); - - // Bus rules - // - // Rule #5: It should be possible to disable one (or all) interrupts - always @(posedge i_clk) - if ((f_past_valid)&&($past(disable_ints))) - assert(($past({i_wb_data[31],i_wb_data[16 +: IUSED]}) - & { r_mie, r_int_enable }) == 0); - - // Rule #6: It should be possible to enable one (or all) interrupts - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(enable_ints))) - assert(($past({i_wb_data[31],i_wb_data[16 +: IUSED]}) - & { r_mie, r_int_enable }) - == $past({i_wb_data[31],i_wb_data[16 +: IUSED]})); - - // Rule #7: It shoule be possible to acknowledge an interrupt, and so - // deactivate it - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(wb_write))) - assert(r_int_state == $past(i_brd_ints - | (r_int_state & ~i_wb_data[IUSED-1:0]))); - - // Rule #8: The interrupt enables should be stable without a write - always @(posedge i_clk) - if ((f_past_valid) && (!$past(i_reset)) && (!$past(wb_write))) - assert($stable({r_mie, r_int_enable})); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - wire [1:0] f_nreqs, f_nacks, f_outstanding; - reg past_stb; - - always @(*) - if (i_wb_stb) - assume(i_wb_cyc); - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assume(!i_wb_cyc); - - - fwb_slave #(.DW(DW), .AW(1), .F_MAX_STALL(0), .F_MAX_ACK_DELAY(1), - .F_LGDEPTH(2), .F_MAX_REQUESTS(1), .F_OPT_MINCLOCK_DELAY(0)) - fwb(i_clk, i_reset, - i_wb_cyc, i_wb_stb, i_wb_we, - 1'b0, i_wb_data, 4'hf, - o_wb_ack, o_wb_stall, o_wb_data, 1'b0, - f_nreqs, f_nacks, f_outstanding); - - always @(*) - assert(f_outstanding == 0); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Other consistency logic - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // Without a write or a reset, past interrupts should remain - // enabled. - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(wb_write))&&(!$past(i_reset))) - begin - assert(($past(r_int_state)& ~r_int_state)==0); - assert((!$past(w_any)) || w_any); - end - - // The outgoing interrupt should never be high unless w_any - // is also high - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(w_any))) - assert(!o_interrupt); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - cover(o_interrupt); - - always @(posedge i_clk) - if (!f_past_valid) - cover($fell(w_any) && $stable(r_int_enable)); - - always @(posedge i_clk) - if (f_past_valid) - begin - cover(!o_interrupt && $past(w_any)); - cover(!o_interrupt && $past(r_mie) && $past(|r_int_state)); - end - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/idecode.v b/delete_later/rtl/cpu/idecode.v deleted file mode 100644 index d914ca7..0000000 --- a/delete_later/rtl/cpu/idecode.v +++ /dev/null @@ -1,2181 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: idecode.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This RTL file specifies how instructions are to be decoded -// into their underlying meanings. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module idecode #( - // {{{ - parameter ADDRESS_WIDTH=24, - parameter [0:0] OPT_MPY = 1'b1, - parameter [0:0] OPT_SHIFTS = 1'b1, - parameter [0:0] OPT_EARLY_BRANCHING = 1'b1, - parameter [0:0] OPT_PIPELINED = 1'b1, - parameter [0:0] OPT_DIVIDE = (OPT_PIPELINED), - parameter [0:0] OPT_FPU = 1'b0, - parameter [0:0] OPT_CIS = 1'b1, - parameter [0:0] OPT_LOCK = (OPT_PIPELINED), - parameter [0:0] OPT_OPIPE = (OPT_PIPELINED), - parameter [0:0] OPT_SIM = 1'b0, - parameter [0:0] OPT_SUPPRESS_NULL_BRANCHES = 1'b0, - parameter [0:0] OPT_USERMODE = 1'b1, - parameter [0:0] OPT_LOWPOWER = 1'b0, - localparam AW = ADDRESS_WIDTH - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, i_ce, i_stalled, - input wire [31:0] i_instruction, - input wire i_gie, - input wire [(AW+1):0] i_pc, - input wire i_pf_valid, i_illegal, - output wire o_valid, o_phase, - output reg o_illegal, - output reg [(AW+1):0] o_pc, - output reg [6:0] o_dcdR, o_dcdA, o_dcdB, - output wire [4:0] o_preA, o_preB, - output wire [31:0] o_I, - output reg o_zI, - output reg [3:0] o_cond, - output reg o_wF, - output reg [3:0] o_op, - output reg o_ALU, o_M, o_DV, o_FP, o_break, - output reg o_lock, - output reg o_wR, o_rA, o_rB, - output wire o_early_branch, o_early_branch_stb, - output wire [(AW+1):0] o_branch_pc, - output wire o_ljmp, - output wire o_pipe, - output reg o_sim /* verilator public_flat */, - output reg [22:0] o_sim_immv /* verilator public_flat */ -`ifdef FORMAL - , output reg [31:0] f_insn_word, - output reg f_insn_gie, - output wire f_insn_is_pipeable -`endif - // }}} - ); - - // Declarations - // {{{ - localparam [3:0] CPU_SP_REG = 4'hd, - CPU_CC_REG = 4'he, - CPU_PC_REG = 4'hf; - localparam CISBIT = 31, - CISIMMSEL = 23, - IMMSEL = 18; - - wire [4:0] w_op; - wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, - w_noop, w_lock, w_sim, w_break, w_special, w_add, w_mpy; - wire [4:0] w_dcdR, w_dcdB, w_dcdA; - wire w_dcdR_pc, w_dcdR_cc; - wire w_dcdA_pc, w_dcdA_cc; - wire w_dcdB_pc, w_dcdB_cc; - wire [3:0] w_cond; - wire w_wF, w_mem, w_sto, w_div, w_fpu; - wire w_wR, w_rA, w_rB, w_wR_n; - wire w_ljmp, w_ljmp_dly, w_cis_ljmp; - wire [31:0] iword; - wire pf_valid; - - reg [14:0] r_nxt_half; - reg [4:0] w_cis_op; - reg [22:0] r_I, w_fullI; - wire [22:0] w_I; - wire w_Iz; - - reg [1:0] w_immsrc; - reg r_valid; - wire insn_is_pipeable, illegal_shift; - // }}} - - assign pf_valid = (i_pf_valid)&&(!o_early_branch_stb); - - // iword - // {{{ - generate if (OPT_CIS) - begin : SET_IWORD - - assign iword = (o_phase) - // set second half as a NOOP ... but really - // shouldn't matter - ? { 1'b1, r_nxt_half[14:0], i_instruction[15:0] } - : i_instruction; - end else begin : CLR_IWORD - assign iword = { 1'b0, i_instruction[30:0] }; - - // verilator coverage_off - // verilator lint_off UNUSED - wire unused_nxt_half; - assign unused_nxt_half = &{ 1'b0, r_nxt_half }; - // verilator lint_on UNUSED - // verilator coverage_on - end endgenerate - // }}} - - // w_ljmp, w_cis_ljmp : Long jump early branching - // {{{ - generate - if (OPT_EARLY_BRANCHING) - begin : GEN_CIS_LONGJUMP - if (OPT_CIS) - begin : CIS_EARLY_BRANCHING - - assign w_cis_ljmp = (o_phase)&&(iword[31:16] == 16'hfcf8); - - end else begin : NOCIS_EARLY_BRANCH - - assign w_cis_ljmp = 1'b0; - - end - - assign w_ljmp = (iword == 32'h7c87c000); - - end else begin : NO_CIS_JUMPING - - assign w_cis_ljmp = 1'b0; - assign w_ljmp = 1'b0; - end endgenerate - // }}} - - // w_cis_op : Get the opcode - // {{{ - generate if (OPT_CIS) - begin : GEN_CIS_OP - - always @(*) - if (!iword[CISBIT]) - w_cis_op = iword[26:22]; - else case(iword[26:24]) - 3'h0: w_cis_op = 5'h00; // SUB - 3'h1: w_cis_op = 5'h01; // AND - 3'h2: w_cis_op = 5'h02; // ADD - 3'h3: w_cis_op = 5'h10; // CMP - 3'h4: w_cis_op = 5'h12; // LW - 3'h5: w_cis_op = 5'h13; // SW - 3'h6: w_cis_op = 5'h18; // LDI - 3'h7: w_cis_op = 5'h0d; // MOV - endcase - - end else begin : GEN_NOCIS_OP - - always @(*) - w_cis_op = w_op; - - end endgenerate - // }}} - - // Decode instructions - // {{{ - assign w_op= iword[26:22]; - assign w_mov = (w_cis_op == 5'h0d); - assign w_ldi = (w_cis_op[4:1] == 4'hc); - assign w_brev = (w_cis_op == 5'h08); - assign w_mpy = (w_cis_op[4:1] == 4'h5)||(w_cis_op[4:0]==5'h0c); - assign w_cmptst = (w_cis_op[4:1] == 4'h8); - assign w_ldilo = (w_cis_op[4:0] == 5'h09); - assign w_ALU = (!w_cis_op[4]) // anything with [4]==0, but ... - &&(w_cis_op[3:1] != 3'h7); // not the divide - assign w_add = (w_cis_op[4:0] == 5'h02); - assign w_mem = (w_cis_op[4:3] == 2'b10)&&(w_cis_op[2:1] !=2'b00); - assign w_sto = (w_mem)&&( w_cis_op[0]); - assign w_div = (!iword[CISBIT])&&(w_op[4:1] == 4'h7); - assign w_fpu = (!iword[CISBIT])&&(w_op[4:3] == 2'b11) - &&(w_dcdR[3:1] != 3'h7) - &&(w_op[2:1] != 2'b00); - // If the result register is either CC or PC, and this would otherwise - // be a floating point instruction with floating point opcode of 0, - // then this is a NOOP. - assign w_special= (!iword[CISBIT])&&(w_dcdR[3:1]==3'h7) - &&(w_op[4:2] == 3'b111); - assign w_break = (w_special)&&(w_op[4:0]==5'h1c); - assign w_lock = (w_special)&&(w_op[4:0]==5'h1d); - assign w_sim = (w_special)&&(w_op[4:0]==5'h1e); - assign w_noop = (w_special)&&(w_op[4:1]==4'hf); // Must include w_sim -`ifdef FORMAL - always @(*) - assert(!w_special || !w_fpu); -`endif - // }}} - - // w_dcdR, w_dcdA - // {{{ - // What register will we be placing results into (if at all)? - // - // Two parts to the result register: the register set, given for - // moves in iword[18] but only for the supervisor, and the other - // four bits encoded in the instruction. - // - assign w_dcdR = { ((!iword[CISBIT])&&(OPT_USERMODE)&&(w_mov)&&(!i_gie))?iword[IMMSEL]:i_gie, - iword[30:27] }; - - // 0 LUTs - assign w_dcdA = w_dcdR; // on ZipCPU, A is always result reg - // 0 LUTs - assign w_dcdA_pc = w_dcdR_pc; - assign w_dcdA_cc = w_dcdR_cc; - // 2 LUTs, 1 delay each - assign w_dcdR_pc = (w_dcdR == {i_gie, CPU_PC_REG}); - assign w_dcdR_cc = (w_dcdR == {i_gie, CPU_CC_REG}); - // }}} - - // dcdB - What register is used in the opB? - // {{{ - assign w_dcdB[4] = ((!iword[CISBIT])&&(w_mov)&&(OPT_USERMODE)&&(!i_gie))?iword[13]:i_gie; - assign w_dcdB[3:0]= (iword[CISBIT]) - ? (((!iword[CISIMMSEL])&&(iword[26:25]==2'b10)) - ? CPU_SP_REG : iword[22:19]) - : iword[17:14]; - - // 2 LUTs, 1 delays each - assign w_dcdB_pc = (w_rB)&&(w_dcdB[3:0] == CPU_PC_REG); - assign w_dcdB_cc = (w_rB)&&(w_dcdB[3:0] == CPU_CC_REG); - // }}} - - // w_cond - // {{{ - // Under what condition will we execute this instruction? Only the - // load immediate instruction and the CIS instructions are completely - // unconditional. Well ... not quite. The BREAK, LOCK, and SIM/NOOP - // instructions are also unconditional. - // - assign w_cond = ((w_ldi)||(w_special)||(iword[CISBIT])) ? 4'h8 : - { (iword[21:19]==3'h0), iword[21:19] }; - // }}} - - // rA - do we need to read register A? - // {{{ - assign w_rA = // Floating point reads reg A - (w_fpu) - // Divide's read A - ||(w_div) - // ALU ops read A, - // except for MOV's and BREV's which don't - ||((w_ALU)&&(!w_brev)&&(!w_mov)) - // STO's read A - ||(w_sto) - // Test/compares - ||(w_cmptst); - // }}} - - // rB -- do we read a register for operand B? - // {{{ - // Specifically, do we add the registers value to the immediate to - // create opB? - assign w_rB = (w_mov) - ||((!iword[CISBIT])&&(iword[IMMSEL])&&(!w_ldi)&&(!w_special)) - ||(( iword[CISBIT])&&(iword[CISIMMSEL])&&(!w_ldi)) - // If using compressed instruction sets, - // we *always* read on memory operands. - ||(( iword[CISBIT])&&(w_mem)); - // }}} - - // wR -- will we be writing our result back? - // {{{ - // wR_n = !wR - // All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR - assign w_wR_n = (w_sto) - ||(w_special) - ||(w_cmptst); - assign w_wR = !w_wR_n; - // }}} - // - // wF -- do we write flags when we are done? - // {{{ - assign w_wF = (w_cmptst) - ||((w_cond[3])&&(w_fpu||w_div - ||((w_ALU)&&(!w_mov)&&(!w_ldilo)&&(!w_brev) - &&(w_dcdR[3:1] != 3'h7)))); - // }}} - - // w_immsrc - where does the immediate value come from - // {{{ - // Bottom 13 bits: no LUT's - // w_dcd[12: 0] -- no LUTs - // w_dcd[ 13] -- 2 LUTs - // w_dcd[17:14] -- (5+i0+i1) = 3 LUTs, 1 delay - // w_dcd[22:18] : 5 LUTs, 1 delay (assuming high bit is o/w determined) - always @(*) - if (w_ldi) - w_immsrc = 0; - else if (w_mov) - w_immsrc = 1; - else if (!iword[IMMSEL]) - w_immsrc = 2; - else // if (!iword[IMMSEL]) - w_immsrc = 3; - // }}} - - // w_fullI -- extracting the immediate value from the insn word - // {{{ - always @(*) - case(w_immsrc) - 2'b00: w_fullI = { iword[22:0] }; // LDI - 2'b01: w_fullI = { {(23-13){iword[12]}}, iword[12:0] }; // MOV - 2'b10: w_fullI = { {(23-18){iword[17]}}, iword[17:0] }; // Immediate - 2'b11: w_fullI = { {(23-14){iword[13]}}, iword[13:0] }; // Reg + Imm - endcase - /* - assign w_fullI = (w_ldi) ? { iword[22:0] } // LDI - // MOVE immediates have one less bit - :((w_mov) ?{ {(23-13){iword[12]}}, iword[12:0] } - // Normal Op-B immediate ... 18 or 14 bits - :((!iword[IMMSEL]) ? { {(23-18){iword[17]}}, iword[17:0] } - : { {(23-14){iword[13]}}, iword[13:0] } - )); - */ - // }}} - - // w_I and w_Iz: Immediate value decoding - // {{{ - generate if (OPT_CIS) - begin : GEN_CIS_IMMEDIATE - wire [7:0] w_halfI, w_halfbits; - - assign w_halfbits = iword[CISIMMSEL:16]; - assign w_halfI = (iword[26:24]==3'h6) ? w_halfbits[7:0] // 8'b for LDI - :(w_halfbits[7])? - { {(6){w_halfbits[2]}}, w_halfbits[1:0]} - :{ w_halfbits[6], w_halfbits[6:0] }; - assign w_I = (iword[CISBIT]) - ? {{(23-8){w_halfI[7]}}, w_halfI } - : w_fullI; - - end else begin : GEN_NOCIS_IMMEDIATE - - assign w_I = w_fullI; - - end endgenerate - - assign w_Iz = (w_I == 0); - // }}} - - // o_phase - // {{{ - // The o_phase parameter is special. It needs to let the software - // following know that it cannot break/interrupt on an o_phase asserted - // instruction, lest the break take place between the first and second - // half of a CIS instruction. To do this, o_phase must be asserted - // when the first instruction half is valid, but not asserted on either - // a 32-bit instruction or the second half of a 2x16-bit instruction. - generate if (OPT_CIS) - begin : GEN_CIS_PHASE - // {{{ - reg r_phase; - - // Phase is '1' on the first instruction of a two-part set - // But, due to the delay in processing, it's '1' when our - // output is valid for that first part, but that'll be the - // same time we are processing the second part ... so it may - // look to us like a '1' on the second half of processing. - - // When no instruction is in the pipe, phase is zero - initial r_phase = 1'b0; - always @(posedge i_clk) - if (i_reset || w_ljmp_dly) - r_phase <= 1'b0; - else if ((i_ce)&&(pf_valid)) - begin - if (o_phase) - // CIS instructions only have two parts. On - // the second part (o_phase is true), return - // back to the first - r_phase <= 0; - else - r_phase <= (i_instruction[CISBIT])&&(!i_illegal); - end else if (i_ce) - r_phase <= 1'b0; - - assign o_phase = r_phase; - // }}} - end else begin : NO_CIS - // {{{ - assign o_phase = 1'b0; - // }}} - end endgenerate - // }}} - - // illegal_shift - // {{{ - generate if (OPT_SHIFTS) - begin : LEGAL_SHIFTS - assign illegal_shift = 1'b0; - end else begin : GEN_ILLEGAL_SHIFT - reg r_illegal_shift; - - always @(*) - begin - r_illegal_shift = 1'b1; - if (i_instruction[CISBIT]) - r_illegal_shift = 1'b0; - else if ((i_instruction[26:22] != 5'h5) - &&(i_instruction[26:22] != 5'h6) - &&(i_instruction[26:22] != 5'h7)) - r_illegal_shift = 1'b0; - else if (!i_instruction[18] - && (i_instruction[17:0] == 18'h1)) - r_illegal_shift = 1'b0; - end - - assign illegal_shift = r_illegal_shift; - end endgenerate - // }}} - - // o_illegal - // {{{ - initial o_illegal = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_illegal <= 1'b0; - else if (i_ce && o_phase) - begin - // {{{ - o_illegal <= o_illegal; - // Cannot happen in compressed word ... - // 1. multiply op-codes - // 2. divide opcodes - // 3. FPU opcodes - // 4. special opcodes - // }}} - end else if (i_ce && i_pf_valid) - begin - // {{{ - o_illegal <= 1'b0; - - if (illegal_shift) - o_illegal <= 1'b1; - - if ((!OPT_CIS)&&(i_instruction[CISBIT])) - o_illegal <= 1'b1; - if ((!OPT_MPY)&&(w_mpy)) - o_illegal <= 1'b1; - - if ((!OPT_DIVIDE)&&(w_div)) - o_illegal <= 1'b1; - else if ((OPT_DIVIDE)&&(w_div)&&(w_dcdR[3:1]==3'h7)) - o_illegal <= 1'b1; - - - if ((!OPT_FPU)&&(w_fpu)) - o_illegal <= 1'b1; - - if ((!OPT_SIM)&&(w_sim)) - // Simulation instructions on real hardware should - // always cause an illegal instruction error - o_illegal <= 1'b1; - - // There are two (missing) special instructions, after - // BREAK, LOCK, SIM, and NOOP. These are special if their - // (unused-result) register is either the PC or CC register. - // - // These should cause an illegal instruction error - if ((w_dcdR[3:1]==3'h7)&&(w_cis_op[4:1]==4'b1101)) - o_illegal <= 1'b1; - - // If the lock function isn't implemented, this should - // also cause an illegal instruction error - if ((!OPT_LOCK)&&(w_lock)) - o_illegal <= 1'b1; - - // Bus errors always create illegal instructions - if (i_illegal) - o_illegal <= 1'b1; - // }}} - end - // }}} - - // o_pc - // {{{ - initial o_pc = 0; - always @(posedge i_clk) - if ((i_ce)&&((o_phase)||(i_pf_valid))) - begin - o_pc[0] <= 1'b0; - - if (OPT_CIS) - begin - if (iword[CISBIT]) - begin - if (o_phase) - o_pc[AW+1:1] <= o_pc[AW+1:1] + 1'b1; - else - o_pc <= { i_pc[AW+1:2], 1'b1, 1'b0 }; - end else begin - // The normal, non-CIS case - o_pc <= { i_pc[AW+1:2] + 1'b1, 2'b00 }; - end - end else begin - // The normal, non-CIS case - o_pc <= { i_pc[AW+1:2] + 1'b1, 2'b00 }; - end - end - // }}} - - // Generate output products - // {{{ - initial o_dcdR = 0; - initial o_dcdA = 0; - initial o_dcdB = 0; - initial o_DV = 0; - initial o_FP = 0; - initial o_lock = 0; - initial o_sim = 1'b0; - initial o_sim_immv = 0; - // r_I, o_zI, o_wR, o_rA, o_rB, o_dcdR, o_dcdA, o_dcdB - always @(posedge i_clk) - if (i_ce) - begin - // {{{ - // o_cond, o_wF - // {{{ - // Under what condition will we execute this - // instruction? Only the load immediate instruction - // is completely unconditional. - o_cond <= w_cond; - // Don't change the flags on conditional instructions, - // UNLESS: the conditional instruction was a CMP - // or TST instruction. - o_wF <= w_wF; - // }}} - - // o_op - // {{{ - // Record what operation/op-code (4-bits) we are doing - // Note that LDI magically becomes a MOV - // instruction here. That way it's a pass through - // the ALU. Likewise, the two compare instructions - // CMP and TST becomes SUB and AND here as well. - // We keep only the bottom four bits, since we've - // already done the rest of the decode necessary to - // settle between the other instructions. For example, - // o_FP plus these four bits uniquely defines the FP - // instruction, o_DV plus the bottom of these defines - // the divide, etc. - o_op <= w_cis_op[3:0]; - if ((w_ldi)||(w_noop)||(w_lock)) - o_op <= 4'hd; - // }}} - - o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR}; - o_dcdA <= { w_dcdA_cc, w_dcdA_pc, w_dcdA}; - o_dcdB <= { w_dcdB_cc, w_dcdB_pc, w_dcdB}; - o_wR <= w_wR; - o_rA <= w_rA; - o_rB <= w_rB; - r_I <= w_I; - o_zI <= w_Iz; - - // o_ALU, o_M, o_DV, o_FP - // {{{ - // Turn a NOOP into an ALU operation--subtract in - // particular, although it doesn't really matter as long - // as it doesn't take longer than one clock. Note - // also that this depends upon not setting any registers - // or flags, which should already be true. - o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop) - ||((!OPT_LOCK)&&(w_lock)); - o_M <= w_mem; - o_DV <= (OPT_DIVIDE)&&(w_div); - o_FP <= (OPT_FPU)&&(w_fpu); - // }}} - - // o_break, o_lock - // {{{ - o_break <= w_break; - o_lock <= (OPT_LOCK)&&(w_lock); - // }}} - - if (OPT_CIS) - r_nxt_half <= { iword[14:0] }; - else - r_nxt_half <= 0; - - // o_sim, o_sim_immv -- simulation instructions vs NOOPs - // {{{ - if (OPT_SIM) - begin - // Support the SIM instruction(s) - o_sim <= (w_sim)||(w_noop); - o_sim_immv <= iword[22:0]; - if (OPT_LOWPOWER && !w_sim && !w_noop) - o_sim_immv <= 0; - end else begin - o_sim <= 1'b0; - o_sim_immv <= 0; - end - // }}} - // }}} - end - // }}} - - assign o_preA = w_dcdA; - assign o_preB = w_dcdB; - - // o_early_branch, o_early_branch_stb, o_branch_pc - // {{{ - generate if (OPT_EARLY_BRANCHING) - begin : GEN_EARLY_BRANCH_LOGIC - // {{{ - reg r_early_branch, r_early_branch_stb, - r_ljmp; - reg [(AW+1):0] r_branch_pc; - wire w_add_to_pc; - - initial r_ljmp = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_ljmp <= 1'b0; - else if (i_ce) - begin - if ((r_ljmp)&&(pf_valid)) - r_ljmp <= 1'b0; - else if (o_early_branch_stb) - r_ljmp <= 1'b0; - else if (pf_valid) - begin - if ((OPT_CIS)&&(iword[CISBIT])) - r_ljmp <= w_cis_ljmp; - else - r_ljmp <= (w_ljmp); - end else if ((OPT_CIS)&&(o_phase)&&(iword[CISBIT])) - r_ljmp <= w_cis_ljmp; - end - assign o_ljmp = r_ljmp; - - assign w_add_to_pc = (!o_phase - && (!OPT_CIS || !i_instruction[CISBIT]) - && (i_instruction[30:27]==CPU_PC_REG) // Rd=PC - && (i_instruction[26:22] == 5'h02) // ADD - && (i_instruction[21:19]==3'h0) // NONE - && !i_instruction[IMMSEL]); - - initial r_early_branch = 1'b0; - initial r_early_branch_stb = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - r_early_branch <= 1'b0; - r_early_branch_stb <= 1'b0; - end else if (i_ce && pf_valid) - begin - if (r_ljmp) - begin - // LW (PC),PC - r_early_branch <= 1'b1; - r_early_branch_stb <= 1'b1; - end else if (w_add_to_pc) - begin - // Add x,PC - r_early_branch <= 1'b1; - r_early_branch_stb <= (!OPT_SUPPRESS_NULL_BRANCHES) - || (i_instruction[IMMSEL-1:0] != 0); - // LDI #x,PC is no longer supported - end else begin - r_early_branch <= 1'b0; - r_early_branch_stb <= 1'b0; - end - end else begin - r_early_branch_stb <= 1'b0; - if (i_ce) - r_early_branch <= 1'b0; - end - - initial r_branch_pc = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && i_reset) - r_branch_pc <= 0; - else if (i_ce) - begin - if (r_ljmp) - r_branch_pc <= { iword[(AW+1):2], - 2'b00 }; - else if (!OPT_LOWPOWER || w_add_to_pc) - begin - // Add x,PC - r_branch_pc[AW+1:2] <= i_pc[AW+1:2] - + {{(AW-15){i_instruction[17]}}, - i_instruction[16:2]} - + {{(AW-1){1'b0}},1'b1}; - r_branch_pc[1:0] <= 2'b00; - end else if (OPT_LOWPOWER) - r_branch_pc <= 0; - - if (OPT_LOWPOWER && !pf_valid) - r_branch_pc <= 0; - end - - assign w_ljmp_dly = r_ljmp; - assign o_early_branch = r_early_branch; - assign o_early_branch_stb = r_early_branch_stb; - assign o_branch_pc = r_branch_pc; -`ifdef FORMAL - always @(*) - if (OPT_LOWPOWER && !r_early_branch) - assert(r_branch_pc == 0); -`endif - // }}} - end else begin : NO_EARLY_BRANCHING - // {{{ - assign w_ljmp_dly = 1'b0; - assign o_early_branch = 1'b0; - assign o_early_branch_stb = 1'b0; - assign o_branch_pc = {(AW+2){1'b0}}; - assign o_ljmp = 1'b0; - - // verilator coverage_off - // verilator lint_off UNUSED - wire early_branch_unused; - assign early_branch_unused = &{ 1'b0, w_add }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} - end endgenerate - // }}} - - // o_pipe - // {{{ - // To be a pipeable operation there must be ... - // 1. Two valid adjacent instructions - // 2. Both must be memory operations, of the same time (both lods - // or both stos) - // 3. Both must use the same register base address - // 4. Both must be to the same address, or the address incremented - // by one - // Note that we're not using iword here ... there's a lot of logic - // taking place, and it's only valid if the new word is not compressed. - // - generate if (OPT_OPIPE) - begin : GEN_OPIPE - // {{{ - reg r_pipe, r_insn_is_pipeable; - - // Pipeline logic is too extreme for a single clock. - // Let's break it into two clocks, using r_insn_is_pipeable - // If this function is true, then the instruction associated - // with the current output *may* have a pipeable instruction - // following it. - // - initial r_insn_is_pipeable = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_insn_is_pipeable <= 1'b0; - else if ((i_ce)&&((!pf_valid)||(i_illegal))&&(!o_phase)) - // Pipeline bubble, can't pipe through it - r_insn_is_pipeable <= 1'b0; - else if (o_ljmp) - r_insn_is_pipeable <= 1'b0; - else if ((i_ce)&&((!OPT_CIS)&&(i_instruction[CISBIT]))) - r_insn_is_pipeable <= 1'b0; - else if (i_ce) - begin // This is a valid instruction - r_insn_is_pipeable <= (w_mem)&&(w_rB) - // PC (and CC) registers can change - // underneath us. Therefore they cannot - // be used as a base register for piped - // memory ops - &&(w_dcdB[3:1] != 3'h7) - // Writes to PC or CC will destroy any - // possibility of pipeing--since they - // could create a jump - &&(w_dcdR[3:1] != 3'h7) - // - // Loads landing in the current address - // pointer register are not allowed, - // as they could then be used to violate - // our rule(s) - &&((w_cis_op[0])||(w_dcdB != w_dcdA)); - end // else - // The pipeline is stalled - - assign insn_is_pipeable = r_insn_is_pipeable; - - initial r_pipe = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_pipe <= 1'b0; - else if (i_ce) - r_pipe <= ((pf_valid)||(o_phase)) - // The last operation must be capable of - // being followed by a pipeable memory op - &&(r_insn_is_pipeable) - // Both must be memory operations - &&(w_mem) - // Both must be writes, or both stores - &&(o_op[0] == w_cis_op[0]) - // Both must be register ops - &&(w_rB) - // Both must use the same register for B - &&(w_dcdB[3:0] == o_dcdB[3:0]); - // // CC or PC registers are not valid addresses - // // Captured above - // // But ... the result can never be B - // // Captured above - // // - // // Reads to CC or PC not allowed - // // &&((o_op[0])||(w_dcdR[3:1] != 3'h7)) - // // Prior-reads to CC or PC not allowed - // // Captured above - // // Same condition, or no condition now - // &&((w_cond[2:0]==o_cond[2:0]) - // ||(w_cond[2:0] == 3'h0)); - // // Same or incrementing immediate - // &&(w_I[22]==r_I[22]); - assign o_pipe = r_pipe; - // }}} - end else begin : GEN_NO_PIPE - // {{{ - assign o_pipe = 1'b0; - assign insn_is_pipeable = 1'b0; - - // verilator coverage_off - // verilator lint_off UNUSED - wire unused_pipable; - assign unused_pipable = &{ 1'b0, insn_is_pipeable }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} - end endgenerate - // }}} - - // o_valid - // {{{ - initial r_valid = 1'b0; - generate if (OPT_PIPELINED) - begin : GEN_DCD_VALID - - always @(posedge i_clk) - if (i_reset) - r_valid <= 1'b0; - else if (i_ce) - r_valid <= ((pf_valid)||(o_phase))&&(!o_ljmp); - else if (!i_stalled) - r_valid <= 1'b0; - - end else begin : GEN_DCD_VALID - - always @(posedge i_clk) - if (i_reset) - r_valid <= 1'b0; - else if (!i_stalled) - r_valid <= ((pf_valid)||(o_phase))&&(!o_ljmp); - else - r_valid <= 1'b0; - - end endgenerate - - assign o_valid = r_valid; - // }}} - - assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] }; - - // Make Verilator happy across all our various options - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire possibly_unused; - assign possibly_unused = &{ 1'b0, w_lock, w_ljmp, w_ljmp_dly, - insn_is_pipeable, w_cis_ljmp, i_pc[1:0], w_add }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - -`define ASSERT assert -`ifdef IDECODE -`define ASSUME assume -`else -`define ASSUME assert -`endif - always @(posedge i_clk) - if ((i_ce)&&(i_pf_valid)&&(!o_phase)) - f_insn_word <= i_instruction; - - assign f_insn_is_pipeable = insn_is_pipeable; - - always @(posedge i_clk) - if ((i_ce)&&(i_pf_valid)&&(!o_phase)) - f_insn_gie <= i_gie; - - always @(posedge i_clk) - if (!i_reset && o_valid) - `ASSUME(f_insn_gie == i_gie); - - always @(*) - if (o_phase) - assert(r_nxt_half == f_insn_word[14:0]); - - //////////////////////////// - // - // - // Assumptions about our inputs - // - // - /////////////////////////// - always @(*) - if (OPT_PIPELINED) - begin - `ASSUME(i_ce == ((!o_valid)||(!i_stalled))); - end else - `ASSUME(i_ce == !i_stalled); - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - `ASSERT(!o_valid); - // `ASSERT(!o_illegal); - `ASSERT(!o_phase); - `ASSERT(!o_ljmp); - `ASSERT(!o_pipe); - - // `ASSUME(!i_pf_valid); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!i_reset)) - `ASSUME(i_gie == $past(i_gie)); - -`ifdef IDECODE - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!$past(i_ce)) - &&($past(f_past_valid))&&(!$past(i_reset,2))&&(!$past(i_ce,2))) - assume(i_ce); -`endif - - reg f_new_insn, f_last_insn; - - initial f_new_insn = 1'b0; - always @(posedge i_clk) - if (i_reset) - f_new_insn <= 1'b0; - else - f_new_insn <= ((pf_valid)&&(!i_stalled)); - - initial f_last_insn = 1'b0; - always @(posedge i_clk) - if (i_reset) - f_last_insn <= 1'b0; - else - f_last_insn <= (o_valid)&&(i_stalled); - - always @(posedge i_clk) - if ((f_past_valid)&&(f_last_insn)&&(!i_reset)) - begin - if (($past(pf_valid))&&(pf_valid)) - begin - `ASSUME(i_illegal || i_instruction == $past(i_instruction)); - `ASSUME(i_gie == $past(i_gie)); - `ASSUME(i_pc == $past(i_pc)); - `ASSUME(i_illegal == $past(i_illegal)); - end - end - - always @(posedge i_clk) - if ((f_past_valid)&&(o_early_branch_stb)) - `ASSUME(!pf_valid); - - always @(*) - if (i_pf_valid) - `ASSUME(i_pc[1:0] == 2'b00); - - always @(*) - if ((o_valid)&&(!o_early_branch)) - `ASSERT((o_illegal)||(o_pc[1] == o_phase)); - - wire [3+7+7+7+32+1+4+1+4+10+(AW+2)+3+23+(AW+2)-1:0] f_result; - assign f_result = { o_phase, o_illegal, i_gie, - o_dcdR, o_dcdA, o_dcdB, - o_I, o_zI, o_cond, o_wF, o_op, - o_ALU, o_M, o_DV, o_FP, o_break, o_lock, - o_wR, o_rA, o_rB, o_early_branch, - o_branch_pc, o_ljmp, o_pipe, o_sim, - o_sim_immv, o_pc }; - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($stable(i_gie))&&(f_last_insn)) - begin - `ASSERT($stable(f_result)); - if (OPT_PIPELINED) - // All but valid will be stable - `ASSERT($stable(o_valid)); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(pf_valid)) - &&(!$past(o_ljmp))) - `ASSERT((!OPT_PIPELINED)||(o_valid)); - - always @(posedge i_clk) - if ((f_past_valid)&&(f_new_insn) - &&($past(pf_valid))&&($past(i_illegal))&&(!$past(o_phase))) - `ASSERT(o_illegal); - -`ifdef IDECODE - //////////////////////////////////////////////////////////////////////// - // - // Let's walk through some basic instructions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // First 8-instructions, SUB - ASR - // {{{ - always @(*) - if ((!iword[CISBIT])&&(iword[26:25]==2'b00)) - begin - // {{{ - `ASSERT(!w_cmptst); - `ASSERT(!w_div); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(!w_mpy); - `ASSERT((w_rA)&&(w_wR)&&(w_ALU)); - `ASSERT(w_rB == iword[IMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond[3] == (iword[21:19] == 3'b000)); - `ASSERT(w_cond[2:0] == iword[21:19]); - `ASSERT((w_wF == w_cond[3])||(w_dcdA[3:1]==3'b111)); - // }}} - end else if ((iword[CISBIT])&&(iword[26:24]<3'b011)) - begin - // {{{ - `ASSERT(!w_cmptst); - `ASSERT(!w_div); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(!w_mpy); - `ASSERT((w_rA)&&(w_wR)&&(w_ALU)); - `ASSERT(w_rB == iword[CISIMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[22:19]); - - if (iword[26:24] == 3'b000) - begin - `ASSERT(w_cis_op == 5'h0); - end else if (iword[26:24] == 5'h01) - begin - `ASSERT(w_cis_op == 5'h01); - end else // if (iword[26:24] == 3'b010) - `ASSERT(w_cis_op == 5'h02); - - `ASSERT(w_cond == 4'h8); - - if (iword[CISIMMSEL]) - begin - `ASSERT(w_I == { {(23-3){iword[18]}}, iword[18:16] }); - end else - `ASSERT(w_I == { {(23-7){iword[22]}}, iword[22:16] }); - // }}} - end else - `ASSERT(!w_add); - // }}} - - // BREV and LDILO - // {{{ - always @(*) - if ((!iword[CISBIT])&&((w_cis_op == 5'h8) - ||(w_cis_op == 5'h09))) - begin - // {{{ - `ASSERT(!w_mpy); - `ASSERT(!w_div); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - if (w_cis_op == 5'h8) - begin - `ASSERT(w_brev); - `ASSERT(!w_ldilo); - `ASSERT((!w_rA)&&(w_wR)&&(w_ALU)); - end else begin// if (w_cis_op == 5'h9) - `ASSERT(w_ldilo); - `ASSERT(!w_brev); - `ASSERT((w_rA)&&(w_wR)&&(w_ALU)); - end - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(w_rB == iword[IMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond[3] == (iword[21:19] == 3'b000)); - `ASSERT(w_cond[2:0] == iword[21:19]); - `ASSERT(!w_wF); - // }}} - end else begin - // {{{ - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - // }}} - end - // }}} - - // Multiply instructions - // {{{ - always @(*) - if ((!iword[CISBIT])&&((w_cis_op == 5'ha) - ||(w_cis_op == 5'h0b) - ||(w_cis_op == 5'h0c))) - begin - // {{{ - `ASSERT(w_mpy); - `ASSERT(!w_div); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT((w_rA)&&(w_wR)&&(w_ALU)); - `ASSERT(w_rB == iword[IMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond[3] == (iword[21:19] == 3'b000)); - `ASSERT(w_cond[2:0] == iword[21:19]); - `ASSERT((w_wF == w_cond[3])||(w_dcdA[3:1]==3'b111)); - // }}} - end else - `ASSERT(!w_mpy); - // }}} - - // Move instruction - // {{{ - always @(*) - if ((!iword[CISBIT])&&((w_cis_op == 5'hd))) - begin - // {{{ - `ASSERT(w_mov); - `ASSERT(!w_div); - `ASSERT(!w_mpy); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT((!w_rA)&&(w_wR)&&(w_ALU)); - `ASSERT(w_rB); - `ASSERT(w_dcdA[4] == ((i_gie)||(iword[IMMSEL]))); - `ASSERT(w_dcdB[4] == ((i_gie)||(iword[13]))); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond[3] == (iword[21:19] == 3'b000)); - `ASSERT(w_cond[2:0] == iword[21:19]); - `ASSERT(!w_wF); - // }}} - end else if ((iword[CISBIT])&&(iword[26:24]==3'b111)) - begin - // {{{ - `ASSERT(w_mov); - `ASSERT(!w_div); - `ASSERT(!w_mpy); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT((!w_rA)&&(w_wR)&&(w_ALU)); - `ASSERT(w_rB); - `ASSERT(w_dcdA[4] == (i_gie)); - `ASSERT(w_dcdB[4] == (i_gie)); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[22:19]); - - `ASSERT(w_cis_op == 5'h0d); - - `ASSERT(w_cond == 4'h8); - `ASSERT(!w_wF); - // }}} - end else - `ASSERT(!w_mov); - // }}} - - // Divide instruction - // {{{ - always @(*) - if ((!iword[CISBIT])&&(iword[26:23]==4'b0111)) - begin - // {{{ - `ASSERT(w_div); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(!w_mpy); - `ASSERT((w_rA)&&(w_wR)); - `ASSERT(w_rB == iword[IMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond[3] == (iword[21:19] == 3'b000)); - `ASSERT(w_cond[2:0] == iword[21:19]); - `ASSERT((w_wF == w_cond[3])||(w_dcdA[3:1]==3'b111)); - // }}} - end else - `ASSERT(!w_div); - // }}} - - // Comparison instructions - // {{{ - always @(*) - if ((!iword[CISBIT])&&(iword[26:23]==4'b1000)) - begin - // {{{ - `ASSERT(w_cmptst); - `ASSERT(!w_div); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(!w_mpy); - `ASSERT((w_rA)&&(!w_wR)&&(!w_ALU)); - `ASSERT(w_rB == iword[IMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond[3] == (iword[21:19] == 3'b000)); - `ASSERT(w_cond[2:0] == iword[21:19]); - `ASSERT(w_wF); - // }}} - end else if ((iword[CISBIT])&&(iword[26:24]==3'b011)) - begin - // {{{ - `ASSERT(w_cmptst); - `ASSERT(!w_div); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(!w_mpy); - `ASSERT((w_rA)&&(!w_wR)&&(!w_ALU)); - `ASSERT(w_rB == iword[CISIMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[22:19]); - - `ASSERT(w_cis_op == 5'h10); - - `ASSERT(w_cond == 4'h8); - if (iword[CISIMMSEL]) - begin - `ASSERT(w_I == { {(23-3){iword[18]}}, iword[18:16] }); - end else - `ASSERT(w_I == { {(23-7){iword[22]}}, iword[22:16] }); - `ASSERT(w_wF); - // }}} - end else - `ASSERT(!w_cmptst); - // }}} - - always @(posedge i_clk) - if ((f_new_insn)&&($past(w_cmptst))) - `ASSERT(o_ALU); - - // Memory instructions - // {{{ - always @(*) - if ((!iword[CISBIT])&&( - (iword[26:23]==4'b1001) // Word - ||(iword[26:23]==4'b1010) // Half-word, or short - ||(iword[26:23]==4'b1011))) // Byte ops - begin - // {{{ - `ASSERT(w_mem); - `ASSERT(w_sto == iword[22]); - `ASSERT(!w_cmptst); - `ASSERT(!w_div); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(!w_mpy); - if (w_sto) - begin - `ASSERT((w_rA)&&(!w_wR)); - end else - `ASSERT((!w_rA)&&(w_wR)); - `ASSERT(!w_ALU); - `ASSERT(w_rB == iword[IMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond[3] == (iword[21:19] == 3'b000)); - `ASSERT(w_cond[2:0] == iword[21:19]); - `ASSERT(!w_wF); - // }}} - end else if ((iword[CISBIT])&&(iword[26:25]==2'b10)) - begin - // {{{ - `ASSERT(w_mem); - `ASSERT(w_sto == iword[24]); - `ASSERT(!w_cmptst); - `ASSERT(!w_div); - `ASSERT(!w_ldi); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(!w_mpy); - if (w_sto) - begin - `ASSERT((w_rA)&&(!w_wR)); - end else - `ASSERT((!w_rA)&&(w_wR)); - `ASSERT(!w_ALU); - `ASSERT(w_rB); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - if (iword[CISIMMSEL]) - begin - `ASSERT(w_dcdB[3:0] == iword[22:19]); - end else - `ASSERT(w_dcdB[3:0] == CPU_SP_REG); - - if (w_sto) - begin - `ASSERT(w_cis_op == 5'h13); - end else - `ASSERT(w_cis_op == 5'h12); - - `ASSERT(w_cond == 4'h8); - `ASSERT(!w_wF); - // }}} - end else begin - // {{{ - `ASSERT(!w_sto); - `ASSERT(!w_mem); - // }}} - end - - always @(*) - if (w_sto) - `ASSERT(w_mem); - // }}} - - // LDI -- Load immediate - // {{{ - always @(*) - if ((!iword[CISBIT])&&(w_op[4:1] == 4'hc)) - begin - // {{{ - `ASSERT(w_ldi); - `ASSERT(!w_mpy); - `ASSERT(!w_div); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT((!w_rA)&&(w_wR)&&(!w_ALU)); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(w_rB == 1'b0); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond == 4'h8); - `ASSERT(!w_wF); - - `ASSERT(w_Iz == (iword[22:0] == 0)); - `ASSERT(w_I[22:0] == iword[22:0]); - // }}} - end else if ((iword[CISBIT])&&(iword[26:24] == 3'b110)) - begin - // {{{ - `ASSERT(w_ldi); - `ASSERT(!w_mpy); - `ASSERT(!w_div); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT((!w_rA)&&(w_wR)&&(!w_ALU)); - `ASSERT(!w_special); - `ASSERT(!w_fpu); - `ASSERT(w_rB == 1'b0); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - - `ASSERT(w_cis_op[4:1] == 4'hc); - - `ASSERT(w_cond == 4'h8); - `ASSERT(!w_wF); - - `ASSERT(w_Iz == (iword[23:16] == 0)); - `ASSERT(w_I[22:0] == { {(23-8){iword[23]}}, iword[23:16] }); - // }}} - end else - `ASSERT(!w_ldi); - // }}} - -`endif // IDECODE - - always @(posedge i_clk) - if ((f_new_insn)&&($past(w_ldi))) - `ASSERT(o_ALU); - - always @(*) - if (!OPT_LOCK) - `ASSERT(!o_lock); - -`ifdef IDECODE - always @(*) - if ((w_break)||(w_lock)||(w_sim)||(w_noop)) - `ASSERT(w_special); - - // FPU -- Floating point instructions - // {{{ - always @(*) - if ((!iword[CISBIT])&&( - (w_cis_op[4:1] == 4'hd) - ||(w_cis_op[4:1] == 4'he) - ||(w_cis_op[4:1] == 4'hf)) - &&(iword[30:28] != 3'h7)) - begin - // {{{ - `ASSERT(w_fpu); - `ASSERT(!w_ldi); - `ASSERT(!w_mpy); - `ASSERT(!w_div); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - `ASSERT((w_wR)&&(!w_ALU)); - if ((w_cis_op == 5'he)||(w_cis_op == 5'hf)) - begin - `ASSERT(!w_rA); - end else begin - `ASSERT(w_rA); - end - `ASSERT(!w_special); - `ASSERT(w_rB == iword[IMMSEL]); - `ASSERT(w_dcdA[4] == i_gie); - `ASSERT(w_dcdB[4] == i_gie); - `ASSERT(w_dcdA[3:0] == iword[30:27]); - `ASSERT(w_dcdB[3:0] == iword[17:14]); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond[3] == (iword[21:19] == 3'b000)); - `ASSERT(w_cond[2:0] == iword[21:19]); - `ASSERT((w_wF == w_cond[3])||(w_dcdA[3:1]==3'b111)); // !!! - // }}} - end else - `ASSERT(!w_fpu); - // }}} - - // Special instructions - // {{{ - always @(*) - if ((!iword[CISBIT])&&( - (w_cis_op == 5'h1c) - ||(w_cis_op == 5'h1d) - ||(w_cis_op == 5'h1e) - ||(w_cis_op == 5'h1f)) - &&(iword[30:28] == 3'h7)) - begin - // {{{ - `ASSERT(w_special); - if (w_cis_op == 5'h1c) - begin // Break instruction - `ASSERT(w_break); - `ASSERT(!w_lock); - `ASSERT(!w_sim); - `ASSERT(!w_noop); - end else if (w_cis_op == 5'h1d) - begin // Lock instruction - `ASSERT(!w_break); - `ASSERT( w_lock); - `ASSERT(!w_sim); - `ASSERT(!w_noop); - end else if (w_cis_op == 5'h1e) - begin // Sim instruction - `ASSERT(!w_break); - `ASSERT(!w_lock); - `ASSERT( w_sim); - `ASSERT( w_noop); - end else begin // NOOP instruction - `ASSERT(!w_break); - `ASSERT(!w_lock); - `ASSERT(!w_sim); - `ASSERT( w_noop); - end - `ASSERT((!w_fpu)||(!OPT_FPU)); - `ASSERT(!w_ldi); - `ASSERT(!w_mpy); - `ASSERT(!w_div); - `ASSERT(!w_cmptst); - `ASSERT(!w_mem); - `ASSERT(!w_sto); - `ASSERT(!w_mov); - `ASSERT(!w_brev); - `ASSERT(!w_ldilo); - - `ASSERT((!w_rA)&&(!w_rB)&&(!w_wR)&&(!w_ALU)); - - `ASSERT(w_cis_op == w_op); - - `ASSERT(w_cond == 4'h8); - `ASSERT(!w_wF); - // }}} - end else begin - // {{{ - `ASSERT(!w_special); - `ASSERT(!w_break); - `ASSERT(!w_lock); - `ASSERT(!w_sim); - `ASSERT(!w_noop); - // }}} - end - // }}} - // }}} -`endif - //////////////////////////////////////////////////////////////////////// - // - // Early branching checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_EARLY_BRANCHING) - begin - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_ce))&&(!$past(i_reset))&&(!i_reset)) - begin - if ($past(pf_valid)) - begin - if ($past(o_ljmp)) - begin - // 2nd half of LW (PC),PC - `ASSERT(o_early_branch); - `ASSERT(o_early_branch_stb); - end else if ((!$past(iword[CISBIT]))&&($past(w_add)) - &&(!$past(w_rB)) - &&($past(w_cond[3])) - &&(o_dcdR[4:0]=={ i_gie, 4'hf })) - begin - // ADD #x,PC - `ASSERT(o_early_branch); - `ASSERT(o_early_branch_stb); - end else if ((!$past(iword[CISBIT])) - &&($past(w_cis_op == 5'h12)) - &&($past(w_rB)) - &&($past(w_cond[3])) - &&(o_zI) - &&(o_dcdB[4:0]=={ i_gie, 4'hf }) - &&(o_dcdR[4:0]=={ i_gie, 4'hf })) - begin - // LW (PC),PC - `ASSERT(!o_early_branch); - `ASSERT(!o_early_branch_stb); - end else if ((OPT_CIS)&&($past(o_phase)) - &&($past(w_cis_op == 5'h12)) - &&($past(w_rB)) - &&($past(w_cond[3])) - &&($past(w_Iz)) - &&($past(w_dcdB_pc)) - &&($past(w_dcdR_pc)) - &&(o_dcdR[4:0]=={ i_gie, 4'hf })) - begin - // (CIS) LW (PC),PC - `ASSERT(!o_early_branch); - `ASSERT(!o_early_branch_stb); - end else begin - `ASSERT(!o_early_branch); - end - end else if ((OPT_CIS)&&($past(o_phase))) - begin - if (($past(w_cis_op == 5'h12)) - &&($past(w_rB)) - &&($past(w_cond[3])) - &&($past(w_Iz)) - &&($past(w_dcdB_pc)) - &&($past(w_dcdR_pc))) - begin - // (CIS) LW (PC),PC - `ASSERT(!o_early_branch); - `ASSERT(!o_early_branch_stb); - end else begin - `ASSERT(!o_early_branch); - `ASSERT(!o_early_branch_stb); - end - end - end else if (!i_reset) - `ASSERT(!o_early_branch_stb); - -// // CIS instruction 16'hfcf8 decodes into: -// // 1.1111.100.1.1111.0000 -// // = LW (PC),PC -// always @(*) -// assume(i_instruction[31:16] != 16'hfcf8); - - end else begin - always @(*) - `ASSERT(!o_early_branch_stb); - always @(*) - `ASSERT(!o_early_branch); - end endgenerate - - always @(*) - if (o_early_branch_stb) - `ASSERT(o_early_branch); - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_early_branch_stb))&&(!$past(pf_valid))) - `ASSERT(!o_early_branch_stb); - // }}} - - // CIS specific checks - // {{{ - generate if (OPT_CIS) - begin : F_OPT_CIS - // {{{ - always @(*) - if (OPT_PIPELINED && !o_valid) - `ASSERT(!o_phase); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))) - begin - if ((o_phase)&&($past(i_ce))) - begin - `ASSERT((iword[30:16] == $past(i_instruction[14:0])) - &&(iword[CISBIT])); - end else if (!o_phase) - `ASSERT(iword == i_instruction); - - if ((!$past(o_phase))&&($past(i_ce)) - &&($past(pf_valid)) - &&(!$past(i_illegal)) - &&(!$past(w_ljmp_dly)) - &&($past(i_instruction[CISBIT])) - &&((!$past(w_dcdR_pc)) - ||(!$past(w_wR)))) - begin - `ASSERT(o_phase); - end else if (($past(o_phase))&&($past(i_ce))) - `ASSERT(!o_phase); - if (($past(i_ce))&&(!$past(o_phase)) - &&($past(i_illegal))&&($past(i_pf_valid))) - `ASSERT((o_illegal)&&(!o_phase)); - - `ASSERT((!o_phase)||(!o_ljmp)); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_stalled))&&($past(pf_valid)) - &&($past(i_ce))) - begin - `ASSERT(o_pc[0] == 1'b0); - if (!$past(iword[CISBIT])) - begin - `ASSERT(o_pc[1:0]==2'b00); - `ASSERT(o_pc[AW+1:2] == $past(i_pc[AW+1:2])+1'b1); - end else if ($past(iword[CISBIT])&&($past(o_phase))) - begin - `ASSERT(o_pc[(AW+1):1] == $past(o_pc[(AW+1):1]) + 1'b1); - end else if ($past(iword[CISBIT])) - begin - `ASSERT(o_pc[(AW+1):1] == { $past(i_pc[(AW+1):2]), 1'b1}); - if (o_valid) - begin - `ASSERT(o_pc[1]); - `ASSERT((o_illegal)||(o_phase)); - end - end - end - - - always @(*) - if (iword[CISBIT]) - begin - `ASSERT((!w_ldi)||(w_I == { {(23-8){iword[23]}}, iword[23:16] })); - `ASSERT((w_ldi)||(iword[CISIMMSEL]) - ||(w_I == { {(23-7){iword[22]}}, iword[22:16] })); - `ASSERT((w_ldi)||(!iword[CISIMMSEL]) - ||(w_I == { {(23-3){iword[18]}}, iword[18:16] })); - end else begin - `ASSERT((!w_ldi)||(w_I == iword[22:0])); - `ASSERT((!w_mov)||(w_I == { {(23-13){iword[12]}}, iword[12:0] })); - `ASSERT((w_ldi)||(w_mov)||(iword[IMMSEL]) - ||(w_I == { {(23-18){iword[17]}}, iword[17:0] })); - `ASSERT((w_ldi)||(w_mov)||(!iword[IMMSEL]) - ||(w_I == { {(23-14){iword[13]}}, iword[13:0] })); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(o_phase)&&($past(i_ce))) - `ASSERT(($past(i_instruction[CISBIT])) - &&(r_nxt_half[14:0]==$past(i_instruction[14:0]))); - // }}} - end else begin - // {{{ - always @(*) - begin - `ASSERT((o_phase)||(iword[30:0] == i_instruction[30:0])); - `ASSERT(o_phase == 1'b0); - `ASSERT(o_pc[0] == 1'b0); - end - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_ce))&&($past(i_pf_valid))) - begin - `ASSERT(o_pc[AW+1:2] == $past(i_pc[AW+1:2]) + 1'b1); - end else if (f_past_valid) - `ASSERT(o_pc == $past(o_pc)); - - always @(*) - `ASSERT(o_pc[1:0] == 2'b00); - - always @(*) - `ASSERT((!w_ldi)||(w_I == iword[22:0])); - always @(*) - `ASSERT((!w_mov)||(w_I == { {(23-13){iword[12]}}, iword[12:0] })); - always @(*) - `ASSERT((w_ldi)||(w_mov)||(iword[IMMSEL]) - ||(w_I == { {(23-18){iword[17]}}, iword[17:0] })); - always @(*) - `ASSERT((w_ldi)||(w_mov)||(!iword[IMMSEL]) - ||(w_I == { {(23-14){iword[13]}}, iword[13:0] })); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_ce))&&(!$past(i_reset))) - `ASSERT((!$past(i_instruction[CISBIT])) - ||(!$past(pf_valid))||(o_illegal)); - // }}} - end endgenerate - // }}} - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_ce && pf_valid)) - &&($past(w_fpu))) - begin - if (OPT_FPU) - begin - `ASSERT(o_FP); - end else if (!$past(w_special)) - `ASSERT(o_illegal); - end - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_ce && pf_valid))&&($past(w_lock))) - begin - if (OPT_LOCK) - begin - `ASSERT(o_lock); - end else - `ASSERT(o_illegal); - end - //////////////////////////////////////////////////////////////////////// - // - // Check pipelined memory instructions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // wire [20:0] f_next_pipe_I, f_this_pipe_I; - - // assign f_this_pipe_I = r_I[22:2]; - // assign f_next_pipe_I = r_I[22:2]+1'b1; - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))) - begin - if (OPT_OPIPE) - begin - if (($past(i_ce)) - &&(($past(pf_valid))||($past(o_phase)))) - begin - if ((!$past(o_M))||(!o_M)) - begin - `ASSERT(!o_pipe); - end else if ($past(o_op[0])!=o_op[0]) - begin - `ASSERT(!o_pipe); - end else if ($past(o_rB)!=o_rB) - begin - `ASSERT(!o_pipe); - end else if ((o_rB)&&($past(o_dcdB) != o_dcdB)) - begin - `ASSERT(!o_pipe); - end else if (($past(o_wR)) - &&($past(o_dcdR[3:1]) == 3'h7)) - begin - `ASSERT(!o_pipe); - end else if (o_wR != $past(o_wR)) - begin - `ASSERT(!o_pipe); - end else if ((o_wR)&&($past(o_dcdR) == o_dcdB)) - begin - `ASSERT(!o_pipe); - end else if ((o_wR)&&(o_dcdB[3:1] == 3'h7)) - begin - `ASSERT(!o_pipe); - // - // Allow reading into the PC register as a form of jumping - // // else if ((o_wR)&&(o_dcdR[3:1] == 3'h7)) - // // `ASSERT(!o_pipe); - // Allow discontinuous reads -- since our crossbar can now - // handle them - // else if (($past(o_cond) != 4'h8) - // &&($past(o_cond) != o_cond)) - // `ASSERT(!o_pipe); - // This never really guaranteed that addresses would only - // increment, nor does it guarantee that addresses won't - // wrap around, so ... we'll just ignore this and (instead) - // generate a bus error in the memory controller on bad - // addresses - // else if ($past(r_I[22])!=r_I[22]) - // `ASSERT(!o_pipe); - // else if (r_I[22:0] - $past(r_I[22:0])>23'h4) - // `ASSERT(!o_pipe); - end else if (!$past(o_valid)) - `ASSERT(!o_pipe); - // else - // assert(o_pipe); - end else if ($past(i_stalled)) - `ASSERT(o_pipe == $past(o_pipe)); - end - end - - always @(*) - `ASSERT((OPT_OPIPE)||(!o_pipe)); - // }}} - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_ce)) - &&($past(i_pf_valid))&&($past(w_mpy))) - `ASSERT((OPT_MPY)||(o_illegal)); - - always @(*) - if (o_valid) - `ASSERT((!o_phase)||(!o_early_branch)); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_valid))&&($past(o_ljmp))&&($past(!i_stalled))) - `ASSERT(!o_valid); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_early_branch_stb))) - begin - `ASSERT(!o_phase); - if (!$past(i_stalled)) - `ASSERT(!o_valid); - `ASSERT(!o_ljmp); - end - - // Unless another valid instruction comes along, once o_ljmp is asserted - // it should stay asserted until either a reset or an early branch - // strobe. - always @(posedge i_clk) - if ((OPT_EARLY_BRANCHING)&&(f_past_valid) - &&($past(o_ljmp))&&(!$past(pf_valid)) - &&(!$past(i_reset))&&(!$past(o_early_branch_stb))) - `ASSERT(o_ljmp); - - // o_ljmp should only ever be asserted following a valid prefetch - // input. Hence, if the prefetch input isn't valid, then o_ljmp - // should be left low - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(o_ljmp)) - &&( (!$past(pf_valid)) || (!$past(i_ce)) ) - &&( !$past(o_phase) ) - &&(!$past(i_reset))&&(!$past(o_early_branch_stb))) - `ASSERT(!o_ljmp); - - always @(posedge i_clk) - if ((OPT_EARLY_BRANCHING)&&(f_past_valid)&&($past(o_ljmp))&&(!o_ljmp) - &&(!$past(i_reset))) - `ASSERT((o_early_branch_stb)&&(!o_valid)); - - always @(posedge i_clk) - `ASSERT((!o_early_branch_stb)||(!o_ljmp)); - - always @(posedge i_clk) - `ASSERT((!o_valid)||(!o_ljmp)||(o_phase == o_pc[1])); - - always @(posedge i_clk) - if (!OPT_CIS) - begin - `ASSERT(!o_phase); - end else if (!f_insn_word[31]) - begin - `ASSERT(!o_phase); - end else if (o_phase) - `ASSERT(o_pc[1]); - - always @(*) - if ((o_early_branch)&&(!o_early_branch_stb)) - `ASSERT(!o_pipe); - - always @(*) - if (o_ljmp) - `ASSERT(!o_pipe); - - always @(*) - `ASSERT(o_dcdR == o_dcdA); - - always @(*) - if ((o_valid)&&(o_phase)) - begin - `ASSERT(!o_illegal); - `ASSERT(o_pc[1]); - `ASSERT(f_insn_word[31]); - end - - always @(posedge i_clk) - if ($rose(o_illegal)) - `ASSERT(o_valid || $past(o_early_branch || o_ljmp)); - - always @(*) - `ASSERT(o_branch_pc[1:0] == 2'b00); - always @(*) - `ASSERT(o_pc[0] == 1'b0); - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_pf_valid))&&(i_pf_valid)) - `ASSUME((i_reset)||($stable(i_gie))); - //////////////////////////////////////////////////////////////////////// - // - // Contract checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - wire fc_illegal, fc_wF, fc_ALU, fc_M, fc_DV, fc_FP, fc_break, - fc_lock, fc_wR, fc_rA, fc_rB, fc_prepipe, fc_sim; - wire [6:0] fc_dcdR, fc_dcdA, fc_dcdB; - wire [31:0] fc_I; - wire [3:0] fc_cond; - wire [3:0] fc_op; - wire [22:0] fc_sim_immv; - - f_idecode #( - // {{{ - .OPT_MPY(OPT_MPY), - .OPT_DIVIDE(OPT_DIVIDE), - .OPT_FPU(OPT_FPU), - .OPT_CIS(OPT_CIS), - .OPT_LOCK(OPT_LOCK), - .OPT_OPIPE(OPT_OPIPE), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_USERMODE(OPT_USERMODE), - .OPT_SIM(OPT_SIM) - // }}} - ) formal_decoder( - // {{{ - .i_instruction(f_insn_word), .i_phase(o_phase), - .i_gie(f_insn_gie), - .o_illegal(fc_illegal), - .o_dcdR(fc_dcdR), .o_dcdA(fc_dcdA), .o_dcdB(fc_dcdB), - .o_I(fc_I), .o_cond(fc_cond), .o_wF(fc_wF), .o_op(fc_op), - .o_ALU(fc_ALU), .o_M(fc_M), .o_DV(fc_DV), .o_FP(fc_FP), - .o_break(fc_break), .o_lock(fc_lock), - .o_wR(fc_wR), .o_rA(fc_rA), .o_rB(fc_rB), - .o_prepipe(fc_prepipe), .o_sim(fc_sim), .o_sim_immv(fc_sim_immv) - // }}} - ); - - always @(posedge i_clk) - if (o_valid && fc_illegal) - assert(o_illegal); - - always @(posedge i_clk) - if (o_valid && !o_illegal) - begin - if (i_reset) - begin - `ASSERT(fc_dcdR[3:0]== o_dcdR[3:0]); // - `ASSERT(fc_dcdA[3:0]== o_dcdA[3:0]); // - `ASSERT(fc_dcdB[3:0]== o_dcdB[3:0]); // - end else begin - `ASSERT(fc_dcdR== o_dcdR); // - `ASSERT(fc_dcdA== o_dcdA); // - `ASSERT(fc_dcdB== o_dcdB); // - end - `ASSERT(fc_I == o_I); - `ASSERT(o_zI == (fc_I == 0)); - `ASSERT(fc_cond== o_cond); - `ASSERT(fc_wF == o_wF); - `ASSERT(fc_op == o_op); - `ASSERT(fc_ALU == o_ALU); - `ASSERT(fc_M == o_M); - `ASSERT(fc_DV == o_DV); - `ASSERT(fc_FP == o_FP); - `ASSERT(fc_break== o_break); - `ASSERT(fc_lock == o_lock); - `ASSERT(fc_wR == o_wR); - `ASSERT(fc_rA == o_rA); - `ASSERT(fc_rB == o_rB); - `ASSERT(fc_sim == o_sim); - `ASSERT(fc_sim_immv == o_sim_immv); - `ASSERT(fc_prepipe == insn_is_pipeable); - end else - `ASSERT((i_reset)||(!insn_is_pipeable)); - - always @(*) - if (o_phase) - `ASSERT(r_nxt_half[14:0] == f_insn_word[14:0]); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!i_reset) - &&($past(i_ce))&&(o_valid)) - begin - `ASSERT(((fc_illegal) - ||$past((i_illegal)&&(!o_phase)) - ||$past((o_illegal)&&( o_phase)))== o_illegal); - end - - always @(posedge i_clk) - if ((!o_valid)||(o_illegal)) - `ASSERT(!insn_is_pipeable); - - generate if ((OPT_CIS)&&(OPT_EARLY_BRANCHING)) - begin - - always @(*) - if ((o_valid) - // LW - &&(o_M)&&(o_op[2:0]==3'b010) - // Zero immediate - &&(o_zI) - // Unconditional - &&(o_cond[3]) - // From PC to PC - &&(o_dcdR[5])&&(o_dcdB[5])) - begin - `ASSERT((o_ljmp) - ||((f_insn_word[31])&&(o_phase || o_illegal))); - end else if (o_valid) - `ASSERT(!o_ljmp); - - end endgenerate - // }}} -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/cpu/iscachable.v b/delete_later/rtl/cpu/iscachable.v deleted file mode 100644 index 6c34dd1..0000000 --- a/delete_later/rtl/cpu/iscachable.v +++ /dev/null @@ -1,61 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: ./iscachable.v -// {{{ -// Project: 10Gb Ethernet switch -// -// DO NOT EDIT THIS FILE! -// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT. -// DO NOT EDIT THIS FILE! -// -// CmdLine: autofpga autofpga -I .: -d -o . allclocks.txt global.txt wbdown.txt icape.txt version.txt gpio.txt spio.txt wbuconsole.txt zipmaster.txt bkram.txt ddr3.txt sdio.txt emmc.txt sdioscope.txt emmcscope.txt mem_bkram_only.txt mem_flash_bkram.txt i2ccpu.txt fan.txt sirefclk.txt i2cscope.txt -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// }}} -`default_nettype none -// -module iscachable( - // {{{ - input wire [28-1:0] i_addr, - output reg o_cachable - // }}} - ); - - always @(*) - begin - o_cachable = 1'b0; - // Bus master: wbwide - // Bus master: wb32 - // Bus master: wb32_sio - // bkram - if ((i_addr[27:0] & 28'he000000) == 28'h4000000) - o_cachable = 1'b1; - // ddr3_controller - if ((i_addr[27:0] & 28'h8000000) == 28'h8000000) - o_cachable = 1'b1; - end - -endmodule diff --git a/delete_later/rtl/cpu/memops.v b/delete_later/rtl/cpu/memops.v deleted file mode 100644 index e00e085..0000000 --- a/delete_later/rtl/cpu/memops.v +++ /dev/null @@ -1,1018 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: memops.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A memory unit to support a CPU. -// -// In the interests of code simplicity, this memory operator is -// susceptible to unknown results should a new command be sent to it -// before it completes the last one. Unpredictable results might then -// occurr. -// -// BIG ENDIAN -// Note that this core assumes a big endian bus, with the MSB -// of the bus word being the least bus address -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module memops #( - // {{{ - parameter ADDRESS_WIDTH=28, - parameter DATA_WIDTH=32, // CPU's register width - parameter BUS_WIDTH=32, - parameter [0:0] OPT_LOCK=1'b1, - WITH_LOCAL_BUS=1'b1, - OPT_ALIGNMENT_ERR=1'b1, - OPT_LOWPOWER=1'b0, - OPT_LITTLE_ENDIAN = 1'b0, - localparam AW=ADDRESS_WIDTH -`ifdef FORMAL - , parameter F_LGDEPTH = 2 -`endif - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // CPU interface - // {{{ - input wire i_stb, i_lock, - input wire [2:0] i_op, - input wire [31:0] i_addr, - input wire [DATA_WIDTH-1:0] i_data, - input wire [4:0] i_oreg, - // CPU outputs - output wire o_busy, - output reg o_rdbusy, - output reg o_valid, - output reg o_err, - output reg [4:0] o_wreg, - output reg [DATA_WIDTH-1:0] o_result, - // }}} - // Wishbone - // {{{ - output wire o_wb_cyc_gbl, - output wire o_wb_cyc_lcl, - output reg o_wb_stb_gbl, - output reg o_wb_stb_lcl, - output reg o_wb_we, - output reg [AW-1:0] o_wb_addr, - output reg [BUS_WIDTH-1:0] o_wb_data, - output reg [BUS_WIDTH/8-1:0] o_wb_sel, - // Wishbone inputs - input wire i_wb_stall, i_wb_ack, i_wb_err, - input wire [BUS_WIDTH-1:0] i_wb_data - // }}} - // }}} - ); - - // Declarations - // {{{ - localparam WBLSB = $clog2(BUS_WIDTH/8); -`ifdef FORMAL - wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding; -`endif - - wire misaligned; - reg r_wb_cyc_gbl, r_wb_cyc_lcl; - reg [2+WBLSB-1:0] r_op; - wire lock_gbl, lock_lcl; - wire lcl_bus, gbl_stb, lcl_stb; - - reg [BUS_WIDTH/8-1:0] oword_sel; - wire [BUS_WIDTH/8-1:0] pre_sel; - wire [BUS_WIDTH-1:0] pre_result; - - wire [1:0] oshift2; - wire [WBLSB-1:0] oshift; - - // }}} - - // misaligned - // {{{ - generate if (OPT_ALIGNMENT_ERR) - begin : GENERATE_ALIGNMENT_ERR - reg r_misaligned; - - always @(*) - casez({ i_op[2:1], i_addr[1:0] }) - 4'b01?1: r_misaligned = i_stb; // Words must be halfword aligned - 4'b0110: r_misaligned = i_stb; // Words must be word aligned - 4'b10?1: r_misaligned = i_stb; // Halfwords must be aligned - // 4'b11??: r_misaligned <= 1'b0; Byte access are never misaligned - default: r_misaligned = 1'b0; - endcase - - assign misaligned = r_misaligned; - end else begin : NO_MISALIGNMENT_ERR - assign misaligned = 1'b0; - end endgenerate - // }}} - - // lcl_stb, gbl_stb - // {{{ - assign lcl_bus = (WITH_LOCAL_BUS)&&(i_addr[31:24]==8'hff); - assign lcl_stb = (i_stb)&&( lcl_bus)&&(!misaligned); - assign gbl_stb = (i_stb)&&(!lcl_bus)&&(!misaligned); - // }}} - - // r_wb_cyc_gbl, r_wb_cyc_lcl - // {{{ - initial r_wb_cyc_gbl = 1'b0; - initial r_wb_cyc_lcl = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - end else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl)) - begin - if ((i_wb_ack)||(i_wb_err)) - begin - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - end - end else begin // New memory operation - // Grab the wishbone - r_wb_cyc_lcl <= (lcl_stb); - r_wb_cyc_gbl <= (gbl_stb); - end - // }}} - - // o_wb_stb_gbl - // {{{ - initial o_wb_stb_gbl = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_stb_gbl <= 1'b0; - else if ((i_wb_err)&&(r_wb_cyc_gbl)) - o_wb_stb_gbl <= 1'b0; - else if (gbl_stb) - o_wb_stb_gbl <= 1'b1; - else if (o_wb_cyc_gbl) - o_wb_stb_gbl <= (o_wb_stb_gbl)&&(i_wb_stall); - // }}} - - // o_wb_stb_lcl - // {{{ - initial o_wb_stb_lcl = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_stb_lcl <= 1'b0; - else if ((i_wb_err)&&(r_wb_cyc_lcl)) - o_wb_stb_lcl <= 1'b0; - else if (lcl_stb) - o_wb_stb_lcl <= 1'b1; - else if (o_wb_cyc_lcl) - o_wb_stb_lcl <= (o_wb_stb_lcl)&&(i_wb_stall); - // }}} - - // o_wb_we, o_wb_data, o_wb_sel - // {{{ - always @(*) - begin - oword_sel = 0; - - casez({ OPT_LITTLE_ENDIAN, i_op[2:1], i_addr[1:0] }) - 5'b00???: oword_sel[3:0] = 4'b1111; - 5'b0100?: oword_sel[3:0] = 4'b1100; - 5'b0101?: oword_sel[3:0] = 4'b0011; - 5'b01100: oword_sel[3:0] = 4'b1000; - 5'b01101: oword_sel[3:0] = 4'b0100; - 5'b01110: oword_sel[3:0] = 4'b0010; - 5'b01111: oword_sel[3:0] = 4'b0001; - // - // verilator coverage_off - 5'b10???: oword_sel[3:0] = 4'b1111; - 5'b1100?: oword_sel[3:0] = 4'b0011; - 5'b1101?: oword_sel[3:0] = 4'b1100; - 5'b11100: oword_sel[3:0] = 4'b0001; - 5'b11101: oword_sel[3:0] = 4'b0010; - 5'b11110: oword_sel[3:0] = 4'b0100; - 5'b11111: oword_sel[3:0] = 4'b1000; - // verilator coverage_on - // - default: oword_sel[3:0] = 4'b1111; - endcase - end - - // pre_sel - // {{{ - generate if (BUS_WIDTH == 32) - begin : COPY_PRESEL - assign pre_sel = oword_sel; - end else if (OPT_LITTLE_ENDIAN) - begin : GEN_LILPRESEL - wire [WBLSB-3:0] shift; - - assign shift = i_addr[WBLSB-1:2]; - assign pre_sel = oword_sel << (4 * i_addr[WBLSB-1:2]); - end else begin : GEN_PRESEL - wire [WBLSB-3:0] shift; - - assign shift = {(WBLSB-2){1'b1}} ^ i_addr[WBLSB-1:2]; - assign pre_sel = oword_sel << (4 * shift); - end endgenerate - // }}} - - assign oshift = i_addr[WBLSB-1:0]; - assign oshift2 = i_addr[1:0]; - - initial o_wb_we = 1'b0; - initial o_wb_data = 0; - initial o_wb_sel = 0; - always @(posedge i_clk) - if (i_stb) - begin - o_wb_we <= i_op[0]; - if (OPT_LOWPOWER) - begin - if (lcl_bus) - begin - // {{{ - o_wb_data <= 0; - casez({ OPT_LITTLE_ENDIAN, i_op[2:1] }) - 3'b010: o_wb_data[31:0] <= { i_data[15:0], {(16){1'b0}} } >> (8*oshift2); - 3'b011: o_wb_data[31:0] <= { i_data[ 7:0], {(24){1'b0}} } >> (8*oshift2); - 3'b00?: o_wb_data[31:0] <= i_data[31:0]; - // - // verilator coverage_off - 3'b110: o_wb_data <= { {(BUS_WIDTH-16){1'b0}}, i_data[15:0] } << (8*oshift2); - 3'b111: o_wb_data <= { {(BUS_WIDTH-8){1'b0}}, i_data[ 7:0] } << (8*oshift2); - 3'b10?: o_wb_data <= { {(BUS_WIDTH-32){1'b0}}, i_data[31:0] } << (8*oshift2); - // verilator coverage_on - // - endcase - // }}} - end else begin - // {{{ - casez({ OPT_LITTLE_ENDIAN, i_op[2:1] }) - 3'b010: o_wb_data <= { i_data[15:0], {(BUS_WIDTH-16){1'b0}} } >> (8*oshift); - 3'b011: o_wb_data <= { i_data[ 7:0], {(BUS_WIDTH- 8){1'b0}} } >> (8*oshift); - 3'b00?: o_wb_data <= { i_data[31:0], {(BUS_WIDTH-32){1'b0}} } >> (8*oshift); - // - 3'b110: o_wb_data <= { {(BUS_WIDTH-16){1'b0}}, i_data[15:0] } << (8*oshift); - 3'b111: o_wb_data <= { {(BUS_WIDTH-8){1'b0}}, i_data[ 7:0] } << (8*oshift); - 3'b10?: o_wb_data <= { {(BUS_WIDTH-32){1'b0}}, i_data[31:0] } << (8*oshift); - // - endcase - // }}} - end - end else - casez({ i_op[2:1] }) - 2'b10: o_wb_data <= { (BUS_WIDTH/16){ i_data[15:0] } }; - 2'b11: o_wb_data <= { (BUS_WIDTH/ 8){ i_data[7:0] } }; - default: o_wb_data <= {(BUS_WIDTH/32){i_data}}; - endcase - - if (lcl_bus) - begin - o_wb_addr <= i_addr[2 +: (AW+2>32 ? (32-2) : AW)]; - o_wb_sel <= oword_sel; - end else begin - o_wb_addr <= i_addr[WBLSB +: (AW+WBLSB>32 ? (32-WBLSB) : AW)]; - o_wb_sel <= pre_sel; - end - - r_op <= { i_op[2:1] , i_addr[WBLSB-1:0] }; - end else if ((OPT_LOWPOWER)&&(!o_wb_cyc_gbl)&&(!o_wb_cyc_lcl)) - begin - o_wb_we <= 1'b0; - o_wb_addr <= 0; - o_wb_data <= {(BUS_WIDTH){1'b0}}; - o_wb_sel <= {(BUS_WIDTH/8){1'b0}}; - end - // }}} - - // o_valid - // {{{ - initial o_valid = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_valid <= 1'b0; - else - o_valid <= (((o_wb_cyc_gbl)||(o_wb_cyc_lcl)) - &&(i_wb_ack)&&(!o_wb_we)); - // }}} - - // o_err - // {{{ - initial o_err = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_err <= 1'b0; - else if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl)) - o_err <= i_wb_err; - else if ((i_stb)&&(!o_busy)) - o_err <= misaligned; - else - o_err <= 1'b0; - // }}} - - assign o_busy = (r_wb_cyc_gbl)||(r_wb_cyc_lcl); - - // o_rdbusy - // {{{ - initial o_rdbusy = 1'b0; - always @(posedge i_clk) - if (i_reset|| ((o_wb_cyc_gbl || o_wb_cyc_lcl)&&(i_wb_err || i_wb_ack))) - o_rdbusy <= 1'b0; - else if (i_stb && !i_op[0] && !misaligned) - o_rdbusy <= 1'b1; - else if (o_valid) - o_rdbusy <= 1'b0; - // }}} - - always @(posedge i_clk) - if (i_stb) - o_wreg <= i_oreg; - - // o_result - // {{{ - generate if (OPT_LITTLE_ENDIAN) - begin : LILEND_RESULT - - assign pre_result = i_wb_data >> (8*r_op[$clog2(BUS_WIDTH/8)-1:0]); - - end else begin : BIGEND_RESULT - - assign pre_result = i_wb_data << (8*r_op[$clog2(BUS_WIDTH/8)-1:0]); - - end endgenerate - - always @(posedge i_clk) - if ((OPT_LOWPOWER)&&(!i_wb_ack)) - o_result <= 32'h0; - else if (o_wb_cyc_lcl && (BUS_WIDTH != 32)) - begin - // The Local bus is naturally (and only) a 32-bit bus - casez({ OPT_LITTLE_ENDIAN, r_op[WBLSB +: 2], r_op[1:0] }) - 5'b?01??: o_result <= i_wb_data[31:0]; - // - // Big endian - 5'b0100?: o_result <= { 16'h00, i_wb_data[31:16] }; - 5'b0101?: o_result <= { 16'h00, i_wb_data[15: 0] }; - 5'b01100: o_result <= { 24'h00, i_wb_data[31:24] }; - 5'b01101: o_result <= { 24'h00, i_wb_data[23:16] }; - 5'b01110: o_result <= { 24'h00, i_wb_data[15: 8] }; - 5'b01111: o_result <= { 24'h00, i_wb_data[ 7: 0] }; - // - // Little endian : Same bus result, just grab a different bits - // from the bus return to send back to the CPU. - // verilator coverage_off - 5'b1100?: o_result <= { 16'h00, i_wb_data[15: 0] }; - 5'b1101?: o_result <= { 16'h00, i_wb_data[31:16] }; - 5'b11100: o_result <= { 24'h00, i_wb_data[ 7: 0] }; - 5'b11101: o_result <= { 24'h00, i_wb_data[15: 8] }; - 5'b11110: o_result <= { 24'h00, i_wb_data[23:16] }; - 5'b11111: o_result <= { 24'h00, i_wb_data[31:24] }; - // verilator coverage_on - default: o_result <= i_wb_data[31:0]; - endcase - end else begin - casez({ OPT_LITTLE_ENDIAN, r_op[$clog2(BUS_WIDTH/8) +: 2] }) - // Word - // - // Big endian - 3'b00?: o_result <= pre_result[BUS_WIDTH-1:BUS_WIDTH-32]; - 3'b010: o_result <= { 16'h00, pre_result[BUS_WIDTH-1:BUS_WIDTH-16] }; - 3'b011: o_result <= { 24'h00, pre_result[BUS_WIDTH-1:BUS_WIDTH-8] }; - // - // Little endian : Same bus result, just grab a different bits - // from the bus return to send back to the CPU. - // verilator coverage_off - 3'b10?: o_result <= pre_result[31: 0]; - 3'b110: o_result <= { 16'h00, pre_result[15: 0] }; - 3'b111: o_result <= { 24'h00, pre_result[ 7: 0] }; - // verilator coverage_on - // - // Just to have an (unused) default - // default: o_result <= pre_result[31:0]; (Messes w/ coverage) - endcase - end - // }}} - - // lock_gbl and lock_lcl - // {{{ - generate - if (OPT_LOCK) - begin : GEN_LOCK - // {{{ - reg r_lock_gbl, r_lock_lcl; - - initial r_lock_gbl = 1'b0; - initial r_lock_lcl = 1'b0; - - always @(posedge i_clk) - if (i_reset) - begin - r_lock_gbl <= 1'b0; - r_lock_lcl <= 1'b0; - end else if (((i_wb_err)&&((r_wb_cyc_gbl)||(r_wb_cyc_lcl))) - ||(misaligned)) - begin - // Kill the lock if - // there's a bus error, or - // User requests a misaligned memory op - r_lock_gbl <= 1'b0; - r_lock_lcl <= 1'b0; - end else begin - // Kill the lock if - // i_lock goes down - // User starts on the global bus, then switches - // to local or vice versa - r_lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl)) - &&(!lcl_stb); - r_lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl)) - &&(!gbl_stb); - end - - assign lock_gbl = r_lock_gbl; - assign lock_lcl = r_lock_lcl; - - assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl); - assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl); - // }}} - end else begin : NO_LOCK - // {{{ - assign o_wb_cyc_gbl = (r_wb_cyc_gbl); - assign o_wb_cyc_lcl = (r_wb_cyc_lcl); - - assign { lock_gbl, lock_lcl } = 2'b00; - - // Make verilator happy - // verilator lint_off UNUSED - wire [2:0] lock_unused; - assign lock_unused = { i_lock, lock_gbl, lock_lcl }; - // verilator lint_on UNUSED - // }}} - end endgenerate - // }}} - -`ifdef VERILATOR - always @(posedge i_clk) - if ((r_wb_cyc_gbl)||(r_wb_cyc_lcl)) - assert(!i_stb); -`endif - - - // Make verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, pre_result }; - generate if (AW < 22) - begin : TOO_MANY_ADDRESS_BITS - - wire [(21-AW):0] unused_addr; - assign unused_addr = i_addr[23:(AW+2)]; - - end endgenerate - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`define ASSERT assert -`ifdef MEMOPS -`define ASSUME assume -`else -`define ASSUME assert -`endif - reg f_past_valid; - - reg [2:0] fcpu_op; - reg [31:0] fcpu_addr, fcpu_data;; - reg [BUS_WIDTH-1:0] fbus_data, fpre_data; - reg [$clog2(BUS_WIDTH/8)-1:0] fcpu_shift; - reg fcpu_local, fcpu_misaligned; - reg [BUS_WIDTH/8-1:0] fbus_sel, fpre_sel; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - `ASSUME(i_reset); - - //////////////////////////////////////////////////////////////////////// - // - // Bus properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial `ASSUME(!i_stb); - - wire f_cyc, f_stb; - assign f_cyc = (o_wb_cyc_gbl)||(o_wb_cyc_lcl); - assign f_stb = (o_wb_stb_gbl)||(o_wb_stb_lcl); - - fwb_master #( - // {{{ - .AW(AW), .F_LGDEPTH(F_LGDEPTH), .DW(BUS_WIDTH), - .F_OPT_RMW_BUS_OPTION(OPT_LOCK), - .F_OPT_DISCONTINUOUS(OPT_LOCK) - // }}} - ) f_wb( - // {{{ - i_clk, i_reset, - f_cyc, f_stb, o_wb_we, o_wb_addr, o_wb_data, o_wb_sel, - i_wb_ack, i_wb_stall, i_wb_data, i_wb_err, - f_nreqs, f_nacks, f_outstanding - // }}} - ); - - - // Rule: Only one of the two CYC's may be valid, never both - always @(posedge i_clk) - `ASSERT((!o_wb_cyc_gbl)||(!o_wb_cyc_lcl)); - - // Rule: Only one of the two STB's may be valid, never both - always @(posedge i_clk) - `ASSERT((!o_wb_stb_gbl)||(!o_wb_stb_lcl)); - - // Rule: if WITH_LOCAL_BUS is ever false, neither the local STB nor CYC - // may be valid - always @(*) - if (!WITH_LOCAL_BUS) - begin - `ASSERT(!o_wb_cyc_lcl); - `ASSERT(!o_wb_stb_lcl); - end - - // Rule: If the global CYC is ever true, the LCL one cannot be true - // on the next clock without an intervening idle of both - always @(posedge i_clk) - if ((f_past_valid)&&($past(r_wb_cyc_gbl))) - `ASSERT(!r_wb_cyc_lcl); - - // Same for if the LCL CYC is true - always @(posedge i_clk) - if ((f_past_valid)&&($past(r_wb_cyc_lcl))) - `ASSERT(!r_wb_cyc_gbl); - - // STB can never be true unless CYC is also true - always @(posedge i_clk) - if (o_wb_stb_gbl) - `ASSERT(r_wb_cyc_gbl); - - always @(posedge i_clk) - if (o_wb_stb_lcl) - `ASSERT(r_wb_cyc_lcl); - - // This core only ever has zero or one outstanding transaction(s) - always @(posedge i_clk) - if ((o_wb_stb_gbl)||(o_wb_stb_lcl)) - begin - `ASSERT(f_outstanding == 0); - end else - `ASSERT((f_outstanding == 0)||(f_outstanding == 1)); - - // The LOCK function only allows up to two transactions (at most) - // before CYC must be dropped. - always @(posedge i_clk) - if ((o_wb_stb_gbl)||(o_wb_stb_lcl)) - begin - if (OPT_LOCK) - begin - `ASSERT((f_outstanding == 0)||(f_outstanding == 1)); - end else - `ASSERT(f_nreqs <= 1); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // CPU properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg f_done; - wire [(F_LGDEPTH-1):0] cpu_outstanding; - wire f_pc, f_rdbusy, f_gie, f_read_cycle; - wire [4:0] f_last_reg; - wire [4:0] f_addr_reg; - // Verilator lint_off UNDRIVEN - (* anyseq *) reg [4:0] f_areg; - // Verilator lint_on UNDRIVEN - - assign f_rdbusy = f_cyc && (f_stb || f_outstanding > 0) && !o_wb_we; - - initial f_done = 1'b0; - always @(posedge i_clk) - if (i_reset) - f_done <= 1'b0; - else - f_done <= ((o_wb_cyc_gbl)||(o_wb_cyc_lcl))&&(i_wb_ack); - - fmem #( - // {{{ - .F_LGDEPTH(F_LGDEPTH), - .OPT_LOCK(OPT_LOCK), - .OPT_MAXDEPTH(1) - // }}} - ) fmemi( - // {{{ - .i_clk(i_clk), - .i_sys_reset(i_reset), - .i_cpu_reset(i_reset), - .i_stb(i_stb), - .i_pipe_stalled(o_busy), - .i_clear_cache(1'b0), - .i_lock(i_lock), - .i_op(i_op), .i_addr(i_addr), .i_data(i_data), .i_oreg(i_oreg), - .i_areg(f_areg), - .i_busy(o_busy), - .i_rdbusy(f_rdbusy), - .i_valid(o_valid), .i_done(f_done), .i_err(o_err), - .i_wreg(o_wreg), .i_result(o_result), - .f_outstanding(cpu_outstanding), - .f_pc(f_pc), - .f_gie(f_gie), - .f_read_cycle(f_read_cycle), - .f_last_reg(f_last_reg), .f_addr_reg(f_addr_reg) - // }}} - ); - - always @(*) - if (!o_err) - assert(cpu_outstanding == f_outstanding + (f_stb ? 1:0) - + ((f_done || o_err) ? 1:0)); - - always @(*) - assert(cpu_outstanding <= 1); - - always @(*) - if (f_pc) - begin - assert(o_wreg[3:1] == 3'h7); - end else if (f_rdbusy) - assert(o_wreg[3:1] != 3'h7); - - always @(*) - if (o_busy) - assert(o_wreg[4] == f_gie); - - always @(*) - if (!o_err) - assert(f_rdbusy == o_rdbusy); - - always @(*) - if (o_busy) - assert(o_wb_we == !f_read_cycle); - - always @(*) - if (cpu_outstanding > 0) - assert(f_last_reg == o_wreg); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Tying the two together - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Following any i_stb request, assuming we are idle, immediately - // begin a bus transaction - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_stb)) - &&(!$past(f_cyc))&&(!$past(i_reset))) - begin - if ($past(misaligned)) - begin - `ASSERT(!f_cyc); - `ASSERT(!o_busy); - `ASSERT(o_err); - `ASSERT(!o_valid); - end else begin - `ASSERT(f_cyc); - `ASSERT(o_busy); - end - end - -// always @(posedge i_clk) -// if (o_busy) -// `ASSUME(!i_stb); - - always @(*) - if (o_err || o_valid) - `ASSERT(!o_busy); - - always @(posedge i_clk) - if (o_wb_cyc_gbl) - `ASSERT((o_busy)||(lock_gbl)); - - always @(posedge i_clk) - if (o_wb_cyc_lcl) - `ASSERT((o_busy)||(lock_lcl)); - - always @(posedge i_clk) - if (f_outstanding > 0) - `ASSERT(o_busy); - - // If a transaction ends in an error, send o_err on the output port. - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset)) - begin - if (($past(f_cyc))&&($past(i_wb_err))) - begin - `ASSERT(o_err); - end else if ($past(misaligned)) - `ASSERT(o_err); - end - - // Always following a successful ACK, return an O_VALID value. - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset)) - begin - if(($past(f_cyc))&&($past(i_wb_ack)) - &&(!$past(o_wb_we))) - begin - `ASSERT(o_valid); - end else if ($past(misaligned)) - begin - `ASSERT((!o_valid)&&(o_err)); - end else - `ASSERT(!o_valid); - end - - always @(posedge i_clk) - if (i_stb) - begin - fcpu_op <= i_op; - fcpu_addr <= i_addr; - fcpu_data <= i_data; - end - - always @(*) - begin - fcpu_local = (&fcpu_addr[31:24]) && WITH_LOCAL_BUS; - - if (OPT_LITTLE_ENDIAN) - begin - // {{{ - casez(fcpu_op[2:1]) - 2'b11: fpre_sel = { {(BUS_WIDTH/8-1){1'b0}}, 1'b1 }; - 2'b10: fpre_sel = { {(BUS_WIDTH/8-2){1'b0}}, 2'b11 }; - 2'b0?: fpre_sel = { {(BUS_WIDTH/8-4){1'b0}}, 4'b1111 }; - endcase - - casez(fcpu_op[2:1]) - 2'b11: fpre_data = { {(BUS_WIDTH- 8){1'b0}}, fcpu_data[ 7:0] }; - 2'b10: fpre_data = { {(BUS_WIDTH-16){1'b0}}, fcpu_data[15:0] }; - 2'b0?: fpre_data = { {(BUS_WIDTH-32){1'b0}}, fcpu_data[31:0] }; - endcase - // }}} - end else if (fcpu_local) - begin - // {{{ - fpre_sel = 0; - casez(fcpu_op[2:1]) - 2'b11: fpre_sel[3:0] = 4'b1000; - 2'b10: fpre_sel[3:0] = 4'b1100; - 2'b0?: fpre_sel[3:0] = 4'b1111; - endcase - - fpre_data = 0; - casez(fcpu_op[2:1]) - 2'b11: fpre_data[31:0] = { fcpu_data[ 7:0], {(24){1'b0}} }; - 2'b10: fpre_data[31:0] = { fcpu_data[15:0], {(16){1'b0}} }; - 2'b0?: fpre_data[31:0] = fcpu_data[31:0]; - endcase - // }}} - end else begin - // {{{ - casez(fcpu_op[2:1]) - 2'b11: fpre_sel = { 1'b1, {(BUS_WIDTH/8-1){1'b0}} }; - 2'b10: fpre_sel = { 2'b11, {(BUS_WIDTH/8-2){1'b0}} }; - 2'b0?: fpre_sel = { 4'b1111, {(BUS_WIDTH/8-4){1'b0}} }; - endcase - - casez(fcpu_op[2:1]) - 2'b11: fpre_data = { fcpu_data[ 7:0], {(BUS_WIDTH- 8){1'b0}} }; - 2'b10: fpre_data = { fcpu_data[15:0], {(BUS_WIDTH-16){1'b0}} }; - 2'b0?: fpre_data = { fcpu_data[31:0], {(BUS_WIDTH-32){1'b0}} }; - endcase - // }}} - end - - - casez({ fcpu_op[2:1], fcpu_addr[1:0] }) - 4'b01?1: fcpu_misaligned = 1'b1; // Words must be halfword aligned - 4'b0110: fcpu_misaligned = 1'b1; // Words must be word aligned - 4'b10?1: fcpu_misaligned = 1'b1; // Halfwords must be aligned - // 4'b11??: fcpu_misaligned <= 1'b0; Byte access are never misaligned - default: fcpu_misaligned = 1'b0; - endcase - - if (fcpu_local) - begin - fcpu_shift = fcpu_addr[1:0]; - if (OPT_LITTLE_ENDIAN) - begin - fbus_sel = fpre_sel << fcpu_shift; - fbus_data = fpre_data << (8*fcpu_shift); - end else begin - fbus_sel = fpre_sel >> (fcpu_shift + (DATA_WIDTH/8-4)); - fbus_data = fpre_data >> (8*(fcpu_shift + (DATA_WIDTH/8-4))); - end - end else begin - fcpu_shift = fcpu_addr[WBLSB-1:0]; - if (OPT_LITTLE_ENDIAN) - begin - fbus_sel = fpre_sel << fcpu_shift; - fbus_data = fpre_data << (8*fcpu_shift); - end else begin - fbus_sel = fpre_sel >> fcpu_shift; - fbus_data = fpre_data >> (8*fcpu_shift); - end - end - - if (!OPT_LOWPOWER) - casez(fcpu_op[2:1]) - 2'b11: fbus_data = {(BUS_WIDTH/ 8){fcpu_data[ 7:0] } }; - 2'b10: fbus_data = {(BUS_WIDTH/16){fcpu_data[15:0] } }; - 2'b0?: fbus_data = {(BUS_WIDTH/32){fcpu_data[31:0] } }; - endcase - end - - always @(*) - if (OPT_ALIGNMENT_ERR && fcpu_misaligned) - assert(!o_valid && !f_cyc); - - always @(*) - if (f_stb) - begin - if (fcpu_local) - begin - assert(o_wb_stb_lcl); - assert(o_wb_addr == fcpu_addr[AW+1:2]); - end else begin - assert(o_wb_stb_gbl); - assert(o_wb_addr == fcpu_addr[WBLSB +: AW]); - end - - if (fcpu_op[0]) - begin - `ASSERT(o_wb_we); - `ASSERT(fcpu_misaligned || o_wb_sel == fbus_sel); - `ASSERT(fcpu_misaligned || o_wb_data == fbus_data); - end else begin - `ASSERT(!o_wb_we); - end - end - - always @(*) - if (f_cyc) - assert(o_wb_cyc_lcl == fcpu_local); - - initial o_wb_we = 1'b0; - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_stb))) - begin - // On a write, assert o_wb_we should be true - assert( $past(i_op[0]) == o_wb_we); - end - - always @(posedge i_clk) - if (o_wb_stb_lcl) - `ASSERT(fcpu_local); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(misaligned))) - begin - `ASSERT(!o_wb_cyc_gbl); - `ASSERT(!o_wb_cyc_lcl); - `ASSERT(!o_wb_stb_gbl); - `ASSERT(!o_wb_stb_lcl); - `ASSERT(o_err); - end - -// always @(posedge i_clk) -// if ((!f_past_valid)||($past(i_reset))) -// `ASSUME(!i_stb); - - always @(posedge i_clk) - if ((f_past_valid)&&(OPT_LOCK) - &&(!$past(i_reset))&&(!$past(i_wb_err)) - &&(!$past(misaligned)) - &&(!$past(lcl_stb)) - &&($past(i_lock))&&($past(lock_gbl))) - assert(lock_gbl); - - always @(posedge i_clk) - if ((f_past_valid)&&(OPT_LOCK) - &&(!$past(i_reset))&&(!$past(i_wb_err)) - &&(!$past(misaligned)) - &&(!$past(lcl_stb)) - &&($past(o_wb_cyc_gbl))&&($past(i_lock)) - &&($past(lock_gbl))) - assert(o_wb_cyc_gbl); - - always @(posedge i_clk) - if ((f_past_valid)&&(OPT_LOCK) - &&(!$past(i_reset))&&(!$past(i_wb_err)) - &&(!$past(misaligned)) - &&(!$past(gbl_stb)) - &&($past(o_wb_cyc_lcl))&&($past(i_lock)) - &&($past(lock_lcl))) - assert(o_wb_cyc_lcl); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - cover(i_wb_ack); - - // Cover a response on the same clock it is made - always @(posedge i_clk) - cover((o_wb_stb_gbl)&&(i_wb_ack)); - - // Cover a response a clock later - always @(posedge i_clk) - cover((o_wb_stb_gbl)&&(i_wb_ack)); - - always @(posedge i_clk) - cover(f_done); - - always @(posedge i_clk) - cover(f_done && !o_busy); - - generate if (WITH_LOCAL_BUS) - begin - - // Same things on the local bus - always @(posedge i_clk) - cover((o_wb_cyc_lcl)&&(!o_wb_stb_lcl)&&(i_wb_ack)); - always @(posedge i_clk) - cover((o_wb_stb_lcl)&&(i_wb_ack)); - - end endgenerate - // }}} - - // Make Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, f_nacks, f_addr_reg }; - // Verilator lint_on UNUSED - // }}} -`endif -// }}} -endmodule -// -// -// Usage (from yosys): -// (BFOR) (!ZOI,ALIGN) (ZOI,ALIGN) (!ZOI,!ALIGN) -// Cells 230 226 281 225 -// FDRE 114 116 116 116 -// LUT2 17 23 76 19 -// LUT3 9 23 17 20 -// LUT4 15 4 11 14 -// LUT5 18 18 7 15 -// LUT6 33 18 54 38 -// MUX7 16 12 2 -// MUX8 8 1 1 -// -// diff --git a/delete_later/rtl/cpu/mpyop.v b/delete_later/rtl/cpu/mpyop.v deleted file mode 100644 index f3067b4..0000000 --- a/delete_later/rtl/cpu/mpyop.v +++ /dev/null @@ -1,428 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: mpyop.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This code has been pulled from the cpuops.v file so as to -// encapsulate the multiply component--the one component that -// (can't be) formally verified well, and so must be abstracted away. -// This separation was done to support potential future abstraction. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module mpyop #( - // {{{ - // The following parameter selects which multiply algorithm we - // use. Timing performance is strictly dependent upon it. - // OPY_MPY - // ------ - // 0 No multiply - // 1 Single op multiply, same timing as an ADD - // 2 Two clock multiply - // 3 Three clock multiply, standard Xlnx DSP timing - // 4 Three clock multiply, Xilinx Spartan DSP timing - // (Anything else) -- low logic slow multiply - // 36 Required setting for the TB to work on the low - // logic slow multiply - parameter OPT_MPY = 1, - parameter [0:0] OPT_LOWPOWER = 1'b0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, i_stb, - // - // Three types of multiply operations. - // 2'b00: 32x32 multiply, returning the low order 32 bits - // 2'b10: 32x32 unsigned multiply, returning upper 32 bits - // 2'b11: 32x32 signed multiply, returning upper 32 bits - input wire [1:0] i_op, - input wire [31:0] i_a, i_b, - output wire o_valid, // True if the result is valid - output wire o_busy, // - output wire [63:0] o_result, // multiply result - output wire o_hi // Return the high half of mpy - // }}} - ); - - - // A 4-way multiplexer can be done in one 6-LUT. - // A 16-way multiplexer can therefore be done in 4x 6-LUT's with - // the Xilinx multiplexer fabric that follows. - // Given that we wish to apply this multiplexer approach to 33-bits, - // this will cost a minimum of 132 6-LUTs. - -// i_stb instead of this_is_a_multiply_op -// o_result -// o_busy -// o_done - generate - if (OPT_MPY == 0) - begin : MPYNONE // No multiply support. - // {{{ - assign o_result = 64'h00; - assign o_busy = 1'b0; - assign o_valid = i_stb; - assign o_hi = 1'b0; // Not needed - -`ifdef VERILATOR - // verilator coverage_off - // verilator lint_off UNUSED - wire mpy_unused; - assign mpy_unused = &{ 1'b0, i_clk, i_reset, i_stb, i_op, i_a, i_b }; - // verilator lint_on UNUSED - // verilator coverage_on -`endif - // }}} - end else begin : IMPY - if (OPT_MPY == 1) - begin : MPY1CK // Our single clock option (no extra clocks) - // {{{ - wire signed [63:0] w_mpy_a_input, w_mpy_b_input; - - assign w_mpy_a_input = {{(32){(i_a[31])&(i_op[0])}},i_a[31:0]}; - assign w_mpy_b_input = {{(32){(i_b[31])&(i_op[0])}},i_b[31:0]}; - - assign o_result = (OPT_LOWPOWER && !i_stb) ? 0 : (w_mpy_a_input * w_mpy_b_input); - - assign o_busy = 1'b0; - assign o_valid = i_stb; - assign o_hi = i_op[1]; - -`ifdef VERILATOR - // verilator coverage_off - // verilator lint_off UNUSED - wire mpy_unused; - assign mpy_unused = &{ 1'b0, i_clk, i_reset, i_stb, i_op[1] }; - // verilator lint_on UNUSED - // verilator coverage_on -`endif - // }}} - end else begin: MPN1 - if (OPT_MPY == 2) - begin : MPY2CK // Our two clock option (ALU must pause for 1 clock) - // {{{ - - // Declarations - // {{{ - reg signed [63:0] r_mpy_a_input, r_mpy_b_input; - reg mpypipe, r_hi; - // }}} - - // r_mpy_?_input: Register the inputs - // {{{ - always @(posedge i_clk) - if (!OPT_LOWPOWER || i_stb) - begin - r_mpy_a_input <={{(32){(i_a[31])&(i_op[0])}},i_a[31:0]}; - r_mpy_b_input <={{(32){(i_b[31])&(i_op[0])}},i_b[31:0]}; - end else begin - r_mpy_a_input <= 0; - r_mpy_b_input <= 0; - end - // }}} - - assign o_result = r_mpy_a_input * r_mpy_b_input; - assign o_busy = 1'b0; - - // mpypipe - // {{{ - initial mpypipe = 1'b0; - always @(posedge i_clk) - if (i_reset) - mpypipe <= 1'b0; - else - mpypipe <= (i_stb); - // }}} - - assign o_valid = mpypipe; // this_is_a_multiply_op; - - // o_hi - // {{{ - always @(posedge i_clk) - if (i_stb) - r_hi <= i_op[1]; - - assign o_hi = r_hi; - // }}} - // }}} - end else begin : MPN2 - if (OPT_MPY == 3) - begin : MPY3CK // Our three clock option (ALU pauses for 2 clocks) - // {{{ - - // Declarations - // {{{ - reg signed [63:0] r_smpy_result; - reg [63:0] r_umpy_result; - reg signed [31:0] r_mpy_a_input, r_mpy_b_input; - reg [1:0] mpypipe; - reg [1:0] r_sgn; - reg r_hi; - // }}} - - // mpypipe (FSM state) - // {{{ - initial mpypipe = 2'b0; - always @(posedge i_clk) - if (i_reset) - mpypipe <= 2'b0; - else - mpypipe <= { mpypipe[0], i_stb }; - // }}} - - // First clock : register r_mpy_?_input, r_sgn - // {{{ - always @(posedge i_clk) - r_sgn <= { r_sgn[0], - (i_op[0] && (!OPT_LOWPOWER || i_stb)) }; - - always @(posedge i_clk) - if (!OPT_LOWPOWER || i_stb) - begin - r_mpy_a_input <= i_a[31:0]; - r_mpy_b_input <= i_b[31:0]; - end else begin - r_mpy_a_input <= 0; - r_mpy_b_input <= 0; - end - // }}} - - // Second clock : perform the multiply - // {{{ -`ifdef VERILATOR - // Veri1ator only implementation - // {{{ - wire signed [63:0] s_mpy_a_input, s_mpy_b_input; - wire [63:0] u_mpy_a_input, u_mpy_b_input; - - assign s_mpy_a_input = {{(32){r_mpy_a_input[31]}},r_mpy_a_input}; - assign s_mpy_b_input = {{(32){r_mpy_b_input[31]}},r_mpy_b_input}; - assign u_mpy_a_input = {32'h00,r_mpy_a_input}; - assign u_mpy_b_input = {32'h00,r_mpy_b_input}; - always @(posedge i_clk) - if (!OPT_LOWPOWER || mpypipe[0]) - r_smpy_result <= s_mpy_a_input * s_mpy_b_input; - always @(posedge i_clk) - if (!OPT_LOWPOWER || mpypipe[0]) - r_umpy_result <= u_mpy_a_input * u_mpy_b_input; - // }}} -`else - // Synthesis implementation - // {{{ - wire [31:0] u_mpy_a_input, u_mpy_b_input; - - assign u_mpy_a_input = r_mpy_a_input; - assign u_mpy_b_input = r_mpy_b_input; - - always @(posedge i_clk) - if (!OPT_LOWPOWER || mpypipe[0]) - r_smpy_result <= r_mpy_a_input * r_mpy_b_input; - always @(posedge i_clk) - if (!OPT_LOWPOWER || mpypipe[0]) - r_umpy_result <= u_mpy_a_input * u_mpy_b_input; - // }}} -`endif - - always @(posedge i_clk) - if (i_stb) - r_hi <= i_op[1]; - - assign o_hi = r_hi; - assign o_busy = mpypipe[0]; - assign o_result = (r_sgn[1])?r_smpy_result:r_umpy_result; - assign o_valid = mpypipe[1]; - // }}} - - // Results are then available and registered on the third clock - // }}} - end else begin : MPN3 - if (OPT_MPY == 4) - begin : MPY4CK // The four clock option, polynomial multiplication - // {{{ - // Declarations - // {{{ - reg [63:0] r_mpy_result; - reg [31:0] r_mpy_a_input, r_mpy_b_input; - reg r_mpy_signed, r_hi; - reg [2:0] mpypipe; - reg [31:0] pp_f, pp_l; // F and L from FOIL - reg [32:0] pp_oi; // The O and I from FOIL - reg [32:0] pp_s; - // }}} - - // First clock, latch in the inputs : mpypipe, r_mpy_?_input - // {{{ - initial mpypipe = 3'b0; - always @(posedge i_clk) - begin - // mpypipe indicates we have a multiply in the - // pipeline. In this case, the multiply - // pipeline is a two stage pipeline, so we need - // two bits in the pipe. - if (i_reset) - mpypipe <= 3'h0; - else begin - mpypipe[0] <= i_stb; - mpypipe[1] <= mpypipe[0]; - mpypipe[2] <= mpypipe[1]; - end - - if (i_op[0]) // i.e. if signed multiply - begin - r_mpy_a_input <= {(~i_a[31]),i_a[30:0]}; - r_mpy_b_input <= {(~i_b[31]),i_b[30:0]}; - end else begin - r_mpy_a_input <= i_a[31:0]; - r_mpy_b_input <= i_b[31:0]; - end - // The signed bit really only matters in the - // case of 64 bit multiply. We'll keep track - // of it, though, and pretend in all other - // cases. - r_mpy_signed <= i_op[0]; - - if (i_stb) - r_hi <= i_op[1]; - else if (OPT_LOWPOWER) - begin - r_mpy_a_input <= 0; - r_mpy_b_input <= 0; - r_mpy_signed <= 0; - end - end - // }}} - - assign o_hi = r_hi; - assign o_busy = |mpypipe[1:0]; - assign o_valid = mpypipe[2]; - - // Second clock, do the multiplies, get the "partial products". - // {{{ - // Here, we break our input up into two halves, - // - // A = (2^16 ah + al) - // B = (2^16 bh + bl) - // - // and use these to compute partial products. - // - // AB = (2^32 ah*bh + 2^16 (ah*bl + al*bh) + (al*bl) - // - // Since we're following the FOIL algorithm to get here, - // we'll name these partial products according to FOIL. - // - // The trick is what happens if A or B is signed. In - // those cases, the real value of A will not be given by - // A = (2^16 ah + al) - // but rather - // A = (2^16 ah[31^] + al) - 2^31 - // (where we have flipped the sign bit of A) - // and so ... - // - // AB= (2^16 ah + al - 2^31) * (2^16 bh + bl - 2^31) - // = 2^32(ah*bh) - // +2^16 (ah*bl+al*bh) - // +(al*bl) - // - 2^31 (2^16 bh+bl + 2^16 ah+al) - // - 2^62 - // = 2^32(ah*bh) - // +2^16 (ah*bl+al*bh) - // +(al*bl) - // - 2^31 (2^16 bh+bl + 2^16 ah+al + 2^31) - // - always @(posedge i_clk) - if (!OPT_LOWPOWER || mpypipe[0]) - begin - pp_f<=r_mpy_a_input[31:16]*r_mpy_b_input[31:16]; - pp_oi<=r_mpy_a_input[31:16]*r_mpy_b_input[15: 0] - + r_mpy_a_input[15: 0]*r_mpy_b_input[31:16]; - pp_l<=r_mpy_a_input[15: 0]*r_mpy_b_input[15: 0]; - // And a special one for the sign - if (r_mpy_signed) - pp_s <= 32'h8000_0000-( - r_mpy_a_input[31:0] - + r_mpy_b_input[31:0]); - else - pp_s <= 33'h0; - end - // }}} - - // Third clock, add the results and get a product: r_mpy_result - // {{{ - always @(posedge i_clk) - if (!OPT_LOWPOWER || mpypipe[1]) - begin - r_mpy_result[15:0] <= pp_l[15:0]; - r_mpy_result[63:16] <= - { 32'h00, pp_l[31:16] } - + { 15'h00, pp_oi } - + { pp_s, 15'h00 } - + { pp_f, 16'h00 }; - end - // }}} - - assign o_result = r_mpy_result; - // Fourth clock -- results are clocked into writeback - // }}} - end else begin : MPYSLOW - // {{{ - // Use an external multiply implementation, for when DSPs aren't - // available. - // - - // Declarations - // {{{ - reg r_hi; - // verilator coverage_off - // verilator lint_off UNUSED - wire unused_aux; - wire [65:0] full_result; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} - - slowmpy #(.LGNA(6), .NA(33) - ) slowmpyi( - i_clk, i_reset, i_stb, - { (i_op[0])&(i_a[31]), i_a }, - { (i_op[0])&(i_b[31]), i_b }, 1'b0, o_busy, - o_valid, full_result, unused_aux - ); - - assign o_result = full_result[63:0]; - - always @(posedge i_clk) - if (i_stb) - r_hi <= i_op[1]; - - assign o_hi = r_hi; - // }}} - end end end end end - endgenerate // All possible multiply results have been determined - -endmodule diff --git a/delete_later/rtl/cpu/pfcache.v b/delete_later/rtl/cpu/pfcache.v deleted file mode 100644 index 5f150ec..0000000 --- a/delete_later/rtl/cpu/pfcache.v +++ /dev/null @@ -1,1003 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: pfcache.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Keeping our CPU fed with instructions, at one per clock and -// with only a minimum number stalls. The entire cache may also -// be cleared (if necessary). -// -// This logic is driven by a couple realities: -// 1. It takes a clock to read from a block RAM address, and hence a clock -// to read from the cache. -// 2. It takes another clock to check that the tag matches -// -// Our goal will be to avoid this second check if at all possible. -// Hence, we'll test on the clock of any given request whether -// or not the request matches the last tag value, and on the next -// clock whether it new tag value (if it has changed). Hence, -// for anything found within the cache, there will be a one -// cycle delay on any branch. -// -// -// Address Words are separated into three components: -// [ Tag bits ] [ Cache line number ] [ Cache position w/in the line ] -// -// On any read from the cache, only the second two components are required. -// On any read from memory, the first two components will be fixed across -// the bus, and the third component will be adjusted from zero to its -// maximum value. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module pfcache #( - // {{{ -`ifdef FORMAL - parameter LGCACHELEN = 4, ADDRESS_WIDTH=30, - LGLINES=2, // Log of # of separate cache lines -`else - parameter LGCACHELEN = 12, ADDRESS_WIDTH=30, - LGLINES=LGCACHELEN-3, // Log of # of separate cache lines -`endif - parameter BUS_WIDTH = 32, // Num data bits on the bus - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - localparam CACHELEN=(1<> (INSN_WIDTH*shift); - assign o_insn= shifted[INSN_WIDTH-1:0]; - - end else begin : BIG_ENDIAN_SHIFT - - assign shifted = cache_word << (INSN_WIDTH*shift); - assign o_insn=shifted[BUS_WIDTH-1:BUS_WIDTH-INSN_WIDTH]; - - end - - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused_shift; - assign unused_shift = &{ 1'b0, shifted }; - // Verilator lint_on UNUSED - // Verilator coverage_on - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Read the tag value associated with this cache line - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign pc_tag = i_pc[WBLSB+LS +: (AW-LS)]; - assign pc_line = i_pc[WBLSB+LS +: (CW-LS)]; - assign last_line = lastpc[WBLSB+LS +: (CW-LS)]; - - // - // Read the tag value associated with this i_pc value - always @(posedge i_clk) - pc_tag_lookup <= { cache_tags[pc_line], pc_line }; - // tagvalipc <= cache_tags[i_pc[WBLSB + LS +: (CW-LS)]]; - - - // - // Read the tag value associated with the lastpc value, from what - // i_pc was when we could not tell if this value was in our cache or - // not, or perhaps from when we determined that i was not in the cache. - // initial tagvallst = 0; - always @(posedge i_clk) - last_tag_lookup <= { cache_tags[last_line], last_line }; - // tagvallst <= cache_tags[lastpc[WBLSB + LS +: (CW-LS)]]; - - // Select from between these two values on the next clock - assign tag_lookup = (isrc)? pc_tag_lookup : last_tag_lookup; - - // i_pc will only increment when everything else isn't stalled, thus - // we can set it without worrying about that. Doing this enables - // us to work in spite of stalls. For example, if the next address - // isn't valid, but the decoder is stalled, get the next address - // anyway. - initial lastpc = 0; - always @(posedge i_clk) - if (w_advance) - lastpc <= i_pc; - - assign lasttag = lastpc[WBLSB + LS +: (AW-LS)]; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Use the tag value to determine if our output instruction will be - // valid. - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign w_v_from_pc = ((pc_tag == lasttag) &&(tag_lookup == pc_tag) - && valid_mask[pc_line]); - assign w_v_from_last = ((tag_lookup == lasttag) - &&(valid_mask[last_line])); - - initial delay = 2'h3; - always @(posedge i_clk) - if (i_reset || i_clear_cache || w_advance) - begin - // Source our valid signal from i_pc - rvsrc <= 1'b1; - // Delay at least two clocks before declaring that - // we have an invalid result. This will give us time - // to check the tag value of what's in the cache. - delay <= 2'h2; - end else if (!r_v && !o_illegal) - begin - // If we aren't sourcing our valid signal from the - // i_pc clock, then we are sourcing it from the - // lastpc clock (one clock later). If r_v still - // isn't valid, we may need to make a bus request. - // Apply our timer and timeout. - rvsrc <= 1'b0; - - // Delay is two once the bus starts, in case the - // bus transaction needs to be restarted upon completion - // This might happen if, after we start loading the - // cache, we discover a branch. The cache load will - // still complete, but the branches address needs to be - // the onen we jump to. This may mean we need to load - // the cache twice. - if (o_wb_cyc) - delay <= 2'h2; - else if (delay != 0) - delay <= delay + 2'b11; // i.e. delay -= 1; - end else begin - // After sourcing our output from i_pc, if it wasn't - // accepted, source the instruction from the lastpc valid - // determination instead - rvsrc <= 1'b0; - if (o_illegal) - delay <= 2'h2; - end - - assign w_invalidate_result = (i_reset)||(i_clear_cache); - - initial r_v_from_pc = 0; - initial r_v_from_last = 0; - always @(posedge i_clk) - begin - r_v_from_pc <= (w_v_from_pc)&&(!w_invalidate_result) - &&(!o_illegal); - r_v_from_last <= (w_v_from_last)&&(!w_invalidate_result); - end - - // Now use rvsrc to determine which of the two valid flags we'll be - // using: r_v_from_pc (the i_pc address), or r_v_from_last (the lastpc - // address) - assign r_v = ((rvsrc)?(r_v_from_pc):(r_v_from_last)); - - always @(*) - o_valid = r_v || o_illegal; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // If the instruction isn't in our cache, then we need to load - // a new cache line from memory. - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial needload = 1'b0; - always @(posedge i_clk) - if (i_clear_cache || o_wb_cyc) - needload <= 1'b0; - else if ((w_advance)&&(!o_illegal)) - needload <= 1'b0; - else - needload <= (delay==0)&&(!w_v_from_last) - // Prevent us from reloading an illegal address - // (i.e. one that produced a bus error) over and over - // and over again - &&(!illegal_valid ||(lasttag != illegal_cache)); - - // - // Working from the rule that you want to keep complex logic out of - // a state machine if possible, we calculate a "last_stb" value one - // clock ahead of time. Hence, any time a request is accepted, if - // last_stb is also true we'll know we need to drop the strobe line, - // having finished requesting a complete cache line. - initial last_addr = 1'b0; - always @(posedge i_clk) - if (!o_wb_cyc) - last_addr <= 1'b0; - else if ((o_wb_addr[(LS-1):1] == {(LS-1){1'b1}}) - &&((!i_wb_stall)|(o_wb_addr[0]))) - last_addr <= 1'b1; - - // - // "last_ack" is almost identical to last_addr, save that this - // will be true on the same clock as the last acknowledgment from the - // bus. The state machine logic will use this to determine when to - // get off the bus and end the wishbone bus cycle. - initial last_ack = 1'b0; - always @(posedge i_clk) - last_ack <= (o_wb_cyc)&&( - (wraddr[(LS-1):1]=={(LS-1){1'b1}}) - &&((wraddr[0])||(i_wb_ack))); - - initial bus_abort = 1'b0; - always @(posedge i_clk) - if (!o_wb_cyc) - bus_abort <= 1'b0; - else if (i_clear_cache || i_new_pc) - bus_abort <= 1'b1; - - // - // Here's the difficult piece of state machine logic--the part that - // determines o_wb_cyc and o_wb_stb. We've already moved most of the - // complicated logic off of this statemachine, calculating it one cycle - // early. As a result, this is a fairly easy piece of logic. - initial o_wb_cyc = 1'b0; - initial o_wb_stb = 1'b0; - always @(posedge i_clk) - if (i_reset || i_clear_cache) - begin - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - end else if (o_wb_cyc) - begin - if (i_wb_err) - o_wb_stb <= 1'b0; - else if (o_wb_stb && !i_wb_stall && last_addr) - o_wb_stb <= 1'b0; - - if ((i_wb_ack && last_ack )|| i_wb_err) - o_wb_cyc <= 1'b0; - - end else if (needload && !i_new_pc) - begin - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - end - - // If we are reading from this cache line, then once we get the first - // acknowledgement, this cache line has the new tag value - always @(posedge i_clk) - if (o_wb_cyc && i_wb_ack) - cache_tags[o_wb_addr[(CW-1):LS]] <= o_wb_addr[(AW-1):CW]; - - - // On each acknowledgment, increment the address we use to write into - // our cache. Hence, this is the write address into our cache block - // RAM. - initial wraddr = 0; - always @(posedge i_clk) - if (o_wb_cyc && i_wb_ack && !last_ack) - wraddr[LS-1:0] <= wraddr[LS-1:0] + 1'b1; - else if (!o_wb_cyc) - wraddr <= { last_line, {(LS){1'b0}} }; - - // - // The wishbone request address. This has meaning anytime o_wb_stb - // is active, and needs to be incremented any time an address is - // accepted--WITH THE EXCEPTION OF THE LAST ADDRESS. We need to keep - // this steady for that last address, unless the last address returns - // a bus error. In that case, the whole cache line will be marked as - // invalid--but we'll need the value of this register to know how - // to do that propertly. - initial o_wb_addr = {(AW){1'b0}}; - always @(posedge i_clk) - if ((o_wb_stb)&&(!i_wb_stall)&&(!last_addr)) - o_wb_addr[(LS-1):0] <= o_wb_addr[(LS-1):0]+1'b1; - else if (!o_wb_cyc) - o_wb_addr <= { lasttag, {(LS){1'b0}} }; - - // Since it is impossible to initialize an array, our cache will start - // up cache uninitialized. We'll also never get a valid ack without - // cyc being active, although we might get one on the clock after - // cyc was active--so we need to test and gate on whether o_wb_cyc - // is true. - // - // wraddr will advance forward on every clock cycle where ack is true, - // hence we don't need to check i_wb_ack here. This will work because - // multiple writes to the same address, ending with a valid write, - // will always yield the valid write's value only after our bus cycle - // is over. - always @(posedge i_clk) - if (o_wb_cyc) - cache[wraddr] <= i_wb_data; - - // VMask ... is a section loaded? - // Note "svmask". It's purpose is to delay the valid_mask setting by - // one clock, so that we can insure the right value of the cache is - // loaded before declaring that the cache line is valid. Without - // this, the cache line would get read, and the instruction would - // read from the last cache line. - initial valid_mask = 0; - initial svmask = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(i_clear_cache)) - begin - valid_mask <= 0; - svmask<= 1'b0; - end else begin - svmask <= (o_wb_cyc && i_wb_ack && last_ack && !bus_abort); - - if (svmask) - valid_mask[saddr] <= !bus_abort; - if (!o_wb_cyc && needload) - valid_mask[last_line] <= 1'b0; - end - - always @(posedge i_clk) - if ((o_wb_cyc)&&(i_wb_ack)) - saddr <= wraddr[(CW-1):LS]; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Handle bus errors here. If a bus read request - // returns an error, then we'll mark the entire - // line as having a (valid) illegal value. - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // - initial illegal_cache = 0; - initial illegal_valid = 0; - always @(posedge i_clk) - if ((i_reset)||(i_clear_cache)) - begin - illegal_cache <= 0; - illegal_valid <= 0; - end else if ((o_wb_cyc)&&(i_wb_err)) - begin - illegal_cache <= o_wb_addr[(AW-1):LS]; - illegal_valid <= 1'b1; - end else if ((o_wb_cyc)&&(i_wb_ack)&&(last_ack)&&(!bus_abort) - &&(wraddr[(CW-1):LS] == illegal_cache[CW-1:LS])) - illegal_valid <= 1'b0; - - initial o_illegal = 1'b0; - always @(posedge i_clk) - if (i_reset || i_clear_cache || i_new_pc) - o_illegal <= 1'b0; - // else if ((o_illegal)||((o_valid)&&(i_ready))) - // o_illegal <= 1'b0; - else if (!o_illegal) - begin - o_illegal <= (!i_wb_err)&&(illegal_valid)&&(!isrc) - &&(illegal_cache == lasttag); - end - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal property section -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations, reset, and f_past_valid - // {{{ - localparam F_LGDEPTH=LS+1; - - reg f_past_valid; - reg [4:0] f_cpu_delay; - reg [((1<<(LGLINES))-1):0] f_past_valid_mask; - reg [AW+WBLSB-1:0] f_next_pc; - reg [AW+WBLSB-1:0] f_next_lastpc; - wire [WBLSB+AW-1:0] f_const_addr, f_address; - wire f_const_illegal; - wire [BUSW-1:0] f_const_insn; - - wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding; - wire [INSN_WIDTH-1:0] f_insn; - - (* anyconst *) reg [BUS_WIDTH-1:0] f_const_word; - - - // Keep track of a flag telling us whether or not $past() - // will return valid results - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - // - // Assume we start from a reset condition - always @(*) - if (!f_past_valid) - assume(i_reset); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assumptions about our inputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - ffetch #( - // {{{ - .ADDRESS_WIDTH(AW + WBLSB-INLSB), .OPT_CONTRACT(1'b1) - // }}} - ) fcpu( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .cpu_new_pc(i_new_pc), - .cpu_clear_cache(i_clear_cache), - .cpu_pc(i_pc), .cpu_ready(i_ready), .pf_valid(o_valid), - .pf_insn(o_insn), .pf_pc(o_pc), .pf_illegal(o_illegal), - .fc_pc(f_const_addr), .fc_illegal(f_const_illegal), - .fc_insn(f_const_insn), .f_address(f_address) - // }}} - ); - - generate if (INSN_WIDTH == BUS_WIDTH) - begin : F_CONST_NOSHIFT - always @(*) - assume(f_const_word == f_const_insn); - end else begin : F_CONST_SHIFT - - wire [WBLSB-INLSB-1:0] f_shift; - wire [BUS_WIDTH-1:0] f_shifted; - wire [INSN_WIDTH-1:0] f_insn_check; - - assign f_shift = f_const_addr[WBLSB-1:INLSB]; - - if (OPT_LITTLE_ENDIAN) - begin - assign f_shifted = f_const_word >> (INSN_WIDTH * f_shift); - assign f_insn_check = f_shifted[INSN_WIDTH-1:0]; - end else begin - assign f_shifted = f_const_word << (INSN_WIDTH * f_shift); - assign f_insn_check = f_shifted[BUS_WIDTH-1:BUS_WIDTH-INSN_WIDTH]; - end - - always @(*) - assume(f_insn_check == f_const_insn); - - end endgenerate - - // - // Let's make some assumptions about how long it takes our - // phantom bus and phantom CPU to respond. - // - // These delays need to be long enough to flush out any potential - // errors, yet still short enough that the formal method doesn't - // take forever to solve. - // - localparam F_CPU_DELAY = 4; - - - // Now, let's repeat this bit but now looking at the delay the CPU - // takes to accept an instruction. - always @(posedge i_clk) - // If no instruction is ready, then keep our counter at zero - if ((!o_valid)||(i_ready)) - f_cpu_delay <= 0; - else - // Otherwise, count the clocks the CPU takes to respond - f_cpu_delay <= f_cpu_delay + 1'b1; - -`ifdef PFCACHE - always @(posedge i_clk) - assume(f_cpu_delay < F_CPU_DELAY); -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // - // - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - if (o_wb_cyc && !bus_abort) - assert(!o_valid); - - //////////////////////////////////////////////////////////////////////// - // - // Assertions about our outputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - fwb_master #( - // {{{ - .AW(AW), .DW(BUSW), .F_LGDEPTH(F_LGDEPTH), - .F_MAX_STALL(2), .F_MAX_ACK_DELAY(3), - .F_MAX_REQUESTS(1<> (INSN_WIDTH * f_shift); - assign f_insn = f_shifted[INSN_WIDTH-1:0]; - end else begin - assign f_shifted = cache[o_pc[WBLSB +: CW]] << (INSN_WIDTH * f_shift); - assign f_insn = f_shifted[BUS_WIDTH-1:BUS_WIDTH-INSN_WIDTH]; - end - - end endgenerate - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_wb_cyc))) - assert(o_wb_addr[(AW-1):LS] == $past(o_wb_addr[(AW-1):LS])); - - always @(posedge i_clk) - if (o_valid && !i_new_pc) - begin - if (!o_illegal) - begin - assert(valid_mask[o_pc[WBLSB+LS +: (CW-LS)]]); - assert(cache_tags[o_pc[WBLSB+LS +: (CW-LS)]] == o_pc[WBLSB+CW +: (AW-CW)]); - assert(o_insn == f_insn); - assert((!illegal_valid) - ||(illegal_cache != o_pc[WBLSB+LS +: (AW-LS)])); - end - - if ($rose(o_illegal)) - assert(o_illegal == ($past(illegal_valid) - &&($past(illegal_cache)== o_pc[WBLSB+LS +: (AW-LS)]))); - end else if (!i_reset && !i_new_pc && !i_clear_cache) - assert(o_pc == f_address); - - always @(*) - if (!i_reset && !i_new_pc && !i_clear_cache) - assert(o_illegal || o_pc == f_address); - - always @(*) - begin - f_next_lastpc = lastpc + 4; - f_next_lastpc[1:0] = 2'b00; - end - - always @(posedge i_clk) - if ((f_past_valid)&& !$past(i_reset || i_clear_cache) - && !o_illegal && !i_new_pc - && !i_clear_cache) - begin - assert(lastpc == r_pc); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(o_valid)&&($past(o_valid)) - &&(!$past(i_reset)) - &&(!$past(i_new_pc)) - &&(!$past(i_ready)) - &&(!o_illegal)) - begin - assert(cache_tags[o_pc[WBLSB+LS +: (CW-LS)]] == o_pc[WBLSB+CW +: (AW-CW)]); - end - - // - // If an instruction is accepted, we should *always* move on to another - // instruction. The only exception is following an i_new_pc (or - // other invalidator), at which point the next instruction should - // be invalid. - always @(posedge i_clk) - if ((f_past_valid)&& $past(o_valid && i_ready && !o_illegal && !i_new_pc)) - begin - // Should always advance the instruction - assert((!o_valid)||(o_pc != $past(o_pc))); - end - - // - // Once an instruction becomes valid, it should never become invalid - // unless there's been a request for a new instruction. - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset || i_clear_cache)) - begin - assert(!o_valid); - assert(!o_illegal); - end else if ($past(o_valid && !i_ready && !i_new_pc)) - begin - if (!$past(o_illegal)) - begin - assert(o_valid); - assert(!o_illegal); - assert($stable(o_insn)); - end else - assert(o_illegal); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // - // Assertions associated with a response to a known address request - // That is, if you assume a value exists at an arbitrary address, - // prove that this value is returned whenever that arbitrary address's - // value gets returned. - // - - wire f_this_pc, f_this_insn, f_this_data, f_this_line, - f_this_ack, f_this_tag; // f_this_addr; - wire [LS-1:0] f_const_line; - wire [AW-LS-1:0] f_const_tag; - - assign f_const_line = f_const_addr[WBLSB+LS +: (CW-LS)]; - assign f_const_tag = f_const_addr[WBLSB+LS +: (AW-LS)]; - - assign f_this_pc = (o_pc == f_const_addr); - // assign f_this_addr = (o_wb_addr == f_const_addr[AW-1:0] ); - assign f_this_insn = (o_insn == f_const_insn); - assign f_this_data = (i_wb_data == f_const_word); - assign f_this_line = (o_wb_addr[AW-1:LS] == f_const_tag); - assign f_this_ack = (f_this_line)&&(f_nacks == f_const_addr[WBLSB +: LS]); - assign f_this_tag = (tag_lookup == f_const_tag); - - always @(posedge i_clk) - if ((o_valid)&&(f_this_pc)&&(!$past(o_illegal))) - begin - assert(o_illegal == f_const_illegal); - if (!o_illegal) - begin - assert(f_this_insn); - assert(f_this_tag); - end - end - - always @(*) - if ((valid_mask[f_const_line]) - &&(cache_tags[f_const_line]==f_const_addr[WBLSB+CW +: (AW-CW)])) - begin - assert(f_const_word == cache[f_const_addr[WBLSB +: CW]]); - end else if ((o_wb_cyc)&&(o_wb_addr[AW-1:LS] == f_const_addr[WBLSB+LS +: (AW-LS)]) - &&(f_nacks > f_const_addr[WBLSB +: LS])) - begin - assert(f_const_word == cache[f_const_addr[WBLSB +: CW]]); - end - - always @(*) - if (o_wb_cyc) - assert(wraddr[CW-1:LS] == o_wb_addr[CW-1:LS]); - - always @(*) - if (!f_const_illegal) - assert((!illegal_valid) ||(illegal_cache != f_const_tag)); - else - assert(cache_tags[f_const_line] != f_const_addr[WBLSB+CW +: (AW-CW)] - || !valid_mask[f_const_line]); - - always @(*) - if ((f_this_line)&&(o_wb_cyc)) - begin - if (f_const_illegal) - begin - assume(!i_wb_ack); - end else - assume(!i_wb_err); - - if ((f_this_ack)&&(i_wb_ack)) - assume(f_this_data); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg f_valid_legal; - always @(*) - f_valid_legal = o_valid && (!o_illegal); - always @(posedge i_clk) // Trace 0 - cover((o_valid)&&( o_illegal)); - always @(posedge i_clk) // Trace 1 - cover(f_valid_legal); - always @(posedge i_clk) // Trace 2 - cover((f_valid_legal) - &&($past(!o_valid && !i_new_pc)) - &&($past(i_new_pc,2))); - always @(posedge i_clk) // Trace 3 - cover((f_valid_legal)&&($past(i_ready))&&($past(i_new_pc))); - always @(posedge i_clk) // Trace 4 - cover((f_valid_legal)&&($past(f_valid_legal && i_ready))); - always @(posedge i_clk) // Trace 5 - cover((f_valid_legal) - &&($past(f_valid_legal && i_ready)) - &&($past(f_valid_legal && i_ready,2)) - &&($past(f_valid_legal && i_ready,3))); - always @(posedge i_clk) // Trace 6 - cover((f_valid_legal) - &&($past(f_valid_legal && i_ready)) - &&($past(f_valid_legal && i_ready,2)) - &&($past(!o_illegal && i_ready && i_new_pc,3)) - &&($past(f_valid_legal && i_ready,4)) - &&($past(f_valid_legal && i_ready,5)) - &&($past(f_valid_legal && i_ready,6))); - // }}} -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/cpu/pipemem.v b/delete_later/rtl/cpu/pipemem.v deleted file mode 100644 index f47bc77..0000000 --- a/delete_later/rtl/cpu/pipemem.v +++ /dev/null @@ -1,940 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: pipemem.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A memory unit to support a CPU, this time one supporting -// pipelined wishbone memory accesses. The goal is to be able -// to issue one pipelined wishbone access per clock, and (given the memory -// is fast enough) to be able to read the results back at one access per -// clock. This renders on-chip memory fast enough to handle single cycle -// (pipelined) access. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module pipemem #( - // {{{ - parameter ADDRESS_WIDTH=28, - parameter BUS_WIDTH=32, - parameter [0:0] OPT_LOCK=1'b1, - WITH_LOCAL_BUS=1'b1, - OPT_ZERO_ON_IDLE=1'b0, - // OPT_ALIGNMENT_ERR - OPT_ALIGNMENT_ERR=1'b0, - localparam AW=ADDRESS_WIDTH, - FLN=4, - parameter [(FLN-1):0] OPT_MAXDEPTH=4'hd - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // CPU interface - // {{{ - input wire i_pipe_stb, i_lock, - input wire [2:0] i_op, - input wire [31:0] i_addr, - input wire [31:0] i_data, - input wire [4:0] i_oreg, - // CPU outputs - output wire o_busy, o_rdbusy, - output wire o_pipe_stalled, - output reg o_valid, - output reg o_err, - output reg [4:0] o_wreg, - output reg [31:0] o_result, - // }}} - // Wishbone outputs - // {{{ - output wire o_wb_cyc_gbl, - output wire o_wb_cyc_lcl, - output reg o_wb_stb_gbl, - output reg o_wb_stb_lcl, o_wb_we, - output reg [(AW-1):0] o_wb_addr, - output reg [BUS_WIDTH-1:0] o_wb_data, - output reg [BUS_WIDTH/8-1:0] o_wb_sel, - // Wishbone inputs - input wire i_wb_stall, i_wb_ack, i_wb_err, - input wire [BUS_WIDTH-1:0] i_wb_data - // }}} - // }}} - ); - - // Declarations - // {{{ - localparam WBLSB = $clog2(BUS_WIDTH/8); - // Verilator lint_off UNUSED - localparam F_LGDEPTH=FLN+1; - // Verilator lint_on UNUSED -`ifdef FORMAL - wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding; - reg f_pc; -`endif - - reg cyc, r_wb_cyc_gbl, r_wb_cyc_lcl, - fifo_full; - wire gbl_stb, lcl_stb, lcl_bus; - reg [(FLN-1):0] rdaddr, wraddr; - wire [(FLN-1):0] nxt_rdaddr, fifo_fill; - reg [4+2+WBLSB-1:0] fifo_mem [0:15]; - reg fifo_gie; - wire [4+2+WBLSB-1:0] w_wreg; - wire misaligned; - - reg [BUS_WIDTH/8-1:0] oword_sel; - wire [BUS_WIDTH/8-1:0] pre_wb_sel; - reg [31:0] oword_data; - wire [BUS_WIDTH-1:0] pre_wb_data, pre_result; - // }}} - - // misaligned - // {{{ - generate if (OPT_ALIGNMENT_ERR) - begin : GEN_ALIGNMENT_ERR - reg r_mis; - - always @(*) - casez({ i_op[2:1], i_addr[1:0] }) - 4'b01?1: r_mis = i_pipe_stb; - 4'b0110: r_mis = i_pipe_stb; - 4'b10?1: r_mis = i_pipe_stb; - default: r_mis = i_pipe_stb; - endcase - - assign misaligned = r_mis; - - end else begin : NO_MISALIGNMENT_ERRS - - assign misaligned = 1'b0; - - end endgenerate - // }}} - - // fifo_mem - // {{{ - always @(posedge i_clk) - fifo_mem[wraddr] <= { i_oreg[3:0], i_op[2:1], i_addr[WBLSB-1:0] }; - // }}} - - // fifo_gie - // {{{ - always @(posedge i_clk) - if (i_pipe_stb) - fifo_gie <= i_oreg[4]; - // }}} - - // wraddr - // {{{ - initial wraddr = 0; - always @(posedge i_clk) - if (i_reset) - wraddr <= 0; - else if (((i_wb_err)&&(cyc))||((i_pipe_stb)&&(misaligned))) - wraddr <= 0; - else if (i_pipe_stb) - wraddr <= wraddr + 1'b1; - // }}} - - // rdaddr - // {{{ - initial rdaddr = 0; - always @(posedge i_clk) - if (i_reset) - rdaddr <= 0; - else if (((i_wb_err)&&(cyc))||((i_pipe_stb)&&(misaligned))) - rdaddr <= 0; - else if ((i_wb_ack)&&(cyc)) - rdaddr <= rdaddr + 1'b1; - // }}} - - assign fifo_fill = wraddr - rdaddr; - - // fifo_full - // {{{ - initial fifo_full = 0; - always @(posedge i_clk) - if (i_reset || !cyc) - fifo_full <= 0; - else if (((i_wb_err)&&(cyc))||((i_pipe_stb)&&(misaligned))) - fifo_full <= 0; - else case({ i_pipe_stb, i_wb_ack }) - 2'b10: fifo_full <= (fifo_fill >= OPT_MAXDEPTH-1); - 2'b01: fifo_full <= 1'b0; - default: begin end - endcase -`ifdef FORMAL - always @(*) - if (!cyc) - begin - assert(fifo_full == 0); - end else - assert(fifo_full == (fifo_fill >= OPT_MAXDEPTH)); - - always @(*) - if (fifo_full) - assert(fifo_fill == OPT_MAXDEPTH); -`endif - // }}} - - assign nxt_rdaddr = rdaddr + 1'b1; - - // lcl_bus, lcl_stb, gbl_stb - // {{{ - assign lcl_bus = (i_addr[31:24]==8'hff)&&(WITH_LOCAL_BUS); - assign lcl_stb = (lcl_bus)&&(!misaligned); - assign gbl_stb = ((!lcl_bus)||(!WITH_LOCAL_BUS))&&(!misaligned); - //= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0)); - // }}} - - // cyc, [or]_wb_[cyc|stb]_[lcl|gbl] - // {{{ - initial cyc = 0; - initial r_wb_cyc_lcl = 0; - initial r_wb_cyc_gbl = 0; - initial o_wb_stb_lcl = 0; - initial o_wb_stb_gbl = 0; - always @(posedge i_clk) - begin - if (cyc) - begin - if (((!i_wb_stall)&&(!i_pipe_stb)&&(!misaligned)) - ||(i_wb_err)) - begin - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - end - - if (((i_wb_ack)&&(nxt_rdaddr == wraddr) - &&((!i_pipe_stb)||(misaligned))) - ||(i_wb_err)) - begin - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - cyc <= 1'b0; - end - end else if (i_pipe_stb) // New memory operation - begin // Grab the wishbone - r_wb_cyc_lcl <= lcl_stb; - r_wb_cyc_gbl <= gbl_stb; - o_wb_stb_lcl <= lcl_stb; - o_wb_stb_gbl <= gbl_stb; - cyc <= (!misaligned); - end - - if (i_reset) - begin - r_wb_cyc_gbl <= 1'b0; - r_wb_cyc_lcl <= 1'b0; - o_wb_stb_gbl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - cyc <= 1'b0; - end - - if (!WITH_LOCAL_BUS) - begin - r_wb_cyc_lcl <= 1'b0; - o_wb_stb_lcl <= 1'b0; - end - end - // }}} - - // pre_wb_sel - // {{{ - always @(*) - begin - oword_sel = 0; - casez({ i_op[2:1], i_addr[1:0] }) - 4'b100?: oword_sel[3:0] = 4'b1100; // Op = 5 - 4'b101?: oword_sel[3:0] = 4'b0011; // Op = 5 - 4'b1100: oword_sel[3:0] = 4'b1000; // Op = 5 - 4'b1101: oword_sel[3:0] = 4'b0100; // Op = 7 - 4'b1110: oword_sel[3:0] = 4'b0010; // Op = 7 - 4'b1111: oword_sel[3:0] = 4'b0001; // Op = 7 - default: oword_sel[3:0] = 4'b1111; // Op = 7 - endcase - end - - generate if (BUS_WIDTH == 32) - begin : GEN_SEL32 - - assign pre_wb_sel = oword_sel; - - end else begin : GEN_WIDESEL32 - - // If we were little endian, we'd do ... - // assign pre_wb_sel = (oword_sel << (4* i_addr[WBLSB-1:2])); - assign pre_wb_sel = {oword_sel[3:0], {(BUS_WIDTH/8-4){1'b0}} } - >> (4* i_addr[WBLSB-1:2]); - - end endgenerate - // }}} - - // pre_wb_data - // {{{ - - always @(*) - casez({ i_op[2:1], i_addr[1:0] }) - 4'b100?: oword_data = { i_data[15:0], 16'h00 }; - 4'b101?: oword_data = { 16'h00, i_data[15:0] }; - 4'b1100: oword_data = { i_data[7:0], 24'h00 }; - 4'b1101: oword_data = { 8'h00, i_data[7:0], 16'h00 }; - 4'b1110: oword_data = { 16'h00, i_data[7:0], 8'h00 }; - 4'b1111: oword_data = { 24'h00, i_data[7:0] }; - default: oword_data = i_data; - endcase - - generate if (BUS_WIDTH == 32) - begin : GEN_DATA32 - - assign pre_wb_data = oword_data; - - end else begin : GEN_WIDEDATA32 - - // If we were little endian, we'd do ... - // assign pre_wb_sel = (word_sel << (4* i_addr[WBLSB-1:2])); - assign pre_wb_data = {oword_data, {(BUS_WIDTH-32){1'b0}} } - >> (32* i_addr[WBLSB-1:2]); - - end endgenerate - // }}} - - // o_wb_addr, o_wb_sel, and o_wb_data - // {{{ - always @(posedge i_clk) - if ((!cyc)||(!i_wb_stall)) - begin - // o_wb_add - // {{{ - if ((OPT_ZERO_ON_IDLE)&&(!i_pipe_stb)) - o_wb_addr <= 0; - else if (lcl_bus) - o_wb_addr <= i_addr[2 +: AW]; - else - o_wb_addr <= i_addr[WBLSB +: AW]; - // }}} - - // o_wb_sel - // {{{ - if ((OPT_ZERO_ON_IDLE)&&(!i_pipe_stb)) - o_wb_sel <= {(BUS_WIDTH/8){1'b0}}; - else if (lcl_bus) - o_wb_sel <= oword_sel; - else - o_wb_sel <= pre_wb_sel; - // }}} - - // o_wb_data - // {{{ - o_wb_data <= 0; - if ((OPT_ZERO_ON_IDLE)&&(!i_pipe_stb)) - o_wb_data <= 0; - else if (lcl_bus) - o_wb_data[31:0] <= oword_data; - else - o_wb_data <= pre_wb_data; - // }}} - end - // }}} - - // o_wb_we - // {{{ - always @(posedge i_clk) - if ((i_pipe_stb)&&(!cyc)) - o_wb_we <= i_op[0]; - else if ((OPT_ZERO_ON_IDLE)&&(!cyc)) - o_wb_we <= 1'b0; - // }}} - - // o_valid - // {{{ - initial o_valid = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_valid <= 1'b0; - else - o_valid <= (cyc)&&(i_wb_ack)&&(!o_wb_we); - // }}} - - // o_err - // {{{ - initial o_err = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_err <= 1'b0; - else - o_err <= ((cyc)&&(i_wb_err))||((i_pipe_stb)&&(misaligned)); - // }}} - - assign o_busy = cyc; - assign o_rdbusy = o_busy && !o_wb_we; - - assign w_wreg = fifo_mem[rdaddr]; - - // o_wreg - // {{{ - always @(posedge i_clk) - o_wreg <= { fifo_gie, w_wreg[2 + WBLSB +: 4] }; - // }}} - - // o_result - // {{{ - generate if (BUS_WIDTH == 32) - begin : COPY_IDATA - - assign pre_result = i_wb_data; - - end else begin : GEN_PRERESULT - - assign pre_result = i_wb_data << (8*w_wreg[WBLSB-1:0]); - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused_preresult; - assign unused_preresult = &{1'b0, pre_result[BUS_WIDTH-33:0] }; - // Verilator lint_on UNUSED - // Verilator coverage_on - end endgenerate - - always @(posedge i_clk) - if ((OPT_ZERO_ON_IDLE)&&((!cyc)||((!i_wb_ack)&&(!i_wb_err)))) - o_result <= 0; - else if ((o_wb_cyc_lcl && WITH_LOCAL_BUS) || (BUS_WIDTH == 32)) - begin - casez({ w_wreg[WBLSB +: 2], w_wreg[1:0] }) - 4'b1100: o_result <= { 24'h00, i_wb_data[31:24] }; - 4'b1101: o_result <= { 24'h00, i_wb_data[23:16] }; - 4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] }; - 4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] }; - 4'b100?: o_result <= { 16'h00, i_wb_data[31:16] }; - 4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] }; - default: o_result <= i_wb_data[31:0]; - endcase - end else begin - casez(w_wreg[WBLSB +: 2]) - 2'b11: o_result <= { 24'h00, pre_result[BUS_WIDTH-1:BUS_WIDTH-8] }; - 2'b10: o_result <= { 16'h00, pre_result[BUS_WIDTH-1:BUS_WIDTH-16] }; - default: o_result <= pre_result[BUS_WIDTH-1:BUS_WIDTH-32]; - endcase - end - // }}} - - // o_pipe_stalled - // {{{ - assign o_pipe_stalled = ((cyc)&&(fifo_full))||((cyc) - &&((i_wb_stall)||((!o_wb_stb_lcl)&&(!o_wb_stb_gbl)))); - // }}} - - // lock_gbl, lock_lcl - // {{{ - generate - if (OPT_LOCK) - begin : LOCK_REGISTER - // {{{ - reg lock_gbl, lock_lcl; - - initial lock_gbl = 1'b0; - initial lock_lcl = 1'b0; - always @(posedge i_clk) - begin - lock_gbl <= r_wb_cyc_gbl || lock_gbl; - lock_lcl <= r_wb_cyc_lcl || lock_lcl; - - if (i_reset || (i_wb_err && cyc) - || (i_pipe_stb && misaligned) - || !i_lock) - begin - lock_gbl <= 1'b0; - lock_lcl <= 1'b0; - end - - if (!WITH_LOCAL_BUS) - lock_lcl <= 1'b0; - end - - assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl); - assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl); - // }}} - end else begin : NO_LOCK - // {{{ - assign o_wb_cyc_gbl = (r_wb_cyc_gbl); - assign o_wb_cyc_lcl = (r_wb_cyc_lcl); - - // Verilator coverage_off - // verilator lint_off UNUSED - wire unused_lock; - assign unused_lock = &{ 1'b0, i_lock }; - // verilator lint_on UNUSED - // Verilator coverage_on - // }}} - end endgenerate - // }}} - - // Make verilator happy - // {{{ - // Verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = { 1'b0 }; - // verilator lint_on UNUSED - // Verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal property section -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations - // {{{ -`define ASSERT assert -`ifdef PIPEMEM -`define ASSUME assume -`else -`define ASSUME assert -`endif - wire [(F_LGDEPTH-1):0] fcpu_outstanding; - wire f_cyc, f_stb; - reg f_done; - wire [3:0] f_pipe_used; - reg [(1<= 13) - `ASSUME(!i_pipe_stb); - - always @(posedge i_clk) - if ((f_cyc)&&(f_pipe_used >= 13)) - `ASSERT((o_busy)&&(o_pipe_stalled)); - - - always @(posedge i_clk) - `ASSERT((!r_wb_cyc_gbl)||(!r_wb_cyc_lcl)); - - always @(posedge i_clk) - `ASSERT((!o_wb_cyc_gbl)||(!o_wb_cyc_lcl)); - - always @(posedge i_clk) - `ASSERT((!o_wb_stb_gbl)||(!o_wb_stb_lcl)); - - always @(*) - if (!WITH_LOCAL_BUS) - begin - assert(!o_wb_cyc_lcl); - assert(!o_wb_stb_lcl); - if (o_wb_stb_lcl) - assert(o_wb_addr[(AW-1):22] == {(8-(30-AW)){1'b1}}); - end - - always @(posedge i_clk) - if (o_wb_stb_gbl) - `ASSERT(o_wb_cyc_gbl); - - always @(posedge i_clk) - if (o_wb_stb_lcl) - `ASSERT(o_wb_cyc_lcl); - - always @(posedge i_clk) - `ASSERT(cyc == (r_wb_cyc_gbl|r_wb_cyc_lcl)); - - always @(posedge i_clk) - `ASSERT(cyc == (r_wb_cyc_lcl)|(r_wb_cyc_gbl)); - - always @(posedge i_clk) - if ((f_past_valid)&&(!i_reset)&&(!$past(misaligned))) - begin - if (f_stb) - begin - `ASSERT(f_pipe_used == f_outstanding + 4'h1); - end else - `ASSERT(f_pipe_used == f_outstanding); - end - - always @(posedge i_clk) - if ((f_past_valid)&&($past(r_wb_cyc_gbl||r_wb_cyc_lcl)) - &&(!$past(f_stb))) - `ASSERT(!f_stb); - - always @(*) - `ASSERT((!lcl_stb)||(!gbl_stb)); - - // - // insist that we only ever accept memory requests for the same GIE - // (i.e. 4th bit of register) - // - always @(*) - if ((i_pipe_stb)&&(wraddr != rdaddr)) - `ASSUME(i_oreg[4] == fifo_gie); - - initial f_pc = 1'b0; - always @(posedge i_clk) - if(i_reset) - f_pc <= 1'b0; - else if (i_pipe_stb && !misaligned) - f_pc <= (((f_pc)&&(f_cyc)) - ||((!i_op[0])&&(i_oreg[3:1] == 3'h7))); - else if (!f_cyc) - f_pc <= 1'b0; - - always @(posedge i_clk) - if ((f_cyc)&&(o_wb_we)) - `ASSERT(!f_pc); - -// always @(*) -// if ((f_pc)&&(f_cyc)) -// `ASSUME(!i_pipe_stb); - - always @(*) - if (wraddr == rdaddr) - begin - `ASSERT(!r_wb_cyc_gbl); - `ASSERT(!r_wb_cyc_lcl); - end else if (f_cyc) - begin - `ASSERT(fifo_fill == f_outstanding + ((f_stb)?1:0)); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The FIFO check - // {{{ - //////////////////////////////////////////////////////////////////////// - // - -`define FIFOCHECK -`ifdef FIFOCHECK - reg [4+2+WBLSB-1:0] fc_mem, frd_mem; - // Verilator lint_off UNDRIVEN - (* anyconst *) reg [3:0] fc_addr; - // Verilator lint_on UNDRIVEN - - wire [3:0] lastaddr = wraddr - 1'b1; - - integer k; - always @(*) - begin - f_mem_used = 0; - for(k = 0 ; k < (1< rdaddr) - begin - if ((k < wraddr)&&(k >= rdaddr)) - f_mem_used[k] = 1'b1; - end else if (k < wraddr) - f_mem_used[k] = 1'b1; - else if (k >= rdaddr) - f_mem_used[k] = 1'b1; - end - end - - always @(*) - fc_mem = fifo_mem[fc_addr]; - always @(*) - frd_mem = fifo_mem[rdaddr]; - - always @(*) - if (cyc && !o_wb_we) - begin - if (f_mem_used[rdaddr] && fc_addr != rdaddr) - begin - assume((frd_mem[1+2+WBLSB +: 3] == 3'h7) - == (f_pc && rdaddr == lastaddr)); - assume(({ fifo_gie, frd_mem[2+WBLSB +: 4] } != f_addr_reg) - || (rdaddr == lastaddr)); - end - - if (f_mem_used[fc_addr]) - begin - `ASSERT((fc_mem[1+2+WBLSB +: 3] == 3'h7) - == (f_pc && fc_addr == lastaddr)); - `ASSERT(({ fifo_gie, fc_mem[2+WBLSB +: 4] } != f_addr_reg) - || fc_addr == lastaddr); - end - end - - always @(*) - if (fifo_fill > 0) - assert({ fifo_gie, fifo_mem[lastaddr][2+WBLSB +: 4] } == f_last_reg); - - initial assert(!fifo_full); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - cover(cyc && !fifo_full); - - always @(posedge i_clk) - cover((f_cyc)&&(f_stb)&&(!i_wb_stall)&&(!i_wb_ack) - &&(!o_pipe_stalled)); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(f_stb))&&($past(f_cyc))) - cover((f_cyc)&&(i_wb_ack)); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(f_stb))&&($past(f_cyc))) - cover($past(i_wb_ack)&&(i_wb_ack)); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_valid))) - cover(o_valid); - -`endif // FIFOCHECK - // }}} - always @(posedge i_clk) - if ((f_past_valid)&&($past(f_past_valid))&&($past(f_cyc))&&($past(f_cyc,2))) - `ASSERT($stable(o_wreg[4])); - - always @(*) - `ASSERT((!f_cyc)||(!o_valid)||(o_wreg[3:1]!=3'h7)); - - // Make Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, f_nreqs, f_nacks }; - // Verilator lint_off UNUSED - // }}} -`endif // FORMAL -// }}} -endmodule -// -// -// Usage (from yosys): (Before) (A,!OPTZ) (A,OPTZ) -// Cells: 302 314 391 -// FDRE 138 140 140 -// LUT1 2 2 2 -// LUT2 38 41 61 -// LUT3 13 16 33 -// LUT4 3 8 12 -// LUT5 22 10 8 -// LUT6 52 59 81 -// MUXCY 6 6 6 -// MUXF7 10 13 21 -// MUXF8 1 2 10 -// RAM64X1D 9 9 9 -// XORCY 8 8 8 -// -// diff --git a/delete_later/rtl/cpu/prefetch.v b/delete_later/rtl/cpu/prefetch.v deleted file mode 100644 index 65c4d64..0000000 --- a/delete_later/rtl/cpu/prefetch.v +++ /dev/null @@ -1,874 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: prefetch.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is a very simple instruction fetch approach. It gets -// one instruction at a time. Future versions should pipeline -// fetches and perhaps even cache results--this doesn't do that. It -// should, however, be simple enough to get things running. -// -// The interface is fascinating. The 'i_pc' input wire is just a -// suggestion of what to load. Other wires may be loaded instead. i_pc -// is what must be output, not necessarily input. -// -// 20150919 -- Added support for the WB error signal. When reading an -// instruction results in this signal being raised, the pipefetch module -// will set an illegal instruction flag to be returned to the CPU together -// with the instruction. Hence, the ZipCPU can trap on it if necessary. -// -// 20171020 -- Added a formal proof to prove that the module works. This -// also involved adding a req_addr register, and the logic associated -// with it. -// -// 20171113 -- Removed the req_addr register, replacing it with a bus abort -// capability. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module prefetch #( - // {{{ - parameter ADDRESS_WIDTH=30, // Byte addr wid - INSN_WIDTH=32, - DATA_WIDTH=INSN_WIDTH, - localparam AW=ADDRESS_WIDTH, - DW=DATA_WIDTH, - parameter [0:0] OPT_ALIGNED = 1'b0, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b1 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // CPU interaction wires - input wire i_new_pc, i_clear_cache, - i_ready, - // We ignore i_pc unless i_new_pc is true as well - input wire [AW-1:0] i_pc, - output reg o_valid, // If output is valid - output reg o_illegal, // bus err result - output reg [INSN_WIDTH-1:0] o_insn, // Insn read from WB - output reg [AW-1:0] o_pc, // Byt addr of that insn - // Wishbone outputs - output reg o_wb_cyc, o_wb_stb, - // verilator coverage_off - output wire o_wb_we, // == const 0 - // verilator coverage_on - output reg [AW-$clog2(DW/8)-1:0] o_wb_addr, - // verilator coverage_off - output wire [DW-1:0] o_wb_data, // == const 0 - // verilator coverage_on - // And return inputs - input wire i_wb_stall, i_wb_ack, i_wb_err, - input wire [DW-1:0] i_wb_data - // }}} - ); - - // Declare local variables - // {{{ - reg invalid; - - wire r_valid; - wire [DATA_WIDTH-1:0] r_insn, i_wb_shifted; - // }}} - - // These are kind of obligatory outputs when dealing with a bus, that - // we'll set them here. Nothing's going to pay attention to these, - // though, this is primarily for form. - assign o_wb_we = 1'b0; - assign o_wb_data = {(DATA_WIDTH){1'b0}}; - - // o_wb_cyc, o_wb_stb - // {{{ - // Let's build it simple and upgrade later: For each instruction - // we do one bus cycle to get the instruction. Later we should - // pipeline this, but for now let's just do one at a time. - initial o_wb_cyc = 1'b0; - initial o_wb_stb = 1'b0; - always @(posedge i_clk) - if ((i_reset || i_clear_cache)||(o_wb_cyc &&(i_wb_ack||i_wb_err))) - begin - // {{{ - // End any bus cycle on a reset, or a return ACK - // or error. - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - // }}} - end else if (!o_wb_cyc &&( - // Start if the last instruction output was - // accepted, *and* it wasn't a bus error - // response - (i_ready && !o_illegal && !r_valid) - // Start if the last bus result ended up - // invalid - ||(invalid) - // Start on any request for a new address - ||i_new_pc)) - begin - // {{{ - // Initiate a bus transaction - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - // }}} - end else if (o_wb_cyc) - begin - // {{{ - // If our request has been accepted, then drop the - // strobe line - if (!i_wb_stall) - o_wb_stb <= 1'b0; - - // Abort on new-pc - // ... clear_cache is identical, save that it will - // immediately be followed by a new PC, so we don't - // need to worry about that other than to drop - // CYC and STB here. - if (i_new_pc) - begin - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - end - // }}} - end - // }}} - - // invalid - // {{{ - // If during the current bus request, a command came in from the CPU - // that will invalidate the results of that request, then we need to - // keep track of an "invalid" flag to remember that and so squash - // the result. - // - initial invalid = 1'b0; - always @(posedge i_clk) - if (i_reset || !o_wb_cyc) - invalid <= 1'b0; - else if (i_new_pc) - invalid <= 1'b1; - // }}} - - // The wishbone request address, o_wb_addr - // {{{ - // The rule regarding this address is that it can *only* be changed - // when no bus request is active. Further, since the CPU is depending - // upon this value to know what "PC" is associated with the instruction - // it is processing, we can't change until either the CPU has accepted - // our result, or it is requesting a new PC (and hence not using the - // output). - // - initial o_wb_addr= 0; - always @(posedge i_clk) - if (i_new_pc) - o_wb_addr <= i_pc[AW-1:$clog2(DATA_WIDTH/8)]; - else if (o_valid && i_ready && !r_valid) - o_wb_addr <= o_wb_addr + 1'b1; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // (Optionally) shift the output word into place - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // This only applies when the bus size doesn't match the instruction - // word size. Here, we only support bus sizes greater than the - // instruction word size. -`ifdef FORMAL - wire [DATA_WIDTH-1:0] f_bus_word; -`endif - - generate if (DATA_WIDTH > INSN_WIDTH) - begin : GEN_SUBSHIFT - // {{{ - localparam NSHIFT = $clog2(DATA_WIDTH/INSN_WIDTH); - - reg rg_valid; - reg [DATA_WIDTH-1:0] rg_insn; - reg [NSHIFT:0] r_count; - reg [NSHIFT-1:0] r_shift; - - // rg_valid - // {{{ - always @(posedge i_clk) - if (i_reset || i_new_pc || i_clear_cache) - rg_valid <= 1'b0; - else if (r_count <= ((o_valid && i_ready) ? 1:0)) - begin - rg_valid <= 1'b0; - if (o_wb_cyc && i_wb_ack && !(&r_shift)) - rg_valid <= 1'b1; - end - // }}} - - // rg_insn - // {{{ - always @(posedge i_clk) - if (i_wb_ack && (r_count <= ((o_valid && i_ready) ? 1:0))) - begin - rg_insn <= i_wb_data; - if (OPT_LITTLE_ENDIAN) - begin - rg_insn <= i_wb_shifted >> INSN_WIDTH; - end else begin - rg_insn <= i_wb_shifted << INSN_WIDTH; - end - end else if (o_valid && i_ready) - begin - if (OPT_LITTLE_ENDIAN) - rg_insn <= rg_insn >> INSN_WIDTH; - else - rg_insn <= rg_insn << INSN_WIDTH; - end - // }}} - - // r_count - // {{{ - always @(posedge i_clk) - if (i_reset || i_new_pc || i_clear_cache) - r_count <= 0; - // Verilator lint_off CMPCONST - else if (o_valid && i_ready && r_valid) - // Verilator lint_on CMPCONST - r_count <= r_count - 1; - else if (o_wb_cyc && i_wb_ack) - begin - // if (OPT_LITTLE_ENDIAN) - r_count <= { 1'b0, ~r_shift }; - end -`ifdef FORMAL - always @(*) - if (!i_reset) - begin - assert(r_valid == (r_count > 0)); - assert(r_count <= (1< 0) - assert(!o_valid && !r_valid); -`endif - // }}} - - assign r_valid = rg_valid; -; - assign r_insn = rg_insn; - if (OPT_LITTLE_ENDIAN) - begin : GEN_LIL_ENDIAN_SHIFT - assign i_wb_shifted = i_wb_data >> (r_shift * INSN_WIDTH); - end else begin : GEN_BIG_ENDIAN_SHIFT - assign i_wb_shifted = i_wb_data << (r_shift * INSN_WIDTH); - end - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused_shift; - assign unused_shift = &{ 1'b0, - r_insn[DATA_WIDTH-1:INSN_WIDTH], - i_wb_shifted[DATA_WIDTH-1:INSN_WIDTH] }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} -`ifdef FORMAL - assign f_bus_word = rg_insn << ((r_count-1)* INSN_WIDTH); - always @(*) - if (!i_reset && r_valid) - begin - assert(o_valid); - assert(r_shift == 0); - // assert((r_count + o_pc[NSHIFT-1:0]) == ((1< INSN_WIDTH) - begin : F_CHECK_SHIFTED_WORD - // {{{ - wire [DW-1:0] f_shifted_insn; - localparam IW = INSN_WIDTH; - - if (OPT_LITTLE_ENDIAN) - begin - assign f_shifted_insn = f_const_bus_word - >> (f_const_addr[$clog2(DW/8)-1:$clog2(IW/8)] * IW); - always @(*) - assume(f_shifted_insn[IW-1:0] == f_const_insn); - - end else begin - assign f_shifted_insn = f_const_bus_word - << (f_const_addr[$clog2(DW/8)-1:$clog2(IW/8)] * IW); - - always @(*) - assume(f_shifted_insn[DW-1:DW-IW] - == f_const_insn); - - end - // }}} - end else begin - // {{{ - always @(*) - assume(f_const_bus_word == f_const_insn); - // }}} - end endgenerate - - // f_addr_pending - // {{{ - initial f_addr_pending = 1'b0; - always @(posedge i_clk) - if (i_reset) - f_addr_pending <= 1'b0; - else if (!o_wb_cyc) - f_addr_pending <= 1'b0; - else if ((o_wb_stb)&&(f_this_addr)) - begin - if ((!i_wb_ack)&&(!i_wb_err)) - f_addr_pending <= 1'b1; - end - // }}} - - // 1. Assume the correct response for the given address - // {{{ - always @(*) - if ((o_wb_stb)&&(f_this_addr)&&(!i_wb_stall)) - begin - if (!f_const_illegal) - begin - assume(!i_wb_err); - end else - assume(!i_wb_ack); - if (i_wb_ack) - assume(f_this_data); - end else if ((o_wb_cyc)&&(f_addr_pending)) - begin - if (!f_const_illegal) - begin - assume(!i_wb_err); - end else - assume(!i_wb_ack); - if (i_wb_ack) - assume(f_this_data); - end - // }}} - - // f_insn_pending - // {{{ - initial f_insn_pending = 1'b0; - always @(posedge i_clk) - if (i_reset) - f_insn_pending <= 1'b0; - else if (i_clear_cache) - f_insn_pending <= 1'b0; - else if (i_new_pc && f_this_req) - f_insn_pending <= 1'b1; - else if ((o_valid)||(i_new_pc)) - f_insn_pending <= 1'b0; - // }}} - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_wb_cyc))&&(o_wb_cyc)&&(f_insn_pending)) - assert(f_this_pc); - - always @(posedge i_clk) - if (((f_past_valid)&&($past(o_wb_cyc))&&($past(f_insn_pending))) - &&(!$past(i_reset))&&(!$past(i_clear_cache)) - &&(!$past(i_new_pc))) - begin - if(!o_wb_cyc) - assert(o_valid && f_this_pc); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(o_wb_cyc))&&(!o_wb_cyc)) - assert(!f_insn_pending); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_wb_cyc))&&(o_wb_cyc)&&(f_this_addr)) - assert(f_addr_pending); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_wb_cyc))&&(f_insn_pending)) - assert(f_this_addr); - // }}} - - // Make Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused_formal; - assign unused_formal = &{ 1'b0, f_nreqs, f_nacks, f_outstanding, - f_const_addr[1:0] }; - // Verilator lint_on UNUSED - // }}} -`endif -// }}} -endmodule -// -// Usage: (this) (mid) (past) -// Cells 167 230 175 -// FDRE 67 97 69 -// LUT1 1 1 1 -// LUT2 1 3 3 -// LUT3 31 63 33 -// LUT4 5 3 3 -// LUT5 1 3 3 -// LUT6 2 1 3 -// MUXCY 29 29 31 -// XORCY 30 30 32 diff --git a/delete_later/rtl/cpu/slowmpy.v b/delete_later/rtl/cpu/slowmpy.v deleted file mode 100644 index dd3ce54..0000000 --- a/delete_later/rtl/cpu/slowmpy.v +++ /dev/null @@ -1,271 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: slowmpy.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is a signed (OPT_SIGNED=1) or unsigned (OPT_SIGNED=0) -// multiply designed for low logic and slow data signals. It -// takes one clock per bit plus two more to complete the multiply. -// -// The OPT_SIGNED version of this algorithm was found on Wikipedia at -// https://en.wikipedia.org/wiki/Binary_multiplier. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module slowmpy #( - // {{{ - parameter LGNA = 6, - parameter [LGNA:0] NA = 33, - parameter [0:0] OPT_SIGNED = 1'b1, - parameter [0:0] OPT_LOWPOWER = 1'b0, - localparam NB = NA // Must be = NA for OPT_SIGNED to work - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire i_stb, - input wire signed [(NA-1):0] i_a, - input wire signed [(NB-1):0] i_b, - // verilator coverage_off - input wire i_aux, - // verilator coverage_on - output reg o_busy, o_done, - output reg signed [(NA+NB-1):0] o_p, - // verilator coverage_off - output reg o_aux - // verilator coverage_on - // }}} - ); - - // Declarations - // {{{ - reg [LGNA-1:0] count; - reg [NA-1:0] p_a; - reg [NB-1:0] p_b; - reg [NA+NB-1:0] partial; - // verilator coverage_off - reg aux; - // verilator coverage_on - reg almost_done; - wire pre_done; - wire [NA-1:0] pwire; - // }}} - - assign pre_done = (count == 0); - - // almost_done - // {{{ - initial almost_done = 1'b0; - always @(posedge i_clk) - almost_done <= (!i_reset)&&(o_busy)&&(pre_done); - // }}} - - // aux, o_done, o_busy - // {{{ - initial aux = 0; - initial o_done = 0; - initial o_busy = 0; - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - aux <= 0; - o_done <= 0; - o_busy <= 0; - // }}} - end else if (!o_busy) - begin - // {{{ - o_done <= 0; - o_busy <= i_stb; - aux <= (!OPT_LOWPOWER || i_stb) ? i_aux : 0; - // }}} - end else if (almost_done) - begin - // {{{ - o_done <= 1; - o_busy <= 0; - // }}} - end else - o_done <= 0; - // }}} - - assign pwire = (p_b[0] ? p_a : 0); - - // count, partial, p_a, p_b - // {{{ - always @(posedge i_clk) - if (!o_busy) - begin - count <= NA[LGNA-1:0]-1; - partial <= 0; - p_a <= i_a; - p_b <= i_b; - - if (OPT_LOWPOWER && !i_stb) - begin - p_a <= 0; - p_b <= 0; - end - end else begin - p_b <= (p_b >> 1); - // partial[NA+NB-1:NB] <= partial[NA+NB - partial[NB-2:0] <= partial[NB-1:1]; - if ((OPT_SIGNED)&&(pre_done)) - partial[NA+NB-1:NB-1] <= { 1'b0, partial[NA+NB-1:NB]} + - { 1'b0, pwire[NA-1], ~pwire[NA-2:0] }; - else if (OPT_SIGNED) - partial[NA+NB-1:NB-1] <= {1'b0,partial[NA+NB-1:NB]} + - { 1'b0, !pwire[NA-1], pwire[NA-2:0] }; - else - partial[NA+NB-1:NB-1] <= {1'b0, partial[NA+NB-1:NB]} - + ((p_b[0]) ? {1'b0,p_a} : 0); - count <= count - 1; - end - // }}} - - // o_p, o_aux - // {{{ - always @(posedge i_clk) - if (almost_done) - begin - if (OPT_SIGNED) - o_p <= partial[NA+NB-1:0] - + { 1'b1, {(NA-2){1'b0}}, 1'b1, {(NB){1'b0}} }; - else - o_p <= partial[NA+NB-1:0]; - o_aux <= aux; - end - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations and reset - // {{{ -`define ASSERT assert -`ifdef SLOWMPY -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - initial assume(i_reset); - always @(*) - if (!f_past_valid) - `ASSUME(i_reset); - // }}} - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))) - begin - `ASSERT(almost_done == 0); - `ASSERT(o_done == 0); - `ASSERT(o_busy == 0); - `ASSERT(aux == 0); - end - - // Assumptions about our inputs - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_stb))&&($past(o_busy))) - begin - `ASSUME(i_stb); - `ASSUME($stable(i_a)); - `ASSUME($stable(i_b)); - end - - // - // For now, just formally verify our internal signaling - // {{{ - - always @(posedge i_clk) - `ASSERT(almost_done == (o_busy&&(&count))); - - always @(*) - if (!(&count[LGNA-1:1])||(count[0])) - `ASSERT(!o_done); - - always @(posedge i_clk) - if (o_done) - `ASSERT(!o_busy); - always @(posedge i_clk) - if (!o_busy) - `ASSERT(!almost_done); - - reg [NA-1:0] f_a, f_b; - always @(posedge i_clk) - if ((i_stb)&&(!o_busy)) - begin - f_a <= i_a; - f_b <= i_b; - end - - always @(*) - if (o_done) - begin - if ((f_a == 0)||(f_b == 0)) - begin - `ASSERT(o_p == 0); - end else - `ASSERT(o_p[NA+NB-1] == f_a[NA-1] ^ f_b[NA-1]); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - always @(posedge i_clk) - cover(o_done); - - reg cvr_past_done; - initial cvr_past_done = 1'b0; - always @(posedge i_clk) - if (o_done) - cvr_past_done <= 1'b1; - - always @(posedge i_clk) - cover((o_done)&&(cvr_past_done)); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/wbarbiter.v b/delete_later/rtl/cpu/wbarbiter.v deleted file mode 100644 index 6a88b61..0000000 --- a/delete_later/rtl/cpu/wbarbiter.v +++ /dev/null @@ -1,380 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbarbiter.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is a priority bus arbiter. It allows two separate wishbone -// masters to connect to the same bus, while also guaranteeing -// that the last master can have the bus with no delay any time it is -// idle. The goal is to minimize the combinatorial logic required in this -// process, while still minimizing access time. -// -// The core logic works like this: -// -// 1. If 'A' or 'B' asserts the o_cyc line, a bus cycle will begin, -// with acccess granted to whomever requested it. -// 2. If both 'A' and 'B' assert o_cyc at the same time, only 'A' -// will be granted the bus. (If the alternating parameter -// is set, A and B will alternate who gets the bus in -// this case.) -// 3. The bus will remain owned by whomever the bus was granted to -// until they deassert the o_cyc line. -// 4. At the end of a bus cycle, o_cyc is guaranteed to be -// deasserted (low) for one clock. -// 5. On the next clock, bus arbitration takes place again. If -// 'A' requests the bus, no matter how long 'B' was -// waiting, 'A' will then be granted the bus. (Unless -// again the alternating parameter is set, then the -// access is guaranteed to switch to B.) -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// -`define WBA_ALTERNATING -// }}} -module wbarbiter #( - // {{{ - parameter DW=32, AW=32, - parameter SCHEME="ALTERNATING", - parameter [0:0] OPT_ZERO_ON_IDLE = 1'b0 -`ifdef FORMAL - , parameter F_MAX_STALL = 3, - parameter F_MAX_ACK_DELAY = 3, - parameter F_LGDEPTH=3 -`endif - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Bus A -- the priority bus - // {{{ - input wire i_a_cyc, i_a_stb, i_a_we, - input wire [(AW-1):0] i_a_adr, - input wire [(DW-1):0] i_a_dat, - input wire [(DW/8-1):0] i_a_sel, - output wire o_a_stall, o_a_ack, o_a_err, - // }}} - // Bus B - // {{{ - input wire i_b_cyc, i_b_stb, i_b_we, - input wire [(AW-1):0] i_b_adr, - input wire [(DW-1):0] i_b_dat, - input wire [(DW/8-1):0] i_b_sel, - output wire o_b_stall, o_b_ack, o_b_err, - // }}} - // Combined/arbitrated bus - // {{{ - output wire o_cyc, o_stb, o_we, - output wire [(AW-1):0] o_adr, - output wire [(DW-1):0] o_dat, - output wire [(DW/8-1):0] o_sel, - input wire i_stall, i_ack, i_err - // }}} -`ifdef FORMAL - , output wire [(F_LGDEPTH-1):0] - f_nreqs, f_nacks, f_outstanding, - f_a_nreqs, f_a_nacks, f_a_outstanding, - f_b_nreqs, f_b_nacks, f_b_outstanding -`endif - // }}} - ); - - // {{{ - // Go high immediately (new cycle) if ... - // Previous cycle was low and *someone* is requesting a bus cycle - // Go low immadiately if ... - // We were just high and the owner no longer wants the bus - // WISHBONE Spec recommends no logic between a FF and the o_cyc - // This violates that spec. (Rec 3.15, p35) - // }}} - - // Local declarations - // {{{ - reg r_a_owner; - // }}} - - assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc; - initial r_a_owner = 1'b1; - - // r_a_owner -- determined through arbitration - // {{{ - generate if (SCHEME == "PRIORITY") - begin : PRI - // {{{ - always @(posedge i_clk) - if (!i_b_cyc) - r_a_owner <= 1'b1; - // Allow B to set its CYC line w/o activating this - // interface - else if ((i_b_stb)&&(!i_a_cyc)) - r_a_owner <= 1'b0; - // }}} - end else if (SCHEME == "ALTERNATING") - begin : ALT - // {{{ - reg last_owner; - - initial last_owner = 1'b0; - always @(posedge i_clk) - if ((i_a_cyc)&&(r_a_owner)) - last_owner <= 1'b1; - else if ((i_b_cyc)&&(!r_a_owner)) - last_owner <= 1'b0; - - always @(posedge i_clk) - if ((!i_a_cyc)&&(!i_b_cyc)) - r_a_owner <= !last_owner; - else if ((r_a_owner)&&(!i_a_cyc)) - begin - - if (i_b_stb) - r_a_owner <= 1'b0; - - end else if ((!r_a_owner)&&(!i_b_cyc)) - begin - - if (i_a_stb) - r_a_owner <= 1'b1; - - end - // }}} - end else // if (SCHEME == "LAST") - begin : LST - // {{{ - always @(posedge i_clk) - if ((!i_a_cyc)&&(i_b_stb)) - r_a_owner <= 1'b0; - else if ((!i_b_cyc)&&(i_a_stb)) - r_a_owner <= 1'b1; - // ?}}} - end endgenerate - // }}} - - // o_we - // {{{ - // Realistically, if neither master owns the bus, the output is a - // don't care. Thus we trigger off whether or not 'A' owns the bus. - // If 'B' owns it all we care is that 'A' does not. Likewise, if - // neither owns the bus than the values on the various lines are - // irrelevant. - assign o_we = (r_a_owner) ? i_a_we : i_b_we; - // }}} - - // Other bus outputs - // {{{ - generate if (OPT_ZERO_ON_IDLE) - begin : LOW_POWER - // {{{ - // OPT_ZERO_ON_IDLE will use up more logic and may even slow - // down the master clock if set. However, it may also reduce - // the power used by the FPGA by preventing things from toggling - // when the bus isn't in use. The option is here because it - // also makes it a lot easier to look for when things happen - // on the bus via VERILATOR when timing and logic counts - // don't matter. - // - assign o_stb = (o_cyc)? ((r_a_owner) ? i_a_stb : i_b_stb):0; - assign o_adr = (o_stb)? ((r_a_owner) ? i_a_adr : i_b_adr):0; - assign o_dat = (o_stb)? ((r_a_owner) ? i_a_dat : i_b_dat):0; - assign o_sel = (o_stb)? ((r_a_owner) ? i_a_sel : i_b_sel):0; - assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0; - assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0; - assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1; - assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1; - assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0; - assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0; - // }}} - end else begin : LOW_LOGIC - // {{{ - - assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb; - assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; - assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; - assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel; - - // We cannot allow the return acknowledgement to ever go high if - // the master in question does not own the bus. Hence we force - // it low if the particular master doesn't own the bus. - assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0; - assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0; - - // Stall must be asserted on the same cycle the input master - // asserts the bus, if the bus isn't granted to him. - assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; - assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1; - - // - // - assign o_a_err = ( r_a_owner) ? i_err : 1'b0; - assign o_b_err = (!r_a_owner) ? i_err : 1'b0; - // }}} - end endgenerate - // }}} - - // Make Verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_reset }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - -`ifdef WBARBITER -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - initial `ASSUME(!i_a_cyc); - initial `ASSUME(!i_a_stb); - - initial `ASSUME(!i_b_cyc); - initial `ASSUME(!i_b_stb); - - initial `ASSUME(!i_ack); - initial `ASSUME(!i_err); - - always @(*) - if (!f_past_valid) - `ASSUME(i_reset); - - always @(posedge i_clk) - begin - if (o_cyc) - assert((i_a_cyc)||(i_b_cyc)); - if ((f_past_valid)&&($past(o_cyc))&&(o_cyc)) - assert($past(r_a_owner) == r_a_owner); - end - - fwb_master #( - // {{{ - .DW(DW), .AW(AW), - .F_MAX_STALL(F_MAX_STALL), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(F_MAX_ACK_DELAY), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1), - .F_OPT_CLK2FFLOGIC(1'b0) - // }}} - ) f_wbm ( - // {{{ - i_clk, i_reset, - o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, - i_ack, i_stall, 32'h0, i_err, - f_nreqs, f_nacks, f_outstanding - // }}} - ); - - fwb_slave #( - // {{{ - .DW(DW), .AW(AW), - .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1), - .F_OPT_CLK2FFLOGIC(1'b0) - // }}} - ) f_wba ( - // {{{ - i_clk, i_reset, - i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, - o_a_ack, o_a_stall, 32'h0, o_a_err, - f_a_nreqs, f_a_nacks, f_a_outstanding - // }}} - ); - - fwb_slave #( - // {{{ - .DW(DW), .AW(AW), - .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1), - .F_OPT_CLK2FFLOGIC(1'b0) - // }}} - ) f_wbb ( - // {{{ - i_clk, i_reset, - i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, - o_b_ack, o_b_stall, 32'h0, o_b_err, - f_b_nreqs, f_b_nacks, f_b_outstanding - // }}} - ); - - // Induction properties, relating nreqs and nacks to r_a_owner - // {{{ - always @(posedge i_clk) - if (r_a_owner) - begin - assert(f_b_nreqs == 0); - assert(f_b_nacks == 0); - assert(f_a_outstanding == f_outstanding); - end else begin - assert(f_a_nreqs == 0); - assert(f_a_nacks == 0); - assert(f_b_outstanding == f_outstanding); - end - // }}} - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset)) - &&($past(i_a_stb))&&(!$past(i_b_cyc))) - assert(r_a_owner); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset)) - &&(!$past(i_a_cyc))&&($past(i_b_stb))) - assert(!r_a_owner); - - always @(posedge i_clk) - if ((f_past_valid)&&(r_a_owner != $past(r_a_owner))) - assert(!$past(o_cyc)); - -`endif -// }}} -endmodule - diff --git a/delete_later/rtl/cpu/wbdblpriarb.v b/delete_later/rtl/cpu/wbdblpriarb.v deleted file mode 100644 index 280cbd3..0000000 --- a/delete_later/rtl/cpu/wbdblpriarb.v +++ /dev/null @@ -1,531 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbdblpriarb.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This should almost be identical to the priority arbiter, save -// for a simple diffence: it allows the arbitration of two -// separate wishbone buses. The purpose of this is to push the address -// resolution back one cycle, so that by the first clock visible to this -// core, it is known which of two parts of the bus the desired address -// will be on, save that we still use the arbiter since the underlying -// device doesn't know that there are two wishbone buses. -// -// So at this point we've deviated from the WB spec somewhat, by allowing -// two CYC and two STB lines. Everything else is the same. This allows -// (in this case the Zip CPU) to determine whether or not the access -// will be to the local ZipSystem bus or the external WB bus on the clock -// before the local bus access, otherwise peripherals were needing to do -// multiple device selection comparisons/test within a clock: 1) is this -// for the local or external bus, and 2) is this referencing me as a -// peripheral. This then caused the ZipCPU to fail all timing specs. -// By creating the two pairs of lines, CYC_A/STB_A and CYC_B/STB_B, the -// determination of local vs external can be made one clock earlier -// where there's still time for the logic, and the second comparison -// now has time to complete. -// -// So let me try to explain this again. To use this arbiter, one of the -// two masters sets CYC and STB before, only the master determines which -// of two address spaces the CYC and STB apply to before the clock and -// only sets the appropriate CYC and STB lines. Then, on the clock tick, -// the arbiter determines who gets *both* busses, as they both share every -// other WB line. Thus, only one of CYC_A and CYC_B going out will ever -// be high at a given time. -// -// Hopefully this makes more sense than it sounds. If not, check out the -// code below for a better explanation. -// -// 20150919 -- Added supported for the WB error signal. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbdblpriarb #( - // {{{ - parameter DW=32, AW=32, - // OPT_ZERO_ON_IDLE - // {{{ - // OPT_ZERO_ON_IDLE uses more logic than the alternative. It - // should be useful for reducing power, as these circuits tend - // to drive wires all the way across the design, but it may also - // slow down the master clock. I've used it as an option when - // using VER1LATOR, 'cause zeroing things on idle can make them - // stand out all the more when staring at wires and dumps and - // such. - parameter [0:0] OPT_ZERO_ON_IDLE = 1'b0 - // }}} -`ifdef FORMAL - // Parameters used in the formal proof only - , parameter F_LGDEPTH = 3, - parameter F_MAX_STALL = 0, - parameter F_MAX_ACK_DELAY=0 -`endif - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Bus A - // {{{ - input wire i_a_cyc_a, i_a_cyc_b, - i_a_stb_a, i_a_stb_b, i_a_we, - input wire [(AW-1):0] i_a_adr, - input wire [(DW-1):0] i_a_dat, - input wire [(DW/8-1):0] i_a_sel, - output wire o_a_stall, o_a_ack, o_a_err, - // }}} - // Bus B - // {{{ - input wire i_b_cyc_a, i_b_cyc_b, - i_b_stb_a, i_b_stb_b, i_b_we, - input wire [(AW-1):0] i_b_adr, - input wire [(DW-1):0] i_b_dat, - input wire [(DW/8-1):0] i_b_sel, - output wire o_b_stall, o_b_ack, o_b_err, - // }}} - // Both buses (i.e. the outgoing, arbitrated bus) - // {{{ - output wire o_cyc_a, o_cyc_b, - o_stb_a, o_stb_b, o_we, - output wire [(AW-1):0] o_adr, - output wire [(DW-1):0] o_dat, - output wire [(DW/8-1):0] o_sel, - input wire i_stall, i_ack, i_err - // }}} -`ifdef FORMAL - // {{{ - // These wires are relics from when the ZipCPU was verified - // with this arbiter internal to it. Since this is no longer - // the case, they're now no more than declarations - , output wire [(F_LGDEPTH-1):0] - f_nreqs_a, f_nacks_a, f_outstanding_a, - f_nreqs_b, f_nacks_b, f_outstanding_b, - f_a_nreqs_a, f_a_nacks_a, f_a_outstanding_a, - f_a_nreqs_b, f_a_nacks_b, f_a_outstanding_b, - f_b_nreqs_a, f_b_nacks_a, f_b_outstanding_a, - f_b_nreqs_b, f_b_nacks_b, f_b_outstanding_b - // }}} -`endif - // }}} - ); - - // r_a_owner - // {{{ - // All of our logic is really captured in the 'r_a_owner' register. - // This register determines who owns the bus. If no one is requesting - // the bus, ownership goes to A on the next clock. Otherwise, if B is - // requesting the bus and A is not, then ownership goes to not A on - // the next clock. (Sounds simple ...) - // - // The CYC logic is here to make certain that, by the time we determine - // who the bus owner is, we can do so based upon determined criteria. - reg r_a_owner; - - initial r_a_owner = 1'b1; - always @(posedge i_clk) - if (i_reset) - r_a_owner <= 1'b1; - /* - // Remain with the "last owner" until 1) the other bus requests - // access, and 2) the last owner no longer wants it. This - // logic "idles" on the last owner. - // - // This is an alternating bus owner strategy - // - else if ((!o_cyc_a)&&(!o_cyc_b)) - r_a_owner <= ((i_b_stb_a)||(i_b_stb_b))? 1'b0:1'b1; - // - // Expanding this out - // - // else if ((r_a_owner)&&((i_a_cyc_a)||(i_a_cyc_b))) - // r_a_owner <= 1'b1; - // else if ((!r_a_owner)&&((i_b_cyc_a)||(i_b_cyc_b))) - // r_a_owner <= 1'b0; - // else if ((r_a_owner)&&((i_b_stb_a)||(i_b_stb_b))) - // r_a_owner <= 1'b0; - // else if ((!r_a_owner)&&((i_a_stb_a)||(i_a_stb_b))) - // r_a_owner <= 1'b0; - // - // Logic required: - // - // Reset line - // + 9 inputs (data) - // + 9 inputs (CE) - // Could be done with three LUTs - // First two evaluate o_cyc_a and o_cyc_b (above) - */ - // Option 2: - // - // "Idle" on A as the owner. - // If a request is made from B, AND A is idle, THEN - // switch. Otherwise, if B is ever idle, revert back to A - // regardless of whether A wants it or not. - else if ((!i_b_cyc_a)&&(!i_b_cyc_b)) - r_a_owner <= 1'b1; - else if ((!i_a_cyc_a)&&(!i_a_cyc_b) - &&((i_b_stb_a)||(i_b_stb_b))) - r_a_owner <= 1'b0; - // }}} - - // o_cyc*, o_stb*, o_we - // {{{ - // Realistically, if neither master owns the bus, the output is a - // don't care. Thus we trigger off whether or not 'A' owns the bus. - // If 'B' owns it all we care is that 'A' does not. Likewise, if - // neither owns the bus than the values on these various lines are - // irrelevant. - - assign o_cyc_a = ((r_a_owner) ? i_a_cyc_a : i_b_cyc_a); - assign o_cyc_b = ((r_a_owner) ? i_a_cyc_b : i_b_cyc_b); - assign o_stb_a = (r_a_owner) ? i_a_stb_a : i_b_stb_a; - assign o_stb_b = (r_a_owner) ? i_a_stb_b : i_b_stb_b; - assign o_we = (r_a_owner) ? i_a_we : i_b_we; - // }}} - - // Other bus outputs and returns - // {{{ - generate if (OPT_ZERO_ON_IDLE) - begin : OPT_LOWPOWER - // {{{ - wire o_cyc, o_stb; - - assign o_cyc = ((o_cyc_a)||(o_cyc_b)); - assign o_stb = ((o_stb_a)||(o_stb_b)); - assign o_adr = (o_stb)?((r_a_owner) ? i_a_adr : i_b_adr):0; - assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0; - assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0; - assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0; - assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0; - assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1; - assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1; - assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0; - assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0; - // }}} - end else begin : OPT_LOWLOGIC - // {{{ - assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; - assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; - assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel; - - // We cannot allow the return acknowledgement to ever go high if - // the master in question does not own the bus. Hence we force it - // low if the particular master doesn't own the bus. - assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0; - assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0; - - // Stall must be asserted on the same cycle the input master asserts - // the bus, if the bus isn't granted to him. - assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; - assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1; - - // - // - assign o_a_err = ( r_a_owner) ? i_err : 1'b0; - assign o_b_err = (!r_a_owner) ? i_err : 1'b0; - // }}} - end endgenerate - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`define ASSERT assert -`ifdef WBDBLPRIARB -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - initial `ASSUME(i_reset); - always @(*) - if (!f_past_valid) - `ASSUME(i_reset); - - initial `ASSUME(!i_a_cyc_a); - initial `ASSUME(!i_a_stb_a); - initial `ASSUME(!i_a_cyc_b); - initial `ASSUME(!i_a_stb_b); - - initial `ASSUME(!i_b_cyc_a); - initial `ASSUME(!i_b_stb_a); - initial `ASSUME(!i_b_cyc_b); - initial `ASSUME(!i_b_stb_b); - - initial `ASSUME(!i_ack); - initial `ASSUME(!i_err); - - always @(*) - `ASSUME((!i_a_cyc_a)||(!i_a_cyc_b)); - always @(*) - `ASSUME((!i_b_cyc_a)||(!i_b_cyc_b)); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_a_cyc_a))) - `ASSUME(!i_a_cyc_b); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_a_cyc_b))) - `ASSUME(!i_a_cyc_a); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_b_cyc_a))) - `ASSUME(!i_b_cyc_b); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_b_cyc_b))) - `ASSUME(!i_b_cyc_a); - - wire f_cyc, f_stb; - assign f_cyc = (o_cyc_a)||(o_cyc_b); - assign f_stb = (o_stb_a)||(o_stb_b); - always @(posedge i_clk) - begin - if (o_cyc_a) - `ASSERT((i_a_cyc_a)||(i_b_cyc_a)); - if (o_cyc_b) - `ASSERT((i_a_cyc_b)||(i_b_cyc_b)); - `ASSERT((!o_cyc_a)||(!o_cyc_b)); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))) - begin - if ($past(f_cyc)) - begin - if (($past(o_cyc_a))&&(o_cyc_a)) - `ASSERT($past(r_a_owner) == r_a_owner); - if (($past(o_cyc_b))&&(o_cyc_b)) - `ASSERT($past(r_a_owner) == r_a_owner); - end else begin - if (($past(i_a_stb_a))||($past(i_a_stb_b))) - `ASSERT(r_a_owner); - if (($past(i_b_stb_a))||($past(i_b_stb_b))) - `ASSERT(!r_a_owner); - end - end - - - fwb_master #( - // {{{ - .AW(AW), .DW(DW), - .F_MAX_STALL(F_MAX_STALL), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(F_MAX_ACK_DELAY), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wbm_a ( - // {{{ - i_clk, i_reset, - o_cyc_a, o_stb_a, o_we, o_adr, o_dat, o_sel, - (o_cyc_a)&&(i_ack), i_stall, 32'h0, (o_cyc_a)&&(i_err), - f_nreqs_a, f_nacks_a, f_outstanding_a - // }}} - ); - - - fwb_master #( - // {{{ - .AW(AW), .DW(DW), - .F_MAX_STALL(F_MAX_STALL), - .F_MAX_ACK_DELAY(F_MAX_ACK_DELAY), - .F_LGDEPTH(F_LGDEPTH), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wbm_b( - // {{{ - i_clk, i_reset, - o_cyc_b, o_stb_b, o_we, o_adr, o_dat, o_sel, - (o_cyc_b)&&(i_ack), i_stall, 32'h0, (o_cyc_b)&&(i_err), - f_nreqs_b, f_nacks_b, f_outstanding_b - // }}} - ); - -`ifdef WBDBLPRIARB -`define F_SLAVE fwb_slave -`else -`define F_SLAVE fwb_counter -`endif - - `F_SLAVE #( - // {{{ - .AW(AW), .DW(DW), .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wba_a( - // {{{ - i_clk, i_reset, - i_a_cyc_a, i_a_stb_a, i_a_we, i_a_adr, i_a_dat, i_a_sel, - (o_cyc_a)&&(o_a_ack), o_a_stall, 32'h0, (o_cyc_a)&&(o_a_err), - f_a_nreqs_a, f_a_nacks_a, f_a_outstanding_a - // }}} - ); - - `F_SLAVE #( - // {{{ - .AW(AW), .DW(DW), .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wba_b( - // {{{ - i_clk, i_reset, - i_a_cyc_b, i_a_stb_b, i_a_we, i_a_adr, i_a_dat, i_a_sel, - (o_cyc_b)&&(o_a_ack), o_a_stall, 32'h0, (o_cyc_b)&&(o_a_err), - f_a_nreqs_b, f_a_nacks_b, f_a_outstanding_b - // }}} - ); - - `F_SLAVE #( - // {{{ - .AW(AW), .DW(DW), .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wbb_a( - // {{{ - i_clk, i_reset, - i_b_cyc_a, i_b_stb_a, i_b_we, i_b_adr, i_b_dat, i_b_sel, - (o_cyc_a)&&(o_b_ack), o_b_stall, 32'h0, (o_cyc_a)&&(o_b_err), - f_b_nreqs_a, f_b_nacks_a, f_b_outstanding_a - // }}} - ); - - `F_SLAVE #( - // {{{ - .AW(AW), .DW(DW), .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wbb_b( - // {{{ - i_clk, i_reset, - i_b_cyc_b, i_b_stb_b, i_b_we, i_b_adr, i_b_dat, i_b_sel, - (o_cyc_b)&&(o_b_ack), o_b_stall, 32'h0, (o_cyc_b)&&(o_b_err), - f_b_nreqs_b, f_b_nacks_b, f_b_outstanding_b - // }}} - ); - - // Induction properties, relating nreqs and nacks to r_a_owner - // {{{ - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))) - begin - if (r_a_owner) - begin : A_IS_OWNER - // {{{ - `ASSERT(f_b_nreqs_a == 0); - `ASSERT(f_b_nreqs_b == 0); - // - `ASSERT(f_b_nacks_a == 0); - `ASSERT(f_b_nacks_b == 0); - // - if (i_a_cyc_a) - begin - `ASSERT(f_a_outstanding_a == f_outstanding_a); - `ASSERT(f_a_outstanding_b == 0); - `ASSERT(f_outstanding_b == 0); - `ASSERT(f_a_nreqs_b == 0); - `ASSERT(f_a_nacks_b == 0); - end else if (i_a_cyc_b) - begin - `ASSERT(f_a_outstanding_b == f_outstanding_b); - `ASSERT(f_a_outstanding_a == 0); - `ASSERT(f_outstanding_a == 0); - `ASSERT(f_a_nreqs_a == 0); - `ASSERT(f_a_nacks_a == 0); - end - // }}} - end else begin : B_IS_OWNER - // {{{ - `ASSERT(f_a_nreqs_a == 0); - `ASSERT(f_a_nreqs_b == 0); - // - `ASSERT(f_a_nacks_a == 0); - `ASSERT(f_a_nacks_b == 0); - // - if (i_b_cyc_a) - begin - `ASSERT(f_b_outstanding_a == f_outstanding_a); - `ASSERT(f_b_outstanding_b == 0); - `ASSERT(f_outstanding_b == 0); - `ASSERT(f_b_nreqs_b == 0); - `ASSERT(f_b_nacks_b == 0); - end else if (i_b_cyc_b) - begin - `ASSERT(f_b_outstanding_b == f_outstanding_b); - `ASSERT(f_b_outstanding_a == 0); - `ASSERT(f_outstanding_a == 0); - `ASSERT(f_b_nreqs_a == 0); - `ASSERT(f_b_nacks_a == 0); - end - // }}} - end - end - // }}} - - always @(posedge i_clk) - if ((r_a_owner)&&(i_b_cyc_a)) - `ASSUME((i_b_stb_a)&&(!i_b_stb_b)); - - always @(posedge i_clk) - if ((r_a_owner)&&(i_b_cyc_b)) - `ASSUME((i_b_stb_b)&&(!i_b_stb_a)); - - always @(posedge i_clk) - if ((!r_a_owner)&&(i_a_cyc_a)) - `ASSUME((i_a_stb_a)&&(!i_a_stb_b)); - - always @(posedge i_clk) - if ((!r_a_owner)&&(i_a_cyc_b)) - `ASSUME((i_a_stb_b)&&(!i_a_stb_a)); - -`endif -// }}} -endmodule - diff --git a/delete_later/rtl/cpu/wbpriarbiter.v b/delete_later/rtl/cpu/wbpriarbiter.v deleted file mode 100644 index 86079d7..0000000 --- a/delete_later/rtl/cpu/wbpriarbiter.v +++ /dev/null @@ -1,296 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbpriarbiter.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is a priority bus arbiter. It allows two separate wishbone -// masters to connect to the same bus, while also guaranteeing -// that one master can have the bus with no delay any time the other -// master is not using the bus. The goal is to eliminate the combinatorial -// logic required in the other wishbone arbiter, while still guarateeing -// access time for the priority channel. -// -// The core logic works like this: -// -// 1. When no one requests the bus, 'A' is granted the bus and guaranteed -// that any access will go right through. -// 2. If 'B' requests the bus (asserts cyc), and the bus is idle, then -// 'B' will be granted the bus. -// 3. Bus grants last as long as the 'cyc' line is high. -// 4. Once 'cyc' is dropped, the bus returns to 'A' as the owner. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbpriarbiter #( - // {{{ - parameter DW=32, AW=32, - // OPT_ZERO_ON_IDLE - // {{{ - // ZERO_ON_IDLE uses more logic than the alternative. It should - // be useful for reducing power, as these circuits tend to drive - // wires all the way across the design, but it may also slow - // down the master clock. I've used it as an option when using - // VER1LATOR, 'cause zeroing things on idle can make them stand - // out all the more when staring at wires and dumps and such. - parameter [0:0] OPT_ZERO_ON_IDLE = 1'b0 - // }}} - // }}} - ) ( - // {{{ - input wire i_clk, - // Bus A - // {{{ - input wire i_a_cyc, i_a_stb, i_a_we, - input wire [(AW-1):0] i_a_adr, - input wire [(DW-1):0] i_a_dat, - input wire [(DW/8-1):0] i_a_sel, - output wire o_a_stall, o_a_ack, o_a_err, - // }}} - // Bus B - // {{{ - input wire i_b_cyc, i_b_stb, i_b_we, - input wire [(AW-1):0] i_b_adr, - input wire [(DW-1):0] i_b_dat, - input wire [(DW/8-1):0] i_b_sel, - output wire o_b_stall, o_b_ack, o_b_err, - // }}} - // Outgoing combined bus - // {{{ - output wire o_cyc, o_stb, o_we, - output wire [(AW-1):0] o_adr, - output wire [(DW-1):0] o_dat, - output wire [(DW/8-1):0] o_sel, - input wire i_stall, i_ack, i_err - // }}} - // }}} - ); - - reg r_a_owner; - - // r_a_owner - // {{{ - // Go high immediately (new cycle) if ... - // Previous cycle was low and *someone* is requesting a bus cycle - // Go low immadiately if ... - // We were just high and the owner no longer wants the bus - // WISHBONE Spec recommends no logic between a FF and the o_cyc - // This violates that spec. (Rec 3.15, p35) - initial r_a_owner = 1'b1; - always @(posedge i_clk) - if (!i_b_cyc) - r_a_owner <= 1'b1; - // Allow B to set its CYC line w/o activating this interface - else if ((i_b_cyc)&&(i_b_stb)&&(!i_a_cyc)) - r_a_owner <= 1'b0; - // }}} - - // CYC, STB, and WE - // {{{ - // Realistically, if neither master owns the bus, the output is a - // don't care. Thus we trigger off whether or not 'A' owns the bus. - // If 'B' owns it all we care is that 'A' does not. Likewise, if - // neither owns the bus than the values on these various lines are - // irrelevant. - - assign o_cyc = (r_a_owner) ? i_a_cyc : i_b_cyc; - assign o_we = (r_a_owner) ? i_a_we : i_b_we; - assign o_stb = (r_a_owner) ? i_a_stb : i_b_stb; - // }}} - - // Everything else - // {{{ - generate if (OPT_ZERO_ON_IDLE) - begin : OPT_LOWPOWER - // {{{ - assign o_adr = (o_stb)?((r_a_owner) ? i_a_adr : i_b_adr):0; - assign o_dat = (o_stb)?((r_a_owner) ? i_a_dat : i_b_dat):0; - assign o_sel = (o_stb)?((r_a_owner) ? i_a_sel : i_b_sel):0; - assign o_a_ack = (o_cyc)&&( r_a_owner) ? i_ack : 1'b0; - assign o_b_ack = (o_cyc)&&(!r_a_owner) ? i_ack : 1'b0; - assign o_a_stall = (o_cyc)&&( r_a_owner) ? i_stall : 1'b1; - assign o_b_stall = (o_cyc)&&(!r_a_owner) ? i_stall : 1'b1; - assign o_a_err = (o_cyc)&&( r_a_owner) ? i_err : 1'b0; - assign o_b_err = (o_cyc)&&(!r_a_owner) ? i_err : 1'b0; - // }}} - end else begin : OPT_LOWLOGIC - // {{{ - assign o_adr = (r_a_owner) ? i_a_adr : i_b_adr; - assign o_dat = (r_a_owner) ? i_a_dat : i_b_dat; - assign o_sel = (r_a_owner) ? i_a_sel : i_b_sel; - - // We cannot allow the return acknowledgement to ever go high if - // the master in question does not own the bus. Hence we force it - // low if the particular master doesn't own the bus. - assign o_a_ack = ( r_a_owner) ? i_ack : 1'b0; - assign o_b_ack = (!r_a_owner) ? i_ack : 1'b0; - - // Stall must be asserted on the same cycle the input master asserts - // the bus, if the bus isn't granted to him. - assign o_a_stall = ( r_a_owner) ? i_stall : 1'b1; - assign o_b_stall = (!r_a_owner) ? i_stall : 1'b1; - - // - // - assign o_a_err = ( r_a_owner) ? i_err : 1'b0; - assign o_b_err = (!r_a_owner) ? i_err : 1'b0; - // }}} - end endgenerate - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`ifdef WBPRIARBITER -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - initial assume(!i_a_cyc); - initial assume(!i_a_stb); - - initial assume(!i_b_cyc); - initial assume(!i_b_stb); - - initial assume(!i_ack); - initial assume(!i_err); - - always @(posedge i_clk) - begin - if (o_cyc) - assert((i_a_cyc)||(i_b_cyc)); - if ((f_past_valid)&&($past(o_cyc))&&(o_cyc)) - assert($past(r_a_owner) == r_a_owner); - if ((f_past_valid)&&($past(!o_cyc))&&($past(i_a_stb))) - assert(r_a_owner); - if ((f_past_valid)&&($past(!o_cyc))&&($past(i_b_stb))) - assert(!r_a_owner); - end - - reg f_reset; - initial f_reset = 1'b1; - always @(posedge i_clk) - f_reset <= 1'b0; - always @(*) - if (!f_past_valid) - assert(f_reset); - - parameter F_LGDEPTH=3; - - wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding, - f_a_nreqs, f_a_nacks, f_a_outstanding, - f_b_nreqs, f_b_nacks, f_b_outstanding; - - fwb_master #( - // {{{ - .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wbm( - // {{{ - i_clk, f_reset, - o_cyc, o_stb, o_we, o_adr, o_dat, o_sel, - i_ack, i_stall, 32'h0, i_err, - f_nreqs, f_nacks, f_outstanding - // }}} - ); - - fwb_slave #( - // {{{ - .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wba( - // {{{ - i_clk, f_reset, - i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, i_a_sel, - o_a_ack, o_a_stall, 32'h0, o_a_err, - f_a_nreqs, f_a_nacks, f_a_outstanding - // }}} - ); - - fwb_slave #( - // {{{ - .F_MAX_STALL(0), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_ACK_DELAY(0), - .F_OPT_RMW_BUS_OPTION(1), - .F_OPT_DISCONTINUOUS(1) - // }}} - ) f_wbb( - // {{{ - i_clk, f_reset, - i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, i_b_sel, - o_b_ack, o_b_stall, 32'h0, o_b_err, - f_b_nreqs, f_b_nacks, f_b_outstanding - // }}} - ); - - // Induction, relate number of requests and acks to r_a_owner - // {{{ - always @(posedge i_clk) - if (r_a_owner) - begin - assert(f_b_nreqs == 0); - assert(f_b_nacks == 0); - assert(f_a_outstanding == f_outstanding); - end else begin - assert(f_a_nreqs == 0); - assert(f_a_nacks == 0); - assert(f_b_outstanding == f_outstanding); - end - // }}} - - always @(posedge i_clk) - if ((r_a_owner)&&(i_b_cyc)) - assume(i_b_stb); - - always @(posedge i_clk) - if ((r_a_owner)&&(i_a_cyc)) - assume(i_a_stb); -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/wbwatchdog.v b/delete_later/rtl/cpu/wbwatchdog.v deleted file mode 100644 index b82f875..0000000 --- a/delete_later/rtl/cpu/wbwatchdog.v +++ /dev/null @@ -1,145 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbwatchdog.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A Zip timer, redesigned to be a bus watchdog -// -// This is basically a timer, but there are some unique features to it. -// -// 1. There is no way to "write" the timeout to this watchdog. It is -// fixed with an input (that is assumed to be constant) -// 2. The counter returns to i_timer and the interrupt is cleared on any -// reset. -// 3. Between resets, the counter counts down to zero. Once (and if) it -// hits zero, it will remain at zero until reset. -// 4. Any time the counter is at zero, and until the reset that resets -// the counter, the output interrupt will be set. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbwatchdog #( - parameter BW = 32 - ) ( - // {{{ - input wire i_clk, i_reset, - // Inputs (these were at one time wishbone controlled ...) - input wire [(BW-1):0] i_timeout, - // Interrupt line - output reg o_int - // }}} - ); - - reg [(BW-1):0] r_value; - - // r_value - // {{{ - initial r_value = {(BW){1'b1}}; - always @(posedge i_clk) - if (i_reset) - r_value <= i_timeout[(BW-1):0]; - else if (!o_int) - r_value <= r_value + {(BW){1'b1}}; // r_value - 1; - // }}} - - // Set the interrupt on our last tick. - // {{{ - initial o_int = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_int <= 1'b0; - else if (!o_int) - o_int <= (r_value == { {(BW-1){1'b0}}, 1'b1 }); - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - //////////////////////////////////////////////////////////////////////// - // - // Assumptions about our inputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - assume(i_timeout > 1); - - always @(posedge i_clk) - if (f_past_valid) - assume(i_timeout == $past(i_timeout)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about our internal state and our outputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_int))&&(!$past(i_reset))) - assert(o_int); - - always @(*) - assert(o_int == (r_value == 0)); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!$past(o_int))) - begin - assert(r_value == $past(r_value)-1'b1); - end - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))) - begin - if (!f_past_valid) - begin - assert(r_value == {(BW){1'b1}}); - end else // if ($past(i_reset)) - assert(r_value == $past(i_timeout)); - assert(!o_int); - end - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipbones.v b/delete_later/rtl/cpu/zipbones.v deleted file mode 100644 index d5024c2..0000000 --- a/delete_later/rtl/cpu/zipbones.v +++ /dev/null @@ -1,681 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipbones.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: In the spirit of keeping the Zip CPU small, this implements a -// Zip System with no peripherals: Any peripherals you wish will -// need to be implemented off-module. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipbones #( - // {{{ - parameter RESET_ADDRESS=32'h1000_0000, - ADDRESS_WIDTH=32, - parameter BUS_WIDTH=32, // Bus data width - // CPU options - // {{{ - parameter [0:0] OPT_PIPELINED=1, - parameter [0:0] OPT_EARLY_BRANCHING=OPT_PIPELINED, - // OPT_LGICACHE - // {{{ - parameter OPT_LGICACHE = 2, - // }}} - // OPT_LGDCACHE - // {{{ - // Set to zero for no data cache - parameter OPT_LGDCACHE = 0, - // }}} - parameter [0:0] START_HALTED=1, - parameter [0:0] OPT_DISTRIBUTED_REGS=1, - // OPT_MPY - // {{{ - parameter OPT_MPY = 3, - // }}} - // OPT_DIV - // {{{ - parameter [0:0] OPT_DIV=1, - // }}} - // OPT_SHIFTS - // {{{ - parameter [0:0] OPT_SHIFTS = 1, - // }}} - // OPT_FPU - // {{{ - parameter [0:0] OPT_FPU = 0, - // }}} - parameter [0:0] OPT_CIS=1, - parameter [0:0] OPT_LOCK=1, - parameter [0:0] OPT_USERMODE=1, - parameter [0:0] OPT_DBGPORT=START_HALTED, - parameter [0:0] OPT_TRACE_PORT=1, - parameter [0:0] OPT_PROFILER=0, - parameter [0:0] OPT_LOWPOWER=0, -`ifdef VERILATOR - parameter [0:0] OPT_SIM=1'b1, - parameter [0:0] OPT_CLKGATE = OPT_LOWPOWER, -`else - parameter [0:0] OPT_SIM=1'b0, - parameter [0:0] OPT_CLKGATE = 1'b0, -`endif - // }}} - parameter RESET_DURATION = 10, - // Short-cut names - // {{{ - // localparam AW=ADDRESS_WIDTH, - localparam DBG_WIDTH=32, // Debug bus data width - localparam // Derived parameters - // PHYSICAL_ADDRESS_WIDTH=ADDRESS_WIDTH, - PAW=ADDRESS_WIDTH-$clog2(BUS_WIDTH/8) -`ifdef OPT_MMU - // VIRTUAL_ADDRESS_WIDTH=30, -`else - // VIRTUAL_ADDRESS_WIDTH=PAW, -`endif - // LGTLBSZ = 6, - // VAW=VIRTUAL_ADDRESS_WIDTH, - - // }}} - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Wishbone master interface from the CPU - // {{{ - output wire o_wb_cyc, o_wb_stb, o_wb_we, - output wire [PAW-1:0] o_wb_addr, - output wire [BUS_WIDTH-1:0] o_wb_data, - output wire [BUS_WIDTH/8-1:0] o_wb_sel, - input wire i_wb_stall, i_wb_ack, - input wire [BUS_WIDTH-1:0] i_wb_data, - input wire i_wb_err, - // }}} - // Incoming interrupts - input wire i_ext_int, - // Our one outgoing interrupt - output wire o_ext_int, - // Wishbone slave interface for debugging purposes - // {{{ - input wire i_dbg_cyc, i_dbg_stb, i_dbg_we, - input wire [5:0] i_dbg_addr, - input wire [DBG_WIDTH-1:0] i_dbg_data, - input wire [DBG_WIDTH/8-1:0] i_dbg_sel, - output wire o_dbg_stall, - output wire o_dbg_ack, - output wire [DBG_WIDTH-1:0] o_dbg_data, - // }}} - output wire [31:0] o_cpu_debug, - // - output wire o_prof_stb, - output wire [ADDRESS_WIDTH-1:0] o_prof_addr, - output wire [31:0] o_prof_ticks - // }}} - ); - - // Declarations - // {{{ - localparam [0:0] DBG_ADDR_CTRL = 1'b0, - DBG_ADDR_CPU = 1'b1; - - // Debug bit allocations - // {{{ - // DBGCTRL - // 5 DBG Catch -- Catch exceptions/fautls w/ debugger - // 4 Clear cache - // 3 RESET_FLAG - // 2 STEP (W=1 steps, and returns to halted) - // 1 HALT(ED) - // 0 HALT - // DBGDATA - // read/writes internal registers - // - localparam HALT_BIT = 0, - STEP_BIT = 2, - RESET_BIT = 3, - CLEAR_CACHE_BIT = 4, - CATCH_BIT = 5; - // }}} - - wire cpu_clken; - wire dbg_cyc, dbg_stb, dbg_we, dbg_stall; - wire [5:0] dbg_addr; - wire [DBG_WIDTH-1:0] dbg_idata; - wire [DBG_WIDTH/8-1:0] dbg_sel; - reg [DBG_WIDTH-1:0] dbg_odata; - reg dbg_ack; - wire cpu_break, dbg_cmd_write, - dbg_cpu_write, dbg_cpu_read; - wire reset_hold, halt_on_fault, dbg_catch; - wire reset_request, release_request, halt_request, - step_request, clear_cache_request; - reg cmd_reset, cmd_halt, cmd_step, cmd_clear_cache, - cmd_write, cmd_read; - reg [2:0] cmd_read_ack; - - reg [4:0] cmd_waddr; - reg [DBG_WIDTH-1:0] cmd_wdata; - wire [2:0] cpu_dbg_cc; - - wire cpu_reset, cpu_halt, cpu_dbg_stall, - cpu_has_halted; - wire cpu_lcl_cyc, cpu_lcl_stb, - cpu_op_stall, cpu_pf_stall, cpu_i_count; - wire [DBG_WIDTH-1:0] cpu_dbg_data; - wire [DBG_WIDTH-1:0] cpu_status; - - wire [DBG_WIDTH-1:0] dbg_cmd_data; - wire [DBG_WIDTH/8-1:0] dbg_cmd_strb; - reg dbg_pre_ack; - reg [DBG_WIDTH-1:0] dbg_cpu_status; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Debug bus signal renaming - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign dbg_cyc = i_dbg_cyc; - assign dbg_stb = i_dbg_stb; - assign dbg_we = i_dbg_we; - assign dbg_addr = i_dbg_addr; - assign dbg_idata = i_dbg_data; - assign dbg_sel = i_dbg_sel; - assign o_dbg_ack = dbg_ack; - assign o_dbg_stall = dbg_stall; - assign o_dbg_data = dbg_odata; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The external debug interface - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign dbg_cpu_write = OPT_DBGPORT && (dbg_stb && !dbg_stall && dbg_we) - && (dbg_addr[5] == DBG_ADDR_CPU) - && dbg_sel == 4'hf; - assign dbg_cpu_read = (dbg_stb && !dbg_stall && !dbg_we - && dbg_addr[5] == DBG_ADDR_CPU); - assign dbg_cmd_write = (dbg_stb && !dbg_stall && dbg_we) - &&(dbg_addr[5] == DBG_ADDR_CTRL); - assign dbg_cmd_data = dbg_idata; - assign dbg_cmd_strb = dbg_sel; - - - assign reset_request = dbg_cmd_write && dbg_cmd_strb[RESET_BIT/8] - && dbg_cmd_data[RESET_BIT]; - assign release_request = dbg_cmd_write && dbg_cmd_strb[HALT_BIT/8] - && !dbg_cmd_data[HALT_BIT]; - assign halt_request = dbg_cmd_write && dbg_cmd_strb[HALT_BIT/8] - && dbg_cmd_data[HALT_BIT]; - assign step_request = dbg_cmd_write && dbg_cmd_strb[STEP_BIT/8] - && dbg_cmd_data[STEP_BIT]; - assign clear_cache_request = dbg_cmd_write - && dbg_cmd_strb[CLEAR_CACHE_BIT/8] - && dbg_cmd_data[CLEAR_CACHE_BIT]; - - // - // reset_hold: Always start us off with an initial reset - // {{{ - generate if (RESET_DURATION > 0) - begin : INITIAL_RESET_HOLD - // {{{ - reg [$clog2(RESET_DURATION)-1:0] reset_counter; - reg r_reset_hold; - - initial reset_counter = RESET_DURATION; - always @(posedge i_clk) - if (i_reset) - reset_counter <= RESET_DURATION; - else if (reset_counter > 0) - reset_counter <= reset_counter - 1; - - initial r_reset_hold = 1; - always @(posedge i_clk) - if (i_reset) - r_reset_hold <= 1; - else - r_reset_hold <= (reset_counter > 1); - - assign reset_hold = r_reset_hold; -`ifdef FORMAL - always @(*) - assert(reset_hold == (reset_counter != 0)); -`endif - // }}} - end else begin : NO_RESET_HOLD - - assign reset_hold = 0; - - end endgenerate - // }}} - - assign halt_on_fault = dbg_catch; - - // cmd_reset - // {{{ - // Always start us off with an initial reset - initial cmd_reset = 1'b1; - always @(posedge i_clk) - if (i_reset) - cmd_reset <= 1'b1; - else if (reset_hold) - cmd_reset <= 1'b1; - else if (cpu_break && !halt_on_fault) - cmd_reset <= 1'b1; - else - cmd_reset <= reset_request; - // }}} - - // cmd_halt - // {{{ - initial cmd_halt = START_HALTED; - always @(posedge i_clk) - if (i_reset) - cmd_halt <= START_HALTED; - else if (cmd_reset && START_HALTED) - cmd_halt <= START_HALTED; - else begin - // {{{ - // When shall we release from a halt? Only if we have - // come to a full and complete stop. Even then, we only - // release if we aren't being given a command to step the CPU. - // - if (!cmd_write && cpu_has_halted && dbg_cmd_write - && (release_request || step_request)) - cmd_halt <= 1'b0; - - // Reasons to halt - - // 1. Halt on any unhandled CPU exception. The cause of the - // exception must be cured before we can (re)start. - // If the CPU is configured to start immediately on power - // up, we leave it to reset on any exception instead. - if (cpu_break && halt_on_fault) - cmd_halt <= 1'b1; - - // 2. Halt on any user request to halt. (Only valid if the - // STEP bit isn't also set) - if (dbg_cmd_write && halt_request && !step_request) - cmd_halt <= 1'b1; - - // 3. Halt on any user request to write to a CPU register - if (dbg_cpu_write) - cmd_halt <= 1'b1; - - // 4. Halt following any step command - if (cmd_step && !step_request) - cmd_halt <= 1'b1; - - // 5. Halt following any clear cache - if (cmd_clear_cache) - cmd_halt <= 1'b1; - - // 6. Halt on any clear cache bit--independent of any step bit - if (clear_cache_request) - cmd_halt <= 1'b1; - // }}} - end - // }}} - - // cmd_clear_cache - // {{{ - initial cmd_clear_cache = 1'b0; - always @(posedge i_clk) - if (i_reset || cpu_reset) - cmd_clear_cache <= 1'b0; - else if (dbg_cmd_write && clear_cache_request && halt_request) - cmd_clear_cache <= 1'b1; - else if (cmd_halt && !cpu_dbg_stall) - cmd_clear_cache <= 1'b0; - // }}} - - // cmd_step - // {{{ - initial cmd_step = 1'b0; - always @(posedge i_clk) - if (i_reset) - cmd_step <= 1'b0; - else if (cmd_reset || cpu_break - || reset_request - || clear_cache_request || cmd_clear_cache - || halt_request || dbg_cpu_write) - cmd_step <= 1'b0; - else if (!cmd_write && cpu_has_halted && step_request) - cmd_step <= 1'b1; - else // if (cpu_dbg_stall) - cmd_step <= 1'b0; -`ifdef FORMAL - // While STEP is true, we can't halt - always @(*) - if (!i_reset && cmd_step) - assert(!cmd_halt); -`endif - // }}} - - // dbg_catch - // {{{ - generate if (!OPT_DBGPORT) - begin : NO_DBG_CATCH - assign dbg_catch = START_HALTED; - end else begin : GEN_DBG_CATCH - reg r_dbg_catch; - - initial r_dbg_catch = START_HALTED; - always @(posedge i_clk) - if (i_reset) - r_dbg_catch <= START_HALTED; - else if (dbg_cmd_write && dbg_cmd_strb[CATCH_BIT/8]) - r_dbg_catch <= dbg_cmd_data[CATCH_BIT]; - - assign dbg_catch = r_dbg_catch; - end endgenerate - // }}} - - assign cpu_reset = (cmd_reset); - assign cpu_halt = (cmd_halt); - - // cpu_status - // {{{ - // 0xffff_f000 -> (Unused / reserved) - // - // 0x0000_0800 -> cpu_break - // 0x0000_0400 -> Interrupt pending - // 0x0000_0200 -> User mode - // 0x0000_0100 -> Sleep (CPU is sleeping) - // - // 0x0000_00c0 -> (Unused/reserved) - // 0x0000_0020 -> dbg_catch - // 0x0000_0010 -> cmd_clear_cache - // - // 0x0000_0008 -> Reset - // 0x0000_0004 -> Step (auto clearing, write only) - // 0x0000_0002 -> Halt (status) - // 0x0000_0001 -> Halt (request) - assign cpu_status = { 16'h0, 4'h0, - cpu_break, i_ext_int, cpu_dbg_cc[1:0], - 2'h0, dbg_catch, 1'b0, - cmd_reset, 1'b0, !cpu_dbg_stall, cmd_halt - }; - - // }}} - - // cmd_write - // {{{ - initial cmd_write = 0; - always @(posedge i_clk) - if (i_reset || cpu_reset) - cmd_write <= 1'b0; - else if (!cmd_write || cpu_has_halted) - cmd_write <= dbg_cpu_write; - // }}} - - // cmd_read - // {{{ - initial cmd_read = 0; - always @(posedge i_clk) - if (i_reset || !dbg_cyc || !OPT_DBGPORT) - cmd_read <= 1'b0; - else if (dbg_cpu_read) - cmd_read <= 1'b1; - else if (cmd_read_ack == 1) - cmd_read <= 1'b0; - - initial cmd_read_ack = 0; - always @(posedge i_clk) - if (i_reset || !dbg_cyc || !OPT_DBGPORT) - cmd_read_ack <= 0; - else if (dbg_cpu_read) - cmd_read_ack <= 2 + (OPT_DISTRIBUTED_REGS ? 0:1); - else if (cmd_read_ack > 0) - cmd_read_ack <= cmd_read_ack - 1; - // }}} - - // cmd_waddr, cmd_wdata - // {{{ - always @(posedge i_clk) - if ((!cmd_write || cpu_has_halted) && dbg_cpu_write) - begin - cmd_waddr <= dbg_addr[4:0]; - cmd_wdata <= dbg_idata; - end - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The CPU itself - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign cpu_clken = cmd_write || cmd_read || dbg_cyc; -`ifdef FORMAL - // {{{ - (* anyseq *) reg f_cpu_halted, f_cpu_data, f_cpu_stall, - f_cpu_break; - (* anyseq *) reg [2:0] f_cpu_dbg_cc; - (* anyseq *) reg [31:0] f_cpu_dbg_data; - - assign cpu_dbg_stall = f_cpu_stall && !f_cpu_halted; - assign cpu_break = f_cpu_break; - assign cpu_dbg_cc = f_cpu_dbg_cc; - assign cpu_dbg_data = f_cpu_dbg_data; - assign cpu_has_halted= f_cpu_halted; - - fdebug #( - // {{{ - .OPT_START_HALTED(START_HALTED), - .OPT_DISTRIBUTED_RAM(OPT_DISTRIBUTED_REGS) - // }}} - ) fdbg ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - .i_cpu_reset(cpu_reset), - .i_halt(cpu_halt), - .i_halted(f_cpu_halted), - .i_clear_cache(cmd_clear_cache), - .i_dbg_we(cmd_write), - .i_dbg_reg(cmd_waddr), - .i_dbg_data(cmd_wdata), - .i_dbg_stall(cpu_dbg_stall), - .i_dbg_break(cpu_break), - .i_dbg_cc(cpu_dbg_cc) - // }}} - ); - // }}} -`else - zipwb #( - // {{{ - .RESET_ADDRESS(RESET_ADDRESS), - .ADDRESS_WIDTH(ADDRESS_WIDTH-$clog2(BUS_WIDTH/8)), - .BUS_WIDTH(BUS_WIDTH), - .OPT_PIPELINED(OPT_PIPELINED), - .OPT_EARLY_BRANCHING(OPT_EARLY_BRANCHING), - .OPT_LGICACHE(OPT_LGICACHE), - .OPT_LGDCACHE(OPT_LGDCACHE), - .OPT_MPY(OPT_MPY), - .OPT_DIV(OPT_DIV), - .OPT_SHIFTS(OPT_SHIFTS), - .IMPLEMENT_FPU(OPT_FPU), - .OPT_CIS(OPT_CIS), - .OPT_LOCK(OPT_LOCK), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_START_HALTED(START_HALTED), - .OPT_SIM(OPT_SIM), - .OPT_DBGPORT(OPT_DBGPORT), - .OPT_TRACE_PORT(OPT_TRACE_PORT), - .OPT_PROFILER(OPT_PROFILER), - .OPT_CLKGATE(OPT_CLKGATE), - .OPT_DISTRIBUTED_REGS(OPT_DISTRIBUTED_REGS), - .OPT_USERMODE(OPT_USERMODE), - .WITH_LOCAL_BUS(0) - // }}} - ) thecpu( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), .i_interrupt(i_ext_int), - .i_cpu_clken(cpu_clken), - // Debug interface - // {{{ - .i_halt(cpu_halt), .i_clear_cache(cmd_clear_cache), - .i_dbg_wreg(cmd_waddr), .i_dbg_we(cmd_write), - .i_dbg_data(cmd_wdata), - .i_dbg_rreg(dbg_addr[4:0]), - .o_dbg_stall(cpu_dbg_stall), - .o_halted(cpu_has_halted), - .o_dbg_reg(cpu_dbg_data), - .o_dbg_cc(cpu_dbg_cc), - .o_break(cpu_break), - // }}} - // Wishbone bus interface - // {{{ - .o_wb_gbl_cyc(o_wb_cyc), .o_wb_gbl_stb(o_wb_stb), - .o_wb_lcl_cyc(cpu_lcl_cyc), - .o_wb_lcl_stb(cpu_lcl_stb), - .o_wb_we(o_wb_we), .o_wb_addr(o_wb_addr), - .o_wb_data(o_wb_data), .o_wb_sel(o_wb_sel), - // Return values from the Wishbone bus - .i_wb_stall(i_wb_stall), .i_wb_ack(i_wb_ack), - .i_wb_data(i_wb_data), - .i_wb_err((i_wb_err)||(cpu_lcl_cyc)), - // }}} - .o_op_stall(cpu_op_stall), .o_pf_stall(cpu_pf_stall), - .o_i_count(cpu_i_count), - .o_debug(o_cpu_debug), - // - .o_prof_stb(o_prof_stb), - .o_prof_addr(o_prof_addr), - .o_prof_ticks(o_prof_ticks) - // }}} - ); -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Return debug response values - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // always @(posedge i_clk) - // dbg_pre_addr <= dbg_addr[5]; - - always @(posedge i_clk) - dbg_cpu_status <= cpu_status; - - initial dbg_pre_ack = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_dbg_cyc) - dbg_pre_ack <= 1'b0; - else - dbg_pre_ack <= dbg_stb && !dbg_stall && !dbg_cpu_read; - - initial dbg_ack = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_dbg_cyc) - dbg_ack <= 1'b0; - else - dbg_ack <= dbg_pre_ack || (cmd_read_ack == 1); - - always @(posedge i_clk) - if (!OPT_LOWPOWER || dbg_pre_ack || cmd_read) - begin - if (cmd_read) - dbg_odata <= cpu_dbg_data; - else - dbg_odata <= dbg_cpu_status; - end - - assign dbg_stall = cmd_read || (cmd_write && cpu_dbg_stall - && dbg_addr[5] == DBG_ADDR_CPU); - // }}} - - assign o_ext_int = (cmd_halt) && (!i_wb_stall); - - // Make Verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, dbg_cyc, cpu_lcl_stb, cpu_op_stall, - cpu_dbg_cc[2], cpu_pf_stall, cpu_i_count }; - // verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH = 3; - - reg [F_LGDEPTH-1:0] fwb_nreqs, fwb_nacks, fwb_outstanding; - wire cpu_dbg_we; - - assign cpu_dbg_we = (dbg_stb && !dbg_stall && dbg_we - &&(dbg_addr[5] == DBG_ADDR_CPU)); - - fwb_slave #( - .AW(6), .DW(DBG_WIDTH), .F_LGDEPTH(F_LGDEPTH) - ) fwb( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(i_dbg_cyc), .i_wb_stb(i_dbg_stb && !o_dbg_stall), - .i_wb_we(i_dbg_we), .i_wb_addr(i_dbg_addr), - .i_wb_data(i_dbg_data), - .i_wb_ack(o_dbg_ack), .i_wb_stall(o_dbg_stall), - .i_wb_idata(o_dbg_data), .i_wb_err(1'b0), - .f_nreqs(fwb_nreqs), .f_nacks(fwb_nacks), - .f_outstanding(fwb_outstanding) - // }}} - ); - - always @(*) - if (i_dbg_cyc) - begin - if (cmd_read_ack > 0) - begin - assert(!dbg_pre_ack); - assert(fwb_outstanding == 1 + (o_dbg_ack ? 1:0)); - end else - assert(fwb_outstanding == dbg_pre_ack + o_dbg_ack); - end - - always @(posedge i_clk) - if ($past(i_dbg_cyc && cpu_dbg_we)) - assume(i_dbg_cyc); -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipcore.v b/delete_later/rtl/cpu/zipcore.v deleted file mode 100644 index 1d93ed7..0000000 --- a/delete_later/rtl/cpu/zipcore.v +++ /dev/null @@ -1,6118 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipcore.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipcore #( - // {{{ - parameter ADDRESS_WIDTH=30, // 32-b word addr width - parameter [31:0] RESET_ADDRESS=32'h010_0000, - parameter OPT_MPY = 0, - parameter [0:0] OPT_SHIFTS = 1, - parameter [0:0] OPT_DIV = 1, - parameter [0:0] IMPLEMENT_FPU = 0, - parameter [0:0] OPT_EARLY_BRANCHING = 1, - parameter [0:0] OPT_CIS = 1'b1, - parameter [0:0] OPT_SIM = 1'b0, - parameter [0:0] OPT_DISTRIBUTED_REGS = 1'b1, - parameter [0:0] OPT_PIPELINED = 1'b1, - parameter [0:0] OPT_PIPELINED_BUS_ACCESS = (OPT_PIPELINED), - parameter [0:0] OPT_LOCK=1, - parameter [0:0] OPT_DCACHE = 1, - parameter [0:0] OPT_USERMODE = 1'b1, - parameter [0:0] OPT_LOWPOWER = 1'b0, - parameter [0:0] OPT_CLKGATE = 1'b1, - parameter [0:0] OPT_START_HALTED = 1'b1, - parameter [0:0] OPT_DBGPORT = 1'b1, - parameter [0:0] OPT_TRACE_PORT = 1'b0, - parameter [0:0] OPT_PROFILER = 1'b0, - - localparam AW=ADDRESS_WIDTH -`ifdef FORMAL - , parameter F_LGDEPTH=4 -`endif - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, i_interrupt, - output wire o_clken, - // Debug interface - // {{{ - input wire i_halt, i_clear_cache, - input wire [4:0] i_dbg_wreg, - input wire i_dbg_we, - input wire [31:0] i_dbg_data, - input wire [4:0] i_dbg_rreg, - // - output wire o_dbg_stall, - output wire [31:0] o_dbg_reg, - output reg [2:0] o_dbg_cc, - output wire o_break, - // }}} - // Instruction fetch interface - // {{{ - output wire o_pf_new_pc, - output wire o_clear_icache, - output wire o_pf_ready, - output wire [(AW+1):0] o_pf_request_address, - input wire i_pf_valid, i_pf_illegal, - input wire [31:0] i_pf_instruction, - input wire [(AW+1):0] i_pf_instruction_pc, - // }}} - // Memory unit interface - // {{{ - output wire o_clear_dcache, - output wire o_mem_ce, - output wire o_bus_lock, - output wire [2:0] o_mem_op, - output wire [31:0] o_mem_addr, - output wire [31:0] o_mem_data, - output wire [AW+1:0] o_mem_lock_pc, - output wire [4:0] o_mem_reg, - input wire i_mem_busy, i_mem_rdbusy, - i_mem_pipe_stalled, i_mem_valid, - input wire i_bus_err, - input wire [4:0] i_mem_wreg, - input wire [31:0] i_mem_result, - // }}} - // Accounting outputs ... to help us count stalls and usage - // {{{ - output wire o_op_stall, - output wire o_pf_stall, - output wire o_i_count, - // }}} - // Debug data for on-line/live tracing - // {{{ - output wire [31:0] o_debug, - //}}} - // (Optional) Profiler data - // {{{ - output wire o_prof_stb, - output wire [AW+1:0] o_prof_addr, - output wire [31:0] o_prof_ticks - // }}} - // }}} - ); - - // Local parameter definitions - // {{{ - // Verilator lint_off UNUSED - localparam [0:0] OPT_MEMPIPE = OPT_PIPELINED_BUS_ACCESS; - localparam [(AW-1):0] RESET_BUS_ADDRESS = RESET_ADDRESS[AW+1:2]; - localparam [3:0] CPU_CC_REG = 4'he, - CPU_PC_REG = 4'hf; - localparam [3:0] CPU_SUB_OP = 4'h0,// also a compare instruction - CPU_AND_OP = 4'h1,// also a test instruction - CPU_BREV_OP= 4'h8, - CPU_MOV_OP = 4'hd; - localparam CPU_CLRDCACHE_BIT=15, // Set to clr D-cache,auto clears - CPU_CLRICACHE_BIT=14, // Set to clr I-cache,auto clears - CPU_PHASE_BIT = 13, // Set on last half of a CIS - CPU_FPUERR_BIT = 12, // Set on floating point error - CPU_DIVERR_BIT = 11, // Set on divide error - CPU_BUSERR_BIT = 10, // Set on bus error - CPU_TRAP_BIT = 9, // User TRAP has taken place - CPU_ILL_BIT = 8, // Illegal instruction - CPU_BREAK_BIT = 7, - CPU_STEP_BIT = 6, // Will step one (or two CIS) ins - CPU_GIE_BIT = 5, - CPU_SLEEP_BIT = 4; - // Verilator lint_on UNUSED - // }}} - - // Register declarations - // {{{ - // The distributed RAM style comment is necessary on the - // SPARTAN6 with XST to prevent XST from oversimplifying the register - // set and in the process ruining everything else. It basically - // optimizes logic away, to where it no longer works. The logic - // as described herein will work, this just makes sure XST implements - // that logic. - // - (* ram_style = "distributed" *) - reg [31:0] regset [0:(OPT_USERMODE)? 31:15]; - - // Condition codes - // (BUS, TRAP,ILL,BREAKEN,STEP,GIE,SLEEP ), V, N, C, Z - reg [3:0] flags, iflags; - wire [15:0] w_uflags, w_iflags; - reg break_en, user_step, sleep, r_halted; - wire break_pending, trap, gie, ubreak, pending_interrupt, - stepped; - wire step; - wire ill_err_u; - reg ill_err_i; - reg ibus_err_flag; - wire ubus_err_flag; - wire idiv_err_flag, udiv_err_flag; - // Verilator coverage_off - wire ifpu_err_flag, ufpu_err_flag; - // Verilator coverage_on - wire ihalt_phase, uhalt_phase; - - // The master chip enable - wire master_ce, master_stall; - // - - // - // PIPELINE STAGE #1 :: Prefetch - // Variable declarations - // - // {{{ - reg [(AW+1):0] pf_pc; - reg new_pc; - wire clear_pipeline; - - reg dcd_stalled; - // wire pf_cyc, pf_stb, pf_we, pf_stall, pf_ack, pf_err; - // wire [(AW-1):0] pf_addr; - // wire pf_valid, pf_gie, pf_illegal; - wire pf_gie; -`ifdef FORMAL - wire [31:0] f_dcd_insn_word; - wire f_dcd_insn_gie; - wire f_dcd_insn_is_pipeable; - reg [31:0] f_op_insn_word; - reg [31:0] f_alu_insn_word; -`endif - - assign clear_pipeline = new_pc; - // }}} - - // - // PIPELINE STAGE #2 :: Instruction Decode - // Variable declarations - // - // - // {{{ - wire [3:0] dcd_opn; - wire dcd_ce, dcd_phase; - wire [4:0] dcd_A, dcd_B, dcd_R, dcd_preA, dcd_preB; - wire dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc; - wire [3:0] dcd_F; - wire dcd_wR, dcd_rA, dcd_rB, - dcd_ALU, dcd_M, dcd_DIV, dcd_FP, - dcd_wF, dcd_gie, dcd_break, dcd_lock, - dcd_pipe, dcd_ljmp; - wire dcd_valid; - wire [AW+1:0] dcd_pc /* verilator public_flat */; - wire [31:0] dcd_I; - wire dcd_zI; // true if dcd_I == 0 - wire dcd_A_stall, dcd_B_stall, dcd_F_stall; - - wire dcd_illegal; - wire dcd_early_branch, dcd_early_branch_stb; - wire [(AW+1):0] dcd_branch_pc; - - wire dcd_sim; - wire [22:0] dcd_sim_immv; - wire prelock_stall, last_lock_insn; - wire cc_invalid_for_dcd; - wire pending_sreg_write; - // }}} - - - // - // - // PIPELINE STAGE #3 :: Read Operands - // Variable declarations - // - // - // - // {{{ - // Now, let's read our operands - reg op_valid /* verilator public_flat */, - op_valid_mem, op_valid_alu; - reg op_valid_div, op_valid_fpu; - wire op_stall; - wire [3:0] op_opn; - wire [4:0] op_R; - reg op_Rcc; - wire [4:0] op_Aid, op_Bid; - wire op_rA, op_rB; - reg [31:0] r_op_Av, r_op_Bv; - wire [AW+1:0] op_pc; - wire [31:0] w_op_Av, w_op_Bv, op_Av, op_Bv; - reg [31:0] w_pcB_v, w_pcA_v; - reg [31:0] w_op_BnI; - wire op_wR; - reg op_wF; - wire op_gie; - wire [3:0] op_Fl; - reg [6:0] r_op_F; - wire [7:0] op_F; - wire op_ce, op_phase, op_pipe; - reg r_op_break; - wire w_op_valid; - wire op_lowpower_clear; - wire [8:0] w_cpu_info; - // Some pipeline control wires - reg op_illegal; - wire op_break; - wire op_lock; - - wire op_sim /* verilator public_flat */; - wire [22:0] op_sim_immv /* verilator public_flat */; - wire alu_sim /* verilator public_flat */; - wire [22:0] alu_sim_immv /* verilator public_flat */; - // }}} - - - // - // - // PIPELINE STAGE #4 :: ALU / Memory - // Variable declarations - // - // - // {{{ - wire [(AW+1):0] alu_pc; - reg [4:0] alu_reg; - reg r_alu_pc_valid, mem_pc_valid; - wire alu_pc_valid; - wire alu_phase; - wire alu_ce /* verilator public_flat */, alu_stall; - wire [31:0] alu_result; - wire [3:0] alu_flags; - wire alu_valid, alu_busy; - wire set_cond; - reg alu_wR, alu_wF; - wire alu_gie, alu_illegal; - - - wire mem_ce, mem_stalled; - - wire div_ce, div_error, div_busy, div_valid; - wire [31:0] div_result; - wire [3:0] div_flags; - - // Verilator coverage_off - wire fpu_ce, fpu_error, fpu_busy, fpu_valid; - wire [31:0] fpu_result; - wire [3:0] fpu_flags; - // Verilator coverage_on - reg adf_ce_unconditional; - - - reg dbgv, dbg_clear_pipe; - reg [31:0] dbg_val; - reg [31:0] debug_pc; - reg r_dbg_stall; - - assign div_ce = (op_valid_div)&&(adf_ce_unconditional)&&(set_cond); - assign fpu_ce = (IMPLEMENT_FPU)&&(op_valid_fpu)&&(adf_ce_unconditional)&&(set_cond); - - // }}} - - // - // - // PIPELINE STAGE #5 :: Write-back - // Variable declarations - // - // {{{ - wire wr_write_pc, wr_write_cc, - wr_write_scc, wr_write_ucc; - reg wr_reg_ce, wr_flags_ce; - reg [3:0] wr_flags; - reg [2:0] wr_index; - wire [4:0] wr_reg_id; - reg [31:0] wr_gpreg_vl, wr_spreg_vl; - wire w_switch_to_interrupt, w_release_from_interrupt; - reg [(AW+1):0] ipc; - wire [(AW+1):0] upc; - reg last_write_to_cc; - wire cc_write_hold; - reg r_clear_icache; - - reg pfpcset; - reg [2:0] pfpcsrc; - - wire w_clken; - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // MASTER: clock enable. - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign master_ce = (!i_halt || alu_phase) - &&(!cc_write_hold)&&(!o_break)&&(!sleep); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Calculate stall conditions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // PIPELINE STAGE #1 :: Prefetch - // These are calculated externally, within the prefetch module. - // - // PIPELINE STAGE #2 :: Instruction Decode - // {{{ - always @(*) - if (OPT_PIPELINED) - dcd_stalled = (dcd_valid && op_stall); - else - dcd_stalled = (!master_ce) - // Can't step forward when we need to be halted - ||(ill_err_i)||(ibus_err_flag)||(idiv_err_flag) - ||((dcd_valid || op_valid) && !dcd_early_branch) - ||(alu_busy)||(div_busy)||(fpu_busy)||(i_mem_busy); - // }}} - // - // PIPELINE STAGE #3 :: Read Operands - // {{{ - generate if (OPT_PIPELINED) - begin : GEN_OP_STALL - reg r_cc_invalid_for_dcd; - reg r_pending_sreg_write; - - // cc_invalid_for_dcd - // {{{ - initial r_cc_invalid_for_dcd = 1'b0; - always @(posedge i_clk) - if (clear_pipeline) - r_cc_invalid_for_dcd <= 1'b0; - else if ((alu_ce || mem_ce)&&(set_cond)&&(op_valid) &&((op_wF) - ||((op_wR)&&(op_R[4:0] == { op_gie, CPU_CC_REG })))) - // If an instruction in the pipeline will write to the - // CC register, then we can't be allowed to release - // any instruction depending upon the CC register - // (for other than conditional execution) into the - // pipeline. - r_cc_invalid_for_dcd <= 1'b1; - else if (r_cc_invalid_for_dcd) - // While the pipeline is busy, keep r_cc_invalid_for_dcd - // high. - r_cc_invalid_for_dcd <= ((alu_busy)||(i_mem_rdbusy)||(div_busy)||(fpu_busy)); - else - r_cc_invalid_for_dcd <= 1'b0; - - assign cc_invalid_for_dcd = r_cc_invalid_for_dcd; - // }}} - - // pending_sreg_write - // {{{ - // Used to determine if we need to stall for flags to be ready - initial r_pending_sreg_write = 1'b0; - always @(posedge i_clk) - if (clear_pipeline) - r_pending_sreg_write <= 1'b0; - else if (((adf_ce_unconditional)||(mem_ce)) - &&(set_cond)&&(!op_illegal) - &&(op_wR) - &&(op_R[3:1] == 3'h7) - &&(op_R[4:0] != { gie, 4'hf })) - r_pending_sreg_write <= 1'b1; - else if ((!i_mem_rdbusy)&&(!alu_busy)) - r_pending_sreg_write <= 1'b0; - - assign pending_sreg_write = r_pending_sreg_write; - // }}} - - assign op_stall = (op_valid)&&( - // {{{ - // Only stall if we're loaded w/valid insns and the - // next stage is accepting our instruction - (!adf_ce_unconditional)&&(!mem_ce) - ) - ||(dcd_valid)&&( - // If we are halted, then accepting anything - // into the Op stage might accept a register - // that then gets modified by the debugging - // interface so as to be invalid. - i_halt - // Stall if we need to wait for an operand A - // to be ready to read - || (dcd_A_stall) - // Likewise for B, also includes logic - // regarding immediate offset (register must - // be in register file if we need to add to - // an immediate) - ||(dcd_B_stall) - // Or if we need to wait on flags to work on the - // CC register - ||(dcd_F_stall) - ); - // }}} - assign op_ce = ((dcd_valid)||(dcd_illegal)||(dcd_early_branch))&&(!op_stall); - - end else begin : NO_OP_STALLS // !OPT_PIPELINED - // {{{ - assign op_stall = 1'b0; // (o_break)||(pending_interrupt); - assign op_ce = ((dcd_valid)||(dcd_early_branch))&&(!op_stall); - assign pending_sreg_write = 1'b0; - assign cc_invalid_for_dcd = 1'b0; - - // verilator coverage_off - // Verilator lint_off UNUSED - wire pipe_unused; - assign pipe_unused = &{ 1'b0, cc_invalid_for_dcd, - pending_sreg_write }; - // Verilator lint_on UNUSED - // verilator coverage_on - // }}} - end endgenerate - - // BUT ... op_ce is too complex for many of the data operations. So - // let's make their circuit enable code simpler. In particular, if - // op_ doesn't need to be preserved, we can change it all we want - // ... right? The clear_pipeline code, for example, really only needs - // to determine whether op_valid is true. - // assign op_change_data_ce = (!op_stall); - // }}} - // - // PIPELINE STAGE #4 :: ALU / Memory - // {{{ - // 1. Basic stall is if the previous stage is valid and the next is - // busy. - // 2. Also stall if the prior stage is valid and the master clock enable - // is de-selected - // 3. Stall if someone on the other end is writing the CC register, - // since we don't know if it'll put us to sleep or not. - // 4. Last case: Stall if we would otherwise move a break instruction - // through the ALU. Break instructions are not allowed through - // the ALU. - generate if (OPT_PIPELINED) - begin : GEN_ALU_STALL - // alu_stall, alu_ce - // {{{ - assign alu_stall = (((master_stall)||(i_mem_rdbusy))&&(op_valid_alu)) //Case 1&2 - ||(wr_reg_ce)&&(wr_write_cc); - // assign // alu_ce = (master_ce)&&(op_valid_alu)&&(!alu_stall) - // &&(!clear_pipeline)&&(!op_illegal) - // &&(!pending_sreg_write) - // &&(!alu_sreg_stall); - assign alu_ce = (adf_ce_unconditional)&&(op_valid_alu); - - // verilator coverage_off - // Verilator lint_off unused - wire unused_alu_stall = &{ 1'b0, alu_stall }; - // Verilator lint_on unused - // verilator coverage_on - // }}} - end else begin : NO_ALU_STALLS - // alu_stall, alu_ce - // {{{ - assign alu_stall = (master_stall); - //assign alu_ce = (master_ce)&&(op_valid_alu) - // &&(!clear_pipeline) - // &&(!alu_stall); - assign alu_ce = (adf_ce_unconditional)&&(op_valid_alu); - - // verilator coverage_off - // Verilator lint_off unused - wire unused_alu_stall = &{ 1'b0, alu_stall }; - // Verilator lint_on unused - // verilator coverage_on - // }}} - end endgenerate - // - - // mem_ce - // {{{ - // Note: if you change the conditions for mem_ce, you must also change - // alu_pc_valid. - // - assign mem_ce = (master_ce)&&(op_valid_mem)&&(!mem_stalled) - &&(!clear_pipeline); - // }}} - - // mem_stalled - // {{{ - generate if (OPT_PIPELINED_BUS_ACCESS) - begin : GEN_PIPELINE_MEM_STALL - // {{{ - assign mem_stalled = (master_stall)||((op_valid_mem)&&( - (i_mem_pipe_stalled) - ||(i_bus_err)||(div_error) - ||(!op_pipe && i_mem_busy) - // Stall waiting for flags to be valid - // Or waiting for a write to the PC register - // Or CC register, since that can change the - // PC as well - ||((wr_reg_ce) - &&((wr_write_pc)||(wr_write_cc))))); - // }}} - end else if (OPT_PIPELINED) - begin : GEN_MEM_STALL - // {{{ - assign mem_stalled = (master_stall)||((op_valid_mem)&&( - (i_bus_err)||(div_error)||(i_mem_busy) - // Stall waiting for flags to be valid - // Or waiting for a write to the PC register - // Or CC register, since that can change the - // PC as well - ||((wr_reg_ce) - &&((wr_write_pc)||(wr_write_cc))))); - // }}} - end else begin : NO_MEM_STALL - // {{{ - assign mem_stalled = master_stall || i_mem_busy; - // }}} - end endgenerate - // }}} - // }}} - - // - // Master stall condition - // {{{ - assign master_stall = (!master_ce)||(!op_valid)||(ill_err_i) - ||(step && stepped) - ||(ibus_err_flag)||(idiv_err_flag) - ||(pending_interrupt && !o_bus_lock)&&(!alu_phase) - ||(alu_busy)||(div_busy)||(fpu_busy)||(op_break) - ||((OPT_PIPELINED)&&( - prelock_stall - ||((i_mem_busy)&&(op_illegal)) - ||((i_mem_busy)&&(op_valid_div)) - ||(alu_illegal)||(o_break))); - // }}} - // - // (Everything but memory) stall condition - // {{{ - - // ALU, DIV, or FPU CE ... equivalent to the OR of all three of these - always @(*) - if (OPT_PIPELINED) - adf_ce_unconditional = - (!master_stall)&&(!op_valid_mem)&&(!i_mem_rdbusy) - &&(!i_mem_busy || !op_wR - || op_R[4:0] != { gie, CPU_CC_REG }); - else - adf_ce_unconditional = (!master_stall)&&(op_valid)&&(!op_valid_mem); - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // PIPELINE STAGE #1 :: Instruction fetch - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign o_pf_ready = (!dcd_stalled && !dcd_phase); - - assign o_pf_new_pc = (new_pc)||((dcd_early_branch_stb)&&(!clear_pipeline)); - - assign o_pf_request_address = ((dcd_early_branch_stb)&&(!clear_pipeline)) - ? dcd_branch_pc:pf_pc; - assign pf_gie = gie; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // PIPELINE STAGE #2 :: Instruction Decode - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign dcd_ce =((OPT_PIPELINED)&&(!dcd_valid))||(!dcd_stalled); - wire [6:0] dcd_full_R, dcd_full_A, dcd_full_B; - - idecode #( - // {{{ - .ADDRESS_WIDTH(AW), - .OPT_MPY((OPT_MPY!=0)? 1'b1:1'b0), - .OPT_SHIFTS(OPT_SHIFTS), - .OPT_PIPELINED(OPT_PIPELINED), - .OPT_EARLY_BRANCHING(OPT_EARLY_BRANCHING), - .OPT_DIVIDE(OPT_DIV), - .OPT_FPU(IMPLEMENT_FPU), - .OPT_LOCK(OPT_LOCK), - .OPT_OPIPE(OPT_PIPELINED_BUS_ACCESS), - .OPT_USERMODE(OPT_USERMODE), - .OPT_SIM(OPT_SIM), - .OPT_CIS(OPT_CIS), - .OPT_LOWPOWER(OPT_LOWPOWER) - // }}} - ) instruction_decoder( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset||clear_pipeline||o_clear_icache), - .i_ce(dcd_ce), - .i_stalled(dcd_stalled), - .i_instruction(i_pf_instruction), .i_gie(pf_gie), - .i_pc(i_pf_instruction_pc), .i_pf_valid(i_pf_valid), - .i_illegal(i_pf_illegal), - .o_valid(dcd_valid), .o_phase(dcd_phase), - .o_illegal(dcd_illegal), .o_pc(dcd_pc), - .o_dcdR(dcd_full_R), .o_dcdA(dcd_full_A), - .o_dcdB(dcd_full_B), - .o_preA(dcd_preA), .o_preB(dcd_preB), - .o_I(dcd_I), .o_zI(dcd_zI), .o_cond(dcd_F), - .o_wF(dcd_wF), .o_op(dcd_opn), - .o_ALU(dcd_ALU), .o_M(dcd_M), .o_DV(dcd_DIV), - .o_FP(dcd_FP), .o_break(dcd_break), .o_lock(dcd_lock), - .o_wR(dcd_wR), .o_rA(dcd_rA), .o_rB(dcd_rB), - .o_early_branch(dcd_early_branch), - .o_early_branch_stb(dcd_early_branch_stb), - .o_branch_pc(dcd_branch_pc), .o_ljmp(dcd_ljmp), - .o_pipe(dcd_pipe), - .o_sim(dcd_sim), .o_sim_immv(dcd_sim_immv) -`ifdef FORMAL - , .f_insn_word(f_dcd_insn_word), - .f_insn_gie(f_dcd_insn_gie), - .f_insn_is_pipeable(f_dcd_insn_is_pipeable) -`endif - // }}} - ); - - assign { dcd_Rcc, dcd_Rpc, dcd_R } = (!OPT_LOWPOWER || dcd_valid || !OPT_PIPELINED) ? dcd_full_R : 7'h0; - assign { dcd_Acc, dcd_Apc, dcd_A } = (!OPT_LOWPOWER || dcd_valid || !OPT_PIPELINED) ? dcd_full_A : 7'h0; - assign { dcd_Bcc, dcd_Bpc, dcd_B } = (!OPT_LOWPOWER || dcd_valid || !OPT_PIPELINED) ? dcd_full_B : 7'h0; - assign dcd_gie = pf_gie; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // PIPELINE STAGE #3 :: Read Operands (Registers) - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // op_pipe - // {{{ - generate if (OPT_PIPELINED_BUS_ACCESS) - begin : GEN_OP_PIPE // Memory pipelining - reg r_op_pipe; - - // To be a pipeable operation, there must be - // two valid adjacent instructions - // Both must be memory instructions - // Both must be writes, or both must be reads - // Both operations must be to the same identical address, - // or at least a single (one) increment above that - // address - // - // However ... we need to know this before this clock, hence - // this is calculated in the instruction decoder. - initial r_op_pipe = 1'b0; - always @(posedge i_clk) - if ((OPT_LOWPOWER && i_reset)||(clear_pipeline)||(i_halt)) - r_op_pipe <= 1'b0; - else if (op_ce) - r_op_pipe <= (dcd_pipe)&&(op_valid_mem)&&(!OPT_LOWPOWER || !dcd_illegal); - else if ((wr_reg_ce)&&(wr_reg_id == op_Bid[4:0])) - r_op_pipe <= 1'b0; - else if (mem_ce) // Clear us any time an op_ is clocked in - r_op_pipe <= 1'b0; - - assign op_pipe = r_op_pipe; -`ifdef FORMAL - always @(*) - if (OPT_LOWPOWER && !op_valid_mem) - assert(!r_op_pipe); -`endif - end else begin : NO_OP_PIPE - - assign op_pipe = 1'b0; - - end endgenerate - // }}} - - // Read from our register set - // {{{ - generate if (OPT_DISTRIBUTED_REGS) - begin : GEN_DISTRIBUTED_REGS - // {{{ - if (OPT_USERMODE) - begin : GEN_FULL_REGSET - - assign w_op_Av = (!OPT_LOWPOWER || dcd_valid || !OPT_PIPELINED) ? regset[dcd_A] : 32'h0; - assign w_op_Bv = (!OPT_LOWPOWER || dcd_valid || !OPT_PIPELINED) ? regset[dcd_B] : 32'h0; - - end else begin : GEN_NO_USERREGS - assign w_op_Av = (!OPT_LOWPOWER || dcd_valid || !OPT_PIPELINED) ? regset[dcd_A[3:0]] : 32'h0; - assign w_op_Bv = (!OPT_LOWPOWER || dcd_valid || !OPT_PIPELINED) ? regset[dcd_B[3:0]] : 32'h0; - end - - // verilator coverage_off - // verilator lint_off UNUSED - wire unused_prereg_addrs; - assign unused_prereg_addrs = &{ 1'b0, dcd_preA, dcd_preB }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} - end else begin : GEN_BLOCKRAM - // {{{ - reg [31:0] pre_rewrite_value, pre_op_Av, pre_op_Bv; - reg pre_rewrite_flag_A, pre_rewrite_flag_B; - - always @(posedge i_clk) - if (dcd_ce) - begin - pre_rewrite_flag_A <= (wr_reg_ce)&&(dcd_preA == wr_reg_id); - pre_rewrite_flag_B <= (wr_reg_ce)&&(dcd_preB == wr_reg_id); - pre_rewrite_value <= wr_gpreg_vl; - end else if (OPT_PIPELINED && dcd_valid) - begin - pre_rewrite_flag_A <= (wr_reg_ce)&&(dcd_A == wr_reg_id); - pre_rewrite_flag_B <= (wr_reg_ce)&&(dcd_B == wr_reg_id); - pre_rewrite_value <= wr_gpreg_vl; - end - - if (OPT_USERMODE) - begin : GEN_FULL_REGSET - - always @(posedge i_clk) - if (dcd_ce || (OPT_PIPELINED && dcd_valid)) - pre_op_Av <= regset[dcd_ce ? dcd_preA : dcd_A]; - - always @(posedge i_clk) - if (dcd_ce || (OPT_PIPELINED && dcd_valid)) - pre_op_Bv <= regset[dcd_ce ? dcd_preB : dcd_B]; - - end else begin : GEN_NO_USERREGS - always @(posedge i_clk) - if (dcd_ce || (OPT_PIPELINED && dcd_valid)) - pre_op_Av <= regset[dcd_ce ? dcd_preA[3:0] : dcd_A[3:0]]; - - always @(posedge i_clk) - if (dcd_ce || (OPT_PIPELINED && dcd_valid)) - pre_op_Bv <= regset[dcd_ce ? dcd_preB[3:0] : dcd_B[3:0]]; - end - - assign w_op_Av = (pre_rewrite_flag_A) ? pre_rewrite_value : pre_op_Av; - assign w_op_Bv = (pre_rewrite_flag_B) ? pre_rewrite_value : pre_op_Bv; - // }}} - end endgenerate - // }}} - - assign w_cpu_info = { - // {{{ - 1'b1, - (OPT_MPY >0)? 1'b1:1'b0, - (OPT_DIV >0)? 1'b1:1'b0, - (IMPLEMENT_FPU >0)? 1'b1:1'b0, - OPT_PIPELINED, - 1'b0, - (OPT_EARLY_BRANCHING > 0)? 1'b1:1'b0, - OPT_PIPELINED_BUS_ACCESS, - OPT_CIS - }; - // }}} - - always @(*) - begin - w_pcA_v = 0; - if ((!OPT_USERMODE)||(dcd_A[4] == dcd_gie)) - w_pcA_v[(AW+1):0] = { dcd_pc[AW+1:2], 2'b00 }; - else - w_pcA_v[(AW+1):0] = { upc[(AW+1):2], uhalt_phase, 1'b0 }; - end - - // Op register addresses - // {{{ - generate if (OPT_PIPELINED) - begin : OP_REG_ADVANEC - // {{{ - reg [4:0] r_op_R; - reg [4:0] r_op_Aid, r_op_Bid; - reg r_op_rA, r_op_rB; - - initial r_op_R = 0; - initial r_op_Aid = 0; - initial r_op_Bid = 0; - initial r_op_rA = 0; - initial r_op_rB = 0; - initial op_Rcc = 0; - always @(posedge i_clk) - begin - if (op_ce && (!OPT_LOWPOWER || w_op_valid)) - begin - r_op_R <= dcd_R; - r_op_Aid <= dcd_A; - if ((dcd_rB)&&(!dcd_early_branch)&&(!dcd_illegal)) - r_op_Bid <= dcd_B; - r_op_rA <= (dcd_rA)&&(!dcd_early_branch)&&(!dcd_illegal); - r_op_rB <= (dcd_rB)&&(!dcd_early_branch)&&(!dcd_illegal); - op_Rcc <= (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie); - end - - if (op_lowpower_clear) - begin - r_op_rA <= 1'b0; - r_op_rB <= 1'b0; - end - end - - assign op_R = r_op_R; - assign op_Aid = r_op_Aid; - assign op_Bid = r_op_Bid; - assign op_rA = r_op_rA; - assign op_rB = r_op_rB; - // }}} - end else begin : OP_REG_COPY - // {{{ - assign op_R = dcd_R; - assign op_Aid = dcd_A; - assign op_Bid = dcd_B; - assign op_rA = dcd_rA; - assign op_rB = dcd_rB; - - always @(*) - op_Rcc = (dcd_Rcc)&&(dcd_wR)&&(dcd_R[4]==dcd_gie); - // }}} - end endgenerate - // }}} - - // r_op_Av -- The registered value of the op A register - // {{{ - reg [2:0] avsrc; - reg [2:0] bvsrc; - reg [1:0] bisrc; - - always @(*) - begin - avsrc = 3'b000; - if (!OPT_PIPELINED || op_ce) - begin - if (dcd_Apc) - avsrc = 3'b101; - else if (dcd_Acc) - avsrc = 3'b110; - else - avsrc = 3'b111; - end - - if (OPT_PIPELINED && wr_reg_ce) - begin - if (!op_ce && wr_reg_id == op_Aid && op_rA) - avsrc = 3'b100; - else if (op_ce && wr_reg_id == dcd_A) - avsrc = 3'b100; - end - end - -// 44313 - initial r_op_Av = 0; - always @(posedge i_clk) - begin - if (avsrc[2]) - case(avsrc[1:0]) - 2'b00: r_op_Av <= wr_gpreg_vl; - 2'b01: r_op_Av <= w_pcA_v; - 2'b10: r_op_Av <= { w_cpu_info, w_op_Av[22:16], (dcd_A[4])?w_uflags:w_iflags }; - 2'b11: r_op_Av <= w_op_Av; - endcase - - if (op_lowpower_clear) - r_op_Av <= 0; - end - // }}} - - // w_op_B -- The registered value of the op B register - // {{{ - always @(*) - begin - w_pcB_v = 0; - if ((!OPT_USERMODE)||(dcd_B[4] == dcd_gie)) - w_pcB_v[(AW+1):0] = { dcd_pc[AW+1:2], 2'b00 }; - else - w_pcB_v[(AW+1):0] = { upc[(AW+1):2], uhalt_phase, 1'b0 }; - end - - always @(*) - if (!dcd_rB) - bisrc = 0; - else if ((OPT_PIPELINED)&&(wr_reg_ce)&&(wr_reg_id == dcd_B)) - bisrc = 1; - else if (dcd_Bcc) - bisrc = 2; - else - bisrc = 3; - - always @(*) - case(bisrc[1:0]) - 2'b00: w_op_BnI = 0; - 2'b01: w_op_BnI = wr_gpreg_vl; - 2'b10: w_op_BnI = { w_cpu_info, w_op_Bv[22:16], - (dcd_B[4]) ? w_uflags : w_iflags }; - 2'b11: w_op_BnI = w_op_Bv; - endcase - - always @(*) - begin - bvsrc = 0; - if ((!OPT_PIPELINED)||(op_ce)) - begin - if ((dcd_Bpc)&&(dcd_rB)) - bvsrc = 3'b100; - else - bvsrc = 3'b101; - end else if ((OPT_PIPELINED)&&(op_rB) - &&(wr_reg_ce)&&(op_Bid == wr_reg_id)) - bvsrc = 3'b110; - end - - initial r_op_Bv = 0; - always @(posedge i_clk) - begin - if (bvsrc[2]) casez(bvsrc[1:0]) - 2'b00: r_op_Bv <= w_pcB_v + { dcd_I[29:0], 2'b00 }; - 2'b01: r_op_Bv <= w_op_BnI + dcd_I; - 2'b1?: r_op_Bv <= wr_gpreg_vl; - endcase - - if (op_lowpower_clear) - r_op_Bv <= 0; - end - // }}} - - // op_F - // {{{ - // The logic here has become more complex than it should be, no thanks - // to Xilinx's Vivado trying to help. The conditions are supposed to - // be two sets of four bits: the top bits specify what bits matter, the - // bottom specify what those top bits must equal. However, two of - // conditions check whether bits are on, and those are the only two - // conditions checking those bits. Therefore, Vivado complains that - // these two bits are redundant. Hence the convoluted expression - // below, arriving at what we finally want in the (now wire net) - // op_F. - initial r_op_F = 7'h00; - always @(posedge i_clk) - begin - if ((!OPT_PIPELINED)||(op_ce)) - // Cannot do op_change_data_ce here since op_F depends - // upon being either correct for a valid op, or correct - // for the last valid op - begin // Set the flag condition codes, bit order is [3:0]=VNCZ - case(dcd_F[2:0]) - 3'h0: r_op_F <= 7'h00; // Always - 3'h1: r_op_F <= 7'h11; // Z - 3'h2: r_op_F <= 7'h44; // LT - 3'h3: r_op_F <= 7'h22; // C - 3'h4: r_op_F <= 7'h08; // V - 3'h5: r_op_F <= 7'h10; // NE - 3'h6: r_op_F <= 7'h40; // GE (!N) - 3'h7: r_op_F <= 7'h20; // NC - endcase - end - - if (op_lowpower_clear) - r_op_F <= 7'h00; - end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value } - assign op_F = { r_op_F[3], r_op_F[6:0] }; - // }}} - - // op_valid - // {{{ - assign w_op_valid = (!clear_pipeline)&&(dcd_valid) - &&(!dcd_ljmp)&&(!dcd_early_branch); - - initial op_valid = 1'b0; - initial op_valid_alu = 1'b0; - initial op_valid_mem = 1'b0; - initial op_valid_div = 1'b0; - initial op_valid_fpu = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(clear_pipeline)) - begin - // {{{ - op_valid <= 1'b0; - op_valid_alu <= 1'b0; - op_valid_mem <= 1'b0; - op_valid_div <= 1'b0; - op_valid_fpu <= 1'b0; - // }}} - end else if (op_ce) - begin - // {{{ - // Do we have a valid instruction? - // The decoder may vote to stall one of its - // instructions based upon something we currently - // have in our queue. This instruction must then - // move forward, and get a stall cycle inserted. - // Hence, the test on dcd_stalled here. If we must - // wait until our operands are valid, then we aren't - // valid yet until then. - if (OPT_PIPELINED || !op_valid) - begin - op_valid <= (w_op_valid)||(dcd_early_branch); - op_valid_alu <= (w_op_valid)&&((dcd_ALU)||(dcd_illegal)); - op_valid_mem <= (dcd_M)&&(!dcd_illegal) - &&(w_op_valid); - op_valid_div <= (OPT_DIV)&&(dcd_DIV)&&(!dcd_illegal)&&(w_op_valid); - op_valid_fpu <= (IMPLEMENT_FPU)&&(dcd_FP)&&(!dcd_illegal)&&(w_op_valid); - end else if ((adf_ce_unconditional)||(mem_ce)) - begin - op_valid <= 1'b0; - op_valid_alu <= 1'b0; - op_valid_mem <= 1'b0; - op_valid_div <= 1'b0; - op_valid_fpu <= 1'b0; - end - // }}} - end else if ((adf_ce_unconditional)||(mem_ce)) - begin - // {{{ - // If nothing advances into the OP stage, yet what was in - // the OP stage moves forward, then we need to invalidate what - // used to be here. - op_valid <= 1'b0; - op_valid_alu <= 1'b0; - op_valid_mem <= 1'b0; - op_valid_div <= 1'b0; - op_valid_fpu <= 1'b0; - // }}} - end - // }}} - - // op_lowpower_clear - // {{{ - generate if (!OPT_LOWPOWER || !OPT_PIPELINED) - begin : NO_OP_LOWPOWER_CLEAR - - assign op_lowpower_clear = 1'b0; - - end else begin : GEN_OP_LOWPOWER_CLEAR - reg r_op_lowpower_clear; - - always @(*) - if (i_reset || clear_pipeline) - r_op_lowpower_clear = 1'b1; - else if (op_ce && !w_op_valid) - r_op_lowpower_clear = 1'b1; - else if ((!op_ce || !w_op_valid)&&(adf_ce_unconditional || mem_ce)) - r_op_lowpower_clear = 1'b1; - else - r_op_lowpower_clear = 1'b0; - - assign op_lowpower_clear = r_op_lowpower_clear; - end endgenerate - // }}} - - // op_break - // {{{ - // Here's part of our debug interface. When we recognize a break - // instruction, we set the op_break flag. That'll prevent this - // instruction from entering the ALU, and cause an interrupt before - // this instruction. Thus, returning to this code will cause the - // break to repeat and continue upon return. To get out of this - // condition, replace the break instruction with what it is supposed - // to be, step through it, and then replace it back. In this fashion, - // a debugger can step through code. - // assign w_op_break = (dcd_break)&&(r_dcd_I[15:0] == 16'h0001); - - initial r_op_break = 1'b0; - always @(posedge i_clk) - if (clear_pipeline) - r_op_break <= 1'b0; - else if ((OPT_PIPELINED)&&(op_ce)) - r_op_break <= (dcd_valid)&&(dcd_break)&&(!dcd_illegal); - else if ((!OPT_PIPELINED)&&(dcd_valid)) - r_op_break <= (dcd_break)&&(!dcd_illegal)&&(!step || !stepped); - - assign op_break = r_op_break; -`ifdef FORMAL - always @(*) - if (op_break) - assert(op_valid || clear_pipeline); -`endif - // }}} - - // op_lock - // {{{ - generate if (!OPT_LOCK) - begin : NO_OPLOCK - - assign op_lock = 1'b0; - - // verilator coverage_off - // Verilator lint_off UNUSED - wire dcd_lock_unused; - assign dcd_lock_unused = &{ 1'b0, dcd_lock }; - // Verilator lint_on UNUSED - // verilator coverage_on - - end else // if (!OPT_LOCK) - begin : GEN_OPLOCK - reg r_op_lock; - - initial r_op_lock = 1'b0; - always @(posedge i_clk) - if (clear_pipeline) - r_op_lock <= 1'b0; - else if (op_ce) - r_op_lock <= (dcd_valid)&&(dcd_lock) - &&(!dcd_illegal); - assign op_lock = r_op_lock; - - end endgenerate - // }}} - - // op_illegal - // {{{ - initial op_illegal = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(clear_pipeline)) - op_illegal <= 1'b0; - else if (OPT_PIPELINED) - begin - if (op_ce) - op_illegal <= (dcd_valid)&&(!dcd_ljmp) - &&(!dcd_early_branch)&&(dcd_illegal); - end else if (!OPT_PIPELINED) - begin - if (dcd_valid) - op_illegal <= (!dcd_ljmp)&&(!dcd_early_branch)&&(dcd_illegal); - end - // }}} - - // op_wF - // {{{ - always @(posedge i_clk) - begin - if ((!OPT_PIPELINED)||(op_ce)) - op_wF <= (dcd_wF)&&((!dcd_Rcc)||(!dcd_wR)) - &&(!dcd_early_branch); - - if (op_lowpower_clear) - op_wF <= 1'b0; - end - // }}} - - // op_wR - // {{{ - generate if ((OPT_PIPELINED)||(OPT_EARLY_BRANCHING)) - begin : GEN_OP_WR - reg r_op_wR; - - initial r_op_wR = 1'b0; - always @(posedge i_clk) - begin - if (op_ce) - r_op_wR <= (dcd_wR)&&(!dcd_early_branch); - if (op_lowpower_clear) - r_op_wR <= 1'b0; - end - - assign op_wR = r_op_wR; - end else begin : COPY_OP_WR - - assign op_wR = dcd_wR; - - end endgenerate - // }}} - - // op_sim, op_sim_immv - // {{{ - generate if (OPT_SIM) - begin : OP_SIM - // - // Only execute this if OPT_SIM is true--that is, if we - // are running from a simulated environment. - // - reg r_op_sim; - reg [22:0] r_op_sim_immv; - - always @(posedge i_clk) - if (op_ce) - begin - r_op_sim <= dcd_sim && (!OPT_LOWPOWER || w_op_valid); - r_op_sim_immv <= dcd_sim_immv; - if (OPT_LOWPOWER && (!dcd_sim || !w_op_valid)) - r_op_sim_immv <= 0; - end else if (adf_ce_unconditional) - begin - r_op_sim <= 1'b0; - if (OPT_LOWPOWER) - r_op_sim_immv <= 0; - end - - assign op_sim = r_op_sim; - assign op_sim_immv = r_op_sim_immv; - - end else begin : NO_OP_SIM - - assign op_sim = 0; - assign op_sim_immv = 0; - - // verilator coverage_off - // Verilator lint_off UNUSED - wire op_sim_unused; - assign op_sim_unused = &{ 1'b0, dcd_sim, dcd_sim_immv }; - // Verilator lint_on UNUSED - // verilator coverage_on - end endgenerate - // }}} - - // op_pc - // {{{ - generate if ((OPT_PIPELINED)||(OPT_EARLY_BRANCHING)) - begin : SET_OP_PC - - reg [AW+1:0] r_op_pc; - - initial r_op_pc[0] = 1'b0; - always @(posedge i_clk) - if (op_ce) - begin - if (dcd_early_branch) - // Need to retire an early branch as a NOOP, - // to make sure our PC is properly updated - r_op_pc <= dcd_branch_pc; - else if (!OPT_LOWPOWER || w_op_valid) - r_op_pc <= dcd_pc; - end - - assign op_pc = r_op_pc; - - end else begin : SET_OP_PC - - assign op_pc = dcd_pc; - - end endgenerate - // }}} - - // op_opn -- the opcode of the current operation - // {{{ - generate if (!OPT_PIPELINED) - begin : COPY_DCD_OPN - - assign op_opn = dcd_opn; - - end else begin : FWD_OPERATION - - reg [3:0] r_op_opn; - - always @(posedge i_clk) - if (op_ce && (!OPT_LOWPOWER || w_op_valid || dcd_early_branch)) - begin - // Which ALU operation? Early branches are - // unimplemented moves - r_op_opn <= ((dcd_early_branch)||(dcd_illegal)) - ? CPU_MOV_OP : dcd_opn; - // opM <= dcd_M; // Is this a memory operation? - // What register will these results be written into? - end - - assign op_opn = r_op_opn; - - end endgenerate - // }}} - assign op_gie = gie; - - assign op_Fl = (op_gie)?(w_uflags[3:0]):(w_iflags[3:0]); - - // op_phase - // {{{ - generate if (OPT_CIS) - begin : OPT_CIS_OP_PHASE - - reg r_op_phase; - - initial r_op_phase = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(clear_pipeline)) - r_op_phase <= 1'b0; - else if (op_ce) - r_op_phase <= (dcd_phase)&&((!dcd_wR)||(!dcd_Rpc)); - - assign op_phase = r_op_phase; - end else begin : OPT_NOCIS_OP_PHASE - assign op_phase = 1'b0; - - // verilator lint_off UNUSED - wire OPT_CIS_dcdRpc; - assign OPT_CIS_dcdRpc = dcd_Rpc; - // verilator lint_on UNUSED - end endgenerate - // }}} - - // op_Av -- the combinatorial A value input to the ALU/MEM/DIV stage - // {{{ - // This is tricky. First, the PC and Flags registers aren't kept in - // register set but in special registers of their own. So step one - // is to select the right register. Step to is to replace that - // register with the results of an ALU or memory operation, if such - // results are now available. Otherwise, we'd need to insert a wait - // state of some type. - // - // The alternative approach would be to define some sort of - // op_stall wire, which would stall any upstream stage. - // We'll create a flag here to start our coordination. Once we - // define this flag to something other than just plain zero, then - // the stalls will already be in place. - generate if (OPT_PIPELINED) - begin : FWD_OP_AV - - assign op_Av = ((wr_reg_ce)&&(wr_reg_id == op_Aid)) - ? wr_gpreg_vl : r_op_Av; - - end else begin : COPY_OP_AV - - assign op_Av = r_op_Av; - - end endgenerate - // }}} - - // dcd_A_stall - // {{{ - // Stall if we have decoded an instruction that will read register A - // AND ... something that may write a register is running - // AND (series of conditions here ...) - // The operation might set flags, and we wish to read the - // CC register - // OR ... (No other conditions) - generate if (OPT_PIPELINED) - begin : GEN_DCDA_STALL - - assign dcd_A_stall = (dcd_rA) // &&(dcd_valid) is checked for elsewhere - &&((op_valid)||(i_mem_rdbusy) - ||(div_busy)||(fpu_busy)) - &&(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Acc)) - ||((dcd_rA)&&(dcd_Acc)&&(cc_invalid_for_dcd)); - end else begin : NO_DCDA_STALL - - // There are no pipeline hazards, if we aren't pipelined - assign dcd_A_stall = 1'b0; - - end endgenerate - // }}} - - // op_Bv - // {{{ - assign op_Bv = ((OPT_PIPELINED)&&(wr_reg_ce) - &&(wr_reg_id == op_Bid)&&(op_rB)) - ? wr_gpreg_vl: r_op_Bv; - // }}} - - // dcd_B_stall, dcd_F_stall - // {{{ - generate if (OPT_PIPELINED) - begin : DCD_BF_STALLS - // Stall if we have decoded an instruction that will read register B - // AND ... something that may write a (unknown) register is running - // AND (series of conditions here ...) - // The operation might set flags, and we wish to read the - // CC register - // OR the operation might set register B, and we still need - // a clock to add the offset to it - assign dcd_B_stall = (dcd_rB) // &&(dcd_valid) is checked for elsewhere - // {{{ - // If the op stage isn't valid, yet something - // is running, then it must have been valid. - // We'll use the last values from that stage - // (op_wR, op_wF, op_R) in our logic below. - &&((op_valid)||(i_mem_rdbusy) - ||(div_busy)||(fpu_busy)||(alu_busy)) - &&( - // Okay, what happens if the result register - // from instruction 1 becomes the input for - // instruction two, *and* there's an immediate - // offset in instruction two? In that case, we - // need an extra clock between the two - // instructions to calculate the base plus - // offset. - // - // What if instruction 1 (or before) is in a - // memory pipeline? We may no longer know what - // the register was! We will then need to - // blindly wait. We'll temper this only waiting - // if we're not piping this new instruction. - // If we were piping, the pipe logic in the - // decode circuit has told us that the hazard - // is clear, so we're okay then. - // - ((!dcd_zI)&&( - ((op_R == dcd_B)&&(op_wR)) - ||((i_mem_rdbusy)&&(!dcd_pipe)) - ||(((alu_busy || - div_busy || i_mem_rdbusy)) - &&(alu_reg == dcd_B)) - ||((wr_reg_ce)&&(wr_reg_id[3:1] == 3'h7)) - )) - // Stall following any instruction that will - // set the flags, if we're going to need the - // flags (CC) register for op_B. - ||(((op_wF)||(cc_invalid_for_dcd))&&(dcd_Bcc)) - // Stall on any ongoing memory operation that - // will write to op_B -- captured above - // ||((i_mem_busy)&&(!mem_we)&&(mem_last_reg==dcd_B)&&(!dcd_zI)) - ) - ||((dcd_rB)&&(dcd_Bcc)&&(cc_invalid_for_dcd)); - // }}} - assign dcd_F_stall = ((!dcd_F[3]) - // {{{ - ||((dcd_rA)&&(dcd_A[3:1]==3'h7) - &&(dcd_A[4:0] != { gie, 4'hf})) - ||((dcd_rB)&&(dcd_B[3:1]==3'h7)) - &&(dcd_B[4:0] != { gie, 4'hf})) - &&(((op_valid)&&(op_wR) - &&(op_R[3:1]==3'h7) - &&(op_R[4:0]!={gie, 4'hf})) - ||(pending_sreg_write)); - // &&(dcd_valid) is checked for elsewhere - // }}} - end else begin : NO_PIPELINE_NO_STALL - // {{{ - // No stalls without pipelining, 'cause how can you have a - // pipeline hazard without the pipeline? - assign dcd_B_stall = 1'b0; - assign dcd_F_stall = 1'b0; - // }}} - end endgenerate - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // PIPELINE STAGE #4 :: Apply Instruction - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // The ALU itself - cpuops #( - // {{{ - .OPT_MPY(OPT_MPY), - .OPT_SHIFTS(OPT_SHIFTS), - .OPT_LOWPOWER(OPT_LOWPOWER) - // }}} - ) doalu( - // {{{ - .i_clk(i_clk), .i_reset((i_reset)||(clear_pipeline)), - .i_stb(alu_ce), - .i_op((!OPT_LOWPOWER || alu_ce) ? op_opn : 4'h0), - .i_a( (!OPT_LOWPOWER || alu_ce) ? op_Av : 32'h0), - .i_b( (!OPT_LOWPOWER || alu_ce) ? op_Bv : 32'h0), - .o_c(alu_result), .o_f(alu_flags), - .o_valid(alu_valid), - .o_busy(alu_busy) - // }}} - ); - - // Divide - // {{{ - generate if (OPT_DIV != 0) - begin : DIVIDE -`ifdef FORMAL -`define DIVIDE_MODULE abs_div -`else -`define DIVIDE_MODULE div -`endif - `DIVIDE_MODULE #( - .OPT_LOWPOWER(OPT_LOWPOWER) - ) thedivide( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || clear_pipeline), - .i_wr(div_ce), .i_signed(op_opn[0]), - .i_numerator(op_Av), .i_denominator(op_Bv), - .o_busy(div_busy), .o_valid(div_valid), - .o_err(div_error), .o_quotient(div_result), - .o_flags(div_flags) - // }}} - ); - - end else begin : NO_DIVIDE - // {{{ - assign div_error = 1'b0; // Can't be high unless div_valid - assign div_busy = 1'b0; - assign div_valid = 1'b0; - assign div_result= 32'h00; - assign div_flags = 4'h0; - - // Make verilator happy here - // verilator coverage_off - // verilator lint_off UNUSED - wire unused_divide; - assign unused_divide = &{ 1'b0, div_ce }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} - end endgenerate - // }}} - - // (Non-existent) FPU - // {{{ - generate if (IMPLEMENT_FPU != 0) - begin : FPU - // - // sfpu thefpu(i_clk, i_reset, fpu_ce, op_opn[2:0], - // op_Av, op_Bv, fpu_busy, fpu_valid, fpu_err, fpu_result, - // fpu_flags); - // -`ifdef FORMAL - abs_div thefpu(i_clk, ((i_reset)||(clear_pipeline)), - fpu_ce, op_opn[2:0], - op_Av, op_Bv, fpu_busy, fpu_valid, fpu_error, fpu_result, - fpu_flags); - -`else - assign fpu_error = 1'b0; // Must only be true if fpu_valid - assign fpu_busy = 1'b0; - assign fpu_valid = 1'b0; - assign fpu_result= 32'h00; - assign fpu_flags = 4'h0; -`endif - end else begin : GEN_NOFPU - assign fpu_error = 1'b0; - assign fpu_busy = 1'b0; - assign fpu_valid = 1'b0; - assign fpu_result= 32'h00; - assign fpu_flags = 4'h0; - end endgenerate - // }}} - - // Condition handling - // {{{ - assign set_cond = ((op_F[7:4]&op_Fl[3:0])==op_F[3:0]); - initial alu_wF = 1'b0; - initial alu_wR = 1'b0; - generate if (OPT_PIPELINED) - begin : GEN_COND_PIPELINED - always @(posedge i_clk) - if (i_reset) - begin - alu_wR <= 1'b0; - alu_wF <= 1'b0; - end else if (alu_ce) - begin - // alu_reg <= op_R; - alu_wR <= (op_wR)&&(set_cond)&&(!op_illegal); - alu_wF <= (op_wF)&&(set_cond)&&(!op_illegal); - end else if (!alu_busy) - begin - // These are strobe signals, so clear them if they - // aren't going to be set for any particular clock - alu_wR <= (r_halted)&&(OPT_DBGPORT && i_dbg_we && !o_dbg_stall); - alu_wF <= 1'b0; - end - end else begin : GEN_COND_NOPIPE - - always @(posedge i_clk) - begin - alu_wR <= (op_wR)&&(set_cond)&&(!op_illegal); - alu_wF <= (op_wF)&&(set_cond)&&(!op_illegal); - end - - end endgenerate - // }}} - - // alu_phase - // {{{ - // Instruction phase (which half of the instruction we are on) tracking - generate if (OPT_CIS) - begin : GEN_ALU_PHASE - - reg r_alu_phase; - - initial r_alu_phase = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(clear_pipeline)) - r_alu_phase <= 1'b0; - else if (((adf_ce_unconditional)||(mem_ce))&&(op_valid)) - r_alu_phase <= op_phase; - else if ((adf_ce_unconditional)||(mem_ce)) - r_alu_phase <= 1'b0; - - assign alu_phase = r_alu_phase; - end else begin : NO_ALUPHASE - - assign alu_phase = 1'b0; - end endgenerate - // }}} - - // alu_reg - // {{{ - generate if (OPT_PIPELINED) - begin : GEN_ALUREG_PIPE - - always @(posedge i_clk) - if (alu_ce || div_ce || o_mem_ce || fpu_ce) - alu_reg <= op_R; - else if (OPT_DBGPORT && i_dbg_we && !o_dbg_stall) - alu_reg <= i_dbg_wreg; - - end else begin : GEN_ALUREG_NOPIPE - - always @(posedge i_clk) - if (OPT_DBGPORT && i_dbg_we && !o_dbg_stall) - alu_reg <= i_dbg_wreg; - else - alu_reg <= op_R; - end endgenerate - // }}} - - // wr_index - // {{{ - initial wr_index = 0; - always @(posedge i_clk) - begin - if ((OPT_PIPELINED && (mem_ce || adf_ce_unconditional)) - ||(!OPT_PIPELINED && op_valid)) - begin - wr_index <= 0; - /* - if (op_valid_mem) - wr_index <= 3'b001; - if (op_valid_alu) - wr_index <= 3'b010; - if (op_valid_div) - wr_index <= 3'b011; - if (op_valid_fpu) - wr_index <= 3'b100; - */ - - wr_index[0] <= (op_valid_mem | op_valid_div); - wr_index[1] <= (op_valid_alu | op_valid_div); - wr_index[2] <= (op_valid_fpu); - end - - if (OPT_DBGPORT && i_dbg_we && !o_dbg_stall) - wr_index <= 3'b000; - - if (!IMPLEMENT_FPU) - wr_index[2] <= 1'b0; - end - // }}} - - // - // DEBUG Register write access starts here - // - // {{{ - initial dbgv = 1'b0; - always @(posedge i_clk) - if (i_reset || !r_halted) - dbgv <= 0; - else - dbgv <= OPT_DBGPORT && i_dbg_we && !o_dbg_stall; - - always @(posedge i_clk) - if (!OPT_LOWPOWER || (OPT_DBGPORT && i_dbg_we)) - dbg_val <= i_dbg_data; - - // dbg_clear_pipe - // {{{ - always @(posedge i_clk) - if (i_reset || clear_pipeline || !r_halted) - dbg_clear_pipe <= 0; - else if (OPT_DBGPORT && i_dbg_we && !o_dbg_stall) - begin - dbg_clear_pipe <= 1'b0; - - if (!OPT_PIPELINED) - dbg_clear_pipe <= 1'b1; - if ((i_dbg_wreg == op_Bid)&&(op_rB)) - dbg_clear_pipe <= 1'b1; - if (i_dbg_wreg[3:1] == 3'h7) - dbg_clear_pipe <= 1'b1; - end else if ((!OPT_PIPELINED)&&(i_clear_cache && !o_dbg_stall)) - dbg_clear_pipe <= 1'b1; - else - dbg_clear_pipe <= 1'b0; - // }}} - - assign alu_gie = gie; - // }}} - - // r_alu_pc - // {{{ - generate if (OPT_PIPELINED) - begin : GEN_ALU_PC - reg [(AW+1):0] r_alu_pc; - initial r_alu_pc = 0; - always @(posedge i_clk) - if ((adf_ce_unconditional) - ||((master_ce)&&(op_valid_mem) - &&(!clear_pipeline)&&(!mem_stalled))) - r_alu_pc <= op_pc; - assign alu_pc = r_alu_pc; - - end else begin : GEN_ALU_PC_NOPIPE - - assign alu_pc = op_pc; - - end endgenerate - // }}} - - // r_alu_illegal - // {{{ - generate if (OPT_PIPELINED) - begin : SET_ALU_ILLEGAL - reg r_alu_illegal; - - initial r_alu_illegal = 0; - always @(posedge i_clk) - if (clear_pipeline) - r_alu_illegal <= 1'b0; - else if (adf_ce_unconditional) - r_alu_illegal <= op_illegal; - else - r_alu_illegal <= 1'b0; - - assign alu_illegal = (r_alu_illegal); - end else begin : SET_ALU_ILLEGAL - assign alu_illegal = op_illegal; - end endgenerate - // }}} - - // r_alu_pc_valid, mem_pc_valid - // {{{ - initial r_alu_pc_valid = 1'b0; - initial mem_pc_valid = 1'b0; - always @(posedge i_clk) - if (clear_pipeline) - r_alu_pc_valid <= 1'b0; - else if ((adf_ce_unconditional)&&(!op_phase)) - r_alu_pc_valid <= 1'b1; - else if (((!alu_busy)&&(!div_busy)&&(!fpu_busy))||(clear_pipeline)) - r_alu_pc_valid <= 1'b0; - - assign alu_pc_valid = (r_alu_pc_valid) - &&((!alu_busy)&&(!div_busy)&&(!fpu_busy)); - - always @(posedge i_clk) - if (i_reset) - mem_pc_valid <= 1'b0; - else - mem_pc_valid <= (mem_ce); - // }}} - - // Bus lock logic - // {{{ - generate if (OPT_LOCK) - begin : BUSLOCK - reg r_prelock_stall; - reg [1:0] r_bus_lock; - reg [AW+1:0] r_lock_pc; - - // r_prelock_stall - // {{{ - initial r_prelock_stall = 1'b0; - always @(posedge i_clk) - if (!OPT_PIPELINED || clear_pipeline) - r_prelock_stall <= 1'b0; - else if (op_valid && op_lock && r_bus_lock == 2'b00 - && adf_ce_unconditional) - r_prelock_stall <= 1'b1; - else if (op_valid && dcd_valid - && (i_pf_valid || dcd_early_branch)) - r_prelock_stall <= 1'b0; - // }}} - - // r_lock_pc - // {{{ - always @(posedge i_clk) - if (op_valid && op_ce && op_lock) - r_lock_pc <= op_pc-4; -`ifdef FORMAL - always @(posedge i_clk) - cover(op_valid && op_ce && op_lock); -`endif - // }}} - - // r_bus_lock - // {{{ - // Count 3 cycles. The lock will only hold solid for three - // cycles after the LOCK instruction is received. Count those - // cycles here. - initial r_bus_lock = 2'b00; - always @(posedge i_clk) - if (clear_pipeline) - r_bus_lock <= 2'b00; - else if (op_valid && (adf_ce_unconditional||mem_ce)) - begin - if (r_bus_lock != 2'b00) - r_bus_lock <= r_bus_lock - 1; - else if (op_lock) - r_bus_lock <= 2'b11; - end - // }}} - - assign prelock_stall = OPT_PIPELINED && r_prelock_stall; - assign o_bus_lock = |r_bus_lock; - assign o_mem_lock_pc = r_lock_pc; - assign last_lock_insn = (r_bus_lock <= 1); -`ifdef FORMAL - // {{{ - if (OPT_PIPELINED) - begin - (* anyconst *) reg r_nojump_lock; - - always @(*) - if (r_nojump_lock && (r_prelock_stall || r_bus_lock)) - begin - assume(!dcd_early_branch); - assume(!dcd_ljmp); - end - - always @(*) - if (!clear_pipeline) case(r_bus_lock) - 2'b11: if (!prelock_stall && r_nojump_lock) - begin - assert(op_valid && dcd_valid && i_pf_valid); - end - 2'b10: begin - assert(!prelock_stall); - if (r_nojump_lock) - begin - assert(dcd_valid); - assert(op_valid + dcd_valid + i_pf_valid >= 2'b10); - end end - 2'b01: begin - assert(!prelock_stall); - if (r_nojump_lock && !dcd_illegal) - begin - assert(op_valid || dcd_valid - || i_pf_valid); - end end - 2'b00: assert(!prelock_stall); - endcase - end else begin - - always @(*) - assert(!prelock_stall); - end - // }}} -`endif - end else begin : NO_BUSLOCK - // {{{ - assign prelock_stall = 1'b0; - assign o_bus_lock = 1'b0; - assign o_mem_lock_pc = 0; - assign last_lock_insn= 1; - // }}} - end endgenerate - // }}} - - // Memory interface - // {{{ - // This logic is now managed outside the ZipCore - // - assign o_mem_ce = mem_ce && set_cond; - assign o_mem_op = ((mem_ce && set_cond) || !OPT_LOWPOWER) ? op_opn[2:0] : 3'h0; - assign o_mem_data = ((mem_ce && set_cond) || !OPT_LOWPOWER) ? op_Av : 32'h0; - assign o_mem_addr = ((mem_ce && set_cond) || !OPT_LOWPOWER) ? op_Bv : 32'h0; - assign o_mem_reg = ((mem_ce && set_cond) || !OPT_LOWPOWER) ? op_R : 5'h0; - - // }}} - - // Sim instructions, alu_sim, alu_sim_immv - // {{{ - wire cpu_sim; - - generate if (OPT_SIM) - begin : ALU_SIM - reg r_alu_sim; - reg [22:0] r_alu_sim_immv; - wire [4:0] regid; - - assign regid = { (OPT_USERMODE && gie), op_sim_immv[3:0]}; - - if (OPT_USERMODE) - begin : GEN_ALLSIM - // {{{ - assign cpu_sim = !i_reset && !clear_pipeline - && adf_ce_unconditional && set_cond - && op_sim && op_valid_alu - &&(!wr_reg_ce || !wr_write_pc - || wr_reg_id[4] != alu_gie); - - initial r_alu_sim = 1'b0; - always @(posedge i_clk) - begin - if (cpu_sim) - begin - // Execute simulation only instructions - // {{{ - if ((op_sim_immv[19:10] == 10'h0)&&(op_sim_immv[8])) - begin // [N/S]EXIT - // {{{ - $finish; - - // if (op_sim_immv[19:4] == 16'h0031) - // Exit(User reg), code cpu_wr_gpreg - // Verilog offers no support for this. - // Veri1ator might, but it isn't - // standard. - // if (op_sim_immv[19:4] == 16'h0030) - // Exit(Normal reg), code cpu_wr_gpreg - // $finish; - // if (op_sim_immv[19:8] == 12'h001) - // Exit(Immediate), code cpu_wr_gpreg - // $finish; - // }}} - end - - if (op_sim_immv[19:0] == 20'h2ff) - begin - // DUMP all registers - // {{{ - if (!op_gie) - begin - $write("sR0 : %08x ", regset[0]); - $write("sR1 : %08x ", regset[1]); - $write("sR2 : %08x ", regset[2]); - $write("sR3 : %08x\n",regset[3]); - - $write("sR4 : %08x ", regset[4]); - $write("sR5 : %08x ", regset[5]); - $write("sR6 : %08x ", regset[6]); - $write("sR7 : %08x\n",regset[7]); - - $write("sR8 : %08x ", regset[8]); - $write("sR9 : %08x ", regset[9]); - $write("sR10: %08x ", regset[10]); - $write("sR11: %08x\n",regset[11]); - - $write("sR12: %08x ", regset[12]); - $write("sSP : %08x ", regset[13]); - $write("sCC : %08x ", w_iflags); - $write("sPC : %08x\n", (!op_gie) ? op_pc : ipc); - $write("\n", (!op_gie) ? op_pc : ipc); - end - - $write("uR0 : %08x ", regset[16]); - $write("uR1 : %08x ", regset[17]); - $write("uR2 : %08x ", regset[18]); - $write("uR3 : %08x\n",regset[19]); - - $write("uR4 : %08x ", regset[20]); - $write("uR5 : %08x ", regset[21]); - $write("uR6 : %08x ", regset[22]); - $write("uR7 : %08x\n",regset[23]); - - $write("uR8 : %08x ", regset[24]); - $write("uR9 : %08x ", regset[25]); - $write("uR10: %08x ", regset[26]); - $write("uR11: %08x\n",regset[27]); - - $write("uR12: %08x ", regset[28]); - $write("uSP : %08x ", regset[29]); - $write("uCC : %08x ", w_uflags); - $write("uPC : %08x\n", (op_gie) ? op_pc : upc); - // }}} - end - - if (op_sim_immv[19:4] == 16'h0020) - begin - // Dump a register - // {{{ - $write("@%08x ", op_pc); - $write("%c", (op_gie) ? "s":"u"); - $write("R[%2d] = 0x", op_sim_immv[3:0]); - // Dump a register - if (wr_reg_ce && wr_reg_id == regid) - $display("%08x", wr_gpreg_vl); - else - $display("%08x", regset[regid]); - // }}} - end - if (op_sim_immv[19:4] == 16'h0021) - begin - // Dump a user register - // {{{ - $write("@%08x u", op_pc); - $write("R[%2d] = 0x", op_sim_immv[3:0]); - if (wr_reg_ce && wr_reg_id == { 1'b1, op_sim_immv[3:0] }) - $display("%08x\n", wr_gpreg_vl); - else - $display("%08x\n", regset[{ 1'b1, - op_sim_immv[3:0]}]); - // }}} - end - if (op_sim_immv[19:4] == 16'h0023) - begin - // SOUT(user register) - // {{{ - if (wr_reg_ce && wr_reg_id == { 1'b1, op_sim_immv[3:0] }) - $write("%c", wr_gpreg_vl[7:0]); - else - $write("%c", regset[{ 1'b1, op_sim_immv[3:0]}][7:0]); - // }}} - end - if (op_sim_immv[19:4] == 16'h0022) - begin - // SOUT(register) - // {{{ - if (wr_reg_ce && wr_reg_id == regid) - $write("%c", wr_gpreg_vl[7:0]); - else - $write("%c", regset[regid][7:0]); - // }}} - end - - if (op_sim_immv[19:8] == 12'h004) - begin - // SOUT(Immediate) - // {{{ - $write("%c", op_sim_immv[7:0]); - // }}} - end - - // ELSE unrecognized SIM instruction - - // Set alu_sim either way - r_alu_sim <= 1'b1; - // }}} - end else - r_alu_sim <= 1'b0; - - if (adf_ce_unconditional) - r_alu_sim_immv <= op_sim_immv; - end - // }}} - end else begin : GEN_NO_USERSIM - // {{{ - assign cpu_sim = !i_reset && !clear_pipeline - && adf_ce_unconditional && set_cond - && op_sim && op_valid_alu - &&(!wr_reg_ce || !wr_write_pc - || wr_reg_id[4] != alu_gie); - - initial r_alu_sim = 1'b0; - always @(posedge i_clk) - begin - if (cpu_sim) - begin - // Execute simulation only instructions - // {{{ - if ((op_sim_immv[19:10] == 10'h0)&&(op_sim_immv[8])) - begin // [N/S]EXIT - // {{{ - $finish; - - // if (op_sim_immv[19:4] == 16'h0031) - // Exit(User reg), code cpu_wr_gpreg - // Verilog offers no support for this. - // Veri1ator might, but it isn't - // standard. - // if (op_sim_immv[19:4] == 16'h0030) - // Exit(Normal reg), code cpu_wr_gpreg - // $finish; - // if (op_sim_immv[19:8] == 12'h001) - // Exit(Immediate), code cpu_wr_gpreg - // $finish; - // }}} - end - - if (op_sim_immv[19:0] == 20'h2ff) - begin - // DUMP all registers - // {{{ - if (!op_gie) - begin - $write(" R0 : %08x ", regset[0]); - $write(" R1 : %08x ", regset[1]); - $write(" R2 : %08x ", regset[2]); - $write(" R3 : %08x\n",regset[3]); - - $write(" R4 : %08x ", regset[4]); - $write(" R5 : %08x ", regset[5]); - $write(" R6 : %08x ", regset[6]); - $write(" R7 : %08x\n",regset[7]); - - $write(" R8 : %08x ", regset[8]); - $write(" R9 : %08x ", regset[9]); - $write(" R10: %08x ", regset[10]); - $write(" R11: %08x\n",regset[11]); - - $write(" R12: %08x ", regset[12]); - $write(" SP : %08x ", regset[13]); - $write(" CC : %08x ", w_iflags); - $write(" PC : %08x\n", op_pc); - end - - // }}} - end - - if (op_sim_immv[19:5] == 15'h0010) - begin - // Dump a register - // {{{ - $write("@%08x ", op_pc); - $write(" R[%2d] = 0x", op_sim_immv[3:0]); - // Dump a register - if (wr_reg_ce&&wr_reg_id[3:0] == regid[3:0]) - $display("%08x", wr_gpreg_vl); - else - $display("%08x", regset[regid[3:0]]); - // }}} - end - if (op_sim_immv[19:5] == 15'h0011) - begin - // SOUT(user register) - // {{{ - if (wr_reg_ce && wr_reg_id[3:0] == op_sim_immv[3:0]) - $write("%c", wr_gpreg_vl[7:0]); - else - $write("%c", regset[op_sim_immv[3:0]][7:0]); - // }}} - end - - if (op_sim_immv[19:8] == 12'h004) - begin - // SOUT(Immediate) - // {{{ - $write("%c", op_sim_immv[7:0]); - // }}} - end - - // ELSE unrecognized SIM instruction - - // Set alu_sim either way - r_alu_sim <= 1'b1; - // }}} - end else - r_alu_sim <= 1'b0; - - if (adf_ce_unconditional) - r_alu_sim_immv <= op_sim_immv; - end - - // Verilator lint_off UNUSED - wire unused_simmv; - assign unused_simmv = &{ 1'b0, regid[4] }; - // Verilator lint_on UNUSED - // }}} - end - - assign alu_sim = r_alu_sim; - assign alu_sim_immv = r_alu_sim_immv; - - end else begin : NO_ALU_SIM - - assign alu_sim = 0; - assign alu_sim_immv = 0; - assign cpu_sim = 0; - - end endgenerate - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // PIPELINE STAGE #5 :: Write-back results - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // - // This stage is not allowed to stall. If results are ready to be - // written back, they are written back at all cost. Sleepy CPU's - // won't prevent write back, nor debug modes, halting the CPU, nor - // anything else. Indeed, the (master_ce) bit is only as relevant - // as knowinig something is available for writeback. - - // (was) wr_discard, wr_reg_ce - // {{{ - // - // Write back to our generic register set ... - // When shall we write back? On one of two conditions - // Note that the flags needed to be checked before issuing the - // bus instruction, so they don't need to be checked here. - // Further, alu_wR includes (set_cond), so we don't need to - // check for that here either. It also includes alu_illegal, so - // again--doesn't need to be checked again here. - -/* - // 12 inputs. This implementation is made worse by wr_index. - always @(*) - case(wr_index) - 3'b000: wr_reg_ce = dbgv; - 3'b001: wr_reg_ce = i_mem_valid; - //3'b010: wr_reg_ce = (!clear_pipeline)&&(alu_wR && alu_valid); - 3'b011: wr_reg_ce = (!clear_pipeline)&&(div_valid)&&(!div_error); - 3'b1??: wr_reg_ce = (!clear_pipeline)&&(fpu_valid)&&(!fpu_error); - default: wr_reg_ce = (!clear_pipeline)&&(alu_wR && alu_valid); - endcase -*/ - // 7-LUT -- without FPU or wr_index (which wasn't needed) - always @(*) - begin - wr_reg_ce = dbgv || i_mem_valid; - if ((alu_wR && alu_valid) - ||(div_valid && !div_error) - ||(fpu_valid && !fpu_error)) - wr_reg_ce = wr_reg_ce || !clear_pipeline; - end -`ifdef FORMAL - always @(*) - if (!i_reset && ((alu_wR && alu_valid) - ||(div_valid && !div_error) - ||(fpu_valid && !fpu_error))) - assert(!dbgv && !i_mem_valid); - - always @(*) - if (!i_reset) - casez(wr_index) - 3'b000: assert(!i_mem_valid && (!alu_wR || !alu_valid) - && (!div_valid || div_error) - && (!fpu_valid || fpu_error)); - 3'b001: assert(!dbgv && (!alu_wR || !alu_valid) - && (!div_valid || div_error) - && (!fpu_valid || fpu_error)); - 3'b010: assert(!dbgv && !i_mem_valid - // && (!alu_wR || !alu_valid) - && (!div_valid || div_error) - && (!fpu_valid || fpu_error)); - 3'b011: assert(!dbgv && !i_mem_valid - && (!alu_wR || !alu_valid) - // && (!div_valid || div_error) - && (!fpu_valid || fpu_error)); - 3'b100: assert(!dbgv && !i_mem_valid - && (!alu_wR || !alu_valid) - && (!div_valid || div_error)); - // && (!fpu_valid || fpu_error); - default: assert(0); - endcase -`endif - // }}} - - // wr_reg_id, wr_write-cc, wr_write_scc, wr_write_ucc, wr_write_pc - // {{{ - // Which register shall be written? - // COULD SIMPLIFY THIS: by adding three bits to these registers, - // One or PC, one for CC, and one for GIE match - // Note that the alu_reg is the register to write on a divide or - // FPU operation. - generate if (OPT_USERMODE) - begin : GEN_USERREG - assign wr_reg_id = (i_mem_valid) ? i_mem_wreg : alu_reg; - end else begin : NO_USERREG - assign wr_reg_id[3:0] = (i_mem_valid) - ? i_mem_wreg[3:0] : alu_reg[3:0]; - - assign wr_reg_id[4] = 1'b0; - end endgenerate - - // Are we writing to the CC register? - // one 5-LUT ea - assign wr_write_cc = (wr_reg_id[3:0] == CPU_CC_REG); - assign wr_write_scc = (wr_reg_id[4:0] == {1'b0, CPU_CC_REG}); - assign wr_write_ucc = (wr_reg_id[4:0] == {1'b1, CPU_CC_REG}); - // Are we writing to the PC? - assign wr_write_pc = (wr_reg_id[3:0] == CPU_PC_REG); - // }}} - - // wr_?preg_vl: Select from among sources the value to be writtena - // {{{ - // One 6-LUT per bit, or 32 6-LUTs w/o FPU - always @(*) - casez(wr_index) - 3'b000: wr_gpreg_vl = dbg_val; - 3'b001: wr_gpreg_vl = i_mem_result; - // 3'b010: wr_gpreg_vl = alu_result; - 3'b011: wr_gpreg_vl = div_result; - 3'b1??: wr_gpreg_vl = fpu_result; - default: wr_gpreg_vl = alu_result; - endcase - - // One 6-LUT per bit, or 32 6-LUTs - always @(*) - case(wr_index[1:0]) - 2'b00: wr_spreg_vl = dbg_val; - 2'b01: wr_spreg_vl = i_mem_result; - // 3'b010: wr_gpreg_vl = alu_result; - default: wr_spreg_vl = alu_result; - endcase - // }}} - - // Update the register set - // {{{ - generate if (OPT_USERMODE) - begin : SET_REGISTERS - - always @(posedge i_clk) - if (wr_reg_ce) - regset[wr_reg_id] <= wr_gpreg_vl; - - end else begin : SET_SREGISTERS - - always @(posedge i_clk) - if (wr_reg_ce) - regset[wr_reg_id[3:0]] <= wr_gpreg_vl; - - end endgenerate - // }}} - - // - // Write back to the condition codes/flags register ... - - // wr_flags_ce : should condition codes be written to? - // {{{ - // When shall we write to our flags register? alu_wF already - // includes the set condition ... - // assign wr_flags_ce = (alu_wF)&&((alu_valid) - // ||(div_valid)||(fpu_valid)) - // &&(!clear_pipeline)&&(!alu_illegal); -/* - // 10 inputs - always @(*) - begin - wr_flags_ce = 0; - if (alu_wF && !clear_pipeline) // Includes !alu_illegal in wF - case(wr_index) - // 3'b000: wr_flags_ce = 0; // Debug - // 3'b001: wr_flags_ce = 0; // Memory - 3'b010: wr_flags_ce = alu_valid; // ALU - 3'b011: wr_flags_ce = div_valid && !div_error; // DIV - 3'b1??: wr_flags_ce = fpu_valid && !fpu_error; // FPU - default: wr_flags_ce = 0; - endcase - end -*/ - // 7-LUT -- since we don't need wr_index - always @(*) - begin - wr_flags_ce = alu_valid || (div_valid && !div_error) - || (fpu_valid && !fpu_error); - if (!alu_wF || clear_pipeline) - wr_flags_ce = 1'b0; - end -`ifdef FORMAL - always @(*) - if (!i_reset) - begin - casez(wr_index) - 3'b000: assert(wr_flags_ce == 1'b0); - 3'b001: assert(wr_flags_ce == 1'b0); - 3'b010: assert(wr_flags_ce == (alu_wF && !clear_pipeline && alu_valid)); - 3'b011: assert(wr_flags_ce == (alu_wF && !clear_pipeline && div_valid && !div_error)); - 3'b100: assert(IMPLEMENT_FPU && wr_flags_ce == (alu_wF && !clear_pipeline && fpu_valid && !fpu_error)); - default: assert(0); - endcase - - if (alu_illegal) - assert(!div_valid && !fpu_valid - && (!alu_wF || !alu_valid)); - end -`endif - // }}} - - // wr_flags: what should the new condition codes be? - // {{{ - always @(*) - begin - wr_flags = 0; - casez(wr_index) - 3'b010: wr_flags = alu_flags; - 3'b011: wr_flags = div_flags; - 3'b1??: wr_flags = fpu_flags; - default: wr_flags = 0; - endcase - end - // }}} - - // w_uflags, w_iflags : Define the current CC registers - // {{{ - assign w_uflags = { 2'b00, uhalt_phase, ufpu_err_flag, - udiv_err_flag, ubus_err_flag, trap, ill_err_u, - ubreak, !gie && user_step, 1'b1, sleep, - (wr_flags_ce && alu_gie) ? wr_flags : flags }; - assign w_iflags = { 2'b00, ihalt_phase, ifpu_err_flag, - idiv_err_flag, ibus_err_flag, trap, ill_err_i, - break_en, 1'b0, 1'b0, sleep, - (wr_flags_ce && !alu_gie) ? wr_flags : iflags }; - // }}} - - // flags: The user condition codes, Z, C, N, and V - // {{{ - // What value to write? - always @(posedge i_clk) - // If explicitly writing the register itself - if (wr_reg_ce && wr_write_ucc) - flags <= wr_gpreg_vl[3:0]; - // Otherwise if we're setting the flags from an ALU operation - else if (wr_flags_ce && alu_gie) - flags <= wr_flags; - // }}} - - // iflags: The supervisor condition codes, Z, C, N, and V - // {{{ - always @(posedge i_clk) - if (wr_reg_ce && wr_write_scc) - iflags <= wr_gpreg_vl[3:0]; - else if (wr_flags_ce && !alu_gie) - iflags <= wr_flags; - // }}} - - // break_en - // {{{ - // The 'break' enable bit. This bit can only be set from supervisor - // mode. It controls what the CPU does upon encountering a break - // instruction. - // - // The goal, upon encountering a break is that the CPU should stop and - // not execute the break instruction, choosing instead to enter into - // either interrupt mode or halt first. - // if ((break_en) AND (break_instruction)) // user mode or not - // HALT CPU - // else if (break_instruction) // only in user mode - // set an interrupt flag, set the user break bit, - // go to supervisor mode, allow supervisor to step the CPU. - initial break_en = 1'b0; - always @(posedge i_clk) - if (i_reset) - break_en <= 1'b0; - else if ((wr_reg_ce)&&(wr_write_scc)) - break_en <= wr_spreg_vl[CPU_BREAK_BIT]; - // }}} - - // break_pending - // {{{ - generate if (OPT_PIPELINED) - begin : GEN_PENDING_BREAK - reg r_break_pending; - - initial r_break_pending = 1'b0; - always @(posedge i_clk) - if (clear_pipeline || !op_valid) - r_break_pending <= 1'b0; - else if (op_break && !r_break_pending) - r_break_pending <= (!alu_busy)&&(!div_busy) - &&(!fpu_busy)&&(!i_mem_busy) - &&(!wr_reg_ce) && (!step || !stepped); - // else - // No need to clear this here. The break will force the - // pipeline to be cleared above, at which point we can - // clear this register. - // r_break_pending <= 1'b0; - - assign break_pending = r_break_pending; - end else begin : GEN_BREAK_NOPIPE - - assign break_pending = op_break; - -`ifdef FORMAL - always @(*) - if (!gie && user_step && stepped) - assert(!op_break); -`endif - end endgenerate - // }}} - - // o_break - // {{{ - // - // This is a 12-input equation on an output. Can this be - // simplified any? What happens if o_break is set? Will it ever - // clear on its own, or does it require a write to the debug port? - assign o_break = (break_en || !op_gie)&&(break_pending) - &&(!clear_pipeline) - ||(ill_err_i) - ||((!alu_gie)&&(i_bus_err)) - ||((!alu_gie)&&(div_error)) - ||((!alu_gie)&&(fpu_error)) - ||((!alu_gie)&&(alu_illegal)&&(!clear_pipeline)); - -`ifdef FORMAL - // Can I assume that, if break_pending is true, that we're either - // in supervisor mode, or that break_en is set? If so, can I - // simplify the calculation above? - // - // No, because once break_pending is set, the supervisor can then - // adjust break_en without adjusting the external break. - // - // always @(*) - // if (break_pending) - // assert(!op_gie || break_en); - - always @(*) - if (!alu_gie && alu_illegal && !clear_pipeline) - assert(!master_ce); - - // Do I need to break on the last condition above? - always @(posedge i_clk) - if (!i_reset && $past(!i_reset && !alu_gie && alu_illegal - && !clear_pipeline && !dbgv)) - assert(ill_err_i); - - always @(*) - if (!i_reset) - assert(!dbgv || !alu_valid); -`endif - // }}} - - // sleep - // {{{ - // The sleep register. Setting the sleep register causes the CPU to - // sleep until the next interrupt. Setting the sleep register within - // interrupt mode causes the processor to halt until a reset. This is - // a panic/fault halt. The trick is that you cannot be allowed to - // set the sleep bit and switch to supervisor mode in the same - // instruction: users are not allowed to halt the CPU. - initial sleep = 1'b0; - generate if (OPT_USERMODE) - begin : GEN_SLEEP - // {{{ - initial sleep = 1'b0; - always @(posedge i_clk) - if (i_reset || w_switch_to_interrupt) - // Wake up on any reset or any switch to supervisor mode - sleep <= 1'b0; - else if (wr_reg_ce && wr_write_cc) - begin - // - // !GIE && SLEEP ==> halted - // GIE && SLEEP ==> sleep until an interrupt - // - if (!alu_gie) - // In supervisor mode, we have no protections. - // The supervisor can set the sleep bit however - // he wants. Well ... not quite. Switching to - // user mode and sleep mode should only be - // possible if the interrupt flag isn't set. - // Hence, if an interrupt is pending, then any - // WAIT instruction essentially becomes a NOOP. - // - // Thus: if (i_interrupt) - // &&(wr_spreg_vl[GIE]) - // don't set the sleep bit - // otherwise however it would o.w. be set - sleep <= (wr_spreg_vl[CPU_SLEEP_BIT]) - &&((!i_interrupt) - ||(!wr_spreg_vl[CPU_GIE_BIT])); - else if (wr_spreg_vl[CPU_GIE_BIT]) - // In user mode, however, you can only set the - // sleep mode while remaining in user mode. - // You can't switch to sleep mode *and* - // supervisor mode at the same time, lest you - // halt the CPU. - sleep <= wr_spreg_vl[CPU_SLEEP_BIT]; - end - // }}} - end else begin : GEN_NO_USERMODE_SLEEP - // {{{ - // Even with no user mode, we still want to implement a sleep - // instruction. Here, we create an r_sleep_is_halt to - // differentiate between the halt and the sleep condition - // so that the supervisor can still cause the CPU to sleep. - // - reg r_sleep_is_halt; - initial r_sleep_is_halt = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_sleep_is_halt <= 1'b0; - else if (wr_reg_ce && wr_write_cc - && wr_spreg_vl[CPU_SLEEP_BIT] - && !wr_spreg_vl[CPU_GIE_BIT]) - // Setting SLEEP and supervisor mode at the same time - // halts the CPU. Halts can only be set here. - // They can only be cleared on reset. - r_sleep_is_halt <= 1'b1; - - // Trying to switch to user mode, either via a WAIT or an RTU - // instruction will cause the CPU to sleep until an interrupt, - // in the NO-USERMODE build. - always @(posedge i_clk) - if (i_reset || (i_interrupt && !r_sleep_is_halt)) - sleep <= 1'b0; - else if ((wr_reg_ce)&&(wr_write_cc) - &&(wr_spreg_vl[CPU_GIE_BIT])) - sleep <= 1'b1; - // }}} - end endgenerate - // }}} - - // step : debug single-step control - // {{{ - initial user_step = 1'b0; - always @(posedge i_clk) - if (i_reset || !OPT_USERMODE) - user_step <= 1'b0; - else if ((wr_reg_ce)&&(!alu_gie)&&(wr_write_ucc)) - // The supervisor can adjust whether or not we are stepping - // the user mode process. This bit does not automatically - // clear, but can always be written while in supervisor mode. - user_step <= wr_spreg_vl[CPU_STEP_BIT]; - - assign step = user_step && gie; - // }}} - - // o_clken - // {{{ - generate if (!OPT_CLKGATE) - begin : NO_CLOCK_GATE - - assign w_clken = 1'b1; - assign o_clken = 1'b1; - - end else begin : GEN_CLOCK_GATE - reg r_clken; - - // Actual clock gating signal - // - // = r_clken || (i_interrupt&&!i_halt) || i_dbg_we - // - initial r_clken = !OPT_START_HALTED; - always @(posedge i_clk) - if (i_reset) - r_clken <= !OPT_START_HALTED; - else if (i_halt && r_halted && (!OPT_DBGPORT || !i_dbg_we)) - r_clken <= i_mem_busy || !i_halt || o_mem_ce; - else if (!i_halt&& (!sleep || i_interrupt || pending_interrupt)) - r_clken <= 1'b1; - else // if (sleep || i_halt) - begin - r_clken <= 1'b0; - - // If we are in the middle of a lock operation, then - // don't shut the clock off - if (o_bus_lock) - r_clken <= 1'b1; - - // If we are in between two compressed instructions - // from the same word, then don't disable the clock - if (alu_phase) - r_clken <= 1'b1; - - // Don't shut the clock off if we are still busy with - // any previous operation(s) - if (i_mem_busy || o_mem_ce - || alu_busy || div_busy || fpu_busy - || wr_reg_ce ||(OPT_DBGPORT && i_dbg_we) - || i_bus_err) - r_clken <= 1'b1; - - if (i_halt && !r_halted) - r_clken <= 1'b1; - - // Should we wait for a valid PF result before halting? - // if (!i_pf_valid) r_clken <= 1'b1; - // if (!op_valid && !dcd_illegal) r_clken <= 1'b1; - // if (!dcd_valid && !i_pf_illegal) r_clken <= 1'b1; - end - - assign w_clken = r_clken; - - // Wake up on interrupts, debug write requests, or the raising - // of the halt flag if we're not sleeping. - assign o_clken = r_clken || (OPT_DBGPORT && i_dbg_we) - || i_clear_cache - || (!i_halt && (i_interrupt || !sleep)); - end endgenerate - // }}} - - // gie, switch_to_interrupt, release_from_interrupt, r_user_stepped - // {{{ - // The GIE register. Only interrupts can disable the interrupt register - generate if (OPT_USERMODE) - begin : GEN_PENDING_INTERRUPT - // {{{ - reg r_pending_interrupt; - reg r_user_stepped; - - // r_user_stepped is used to make certain that we stop a - // user task once a full instruction has been accomplished. - initial r_user_stepped = 1'b0; - always @(posedge i_clk) - if (i_reset || !gie || !user_step) - r_user_stepped <= 1'b0; - // else if(w_switch_to_interrupt) - // While this is technically what we want, we can wait - // a clock cycle to speed up the CPU by not depending upon - // the complex w_switch_to_interrupt calculation here - // r_user_stepped <= 1'b0; - else if (op_valid && !op_phase && !op_lock && last_lock_insn - && (adf_ce_unconditional || mem_ce)) - r_user_stepped <= 1'b1; - - initial r_pending_interrupt = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_pending_interrupt <= 1'b0; - else if (!gie || w_switch_to_interrupt) - r_pending_interrupt <= 1'b0; - else if (clear_pipeline && (!user_step || !stepped)) - r_pending_interrupt <= 1'b0; - else begin - if (i_interrupt) - r_pending_interrupt <= 1'b1; - - if (break_pending) - r_pending_interrupt <= 1'b1; - - if (adf_ce_unconditional && op_illegal) - r_pending_interrupt <= 1'b1; - - if (((!alu_busy && !i_mem_busy && !div_busy && !fpu_busy) - || wr_reg_ce) && user_step && stepped) - r_pending_interrupt <= 1'b1; - end - - assign pending_interrupt = r_pending_interrupt && !i_halt; - - - assign w_switch_to_interrupt = (gie)&&( - // On interrupt (obviously) - ((pending_interrupt) - &&(!alu_phase)&&(!o_bus_lock)&&(!i_mem_busy)) - // - // On division by zero. If the divide isn't - // implemented, div_valid and div_error will be short - // circuited and that logic will be bypassed - ||(div_error) - // - // Same thing on a floating point error. Note that - // fpu_error must *never* be set unless fpu_valid is - // also set as well, else this will fail. - ||(fpu_error) - // - // - ||(i_bus_err) - // - // If we write to the CC register - ||((wr_reg_ce)&&(!wr_spreg_vl[CPU_GIE_BIT]) - &&(wr_reg_id[4])&&(wr_write_cc)) - ); - assign w_release_from_interrupt = (!gie)&&(!i_interrupt) - // Then if we write the sCC register - &&(((wr_reg_ce)&&(wr_spreg_vl[CPU_GIE_BIT]) - &&(wr_write_scc)) - ); - -`ifdef FORMAL - always @(posedge i_clk) - if (r_pending_interrupt && gie && !clear_pipeline) - assert(i_interrupt || user_step || alu_illegal - || ill_err_u || break_pending); - - always @(posedge i_clk) - if (f_past_valid && $past(user_step && stepped && !o_bus_lock - && !o_dbg_stall)) - assert(!gie || r_pending_interrupt); -`endif - assign stepped = r_user_stepped; - // }}} - end else begin : NO_PENDING_INTS - // {{{ - assign w_switch_to_interrupt = 1'b0; - assign w_release_from_interrupt = 1'b0; - assign pending_interrupt = 1'b0; - assign stepped = 1'b0; - - // Verilator lint_off UNUSED - wire unused_int_signals; - assign unused_int_signals = &{ 1'b0, last_lock_insn }; - // Verilator lint_on UNUSED - // }}} - end endgenerate - - generate if (OPT_USERMODE) - begin : SET_GIE - - reg r_gie; - - initial r_gie = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_gie <= 1'b0; // Supervisor mode - else if (w_switch_to_interrupt) - r_gie <= 1'b0; // Supervisor mode - else if (w_release_from_interrupt) - r_gie <= 1'b1; // User mode - - assign gie = r_gie; - end else begin : ZERO_GIE - - assign gie = 1'b0; - - end endgenerate - // }}} - - // trap, ubreak - // {{{ - generate if (OPT_USERMODE) - begin : SET_TRAP_N_UBREAK - // {{{ - - reg r_trap; - reg r_ubreak; - - // A trap is generated when the user writes to the CC - // register to clear the GIE bit. This is how the supervisor - // can tell that supervisor mode was entered by a request from - // usermode. - initial r_trap = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(w_release_from_interrupt)) - r_trap <= 1'b0; - else if (wr_reg_ce && wr_write_ucc) - begin - if (!alu_gie) - // The trap bit can only be cleared by the - // supervisor. - r_trap <= (r_trap)&&(wr_spreg_vl[CPU_TRAP_BIT]); - else if (!wr_spreg_vl[CPU_GIE_BIT]) // && alu_gie - // Execute a trap - r_trap <= !dbgv; - end - - // A user break is an indication of an exception. Something - // went wrong. When entering supervisor mode, if this bit - // is set the supervisor then knows something went wrong in - // userspace that needs to be looked into. - initial r_ubreak = 1'b0; - always @(posedge i_clk) - if (i_reset || w_release_from_interrupt) - r_ubreak <= 1'b0; - else if (op_gie && break_pending && w_switch_to_interrupt) - // Breaks are set when a BREAK instruction is accepted - // for execution from the OP stage, *and* when in user - // mode - r_ubreak <= 1'b1; - else if ((!alu_gie || dbgv)&&(wr_reg_ce)&&(wr_write_ucc)) - // Allow the supervisor or debug port to clear this - // register--but not to set it - r_ubreak <= (ubreak)&&(wr_spreg_vl[CPU_BREAK_BIT]); - - assign trap = r_trap; - assign ubreak = r_ubreak; - // }}} - end else begin : NO_USERTRAP - - assign trap = 1'b0; - assign ubreak = 1'b0; - - end endgenerate - // }}} - - // ill_err_i, ill_err_u: Illegal instruction flags - // {{{ - initial ill_err_i = 1'b0; - always @(posedge i_clk) - if (i_reset) - ill_err_i <= 1'b0; - else if (dbgv && wr_write_scc) - // Only the debug interface (or a CPU reset) can clear the - // supervisor's illegal instruction flag - ill_err_i <= (ill_err_i)&&(wr_spreg_vl[CPU_ILL_BIT]); - else if (!alu_gie && alu_illegal && !clear_pipeline) - // The supervisor's illegal instruction flag is set in - // supervisor (not user) mode, on trying to execute the illegal - // instruction - ill_err_i <= 1'b1; - - generate if (OPT_USERMODE) - begin : SET_USER_ILLEGAL_INSN - - reg r_ill_err_u; - - // - // The user's illegal instruction exception flag. Used and - // cleared by the supervisor. - // - - initial r_ill_err_u = 1'b0; - always @(posedge i_clk) - // The bit is automatically cleared on release from interrupt - // or reset - if (i_reset || w_release_from_interrupt) - r_ill_err_u <= 1'b0; - else if ((!alu_gie || dbgv)&&(wr_reg_ce)&&(wr_write_ucc)) - // Either the supervisor or the debugger can clear this - // bit. (Neither can set it) - r_ill_err_u <=((ill_err_u)&&(wr_spreg_vl[CPU_ILL_BIT])); - else if (alu_gie && alu_illegal && !clear_pipeline) - // This flag is set if the CPU ever attempts to execute - // an illegal instruction while in user mode. - r_ill_err_u <= 1'b1; - - assign ill_err_u = r_ill_err_u; - - end else begin : NO_USER_ILL - - assign ill_err_u = 1'b0; - - end endgenerate - // }}} - - // ibus_err_flag, ubus_err_flag : Bus error flags - // {{{ - // Supervisor/interrupt bus error flag -- this will crash the CPU if - // ever set. - initial ibus_err_flag = 1'b0; - always @(posedge i_clk) - if (i_reset) - ibus_err_flag <= 1'b0; - else if ((dbgv)&&(wr_write_scc)) - ibus_err_flag <= (ibus_err_flag)&&(wr_spreg_vl[CPU_BUSERR_BIT]); - else if ((i_bus_err)&&(!alu_gie)) - ibus_err_flag <= 1'b1; - - // User bus error flag -- if ever set, it will cause an interrupt to - // supervisor mode. - generate if (OPT_USERMODE) - begin : SET_USER_BUSERR - - reg r_ubus_err_flag; - - initial r_ubus_err_flag = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(w_release_from_interrupt)) - r_ubus_err_flag <= 1'b0; - else if (((!alu_gie)||(dbgv))&&(wr_reg_ce)&&(wr_write_ucc)) - r_ubus_err_flag <= (ubus_err_flag)&&(wr_spreg_vl[CPU_BUSERR_BIT]); - else if ((i_bus_err)&&(alu_gie)) - r_ubus_err_flag <= 1'b1; - - assign ubus_err_flag = r_ubus_err_flag; - end else begin : NO_USER_BUSERR - - assign ubus_err_flag = 1'b0; - - end endgenerate - // }}} - - // idiv_err_flag, udiv_err_flag : Divide by zero error flags - // {{{ - generate if (OPT_DIV != 0) - begin : DIVERR - // {{{ - reg r_idiv_err_flag; - - // Supervisor/interrupt divide (by zero) error flag -- this will - // crash the CPU if ever set. This bit is thus available for us - // to be able to tell if/why the CPU crashed. - initial r_idiv_err_flag = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_idiv_err_flag <= 1'b0; - else if ((dbgv)&&(wr_write_scc)) - r_idiv_err_flag <= (r_idiv_err_flag)&&(wr_spreg_vl[CPU_DIVERR_BIT]); - else if ((div_error)&&(!alu_gie)) - r_idiv_err_flag <= 1'b1; - - assign idiv_err_flag = r_idiv_err_flag; - - if (OPT_USERMODE) - begin : USER_DIVERR - - reg r_udiv_err_flag; - - // User divide (by zero) error flag -- if ever set, it will - // cause a sudden switch interrupt to supervisor mode. - initial r_udiv_err_flag = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(w_release_from_interrupt)) - r_udiv_err_flag <= 1'b0; - else if (((!alu_gie)||(dbgv))&&(wr_reg_ce) - &&(wr_write_ucc)) - r_udiv_err_flag <= (r_udiv_err_flag)&&(wr_spreg_vl[CPU_DIVERR_BIT]); - else if ((div_error)&&(alu_gie)) - r_udiv_err_flag <= 1'b1; - - assign udiv_err_flag = r_udiv_err_flag; - end else begin : NO_USER_DIVERR - assign udiv_err_flag = 1'b0; - end - // }}} - end else begin : NO_DIVERR - // {{{ - assign idiv_err_flag = 1'b0; - assign udiv_err_flag = 1'b0; - // }}} - end endgenerate - // }}} - - // ifpu_err_flag, ufpu_err_flag : Floating point error flag(s) - // {{{ - generate if (IMPLEMENT_FPU !=0) - begin : FPUERR - // {{{ - // Supervisor/interrupt floating point error flag -- this will - // crash the CPU if ever set. - reg r_ifpu_err_flag, r_ufpu_err_flag; - initial r_ifpu_err_flag = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_ifpu_err_flag <= 1'b0; - else if ((dbgv)&&(wr_write_scc)) - r_ifpu_err_flag <= (r_ifpu_err_flag)&&(wr_spreg_vl[CPU_FPUERR_BIT]); - else if ((fpu_error)&&(fpu_valid)&&(!alu_gie)) - r_ifpu_err_flag <= 1'b1; - // User floating point error flag -- if ever set, it will cause - // a sudden switch interrupt to supervisor mode. - initial r_ufpu_err_flag = 1'b0; - always @(posedge i_clk) - if ((i_reset)&&(w_release_from_interrupt)) - r_ufpu_err_flag <= 1'b0; - else if (((!alu_gie)||(dbgv))&&(wr_reg_ce) - &&(wr_write_ucc)) - r_ufpu_err_flag <= (r_ufpu_err_flag)&&(wr_spreg_vl[CPU_FPUERR_BIT]); - else if ((fpu_error)&&(alu_gie)&&(fpu_valid)) - r_ufpu_err_flag <= 1'b1; - - assign ifpu_err_flag = r_ifpu_err_flag; - assign ufpu_err_flag = r_ufpu_err_flag; - // }}} - end else begin : NO_FPUERR - // {{{ - assign ifpu_err_flag = 1'b0; - assign ufpu_err_flag = 1'b0; - // }}} - end endgenerate - // }}} - - // ihalt_phase, uhalt_phase : If an instruction was broken when halting - // {{{ - generate if (OPT_CIS) - begin : GEN_IHALT_PHASE - reg r_ihalt_phase; - - initial r_ihalt_phase = 0; - always @(posedge i_clk) - if (i_reset) - r_ihalt_phase <= 1'b0; - else if ((!alu_gie)&&(alu_pc_valid)&&(!clear_pipeline)) - r_ihalt_phase <= alu_phase; - - assign ihalt_phase = r_ihalt_phase; - end else begin : GEN_IHALT_PHASE - - assign ihalt_phase = 1'b0; - - end endgenerate - - generate if ((!OPT_CIS) || (!OPT_USERMODE)) - begin : GEN_UHALT_PHASE - - assign uhalt_phase = 1'b0; - - end else begin : GEN_UHALT_PHASE - - reg r_uhalt_phase; - - initial r_uhalt_phase = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(w_release_from_interrupt)) - r_uhalt_phase <= 1'b0; - else if ((alu_gie)&&(alu_pc_valid)) - r_uhalt_phase <= alu_phase; - else if ((!alu_gie)&&(wr_reg_ce)&&(wr_write_pc) - &&(wr_reg_id[4])) - r_uhalt_phase <= wr_spreg_vl[1]; - - assign uhalt_phase = r_uhalt_phase; - - end endgenerate - // }}} - - // ipc, upc: Program counters - // {{{ - // - // Write backs to the PC register, and general increments of it - // We support two: upc and ipc. If the instruction is normal, - // we increment upc, if interrupt level we increment ipc. If - // the instruction writes the PC, we write whichever PC is appropriate. - // - // Do we need to all our partial results from the pipeline? - // What happens when the pipeline has gie and !gie instructions within - // it? Do we clear both? What if a gie instruction tries to clear - // a non-gie instruction? - - // upc - generate if (OPT_USERMODE) - begin : SET_USER_PC - // {{{ - reg [(AW+1):0] r_upc; - - always @(posedge i_clk) - if ((wr_reg_ce)&&(wr_reg_id[4])&&(wr_write_pc)) - r_upc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; - else if ((alu_gie)&& - (((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal)) - ||(mem_pc_valid))) - r_upc <= alu_pc; - - assign upc = r_upc; - // }}} - end else begin : NO_UPC - // {{{ - assign upc = {(AW+2){1'b0}}; - // }}} - end endgenerate - - // ipc - // {{{ - initial ipc = { RESET_BUS_ADDRESS, 2'b00 }; - always @(posedge i_clk) - if (i_reset) - ipc <= { RESET_BUS_ADDRESS, 2'b00 }; - else if ((wr_reg_ce)&&(!wr_reg_id[4])&&(wr_write_pc)) - ipc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; - else if ((!alu_gie)&&(!alu_phase)&& - (((alu_pc_valid)&&(!clear_pipeline)&&(!alu_illegal)) - ||(mem_pc_valid))) - ipc <= alu_pc; - // }}} - // }}} - - // pf_pc : the program counter used by the pre-fetch - // {{{ - - // pfpcset, pfpcsrc - // {{{ - always @(*) - begin - pfpcset = 0; - pfpcsrc = 0; - if (i_reset) - begin - pfpcsrc = 0; - pfpcset = 1; - end else if ((dbgv)&&(wr_reg_ce)&&(wr_reg_id[4] == gie && wr_write_pc)) - begin - pfpcsrc = 1; // spreg - pfpcset = 1; - end else if ((w_switch_to_interrupt) - ||((!gie)&&((o_clear_icache)||(dbg_clear_pipe)))) - begin - pfpcsrc = 2; // ipc - pfpcset = 1; - end else if ((w_release_from_interrupt)||((gie)&&((o_clear_icache)||(dbg_clear_pipe)))) - begin - pfpcsrc = 3; // upc - pfpcset = 1; - end else if ((wr_reg_ce)&&(wr_reg_id[4] == gie && wr_write_pc)) - begin - pfpcsrc = 1; // spreg - pfpcset = 1; - end else if ((dcd_early_branch_stb)&&(!clear_pipeline)) - begin - pfpcsrc = 4; // branch - pfpcset = 1; - end else if ((new_pc)||(o_pf_ready&& i_pf_valid)) - begin - pfpcsrc = 5; // PC increment - pfpcset = 1; - end - end - // }}} - - initial pf_pc = { RESET_BUS_ADDRESS, 2'b00 }; - always @(posedge i_clk) - if (pfpcset) - case(pfpcsrc) - 3'b000: pf_pc <= { RESET_BUS_ADDRESS, 2'b00 }; - 3'b001: pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; - 3'b010: pf_pc <= { ipc[(AW+1):2], 2'b00 }; - 3'b011: pf_pc <= { upc[(AW+1):2], 2'b00 }; - 3'b100: pf_pc <= { dcd_branch_pc[AW+1:2] + 1'b1, 2'b00 }; - 3'b101: pf_pc <= { pf_pc[(AW+1):2] + 1'b1, 2'b00 }; - default: pf_pc <= { RESET_BUS_ADDRESS, 2'b00 }; - endcase -/* - if (i_reset) - pf_pc <= { RESET_BUS_ADDRESS, 2'b00 }; - else if ((dbg_clear_pipe)&&(wr_reg_ce)&&(wr_write_pc)) - pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; - else if ((w_switch_to_interrupt) - ||((!gie)&&((o_clear_icache)||(dbg_clear_pipe)))) - pf_pc <= { ipc[(AW+1):2], 2'b00 }; - else if ((w_release_from_interrupt)||((gie)&&((o_clear_icache)||(dbg_clear_pipe)))) - pf_pc <= { upc[(AW+1):2], 2'b00 }; - else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) - pf_pc <= { wr_spreg_vl[(AW+1):2], 2'b00 }; - else if ((dcd_early_branch_stb)&&(!clear_pipeline)) - pf_pc <= { dcd_branch_pc[AW+1:2] + 1'b1, 2'b00 }; - else if ((new_pc)||((!pf_stalled)&&(i_pf_valid))) - pf_pc <= { pf_pc[(AW+1):2] + 1'b1, 2'b00 }; -*/ - // }}} - - initial last_write_to_cc = 1'b0; - always @(posedge i_clk) - if (i_reset) - last_write_to_cc <= 1'b0; - else - last_write_to_cc <= (wr_reg_ce)&&(wr_write_cc); - assign cc_write_hold = (wr_reg_ce && wr_write_cc)||(last_write_to_cc); - - // o_clear_icache - // {{{ - // If we aren't pipelined, or equivalently if we have no cache, these - // instructions will get quietly (or not so quietly) ignored by the - // optimizer. - initial r_clear_icache = 1'b1; - always @(posedge i_clk) - if (i_reset) - r_clear_icache <= 1'b0; - else if (i_clear_cache && !o_dbg_stall) - r_clear_icache <= 1'b1; - else if ((wr_reg_ce)&&(wr_write_scc)) - r_clear_icache <= wr_spreg_vl[CPU_CLRICACHE_BIT]; - else - r_clear_icache <= 1'b0; - - assign o_clear_icache = r_clear_icache; - // }}} - - // o_clear_dcache - // {{{ - generate if (OPT_DCACHE) - begin : CLEAR_DCACHE - reg r_clear_dcache; - - initial r_clear_dcache = 1'b1; - always @(posedge i_clk) - if (i_reset) - r_clear_dcache <= 1'b0; - else if (i_clear_cache && !o_dbg_stall) - r_clear_dcache <= 1'b1; - else if ((wr_reg_ce)&&(wr_write_scc)) - r_clear_dcache <= wr_spreg_vl[CPU_CLRDCACHE_BIT]; - else - r_clear_dcache <= 1'b0; - - assign o_clear_dcache = r_clear_dcache; - end else begin : NOCLEAR_DCACHE - - assign o_clear_dcache = 1'b0; - - end endgenerate - // }}} - - // new_pc : does the Prefetch need to clear the pipeline and start over? - // {{{ - initial new_pc = 1'b1; - always @(posedge i_clk) - if ((i_reset)||(o_clear_icache)||(dbg_clear_pipe)) - new_pc <= 1'b1; - else if (w_switch_to_interrupt) - new_pc <= 1'b1; - else if (w_release_from_interrupt) - new_pc <= 1'b1; - // else if ((wr_reg_ce)&&(wr_reg_id[4] == gie)&&(wr_write_pc)) - // Can't check for *this* PC here, since a user PC might be - // loaded in the pipeline and hence rewritten. Thus, while - // I hate to do it, we'll need to clear the pipeline on any - // PC write - else if ((wr_reg_ce)&&(alu_gie == wr_reg_id[4])&&(wr_write_pc)) - new_pc <= 1'b1; - else - new_pc <= 1'b0; - // }}} - - // - // The debug write-back interface - // {{{ - - // debug_pc - // {{{ - generate if (OPT_USERMODE) - begin : DBGPC_FULL - // {{{ - always @(*) - begin - debug_pc = 0; - if (!OPT_DBGPORT) - begin - // Empty block--if there's no debug port, we'll - // leave this valu at zero to reduce power - end else if (i_dbg_rreg[4]) - // User mode - debug_pc[(AW+1):0] - = { upc[(AW+1):2], uhalt_phase, 1'b0 }; - else - // Supervisor mode - debug_pc[(AW+1):0] - = { ipc[(AW+1):2], ihalt_phase, 1'b0 }; - end - // }}} - end else begin : DBGPC_NO_USER - // {{{ - always @(*) - begin - debug_pc = 0; - if (OPT_DBGPORT) - debug_pc[(AW+1):0] = { ipc[AW+1:2], ihalt_phase, 1'b0 }; - end - // }}} - end endgenerate - // }}} - - // o_dbg_reg - // {{{ - generate if (!OPT_DBGPORT) - begin : NO_DBGPORT - - assign o_dbg_reg = 0; - - // verilator lint_off UNUSED - wire unused_dbgport; - assign unused_dbgport = &{ 1'b0, i_dbg_rreg, debug_pc }; - // verilator lint_on UNUSED - - end else if (OPT_USERMODE) - begin : SETDBG - // {{{ - reg [31:0] pre_dbg_reg, r_dbg_reg; - - if (OPT_DISTRIBUTED_REGS) - begin : GEN_DISTRIBUTED_RAM_DBG - // {{{ - always @(*) - pre_dbg_reg = regset[i_dbg_rreg]; - - always @(posedge i_clk) - begin - r_dbg_reg <= pre_dbg_reg; - if (i_dbg_rreg[3:0] == CPU_PC_REG) - r_dbg_reg <= debug_pc; - else if (i_dbg_rreg[3:0] == CPU_CC_REG) - begin - r_dbg_reg[15:0] <= (i_dbg_rreg[4]) - ? w_uflags : w_iflags; - r_dbg_reg[31:23] <= w_cpu_info; - r_dbg_reg[CPU_GIE_BIT] <= i_dbg_rreg[4]; - end - end - - assign o_dbg_reg = r_dbg_reg; - // }}} - end else begin : GEN_BKRAM_DBG - // {{{ - reg [1:0] dbg_reg_sel; - reg [31:0] pre_dbg_special; - - // First clock - - always @(posedge i_clk) - begin - dbg_reg_sel[1] <= (i_dbg_rreg[3:1] == 3'h7); - dbg_reg_sel[0] <= i_dbg_rreg[0]; - end - - always @(posedge i_clk) - pre_dbg_reg <= regset[i_dbg_rreg]; - - always @(posedge i_clk) - if (i_dbg_rreg[0]) - pre_dbg_special <= debug_pc; - else begin - pre_dbg_special <= 0; - pre_dbg_special[15:0] <= (i_dbg_rreg[4]) - ? w_uflags : w_iflags; - pre_dbg_special[31:23] <= w_cpu_info; - pre_dbg_special[CPU_GIE_BIT] <= i_dbg_rreg[4]; - end - - // Second clock - - always @(posedge i_clk) - if (!dbg_reg_sel[1]) - r_dbg_reg <= pre_dbg_reg; - else if (dbg_reg_sel[0]) - r_dbg_reg <= pre_dbg_special; - else begin - r_dbg_reg <= pre_dbg_special; - r_dbg_reg[22:16] <= pre_dbg_reg[22:16]; - end - - - assign o_dbg_reg = r_dbg_reg; - // }}} - end - // }}} - end else begin : NO_USER_SETDBG - // {{{ - reg [31:0] r_dbg_reg, pre_dbg_reg; - - if (OPT_DISTRIBUTED_REGS) - begin : GEN_DISTRIBUTED_RAM_DBG - - always @(*) - pre_dbg_reg = regset[i_dbg_rreg[3:0]]; - - always @(posedge i_clk) - begin - r_dbg_reg <= pre_dbg_reg; - if (i_dbg_rreg[3:0] == CPU_PC_REG) - r_dbg_reg <= debug_pc; - else if (i_dbg_rreg[3:0] == CPU_CC_REG) - begin - r_dbg_reg[15:0] <= w_iflags; - r_dbg_reg[31:23] <= w_cpu_info; - r_dbg_reg[CPU_GIE_BIT] <= 1'b0; - end - end - end else begin : GEN_BKRAM_DBG - // {{{ - reg [1:0] dbg_reg_sel; - reg [31:0] pre_dbg_special; - - // First clock - - always @(posedge i_clk) - begin - dbg_reg_sel[1] <= (i_dbg_rreg[3:1] == 3'h7); - dbg_reg_sel[0] <= i_dbg_rreg[0]; - end - - always @(posedge i_clk) - pre_dbg_reg <= regset[i_dbg_rreg[3:0]]; - - always @(posedge i_clk) - if (i_dbg_rreg[0]) - pre_dbg_special <= debug_pc; - else begin - pre_dbg_special <= 0; - pre_dbg_special[15:0] <= w_iflags; - pre_dbg_special[31:23] <= w_cpu_info; - pre_dbg_special[CPU_GIE_BIT] <= 1'b0; - end - - // Second clock - - always @(posedge i_clk) - if (!dbg_reg_sel[1]) - r_dbg_reg <= pre_dbg_reg; - else if (dbg_reg_sel[0]) - r_dbg_reg <= pre_dbg_special; - else begin - r_dbg_reg <= pre_dbg_special; - r_dbg_reg[22:16] <= pre_dbg_reg[22:16]; - end - - assign o_dbg_reg = r_dbg_reg; - // }}} - end - - assign o_dbg_reg = r_dbg_reg; - // }}} - end endgenerate - // }}} - - always @(posedge i_clk) - o_dbg_cc <= { i_bus_err, gie, sleep }; - - // r_halted - // {{{ - generate if (OPT_PIPELINED) - begin : GEN_HALT_PIPELINED - // {{{ - initial r_halted = OPT_START_HALTED; - always @(posedge i_clk) - if (i_reset) - r_halted <= OPT_START_HALTED; - else if (!i_halt) - r_halted <= 1'b0; - else if (r_halted) - r_halted <= 1'b1; - else - r_halted <= (!alu_phase)&&(!o_bus_lock)&&( - // To be halted, any long lasting instruction - // must be completed. - (i_pf_valid)&&(!i_mem_busy)&&(!alu_busy) - &&(!div_busy)&&(!fpu_busy) - // Operations must either be valid, or illegal - &&((dcd_valid)||(dcd_illegal))); - // }}} - end else begin : GEN_HALT_NOPIPE - // {{{ - initial r_halted = OPT_START_HALTED; - always @(posedge i_clk) - if (i_reset) - r_halted <= OPT_START_HALTED; - else if (!i_halt) - r_halted <= 1'b0; - else if (r_halted) - r_halted <= 1'b1; - else - r_halted <= (!alu_phase) - // To be halted, any long lasting instruction - // must be completed. - &&(i_pf_valid)&&(!i_mem_busy)&&(!alu_busy) - &&(!div_busy)&&(!fpu_busy); - // }}} - end endgenerate - // }}} - - // o_dbg_stall - // {{{ - initial r_dbg_stall = 1'b1; - - always @(posedge i_clk) - if (i_reset) - r_dbg_stall <= 1'b1; - else if (!r_halted || (wr_reg_ce && wr_reg_id[3:1] == 3'h7)) - r_dbg_stall <= 1'b1; - else - r_dbg_stall <= (OPT_DBGPORT && i_dbg_we && !o_dbg_stall); - - assign o_dbg_stall = OPT_DBGPORT && (!r_halted || r_dbg_stall); - // }}} - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Accounting outputs - // {{{ - - // - // - // Produce accounting outputs: Account for any CPU stalls, so we can - // later evaluate how well we are doing. - // - // - assign o_op_stall = (master_ce)&&(op_stall); - assign o_pf_stall = (master_ce)&&(!i_pf_valid); - assign o_i_count = (alu_pc_valid)&&(!clear_pipeline); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The debug scope output - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_TRACE_PORT) - begin : GEN_DEBUG_PORT - localparam [1:0] - DBGSRC_FLAGS = 2'b00, - DBGSRC_WRITEBACK = 2'b01, - DBGSRC_JUMP = 2'b10; - - reg [31:0] r_debug; - reg debug_trigger, dbg_mem_we; - wire [27:0] debug_flags; - reg [1:0] dbgsrc; - // Verilator lint_off UNUSED - wire [27:0] dbg_pc, dbg_wb_addr; - // Verilator lint_on UNUSED - - - initial debug_trigger = 1'b0; - always @(posedge i_clk) - debug_trigger <= (!i_halt)&&(o_break); - - always @(posedge i_clk) - if (o_mem_ce) - dbg_mem_we <= o_mem_op[0]; - - assign debug_flags = { master_ce, i_halt, o_break, sleep, - gie, ibus_err_flag, trap, ill_err_i, - o_clear_icache, i_pf_valid, i_pf_illegal, dcd_ce, - dcd_valid, dcd_stalled, op_ce, op_valid, - op_pipe, alu_ce, alu_busy, alu_wR, - alu_illegal, alu_wF, mem_ce, dbg_mem_we, - i_mem_busy, i_mem_pipe_stalled, (new_pc), (dcd_early_branch) }; - - if (AW-1 < 27) - begin : GEN_SHORT_DBGPC - assign dbg_pc[(AW-1):0] = pf_pc[(AW+1):2]; - assign dbg_pc[27:AW] = 0; - - assign dbg_wb_addr[(AW-1):0] = 0; - assign dbg_wb_addr[27:AW] = 0; - end else // if (AW-1 >= 27) - begin : GEN_WIDE_DBGPC - assign dbg_pc[27:0] = pf_pc[29:2]; - assign dbg_wb_addr = 0; - end - - always @(posedge i_clk) - begin - dbgsrc <= 0; - if ((i_halt)||(!master_ce)||(debug_trigger)||(o_break)) - dbgsrc <= DBGSRC_FLAGS; - else if ((i_mem_valid)||((!clear_pipeline)&&(!alu_illegal) - &&(((alu_wR)&&(alu_valid)) - ||(div_valid)||(fpu_valid)))) - dbgsrc <= DBGSRC_WRITEBACK; - else if (clear_pipeline) - dbgsrc <= DBGSRC_JUMP; - else - dbgsrc <= DBGSRC_FLAGS; - end - - always @(posedge i_clk) - casez(dbgsrc) - DBGSRC_FLAGS: - r_debug <= { debug_trigger, 3'b101, - debug_flags }; - DBGSRC_WRITEBACK: - r_debug <= { debug_trigger, 1'b0, - wr_reg_id[3:0], wr_gpreg_vl[25:0]}; - DBGSRC_JUMP: r_debug <= { debug_trigger, 3'b100, - dbg_pc }; - default: r_debug <= 32'h0; - endcase - - assign o_debug = r_debug; - - end else begin : NO_TRACE_PORT - - assign o_debug = 32'h0; - - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // (Optional) Hardware profiler support - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_PROFILER) - begin : GEN_PROFILER - reg prof_stb; - reg [AW+1:0] prof_addr; - reg [31:0] prof_ticks; - - initial prof_stb = 1'b0; - always @(posedge i_clk) - if (i_reset || clear_pipeline) - prof_stb <= 1'b0; - else - prof_stb <= (alu_pc_valid || mem_pc_valid); - - initial prof_addr = 0; - always @(posedge i_clk) - if (i_reset || clear_pipeline) - prof_addr <= RESET_ADDRESS[AW+1:0]; - else if (alu_pc_valid || mem_pc_valid) - prof_addr <= alu_pc; - - initial prof_ticks = 0; - always @(posedge i_clk) - if (i_reset) - prof_ticks <= 0; - else if (!i_halt) - prof_ticks <= prof_ticks + 1; - - assign o_prof_stb = prof_stb; - assign o_prof_addr = prof_addr; - assign o_prof_ticks = prof_ticks; - end else begin : NO_PROFILER - assign o_prof_stb = 1'b0; - assign o_prof_addr = 0; - assign o_prof_ticks = 0; - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // (Optional) Verilator $display simulation dumping support - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // The following is somewhat useful for debugging under Icarus Verilog. - // In that case, the VCD file can tell you what's going on at any - // specific moment, but it doesn't put the register set into the VCD - // file, nor does it give you any insight into the current contents of - // the memory, or how they got that way. The following is intended to - // be a first step towards that end. - // - // As currently envisioned, we track values written to the registers, - // and values read and written to memory. The program counter offered - // is typically off by 4 from the actual instruction address being - // completed. It may be off by more in the case of memory instructions. - // I haven't (yet) tried to make the PC given match the instruction - // address--so that may be an item to do later. - // - // You can activate (or de-activate) these instructions via the - // OPT_SIM_DEBUG flag below. If set to one, the simulation debuggin - // statements will be output as the CPU executes. - localparam OPT_SIM_DEBUG = 1'b0; - generate if (OPT_SIM_DEBUG) - begin : GEN_SIM_DEBUG - - reg [31:0] nstime; - - initial nstime = 0; - always @(posedge i_clk) - nstime <= nstime + 10; - - always @(posedge i_clk) - if (!i_reset && o_mem_ce) - begin - if (o_mem_reg[4] && !o_mem_op[0]) - begin - case(o_mem_op[2:1]) - // 3'b000: - // 3'b001: - 2'b01: $display("MEM: %8d LW uR%1d <- @%08x", nstime, o_mem_reg[3:0], o_mem_addr); - 2'b10: $display("MEM: %8d LH uR%1d <- @%08x", nstime, o_mem_reg[3:0], o_mem_addr); - 2'b11: $display("MEM: %8d LB uR%1d <- @%08x", nstime, o_mem_reg[3:0], o_mem_addr); - default: $display("MEM: %8d Unknown MEM op: %d\n", nstime, o_mem_op); - endcase - end else case(o_mem_op[2:0]) - // 3'b000: - // 3'b001: - 3'b010: $display("MEM: %8d LW sR%1d <- @%08x", nstime, o_mem_reg, o_mem_addr); - 3'b011: $display("MEM: %8d SW 0x%08x -> @%08x", nstime, o_mem_data, o_mem_addr); - 3'b100: $display("MEM: %8d LH sR%1d <- @%08x", nstime, o_mem_reg, o_mem_addr); - 3'b101: $display("MEM: %8d SH 0x%08x -> @%04x", nstime, o_mem_data[15:0], o_mem_addr); - 3'b110: $display("MEM: %8d LB sR%1d <- @%08x", nstime, o_mem_reg, o_mem_addr); - 3'b111: $display("MEM: %8d SB 0x%08x -> @%02x", nstime, o_mem_data[7:0], o_mem_addr); - default: $display("MEM: %8d Unknown MEM op: %d\n", nstime, o_mem_op); - endcase - end - - always @(posedge i_clk) - if (!i_reset && i_bus_err) - begin - $display("MEM: %8d BUS ERROR!!", nstime); - end - - always @(posedge i_clk) - if (!i_reset && wr_reg_ce) - begin - if (i_mem_valid) - begin - if (i_mem_wreg[4]) - $display("MEM: %8d Load 0x%08x -> uR%1d", nstime, i_mem_result, i_mem_wreg[3:0]); - else - $display("MEM: %8d Load 0x%08x -> sR%1d", nstime, i_mem_result, i_mem_wreg[3:0]); - end - - if (wr_reg_id[4] && OPT_USERMODE) - begin - if (wr_reg_id[3:0] == CPU_PC_REG) - $display("REG: %8d uPC <- 0x%08x [0x%08x]", nstime, wr_spreg_vl, (gie) ? upc : ipc); - else if (wr_reg_id[3:0] == CPU_CC_REG) - $display("REG: %8d uCC <- 0x%08x [0x%08x]", nstime, wr_spreg_vl, (gie) ? upc : ipc); - else if (wr_reg_id == 4'hd) - $display("REG: %8d uSP <- 0x%08x [0x%08x]", nstime, wr_gpreg_vl, (gie) ? upc : ipc); - else - $display("REG: %8d uR%1x <- 0x%08x [0x%08x]", nstime, wr_reg_id[3:0], wr_gpreg_vl, (gie) ? upc : ipc); - end else begin - - if (wr_reg_id[3:0] == CPU_PC_REG) - $display("REG: %8d sPC <- 0x%08x [0x%08x]", nstime, wr_spreg_vl, ipc); - else if (wr_reg_id[3:0] == CPU_CC_REG) - $display("REG: %8d sCC <- 0x%08x [0x%08x]", nstime, wr_spreg_vl, ipc); - else if (wr_reg_id[3:0] == 4'hd) - $display("REG: %8d sSP <- 0x%08x [0x%08x]", nstime, wr_gpreg_vl, ipc); - else - $display("REG: %8d sR%1x <- 0x%08x [0x%08x]", nstime, wr_reg_id[3:0], wr_gpreg_vl, ipc); - end - end - end endgenerate - // }}} - - // Make verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, fpu_ce, wr_spreg_vl[1:0], - ipc[1:0], upc[1:0], pf_pc[1:0], - dcd_rA, dcd_pipe, dcd_zI, - dcd_A_stall, dcd_B_stall, dcd_F_stall, - op_Rcc, op_pipe, op_lock, i_mem_pipe_stalled, prelock_stall, - dcd_F, w_clken }; - generate if (AW+2 < 32) - begin : UNUSED_AW - wire generic_ignore; - assign generic_ignore = &{ 1'b0, wr_spreg_vl[31:(AW+2)] }; - end if (!OPT_USERMODE) - begin : UNUSED_USERMODE - wire unused_usermode; - assign unused_usermode = &{ 1'b0, alu_reg[4], i_mem_wreg[4], - i_dbg_rreg[4] }; - end endgenerate - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations - // {{{ -`ifdef ZIPCPU -`define ASSUME assume -`else -`define ASSUME assert -`endif -`define ASSERT assert -// -// - - wire [1+1+4+15+6+4+13+AW+1+32+4+23-1:0] f_dcd_data; - wire fc_op_prepipe; - wire [6:0] fc_alu_Aid; - wire fc_alu_wR, fc_alu_M, fc_alu_prepipe; - reg f_alu_phase; - - reg f_past_valid; - - reg [2:0] f_dbg_pc_seq, f_dbg_cc_seq, f_dbg_reg_seq; - - wire fc_op_illegal, fc_op_wF, fc_op_ALU, fc_op_M, - fc_op_DV, fc_op_FP, fc_op_break, - fc_op_lock, fc_op_wR, fc_op_rA, fc_op_rB, - fc_op_sim; - wire [6:0] fc_op_Rid, fc_op_Aid, fc_op_Bid; - wire [31:0] fc_op_I; - wire [3:0] fc_op_cond; - wire [3:0] fc_op_op; - wire [22:0] fc_op_sim_immv; - wire f_op_insn; //f_alu_insn,f_wb_insn - reg f_op_phase, f_op_early_branch; - reg f_op_zI; - reg f_op_branch; - - wire [31:0] f_Bv; - reg [31:0] f_Av, f_pre_Bv; - - reg f_alu_branch; - - wire [31:0] f_dcd_mem_addr; - wire [AW-1:0] f_next_mem, f_op_mem_addr; - wire [4+AW+2+7+4-1:0] f_op_data; - - wire fc_alu_illegal, fc_alu_wF, fc_alu_ALU, fc_alu_DV, - fc_alu_FP, fc_alu_break, fc_alu_lock, - fc_alu_rA, fc_alu_rB, fc_alu_sim; - wire [6:0] fc_alu_Rid, fc_alu_Bid; - wire [31:0] fc_alu_I; - wire [3:0] fc_alu_cond; - wire [3:0] fc_alu_op; - wire [22:0] fc_alu_sim_immv; - - wire [F_LGDEPTH-1:0] f_mem_outstanding; - wire f_mem_gie, f_mem_pc, f_read_cycle, - f_exwrite_cycle; - wire [4:0] f_last_reg, f_addr_reg; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - -`ifndef VERIFIC - initial assume(i_reset); -`endif - always @(posedge i_clk) - if (!f_past_valid) - assume(i_reset); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The debugging interface - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - fdebug #( - .OPT_START_HALTED(OPT_START_HALTED), - .OPT_DISTRIBUTED_RAM(OPT_DISTRIBUTED_REGS) - ) fdbg ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - .i_cpu_reset(i_reset), - .i_halt(i_halt), - .i_halted(r_halted), - .i_clear_cache(i_clear_cache), - .i_dbg_we(i_dbg_we), - .i_dbg_reg(i_dbg_wreg), - .i_dbg_data(i_dbg_data), - .i_dbg_stall(o_dbg_stall), - .i_dbg_break(o_break), - .i_dbg_cc(o_dbg_cc) - // , .i_dbg_rreg(i_dbg_rreg), - // .i_dbg_rdata(o_dbg_rdata), - // }}} - ); - - always @(*) - if (i_halt && r_halted) - begin - `ASSERT(!alu_ce); - `ASSERT(!alu_phase); - `ASSERT(!div_ce); - `ASSERT(!o_mem_ce); - `ASSERT(f_mem_outstanding == 0); - end - - initial f_dbg_pc_seq = 0; - always @(posedge i_clk) - if (i_reset) - f_dbg_pc_seq <= 0; - else begin - f_dbg_pc_seq[0] <= i_dbg_we && !o_dbg_stall - && (i_dbg_wreg == { gie, CPU_PC_REG }); - f_dbg_pc_seq[2:1] <= f_dbg_pc_seq[1:0]; - end - - always @(posedge i_clk) - begin - if (f_dbg_pc_seq[0]) - begin - `ASSERT(dbgv && alu_reg == { gie, CPU_PC_REG }); - end - - if (f_dbg_pc_seq[1]) - begin - `ASSERT(clear_pipeline); - `ASSERT(o_pf_request_address == $past({ i_dbg_data[31:2], 2'b00 },2)); - end - end - - initial f_dbg_cc_seq = 0; - always @(posedge i_clk) - if (i_reset) - f_dbg_cc_seq <= 0; - else begin - f_dbg_cc_seq[0] <= i_dbg_we && !o_dbg_stall - && (i_dbg_wreg == { gie, CPU_CC_REG }); - f_dbg_cc_seq[2:1] <= f_dbg_cc_seq[1:0]; - end - - always @(posedge i_clk) - if (f_dbg_cc_seq[0]) - begin - `ASSERT(wr_reg_ce); - `ASSERT(wr_reg_id == $past(i_dbg_wreg)); - `ASSERT(wr_spreg_vl == $past(i_dbg_data)); - end - - initial f_dbg_reg_seq = 0; - always @(posedge i_clk) - if (i_reset) - f_dbg_reg_seq <= 0; - else begin - f_dbg_reg_seq[0] <= i_dbg_we && !o_dbg_stall - && (i_dbg_rreg[3:1] != 3'h7 ); - f_dbg_reg_seq[2:1] <= f_dbg_reg_seq[1:0]; - end - - always @(posedge i_clk) - begin - if (f_dbg_reg_seq[0] && !i_reset) - begin - `ASSERT(dbgv && alu_reg == $past(i_dbg_wreg)); - `ASSERT($past(i_dbg_rreg[3:1]) != 3'h7); - `ASSERT(dbg_val == $past(i_dbg_data)); - - `ASSERT(wr_reg_ce); - `ASSERT(wr_gpreg_vl == $past(i_dbg_data)); - `ASSERT(wr_reg_id == $past(i_dbg_wreg)); - end - - // if (f_dbg_reg_seq[1]) - // begin - // end - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Reset checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))) - begin - // Initial assertions - `ASSERT(!i_pf_valid); - `ASSERT(!dcd_phase); - `ASSERT(!op_phase); - `ASSERT(!alu_phase); - // - `ASSERT(!i_pf_valid); - `ASSERT(!dcd_valid); - `ASSERT(!op_valid); - `ASSERT(!op_valid_mem); - `ASSERT(!op_valid_div); - `ASSERT(!op_valid_alu); - `ASSERT(!op_valid_fpu); - // - `ASSERT(!alu_valid); - `ASSERT(!alu_busy); - // - `ASSERT(!i_mem_valid); - `ASSERT(!i_mem_rdbusy); - `ASSERT(!i_bus_err); - // - `ASSERT(!div_valid); - `ASSERT(!div_busy); - `ASSERT(!div_error); - // - `ASSERT(!fpu_valid); - `ASSERT(!fpu_busy); - `ASSERT(!fpu_error); - // - `ASSERT(!ill_err_i); - `ASSERT(!ill_err_u); - `ASSERT(!idiv_err_flag); - `ASSERT(!udiv_err_flag); - `ASSERT(!ibus_err_flag); - `ASSERT(!ubus_err_flag); - `ASSERT(!ifpu_err_flag); - `ASSERT(!ufpu_err_flag); - `ASSERT(!ihalt_phase); - `ASSERT(!uhalt_phase); - end - - always @(*) - begin - if (i_pf_valid) `ASSERT(f_past_valid); - if (dcd_valid) `ASSERT(f_past_valid); - if (alu_pc_valid) `ASSERT(f_past_valid); - if (i_mem_valid) `ASSERT(f_past_valid); - if (div_valid) `ASSERT(f_past_valid); - if (fpu_valid) `ASSERT(f_past_valid); - if (w_op_valid) `ASSERT(f_past_valid); - // if (i_mem_busy) `ASSERT(f_past_valid); - if (i_mem_rdbusy) `ASSERT(f_past_valid); - if (div_busy) `ASSERT(f_past_valid); - if (fpu_busy) `ASSERT(f_past_valid); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Pipeline signaling check - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (clear_pipeline) - begin - // `ASSERT(!alu_ce); - `ASSERT(!mem_ce); - end - - always @(posedge i_clk) - if ((f_past_valid)&&($past(clear_pipeline))) - begin - `ASSERT(!alu_busy); - `ASSERT(!div_busy); - `ASSERT(!i_mem_rdbusy); - `ASSERT(!fpu_busy); - // - `ASSERT(!alu_valid); - `ASSERT(!div_valid); - `ASSERT(!fpu_valid); - end - - always @(*) - if (dcd_ce) - `ASSERT((op_ce)||(!dcd_valid)); - - always @(*) - if ((op_ce)&&(!clear_pipeline)) - `ASSERT((adf_ce_unconditional)||(mem_ce)||(!op_valid)); - - // - // Make sure the dcd stage is never permanently stalled - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(alu_wR))&&(!$past(alu_wF)) - &&($past(f_past_valid,2))&&(!$past(alu_wR,2))&&(!$past(alu_wF)) - &&(!op_valid)&&(master_ce) - &&(!clear_pipeline)&&(!i_reset) - &&(!div_busy)&&(!div_valid) - &&(!i_mem_busy)&&(!i_mem_valid)&&(!i_bus_err) - &&(!alu_busy)&&(!alu_pc_valid)&&(!alu_valid) - &&(!fpu_busy)&&(!fpu_valid)&&(!fpu_error) - &&(!op_break)&&(!o_break) - &&(!w_switch_to_interrupt) - &&(!ibus_err_flag)&&(!ill_err_i)&&(!idiv_err_flag)) - begin - if (OPT_PIPELINED) - `ASSERT(dcd_ce || cc_invalid_for_dcd || i_halt); - if (!dcd_valid) - `ASSERT(dcd_ce); - end - - always @(posedge i_clk) - if (OPT_PIPELINED && !i_halt && !i_reset && (wr_flags_ce - || (wr_reg_ce && wr_reg_id == { op_gie, CPU_CC_REG }))) - `ASSERT(cc_invalid_for_dcd); - - always @(posedge i_clk) - if (!f_past_valid || !OPT_PIPELINED) - begin - `ASSERT(!cc_invalid_for_dcd); - end else if (alu_busy) - begin - `ASSERT(cc_invalid_for_dcd == (alu_wF || alu_reg == { gie, CPU_CC_REG })); - end else if (i_mem_rdbusy || i_bus_err) - begin - `ASSERT(i_bus_err || f_exwrite_cycle - || cc_invalid_for_dcd == (alu_reg == { gie, CPU_CC_REG })); - end else if (!clear_pipeline && cc_invalid_for_dcd) - begin - `ASSERT(alu_illegal || wr_flags_ce - || ((i_mem_valid || i_bus_err) - && ($past(i_mem_rdbusy - && f_last_reg == { gie, CPU_CC_REG }))) - || (wr_flags_ce || (wr_reg_ce && wr_reg_id == { op_gie, CPU_CC_REG })) - || ($past(wr_flags_ce) - || $past(wr_reg_ce && wr_reg_id == { op_gie, CPU_CC_REG }))); - end - - // - // Make sure the ops stage is never permanently stalled - always @(*) - if ((op_valid)&&(master_ce)&&(!clear_pipeline)&&(!i_reset) - &&(!div_busy)&&(!div_valid) - &&(!i_mem_busy)&&(!i_mem_valid)&&(!i_bus_err) - &&(!alu_busy)&&(!alu_pc_valid) - &&(!fpu_busy)&&(!fpu_valid)&&(!fpu_error) - &&(!op_break)&&(!o_break) - &&(!w_switch_to_interrupt) - &&(!alu_illegal) && (!prelock_stall) - &&(!step || !stepped) - &&(!ibus_err_flag)&&(!ill_err_i)&&(!idiv_err_flag)) - `ASSERT(adf_ce_unconditional | mem_ce); - - // always @(posedge i_clk) - // if (f_past_valid&& $past(op_valid && dcd_valid && i_pf_valid - // && !op_ce)) - // `ASSERT(!prelock_stall); - - // - // Make sure that, following an op_ce && op_valid, op_valid is only - // true if dcd_valid was as well - always @(posedge i_clk) - if ((f_past_valid)&&($past(op_ce && op_valid && !dcd_valid))) - begin - if ($past(dcd_early_branch)) - begin - `ASSERT(!dcd_early_branch); - end else - `ASSERT(!op_valid); - end - - // - // Same for the next step - always @(posedge i_clk) - if ((f_past_valid)&&($past(op_valid && (mem_ce ||adf_ce_unconditional))) - &&(!$past(dcd_valid))) - begin - if ($past(dcd_early_branch)) - begin - `ASSERT(!dcd_early_branch); - end else - `ASSERT(!op_valid); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about the Program counter - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - if (i_pf_valid) - `ASSERT(i_pf_instruction_pc[1:0]==2'b00); - - always @(*) - if ((dcd_valid)&&(!dcd_illegal)) - `ASSERT((!dcd_pc[1])||(dcd_phase)); - - always @(*) - `ASSERT(!op_pc[0]); - - always @(*) - `ASSERT(!alu_pc[0]); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about the prefetch (output) stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if ((!clear_pipeline)&&(i_pf_valid)) - `ASSERT(pf_gie == gie); - - always @(*) - if ((i_pf_valid)&&(!clear_pipeline)) - `ASSERT(pf_gie == gie); - - ffetch #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .OPT_CONTRACT(1'b0), - .OPT_ALIGNED(1'b1)) - chkifetch( - .i_clk(i_clk), .i_reset(i_reset), - .cpu_new_pc(o_pf_new_pc), - .cpu_clear_cache(o_clear_icache), - .cpu_pc(o_pf_request_address), .pf_valid(i_pf_valid), - .cpu_ready(o_pf_ready), .pf_pc(i_pf_instruction_pc), - .pf_insn(i_pf_instruction), .pf_illegal(i_pf_illegal)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about the decode stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign f_dcd_data = { - dcd_phase, - dcd_opn, dcd_A, dcd_B, dcd_R, // 4+15 - dcd_Acc, dcd_Bcc, dcd_Apc, dcd_Bpc, dcd_Rcc, dcd_Rpc,//6 - dcd_F, // 4 - dcd_wR, dcd_rA, dcd_rB, - dcd_ALU, dcd_M, dcd_DIV, dcd_FP, - dcd_wF, dcd_gie, dcd_break, dcd_lock, - dcd_pipe, dcd_ljmp, - dcd_pc, // AW+1 - dcd_I, // 32 - dcd_zI, // true if dcd_I == 0 - dcd_illegal, - dcd_early_branch, - dcd_sim, dcd_sim_immv - }; - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!$past(clear_pipeline)) - &&(!$past(o_clear_icache)) - &&($past(dcd_valid))&&($past(dcd_stalled)) - &&(!clear_pipeline)) - begin - `ASSERT((!OPT_PIPELINED)||(dcd_valid)); - `ASSERT((!dcd_valid && OPT_LOWPOWER) || $stable(f_dcd_data)); - `ASSERT((!dcd_valid && OPT_LOWPOWER) || $stable(f_dcd_insn_word)); - end - - always @(*) - if ((dcd_valid || dcd_phase)&&(!clear_pipeline)) - `ASSERT(f_dcd_insn_gie == dcd_gie); - - always @(posedge i_clk) - if ((dcd_valid)&&(!dcd_illegal)&&(!clear_pipeline)) - begin - `ASSERT(dcd_gie == gie); - if ((gie)||(dcd_phase)) - begin - `ASSERT((!dcd_wR)||(dcd_R[4]==dcd_gie)); - `ASSERT((!dcd_rA)||(dcd_A[4]==dcd_gie)); - `ASSERT((!dcd_rB)||(dcd_B[4]==dcd_gie)); - end else if ((!dcd_early_branch)&&((dcd_M) - ||(dcd_DIV)||(dcd_FP)||(!dcd_wR))) - `ASSERT(!dcd_gie); - if ((dcd_ALU)&&(dcd_opn==CPU_MOV_OP)) - begin - `ASSERT(((!dcd_rA)&&(dcd_wR)) - ||((!dcd_rA)&&(!dcd_rB)&&(!dcd_wR))); - end else if (dcd_ALU) - `ASSERT( - (gie == dcd_R[4]) - &&(gie == dcd_A[4]) - &&((!dcd_rB)||(gie == dcd_B[4])) - &&(dcd_gie == gie)); - end - - always @(*) - if ((op_valid)&&(op_rA)&&(op_Aid[3:1] == 3'h7)&&(!clear_pipeline) - &&(op_Aid[4:0] != { gie, 4'hf})) - `ASSERT(!pending_sreg_write); - - always @(*) - if ((op_valid)&&(op_rB)&&(op_Bid[3:1] == 3'h7)&&(!clear_pipeline) - &&(op_Bid[4:0] != { gie, 4'hf})) - `ASSERT(!pending_sreg_write); - - - always @(*) - if ((dcd_valid)&&(!clear_pipeline)) - `ASSERT(dcd_gie == gie); - - // - // - // Piped Memory assertions - // - // - always @(*) - if ((dcd_valid)&&(dcd_M)&&(dcd_pipe)&&(!dcd_illegal)&&(!alu_illegal) - &&(!break_pending)&&(!clear_pipeline)) - begin - if (op_valid_mem) - begin - `ASSERT(op_opn[0] == dcd_opn[0]); - `ASSERT((!dcd_rB) - ||(op_Bid[4:0] == dcd_B[4:0])); - `ASSERT(op_rB == dcd_rB); - end - `ASSERT(dcd_B[4] == dcd_gie); - end - - always @(*) - if (op_valid_mem && op_pipe && i_mem_busy) - `ASSERT(f_read_cycle == !op_opn[0]); - - always @(*) - if ((dcd_valid)&&(!dcd_M)) - `ASSERT((dcd_illegal)||(!dcd_pipe)); - - assign f_dcd_mem_addr = w_op_BnI+dcd_I; - - always @(posedge i_clk) - if ((f_past_valid)&&($past(dcd_early_branch))&&(!dcd_early_branch) - &&(dcd_valid)) - `ASSERT(!dcd_pipe); - always @(*) - if ((dcd_valid)&&(dcd_early_branch)) - `ASSERT(!dcd_M); - - always @(*) - if ((dcd_valid)&&(!dcd_illegal)&&(!fc_op_prepipe)) - `ASSERT(!dcd_pipe); - - always @(*) - if ((dcd_valid)&&(dcd_pipe)&&(w_op_valid)) - begin - // `ASSERT((dcd_A[3:1] != 3'h7)||(dcd_opn[0])); - `ASSERT(dcd_B[3:1] != 3'h7); - `ASSERT(dcd_rB); - `ASSERT(dcd_M); - `ASSERT(dcd_B == op_Bid); - if (op_valid) - `ASSERT((op_valid_mem)||(op_illegal)); - - if (op_valid_mem) - begin - `ASSERT((dcd_I[AW+1:3] == 0) - ||(!alu_busy)||(!div_busy) - ||(!alu_wR)||(alu_reg != dcd_B)); - `ASSERT((!op_wR)||(op_Aid != op_Bid)); - end - end - - // - // Decode option processing - // - - // OPT_CIS ... the compressed instruction set - always @(*) - if ((!OPT_CIS)&&(dcd_valid)) - begin - `ASSERT(!dcd_phase); - `ASSERT(dcd_pc[1:0] == 2'b0); - end - - always @(*) - if ((dcd_valid)&&(dcd_phase)) - `ASSERT(f_dcd_insn_word[31]); - - - // OPT_EARLY_BRANCHING - always @(*) - if (!OPT_EARLY_BRANCHING) - `ASSERT((!dcd_early_branch) - &&(!dcd_early_branch_stb) - &&(!dcd_ljmp)); - - // OPT_DIV - always @(*) - if ((dcd_DIV)&&(dcd_valid)&&(!dcd_illegal)) - `ASSERT(dcd_wR); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about the op stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign f_op_data = { op_valid_mem, op_valid_alu, - op_valid_div, op_valid_fpu, - // The Av and Bv values can change while we are stalled in the - // op stage--that's why we are stalled there - // r_op_Av, r_op_Bv, // 32 ea - op_pc[AW+1:2], // AW - op_wR, op_wF, - r_op_F, // 7 - op_illegal, op_break, - op_lock, op_pipe - }; - - - always @(posedge i_clk) - if ((f_past_valid)&&($past(op_valid))&&(!$past(i_reset)) - &&(!$past(clear_pipeline))) - begin - if (($past(op_valid_mem))&&($past(mem_stalled))) - `ASSERT($stable(f_op_data[AW+16:1])&&(!$rose(op_pipe))); - if (($past(op_valid_div))&&($past(div_busy))) - `ASSERT($stable(f_op_data)); - end - - f_idecode #( - // {{{ - .OPT_MPY((OPT_MPY!=0)? 1'b1:1'b0), - .OPT_SHIFTS(OPT_SHIFTS), - .OPT_DIVIDE(OPT_DIV), - .OPT_FPU(IMPLEMENT_FPU), - .OPT_LOCK(OPT_LOCK), - .OPT_OPIPE(OPT_PIPELINED_BUS_ACCESS), - .OPT_SIM(1'b0), - .OPT_USERMODE(OPT_USERMODE), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_CIS(OPT_CIS) - // }}} - ) f_insn_decode_op( - // {{{ - f_op_insn_word, f_op_phase, op_gie, - fc_op_illegal, fc_op_Rid, fc_op_Aid, fc_op_Bid, - fc_op_I, fc_op_cond, fc_op_wF, fc_op_op, fc_op_ALU, - fc_op_M, fc_op_DV, fc_op_FP, fc_op_break, fc_op_lock, - fc_op_wR, fc_op_rA, fc_op_rB, fc_op_prepipe, - fc_op_sim, fc_op_sim_immv - // }}} - ); - - initial f_op_early_branch = 1'b0; - always @(posedge i_clk) - if (op_ce && (!OPT_MEMPIPE || dcd_valid || dcd_illegal || dcd_early_branch)) - begin - f_op_insn_word <= f_dcd_insn_word; - f_op_phase <= dcd_phase; - f_op_early_branch <= dcd_early_branch; - f_op_zI <= dcd_zI; - end - - initial f_op_branch = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(clear_pipeline)) - f_op_branch <= 1'b0; - else if (op_ce) - f_op_branch <= (dcd_early_branch)||dcd_ljmp; - else if ((adf_ce_unconditional)||(mem_ce)) - f_op_branch <= 1'b0; - - always @(*) - if (!OPT_EARLY_BRANCHING) - begin - `ASSERT(!f_op_branch); - end else if ((f_op_early_branch)&&(op_valid)) - `ASSERT(f_op_branch); - - - always @(posedge i_clk) - if (op_valid &&(f_op_branch || !fc_op_illegal)&& !clear_pipeline) - begin - // {{{ - if (f_op_branch) - begin - // {{{ - `ASSERT(!op_valid_alu); - `ASSERT(!op_valid_mem); - `ASSERT(!op_valid_div); - `ASSERT(!op_valid_fpu); - `ASSERT(!op_illegal); - `ASSERT(!op_rA); - `ASSERT(!op_rB); - `ASSERT(!op_wR); - `ASSERT(!op_wF); - `ASSERT(op_opn == CPU_MOV_OP); - // }}} - end - - if (op_illegal) - begin - // {{{ - `ASSERT(!op_valid_mem); - `ASSERT(!op_valid_div); - `ASSERT(!op_valid_fpu); - `ASSERT( op_valid_alu); - `ASSERT((!OPT_PIPELINED)||(!op_rA)); - `ASSERT((!OPT_PIPELINED)||(!op_rB)); - `ASSERT(!f_op_branch); - // }}} - end else begin - if (!f_op_branch) - begin - // {{{ - `ASSERT(fc_op_ALU == op_valid_alu); - `ASSERT(fc_op_M == op_valid_mem); - `ASSERT(fc_op_DV == op_valid_div); - `ASSERT(fc_op_FP == op_valid_fpu); - `ASSERT(fc_op_rA == op_rA); - `ASSERT(fc_op_rB == op_rB); - `ASSERT(fc_op_wF == op_wF); - `ASSERT(fc_op_Rid[4:0] == op_R); - `ASSERT(f_op_zI == (fc_op_I == 0)); - `ASSERT(fc_op_wF == op_wF); - `ASSERT(fc_op_lock == op_lock); - if (!OPT_PIPELINED && step && stepped) - begin - `ASSERT(!op_break); - end else begin - `ASSERT(fc_op_break == op_break); - end - `ASSERT(fc_op_I == 0 || !i_mem_rdbusy - || f_exwrite_cycle - || !fc_op_rB - || (fc_op_Bid[4:0] != f_last_reg - && (f_mem_outstanding <= 1) - && (!fc_op_M || !op_pipe)) - || fc_op_Bid[4:0] == f_addr_reg); - if (!i_halt && !i_reset && !f_exwrite_cycle) - `ASSERT((!wr_reg_ce) - ||(wr_reg_id != fc_op_Bid[4:0]) - ||(!op_rB)||(fc_op_I == 0)); - - `ASSERT(fc_op_sim == op_sim); - `ASSERT(fc_op_sim_immv == op_sim_immv); - - case(fc_op_cond[2:0]) - 3'h0: `ASSERT(op_F == 8'h00); // Always - 3'h1: `ASSERT(op_F == 8'h11); // Z - 3'h2: `ASSERT(op_F == 8'h44); // LT - 3'h3: `ASSERT(op_F == 8'h22); // C - 3'h4: `ASSERT(op_F == 8'h88); // V - 3'h5: `ASSERT(op_F == 8'h10); // NE - 3'h6: `ASSERT(op_F == 8'h40); // GE (!N) - 3'h7: `ASSERT(op_F == 8'h20); // NC - endcase - - if ((fc_op_wR)&&(fc_op_Rid[4:0] == { gie, CPU_PC_REG})) - begin - `ASSERT(!op_phase); - end else - `ASSERT(f_op_phase == op_phase); - // }}} - end // Bit order is { (flags_not_used), VNCZ mask, VNCZ value } - `ASSERT((!op_wR)||(fc_op_Rid[4:0] == op_R)); - `ASSERT(((!op_wR)&&(!op_rA))||(fc_op_Aid[4:0] == op_Aid[4:0])); - `ASSERT((!op_rB)||(fc_op_Bid[4:0] == op_Bid)); - // - // if ((!alu_illegal)&&(!ill_err_i)&&(!clear_pipeline)) - - if (f_op_early_branch) - begin - // {{{ - `ASSERT(op_opn == CPU_MOV_OP); - `ASSERT(!op_wR); - `ASSERT(!op_wF); - `ASSERT(f_op_branch); - // }}} - end else begin - // {{{ - `ASSERT(fc_op_op == op_opn); - `ASSERT(fc_op_wR == op_wR); - // }}} - end - end - if (!OPT_PIPELINED_BUS_ACCESS) - `ASSERT((!i_mem_rdbusy)||(i_mem_wreg != fc_op_Bid) - ||(!fc_op_rB)||(fc_op_I == 0)); - // }}} - end else if (op_valid && !clear_pipeline && fc_op_illegal) - begin - // {{{ - `ASSERT(op_illegal); - `ASSERT(op_valid_alu); - `ASSERT(!f_op_branch); - // }}} - end - - always @(*) - if ((op_valid)&&(op_illegal)) - begin - `ASSERT(!op_valid_div); - `ASSERT(!op_valid_fpu); - `ASSERT(!op_valid_mem); - end - -// always @(*) -// if (!op_valid) -// `ASSERT(!op_break); - - always @(*) - if ((!OPT_CIS)&&(op_valid)) - begin - `ASSERT((!op_phase)||(op_illegal)); - `ASSERT(op_pc[1:0] == 2'b0); - end - - always @(*) - if ((!OPT_LOCK)&&(op_valid)) - `ASSERT((!op_lock)||(op_illegal)); - - always @(*) - if (!OPT_EARLY_BRANCHING) - `ASSERT(!f_op_early_branch); - - - always @(*) - if (op_ce) - `ASSERT((dcd_valid)||(dcd_illegal)||(dcd_early_branch)); - - always @(*) - if ((f_past_valid)&&(!f_op_zI)&&(i_mem_rdbusy)&&(op_valid)&&(op_rB)) - `ASSERT((!OPT_DCACHE)||(OPT_MEMPIPE) - ||(i_mem_wreg != op_Bid)); - - always @(posedge i_clk) - if ((op_valid)&&(op_rB)&&(!f_op_zI)&&((i_mem_rdbusy)||(i_mem_valid)) - &&(i_mem_wreg != {gie, CPU_PC_REG})) - begin - if (!OPT_MEMPIPE) - begin - `ASSERT(fc_alu_Aid[4:0] == i_mem_wreg); - `ASSERT(i_mem_wreg != op_Bid); - end - end - - always @(posedge i_clk) - if (i_mem_rdbusy) - begin - `ASSERT(fc_alu_M); - `ASSERT(!OPT_PIPELINED||fc_alu_wR || (OPT_LOCK && f_mem_pc)); - end - - always @(*) - if ((op_valid)&&(!clear_pipeline)) - `ASSERT(op_gie == gie); - - always @(*) - if ((op_valid_alu)&&(!op_illegal)) - begin - if ((op_opn != CPU_SUB_OP) - &&(op_opn != CPU_AND_OP) - &&(op_opn != CPU_MOV_OP)) - begin - `ASSERT(op_wR); - end - if ((op_opn != CPU_MOV_OP)&&(op_opn != CPU_BREV_OP)) - `ASSERT(op_rA); - end - - - always @(posedge i_clk) - if ((op_valid)&&(!op_illegal) - &&(!alu_illegal)&&(!ill_err_i)&&(!clear_pipeline)) - begin - `ASSERT(op_gie == gie); - if ((gie)||(op_phase)) - begin - `ASSERT((!op_wR)||(op_R[4] == gie)); - `ASSERT((!op_rA)||(op_Aid[4] == gie)); - `ASSERT((!op_rB)||(op_Bid[4] == gie)); - end else if (((op_valid_mem) - ||(op_valid_div)||(op_valid_fpu) - ||((op_valid_alu)&&(op_opn!=CPU_MOV_OP)))) - begin - `ASSERT((!op_wR)||(op_R[4] == gie)); - `ASSERT((!op_rA)||(op_Aid[4] == gie)); - `ASSERT((!op_rB)||(op_Bid[4] == gie)); - end - end - - always @(posedge i_clk) - if ((!op_valid)&&(!$past(op_illegal)) - &&(!clear_pipeline)&&(!pending_interrupt)) - `ASSERT(!op_illegal); - - always @(*) - begin - if (alu_ce) - `ASSERT(adf_ce_unconditional); - if (div_ce) - `ASSERT(adf_ce_unconditional); - if (fpu_ce) - `ASSERT(adf_ce_unconditional); - - if ((op_valid)&&(op_illegal)) - `ASSERT(op_valid_alu); - end - - always @(*) - if (mem_ce) - `ASSERT((op_valid)&&(op_valid_mem)&&(!op_illegal)); - - always @(*) - if (div_ce) - `ASSERT(op_valid_div); - - - always @(*) - if ((ibus_err_flag)||(ill_err_i)||(idiv_err_flag)) - begin - `ASSERT(master_stall); - `ASSERT(!mem_ce); - `ASSERT(!alu_ce); - `ASSERT(!div_ce); - `ASSERT(!adf_ce_unconditional); - end - - always @(posedge i_clk) - if ((adf_ce_unconditional)||(mem_ce)) - `ASSERT(op_valid); - - always @(*) - if ((op_valid_alu)&&(!adf_ce_unconditional)&&(!clear_pipeline)) - `ASSERT(!op_ce); - - always @(*) - if ((op_valid_div)&&(!adf_ce_unconditional)) - `ASSERT(!op_ce); - - always @(posedge i_clk) - if (alu_stall) - `ASSERT(!alu_ce); - always @(posedge i_clk) - if (mem_stalled) - `ASSERT(!o_mem_ce); - always @(posedge i_clk) - if (div_busy) - `ASSERT(!div_ce); - - always @(*) - if ((!i_reset)&&(break_pending)&&(!clear_pipeline)) - `ASSERT((op_valid)&&(op_break)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // Op: Memory pipeline assertions - // - - assign f_next_mem = o_mem_addr + 1'b1; - assign f_op_mem_addr = op_Bv[AW+1:2]; - - fmem #( - // {{{ - .OPT_LOCK(OPT_LOCK), - .F_LGDEPTH(F_LGDEPTH), - .OPT_MAXDEPTH((OPT_PIPELINED && OPT_PIPELINED_BUS_ACCESS) - ? 14:1), - .OPT_AXI_LOCK(2) // Let the solver pick - // }}} - ) chkmemops( - // {{{ - .i_clk(i_clk), .i_sys_reset(i_reset), .i_cpu_reset(i_reset), - // - .i_stb(o_mem_ce), - .i_pipe_stalled(i_mem_pipe_stalled), - .i_clear_cache(o_clear_dcache), - .i_lock(o_bus_lock), - .i_op(o_mem_op), .i_data(o_mem_data), .i_addr(o_mem_addr), - .i_oreg(o_mem_reg), .i_areg(op_Bid), - .i_busy(i_mem_busy),.i_rdbusy(i_mem_rdbusy), - .i_valid(i_mem_valid), .i_err(i_bus_err), .i_wreg(i_mem_wreg), - .i_result(i_mem_result), - .f_outstanding(f_mem_outstanding), - .f_pc(f_mem_pc), .f_gie(f_mem_gie), - .f_read_cycle(f_read_cycle), - .f_axi_write_cycle(f_exwrite_cycle), - .f_last_reg(f_last_reg), .f_addr_reg(f_addr_reg) - // }}} - ); - - always @(*) - if ((op_valid)&&(!fc_alu_prepipe)) - `ASSERT((!op_valid_mem)||(!op_pipe)); - - // Validate op_opn and (some of) op_Bid - // {{{ - always @(*) - if ((op_valid_mem)&&(op_pipe)) - begin - // {{{ - if (i_mem_rdbusy) - `ASSERT(op_opn[0] == f_exwrite_cycle); - if (f_mem_outstanding > ((i_bus_err || i_mem_valid) ? 1:0)) - `ASSERT(op_opn[0] != fc_alu_wR); - - // if ((i_mem_busy)&&(!i_mem_rdbusy && !i_mem_valid)) - // `ASSERT(!o_mem_ce || op_opn[0] == 1'b1); - - if (i_mem_rdbusy) - begin - if (OPT_PIPELINED_BUS_ACCESS) - begin end - else if (OPT_DCACHE) - `ASSERT(!i_mem_valid || i_mem_wreg != op_Bid); - end - // }}} - end - // }}} - - always @(posedge i_clk) - if (op_valid_mem && op_pipe) - begin - // {{{ - if ((i_mem_busy)&&(!OPT_DCACHE)) - `ASSERT((f_op_mem_addr == o_mem_addr) - ||(f_op_mem_addr == f_next_mem)); - if (i_mem_valid) - `ASSERT(op_Bid != i_mem_wreg); - - if (alu_busy||alu_valid) - `ASSERT((!alu_wR)||(op_Bid != alu_reg)); - - if (f_past_valid) - begin - if ((i_mem_busy)&&(!OPT_DCACHE)) - `ASSERT((op_Bv[(AW+1):2]==o_mem_addr[(AW-1):0]) - ||(op_Bv[(AW+1):2]==o_mem_addr[(AW-1):0]+1'b1)); - - if ($past(mem_ce)) - `ASSERT(op_Bid == $past(op_Bid)); - end - - `ASSERT(op_Bid[3:1] != 3'h7); - - if ((i_mem_rdbusy||i_mem_valid) && !f_exwrite_cycle) - begin - if (!OPT_MEMPIPE) - begin - // {{{ - `ASSERT(fc_alu_Aid[4:0] == i_mem_wreg); - `ASSERT(i_mem_wreg != op_Bid); - // }}} - end else if (OPT_DCACHE) - begin - // {{{ - `ASSERT(fc_alu_Aid[4:0] != op_Bid); - // }}} - end else // if (!OPT_DCACHE) - begin - // {{{ - if ((i_mem_valid) - ||($past(i_mem_rdbusy))) - `ASSERT(i_mem_wreg != op_Bid); - // }}} - end - end - // }}} - end - - always @(*) - if ((dcd_valid)&&(dcd_pipe)) - `ASSERT((op_Aid[3:1] != 3'h7)||(op_opn[0])); - - always @(*) - if ((op_valid)&(!op_valid_mem)) - `ASSERT((op_illegal)||(!op_pipe)); - - // Check f_addr_reg and f_last_reg - // {{{ - always @(*) - if (OPT_MEMPIPE && (op_valid && op_rB) && !f_exwrite_cycle - &&(!f_op_zI)&&(i_mem_rdbusy || i_mem_valid)) - `ASSERT(f_last_reg != op_Bid); - - always @(*) - if (i_mem_rdbusy && !f_exwrite_cycle) - `ASSERT(f_last_reg == alu_reg); - - always @(*) - if ((op_valid_mem)&&(op_pipe) && i_mem_valid) - `ASSERT(op_Bid != i_mem_wreg); - - always @(*) - if ((op_valid_mem)&&(op_pipe) && (i_mem_rdbusy || i_mem_valid)) - `ASSERT(op_Bid == f_addr_reg); - - always @(*) - if (i_mem_rdbusy) - begin - if (op_valid_mem && op_pipe) - begin - `ASSERT(op_Bid == f_addr_reg); - `ASSERT(op_Bid != f_last_reg); - if (dcd_M && dcd_pipe && !dcd_illegal - && !dcd_early_branch) - `ASSERT(op_Bid == dcd_B[4:0]); - end else if (!op_valid_mem && dcd_M && dcd_pipe - && !dcd_illegal && !dcd_early_branch) - `ASSERT(dcd_B[4:0] == f_addr_reg); - end - // }}} - - always @(*) - if (op_valid && !f_op_zI && i_mem_rdbusy && (f_last_reg != { gie, CPU_PC_REG })) - `ASSERT(!op_rB || fc_op_Bid[4:0] == f_addr_reg - ||((f_mem_outstanding == 1) && (fc_op_Bid[4:0] != f_last_reg))); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about the ALU stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if ((alu_ce)&&(!clear_pipeline)) - `ASSERT((op_valid_alu)&&(op_gie == gie)); - always @(*) - if ((mem_ce)&&(!clear_pipeline)) - `ASSERT((op_valid_mem)&&(op_gie == gie)); - always @(*) - if ((div_ce)&&(!clear_pipeline)) - `ASSERT((op_valid_div)&&(op_gie == gie)); - - always @(*) - if ((!clear_pipeline)&&((i_mem_valid)||(div_valid)||(div_busy) - ||(i_mem_rdbusy)||(alu_valid))) - `ASSERT(alu_gie == gie); - always @(*) - if ((!OPT_CIS)&&(alu_pc_valid)) - `ASSERT(alu_pc[1:0] == 2'b0); - always @(*) - if (!OPT_LOCK) - `ASSERT((!o_bus_lock)&&(!prelock_stall)); - always @(*) - if (!OPT_DIV) - `ASSERT((!dcd_DIV)&&(!op_valid_div)&&(!div_busy)&&(!div_valid)&&(!div_ce)); - always @(*) - if (OPT_MPY == 0) - `ASSERT(alu_busy == 1'b0); - - - always @(*) - if (!clear_pipeline) - begin - if ((alu_valid)||(alu_illegal)) - `ASSERT(alu_gie == gie); - if (div_valid) - `ASSERT(alu_gie == gie); - end - - always @(*) - if (alu_busy) - begin - `ASSERT(!i_mem_rdbusy); - `ASSERT(!div_busy); - `ASSERT(!fpu_busy); - end else if (i_mem_rdbusy) - begin - `ASSERT(!div_busy); - `ASSERT(!fpu_busy); - end else if (div_busy) - `ASSERT(!fpu_busy); - - always @(posedge i_clk) - if ((div_valid)||(div_busy)) - `ASSERT(alu_reg[3:1] != 3'h7); - - always @(posedge i_clk) - if ((f_past_valid)&&(wr_reg_ce) - &&((!$past(r_halted))||(!$past(i_dbg_we)))) - `ASSERT(alu_gie == gie); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract checking : A operand - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - begin - f_Av = regset[fc_op_Aid[4:0]]; - if (fc_op_Aid[3:0] == CPU_PC_REG) - begin - if ((wr_reg_ce)&&(wr_reg_id == fc_op_Aid[4:0])) - f_Av = wr_spreg_vl; - else if (fc_op_Aid[4] == op_gie) - f_Av = op_pc; // f_next_addr; - else if (fc_op_Aid[3:0] == { 1'b1, CPU_PC_REG }) - begin - f_Av[31:(AW+1)] = 0; - f_Av[(AW+1):0] = { upc, uhalt_phase, 1'b0 }; - end - end else if (fc_op_Aid[4:0] == { 1'b0, CPU_CC_REG }) - begin - f_Av = { w_cpu_info, regset[fc_op_Aid[4:0]][22:16], w_iflags }; - if ((wr_reg_ce)&&(wr_reg_id == fc_op_Aid[4:0])) - f_Av[22:16] = wr_spreg_vl[22:16]; - end else if (fc_op_Aid[4:0] == { 1'b1, CPU_CC_REG }) - begin - f_Av = { w_cpu_info, regset[fc_op_Aid[4:0]][22:16], w_uflags }; - if ((wr_reg_ce)&&(wr_reg_id == fc_op_Aid[4:0])) - f_Av[22:16] = wr_spreg_vl[22:16]; - end else if ((wr_reg_ce)&&(wr_reg_id == fc_op_Aid[4:0])) - f_Av = wr_gpreg_vl; - else - f_Av = regset[fc_op_Aid[4:0]]; - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract checking : B operand - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // The PRE-logic - always @(*) - begin - f_pre_Bv = regset[fc_op_Bid[4:0]]; - // - if (fc_op_Bid[3:0] == CPU_PC_REG) - begin - // Can always read your own address - if (fc_op_Bid[4] == op_gie) - f_pre_Bv = { {(30-AW){1'b0}}, op_pc[(AW+1):2], 2'b00 }; // f_next_addr; - else // if (fc_op_Bid[4]) - // Supervisor or user may read the users PC reg - begin - f_pre_Bv = 0; - f_pre_Bv[(AW+1):0] = { upc[(AW+1):2], uhalt_phase, 1'b0 }; - if ((wr_reg_ce)&&(wr_reg_id == fc_op_Bid[4:0])) - f_pre_Bv = wr_spreg_vl; - end - end else if (fc_op_Bid[3:0] == CPU_CC_REG) - begin - f_pre_Bv = { w_cpu_info, regset[fc_op_Bid[4:0]][22:16], - w_uflags }; - // if ((fc_op_Bid[4] == op_gie)&&(!fc_op_Bid[4])) - f_pre_Bv[15:0] = (gie || fc_op_Bid[4]) ? w_uflags : w_iflags; - - if ((wr_reg_ce)&&(wr_reg_id == fc_op_Bid[4:0])) - f_pre_Bv[22:16] = wr_spreg_vl[22:16]; - - end else if ((wr_reg_ce)&&(wr_reg_id == fc_op_Bid[4:0])) - f_pre_Bv = wr_gpreg_vl; - else - f_pre_Bv = regset[fc_op_Bid[4:0]]; - end - - - // The actual calculation of B - assign f_Bv = (fc_op_rB) - ? ((fc_op_Bid[5]) - ? ( { f_pre_Bv }+{ fc_op_I[29:0],2'b00 }) - : (f_pre_Bv + fc_op_I)) - : fc_op_I; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // CONTRACT: The operands to an ALU/MEM/DIV operation must be valid. - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - if (!i_reset && op_valid && !op_illegal - && (!clear_pipeline && !dbg_clear_pipe) - && (!i_halt || !dbgv) - &&((!wr_reg_ce)||(wr_reg_id!= { gie, CPU_PC_REG })) - &&(!f_op_branch)) - begin - if ((fc_op_rA)&&(fc_op_Aid[3:1] != 3'h7)) - `ASSERT(f_Av == op_Av); - - if (!fc_op_rB || fc_op_Bid[4:0] != { gie, CPU_CC_REG } - || !OPT_PIPELINED) - begin - `ASSERT(f_Bv == op_Bv); - end else if (f_op_zI) - `ASSERT(((f_Bv ^ op_Bv) & 32'hffff_c0ff) == 0); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about the ALU stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // alu_valid - // alu_ce - // alu_stall - // ALU stage assertions - - always @(posedge i_clk) - if ((alu_ce)||(mem_ce)||(div_ce)||(fpu_ce)) - begin - f_alu_insn_word <= f_op_insn_word; - f_alu_phase <= f_op_phase; - end - - initial f_alu_branch = 1'b0; - always @(posedge i_clk) - if ((adf_ce_unconditional)||(mem_ce)) - f_alu_branch <= f_op_branch; - else - f_alu_branch <= 1'b0; - - f_idecode #( - // {{{ - .OPT_MPY((OPT_MPY!=0)? 1'b1:1'b0), - .OPT_SHIFTS(OPT_SHIFTS), - .OPT_DIVIDE(OPT_DIV), - .OPT_FPU(IMPLEMENT_FPU), - .OPT_LOCK(OPT_LOCK), - .OPT_OPIPE(OPT_PIPELINED_BUS_ACCESS), - .OPT_SIM(1'b0), - .OPT_USERMODE(OPT_USERMODE), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_CIS(OPT_CIS) - // }}} - ) f_insn_decode_alu( - // {{{ - f_alu_insn_word, f_alu_phase, alu_gie, - fc_alu_illegal, fc_alu_Rid, fc_alu_Aid, fc_alu_Bid, - fc_alu_I, fc_alu_cond, fc_alu_wF, fc_alu_op, fc_alu_ALU, - fc_alu_M, fc_alu_DV, fc_alu_FP, fc_alu_break, - fc_alu_lock, fc_alu_wR, fc_alu_rA, fc_alu_rB, - fc_alu_prepipe, fc_alu_sim, fc_alu_sim_immv - // }}} - ); - - always @(posedge i_clk) - if (!wr_reg_ce) - begin - if (f_alu_branch) - begin - `ASSERT((!div_valid)&&(!div_busy)); - `ASSERT((!fpu_valid)&&(!fpu_busy)); - `ASSERT(!i_mem_rdbusy); - `ASSERT(!alu_busy); - end else begin - `ASSERT(fc_alu_sim == alu_sim); - `ASSERT(fc_alu_sim_immv == alu_sim_immv); - - if (!fc_alu_DV) - `ASSERT((!div_valid)&&(!div_busy)&&(!div_error)); - if (!fc_alu_M) - `ASSERT(!i_mem_rdbusy); - if (!fc_alu_ALU) - `ASSERT(!alu_busy); - if (!fc_alu_FP) - `ASSERT((!fpu_busy)&&(!fpu_error)); - if (alu_busy) - `ASSERT((fc_alu_op[3:1] == 3'h5) - ||(fc_alu_op[3:0] == 4'hc)); - if ((alu_busy)||(div_busy)||(fpu_busy)) - begin - `ASSERT(!i_mem_rdbusy); - `ASSERT((clear_pipeline) - ||(fc_alu_Rid[4:0] == alu_reg)); - if (alu_busy) - `ASSERT(fc_alu_wF == alu_wF); - if ((fc_alu_Rid[3:1] == 3'h7)&&(alu_wR) - &&(fc_alu_Rid[4:0] != { gie, 4'hf })) - `ASSERT(pending_sreg_write); - end else if (i_mem_rdbusy) - begin - if ($past(i_mem_rdbusy)) - `ASSERT(fc_alu_Rid[4] == f_mem_gie); - end - - //if ((div_busy)||(fpu_busy)) - // `ASSERT(alu_wR); - //else - if ((alu_busy)&&(alu_wR)) - `ASSERT(fc_alu_wR); - - if (alu_busy || i_mem_rdbusy || div_busy) - begin - if ((fc_alu_wR)&&(fc_alu_Rid[4:0] == { gie, CPU_PC_REG})) - begin - `ASSERT(!alu_phase); - end else - `ASSERT(f_alu_phase == alu_phase); - end - end - - end else if (!dbgv) // && wr_reg_ce - begin - `ASSERT(fc_alu_DV || (!div_valid)&&(!div_error)); - `ASSERT(fc_alu_ALU|| !alu_valid); - `ASSERT(fc_alu_M || !i_mem_valid); - `ASSERT(fc_alu_FP || (!fpu_valid)&&(!fpu_error)); - `ASSERT((!alu_busy)&&(!div_busy)&&(!fpu_busy)); - - if ((!alu_illegal)&&(fc_alu_cond[3])&&(fc_alu_wR)&&(fc_alu_ALU)) - `ASSERT(alu_wR); - if (!i_mem_valid) - `ASSERT(fc_alu_Rid[4:0] == alu_reg); - if (f_exwrite_cycle) - begin - `ASSERT(!alu_wR); - end else - `ASSERT((!alu_wR)||(fc_alu_wR == alu_wR)); - if (alu_valid) - `ASSERT(fc_alu_wF == alu_wF); - if (!fc_alu_wF) - `ASSERT(!wr_flags_ce); - - `ASSERT(!f_alu_branch); - end - - always @(posedge i_clk) - if (f_mem_pc && i_mem_rdbusy) - begin - // {{{ - `ASSERT(!OPT_PIPELINED || cc_invalid_for_dcd || !fc_alu_wR - || fc_alu_Rid[4:0] != { gie, CPU_CC_REG }); - `ASSERT(!mem_ce); - - if (OPT_PIPELINED && fc_alu_Rid[4:0] != { gie, CPU_PC_REG } - && (!OPT_LOCK || fc_alu_wR)) - `ASSERT(pending_sreg_write); - if ((!OPT_DCACHE)||(!OPT_MEMPIPE)) - begin - `ASSERT(!fc_alu_prepipe); - end else if ((i_mem_rdbusy && !f_exwrite_cycle) - &&(!$past(mem_ce))&&(!$past(mem_ce,2))) - `ASSERT(!fc_alu_prepipe); - // }}} - end else if (i_mem_rdbusy) - begin - `ASSERT(!pending_sreg_write); - // assert(!cc_invalid_for_dcd); - end - - // Ongoing memory operation check - // {{{ - always @(posedge i_clk) - if (i_mem_rdbusy) - begin - // In pipelined mode, this is an ongoing load operation - // Otherwise, mem_rdbusy == i_mem_busy and we have no idea - // what type of operation we are in - `ASSERT(!fc_alu_illegal); - `ASSERT(fc_alu_M); - `ASSERT(gie == alu_reg[4]); - if (fc_alu_rB) - `ASSERT(fc_alu_Bid[4:0] == f_addr_reg); - - if (!f_exwrite_cycle) - begin - `ASSERT(alu_reg == f_last_reg); - if (alu_reg == f_addr_reg) - `ASSERT(!op_pipe); - end - if (fc_alu_cond[3]) - `ASSERT(fc_alu_Rid[4:0] == alu_reg); - - if ((fc_alu_wR)&&(fc_alu_Rid[4:0] == { gie, CPU_PC_REG})) - begin - `ASSERT(!alu_phase); - end else - `ASSERT(f_alu_phase == alu_phase); - - if (f_exwrite_cycle) - begin - `ASSERT(!fc_alu_wR); - end else - `ASSERT(fc_alu_wR); - end else if ((i_mem_busy)&&(fc_alu_M) - &&(f_mem_outstanding > ((i_mem_valid || i_bus_err) ? 1:0)) - &&(!i_bus_err)) - begin // Ongoing store operation - // {{{ - `ASSERT(!fc_alu_illegal); - `ASSERT(fc_alu_M); - `ASSERT(!fc_alu_wR); - // }}} - end - // }}} - - always @(*) - if (!fc_alu_wR && i_mem_rdbusy) - begin - `ASSERT(OPT_LOCK); - `ASSERT(f_mem_outstanding == 1); - `ASSERT(f_mem_pc); - `ASSERT(!f_read_cycle); - `ASSERT(!cc_invalid_for_dcd); - `ASSERT(f_exwrite_cycle); - // `ASSERT(i_mem_wreg[3:0] == 4'hf); - `ASSERT(fc_alu_M); - `ASSERT(!pending_sreg_write); - `ASSERT(!alu_wR); - end else if (i_mem_rdbusy) - begin - `ASSERT(fc_alu_wR); - `ASSERT(!f_exwrite_cycle); - `ASSERT(f_read_cycle); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about the writeback stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_reset))&&($past(gie) != gie)) - `ASSERT(clear_pipeline); - - always @(*) - if (!IMPLEMENT_FPU) - begin - `ASSERT(!ifpu_err_flag); - `ASSERT(!ufpu_err_flag); - end - - always @(posedge i_clk) - if (dbgv) - begin - `ASSERT(wr_index == 3'h0); - `ASSERT(wr_gpreg_vl == $past(i_dbg_data)); - `ASSERT(wr_spreg_vl == $past(i_dbg_data)); - end - - always @(*) - if (i_mem_rdbusy || i_mem_valid) - begin - `ASSERT(wr_index == 3'h1); - if (i_mem_valid) - `ASSERT(wr_gpreg_vl == i_mem_result); - end - - always @(*) - if (alu_busy || alu_valid) - begin - `ASSERT(wr_index == 3'h2); - if (alu_valid) - begin - `ASSERT(wr_gpreg_vl == alu_result); - `ASSERT(wr_spreg_vl == alu_result); - end - end - - always @(*) - if (div_busy || div_valid || div_error) - begin - `ASSERT(wr_index == 3'h3); - if (div_valid) - `ASSERT(wr_gpreg_vl == div_result); - end - - always @(*) - if (fpu_busy || fpu_valid || fpu_error) - begin - `ASSERT(wr_index == 3'h4); - if (fpu_valid) - `ASSERT(wr_gpreg_vl == fpu_result); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(r_halted)) - begin - `ASSERT(!div_busy); - `ASSERT(!i_mem_rdbusy); - `ASSERT(!alu_busy); - `ASSERT(!div_valid); - `ASSERT(!i_mem_valid); - `ASSERT(!alu_valid); - end - - always @(*) - if (((wr_reg_ce)||(wr_flags_ce))&&(!dbgv)) - `ASSERT(!alu_illegal); - - always @(*) - if (!fc_alu_wR && (!OPT_LOCK || !f_mem_pc)) - `ASSERT(!i_mem_rdbusy); - - always @(*) - if (alu_illegal) - `ASSERT(!i_mem_rdbusy); - - always @(posedge i_clk) - if (wr_reg_ce && !$past(i_dbg_we)) - begin - if (!fc_alu_wR) - `ASSERT(OPT_LOCK && f_exwrite_cycle); - - // Since writes are asynchronous, they can create errors later - `ASSERT((!i_bus_err)||(!i_mem_valid)); - `ASSERT(!fpu_error); - `ASSERT(!div_error); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Clock enable checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!OPT_CLKGATE) - begin - assert(w_clken); - assert(o_clken); - end else if (!f_past_valid) - begin end // clken can be anything on the first clock - else if ($past(i_reset)) - begin - assert(w_clken != OPT_START_HALTED); - end else if ($past((!i_halt || !r_halted) && (!sleep || i_interrupt))) - begin - assert(w_clken); - end else if ($past((i_mem_busy && f_mem_outstanding > 0) || o_mem_ce)) - begin - assert(w_clken); - end else if (i_mem_busy || div_busy || alu_busy || fpu_busy) - begin - assert(o_clken); - end else if ($past((i_interrupt || pending_interrupt) && !i_halt)) - begin - assert(o_clken); - end else if (!sleep && !r_halted) - begin - assert(o_clken); - end - - // always @(posedge i_clk) - // if (f_past_valid && i_mem_busy) - // assert(!r_halted); - - always @(posedge i_clk) - if (!OPT_CLKGATE) - begin - assert(o_clken); - end else if (!f_past_valid) - begin - end else if (i_dbg_we || i_clear_cache || f_mem_outstanding > 0) - begin - assert(o_clken); - end else if (!i_halt && (i_interrupt || !sleep)) - assert(o_clken); - - - always @(posedge i_clk) - if (!i_reset && sleep) - begin - assert(!wr_reg_ce || dbgv); - assert(!i_mem_rdbusy); - end - - always @(posedge i_clk) - if (!i_reset && r_halted) - assert(!i_mem_rdbusy); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Low power checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // In low power mode, *nothing* should change unless we are doing - // something. - - generate if (OPT_LOWPOWER && OPT_PIPELINED) - begin : F_OPT_LOWPOWER_CHECK - wire [70:0] op_state; - - // - // OP* registers can only be expected to hold steady if - // pipelined. If not pipelined, many of these registers - // become aliases for the decode registers which will - // (of course) change from one clock to the next. - // - assign op_state = { op_valid_mem, op_valid_div, op_valid_alu, - op_valid_fpu, - op_opn, op_R, op_Rcc, op_Aid, - op_Bid, op_pc, - r_op_break, op_illegal }; - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && !$past(clear_pipeline) - && ($past(op_valid && !adf_ce_unconditional && !mem_ce) - ||($past(!op_valid && !dcd_ljmp) && !op_valid))) - begin - assert($stable(op_state)); - end - - always @(posedge i_clk) - if (f_past_valid && !op_valid) - begin - assert(r_op_F == 7'h00); - assert(!op_wR); - assert(!op_wF); - assert(!op_rA); - assert(!op_rB); - - assert(r_op_Av == 0); - assert(r_op_Bv == 0); - end - - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Step properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (f_past_valid && !i_reset && $past(!gie)) - assert(!stepped); - - always @(posedge i_clk) - if (f_past_valid && step && stepped) - begin - assert(!break_pending); - assert(!o_bus_lock); - end - - always @(posedge i_clk) - if (f_past_valid && !i_reset && !o_bus_lock && !$past(o_bus_lock) - && !$past(o_dbg_stall) && !o_dbg_stall) - begin - if (step && !stepped) - begin - `ASSERT(!i_mem_rdbusy); - `ASSERT(!div_busy); - `ASSERT(!alu_busy); - `ASSERT(!fpu_busy); - end - - if (wr_reg_ce || wr_flags_ce) - `ASSERT(!step || stepped); - end - - always @(posedge i_clk) - if (!i_reset &&(i_mem_rdbusy|| div_busy|| alu_busy || fpu_busy)) - assert(!r_halted); - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && i_mem_busy) - assert(!$rose(r_halted)); - - always @(posedge i_clk) - if (step && stepped) - begin - assert(!adf_ce_unconditional); - assert(!div_ce); - assert(!mem_ce); - assert(!fpu_ce); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Ad-hoc (unsorted) properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_mem_rdbusy)) - &&(!$past(i_mem_valid) - ||($past(i_mem_wreg[3:1] != 3'h7)))) - `ASSERT(!i_mem_valid || i_mem_wreg[4] == alu_gie); - - always @(posedge i_clk) - if (i_mem_valid) - `ASSERT(i_mem_wreg[4] == alu_gie); - - always @(posedge i_clk) - if (i_mem_rdbusy) - `ASSERT(alu_gie == f_mem_gie); - - always @(posedge i_clk) - if (f_mem_outstanding > 0) - `ASSERT(alu_gie == f_mem_gie); - - - - // Break instructions are not allowed to move past the op stage - always @(*) - if ((break_pending)||(op_break)) - `ASSERT((!alu_ce)&&(!mem_ce)&&(!div_ce)&&(!fpu_ce)); - - always @(*) - if (op_break) - `ASSERT((!alu_ce)&&(!mem_ce)&&(!div_ce)&&(!fpu_ce)); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset)) - &&($past(break_pending))&&(!break_pending)) - `ASSERT((clear_pipeline)||($past(clear_pipeline))); - - always @(*) - if ((o_break)||((alu_valid)&&(alu_illegal))) - begin - `ASSERT(!alu_ce); - `ASSERT(!mem_ce); - `ASSERT(!div_ce); - `ASSERT(!fpu_ce); - `ASSERT(!i_mem_rdbusy); - // The following two shouldn't be true, but will be true - // following a bus error - if (!i_bus_err) - begin - `ASSERT(!alu_busy); - `ASSERT(!div_busy); - `ASSERT(!fpu_busy); - end - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!$past(clear_pipeline))&& - ($past(div_busy))&&(!clear_pipeline)) - begin - `ASSERT($stable(alu_reg)); - `ASSERT(alu_reg[4] == alu_gie); - `ASSERT($stable(alu_pc)); - `ASSERT($stable(alu_phase)); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!i_reset) - &&(!$past(clear_pipeline))&&(!clear_pipeline) - &&(($past(div_busy))||($past(i_mem_rdbusy)))) - `ASSERT($stable(alu_gie)); - - always @(posedge i_clk) - if (i_mem_rdbusy && f_mem_outstanding > 0) - `ASSERT(!new_pc); - - always @(posedge i_clk) - if ((wr_reg_ce)&&((wr_write_cc)||(wr_write_pc))) - `ASSERT(wr_spreg_vl == wr_gpreg_vl); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(clear_pipeline))&&(!$past(i_reset)) - &&($past(op_valid))&&($past(op_illegal))&&(!op_illegal)) - `ASSERT(alu_illegal); - - always @(*) - if ((OPT_PIPELINED)&&(alu_valid)&&(alu_wR)&&(!clear_pipeline) - &&(alu_reg[3:1] == 3'h7) - &&(alu_reg[4:0] != { gie, CPU_PC_REG })) - `ASSERT(pending_sreg_write); - - always @(posedge i_clk) - if ((OPT_PIPELINED)&&(i_mem_valid || i_mem_rdbusy) - &&(f_last_reg[3:1] == 3'h7) - &&(!f_exwrite_cycle - && f_last_reg[4:0] != { gie, CPU_PC_REG })) - begin - `ASSERT(pending_sreg_write); - end else if ((OPT_PIPELINED)&&(OPT_DCACHE) - && i_mem_valid - &&($past(i_mem_rdbusy)) - &&($past(i_mem_rdbusy,2))) - `ASSERT((i_mem_wreg[3:1] != 3'h7) - ||f_exwrite_cycle - ||(i_mem_wreg == { gie, CPU_PC_REG}) - ||(pending_sreg_write)); - - always @(*) - if ((op_valid_alu)||(op_valid_div)||(op_valid_mem)||(op_valid_fpu)) - `ASSERT(op_valid); - - always @(*) - if (!OPT_PIPELINED) - begin - if (op_valid) - begin - `ASSERT(!dcd_valid); - `ASSERT(!i_mem_busy || f_mem_outstanding == 0); - `ASSERT(!alu_busy); - `ASSERT(!div_busy); - `ASSERT((!wr_reg_ce)||(dbgv)); - `ASSERT(!wr_flags_ce); - end - end - - always @(posedge i_clk) - if ((!OPT_PIPELINED)&&(f_past_valid)) - begin - if (op_valid) - `ASSERT($stable(f_dcd_insn_word)); - end - - always @(posedge i_clk) - if ((alu_ce)||(div_ce)||(fpu_ce)) - `ASSERT(adf_ce_unconditional); - - always @(posedge i_clk) - if ((!clear_pipeline)&&(master_ce)&&(op_ce)&&(op_valid)) - begin - if (op_valid_mem) - begin - `ASSERT((mem_ce)||(!set_cond)); - end else begin - `ASSERT(!master_stall); - if ((set_cond)&&(op_valid_div)) - `ASSERT(div_ce||pending_sreg_write); - if (!op_valid_alu) - `ASSERT(!alu_ce); - end - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Debug port read properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - - generate if (OPT_DBGPORT) - begin : CHK_DBGPORT_READS - reg [31:0] f_dbg_check; - - // o_dbg_reg -- Reading from the debugging interface - if (OPT_DISTRIBUTED_REGS) - begin : F_CHK_DISTRIBUTED_RAM - // {{{ - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_halt))&&(!$past(i_dbg_we))) - begin - if ($past(i_dbg_rreg[3:1]) != 3'h7) - `ASSERT(o_dbg_reg == $past(regset[i_dbg_rreg])); - if ($past(i_dbg_rreg[4:0]) == 5'h0f) - `ASSERT(o_dbg_reg[AW+1:0] == $past({ ipc[(AW+1):2], ihalt_phase, 1'b0})); - if ($past(i_dbg_rreg[4:0]) == 5'h1f) - `ASSERT(o_dbg_reg[AW+1:0] == $past({ upc[(AW+1):2], uhalt_phase, 1'b0})); - if ($past(i_dbg_rreg[4:0]) == 5'h0e) - begin - `ASSERT(o_dbg_reg[15:6] == $past(w_iflags[15:6])); - `ASSERT(o_dbg_reg[ 4:0] == $past(w_iflags[ 4:0])); - end - - if ($past(i_dbg_rreg[4:0]) == 5'h1e) - begin - `ASSERT(o_dbg_reg[15:6] == $past(w_uflags[15:6])); - `ASSERT(o_dbg_reg[ 4:0] == $past(w_uflags[ 4:0])); - end - - if ($past(i_dbg_rreg[3:0]) == 4'he) - begin - `ASSERT(o_dbg_reg[15] == 1'b0); - `ASSERT(o_dbg_reg[31:23] == w_cpu_info); - `ASSERT(o_dbg_reg[CPU_GIE_BIT] == $past(i_dbg_rreg[4])); - end - end - // }}} - end else begin : F_CHK_NO_DISTRIBUTED_RAM - // {{{ - always @(posedge i_clk) - if (f_past_valid&&$past(f_past_valid) - && $past(i_halt)&&$past(i_halt,2) - &&(!$past(i_dbg_we))) - begin - if ($past(i_dbg_rreg[3:1],2) != 3'h7) - `ASSERT(o_dbg_reg - == $past(regset[i_dbg_rreg],2)); - end - // }}} - end - - - if (OPT_USERMODE) - begin : CHK_USER - always @(*) - begin - f_dbg_check = regset[i_dbg_rreg]; - case(i_dbg_rreg) - 5'h0e: begin - f_dbg_check[15:0] = w_iflags; - f_dbg_check[31:23] = w_cpu_info; - f_dbg_check[CPU_GIE_BIT] <= 1'b0; - end - 5'h0f: f_dbg_check[(AW+1):0] - = { ipc[(AW+1):2], ihalt_phase, 1'b0 }; - 5'h1e: begin - f_dbg_check[15:0] = w_uflags; - f_dbg_check[31:23] = w_cpu_info; - f_dbg_check[CPU_GIE_BIT] <= 1'b1; - end - 5'h1f: f_dbg_check[(AW+1):0] - = { upc[(AW+1):2], uhalt_phase, 1'b0 }; - default: - f_dbg_check = regset[i_dbg_rreg]; - endcase - end - end else begin : NO_USER - always @(*) - begin - if (OPT_DISTRIBUTED_REGS) - f_dbg_check = regset[i_dbg_rreg]; - else - f_dbg_check = 0; - case(i_dbg_rreg[3:0]) - 4'h0e: begin - f_dbg_check[15:0] = w_iflags; - f_dbg_check[31:23] = w_cpu_info; - f_dbg_check[CPU_GIE_BIT] <= 1'b0; - end - 4'h0f: f_dbg_check[(AW+1):0] - = { ipc[(AW+1):2], ihalt_phase, 1'b0 }; - default: - f_dbg_check = regset[i_dbg_rreg[3:0]]; - endcase - end - end - - if (OPT_DISTRIBUTED_REGS) - begin - always @(posedge i_clk) - if (!i_reset && !$past(i_reset)) - assert(o_dbg_reg == $past(f_dbg_check)); - end else begin - always @(posedge i_clk) - if (!i_reset && !$past(i_reset) && !$past(i_reset,2)) - assert(o_dbg_reg == $past(f_dbg_check,2)); - end - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover statements - // {{{ - //////////////////////////////////////////////////////////////////////// - // - always @(posedge i_clk) - begin - cover(!i_reset); - cover(!i_halt); - cover(!i_reset && !i_halt); - end - - always @(posedge i_clk) - if (!i_halt && !i_reset) - begin - cover(i_pf_valid && i_pf_illegal); - cover(i_pf_valid && !i_pf_illegal); - - cover(dcd_valid && dcd_illegal); - cover(dcd_valid && !dcd_illegal); - - cover(op_valid && !op_illegal); - cover(op_valid && op_illegal); - cover(op_valid && !op_illegal && op_ce); - cover(op_valid && op_illegal && op_ce); - - cover(alu_valid); - cover(div_valid); - cover(o_mem_ce); - cover(i_mem_valid); - - cover(wr_reg_ce); - - cover(gie); - end - - always @(posedge i_clk) - if (!i_halt && !i_reset && !$past(i_reset)) - begin - cover(i_interrupt && !alu_phase && !o_bus_lock); - cover(alu_illegal); - cover( gie && w_switch_to_interrupt); - cover(!gie && w_release_from_interrupt); - - // Cover an illegal instruction - cover(alu_illegal); - cover(alu_illegal && !clear_pipeline); - - - // Cover a break instruction - cover((master_ce)&&(break_pending)&&(!break_en)); - cover(o_break); -// if (master_ce && (break_en || break_pending)) -// `ASSERT(!wr_reg_ce); - - - cover(gie); - cover(step); - cover(step && w_switch_to_interrupt); - cover(step && w_switch_to_interrupt && !i_interrupt); - end - - always @(posedge i_clk) - if (!i_halt && !i_reset && !$past(i_reset)) - begin - cover(step); - cover(step && wr_reg_ce); - cover($fell(step) && $stable(!i_reset && !i_halt)); - cover($past(step && !i_reset && !i_halt)); - cover($past(step && !i_reset && !i_halt,2)); - cover(!o_bus_lock && alu_ce && step); - cover(user_step && !gie); - cover(user_step && gie); - cover(user_step && gie && wr_reg_ce); - - // Cover a division by zero - cover(!OPT_DIV || div_busy); - cover(!OPT_DIV || div_error); - cover(!OPT_DIV || div_valid); - end - - generate if (OPT_DIV) - begin : F_DIVIDE - always @(posedge i_clk) - if (!i_halt && !i_reset && !$past(i_reset)) - begin - // Cover a division by zero - cover(div_busy); - cover(div_error); - cover(div_valid); - end - end endgenerate - - generate if (OPT_LOCK) - begin : F_CVR_LOCK - - always @(posedge i_clk) - if (f_past_valid && !i_reset - && !$past(i_reset || clear_pipeline)) - begin - cover($rose(o_bus_lock)); - cover($fell(o_bus_lock)); - cover($fell(o_bus_lock) - && !$past(i_bus_err || div_error || alu_illegal)); - end - - end else begin - - always @(*) - `ASSERT(!o_bus_lock); - - end endgenerate - - always @(posedge i_clk) - if (!i_halt && !i_reset && !$past(i_reset) && wr_reg_ce) - begin - `ASSERT(!alu_illegal); - end - - always @(posedge i_clk) - if (!i_halt && !i_reset && wr_reg_ce) - begin - cover(o_bus_lock); - - // Cover the switch to interrupt - cover(i_interrupt); - cover(i_interrupt && !alu_phase); - cover(i_interrupt && !o_bus_lock); - cover((i_interrupt)&&(!alu_phase)&&(!o_bus_lock)); - - // Cover a "step" instruction - // - cover(((alu_pc_valid)||(mem_pc_valid)) - &&(step)&&(!alu_phase)&&(!o_bus_lock)); - // `ASSERT(!(((alu_pc_valid)||(mem_pc_valid)) - // &&(step)&&(!alu_phase)&&(!o_bus_lock))); - - // Cover a bus error - cover(i_bus_err); - - // Cover a TRAP instruction to the CC register - cover(!alu_gie && !wr_spreg_vl[CPU_GIE_BIT] - &&(wr_reg_id[4])&&(wr_write_cc)); - - // Cover an AXI lock return branch - cover(i_mem_valid && f_exwrite_cycle && !f_read_cycle); - end - - // Cover all the various reasons to switch to an interrupt - // {{{ - always @(posedge i_clk) - if ((f_past_valid && !i_reset && !$past(i_reset) && !i_halt) && gie) - begin - cover((pending_interrupt) - &&(!alu_phase)&&(!o_bus_lock)&&(!i_mem_busy)); - - cover(div_error); - // cover(fpu_error); - cover(i_bus_err); - cover(wr_reg_ce && !wr_spreg_vl[CPU_GIE_BIT] - && wr_reg_id[4] && wr_write_cc); - - if (!clear_pipeline && !w_switch_to_interrupt) - begin - cover(pending_interrupt); - - cover(i_interrupt); - - cover(mem_ce && step); - cover(break_pending && !adf_ce_unconditional); - cover(adf_ce_unconditional && op_illegal); - cover(adf_ce_unconditional && step); - end - - `ASSERT(!adf_ce_unconditional || !break_pending); - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Careless assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Once asserted, an interrupt will stay asserted while the CPU is - // in user mode - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_interrupt && (gie || !i_mem_busy)))) - assume(i_interrupt); - // }}} -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipcounter.v b/delete_later/rtl/cpu/zipcounter.v deleted file mode 100644 index c254032..0000000 --- a/delete_later/rtl/cpu/zipcounter.v +++ /dev/null @@ -1,239 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipcounter.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// A very, _very_ simple counter. It's purpose doesn't really -// include rollover, but it will interrupt on rollover. It can be set, -// although my design concept is that it can be reset. It cannot be -// halted. It will always produce interrupts--whether or not they are -// handled interrupts is another question--that's up to the interrupt -// controller. -// -// My intention is to use this counter for process accounting: I should -// be able to use this to count clock ticks of processor time assigned to -// each task by resetting the counter at the beginning of every task -// interval, and reading the result at the end of the interval. As long -// as the interval is less than 2^32 clocks, there should be no problem. -// Similarly, this can be used to measure CPU wishbone bus stalls, -// prefetch stalls, or other CPU stalls (i.e. stalling as part of a JMP -// instruction, or a read from the condition codes following a write). -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipcounter #( - // {{{ - parameter BW = 32 -`ifdef FORMAL - , localparam F_LGDEPTH = 2 -`endif - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, i_event, - // Wishbone inputs - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [(BW-1):0] i_wb_data, - // Wishbone outputs - output wire o_wb_stall, - output reg o_wb_ack, - output reg [(BW-1):0] o_wb_data, - // Interrupt line - output reg o_int - // }}} - ); - - // o_int, o_wb_data - // {{{ - initial o_int = 0; - initial o_wb_data = 32'h00; - always @(posedge i_clk) - if (i_reset) - { o_int, o_wb_data } <= 0; - else if ((i_wb_stb)&&(i_wb_we)) - { o_int, o_wb_data } <= { 1'b0, i_wb_data }; - else if (i_event) - { o_int, o_wb_data } <= o_wb_data+{{(BW-1){1'b0}},1'b1}; - else - o_int <= 1'b0; - // }}} - - // o_wb_ack - // {{{ - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_ack <= 1'b0; - else - o_wb_ack <= i_wb_stb; - // }}} - assign o_wb_stall = 1'b0; - - - // Make verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - //////////////////////////////////////////////////////////////////////// - // - // Assumptions about our inputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus interface properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // We never stall the bus - always @(*) - assert(!o_wb_stall); - - // We always ack every transaction on the following clock - always @(posedge i_clk) - assert(o_wb_ack == ((f_past_valid)&&(!$past(i_reset)) - &&($past(i_wb_stb)))); - - wire [(F_LGDEPTH-1):0] f_nreqs, f_nacks, f_outstanding; - - fwb_slave #( - // {{{ - .AW(1), .F_MAX_STALL(0), - .F_MAX_ACK_DELAY(1), .F_LGDEPTH(F_LGDEPTH) - // }}} - ) fwbi( - // {{{ - i_clk, i_reset, - i_wb_cyc, i_wb_stb, i_wb_we, 1'b0, i_wb_data, 4'hf, - o_wb_ack, o_wb_stall, o_wb_data, 1'b0, - f_nreqs, f_nacks, f_outstanding - // }}} - ); - - always @(*) - if ((o_wb_ack)&&(i_wb_cyc)) - begin - assert(f_outstanding==1); - end else - assert(f_outstanding == 0); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assumptions about our outputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Drop the interrupt line and reset the counter on any reset - // {{{ - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assert((!o_int)&&(o_wb_data == 0)); - // }}} - - // Clear the interrupt and set the counter on any write (other than - // during a reset) - // {{{ - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset)) - &&($past(i_wb_stb))&&($past(i_wb_we))) - assert((!o_int)&&(o_wb_data == $past(i_wb_data))); - // }}} - - // Normal logic of the routine itself - // {{{ - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!$past(i_wb_stb))) - begin - if (!$past(i_event)) - begin - // If the CE line wasn't set on the last clock, then the - // counter must not change, and the interrupt line must - // be low. - assert(o_wb_data == $past(o_wb_data)); - assert(!o_int); - end else // if ($past(i_event)) - begin - // Otherwise, if the CE line was high on the last clock, - // then our counter should have incremented. - assert(o_wb_data == $past(o_wb_data) + 1'b1); - - // Likewise, if the counter rolled over, then the - // output interrupt, o_int, should be true. - if ($past(o_wb_data)=={(BW){1'b1}}) - begin - assert(o_int); - end else - // In all other circumstances it should be clear - assert(!o_int); - end - end - // ?}}} - - // The output interrupt should never be true two clocks in a row - // {{{ - always @(posedge i_clk) - if ((f_past_valid)&&($past(o_int))) - assert(!o_int); - // }}} - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipdma.v b/delete_later/rtl/cpu/zipdma.v deleted file mode 100644 index a1260ec..0000000 --- a/delete_later/rtl/cpu/zipdma.v +++ /dev/null @@ -1,440 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipdma.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: (Upgraded) Wishbone DMA controller for the ZipCPU -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipdma #( - // {{{ - parameter ADDRESS_WIDTH=30, LGMEMLEN = 10, - parameter LGDMALENGTH=ADDRESS_WIDTH, - parameter SLV_WIDTH=32, - parameter BUS_WIDTH=512, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter [0:0] OPT_LOWPOWER = 1'b0, - parameter [0:0] OPT_REGISTER_RAM = 1'b0, - localparam AW=ADDRESS_WIDTH-$clog2(BUS_WIDTH/8) - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Slave port - // {{{ - // Slave/control wishbone inputs - input wire i_swb_cyc, i_swb_stb, i_swb_we, - input wire [1:0] i_swb_addr, - input wire [SLV_WIDTH-1:0] i_swb_data, - input wire [SLV_WIDTH/8-1:0] i_swb_sel, - // Slave/control wishbone outputs - output wire o_swb_stall, - output wire o_swb_ack, - output wire [SLV_WIDTH-1:0] o_swb_data, - // }}} - // Master/DMA port - // {{{ - output wire o_mwb_cyc, o_mwb_stb, o_mwb_we, - output wire [AW-1:0] o_mwb_addr, - output wire [BUS_WIDTH-1:0] o_mwb_data, - output wire [BUS_WIDTH/8-1:0] o_mwb_sel, - // Master/DMA wishbone responses from the bus - input wire i_mwb_stall, i_mwb_ack, - input wire [BUS_WIDTH-1:0] i_mwb_data, - input wire i_mwb_err, - // }}} - // The interrupt device interrupt lines - input wire [31:0] i_dev_ints, - // An interrupt to be set upon completion - output wire o_interrupt - // }}} - ); - - // Local declarations - // {{{ - localparam FIFO_WIDTH = BUS_WIDTH+$clog2(BUS_WIDTH/8)+2; - localparam LGFIFO = LGMEMLEN-$clog2(BUS_WIDTH/8); - - wire dma_request, dma_abort, - dma_busy, dma_err; - wire [ADDRESS_WIDTH-1:0] dma_src, dma_dst, - read_addr, write_addr; - wire [LGDMALENGTH-1:0] dma_length, remaining_len; - wire [LGMEMLEN:0] dma_transferlen; - wire dma_trigger; - - wire mm2s_request, s2mm_request; - wire mm2s_busy, s2mm_busy; - wire mm2s_err, s2mm_err; - wire mm2s_inc, s2mm_inc; - wire [1:0] mm2s_size, s2mm_size; - wire [ADDRESS_WIDTH-1:0] mm2s_addr, s2mm_addr; - wire [LGMEMLEN:0] mm2s_transferlen, s2mm_transferlen; - - wire mm2s_rd_cyc, mm2s_rd_stb, mm2s_rd_we, - mm2s_rd_stall, mm2s_rd_ack, mm2s_rd_err; - wire [AW-1:0] mm2s_rd_addr; - wire [BUS_WIDTH-1:0] mm2s_rd_data; - wire [BUS_WIDTH/8-1:0] mm2s_rd_sel; - - wire mm2s_valid, mm2s_ready, mm2s_last; - wire [BUS_WIDTH-1:0] mm2s_data; - wire [$clog2(BUS_WIDTH/8):0] mm2s_bytes; - - wire rx_valid, rx_ready, rx_last; - wire [BUS_WIDTH-1:0] rx_data; - wire [$clog2(BUS_WIDTH/8):0] rx_bytes; - - wire tx_valid, tx_ready, tx_last; - wire [BUS_WIDTH-1:0] tx_data; - wire [$clog2(BUS_WIDTH/8):0] tx_bytes; - - wire sfifo_full, sfifo_empty; - wire [LGFIFO:0] ign_sfifo_fill; - - wire s2mm_valid, s2mm_ready, s2mm_last; - wire [BUS_WIDTH-1:0] s2mm_data; - wire [$clog2(BUS_WIDTH/8):0] s2mm_bytes; - - wire s2mm_wr_cyc, s2mm_wr_stb, s2mm_wr_we, - s2mm_wr_stall, s2mm_wr_ack, s2mm_wr_err; - wire [AW-1:0] s2mm_wr_addr; - wire [BUS_WIDTH-1:0] s2mm_wr_data; - wire [BUS_WIDTH/8-1:0] s2mm_wr_sel; - - wire wb_cyc, wb_stb, wb_we, - wb_stall, wb_ack, wb_err; - wire [AW-1:0] wb_addr; - wire [BUS_WIDTH-1:0] wb_data, wb_idata; - wire [BUS_WIDTH/8-1:0] wb_sel; - // }}} - - - zipdma_ctrl #( - // {{{ - .ADDRESS_WIDTH(ADDRESS_WIDTH), - .LGMEMLEN(LGMEMLEN), - .LGDMALENGTH(ADDRESS_WIDTH), - .OPT_LOWPOWER(OPT_LOWPOWER) - // }}} - ) u_controller ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // Slave WB control port - // {{{ - // Slave/control wishbone inputs - .i_cyc(i_swb_cyc), .i_stb(i_swb_stb), .i_we(i_swb_we), - .i_addr(i_swb_addr), - .i_data(i_swb_data), .i_sel(i_swb_sel), - // Slave/control wishbone outputs - .o_stall(o_swb_stall), - .o_ack(o_swb_ack), .o_data(o_swb_data), - // }}} - // Internal DMA controls - // {{{ - .o_dma_request(dma_request), .o_dma_abort(dma_abort), - .i_dma_busy(dma_busy), .i_dma_err(dma_err), - .o_src_addr(dma_src), .o_dst_addr(dma_dst), - .o_length(dma_length), .o_transferlen(dma_transferlen), - .o_mm2s_inc(mm2s_inc), .o_mm2s_size(mm2s_size), - .o_s2mm_inc(s2mm_inc), .o_s2mm_size(s2mm_size), - // - .o_trigger(dma_trigger), - // - .i_current_src(read_addr), - .i_current_dst(write_addr), - .i_remaining_len(remaining_len), - // }}} - .i_dma_int(i_dev_ints), .o_interrupt(o_interrupt) - // }}} - ); - - zipdma_fsm #( - // {{{ - .ADDRESS_WIDTH(ADDRESS_WIDTH), - .LGDMALENGTH(ADDRESS_WIDTH), - .LGSUBLENGTH(LGMEMLEN) - // }}} - ) u_dma_fsm ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_soft_reset(dma_abort), - // DMA control - // {{{ - .i_dma_request(dma_request), - .o_dma_busy(dma_busy), .o_dma_err(dma_err), - .i_src_addr(dma_src), .i_dst_addr(dma_dst), - .i_length(dma_length), .i_transferlen(dma_transferlen), - .i_trigger(dma_trigger), - .o_remaining_len(remaining_len), - // }}} - // Downstream MM2S configuration - // {{{ - .o_mm2s_request(mm2s_request), - .i_mm2s_busy(mm2s_busy), - .i_mm2s_err(mm2s_err), - .i_mm2s_inc(mm2s_inc), - .o_mm2s_addr(mm2s_addr), - .o_mm2s_transferlen(mm2s_transferlen), - // }}} - // Downstream S2MM configuration - // {{{ - .o_s2mm_request(s2mm_request), - .i_s2mm_busy(s2mm_busy), - .i_s2mm_err(s2mm_err), - .i_s2mm_inc(s2mm_inc), - .o_s2mm_addr(s2mm_addr), - .o_s2mm_transferlen(s2mm_transferlen) - // }}} - // }}} - ); - - zipdma_mm2s #( - // {{{ - .ADDRESS_WIDTH(ADDRESS_WIDTH), - .BUS_WIDTH(BUS_WIDTH), - .LGLENGTH(LGMEMLEN), - .OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN), - .OPT_LOWPOWER(OPT_LOWPOWER) - // }}} - ) u_mm2s ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || dma_abort), - // DMA control - // {{{ - .i_request(mm2s_request), - .o_busy(mm2s_busy), .o_err(mm2s_err), - .i_inc(mm2s_inc), .i_size(mm2s_size), - .i_transferlen(mm2s_transferlen), - .i_addr(mm2s_addr), - // }}} - // Wishbone master interface - // {{{ - .o_rd_cyc(mm2s_rd_cyc), - .o_rd_stb(mm2s_rd_stb), - .o_rd_we(mm2s_rd_we), - .o_rd_addr(mm2s_rd_addr), - .o_rd_data(mm2s_rd_data), - .o_rd_sel(mm2s_rd_sel), - // - .i_rd_stall(mm2s_rd_stall), - .i_rd_ack(mm2s_rd_ack), - .i_rd_data(wb_idata), - .i_rd_err(mm2s_rd_err), - // }}} - // MM2S Stream interface - // {{{ - .M_VALID(mm2s_valid), - .M_READY(mm2s_ready), - .M_DATA(mm2s_data), - .M_BYTES(mm2s_bytes), - .M_LAST(mm2s_last) - // }}} - // }}} - ); - - zipdma_rxgears #( - // {{{ - .BUS_WIDTH(BUS_WIDTH), - .OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN) - // }}} - ) u_rxgears ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), .i_soft_reset(dma_abort), - // - .S_VALID(mm2s_valid), .S_READY(mm2s_ready), - .S_DATA(mm2s_data), .S_BYTES(mm2s_bytes), - .S_LAST(mm2s_last), - // - .M_VALID(rx_valid), .M_READY(rx_ready), - .M_DATA(rx_data), .M_BYTES(rx_bytes), - .M_LAST(rx_last) - // }}} - ); - - sfifo #( - // {{{ - .BW(FIFO_WIDTH), - .LGFLEN(LGFIFO), - .OPT_ASYNC_READ(!OPT_REGISTER_RAM), - .OPT_WRITE_ON_FULL(1'b0), - .OPT_READ_ON_EMPTY(1'b0) - // }}} - ) u_sfifo ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || dma_abort), - // - .i_wr(rx_valid), .i_data({ rx_last, rx_bytes, rx_data }), - .o_full(sfifo_full), .o_fill(ign_sfifo_fill), - // - .i_rd(tx_ready), .o_data({ tx_last, tx_bytes, tx_data }), - .o_empty(sfifo_empty) - // }}} - ); - - assign rx_ready = !sfifo_full; - assign tx_valid = !sfifo_empty; - - zipdma_txgears #( - // {{{ - .BUS_WIDTH(BUS_WIDTH), - .OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN) - // }}} - ) u_txgears ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_soft_reset(dma_abort), .i_size(s2mm_size), - // Incoming stream - // {{{ - .S_VALID(tx_valid), .S_READY(tx_ready), - .S_DATA(tx_data), .S_BYTES(tx_bytes), - .S_LAST(tx_last), - // }}} - // Outgoing stream to S2MM - // {{{ - .M_VALID(s2mm_valid), .M_READY(s2mm_ready), - .M_DATA(s2mm_data), .M_BYTES(s2mm_bytes), - .M_LAST(s2mm_last) - // }}} - // }}} - ); - - zipdma_s2mm #( - // {{{ - .ADDRESS_WIDTH(ADDRESS_WIDTH), - .BUS_WIDTH(BUS_WIDTH), - .OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN), - .LGPIPE(LGMEMLEN) - // }}} - ) u_s2mm ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || dma_abort), - // S2MM configuration - // {{{ - .i_request(s2mm_request), - .o_busy(s2mm_busy), .o_err(s2mm_err), - .i_inc(s2mm_inc), .i_size(s2mm_size), - .i_addr(s2mm_addr), - // }}} - // Stream data source - // {{{ - .S_VALID(s2mm_valid), .S_READY(s2mm_ready), - .S_DATA(s2mm_data), .S_BYTES(s2mm_bytes), - .S_LAST(s2mm_last), - // }}} - // Outgoing Wishbone interface - // {{{ - .o_wr_cyc(s2mm_wr_cyc), - .o_wr_stb(s2mm_wr_stb), - .o_wr_we(s2mm_wr_we), - .o_wr_addr(s2mm_wr_addr), - .o_wr_data(s2mm_wr_data), - .o_wr_sel(s2mm_wr_sel), - // - .i_wr_stall(s2mm_wr_stall), - .i_wr_ack(s2mm_wr_ack), - .i_wr_data(wb_idata), - .i_wr_err(s2mm_wr_err) - // }}} - // }}} - ); - - wbarbiter #( - // {{{ - .DW(BUS_WIDTH), .AW(AW), .OPT_ZERO_ON_IDLE(OPT_LOWPOWER) - // }}} - ) u_arbiter ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_a_cyc(mm2s_rd_cyc), .i_a_stb(mm2s_rd_stb), - .i_a_we(mm2s_rd_we), .i_a_adr(mm2s_rd_addr), - .i_a_dat((OPT_LOWPOWER) ? mm2s_rd_data : s2mm_wr_data), - .i_a_sel(mm2s_rd_sel), - .o_a_stall(mm2s_rd_stall), .o_a_ack(mm2s_rd_ack), - .o_a_err(mm2s_rd_err), - // - .i_b_cyc(s2mm_wr_cyc), .i_b_stb(s2mm_wr_stb), - .i_b_we(s2mm_wr_we), .i_b_adr(s2mm_wr_addr), - .i_b_dat(s2mm_wr_data), .i_b_sel(s2mm_wr_sel), - .o_b_stall(s2mm_wr_stall), .o_b_ack(s2mm_wr_ack), - .o_b_err(s2mm_wr_err), - // - .o_cyc(wb_cyc), .o_stb(wb_stb), - .o_we(wb_we), .o_adr(wb_addr), - .o_dat(wb_data), .o_sel(wb_sel), - .i_stall(wb_stall), .i_ack(wb_ack), - .i_err(wb_err) - // }}} - ); - - assign o_mwb_cyc = wb_cyc; - assign o_mwb_stb = wb_stb; - assign o_mwb_we = wb_we; - assign o_mwb_addr = wb_addr; - assign o_mwb_data = wb_data; - assign o_mwb_sel = wb_sel; - assign wb_stall = i_mwb_stall; - assign wb_ack = i_mwb_ack; - assign wb_idata = i_mwb_data; - assign wb_err = i_mwb_err; - - assign read_addr = { mm2s_rd_addr, {($clog2(BUS_WIDTH/8)){1'b0}} }; - assign write_addr = { s2mm_wr_addr, {($clog2(BUS_WIDTH/8)){1'b0}} }; - - // Make verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, ign_sfifo_fill, mm2s_rd_data, rx_ready, - s2mm_transferlen }; - // verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipdma_ctrl.v b/delete_later/rtl/cpu/zipdma_ctrl.v deleted file mode 100644 index a05ae39..0000000 --- a/delete_later/rtl/cpu/zipdma_ctrl.v +++ /dev/null @@ -1,343 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipdma_ctrl.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: ZipDMA -- Simply handles the control requests for the ZipDMA. -// Status reads and control writes using a 32-bit Wishbone bus -// interface are handled here. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipdma_ctrl #( - // {{{ - parameter ADDRESS_WIDTH=30, LGMEMLEN = 10, - parameter SLV_WIDTH=32, - // BUS_WIDTH=512, - parameter LGDMALENGTH = ADDRESS_WIDTH, - parameter ABORT_KEY = 32'h41425254, - parameter [0:0] OPT_LOWPOWER = 1'b0, - // == { 8'd65, 8'd66, 8'd82, 8'd84 }, "ABRT", - localparam AW = ADDRESS_WIDTH - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Slave / control port - // {{{ - input wire i_cyc, i_stb, i_we, - input wire [1:0] i_addr, - input wire [SLV_WIDTH-1:0] i_data, - input wire [SLV_WIDTH/8-1:0] i_sel, - // - output wire o_stall, - output reg o_ack, - output reg [SLV_WIDTH-1:0] o_data, - // }}} - // DMA control wires and feedback - // {{{ - output reg o_dma_request, - output reg o_dma_abort, - input wire i_dma_busy, i_dma_err, - output reg [AW-1:0] o_src_addr, - output reg [AW-1:0] o_dst_addr, - output reg [LGDMALENGTH-1:0] o_length, - output reg [LGMEMLEN:0] o_transferlen, - output reg o_mm2s_inc, o_s2mm_inc, - output reg [1:0] o_mm2s_size,o_s2mm_size, - // - output reg o_trigger, - // - input wire [AW-1:0] i_current_src, - input wire [AW-1:0] i_current_dst, - input wire [LGDMALENGTH-1:0] i_remaining_len, - // }}} - input wire [31:0] i_dma_int, - output reg o_interrupt - // }}} - ); - - // Local declarations - // {{{ - reg int_trigger, r_err, r_zero_len, r_busy; - reg [4:0] int_sel; - reg [SLV_WIDTH-1:0] next_src, next_dst, next_len, next_tlen, - w_control_reg; - // }}} - - // o_ack - // {{{ - initial o_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_ack <= 1'b0; - else - o_ack <= i_stb; - // }}} - - assign o_stall = 1'b0; - - // w_control_reg - // {{{ - always @(*) - begin - w_control_reg = 0; - w_control_reg[31] = i_dma_busy; - w_control_reg[30] = r_err || i_dma_err; - w_control_reg[29] = int_trigger; - w_control_reg[28:24] = int_sel; - // - w_control_reg[LGMEMLEN:0] = o_transferlen; - // - w_control_reg[22] = !o_s2mm_inc; - w_control_reg[21:20] = o_s2mm_size; - // - w_control_reg[18] = !o_mm2s_inc; - w_control_reg[17:16] = o_mm2s_size; - end - // }}} - - // o_data - // {{{ - always @(posedge i_clk) - if (!OPT_LOWPOWER || (i_stb && !o_stall && !i_we)) - begin - o_data <= 0; - case(i_addr) - 2'b00: o_data <= w_control_reg; - 2'b01: o_data[AW-1:0] <= (i_dma_busy) ? i_current_src : o_src_addr; - 2'b10: o_data[AW-1:0] <= (i_dma_busy) ? i_current_dst : o_dst_addr; - 2'b11: o_data[LGDMALENGTH-1:0] <= (i_dma_busy) ? i_remaining_len : o_length; - endcase - end - // }}} - - // o_trigger - // {{{ - always @(posedge i_clk) - if (i_reset || o_dma_abort || i_dma_err || !i_dma_busy) - o_trigger <= 1'b0; - else if (!int_trigger) - o_trigger <= 1'b1; - else - o_trigger <= i_dma_int[int_sel]; - // }}} - - // next_src - // {{{ - always @(*) - begin - next_src = 32'h00; - next_src[AW-1:0] = o_src_addr; - - if (i_sel[0]) next_src[ 7: 0] = i_data[ 7: 0]; - if (i_sel[1]) next_src[15: 8] = i_data[15: 8]; - if (i_sel[2]) next_src[23:16] = i_data[23:16]; - if (i_sel[3]) next_src[31:24] = i_data[31:24]; - end - // }}} - - // next_dst - // {{{ - always @(*) - begin - next_dst = 32'h00; - next_dst[AW-1:0] = o_dst_addr; - - if (i_sel[0]) next_dst[ 7: 0] = i_data[ 7: 0]; - if (i_sel[1]) next_dst[15: 8] = i_data[15: 8]; - if (i_sel[2]) next_dst[23:16] = i_data[23:16]; - if (i_sel[3]) next_dst[31:24] = i_data[31:24]; - end - // }}} - - // next_len - // {{{ - always @(*) - begin - next_len = 32'h00; - next_len[LGDMALENGTH-1:0] = o_length; - - if (i_sel[0]) next_len[ 7: 0] = i_data[ 7: 0]; - if (i_sel[1]) next_len[15: 8] = i_data[15: 8]; - if (i_sel[2]) next_len[23:16] = i_data[23:16]; - if (i_sel[3]) next_len[31:24] = i_data[31:24]; - end - // }}} - - // next_tlen - // {{{ - always @(*) - begin - next_tlen = 32'h00; - next_tlen[LGMEMLEN-1:0] = o_transferlen[LGMEMLEN-1:0]; - - if (i_sel[0]) next_tlen[ 7: 0] = i_data[ 7: 0]; - if (i_sel[1]) next_tlen[15: 8] = i_data[15: 8]; - if (i_sel[2]) next_tlen[23:16] = i_data[23:16]; - if (i_sel[3]) next_tlen[31:24] = i_data[31:24]; - - next_tlen[SLV_WIDTH-1:LGMEMLEN] = 0; - next_tlen[LGMEMLEN] = (next_tlen[LGMEMLEN-1:0] == 0); - end - // }}} - - // Process i_data writes - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - o_src_addr <= {(AW){1'b0}}; - o_dst_addr <= {(AW){1'b0}}; - o_length <= {(LGDMALENGTH){1'b0}}; - r_zero_len <= 1'b1; - o_transferlen <= { 1'b1, {(LGMEMLEN){1'b0}} }; - - o_s2mm_inc <= 1'b0; - o_s2mm_size <= 2'b0; - - o_mm2s_inc <= 1'b0; - o_mm2s_size <= 2'b0; - - int_trigger <= 1'b0; - int_sel <= 5'h0; - // }}} - end else if (i_stb && !o_stall && i_we && !o_dma_request && !i_dma_busy) - begin // Register write, DMA is idle - // {{{ - case(i_addr) - 2'b00: begin // Control registers - // {{{ - o_transferlen[LGMEMLEN:0] <= next_tlen[LGMEMLEN:0]; - if (i_sel[2]) - begin - o_s2mm_inc <= !i_data[22]; - o_s2mm_size <= i_data[21:20]; - // - o_mm2s_inc <= !i_data[18]; - o_mm2s_size <= i_data[17:16]; - end - - if (i_sel[3]) - begin - int_trigger <= i_data[29]; - int_sel <= i_data[28:24]; - end end - // }}} - 2'b01: o_src_addr <= next_src[AW-1:0]; - 2'b10: o_dst_addr <= next_dst[AW-1:0]; - 2'b11: begin // o_length - // {{{ - o_length <= next_len[LGDMALENGTH-1:0]; - r_zero_len <= (next_len[LGDMALENGTH-1:0] == 0); - end - // }}} - endcase - // }}} - end else if (i_dma_busy) - begin - o_src_addr <= i_current_src; - o_dst_addr <= i_current_dst; - end - // }}} - - // o_dma_request, o_dma_abort, o_interrupt, r_err - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - o_dma_request <= 1'b0; - o_dma_abort <= 1'b0; - - r_err <= 1'b0; - - o_interrupt <= 1'b0; - // }}} - end else begin - r_busy <= i_dma_busy; - - if (!i_dma_busy) - begin - o_dma_request <= 1'b0; - o_dma_abort <= 1'b0; - end - - if (i_dma_err) - r_err <= 1'b1; - if (r_busy && (!i_dma_busy || i_dma_err)) - o_interrupt <= 1'b1; - - if (i_stb && !o_stall && i_we && i_addr == 2'b00) - begin - // {{{ - if (o_dma_request || i_dma_busy) - begin - // Deal with abort requests - if ((&i_sel) && i_data == ABORT_KEY) - { o_dma_request, o_dma_abort } <= 2'b01; - - end else if (i_sel[3]) - begin - // Clear interrupts, errors, and potentially - // restart the DMA - if (i_data[29] || !i_data[30]) - o_interrupt <= 1'b0; - if (i_data[30]) - r_err <= 1'b0; - if (!i_data[31] && (!r_err || i_data[30])) - o_dma_request <= !r_zero_len; - end - // }}} - end - end - // }}} - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_cyc, next_tlen[SLV_WIDTH-1:LGMEMLEN] }; - generate if (SLV_WIDTH > AW) - begin : UNUSED_WIDE_ADDR - wire unused_addr; - assign unused_addr = &{ 1'b0, - next_src[SLV_WIDTH-1:AW], - next_dst[SLV_WIDTH-1:AW] - }; - end if (SLV_WIDTH > LGDMALENGTH) - begin : UNUSED_LEN - wire unused_len; - assign unused_len = &{ 1'b0, - next_len[SLV_WIDTH-1:LGDMALENGTH] - }; - end endgenerate - // Verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/cpu/zipdma_fsm.v b/delete_later/rtl/cpu/zipdma_fsm.v deleted file mode 100644 index 11e39e7..0000000 --- a/delete_later/rtl/cpu/zipdma_fsm.v +++ /dev/null @@ -1,221 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipdma_fsm.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: ZipDMA's control FSM -// -// Since the Wishbone bus can only accommodate either a read or a write -// transaction, large DMA transfers need to be broken up between reads -// and writes. This function accomplishes that purpose--issuing read -// requests of the zipdma_mm2s controller, followed by write requests -// of the zipdma_s2mm controller. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipdma_fsm #( - // {{{ - parameter ADDRESS_WIDTH = 32, // Byte ADDR width - parameter LGDMALENGTH = ADDRESS_WIDTH, - parameter LGSUBLENGTH = 10 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - input wire i_soft_reset, - // DMA control - // {{{ - input wire i_dma_request, - output reg o_dma_busy, - output reg o_dma_err, - input wire [ADDRESS_WIDTH-1:0] i_src_addr, - input wire [ADDRESS_WIDTH-1:0] i_dst_addr, - input wire [LGDMALENGTH-1:0] i_length, - input wire [LGSUBLENGTH:0] i_transferlen, - - output wire [LGDMALENGTH-1:0] o_remaining_len, - // }}} - input wire i_trigger, - // MM2S control - // {{{ - output reg o_mm2s_request, - input wire i_mm2s_busy, - input wire i_mm2s_err, - input wire i_mm2s_inc, - // input wire [1:0] i_mm2s_size, - output reg [ADDRESS_WIDTH-1:0] o_mm2s_addr, - output wire [LGSUBLENGTH:0] o_mm2s_transferlen, - // }}} - // S2MM control - // {{{ - output reg o_s2mm_request, - input wire i_s2mm_busy, - input wire i_s2mm_err, - input wire i_s2mm_inc, - // input wire [1:0] i_s2mm_size, - output reg [ADDRESS_WIDTH-1:0] o_s2mm_addr, - output wire [LGSUBLENGTH:0] o_s2mm_transferlen - // }}} - // }}} - ); - - // Local declarations - // {{{ - localparam [1:0] S_IDLE = 2'b00, - S_WAIT = 2'b01, - S_READ = 2'b10, - S_WRITE = 2'b11; - - reg [LGDMALENGTH-1:0] r_length; - reg [LGSUBLENGTH:0] r_transferlen; - reg [1:0] fsm_state; - // }}} - - always @(posedge i_clk) - if (i_reset || i_soft_reset || i_mm2s_err || i_s2mm_err) - begin - // {{{ - o_dma_busy <= 0; - r_length <= 0; - r_transferlen <= 0; - o_mm2s_request <= 0; - o_s2mm_request <= 0; - - o_mm2s_addr <= 0; - o_s2mm_addr <= 0; - - fsm_state <= S_IDLE; - // }}} - end else if (!o_dma_busy) - begin - // {{{ - o_dma_busy <= 1'b0; - - r_length <= 0; - // Verilator lint_off WIDTH - r_transferlen <= (i_length < i_transferlen) ? i_length - : i_transferlen; - // Verilator lint_on WIDTH - - fsm_state <= S_IDLE; - - o_mm2s_request <= 0; - o_s2mm_request <= 0; - - if (i_dma_request) - begin - o_dma_busy <= 1'b1; - - fsm_state <= (i_trigger) ? S_READ : S_WAIT; - o_mm2s_request <= i_trigger; - - o_mm2s_addr <= i_src_addr; - o_s2mm_addr <= i_dst_addr; - r_length <= i_length; - end -`ifdef FORMAL - assert(fsm_state == S_IDLE); -`endif - // }}} - end else case(fsm_state) - S_WAIT: begin - // {{{ - if (r_length == 0) - o_dma_busy <= 0; - else if (i_trigger) - begin - fsm_state <= S_READ; - o_mm2s_request <= 1'b1; - end end - // }}} - S_READ: begin - // {{{ - if (o_mm2s_request && !i_mm2s_busy) // VALID && READY - o_mm2s_request <= 1'b0; - if (!i_mm2s_busy && !o_mm2s_request) - begin - fsm_state <= S_WRITE; - o_s2mm_request <= 1'b1; - - if (i_mm2s_inc) - // Verilator lint_off WIDTH - o_mm2s_addr <= o_mm2s_addr + r_transferlen; - // Verilator lint_on WIDTH - - // Verilator lint_off WIDTH - r_length <= (r_length > r_transferlen) - ? r_length - r_transferlen : 0; - // Verilator lint_on WIDTH - end end - // }}} - S_WRITE: begin - // {{{ - if (o_s2mm_request && !i_s2mm_busy) // VALID && READY - o_s2mm_request <= 1'b0; - if (!i_s2mm_busy && !o_s2mm_request) - begin - fsm_state <= (i_trigger) ? S_READ : S_WAIT; - o_mm2s_request <= (i_trigger); - - // Verilator lint_off WIDTH - if (r_transferlen > r_length) - // Verilator lint_on WIDTH - r_transferlen <= r_length[LGSUBLENGTH:0]; - - if (i_s2mm_inc) - // Verilator lint_off WIDTH - o_s2mm_addr <= o_s2mm_addr + r_transferlen; - // Verilator lint_on WIDTH - - if (r_length == 0) - begin - fsm_state <= S_IDLE; - o_mm2s_request <= 1'b0; - o_dma_busy <= 1'b0; - end - end end - // }}} - // Verilator coverage_off - default: begin end - // Verilator coverage_on - endcase - - assign o_s2mm_transferlen = r_transferlen; - assign o_mm2s_transferlen = r_transferlen; - assign o_remaining_len = r_length; - - // o_dma_err - // {{{ - always @(posedge i_clk) - if (i_reset || i_soft_reset || !o_dma_busy) - o_dma_err <= 1'b0; - else - o_dma_err <= (i_mm2s_busy && i_mm2s_err) - || (i_s2mm_busy && i_s2mm_err); - // }}} -endmodule diff --git a/delete_later/rtl/cpu/zipdma_mm2s.v b/delete_later/rtl/cpu/zipdma_mm2s.v deleted file mode 100644 index 4f0279f..0000000 --- a/delete_later/rtl/cpu/zipdma_mm2s.v +++ /dev/null @@ -1,1137 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipdma_mm2s.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: ZipDMA -- Read values from memory -// -// This is the first component of the DMA sequence. It reads values from -// memory, and aligns them with an outgoing data stream. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipdma_mm2s #( - // {{{ - parameter ADDRESS_WIDTH=30, - parameter BUS_WIDTH = 64, - parameter LGLENGTH=10, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter [0:0] OPT_LOWPOWER = 1'b0, - // Abbreviations - localparam DW = BUS_WIDTH, - localparam AW = ADDRESS_WIDTH-$clog2(DW/8) - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Configuration - // {{{ - input wire i_request, - output reg o_busy, o_err, - input wire i_inc, - input wire [1:0] i_size, - input wire [LGLENGTH:0] i_transferlen, - input wire [ADDRESS_WIDTH-1:0] i_addr, // Byte address - // }}} - // Wishbone master interface - // {{{ - output reg o_rd_cyc, o_rd_stb, - // Verilator coverage_off - output wire o_rd_we, - // Verilator coverage_on - output reg [AW-1:0] o_rd_addr, - // Verilator coverage_off - output wire [DW-1:0] o_rd_data, - // Verilator coverage_on - output reg [DW/8-1:0] o_rd_sel, - input wire i_rd_stall, - input wire i_rd_ack, - input wire [DW-1:0] i_rd_data, - input wire i_rd_err, - // }}} - // Outgoing Stream interface - // {{{ - output wire M_VALID, - input wire M_READY, // *MUST* be 1 - output wire [DW-1:0] M_DATA, - // How many bytes are valid? - output wire [$clog2(DW/8):0] M_BYTES, - output wire M_LAST - // }}} - // }}} - ); - - // Local declarations - // {{{ - localparam [1:0] SZ_BYTE = 2'b11, - SZ_16B = 2'b10, - SZ_32B = 2'b01, - SZ_BUS = 2'b00; - localparam WBLSB = $clog2(DW/8); - reg [WBLSB:0] nxtstb_size, rdstb_size, rdack_size, first_size; - reg [ADDRESS_WIDTH-1:0] next_addr, last_request_addr; - reg [WBLSB-1:0] subaddr, rdack_subaddr; - reg [DW/8-1:0] nxtstb_sel, first_sel, base_sel, ibase_sel; - reg [LGLENGTH:0] wb_outstanding; - - reg [WBLSB+1:0] fill, next_fill; - - reg m_valid, m_last; - reg [DW-1:0] sreg; - reg [WBLSB:0] m_bytes; - - reg [LGLENGTH:0] rdstb_len, rdack_len; - - reg [WBLSB-1:0] pre_shift; - reg [DW-1:0] pre_shifted_data; - - reg r_inc; - reg [1:0] r_size; - // }}} - - assign o_rd_we = 1'b0; - assign o_rd_data = {(DW){1'b0}}; - - // Copy the configuration whenever i_request && !o_busy - // {{{ - always @(posedge i_clk) - if (!o_busy && (!OPT_LOWPOWER || i_request)) - begin - r_inc <= i_inc; - r_size <= i_size; - // r_transferlen <= i_transferlen; - // r_addr <= i_addr; - end - // }}} - - // nxtstb_size - // {{{ - generate if (BUS_WIDTH > 32) - begin : GEN_NXTSTB_SIZE - // {{{ - always @(*) - begin - first_size = 0; - case(i_size) - SZ_BYTE: first_size = 1; - SZ_16B: first_size = (i_addr[0]) ? 1:2; - // Verilator lint_off WIDTH - SZ_32B: first_size = 4 - i_addr[1:0]; - SZ_BUS: first_size = (DW/8)-i_addr[WBLSB-1:0]; - endcase - - if (first_size > i_transferlen) - first_size = i_transferlen; - end - - always @(*) - begin - nxtstb_size = rdstb_size; - - case(r_size) - SZ_BYTE: nxtstb_size = 1; - SZ_16B: nxtstb_size = (rdstb_len == 3) ? 1 : 2; - // Verilator lint_off WIDTH - SZ_32B: nxtstb_size = (rdstb_len >= 4 && rdstb_len < 8) - ? (rdstb_len - 4) : 4; - SZ_BUS: begin - nxtstb_size = (DW/8); - if (DW/8 > rdstb_len - rdstb_size) - nxtstb_size = - { 1'b0, rdstb_len[WBLSB:0] } - -{ 1'b0, rdstb_size[WBLSB:0]}; - // if (o_rd_stb && nxtstb_size > (DW/8)-subaddr) - // nxtstb_size = (DW/8)-subaddr; - end - // Verilator lint_on WIDTH - endcase - end - // }}} - end else begin : STD_NXTSTB_SIZE - // {{{ - always @(*) - begin - first_size = 0; - case(i_size) - SZ_BYTE: first_size = 1; - SZ_16B: first_size = (i_addr[0]) ? 1:2; - // Verilator lint_off WIDTH - default: - first_size = (DW/8)-i_addr[WBLSB-1:0]; - endcase - - if (first_size > i_transferlen) - first_size = i_transferlen; - // Verilator lint_on WIDTH - end - - always @(*) - begin - nxtstb_size = rdstb_size; - - casez(r_size) - SZ_BYTE: nxtstb_size = 1; - SZ_16B: nxtstb_size = (rdstb_len == 3) ? 1 : 2; - default: begin - // Verilator lint_off WIDTH - nxtstb_size = (DW/8); - if ((rdstb_len[LGLENGTH:WBLSB+1] == 0) - &&(rdstb_size + DW/8 > rdstb_len[WBLSB:0])) - nxtstb_size = - { 1'b0, rdstb_len[WBLSB:0] } - -{ 1'b0, rdstb_size[WBLSB:0]}; - end - // Verilator lint_on WIDTH - endcase - end - // }}} - end endgenerate - // }}} - - // next_addr - // {{{ - always @(*) - begin - next_addr = { o_rd_addr, subaddr }; - - if (o_rd_stb && !i_rd_stall) - next_addr = next_addr - + { {(ADDRESS_WIDTH-WBLSB-1){1'b0}}, rdstb_size }; - end - // }}} - - // o_rd_cyc, o_rd_stb, o_busy, o_err, rdstb_len, rdstb_size - // {{{ - initial { o_rd_cyc, o_rd_stb } = 2'b00; - initial { o_busy, o_err } = 2'b00; - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - o_rd_cyc <= 1'b0; - o_rd_stb <= 1'b0; - { o_rd_addr, subaddr } <= 0; - - rdstb_size <= 0; - rdstb_len <= 0; - o_busy <= 0; - o_err <= 0; - // }}} - end else if (o_rd_cyc && i_rd_err) - begin - // {{{ - o_rd_cyc <= 1'b0; - o_rd_stb <= 1'b0; - { o_rd_addr, subaddr } <= 0; - - rdstb_size <= 0; - rdstb_len <= 0; - - o_busy <= 0; - o_err <= 1; - // }}} - end else if (!o_busy) - begin - // {{{ - o_rd_cyc <= i_request; - o_rd_stb <= i_request; - o_busy <= i_request; - o_err <= 0; - - rdstb_size <= 0; - rdstb_len <= 0; - if (!OPT_LOWPOWER || i_request) - begin - { o_rd_addr, subaddr } <= i_addr; - - // rdstb_size - rdstb_size <= first_size; - - // rdstb_len - rdstb_len <= i_transferlen; - end - // }}} - end else begin - if (!i_rd_stall) - o_rd_stb <= 1'b0; - - if (rdstb_len > { {(LGLENGTH-WBLSB){1'b0}}, rdstb_size }) - o_rd_stb <= 1'b1; - - if (o_rd_stb && !i_rd_stall) - begin - // {{{ - if (rdstb_len <= { {(LGLENGTH-WBLSB){1'b0}}, rdstb_size }) - begin - rdstb_len <= 0; - end else begin - rdstb_len <= rdstb_len - - { {(LGLENGTH-WBLSB){1'b0}}, rdstb_size }; - o_rd_stb <= 1'b1; - end - - // rdstb_size - rdstb_size <= nxtstb_size; - - { o_rd_addr, subaddr } <= next_addr; - // }}} - end - - if (wb_outstanding == (i_rd_ack ? 1:0) && !o_rd_stb) - o_rd_cyc <= 1'b0; - - if (m_valid && m_last) - o_busy <= 0; - end -`ifdef FORMAL - always @(*) - if (!o_busy) - begin - assert(!m_valid); - end else if (m_valid && m_last) - begin - assert(rdack_len == 0); - assert(fill == m_bytes); - end - - always @(*) - if (o_busy) - assert(rdstb_len <= rdack_len); -`endif - // }}} - - // o_rd_sel - // {{{ - - // ibase_sel - generate if (BUS_WIDTH > 32) - begin : GEN_STRB - // {{{ - always @(*) - begin - ibase_sel = 0; - - if (OPT_LITTLE_ENDIAN) - begin - // {{{ - // Verilator coverage_off - case(i_size) - SZ_BYTE: ibase_sel = {{(DW/8-1){1'b0}}, 1'b1} << i_addr[WBLSB-1:0]; - SZ_16B: ibase_sel = {{(DW/8-2){1'b0}}, 2'h3} << {i_addr[WBLSB-1:1], 1'b0 }; - SZ_32B: ibase_sel = {{(DW/8-4){1'b0}}, 4'b1111} << {i_addr[WBLSB-1:2], 2'b0 }; - SZ_BUS: ibase_sel = {(DW/8){1'b1}}; - endcase - // Verilator coverage_on - // }}} - end else begin - // {{{ - case(i_size) - SZ_BYTE: ibase_sel= {1'h1, {(DW/8-1){1'b0}} } >> i_addr[WBLSB-1:0]; - SZ_16B: ibase_sel = {2'h3, {(DW/8-2){1'b0}} } >> {i_addr[WBLSB-1:1], 1'b0 }; - SZ_32B: ibase_sel = {4'hf, {(DW/8-4){1'b0}} } >> {i_addr[WBLSB-1:2], 2'b0 }; - SZ_BUS: ibase_sel = {(DW/8){1'b1}}; - endcase - // }}} - end - end - // }}} - end else begin : MIN_STRB - // {{{ - always @(*) - begin - ibase_sel = 0; - - if (OPT_LITTLE_ENDIAN) - begin - // {{{ - // Verilator coverage_off - case(i_size) - SZ_BYTE: ibase_sel = {{(DW/8-1){1'b0}}, 1'b1} << i_addr[WBLSB-1:0]; - SZ_16B: ibase_sel = {{(DW/8-2){1'b0}}, 2'h3} << {i_addr[WBLSB-1:1], 1'b0 }; - default: ibase_sel = {(DW/8){1'b1}}; - endcase - // Verilator coverage_on - // }}} - end else begin - // {{{ - case(i_size) - SZ_BYTE: ibase_sel= {1'h1, {(DW/8-1){1'b0}} } << i_addr[WBLSB-1:0]; - SZ_16B: ibase_sel = {2'h3, {(DW/8-2){1'b0}} } << {i_addr[WBLSB-1:1], 1'b0 }; - default: ibase_sel = {(DW/8){1'b1}}; - endcase - // }}} - end - end - // }}} - end endgenerate - - always @(posedge i_clk) - if (i_reset || (o_rd_cyc && i_rd_err)) - begin - // {{{ - base_sel <= 0; - // }}} - end else if (!o_busy) - begin - base_sel <= 0; - if (i_request || !OPT_LOWPOWER) - base_sel <= ibase_sel; - end else if (o_rd_stb && !i_rd_stall) - base_sel <= nxtstb_sel; - - // nxtstb_sel - // {{{ - generate if (DW == 32) - begin : GEN_NXTSTB_SEL - // {{{ - always @(*) - if (OPT_LITTLE_ENDIAN) - begin - case(r_size) - SZ_BYTE: nxtstb_sel = { base_sel[DW/8-2:0], base_sel[DW/8-1] }; - SZ_16B: nxtstb_sel = { base_sel[DW/8-3:0], base_sel[DW/8-1:DW/8-2] }; - default: - nxtstb_sel = {(DW/8){1'b1}}; - endcase - - if (!r_inc) - nxtstb_sel = base_sel; - end else begin - case(r_size) - SZ_BYTE: nxtstb_sel = { base_sel[0:0], base_sel[DW/8-1:1] }; - SZ_16B: nxtstb_sel = { base_sel[1:0], base_sel[DW/8-1:2] }; - default: - nxtstb_sel = {(DW/8){1'b1}}; - endcase - - if (!r_inc) - nxtstb_sel = base_sel; - end - // }}} - end else begin : GEN_WIDE_NXTSTB_SEL - always @(*) - if (OPT_LITTLE_ENDIAN) - begin - case(r_size) - SZ_BYTE: nxtstb_sel = { base_sel[DW/8-2:0], base_sel[DW/8-1] }; - SZ_16B: nxtstb_sel = { base_sel[DW/8-3:0], base_sel[DW/8-1:DW/8-2] }; - SZ_32B: nxtstb_sel = { base_sel[DW/8-5:0], base_sel[DW/8-1:DW/8-4] }; - SZ_BUS: nxtstb_sel = {(DW/8){1'b1}}; - endcase - - if (!r_inc) - nxtstb_sel = base_sel; - end else begin - case(r_size) - SZ_BYTE: nxtstb_sel = { base_sel[0:0], base_sel[DW/8-1:1] }; - SZ_16B: nxtstb_sel = { base_sel[1:0], base_sel[DW/8-1:2] }; - SZ_32B: nxtstb_sel = { base_sel[3:0], base_sel[DW/8-1:4] }; - SZ_BUS: nxtstb_sel = {(DW/8){1'b1}}; - endcase - - if (!r_inc) - nxtstb_sel = base_sel; - end - end endgenerate - // }}} - - // first_sel - generate if (BUS_WIDTH > 32) - begin : GEN_FIRST_SEL - // {{{ - always @(*) - begin - first_sel = 0; - - if (OPT_LITTLE_ENDIAN) - begin - // {{{ - // Verilator coverage_off - case(i_size) - SZ_BYTE: first_sel = {{(DW/8-1){1'b0}}, 1'b1} << i_addr[WBLSB-1:0]; - SZ_16B: first_sel = {{(DW/8-2){1'b0}}, 1'b1,i_addr[0]} << {i_addr[WBLSB-1:1], 1'b0 }; - SZ_32B: case(i_addr[1:0]) - 2'b00: first_sel = {{(DW/8-4){1'b0}}, 4'b1111} << {i_addr[WBLSB-1:2], 2'b0 }; - 2'b01: first_sel = {{(DW/8-4){1'b0}}, 4'b1110} << {i_addr[WBLSB-1:2], 2'b0 }; - 2'b10: first_sel = {{(DW/8-4){1'b0}}, 4'b1100} << {i_addr[WBLSB-1:2], 2'b0 }; - 2'b11: first_sel = {{(DW/8-4){1'b0}}, 4'b1000} << {i_addr[WBLSB-1:2], 2'b0 }; - endcase - SZ_BUS: first_sel = {(DW/8){1'b1}} << i_addr[WBLSB-1:0]; - endcase - // Verilator coverage_on - // }}} - end else begin - // {{{ - case(i_size) - SZ_BYTE: first_sel = {1'b1, {(DW/8-1){1'b0}} } >> i_addr[WBLSB-1:0]; - SZ_16B: first_sel = {i_addr[0], 1'b1, {(DW/8-2){1'b0}} } - >> {i_addr[WBLSB-1:1], 1'b0 }; - SZ_32B: case(i_addr[1:0]) - 2'b00: first_sel = {4'b1111, {(DW/8-4){1'b0}} } >> {i_addr[WBLSB-1:2], 2'b0 }; - 2'b01: first_sel = {4'b0111, {(DW/8-4){1'b0}} } >> {i_addr[WBLSB-1:2], 2'b0 }; - 2'b10: first_sel = {4'b0011, {(DW/8-4){1'b0}} } >> {i_addr[WBLSB-1:2], 2'b0 }; - 2'b11: first_sel = {4'b0001, {(DW/8-4){1'b0}} } >> {i_addr[WBLSB-1:2], 2'b0 }; - endcase - SZ_BUS: first_sel = {(DW/8){1'b1}} >> i_addr[WBLSB-1:0]; - endcase - // }}} - end - end - // }}} - end else begin : MIN_FIRST_SEL - // {{{ - always @(*) - begin - first_sel = 0; - - if (OPT_LITTLE_ENDIAN) - begin - // {{{ - casez(i_size) - SZ_BYTE: first_sel = 4'b0001 << i_addr[WBLSB-1:0]; - SZ_16B: first_sel = 4'b0011 << {i_addr[WBLSB-1:1], 1'b0 }; - default: case(i_addr[1:0]) - 2'b00: first_sel = 4'b1111; - 2'b01: first_sel = 4'b1110; - 2'b10: first_sel = 4'b1100; - 2'b11: first_sel = 4'b1000; - endcase - endcase - // }}} - end else begin - // {{{ - casez(i_size) - SZ_BYTE: first_sel = 4'b1000 >> i_addr[WBLSB-1:0]; - SZ_16B: first_sel = 4'b1100 - >> {i_addr[WBLSB-1:1], 1'b0 }; - default: case(i_addr[1:0]) - 2'b00: first_sel = 4'b1111; - 2'b01: first_sel = 4'b0111; - 2'b10: first_sel = 4'b0011; - 2'b11: first_sel = 4'b0001; - endcase - endcase - // }}} - end - end - // }}} - end endgenerate - - // o_rd_sel - always @(posedge i_clk) - if (i_reset || (o_rd_cyc && i_rd_err)) - begin - // {{{ - o_rd_sel <= 0; - // }}} - end else if (!o_busy) - begin - // {{{ - o_rd_sel <= {(DW/8){1'b0}}; - - if (!OPT_LOWPOWER || i_request) - o_rd_sel <= first_sel; - // }}} - end else if (o_rd_stb && !i_rd_stall) - o_rd_sel <= nxtstb_sel; - // }}} - - // wb_outstanding - // {{{ - initial wb_outstanding = 0; - always @(posedge i_clk) - if (i_reset || !o_rd_cyc || i_rd_err) - wb_outstanding <= 0; - // wb_pipeline_full <= 1'b0; - else case({ (o_rd_stb && !i_rd_stall), i_rd_ack }) - 2'b10: wb_outstanding <= wb_outstanding + 1; - 2'b01: wb_outstanding <= wb_outstanding - 1; - default: begin end - endcase - // }}} - - // rdack_subaddr - // {{{ - always @(posedge i_clk) - if (!o_busy) - begin - if (!OPT_LOWPOWER || i_request) - rdack_subaddr <= i_addr[WBLSB-1:0]; - end else if (i_rd_ack) - begin - // Verilator lint_off WIDTH - if (r_inc) - rdack_subaddr <= rdack_subaddr + rdack_size; - else case(r_size) - SZ_BYTE: begin end - SZ_16B: rdack_subaddr[ 0] <= 1'b0; - SZ_32B: rdack_subaddr[1:0] <= 2'b0; - SZ_BUS: rdack_subaddr[WBLSB-1:0] <= {(WBLSB){1'b0}}; - endcase - // Verilator lint_on WIDTH - end - // }}} - - // rdack_len - // {{{ - // Total length remaining, from the perspective of the bus return. - // Hence, on any bus return, we drop by the number of bytes valid - // in that return, or minus rdack_size. - always @(posedge i_clk) - if (!o_busy) - begin - if (!OPT_LOWPOWER || i_request) - rdack_len <= i_transferlen; - end else if (i_rd_ack) - begin - rdack_len <= rdack_len-{ {(LGLENGTH-WBLSB){1'b0}}, rdack_size }; - if (rdack_len <= { {(LGLENGTH-WBLSB){1'b0}}, rdack_size }) - rdack_len <= 0; - end - // }}} - - // rdack_size - // {{{ - always @(posedge i_clk) - if (!o_busy) - begin - if (!OPT_LOWPOWER || i_request) - rdack_size <= first_size; - end else if (i_rd_ack) - begin - case(r_size) - SZ_BYTE:rdack_size <= 1; - SZ_16B: rdack_size <= 2; - SZ_32B: rdack_size <= 4; - // Verilator lint_off WIDTH - SZ_BUS: if (rdack_len > DW/8 + rdack_size) - rdack_size <= DW/8; - else - rdack_size <= rdack_len - rdack_size; - // Verilator lint_on WIDTH - endcase - end - // }}} - - // fill, next_fill (depends on rdack_size) - // {{{ - always @(*) - begin - next_fill = fill; - if (M_VALID) - next_fill = next_fill - M_BYTES; - if (i_rd_ack) - next_fill = next_fill + { 1'b0, rdack_size }; - end - - always @(posedge i_clk) - if (!o_busy) - fill <= 0; - else - fill <= next_fill; - // }}} - - // m_valid - // {{{ - initial m_valid = 0; - always @(posedge i_clk) - if (!o_busy) - m_valid <= 1'b0; - else begin - // Verilator lint_off WIDTH - m_valid <= 0; - if ((!m_valid || !m_last) && rdack_len == 0 && fill > 0) - m_valid <= 1; - else if (o_rd_cyc && i_rd_ack) - m_valid <= 1'b1; // ((next_fill >= DW/8) - // || (rdack_len <= { {(LGLENGTH-1){1'b0}}, rdack_size })); - // Verilator lint_on WIDTH - end - // }}} - - // sreg - // {{{ - initial pre_shift = 0; - always @(posedge i_clk) - if (!o_busy) - begin - pre_shift <= 0; - if (!OPT_LOWPOWER || i_request) - pre_shift <= i_addr[WBLSB-1:0]; - end else if (o_rd_cyc && i_rd_ack) - begin - case(r_size) - SZ_BYTE: pre_shift <= pre_shift + (r_inc ? 1 : 0); - SZ_16B: begin - // {{{ - pre_shift <= pre_shift + (r_inc ? 2 : 0); - pre_shift[0] <= 1'b0; - end - // }}} - SZ_32B: begin - // {{{ - // Verilator lint_off WIDTH - pre_shift <= pre_shift + (r_inc ? 4 : 0); - // Verilator lint_on WIDTH - pre_shift[1:0] <= 2'b0; - end - // }}} - SZ_BUS: pre_shift <= 0; - endcase - end - - always @(*) - if (OPT_LITTLE_ENDIAN) - pre_shifted_data = i_rd_data >> (8*pre_shift); - else - pre_shifted_data = i_rd_data << (8*pre_shift); - - initial sreg = 0; - always @(posedge i_clk) - if (!o_busy) - sreg <= 0; - else if (o_rd_cyc && i_rd_ack) - begin - // {{{ - // Verilator lint_off WIDTH - sreg <= pre_shifted_data; - // Verilator lint_on WIDTH - // }}} - end else if (m_valid) - begin - // {{{ - sreg <= {(DW){1'b0}}; - // }}} - end - // }}} - - // m_bytes - // {{{ - initial m_bytes = 0; - always @(posedge i_clk) - if (!o_busy) - begin - m_bytes <= 0; - end else if (i_rd_ack) - begin - if (|next_fill[WBLSB+1:WBLSB]) // if next_fill >= DW/8) - // Verilator lint_off WIDTH - m_bytes <= DW/8; - // Verilator lint_on WIDTH - else - m_bytes <= { 1'b0, next_fill[WBLSB-1:0] }; - end else if (rdack_len == 0) - m_bytes <= next_fill[WBLSB:0]; -`ifdef FORMAL - always @(*) - if (M_VALID) - assert(M_BYTES <= DW/8); -`endif - // }}} - - // m_last - // {{{ - always @(*) - begin - last_request_addr = i_addr; - if (r_inc) - // Verilator lint_off WIDTH - last_request_addr = i_addr + i_transferlen - 1; - // Verilator lint_on WIDTH - end - - initial m_last = 0; - always @(posedge i_clk) - if (!o_busy) - begin - m_last <= 1'b0; - if (!OPT_LOWPOWER || i_request) - case(i_size) - SZ_BYTE: m_last <= (i_transferlen <= 1); - SZ_16B: m_last <= (last_request_addr[ADDRESS_WIDTH-1:1] != i_addr[ADDRESS_WIDTH-1:1]); - SZ_32B: m_last <= (last_request_addr[ADDRESS_WIDTH-1:2] != i_addr[ADDRESS_WIDTH-1:2]); - SZ_BUS: m_last <= (last_request_addr[ADDRESS_WIDTH-1:WBLSB] != i_addr[ADDRESS_WIDTH-1:WBLSB]); - endcase - end else if (i_rd_ack) - begin - // Verilator lint_off WIDTH - m_last <= (rdack_len <= rdack_size) && (next_fill <= DW/8); - // Verilator lint_on WIDTH - end else if (rdack_len == 0) - m_last <= 1; - // }}} - - assign M_VALID = m_valid; - assign M_DATA = sreg; - assign M_BYTES= m_bytes; - assign M_LAST = m_last; - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, M_READY, last_request_addr[0] }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH = LGLENGTH+1-WBLSB; - localparam F_LGCOUNT = LGLENGTH+1; - reg f_past_valid; - wire [F_LGDEPTH-1:0] fwb_nreqs, fwb_nacks, fwb_outstanding; - (* anyconst *) reg f_cfg_inc; - (* anyconst *) reg [1:0] f_cfg_size; - (* anyconst *) reg [ADDRESS_WIDTH-1:0] f_cfg_addr; - (* anyconst *) reg [LGLENGTH:0] f_cfg_len; - reg [F_LGCOUNT-1:0] f_rcvd, f_sent; - reg [WBLSB:0] f_ack_size; - reg [LGLENGTH:0] r_transferlen; - reg [ADDRESS_WIDTH-1:0] r_addr; - - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - //////////////////////////////////////////////////////////////////////// - // - // Configuration properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset) || $past(o_err)) - begin - assume(!i_request); - end else if ($past(o_busy && i_request)) - begin - assume(i_request); - assume($stable(i_inc)); - assume($stable(i_size)); - assume($stable(i_addr)); - assume($stable(i_transferlen)); - end - - always @(posedge i_clk) - if (!o_busy && (!OPT_LOWPOWER || i_request)) - begin - // Shadow copy of these registers - r_transferlen <= i_transferlen; - r_addr <= i_addr; - end - - always @(*) - if (i_request && !o_busy) - begin - assume(i_inc == f_cfg_inc); - assume(i_size == f_cfg_size); - assume(i_addr == f_cfg_addr); - assume(i_transferlen == f_cfg_len); - end else if (o_busy) - begin - assert(r_inc == f_cfg_inc); - assert(r_size == f_cfg_size); - assert(r_addr == f_cfg_addr); - assert(r_transferlen == f_cfg_len); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - fwb_master #( - // {{{ - .AW(AW), .DW(DW), .F_LGDEPTH(F_LGDEPTH), - .F_OPT_RMW_BUS_OPTION(1'b0), - .F_OPT_DISCONTINUOUS(1'b0), - .F_OPT_SOURCE(1'b1) - // }}} - ) fwb ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_wb_cyc(o_rd_cyc), - .i_wb_stb(o_rd_stb), - .i_wb_we(o_rd_we), - .i_wb_addr(o_rd_addr), - .i_wb_data(o_rd_data), - .i_wb_sel(o_rd_sel), - // - .i_wb_stall(i_rd_stall), - .i_wb_ack(i_rd_ack), - .i_wb_idata(i_rd_data), - .i_wb_err(i_rd_err), - // - .f_nreqs(fwb_nreqs), .f_nacks(fwb_nacks), - .f_outstanding(fwb_outstanding) - // }}} - ); - - always @(*) - assert(!o_rd_we); - - always @(*) - if (f_past_valid && o_rd_stb) - begin - assert(o_rd_sel != 0); - - case(i_size) - SZ_BYTE:assert($countones(o_rd_sel) == 1); - SZ_16B: assert($countones(o_rd_sel) <= 2); - SZ_32B: assert($countones(o_rd_sel) <= 4); - default: begin end - endcase - end - - always @(*) - if (f_past_valid && o_rd_cyc) - assert(fwb_outstanding == wb_outstanding); - - // f_rcvd - // {{{ - initial f_rcvd = 0; - always @(posedge i_clk) - if (i_reset || !o_busy || o_err) - f_rcvd <= 0; - else if (o_rd_cyc && i_rd_ack) - begin - if (f_rcvd == 0) - begin - case(i_size) - SZ_BYTE: f_rcvd <= f_rcvd + 1; - SZ_16B: f_rcvd <= f_rcvd + (2 - i_addr[ 0]); - SZ_32B: f_rcvd <= f_rcvd + (4 - i_addr[1:0]); - SZ_BUS: f_rcvd <= f_rcvd + (DW/8 - i_addr[WBLSB-1:0]); - endcase - end else case(i_size) - SZ_BYTE: f_rcvd <= f_rcvd + 1; - SZ_16B: f_rcvd <= f_rcvd + 2; - SZ_32B: f_rcvd <= f_rcvd + 4; - SZ_BUS: f_rcvd <= f_rcvd + DW/8; - endcase - end - // }}} - - // f_ack_size - // {{{ - always @(*) - begin - case(i_size) - SZ_BYTE: f_ack_size = 1; - SZ_16B: f_ack_size = 2; - SZ_32B: f_ack_size = 4; - SZ_BUS: f_ack_size = DW/8; - endcase - - if (f_rcvd == 0) - case(i_size) - SZ_BYTE: f_ack_size = 1; - SZ_16B: f_ack_size = (2 - i_addr[ 0]); - SZ_32B: f_ack_size = (4 - i_addr[1:0]); - SZ_BUS: f_ack_size = (DW/8-i_addr[WBLSB-1:0]); - endcase - - if (f_rcvd + f_ack_size > i_transferlen) - f_ack_size = i_transferlen - f_rcvd; - end - // }}} - - always @(*) - if (!i_reset && o_busy) - begin - assert(rdack_size == f_ack_size); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Outgoing stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - assert(!M_VALID); - end - - always @(*) - if (f_past_valid && M_VALID) - begin - assert(M_BYTES > 0); - assert(M_BYTES <= (DW/8)); - - if (M_LAST) - assert(!o_rd_stb); - end - - initial f_sent = 0; - always @(posedge i_clk) - if (i_reset) - f_sent <= 0; - else if (M_VALID && M_READY) - begin - if (M_LAST) - f_sent <= 0; - else - f_sent <= f_sent + M_BYTES; - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Contract" properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - (* anyconst *) reg fc_check; - (* anyconst *) reg [F_LGCOUNT-1:0] fc_posn; - (* anyconst *) reg [7:0] fc_byte; - - wire fwb_check, fm_check; - reg [WBLSB-1:0] fwb_shift, fm_shift; - reg [DW-1:0] fwb_shifted, fm_shifted; - - // Assume a known response from the bus - // {{{ - assign fwb_check = fc_check && (o_rd_cyc && i_rd_ack) - && (f_rcvd <= fc_posn) - && (fc_posn < f_rcvd + f_ack_size); - - always @(*) - begin - fwb_shift = f_rcvd - fc_posn; - fwb_shift = fwb_shift + pre_shift; - end - - always @(*) - if (OPT_LITTLE_ENDIAN) - fwb_shifted = i_rd_data >> (8*fwb_shift); - else - fwb_shifted = i_rd_data << (8*fwb_shift); - - always @(*) - if (fwb_check) - begin - if (OPT_LITTLE_ENDIAN) - assume(fwb_shifted[7:0] == fc_byte); - else - assume(fwb_shifted[DW-1:DW-8] == fc_byte); - end - // }}} - - // Assert a specific output - // {{{ - assign fm_check = fc_check && M_VALID - && (f_sent <= fc_posn) - && (fc_posn < f_sent + fill); - - always @(*) - fm_shift = fc_posn - f_sent; - - always @(*) - if (OPT_LITTLE_ENDIAN) - fm_shifted = sreg >> (8*fm_shift); - else - fm_shifted = sreg << (8*fm_shift); - - always @(*) - if (!i_reset && fm_check) - begin - if (OPT_LITTLE_ENDIAN) - begin - assert(fm_shifted[7:0] == fc_byte); - end else - assert(fm_shifted[2*DW-1:2*DW-8] == fc_byte); - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - begin - cover(!i_reset && i_request); - cover(o_busy); - cover(o_rd_cyc); - cover(o_rd_cyc && i_rd_ack); - end - - always @(*) - cover(!i_reset && fm_check); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // The outgoing stream isn't quite an AXI stream master interface, - // since WB doesn't have backpressure. Therefore, we assume M_READY - // is always high when we need it to be. - - always @(*) - if (!i_reset && M_VALID) - assume(M_READY); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipdma_rxgears.v b/delete_later/rtl/cpu/zipdma_rxgears.v deleted file mode 100644 index 51c65f8..0000000 --- a/delete_later/rtl/cpu/zipdma_rxgears.v +++ /dev/null @@ -1,539 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipdma_rxgears.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: ZipDMA -- A gearbox to pack received data. This is part of our -// alignment process. Data comes in, gets read, gets packed, goes -// into the FIFO, gets unpacked, and eventually written back to the bus. -// Here, we simply pack words prior to stuffing them into the FIFO. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipdma_rxgears #( - // {{{ - parameter BUS_WIDTH = 64, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - // Abbreviations - localparam DW = BUS_WIDTH - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Configuration - // {{{ - input wire i_soft_reset, - // }}} - // Incoming Stream interface - // {{{ - input wire S_VALID, - output wire S_READY, - input wire [DW-1:0] S_DATA, - // How many bytes are valid? - input wire [$clog2(DW/8):0] S_BYTES, - input wire S_LAST, - // }}} - // Outgoing Stream interface - // {{{ - output wire M_VALID, - input wire M_READY, - output wire [DW-1:0] M_DATA, - // How many bytes are valid? - output wire [$clog2(DW/8):0] M_BYTES, - output wire M_LAST - // }}} - // }}} - ); - - // Local declarations - // {{{ - localparam WBLSB = $clog2(DW/8); - reg [2*DW-1:0] sreg; - reg [WBLSB+1:0] next_fill, fill; - reg m_valid, m_last, next_last, - r_last, r_full; - reg [WBLSB:0] m_bytes; - reg [WBLSB-1:0] shift; - - reg [DW-1:0] s_data; - integer ik; - - // }}} - - // next_fill, next_last - // {{{ - always @(*) - begin - next_fill = fill; - if (M_VALID && M_READY) - begin - if (M_LAST) - next_fill = 0; - else - next_fill[WBLSB+1:WBLSB] - = next_fill[WBLSB+1:WBLSB] - 1; - end - - if (S_VALID && S_READY) - next_fill = next_fill + S_BYTES; - - next_last = 0; - if (S_VALID && S_READY && S_LAST) - next_last = (next_fill[WBLSB+1:WBLSB] == 2'b00) - ||((next_fill[WBLSB+1:WBLSB] == 2'b01) - &&(next_fill[WBLSB-1:0] == 0)); - // Was next_fill <= DW/8); - end - // }}} - - // fill - // {{{ - initial fill = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - fill <= 0; - else - fill <= next_fill; -`ifdef FORMAL - always @(*) - assert(fill < 2*DW/8); -`endif - // }}} - - // r_full - // {{{ -/* - // This isn't necessary, since r_full == fill[WBLSB]; - initial r_full = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - r_full <= 0; - else if (M_VALID && M_READY) - r_full <= 1'b0; - else if (S_VALID && S_READY) - r_full <= (next_fill >= (DW/8)); -*/ - always @(*) - // Verilator lint_off WIDTH - r_full = (fill >= (DW/8)); - // Verilator lint_on WIDTH - // }}} - - // m_valid - // {{{ - initial m_valid = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - m_valid <= 0; - else if (!M_VALID || M_READY) - m_valid <= r_last || (S_VALID && S_READY && S_LAST) - || (|next_fill[WBLSB+1:WBLSB]); -`ifdef FORMAL - always @(*) - if (fill >= (DW/8) || r_last || m_last) - assert(m_valid); - - always @(*) - if (m_last) - assert(m_bytes == fill); -`endif - // }}} - - // m_bytes - // {{{ - initial m_bytes = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - m_bytes <= 0; - else if (!M_VALID || M_READY) - m_bytes <= (|next_fill[WBLSB+1:WBLSB]) - ? { 1'b1, {(WBLSB){1'b0}} } // DW/8 - : { 1'b0, next_fill[WBLSB-1:0] }; - // m_bytes <= (next_fill > (DW/8)) ? DW/8 : next_fill; - // }}} - - // r_last, m_last - // {{{ - initial { r_last, m_last } = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - { r_last, m_last } <= 0; - else if (S_VALID && S_READY && S_LAST) - { r_last, m_last } <= { !next_last, next_last }; - else if (M_VALID && M_READY) - { r_last, m_last } <= { 1'b0, r_last }; - // }}} - - // sreg - // {{{ - always @(*) - begin - s_data = 0; - for(ik=0; ik>(shift*8)); - // Verilator lint_on WIDTH - else - sreg <= { sreg[DW-1:0], {(DW){1'b0}} }; - end else if (S_VALID && S_READY) - // Verilator lint_off WIDTH - sreg <= sreg | ({ s_data, {(DW){1'b0}} } >> (shift*8)); - // Verilator lint_on WIDTH - end - // Verilator lint_on WIDTH - // }}} - - assign M_VALID = m_valid; - assign M_DATA = (OPT_LITTLE_ENDIAN) ? sreg[DW-1:0] : sreg[2*DW-1:DW]; - assign M_BYTES = m_bytes; - assign M_LAST = m_last; - - assign S_READY = (!M_LAST && !r_last) - && (!M_VALID || (M_READY || !r_full)); - // || (S_BYTES + fill < 2*DW/8)))); - - // Keep Verilator happy - // {{{ - // wire unused; - // assign unused = &{ 1'b0, ... }; - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGCOUNT = 16; - reg f_past_valid; - reg [F_LGCOUNT-1:0] f_rcvd, f_sent; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - //////////////////////////////////////////////////////////////////////// - // - // Incoming stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset || i_soft_reset)) - assume(!S_VALID); - else if ($past(S_VALID && !S_READY)) - begin - assume(S_VALID); - assume($stable(S_DATA)); - assume($stable(S_BYTES)); - assume($stable(S_LAST)); - end - - always @(*) - if (!i_reset && S_VALID) - begin - assume(S_BYTES <= (DW/8)); - assume(S_BYTES > 0); - end - - initial f_rcvd = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - f_rcvd <= 0; - else if (S_VALID && S_READY) - begin - if (S_LAST) - f_rcvd <= 0; - else - f_rcvd <= f_rcvd + S_BYTES; - end - - always @(*) - begin - assume(!f_rcvd[F_LGCOUNT-1]); - assume({ 1'b0, f_rcvd } + (S_VALID ? S_BYTES : 0) - < (1<<(F_LGCOUNT-1))); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Outgoing stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset || i_soft_reset)) - begin - assert(!M_VALID); - assert(!r_last); - assert(!M_LAST); - end else if ($past(M_VALID && !M_READY)) - begin - assert(M_VALID); - assert($stable(M_DATA)); - assert($stable(M_BYTES)); - assert($stable(M_LAST)); - end - - always @(*) - if (!i_reset && M_VALID) - begin - assert(M_BYTES <= (DW/8)); - assert(M_BYTES > 0); - - if (!M_LAST) - assert(M_BYTES == (DW/8)); - end - - initial f_sent = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - f_sent <= 0; - else if (M_VALID && M_READY) - begin - if (M_LAST) - f_sent <= 0; - else - f_sent <= f_sent + M_BYTES; - end - - reg [F_LGCOUNT-1:0] f_buffered; - - always @(*) - begin - f_buffered = f_sent + fill; - - assert(!f_sent[F_LGCOUNT-1]); - assert(!f_buffered[F_LGCOUNT-1]); - - assert(f_buffered >= f_sent); - - assert(f_sent[WBLSB-1:0] == 0); - end - - always @(*) - if (!i_reset) - begin - if (!m_last && !r_last) - begin - assert(f_sent + fill == f_rcvd); - assert(f_sent <= f_rcvd); - end - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Induction properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (!i_reset) - begin - assert(!r_last || !M_LAST); - - if (r_last) - assert(M_VALID && fill > (DW/8)); - end - - always @(*) - if (!i_reset) - begin - if (fill > (DW/8)) - assert(M_BYTES == (DW/8)); - else - assert(M_BYTES == fill); - end - - always @(*) - if (!i_reset && (r_last || M_LAST)) - assert(f_rcvd == 0); - else if (!i_reset) - assert(fill[WBLSB-1:0] == f_rcvd[WBLSB-1:0]); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - (* anyconst *) reg fc_check; - (* anyconst *) reg [F_LGCOUNT-1:0] fc_posn; - (* anyconst *) reg [7:0] fc_byte; - - wire frx_check, ftx_check; - reg [WBLSB-1:0] frx_shift; - reg [WBLSB+1:0] ftx_shift; - reg [DW-1:0] frx_shifted; - reg [2*DW-1:0] ftx_shifted; - - always @(*) - frx_shift = fc_posn [WBLSB-1:0]- f_rcvd[WBLSB-1:0]; - - always @(*) - if (OPT_LITTLE_ENDIAN) - frx_shifted = S_DATA >> (8*frx_shift); - else - frx_shifted = S_DATA << (8*frx_shift); - - assign frx_check = fc_check && S_VALID && f_rcvd <= fc_posn - && (fc_posn < f_rcvd + S_BYTES); - - always @(*) - if (!i_reset && frx_check) - begin - if (OPT_LITTLE_ENDIAN) - begin - assume(frx_shifted[7:0] == fc_byte); - end else begin - assume(frx_shifted[DW-1:DW-8] == fc_byte); - end - end - - always @(*) - begin - ftx_shift = fc_posn[WBLSB:0]- f_sent[WBLSB:0]; - ftx_shift[WBLSB+1] = 0; - end - - always @(*) - if (OPT_LITTLE_ENDIAN) - ftx_shifted = sreg >> (8*ftx_shift); - else - ftx_shifted = sreg << (8*ftx_shift); - - assign ftx_check = fc_check && f_sent <= fc_posn - && (fc_posn < f_sent + fill); - - always @(*) - if (!i_reset && ftx_check) - begin - if (OPT_LITTLE_ENDIAN) - begin - assert(ftx_shifted[7:0] == fc_byte); - end else begin - assert(ftx_shifted[2*DW-1:2*DW-8] == fc_byte); - end - end - - always @(*) - if (!i_reset) - begin - for(ik=0; ik<2*DW/8; ik=ik+1) - if (fill <= ik) - begin - if (OPT_LITTLE_ENDIAN) - assert(sreg[8*ik +: 8] == 8'h00); - else - assert(sreg[2*DW-8-8*ik +: 8] == 8'h00); - end - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipdma_s2mm.v b/delete_later/rtl/cpu/zipdma_s2mm.v deleted file mode 100644 index df94981..0000000 --- a/delete_later/rtl/cpu/zipdma_s2mm.v +++ /dev/null @@ -1,975 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipdma_s2mm.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: ZipDMA -- Writes data, having gone through the realignment -// pipeline, back to the bus. This data will be written either -// 1, 2, or 4 bytes at a time, or at the full width of the bus. -// -// When writing 2 or 4 bytes at a time, the address must (currently) be -// aligned. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipdma_s2mm #( - // {{{ - parameter ADDRESS_WIDTH=30, - parameter BUS_WIDTH = 64, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter LGPIPE = 10, - // Abbreviations - localparam DW = BUS_WIDTH, - localparam AW = ADDRESS_WIDTH-$clog2(DW/8) - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Configuration - // {{{ - input wire i_request, - output reg o_busy, o_err, - input wire i_inc, - input wire [1:0] i_size, - // input wire [LGLENGTH:0] i_transferlen, - input wire [ADDRESS_WIDTH-1:0] i_addr, // Byte address - // }}} - // Incoming Stream interface - // {{{ - input wire S_VALID, - output wire S_READY, - input wire [DW-1:0] S_DATA, - // How many bytes are valid? - input wire [$clog2(DW/8):0] S_BYTES, - input wire S_LAST, - // }}} - // Outgoing Wishbone interface - // {{{ - output reg o_wr_cyc, o_wr_stb, - output wire o_wr_we, - output reg [AW-1:0] o_wr_addr, - output reg [DW-1:0] o_wr_data, - output reg [DW/8-1:0] o_wr_sel, - input wire i_wr_stall, - input wire i_wr_ack, - input wire [DW-1:0] i_wr_data, - input wire i_wr_err - // }}} - // }}} - ); - - // Local decalarations - // {{{ - localparam [1:0] SZ_BYTE = 2'b11, - SZ_16B = 2'b10, - SZ_32B = 2'b01, - SZ_BUS = 2'b00; - localparam WBLSB = $clog2(DW/8); - integer ik; - // - reg r_inc; - reg [1:0] r_size; - // - reg [ADDRESS_WIDTH:0] next_addr; - reg [WBLSB-1:0] subaddr; - reg [2*DW-1:0] next_data; - reg [DW-1:0] r_data; - reg [2*DW/8-1:0] next_sel, pre_sel; - reg [DW/8-1:0] r_sel; - reg r_last; - - reg [LGPIPE-1:0] wb_outstanding; - reg wb_pipeline_full; - reg addr_overflow; - // }}} - - assign o_wr_we = 1'b1; - - // Copy config: r_inc, r_size(, r_addr) - // {{{ - always @(posedge i_clk) - if (i_request && !o_busy) - begin - r_inc <= i_inc; - r_size <= i_size; - // r_addr <= i_addr; - end - // }}} - - // next_addr - // {{{ - always @(*) - begin - next_addr = { 1'b0, o_wr_addr, subaddr }; - - if (o_wr_stb && !i_wr_stall) - case(r_size) - SZ_BYTE: if (r_inc) - next_addr = next_addr + 1; - SZ_16B: begin // 16-bit addressing - if (r_inc) - next_addr = next_addr + 2; - else - next_addr[ 0] = 0; - end - SZ_32B: begin // 32-bit addressing - if (r_inc) - next_addr = next_addr + 4; - else - next_addr[1:0] = 0; - end - SZ_BUS: begin // Full word addressing - if (r_inc) - next_addr = next_addr + { {(AW-1){1'b0}}, 1'b1, - {(WBLSB){1'b0}} }; - else - next_addr[WBLSB-1:0] = 0; - end - endcase - end - - always @(*) - addr_overflow = next_addr[ADDRESS_WIDTH]; -`ifdef FORMAL - always @(posedge i_clk) - if (!i_reset && o_busy && !r_inc) - case(r_size) - SZ_BYTE: begin end - SZ_16B: assert(next_addr[0] == 0); - SZ_32B: assert(next_addr[1:0] == 0); - SZ_BUS: assert(next_addr[WBLSB-1:0] == 0); - endcase -`endif - // }}} - - // next_data - // {{{ - always @(*) - if (OPT_LITTLE_ENDIAN) - begin - next_data = { {(DW){1'b0}}, r_data }; - - // Zero out unused data - for(ik=0; ik> (next_addr[WBLSB-1:0]*8)); - end - // }}} - - // next_sel - // {{{ - always @(*) - begin - pre_sel = 0; - - if (OPT_LITTLE_ENDIAN) - begin - for(ik=0; ik> (next_addr[WBLSB-1:0])); - end - end - // }}} - - // wb_pipeline_full, wb_outstanding - // {{{ - initial wb_pipeline_full = 1'b0; - initial wb_outstanding = 0; - always @(posedge i_clk) - if (i_reset || !o_wr_cyc || i_wr_err) - begin - wb_pipeline_full <= 1'b0; - wb_outstanding <= 0; - end else case({ (o_wr_stb && !i_wr_stall), i_wr_ack }) - 2'b10: begin - wb_pipeline_full <= (&wb_outstanding[LGPIPE-1:2]) - && (|wb_outstanding[1:0]); - wb_outstanding <= wb_outstanding + 1; - end - 2'b01: begin - wb_pipeline_full <= (&wb_outstanding[LGPIPE-1:0]); - wb_outstanding <= wb_outstanding - 1; - end - default: begin end - endcase - -`ifdef FORMAL - always @(*) - if (!i_reset || !o_wr_cyc) - assert(wb_pipeline_full == (&wb_outstanding[LGPIPE-1:1])); - - always @(*) - if (!i_reset && o_wr_cyc && (&wb_outstanding)) - assert(!o_wr_stb); -`endif - // }}} - - // crc, stb, o_wr_addr, o_wr_sel, o_busy, o_err, subaddr - // {{{ - initial o_wr_cyc = 1'b0; - initial o_wr_stb = 1'b0; - initial o_busy = 1'b0; - initial o_err = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - o_wr_cyc <= 0; - o_wr_stb <= 0; - o_wr_addr <= 0; - - o_busy <= 1'b0; - o_err <= 1'b0; - { o_wr_addr, subaddr } <= {(ADDRESS_WIDTH){1'b0}}; - r_last <= 1'b0; - // }}} - end else if (!o_busy || o_err || (o_wr_cyc && i_wr_err)) - begin - // {{{ - o_wr_cyc <= 0; - o_wr_stb <= 0; - o_wr_addr <= 0; - - o_busy <= i_request && !o_busy; - - o_err <= o_wr_cyc && i_wr_err; - if (o_wr_cyc && i_wr_err) - o_busy <= 1'b0; - - o_wr_addr <= i_addr[ADDRESS_WIDTH-1:WBLSB]; - subaddr <= i_addr[WBLSB-1:0]; - r_last <= 1'b0; - // }}} - end else if (!o_wr_stb || !i_wr_stall) - begin - // {{{ - o_wr_stb <= 1'b0; - - if (o_wr_stb) - { o_wr_addr, subaddr } <= next_addr[ADDRESS_WIDTH-1:0]; - - if (addr_overflow) - { o_err, o_wr_cyc, o_wr_stb } <= 3'b100; - else if (!wb_pipeline_full) - begin - if ((r_last && (|r_sel)) || (S_VALID && !r_last)) - begin - // Need to flush our last result out - { o_wr_cyc, o_wr_stb } <= 2'b11; - - end else if (wb_outstanding + (o_wr_stb ? 1:0) - == (i_wr_ack ? 1:0)) - begin - // We are all done writing - o_wr_cyc <= 1'b0; - o_busy <= !r_last; - end - end - - if (S_VALID && !r_last) - r_last <= S_LAST; - // }}} - end - -`ifdef FORMAL - always @(posedge i_clk) - if (i_reset || !o_busy || o_err || (o_wr_cyc && i_wr_err)) - begin - end else if (!o_wr_stb || !i_wr_stall) - begin - // {{{ - if (addr_overflow) - begin - end else if (!wb_pipeline_full) - begin - if (r_last && (|r_sel)) - begin - // Need to flush our last result out - assert(!S_READY); - end else if (S_VALID && !r_last) - begin - assert(S_VALID && S_READY); - end else begin - assert(!S_VALID || !S_READY); - end - end else begin - assert(!S_READY); - end - // }}} - end else begin - assert(!S_READY); - end - - always @(*) - if (!i_reset && !o_busy) - assert(!o_wr_cyc); -`endif - // }}} - - // o_wr_data, o_wr_sel - // {{{ - always @(posedge i_clk) - if (!o_busy) // i_reset || !o_busy || o_err || (o_wr_cyc && i_wr_err)) - begin - // {{{ - { r_data, o_wr_data } <= {(2*DW ){1'b0}}; - { r_sel, o_wr_sel } <= {(2*DW/8){1'b0}}; - // }}} - end else if ((!o_wr_stb || !i_wr_stall) && !wb_pipeline_full - && (r_last || S_VALID)) - begin - // {{{ - if (OPT_LITTLE_ENDIAN) - begin - { r_data, o_wr_data } <= next_data; - { r_sel, o_wr_sel } <= next_sel; - end else begin - { o_wr_data, r_data } <= next_data; - { o_wr_sel, r_sel } <= next_sel; - end - // }}} - end - // }}} - - assign S_READY = !r_last && o_busy && (!o_wr_stb || !i_wr_stall) - && !wb_pipeline_full; - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wr_data }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH = LGPIPE+1; - reg f_past_valid; - (* anyconst *) reg [ADDRESS_WIDTH-1:0] f_cfg_addr; - (* anyconst *) reg [1:0] f_cfg_size; - (* anyconst *) reg f_cfg_inc; - wire [F_LGDEPTH-1:0] fwb_nreqs, fwb_nacks, fwb_outstanding; - reg [ADDRESS_WIDTH:0] f_posn, fwb_addr, fwb_posn; - reg [WBLSB-1:0] fr_sel_count, fr_sel_count_past; - reg [ADDRESS_WIDTH-1:0] r_addr; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - //////////////////////////////////////////////////////////////////////// - // - // Control interface properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assume(!i_request); - else if ($past(i_request && o_busy)) - begin - assume(i_request); - assume($stable(i_inc)); - assume($stable(i_size)); - assume($stable(i_addr)); - end - - always @(posedge i_clk) - if (i_request && !o_busy) - begin - // r_inc <= i_inc; - // r_size <= i_size; - r_addr <= i_addr; - end - - always @(*) - if (!f_cfg_inc) case(f_cfg_size) - SZ_BYTE: begin end - SZ_16B: assume(f_cfg_addr[0] == 1'b0); - SZ_32B: assume(f_cfg_addr[1:0] == 2'b0); - SZ_BUS: assume(f_cfg_addr[WBLSB-1:0] == 0); - endcase - - always @(*) - if (i_request && !o_busy) - begin - assume(i_inc == f_cfg_inc); - assume(i_size == f_cfg_size); - assume(i_addr == f_cfg_addr); - end - - always @(*) - if (!i_reset && o_busy) - begin - assert(r_addr == f_cfg_addr); - assert(r_size == f_cfg_size); - assert(r_inc == f_cfg_inc); - - if (!r_inc) - case(r_size) - SZ_BYTE: begin end - SZ_16B: assert(r_addr[0] == 1'b0); - SZ_32B: assert(r_addr[1:0] == 2'b0); - SZ_BUS: assert(r_addr[WBLSB-1:0] == 0); - endcase - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - assume(!S_VALID); - end else if ($past(S_VALID && !S_READY)) - begin - assume(S_VALID); - assume($stable(S_DATA)); - assume($stable(S_BYTES)); - assume($stable(S_LAST)); - end - - always @(*) - if (S_VALID) - begin - assume(S_BYTES <= DW/8); - assume(S_BYTES > 0); - - if (!S_LAST) - case(f_cfg_size) - 2'b11: assume(S_BYTES == 1); - 2'b10: assume(S_BYTES == 2); - 2'b01: assume(S_BYTES == 4); - 2'b00: assume(S_BYTES == (DW/8)); - endcase - else case(f_cfg_size) - 2'b11: assume(S_BYTES == 1); - 2'b10: assume(S_BYTES <= 2); - 2'b01: assume(S_BYTES <= 4); - 2'b00: assume(S_BYTES <= (DW/8)); - endcase - end - - always @(posedge i_clk) - if (i_reset || !o_busy) - f_posn <= 0; - else if (S_VALID && S_READY) - f_posn <= f_posn + S_BYTES; - - always @(*) - if (o_busy) - assume(!f_posn[ADDRESS_WIDTH] || (f_posn[ADDRESS_WIDTH-1:0]==0 - && r_last)); - - always @(*) - if (!i_reset && o_busy) - begin - if (r_last) - begin - end else case(f_cfg_size) - 2'b11: begin end - 2'b10: assert(f_posn[0] == 1'b0); - 2'b01: assert(f_posn[1:0] == 2'b0); - 2'b00: assert(f_posn[WBLSB-1:0] == 0); - endcase - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - fwb_master #( - .AW(AW), .DW(DW), .F_LGDEPTH(F_LGDEPTH), - .F_OPT_DISCONTINUOUS(1'b1), - .F_MAX_STALL(2), - .F_MAX_ACK_DELAY(2) - ) fwb ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc( o_wr_cyc), - .i_wb_stb( o_wr_stb), - .i_wb_we( o_wr_we), - .i_wb_addr(o_wr_addr), - .i_wb_data(o_wr_data), - .i_wb_sel( o_wr_sel), - // - .i_wb_stall(i_wr_stall), - .i_wb_ack( i_wr_ack), - .i_wb_idata(i_wr_data), - .i_wb_err( i_wr_err), - // - .f_nreqs(fwb_nreqs), - .f_nacks(fwb_nacks), - .f_outstanding(fwb_outstanding) - // }}} - ); - - always @(*) - if (!i_reset && o_wr_stb) - assert(|o_wr_sel); - - always @(*) - if (o_wr_cyc) - assert(fwb_outstanding == wb_outstanding); - - initial fwb_posn = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - fwb_posn <= 0; - else if (o_wr_stb && !i_wr_stall) - fwb_posn <= fwb_posn + $countones(o_wr_sel); - - always @(*) - if (!i_reset && o_busy && !o_err) - assert(f_posn == fwb_posn + $countones(r_sel) - + (o_wr_stb ? $countones(o_wr_sel) : 0)); - - always @(*) - if (r_inc) - begin - fwb_addr = r_addr + fwb_posn; - - if (fwb_posn > 0) - case(r_size) - SZ_16B: fwb_addr[ 0] = 0; - SZ_32B: fwb_addr[1:0] = 0; - SZ_BUS: fwb_addr[WBLSB-1:0] = 0; - default: begin end - endcase - end else begin - // fwb_addr = r_addr + fwb_posn; - fwb_addr = r_addr; - - case(r_size) - SZ_BYTE: begin end - SZ_16B: fwb_addr[0] = 0; - SZ_32B: fwb_addr[1:0] = 0; - SZ_BUS: fwb_addr[WBLSB-1:0] = 0; - endcase - end - - always @(*) - if (!i_reset && o_busy && !r_last && !o_err) - // && (o_wr_stb || !fwb_addr[ADDRESS_WIDTH]) && !r_last) - begin - assert({ 1'b0, o_wr_addr } == fwb_addr[ADDRESS_WIDTH:WBLSB]); - case(r_size) - SZ_BUS: assert(subaddr == r_addr[WBLSB-1:0]); - SZ_16B: assert(subaddr == { fwb_addr[WBLSB-1:1], r_addr[0] }); - SZ_32B: assert(subaddr == { fwb_addr[WBLSB-1:2], r_addr[1:0] }); - default: - assert(subaddr == fwb_addr[WBLSB-1:0]); - endcase - end - - always @(*) - if (o_busy && fwb_addr[ADDRESS_WIDTH] && !r_last) - begin - assert(o_err); - // assert(fwb_addr[ADDRESS_WIDTH-1:0] <= DW/8); - end - - always @(*) - if (!o_busy || o_err) - assert(!o_wr_cyc); - - always @(*) - if (!i_reset && o_busy) - begin - if (!r_inc) - case(r_size) - SZ_BYTE: begin end - SZ_16B: assert(subaddr[0] == 1'b0); - SZ_32B: assert(subaddr[1:0] == 2'b00); - SZ_BUS: assert(subaddr == 0); - endcase else case(r_size) - SZ_BYTE: begin end - SZ_16B: assert(subaddr[0] == r_addr[0]); - SZ_32B: assert(subaddr[1:0] == r_addr[1:0]); - SZ_BUS: assert(subaddr == r_addr[WBLSB-1:0]); - endcase - end - - always @(*) - fr_sel_count = $countones(r_sel); - - always @(posedge i_clk) - if (!o_wr_sel || !i_wr_stall) - fr_sel_count_past <= fr_sel_count; - - always @(posedge i_clk) - if(!i_reset && o_busy && !o_err && !r_last && $past(S_VALID && S_READY)) - begin - assert(o_wr_stb); - assert($countones({ r_sel, o_wr_sel }) - == $past(S_BYTES + fr_sel_count)); - end - - always @(*) - if (!i_reset && o_busy) - begin - if (o_err) - assert(!o_wr_cyc); - if (f_posn == 0) - begin - assert(r_sel == 0); - assert(!o_wr_cyc); - assert(wb_outstanding == 0); - end else - case(r_size) - SZ_BYTE: assert(r_sel == 0); - SZ_16B: begin - if (OPT_LITTLE_ENDIAN) - begin - assert(r_sel[DW/8-1:1] == 0); - end else begin - assert(r_sel[DW/8-2:0] == 0); - end - - if (!o_wr_stb) begin end - else if (subaddr + 2 <= DW/8) - begin - assert(r_sel == 0); - end else if (!r_last) - begin - assert(r_sel[(OPT_LITTLE_ENDIAN) ? 0 : (DW/8-1)] == (subaddr+2 > DW/8)); - end else begin - assert(r_sel[(OPT_LITTLE_ENDIAN) ? 0 : (DW/8-1)] <= (subaddr+2 > DW/8)); - end end - SZ_32B: begin - if (OPT_LITTLE_ENDIAN) - begin - assert(r_sel[DW/8-1:3] == 0); - end else begin - assert(r_sel[DW/8-4:0] == 0); - end - - if (!o_wr_stb) begin end - else if (subaddr + 4 <= DW/8) - begin - assert(r_sel == 0); - /* - end else if (!r_last) - begin - assert($countones(r_sel) == subaddr+4-DW/8); - end else begin - assert($countones(r_sel) <= subaddr+4-DW/8); - */ - end end - SZ_BUS: begin - assert(!(&r_sel)); - if (subaddr == 0) - assert(r_sel == 0); - end - default: begin end - endcase - - if (OPT_LITTLE_ENDIAN) - begin - if (!o_wr_sel[DW/8-1]) - assert(!r_sel[0]); - end else begin - if (!o_wr_sel[0]) - assert(!r_sel[DW/8-1]); - end - - for(ik=0; ik 2) - assert(!r_sel[ik]); - SZ_BUS: if (ik >= r_addr[DW/8-1:0]) - assert(!r_sel[ik]); - default: begin end - endcase - end else begin - if (ik > 0 && !r_sel[DW/8-ik]) - begin - assert(!r_sel[DW/8-1-ik]); - end - - case(r_size) - SZ_32B: begin - /*if (ik >= 4 || subaddr + ik < DW/8 - || subaddr + ik - DW/8 >= 4) - // assert(!r_sel[subaddr+ik-DW/8]); - assert(!r_sel[DW/5-1-ik-subaddr]); - */ - end - SZ_BUS: begin - /* - if (ik > DW/8-1-i_addr[DW/8-1:0]) - assert(!r_sel[ik]); - */ - end - default: begin end - endcase - end - end - - always @(*) - if (!i_reset && o_busy && !r_inc) - assert(r_sel == 0); - - reg [WBLSB-1:0] f_sum; - - always @(*) - if (r_inc) - f_sum = fwb_posn[WBLSB-1:0] + r_addr[WBLSB-1:0]; - else - f_sum = fwb_posn[WBLSB-1:0]; - - always @(*) - if (!i_reset && o_busy && fwb_posn > 0) - begin - if (!r_last) case(r_size) - SZ_16B: assert(f_sum[ 0] == 0); - SZ_32B: assert(f_sum[1:0] == 0); - SZ_BUS: assert(f_sum[WBLSB-1:0] == 0); - default: begin end - endcase - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - (* anyconst *) reg fc_check; - (* anyconst *) reg [ADDRESS_WIDTH:0] fc_posn; - (* anyconst *) reg [7:0] fc_byte; - - reg [ADDRESS_WIDTH:0] f_shift, fwb_shift; - reg [DW-1:0] fc_partial; - reg [2*DW-1:0] fc_partial_wb; - reg [2*DW/8-1:0] fc_partial_sel; - wire [DW-1:0] fz_data; - wire [DW/8-1:0] fz_sel; - - assign fz_data = 0; - assign fz_sel = 0; - - always @(*) - begin - f_shift = (fc_posn - f_posn); - f_shift[ADDRESS_WIDTH:WBLSB] = 0; - end - - always @(*) - if (OPT_LITTLE_ENDIAN) - fc_partial = S_DATA >> (8*f_shift); - else - fc_partial = S_DATA << (8*f_shift); - - wire fin_check, fwb_check; - assign fin_check = fc_check && S_VALID && (f_posn <= fc_posn) - && (fc_posn < f_posn + S_BYTES); - assign fwb_check = fc_check && o_busy && !o_err - && (fwb_posn <= fc_posn) - &&((o_wr_stb && fc_posn < fwb_posn + $countones(o_wr_sel)) - ||(!o_wr_stb && fc_posn < fwb_posn + $countones(r_sel))); - - always @(*) - if (fin_check) - begin - if (OPT_LITTLE_ENDIAN) - assume(fc_partial[7:0] == fc_byte); - else - assume(fc_partial[DW-1:DW-8] == fc_byte); - end - - always @(*) - begin - fwb_shift = 0; - if (r_inc) - begin - fwb_shift[WBLSB-1:0] = fc_posn[WBLSB-1:0] - - fwb_posn[WBLSB-1:0]; - if (o_wr_stb) - fwb_shift[WBLSB-1:0] = fwb_shift[WBLSB-1:0] + fwb_addr[WBLSB-1:0]; - end else - fwb_shift[WBLSB-1:0] = fc_posn[WBLSB-1:0] - fwb_posn[WBLSB-1:0] - + r_addr[WBLSB-1:0]; - end - - always @(*) - if (OPT_LITTLE_ENDIAN) - begin - if (o_wr_stb) - begin - fc_partial_wb ={ r_data, o_wr_data} >> (8*fwb_shift); - fc_partial_sel={ r_sel, o_wr_sel } >> fwb_shift; - end else begin - fc_partial_wb ={ fz_data, r_data} >> (8*fwb_shift); - fc_partial_sel={ fz_sel, r_sel } >> fwb_shift; - end - end else begin - if (o_wr_stb) - begin - fc_partial_wb ={ o_wr_data, r_data }<< (8*fwb_shift); - fc_partial_sel={ o_wr_sel, r_sel } << fwb_shift; - end else begin - fc_partial_wb ={ r_data,fz_data } << (8*fwb_shift); - fc_partial_sel={ r_sel, fz_sel } << fwb_shift; - end - end - - always @(*) - if (o_busy) - assert(fwb_posn <= f_posn); - - always @(*) - if (fwb_check) - begin - if (OPT_LITTLE_ENDIAN) - begin - assert(fc_partial_wb[7:0] == fc_byte); - assert(fc_partial_sel[0]); - end else begin - assert(fc_partial_wb[2*DW-1:2*DW-8] == fc_byte); - assert(fc_partial_sel[2*DW/8-1]); - end - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!i_reset && !$past(i_reset)) - cover(i_request); - - always @(posedge i_clk) - if (!i_reset && !$past(i_reset)) - cover(o_busy); - - always @(posedge i_clk) - if (!i_reset && !$past(i_reset) && $past(o_busy)) - begin - cover(!o_busy); - - if (!o_busy) - begin - case({ r_inc, r_size }) - 3'b000: cover(f_posn > DW/8); - 3'b001: cover(f_posn > DW/8); - 3'b010: cover(f_posn > DW/8); - 3'b011: cover(f_posn > DW/8); - 3'b100: cover(f_posn > DW/8); - 3'b101: cover(f_posn > DW/8); - 3'b110: cover(f_posn > DW/8); - 3'b111: cover(f_posn > DW/8); - endcase - end - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - case(f_cfg_size) - SZ_BYTE: begin end - SZ_BUS: begin end - SZ_16B: assume(f_cfg_addr[0] == 1'b0); - SZ_32B: assume(f_cfg_addr[1:0] == 2'b0); - endcase - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipdma_txgears.v b/delete_later/rtl/cpu/zipdma_txgears.v deleted file mode 100644 index 98bd703..0000000 --- a/delete_later/rtl/cpu/zipdma_txgears.v +++ /dev/null @@ -1,757 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipdma_txgears.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: ZipDMA -- Unpack bus words into 1, 2, 4, or more bytes per -// outgong word. This is to support peripherals which require -// 1, 2, or 4 byte transfers (only), as well as peripherals like memory -// with no such restrictions. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipdma_txgears #( - // {{{ - parameter BUS_WIDTH = 512, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - // Abbreviations - localparam DW = BUS_WIDTH - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Configuration - // {{{ - input wire i_soft_reset, - input wire [1:0] i_size, - // }}} - // Incoming Stream interface - // {{{ - input wire S_VALID, - output wire S_READY, - input wire [DW-1:0] S_DATA, - // How many bytes are valid? - input wire [$clog2(DW/8):0] S_BYTES, - input wire S_LAST, - // }}} - // Outgoing Stream interface - // {{{ - output wire M_VALID, - input wire M_READY, - output wire [DW-1:0] M_DATA, - // How many bytes are valid? - output wire [$clog2(DW/8):0] M_BYTES, - output wire M_LAST - // }}} - // }}} - ); - - // Local declarations - // {{{ - localparam WBLSB = $clog2(DW/8); - localparam [1:0] SZ_BYTE = 2'b11, - SZ_16B = 2'b10, - SZ_32B = 2'b01, - SZ_BUS = 2'b00; - reg m_valid, m_last, r_last, r_next; - reg [DW-1:0] sreg; - reg [WBLSB:0] m_bytes, fill; - // }}} - - // sreg, fill - // {{{ - initial {sreg, fill } = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - begin - sreg <= 0; - fill <= 0; - end else if (S_VALID && S_READY) - begin - sreg <= S_DATA; - fill <= S_BYTES; - end else if (M_VALID && M_READY) - begin - if (M_LAST) - { sreg, fill } <= 0; - else if (OPT_LITTLE_ENDIAN) - begin - // Verilator coverage_off - case(i_size) - SZ_BYTE: begin sreg <= sreg >> 8; fill <= fill - 1; end - SZ_16B: begin sreg <= sreg >> 16; fill <= fill - 2; end - SZ_32B: begin sreg <= sreg >> 32; fill <= fill - 4; end - SZ_BUS: begin sreg <= 0; fill <= 0; end - endcase - // Verilator coverage_on - end else begin - case(i_size) - SZ_BYTE: begin sreg <= sreg << 8; fill <= fill - 1; end - SZ_16B: begin sreg <= sreg << 16; fill <= fill - 2; end - SZ_32B: begin sreg <= sreg << 32; fill <= fill - 4; end - SZ_BUS: begin sreg <= 0; fill <= 0; end - endcase - end - end -`ifdef FORMAL - always @(*) - if (!i_reset) - assert(fill <= (DW/8)); -`endif - // }}} - - // m_valid - // {{{ - initial m_valid = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - m_valid <= 0; - else if (!M_VALID || M_READY) - begin - if (S_VALID && S_READY) - m_valid <= 1'b1; - else case(i_size) - SZ_BYTE: m_valid <= (fill > 1); - SZ_16B: m_valid <= (fill > 2); - SZ_32B: m_valid <= (fill > 4); - SZ_BUS: m_valid <= 0; - endcase - end -`ifdef FORMAL - always @(*) - if (m_valid) - assert(m_bytes <= fill); -`endif - // }}} - - // m_bytes - // {{{ - generate if (BUS_WIDTH > 32) - begin : GEN_MBYTES - // {{{ - initial m_bytes = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - m_bytes <= 0; - else if (S_VALID && S_READY) - begin - case(i_size) - SZ_BYTE: m_bytes <= 1; - SZ_16B: m_bytes <= (S_BYTES > 2) ? 2 : S_BYTES; - SZ_32B: m_bytes <= (S_BYTES > 4) ? 4 : S_BYTES; - SZ_BUS: m_bytes <= S_BYTES; - endcase - end else if (!M_VALID || M_READY) - begin - case(i_size) - SZ_BYTE: m_bytes <= 1; - SZ_16B: m_bytes <= (fill >= 4) ? 2 - : (&fill[1:0]) ? 1 : 0; - SZ_32B: m_bytes <= (fill >= 8) ? 4 - : (fill[2]) ? ({ {(WBLSB-1){1'b0}}, fill[1:0] }) - : 0; - SZ_BUS: m_bytes <= 0; - endcase - end - // }}} - end else begin : MIN_MBYTES - // {{{ - initial m_bytes = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - m_bytes <= 0; - else if (S_VALID && S_READY) - begin - casez(i_size) - SZ_BYTE: m_bytes <= 1; - SZ_16B: m_bytes <= (S_BYTES > 2) ? 2 : S_BYTES; - default: m_bytes <= S_BYTES; - endcase - end else if (!M_VALID || M_READY) - begin - casez(i_size) - SZ_BYTE: m_bytes <= 1; - SZ_16B: m_bytes <= (fill >= 4) ? 2 - : (&fill[1:0]) ? 1 : 0; - default: m_bytes <= 0; - endcase - end - // }}} - end endgenerate -`ifdef FORMAL - // {{{ - always @(*) - if (!i_reset && M_VALID) - begin - assert(m_bytes > 0); - assert(m_bytes <= fill); - if (M_LAST) - assert(m_bytes == fill); - - case(i_size) - SZ_BYTE: assert(m_bytes == 1); - SZ_16B: begin - assert(m_bytes <= 2); - if (m_bytes < 2) - assert(M_LAST && m_bytes == fill); - end - SZ_32B: begin - assert(m_bytes <= 4); - if (m_bytes < 4) - assert(M_LAST && m_bytes == fill); - end - SZ_BUS: begin - assert(m_bytes <= DW/8); - if (m_bytes < (DW/8)) - assert(M_LAST && m_bytes == fill); - end - endcase - end - // }}} -`endif - // }}} - - // r_next -- Are we on our last word? - // {{{ - // Only allow S_READY if r_next is true, so r_next must be true when - // we output the last word of the shift register. - generate if (BUS_WIDTH > 32) - begin : GEN_NEXT - // {{{ - initial r_next = 1; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - r_next <= 1; - else if (M_VALID && M_READY && M_LAST) - r_next <= 1; - else if (S_VALID && S_READY) - begin - case(i_size) - SZ_BYTE:r_next <= (S_BYTES == 1); - SZ_16B: r_next <= (S_BYTES <= 2); - SZ_32B: r_next <= (S_BYTES <= 4); - SZ_BUS: r_next <= 1; - endcase - - if (S_LAST) - r_next <= 0; - end else if (M_VALID && M_READY) - begin - case(i_size) - SZ_BYTE:r_next <= (fill <= 2); - SZ_16B: r_next <= (fill <= 4); - SZ_32B: r_next <= (fill <= 8); - SZ_BUS: r_next <= 1; - endcase - - if (r_last) - r_next <= 0; - end - // }}} - end else begin : MIN_NEXT - // {{{ - initial r_next = 1; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - r_next <= 1; - else if (M_VALID && M_READY && M_LAST) - r_next <= 1; - else if (S_VALID && S_READY) - begin - casez(i_size) - SZ_BYTE: r_next <= (S_BYTES == 1); - SZ_16B: r_next <= (S_BYTES <= 2); - default: r_next <= 1; - endcase - - if (S_LAST) - r_next <= 0; - end else if (M_VALID && M_READY) - begin - casez(i_size) - SZ_BYTE: r_next <= (fill <= 2); - SZ_16B: r_next <= (fill <= 4); - default: r_next <= 1; - endcase - - if (r_last) - r_next <= 0; - end - // }}} - end endgenerate - -`ifdef FORMAL - // {{{ - reg [1:0] f_mid_packet; - - // f_mid_packet - // {{{ - initial f_mid_packet = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - f_mid_packet <= 0; - else if (S_VALID && S_READY) - f_mid_packet <= (S_LAST) ? 2'b10 : 2'b01; - else if (M_VALID && M_READY && M_LAST) - f_mid_packet <= 2'b00; - - always @(*) - assert(f_mid_packet != 2'b11); - // }}} - - always @(*) - if (!i_reset) begin - - assert(f_mid_packet[1] == (r_last || m_last)); - - if (f_mid_packet[1]) - begin - assert(!r_next); - end else case(i_size) - SZ_BYTE:assert(r_next == (fill <= 1)); - SZ_16B: assert(r_next == (fill <= 2)); - SZ_32B: assert(r_next == (fill <= 4)); - SZ_BUS: assert(r_next); - endcase - end - // }}} -`endif - // }}} - - // r_last, m_last - // {{{ - generate if (BUS_WIDTH > 32) - begin : GEN_LAST - // {{{ - initial { r_last, m_last } = 2'b00; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - { r_last, m_last } <= 0; - else if (S_VALID && S_READY) - begin - case(i_size) - SZ_BYTE: { r_last, m_last } <= { (S_BYTES > 1), (S_BYTES == 1) }; - SZ_16B: { r_last, m_last } <= { (S_BYTES > 2), (S_BYTES <= 2) }; - SZ_32B: { r_last, m_last } <= { (S_BYTES > 4), (S_BYTES <= 4) }; - SZ_BUS: { r_last, m_last } <= { 1'b0, S_LAST }; - endcase - - if (!S_LAST) - { r_last, m_last } <= 2'b00; - end else if (M_VALID && M_READY) - begin - case(i_size) - SZ_BYTE:m_last <= r_last && (fill <= 2); - SZ_16B: m_last <= r_last && (fill <= 4); - SZ_32B: m_last <= r_last && (fill <= 8); - SZ_BUS: m_last <= 0; - endcase - - case(i_size) - SZ_BYTE:r_last <= r_last && (fill > 2); - SZ_16B: r_last <= r_last && (fill > 4); - SZ_32B: r_last <= r_last && (fill > 8); - SZ_BUS: r_last <= 0; - endcase - - // if (M_LAST) - // { r_last, m_last } <= 2'b00; - end - // }}} - end else begin : MIN_LAST - // {{{ - initial { r_last, m_last } = 2'b00; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - { r_last, m_last } <= 0; - else if (S_VALID && S_READY) - begin - casez(i_size) - SZ_BYTE: { r_last, m_last } <= { (S_BYTES > 1), (S_BYTES == 1) }; - SZ_16B: { r_last, m_last } <= { (S_BYTES > 2), (S_BYTES <= 2) }; - default: { r_last, m_last } <= { (S_BYTES > 4), (S_BYTES <= 4) }; - endcase - - if (!S_LAST) - { r_last, m_last } <= 2'b00; - end else if (!M_VALID || M_READY) - begin - casez(i_size) - SZ_BYTE: m_last <= r_last && (fill <= 2); - SZ_16B: m_last <= r_last && (fill <= 4); - default: m_last <= 0; - endcase - - casez(i_size) - SZ_BYTE: r_last <= r_last && (fill > 2); - SZ_16B: r_last <= r_last && (fill > 4); - default: r_last <= 0; - endcase - - // if (M_LAST) - // { r_last, m_last } <= 2'b00; - end - // }}} - end endgenerate - -`ifdef FORMAL - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && M_VALID && M_READY && M_LAST)) - assert({ r_last, m_last } == 2'b00); -`endif - // }}} - - assign M_VALID = m_valid; - assign M_DATA = sreg; - assign M_BYTES = m_bytes; - assign M_LAST = m_last; - - assign S_READY = !M_VALID || (M_READY && r_next); -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGCOUNT = 16; - reg f_past_valid; - (* anyconst *) reg [1:0] f_cfg_size; - reg [F_LGCOUNT-1:0] f_rcvd, f_sent; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - always @(*) - if (!i_reset) - assume(i_size == f_cfg_size); - - //////////////////////////////////////////////////////////////////////// - // - // Incoming stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Basic stream properties - // {{{ - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset || i_soft_reset)) - assume(!S_VALID); - else if ($past(S_VALID && !S_READY)) - begin - assume(S_VALID); - assume($stable(S_DATA)); - assume($stable(S_BYTES)); - assume($stable(S_LAST)); - end - // }}} - - // Properties of S_BYTES: incoming words are packed - // {{{ - always @(*) - if (!i_reset && S_VALID) - begin - assume(S_BYTES > 0); - assume(S_BYTES <= (DW/8)); - if (!S_LAST) - assume(S_BYTES == (DW/8)); - end - // }}} - - // f_rcvd - // {{{ - initial f_rcvd = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - f_rcvd = 0; - else if (S_VALID && S_READY) - begin - if (S_LAST) - f_rcvd <= 0; - else - f_rcvd <= f_rcvd + S_BYTES; - end - - always @(*) - assume(!f_rcvd[F_LGCOUNT-1]); - - always @(*) - if (f_mid_packet == 2'b00 || f_mid_packet == 2'b10) - begin - assert(f_rcvd == 0); - end else - assert(f_rcvd > 0); - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Outgoing stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Basic stream property - // {{{ - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset || i_soft_reset)) - assert(!M_VALID); - else if ($past(M_VALID && !M_READY)) - begin - assert(M_VALID); - assert($stable(M_DATA)); - assert($stable(M_BYTES)); - assert($stable(M_LAST)); - end - // }}} - - // Bounding/checking M_LAST - // {{{ - always @(*) - if (!i_reset && M_VALID) - begin - assert(M_BYTES > 0); - assert(M_BYTES <= (DW/8)); - - if (!M_LAST) - case(f_cfg_size) - SZ_BYTE: assert(M_BYTES == 1); - SZ_16B: assert(M_BYTES == 2); - SZ_32B: assert(M_BYTES == 4); - SZ_BUS: assert(M_BYTES == (DW/8)); - endcase - else - case(f_cfg_size) - SZ_BYTE: assert(M_BYTES == 1); - SZ_16B: assert(M_BYTES <= 2); - SZ_32B: assert(M_BYTES <= 4); - SZ_BUS: assert(M_BYTES <= (DW/8)); - endcase - end - // }}} - - // Bounding/checking fill - // {{{ - always @(*) - if (!i_reset) - begin - assert(!r_last || !M_LAST); - if (r_last || M_LAST) - assert(M_VALID); - - if (r_last) - case(f_cfg_size) - SZ_BYTE: assert(fill > 1); - SZ_16B: assert(fill > 2); - SZ_32B: assert(fill > 4); - SZ_BUS: assert(0); - endcase - - if (M_LAST) - begin - assert(fill > 0); - - case(f_cfg_size) - 2'b11: assert(fill == 1); - SZ_16B: assert(fill <= 2); - SZ_32B: assert(fill <= 4); - SZ_BUS: begin end - endcase - end - end - - always @(*) - if (!i_reset) - begin - assert(fill <= (DW/8)); - assert(M_VALID == (fill > 0)); - - if (M_LAST) - assert(fill == M_BYTES); - - if (!M_LAST && !r_last) - case(f_cfg_size) - SZ_BYTE: begin end // assert(fill > 0); - SZ_16B: assert(fill[0] == 1'b0); - SZ_32B: assert(fill[1:0] == 2'b00); - SZ_BUS: assert(fill[WBLSB-1:0] == 0); - endcase - end - // }}} - - // f_sent - // {{{ - initial f_sent = 0; - always @(posedge i_clk) - if (i_reset || i_soft_reset) - f_sent <= 0; - else if (M_VALID && M_READY) - begin - if (M_LAST) - f_sent <= 0; - else - f_sent <= f_sent + M_BYTES; - end - - always @(*) - begin - assume(!f_sent[F_LGCOUNT-1]); - - if (!r_last && !m_last) - begin - assert(f_sent + fill == f_rcvd); - assert(f_sent <= f_rcvd); - end - end - - always @(*) - if (f_mid_packet == 2'b00) - begin - assert(f_sent == 0); - end else if (f_mid_packet == 2'b10) - assert(M_VALID || f_sent > 0); - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Contract" properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - (* anyconst *) reg fc_check; - (* anyconst *) reg [F_LGCOUNT-1:0] fc_posn; - (* anyconst *) reg [7:0] fc_byte; - - wire fs_check, fm_check; - reg [WBLSB-1:0] fs_shift, fm_shift; - reg [DW-1:0] fs_shifted, fm_shifted; - - // Slave assumption - // {{{ - assign fs_check = fc_check && S_VALID && f_rcvd <= fc_posn - && (fc_posn < f_rcvd + S_BYTES); - - always @(*) - fs_shift = fc_posn - f_rcvd; - - always @(*) - if (OPT_LITTLE_ENDIAN) - fs_shifted = S_DATA >> (8*fs_shift); - else - fs_shifted = S_DATA << (8*fs_shift); - - always @(*) - if (!i_reset && fs_check) - begin - if (OPT_LITTLE_ENDIAN) - assume(fs_shifted[7:0] == fc_byte); - else - assume(fs_shifted[DW-1:DW-8] == fc_byte); - end - // }}} - - // Master assertion - // {{{ - assign fm_check = fc_check && f_sent <= fc_posn - && (fc_posn < f_sent + fill); - - always @(*) - fm_shift = fc_posn - f_sent; - - always @(*) - if (OPT_LITTLE_ENDIAN) - fm_shifted = sreg >> (8*fm_shift); - else - fm_shifted = sreg << (8*fm_shift); - - always @(*) - if (!i_reset && fm_check) - begin - if (OPT_LITTLE_ENDIAN) - begin - assert(fm_shifted[7:0] == fc_byte); - end else begin - assert(fm_shifted[DW-1:DW-8] == fc_byte); - end - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!i_reset && M_VALID && M_READY && M_LAST) - begin - cover(i_size == SZ_BYTE && f_sent > DW/8); - cover(i_size == SZ_16B && f_sent > DW/8); - cover(i_size == SZ_32B && f_sent > DW/8); - cover(i_size == SZ_BUS && f_sent > DW/8); - - cover(i_size == SZ_BYTE && f_sent > 2*DW/8+1); - cover(i_size == SZ_16B && f_sent > 2*DW/8+1); - cover(i_size == SZ_32B && f_sent > 2*DW/8+1); - cover(i_size == SZ_BUS && f_sent > 2*DW/8+1); - - cover(i_size == SZ_BUS && f_sent > 2*DW/8+2); - cover(i_size == SZ_BUS && f_sent > 2*DW/8+3); - cover(i_size == SZ_BUS && f_sent > 2*DW/8+4); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipjiffies.v b/delete_later/rtl/cpu/zipjiffies.v deleted file mode 100644 index f3ba553..0000000 --- a/delete_later/rtl/cpu/zipjiffies.v +++ /dev/null @@ -1,334 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipjiffies.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This peripheral is motivated by the Linux use of 'jiffies'. -// A process, in Linux, can request to be put to sleep until a certain -// number of 'jiffies' have elapsed. Using this interface, the CPU can -// read the number of 'jiffies' from this peripheral (it only has the -// one location in address space), add the sleep length to it, and -// write the result back to the peripheral. The zipjiffies peripheral -// will record the value written to it only if it is nearer the current -// counter value than the last current waiting interrupt time. If no -// other interrupts are waiting, and this time is in the future, it will -// be enabled. (There is currrently no way to disable a jiffie interrupt -// once set.) The processor may then place this sleep request into a -// list among other sleep requests. Once the timer expires, it would -// write the next jiffy request to the peripheral and wake up the process -// whose timer had expired. -// -// Quite elementary, really. -// -// Interface: -// This peripheral contains one register: a counter. Reads from the -// register return the current value of the counter. Writes within -// the (N-1) bit space following the current time set an interrupt. -// Writes of values that occurred in the last 2^(N-1) ticks will be -// ignored. The timer then interrupts when its value equals that time. -// Multiple writes cause the jiffies timer to select the nearest possible -// interrupt. Upon an interrupt, the next interrupt time/value is cleared -// and will need to be reset if the CPU wants to get notified again. With -// only the single interface, there is no way of knowing when the next -// interrupt is scheduled for, neither is there any way to slow down the -// interrupt timer in case you don't want it overflowing as often and you -// wish to wait more jiffies than it supports. Thus, currently, if you -// have a timer you wish to wait upon that is more than 2^31 into the -// future, you would need to set timers along the way, wake up on those -// timers, and set further timer's until you finally get to your -// destination. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipjiffies #( - parameter BW = 32 - ) ( - // {{{ - input wire i_clk, i_reset, i_ce, - // Wishbone inputs - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [(BW-1):0] i_wb_data, - input wire [BW/8-1:0] i_wb_sel, - // Wishbone outputs - output wire o_wb_stall, - output reg o_wb_ack, - output wire [(BW-1):0] o_wb_data, - // Interrupt line - output reg o_int - // }}} - ); - - // Local declarations - // {{{ - reg [(BW-1):0] r_counter; - // - reg int_set, new_set, int_now; - reg [(BW-1):0] int_when, new_when; - reg signed [(BW-1):0] till_wb, till_when; - // }}} - - // r_counter - // {{{ - // Our counter logic: The counter is always counting up--it cannot - // be stopped or altered. It's really quite simple. Okay, not quite. - // We still support the clock enable line. We do this in order to - // support debugging, so that if we get everything running inside a - // debugger, the timer's all slow down so that everything can be stepped - // together, one clock at a time. - // - initial r_counter = 0; - always @(posedge i_clk) - if (i_reset) - r_counter <= 0; - else if (i_ce) - r_counter <= r_counter+1; - // }}} - - // int_now - // {{{ - initial int_now = 0; - always @(posedge i_clk) - if (i_reset) - int_now <= 0; - else if (i_ce) - int_now <= ((r_counter + 1) == (int_when)); - else - int_now <= 1'b0; - // }}} - - // new_set, new_when - // {{{ - // Writes to the counter set an interrupt--but only if they are in the - // future as determined by the signed result of an unsigned subtract. - // - // assign till_when = int_when-r_counter; - // assign till_wb = new_when-r_counter; - - initial new_set = 1'b0; - always @(posedge i_clk) - begin - // Delay WB commands (writes) by a clock to simplify our logic - new_set <= (i_wb_stb && i_wb_we); - // new_when is a don't care when new_set = 0, so don't worry - // about setting it at all times. - new_when<= i_wb_data; - - till_wb <= (i_wb_data - r_counter - (i_ce ? 1:0)); - - till_when <= (int_when - i_wb_data); - - if (i_reset) - new_set <= 1'b0; - end - // }}} - - // o_int, int_set - // {{{ - initial o_int = 1'b0; - initial int_set = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - o_int <= 0; - int_set <= 0; - // }}} - end else begin - // {{{ - o_int <= 1'b0; - if ((i_ce)&&(int_set)&&(r_counter == int_when)) - // Interrupts are self-clearing - o_int <= 1'b1; // Set the interrupt flag for one clock - else if ((new_set)&&(till_wb <= 0)) - o_int <= 1'b1; - - if ((new_set)&&(till_wb > 0)) - int_set <= 1'b1; - else if (int_now) - int_set <= 1'b0; - // }}} - end - // }}} - - // int_when - // {{{ - always @(posedge i_clk) - if ((new_set)&&(till_wb > 0)&&((till_when[BW-1])||(!int_set))) - int_when <= new_when; - // }}} - - // o_wb_ack - // {{{ - // Acknowledge any wishbone accesses -- everything we did took only - // one clock anyway. - // - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_ack <= 1'b0; - else - o_wb_ack <= i_wb_stb; - // }}} - - assign o_wb_data = r_counter; - assign o_wb_stall = 1'b0; - - // Make verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_wb_sel }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - //////////////////////////////////////////////////////////////////////// - // - // Assumptions about our inputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // One basic WB assumtion - - // Anytime the stb is high, the cycle line must also be high - always @(posedge i_clk) - assume((!i_wb_stb)||(i_wb_cyc)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about our bus outputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // We never stall the bus - always @(*) - assert(!o_wb_stall); - - // We always ack every transaction on the following clock - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_stb))) - begin - assert(o_wb_ack); - end else - assert(!o_wb_ack); - // }}} - /////////////////////////////////////////////////////////////////////// - // - // Assumptions about our internal state and our outputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_reset))) - begin - assert(!o_wb_ack); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_stb)) - &&($past(i_wb_we))) - assert(new_when == $past(i_wb_data)); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_stb)) - &&($past(i_wb_we))) - begin - assert(new_set); - end else - assert(!new_set); - - // - // - // - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_reset))) - assert(!o_int); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_reset))) - begin - assert(!int_set); - assert(!new_set); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(new_set)) - &&(!$past(till_wb[BW-1])) - &&($past(till_wb) > 0)) - assert(int_set); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(i_ce)) - &&($past(r_counter)==$past(int_when))) - begin - assert((o_int)||(!$past(int_set))); - // assert((!int_set)||($past(new_set))); // !!!!! - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!$past(new_set))&&(!$past(int_set))) - assert(!int_set); - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))) - begin - assert(!o_int); - end else if (($past(new_set))&&($past(till_wb) < 0)) - assert(o_int); - - always @(posedge i_clk) - if ((f_past_valid)&& - ((!$past(new_set)) - ||($past(till_wb[BW-1])) - ||($past(till_wb == 0)))) - assert(int_when == $past(int_when)); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipsystem.v b/delete_later/rtl/cpu/zipsystem.v deleted file mode 100644 index 9e8109d..0000000 --- a/delete_later/rtl/cpu/zipsystem.v +++ /dev/null @@ -1,1847 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipsystem.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This portion of the ZIP CPU implements a number of soft -// peripherals to the CPU nearby its CORE. The functionality -// sits on the data bus, and does not include any true external hardware -// peripherals. The peripherals included here include: -// -// Local interrupt controller--for any/all of the interrupts generated -// here. This would include a pin for interrupts generated -// elsewhere, so this interrupt controller could be a master -// handling all interrupts. My interrupt controller would work -// for this purpose. -// -// The ZIP-CPU supports only one interrupt because, as I understand -// modern systems (Linux), they tend to send all interrupts to the -// same interrupt vector anyway. Hence, that's what we do here. -// -// Interval timer(s) (Count down from fixed value, and either stop on -// zero, or issue an interrupt and restart automatically on zero) -// These can be implemented as watchdog timers if desired--the -// only difference is that a watchdog timer's interrupt feeds the -// reset line instead of the processor interrupt line. -// -// Watch-dog timer: this is the same as an interval timer, only it's -// interrupt/time-out line is wired to the reset line instead of -// the interrupt line of the CPU. -// -// Direct Memory Access Controller: This controller allows you to command -// automatic memory moves. Such memory moves will take place -// without the CPU's involvement until they are done. See the -// DMA specification for more information. (Currently contained -// w/in the ZipCPU spec.) -// -// (Potentially an eventual floating point co-processor ...?) -// -// Busses: The ZipSystem implements a series of busses to make this take -// place. These busses are identified by their prefix: -// -// cpu This is the bus as the CPU sees it. Since the CPU controls -// two busses (a local and a global one), it uses _gbl_ to indicate -// the external bus (going through the MMU if necessary) and -// _lcl_ to indicate a peripheral bus seen here. -// -// mmu Sits between the CPU's wishbone interface and the external -// bus. Has no access to peripherals. -// -// sys A local bus implemented here within this space. This is how the -// CPU talks to the ZipSystem peripherals. However, this bus -// can also be accessed from the external debug bus. -// -// io_dbg -// io_wb -// -// dbg This is identical to the io_dbg bus, but separated by a clock -// dc The output of the DMA controller -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -// -// Debug address space: -// {{{ -// 0-15 0x0? Supervisors registers -// 16-31 0x1? User registers -// 32-63 0x2? CPU command register (singular, one register only) -// 64 0x40 Interrupt controller -// 65 0x41 Watchdog -// 66 0x42 Bus watchdog -// 67 0x43 CTRINT -// 68 0x44 Timer A -// 69 0x45 Timer B -// 70 0x46 Timer C -// 71 0x47 Jiffies -// 72 0x48 Master task counter -// 73 0x49 Master task counter -// 74 0x4a Master task counter -// 75 0x4b Master instruction counter -// 76 0x4c User task counter -// 77 0x4d User task counter -// 78 0x4e User task counter -// 79 0x4f User instruction counter -// 80 0x50 DMAC Control/Status register -// 81 0x51 DMAC Length -// 82 0x52 DMAC Read (source) address -// 83 0x53 DMAC Write (destination) address -// -/////// /////// /////// /////// -// -// (MMU ... is not available via debug bus) -// }}} -module zipsystem #( - // {{{ - parameter RESET_ADDRESS=32'h1000_0000, - ADDRESS_WIDTH=32, - parameter BUS_WIDTH=32, // Bus data width - localparam DBG_WIDTH=32, - // CPU options - // {{{ - parameter [0:0] OPT_PIPELINED=1, - parameter [0:0] OPT_EARLY_BRANCHING=OPT_PIPELINED, - // OPT_LGICACHE - // {{{ - parameter OPT_LGICACHE=10, - // }}} - // OPT_LGDCACHE - // {{{ - // Set to zero for no data cache - parameter OPT_LGDCACHE=10, - // }}} - parameter [0:0] START_HALTED=1, - parameter [0:0] OPT_DISTRIBUTED_REGS=1, - parameter EXTERNAL_INTERRUPTS=1, - // OPT_MPY - // {{{ - parameter OPT_MPY = 3, - // }}} - // OPT_DIV - // {{{ - parameter [0:0] OPT_DIV=1, - // }}} - // OPT_SHIFTS - // {{{ - parameter [0:0] OPT_SHIFTS = 1, - // }}} - // OPT_FPU - // {{{ - parameter [0:0] OPT_FPU = 0, - // }}} - parameter [0:0] OPT_CIS=1, - parameter [0:0] OPT_LOCK=1, - parameter [0:0] OPT_USERMODE=1, - parameter [0:0] OPT_DBGPORT=START_HALTED, - parameter [0:0] OPT_TRACE_PORT=1, - parameter [0:0] OPT_PROFILER=0, - parameter [0:0] OPT_LOWPOWER=0, - // }}} - // Local bus options - // {{{ - // OPT_DMA - // {{{ - parameter [0:0] OPT_DMA=1, - parameter DMA_LGMEM = 10, - // }}} - // OPT_ACCOUNTING - // {{{ - parameter [0:0] OPT_ACCOUNTING = 1'b1, - // }}} - // Bus delay options - // {{{ - // While I hate adding delays to any bus access, this next - // delay is required to make timing close in my Basys-3 design. - parameter [0:0] DELAY_DBG_BUS = 1'b1, - // - parameter [0:0] DELAY_EXT_BUS = 1'b0, - // }}} -`ifdef VERILATOR - parameter [0:0] OPT_SIM=1'b1, - parameter [0:0] OPT_CLKGATE = OPT_LOWPOWER, -`else - parameter [0:0] OPT_SIM=1'b0, - parameter [0:0] OPT_CLKGATE = 1'b0, -`endif - // }}} - parameter RESET_DURATION = 0, - // Short-cut names - // {{{ - localparam // Derived parameters - // PHYSICAL_ADDRESS_WIDTH=ADDRESS_WIDTH, - PAW=ADDRESS_WIDTH-$clog2(BUS_WIDTH/8) - // }}} - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Wishbone master interface from the CPU - // {{{ - output wire o_wb_cyc, o_wb_stb, o_wb_we, - output wire [PAW-1:0] o_wb_addr, - output wire [BUS_WIDTH-1:0] o_wb_data, - output wire [BUS_WIDTH/8-1:0] o_wb_sel, - input wire i_wb_stall, i_wb_ack, - input wire [BUS_WIDTH-1:0] i_wb_data, - input wire i_wb_err, - // }}} - // Incoming interrupts - input wire [(EXTERNAL_INTERRUPTS-1):0] i_ext_int, - // Our one outgoing interrupt - output wire o_ext_int, - // Wishbone slave interface for debugging purposes - // {{{ - input wire i_dbg_cyc, i_dbg_stb, i_dbg_we, - input wire [6:0] i_dbg_addr, - input wire [DBG_WIDTH-1:0] i_dbg_data, - input wire [DBG_WIDTH/8-1:0] i_dbg_sel, - output wire o_dbg_stall, - output wire o_dbg_ack, - output wire [DBG_WIDTH-1:0] o_dbg_data, - // }}} - output wire [31:0] o_cpu_debug, - // - output wire o_prof_stb, - output wire [ADDRESS_WIDTH-1:0] o_prof_addr, - output wire [31:0] o_prof_ticks - // }}} - ); - - // Local declarations - // {{{ - // Local parameter declarations - // {{{ - localparam DW=BUS_WIDTH; - // Peripheral addresses - // {{{ - // Verilator lint_off UNUSED - // These values may (or may not) be used, depending on whether or not - // the respective peripheral is included in the CPU. - localparam [31:0] PERIPHBASE = 32'hc0000000; - localparam [7:0] INTCTRL = 8'h0, - WATCHDOG = 8'h1, // Interrupt generates reset signal - BUSWATCHDOG = 8'h2, // Sets IVEC[0] - CTRINT = 8'h3, // Sets IVEC[5] - TIMER_A = 8'h4, // Sets IVEC[4] - TIMER_B = 8'h5, // Sets IVEC[3] - TIMER_C = 8'h6, // Sets IVEC[2] - JIFFIES = 8'h7, // Sets IVEC[1] - // Accounting counter addresses - MSTR_TASK_CTR = 8'h08, - MSTR_MSTL_CTR = 8'h09, - MSTR_PSTL_CTR = 8'h0a, - MSTR_INST_CTR = 8'h0b, - USER_TASK_CTR = 8'h0c, - USER_MSTL_CTR = 8'h0d, - USER_PSTL_CTR = 8'h0e, - USER_INST_CTR = 8'h0f, - // The MMU - MMU_ADDR = 8'h80, - // DMA controller (DMAC) - // Although I have a hole at 5'h2, the DMA controller - // requires four wishbone addresses, therefore we place - // it by itself and expand our address bus width here - // by another bit. - DMAC_ADDR = 8'h10; - // Verilator lint_on UNUSED - // }}} - - // Debug bit allocations - // {{{ - // DBGCTRL - // 5 DBG Catch -- Catch exceptions/fautls w/ debugger - // 4 Clear cache - // 3 RESET_FLAG - // 2 STEP (W=1 steps, and returns to halted) - // 1 HALT(ED) - // 0 HALT - // DBGDATA - // read/writes internal registers - // - localparam HALT_BIT = 0, - STEP_BIT = 2, - RESET_BIT = 3, - CLEAR_CACHE_BIT = 4, - CATCH_BIT = 5; - // }}} - - // Virtual address width (unused) - // {{{ - localparam -`ifdef OPT_MMU - VIRTUAL_ADDRESS_WIDTH=30; -`else - VIRTUAL_ADDRESS_WIDTH=PAW; -`endif - // LGTLBSZ = 6, // Log TLB size - // VAW=VIRTUAL_ADDRESS_WIDTH, - // }}} - - localparam [1:0] DBG_ADDR_CTRL= 2'b00, - DBG_ADDR_CPU = 2'b01, - DBG_ADDR_SYS = 2'b10; - // }}} - - wire [14:0] main_int_vector, alt_int_vector; - wire ctri_int, tma_int, tmb_int, tmc_int, jif_int, dmac_int; - wire mtc_int, moc_int, mpc_int, mic_int, - utc_int, uoc_int, upc_int, uic_int; - wire [DBG_WIDTH-1:0] actr_data; - wire actr_ack, actr_stall; - - wire cpu_clken; - // - // - wire sys_cyc, sys_stb, sys_we; - wire [7:0] sys_addr; - wire [DBG_WIDTH-1:0] sys_data; - wire [PAW-1:0] cpu_addr; - reg [DBG_WIDTH-1:0] sys_idata; - reg sys_ack; - wire sys_stall; - - wire sel_counter, sel_timer, sel_pic, sel_apic, - sel_watchdog, sel_bus_watchdog, sel_dmac, sel_mmus; - - wire dbg_cyc, dbg_stb, dbg_we; - wire [6:0] dbg_addr; - wire [DBG_WIDTH-1:0] dbg_idata; - reg dbg_ack; - wire dbg_stall; - reg [DBG_WIDTH-1:0] dbg_odata; - wire [DBG_WIDTH/8-1:0] dbg_sel; - wire no_dbg_err; - - wire cpu_break, dbg_cmd_write, - dbg_cpu_write, dbg_cpu_read; - wire [DBG_WIDTH-1:0] dbg_cmd_data; - wire [DBG_WIDTH/8-1:0] dbg_cmd_strb; - wire reset_hold, halt_on_fault, dbg_catch; - wire reset_request, release_request, halt_request, - step_request, clear_cache_request; - reg cmd_reset, cmd_halt, cmd_step, cmd_clear_cache, - cmd_write, cmd_read; - reg [4:0] cmd_waddr; - reg [DBG_WIDTH-1:0] cmd_wdata; - wire [2:0] cpu_dbg_cc; - - wire cpu_reset, cpu_halt, - cpu_has_halted; - wire cpu_dbg_stall; - wire [DBG_WIDTH-1:0] cpu_status; - wire cpu_gie; - - wire wdt_stall, wdt_ack, wdt_reset; - wire [DBG_WIDTH-1:0] wdt_data; - reg wdbus_ack; - reg [PAW-1:0] r_wdbus_data; - wire [DBG_WIDTH-1:0] pic_data; - wire [DBG_WIDTH-1:0] wdbus_data; - wire reset_wdbus_timer, wdbus_int; - - wire cpu_op_stall, cpu_pf_stall, cpu_i_count; - - wire dmac_stb, dc_err; - wire [DBG_WIDTH-1:0] dmac_data; - wire dmac_stall, dmac_ack; - wire dc_cyc, dc_stb, dc_we, dc_stall, dc_ack; - wire [PAW-1:0] dc_addr; - wire [BUS_WIDTH-1:0] dc_data; - wire [BUS_WIDTH/8-1:0] dc_sel; - wire cpu_gbl_cyc; - wire [31:0] dmac_int_vec; - - wire ctri_sel, ctri_stall, ctri_ack; - wire [DBG_WIDTH-1:0] ctri_data; - - wire tma_stall, tma_ack; - wire tmb_stall, tmb_ack; - wire tmc_stall, tmc_ack; - wire jif_stall, jif_ack; - wire [DBG_WIDTH-1:0] tma_data; - wire [DBG_WIDTH-1:0] tmb_data; - wire [DBG_WIDTH-1:0] tmc_data; - wire [DBG_WIDTH-1:0] jif_data; - - wire pic_stall, pic_ack; - - wire cpu_gbl_stb, cpu_lcl_cyc, cpu_lcl_stb, - cpu_we; - wire [BUS_WIDTH-1:0] cpu_data; - wire [BUS_WIDTH/8-1:0] cpu_sel, mmu_sel; - wire [BUS_WIDTH-1:0] cpu_idata; - wire cpu_stall; - wire pic_interrupt; - wire cpu_ack, cpu_err; - wire [DBG_WIDTH-1:0] cpu_dbg_data; - - wire ext_stall, ext_ack; - wire mmu_cyc, mmu_stb, mmu_we, mmu_stall, mmu_ack, - mmu_err, mmus_stall, mmus_ack; - wire [PAW-1:0] mmu_addr; - wire [BUS_WIDTH-1:0] mmu_data, mmu_idata; - wire [DBG_WIDTH-1:0] mmus_data; - wire cpu_miss; - - wire mmu_cpu_stall, mmu_cpu_ack; - wire [BUS_WIDTH-1:0] mmu_cpu_idata; - - // The wires associated with cache snooping - wire pf_return_stb, pf_return_we, pf_return_cachable; - wire [19:0] pf_return_v, pf_return_p; - - wire ext_cyc, ext_stb, ext_we, ext_err; - wire [PAW-1:0] ext_addr; - wire [BUS_WIDTH-1:0] ext_odata; - wire [BUS_WIDTH/8-1:0] ext_sel; - wire [BUS_WIDTH-1:0] ext_idata; - - reg [DBG_WIDTH-1:0] tmr_data; - reg [2:0] w_ack_idx, ack_idx; - reg last_sys_stb; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Handle our interrupt vector generation/coordination - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Main interrupt vector - // {{{ - assign main_int_vector[5:0] = { ctri_int, tma_int, tmb_int, tmc_int, - jif_int, dmac_int }; - generate if (EXTERNAL_INTERRUPTS < 9) - begin : TRIM_MAIN_INTS - assign main_int_vector[14:6] = { {(9-EXTERNAL_INTERRUPTS){1'b0}}, - i_ext_int }; - end else begin : NO_TRIM_MAIN_INTS - assign main_int_vector[14:6] = i_ext_int[8:0]; - end endgenerate - // }}} - - // The alternate interrupt vector - // {{{ - generate if (EXTERNAL_INTERRUPTS <= 9 && OPT_ACCOUNTING) - begin : ALT_ACCOUNTING_INTS - assign alt_int_vector = { 7'h00, - mtc_int, moc_int, mpc_int, mic_int, - utc_int, uoc_int, upc_int, uic_int }; - end else if (EXTERNAL_INTERRUPTS <= 9) // && !OPT_ACCOUNTING - begin : ALT_NO_INTS - assign alt_int_vector = { 15'h00 }; - end else if (OPT_ACCOUNTING && EXTERNAL_INTERRUPTS >= 15) - begin : ALT_ACCT_PLUS_INTS - assign alt_int_vector = { i_ext_int[14:8], - mtc_int, moc_int, mpc_int, mic_int, - utc_int, uoc_int, upc_int, uic_int }; - end else if (OPT_ACCOUNTING) - begin : ALT_ACCT_SOME_INTS - - assign alt_int_vector = { {(7-(EXTERNAL_INTERRUPTS-9)){1'b0}}, - i_ext_int[(EXTERNAL_INTERRUPTS-1):9], - mtc_int, moc_int, mpc_int, mic_int, - utc_int, uoc_int, upc_int, uic_int }; - end else if (!OPT_ACCOUNTING && EXTERNAL_INTERRUPTS >= 24) - begin : ALT_NO_ACCOUNTING_INTS - - assign alt_int_vector = { i_ext_int[(EXTERNAL_INTERRUPTS-1):9] }; - end else begin : ALT_TRIM_INTS - assign alt_int_vector = { {(15-(EXTERNAL_INTERRUPTS-9)){1'b0}}, - i_ext_int[(EXTERNAL_INTERRUPTS-1):9] }; - - end endgenerate - // }}} - - // Make Verilator happy - // {{{ - generate if (!OPT_ACCOUNTING) - begin : UNUSED_ACCOUNTING - // Verilator lint_off UNUSED - wire unused_ctrs; - assign unused_ctrs = &{ 1'b0, - moc_int, mpc_int, mic_int, mtc_int, - uoc_int, upc_int, uic_int, utc_int, - cpu_gie, cpu_op_stall, cpu_pf_stall, cpu_i_count }; - // Verilator lint_on UNUSED - end endgenerate - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Delay the debug port by one clock, to meet timing requirements - // {{{ - //////////////////////////////////////////////////////////////////////// - // - generate if (DELAY_DBG_BUS) - begin : DELAY_THE_DEBUG_BUS - // {{{ - wire dbg_err; - assign dbg_err = 1'b0; - busdelay #( - // {{{ - .AW(7),.DW(32) - // }}} - ) wbdelay( - // {{{ - i_clk, i_reset, - i_dbg_cyc, i_dbg_stb, i_dbg_we, i_dbg_addr, i_dbg_data, - 4'hf, - o_dbg_stall, o_dbg_ack, o_dbg_data, no_dbg_err, - dbg_cyc, dbg_stb, dbg_we, dbg_addr, dbg_idata, dbg_sel, - dbg_stall, dbg_ack, dbg_odata, dbg_err - // }}} - ); - // }}} - end else begin : NO_DEBUG_BUS_DELAY - // {{{ - assign dbg_cyc = i_dbg_cyc; - assign dbg_stb = i_dbg_stb; - assign dbg_we = i_dbg_we; - assign dbg_addr = i_dbg_addr; - assign dbg_idata = i_dbg_data; - assign o_dbg_ack = dbg_ack; - assign o_dbg_stall = dbg_stall; - assign o_dbg_data = dbg_odata; - assign dbg_sel = 4'b1111; - assign no_dbg_err = 1'b0; - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus decoding, sel_* - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign sel_pic = (sys_stb)&&(sys_addr == INTCTRL); - assign sel_watchdog = (sys_stb)&&(sys_addr == WATCHDOG); - assign sel_bus_watchdog= (sys_stb)&&(sys_addr == BUSWATCHDOG); - assign sel_apic = (sys_stb)&&(sys_addr == CTRINT); - assign sel_timer = (sys_stb)&&(sys_addr[7:2]==TIMER_A[7:2]); - assign sel_counter = (sys_stb)&&(sys_addr[7:3]==MSTR_TASK_CTR[7:3]); - assign sel_dmac = (sys_stb)&&(sys_addr[7:4] ==DMAC_ADDR[7:4]); - assign sel_mmus = (sys_stb)&&(sys_addr[7]); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The external debug interface - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign dbg_cpu_write = OPT_DBGPORT && (dbg_stb && !dbg_stall && dbg_we) - && (dbg_addr[6:5] == DBG_ADDR_CPU) - && dbg_sel == 4'hf; - assign dbg_cpu_read = (dbg_stb && !dbg_stall && !dbg_we - && dbg_addr[6:5] == DBG_ADDR_CPU); - assign dbg_cmd_write = (dbg_stb)&&(dbg_we) - &&(dbg_addr[6:5] == DBG_ADDR_CTRL); - assign dbg_cmd_data = dbg_idata; - assign dbg_cmd_strb = dbg_sel; - - - assign reset_request = dbg_cmd_write && dbg_cmd_strb[RESET_BIT/8] - && dbg_cmd_data[RESET_BIT]; - assign release_request = dbg_cmd_write && dbg_cmd_strb[HALT_BIT/8] - && !dbg_cmd_data[HALT_BIT]; - assign halt_request = dbg_cmd_write && dbg_cmd_strb[HALT_BIT/8] - && dbg_cmd_data[HALT_BIT]; - assign step_request = dbg_cmd_write && dbg_cmd_strb[STEP_BIT/8] - && dbg_cmd_data[STEP_BIT]; - assign clear_cache_request = dbg_cmd_write - && dbg_cmd_strb[CLEAR_CACHE_BIT/8] - && dbg_cmd_data[CLEAR_CACHE_BIT]; - - // - // reset_hold: Always start us off with an initial reset - // {{{ - generate if (RESET_DURATION > 0) - begin : INITIAL_RESET_HOLD - // {{{ - reg [$clog2(RESET_DURATION)-1:0] reset_counter; - reg r_reset_hold; - - initial reset_counter = RESET_DURATION; - always @(posedge i_clk) - if (i_reset) - reset_counter <= RESET_DURATION; - else if (reset_counter > 0) - reset_counter <= reset_counter - 1; - - initial r_reset_hold = 1; - always @(posedge i_clk) - if (i_reset) - r_reset_hold <= 1; - else - r_reset_hold <= (reset_counter > 1); - - assign reset_hold = r_reset_hold; -`ifdef FORMAL - always @(*) - assert(reset_hold == (reset_counter != 0)); -`endif - // }}} - end else begin : NO_RESET_HOLD - - assign reset_hold = 0; - - end endgenerate - // }}} - - assign halt_on_fault = dbg_catch; - - // cmd_reset - // {{{ - // Always start us off with an initial reset - initial cmd_reset = 1'b1; - always @(posedge i_clk) - if (i_reset) - cmd_reset <= 1'b1; - else if (reset_hold || wdt_reset) - cmd_reset <= 1'b1; - else if (cpu_break && !halt_on_fault) - cmd_reset <= 1'b1; - else - cmd_reset <= reset_request; - // }}} - - // cmd_halt - // {{{ - initial cmd_halt = START_HALTED; - always @(posedge i_clk) - if (i_reset) - cmd_halt <= START_HALTED; - else if (cmd_reset && START_HALTED) - cmd_halt <= START_HALTED; - else begin - // {{{ - // When shall we release from a halt? Only if we have - // come to a full and complete stop. Even then, we only - // release if we aren't being given a command to step the CPU. - // - if (!cmd_write && cpu_has_halted && dbg_cmd_write - && (release_request || step_request)) - cmd_halt <= 1'b0; - - // Reasons to halt - - // 1. Halt on any unhandled CPU exception. The cause of the - // exception must be cured before we can (re)start. - // If the CPU is configured to start immediately on power - // up, we leave it to reset on any exception instead. - if (cpu_break && halt_on_fault) - cmd_halt <= 1'b1; - - // 2. Halt on any user request to halt. (Only valid if the - // STEP bit isn't also set) - if (dbg_cmd_write && halt_request && !step_request) - cmd_halt <= 1'b1; - - // 3. Halt on any user request to write to a CPU register - if (dbg_cpu_write) - cmd_halt <= 1'b1; - - // 4. Halt following any step command - if (cmd_step && !step_request) - cmd_halt <= 1'b1; - - // 5. Halt following any clear cache - if (cmd_clear_cache) - cmd_halt <= 1'b1; - - // 6. Halt on any clear cache bit--independent of any step bit - if (clear_cache_request) - cmd_halt <= 1'b1; - // }}} - end - // }}} - - // cmd_clear_cache - // {{{ - initial cmd_clear_cache = 1'b0; - always @(posedge i_clk) - if (i_reset || cpu_reset) - cmd_clear_cache <= 1'b0; - else if (dbg_cmd_write && clear_cache_request && halt_request) - cmd_clear_cache <= 1'b1; - else if (cmd_halt && !cpu_dbg_stall) - cmd_clear_cache <= 1'b0; - // }}} - - // cmd_step - // {{{ - initial cmd_step = 1'b0; - always @(posedge i_clk) - if (i_reset) - cmd_step <= 1'b0; - else if (cmd_reset || cpu_break - || reset_request - || clear_cache_request || cmd_clear_cache - || halt_request || dbg_cpu_write) - cmd_step <= 1'b0; - else if (!cmd_write && cpu_has_halted && step_request) - cmd_step <= 1'b1; - else // if (cpu_dbg_stall) - cmd_step <= 1'b0; -`ifdef FORMAL - // While STEP is true, we can't halt - always @(*) - if (!i_reset && cmd_step) - assert(!cmd_halt); -`endif - // }}} - - // dbg_catch - // {{{ - generate if (!OPT_DBGPORT) - begin : NO_DBG_CATCH - assign dbg_catch = START_HALTED; - end else begin : GEN_DBG_CATCH - reg r_dbg_catch; - - initial r_dbg_catch = START_HALTED; - always @(posedge i_clk) - if (i_reset) - r_dbg_catch <= START_HALTED; - else if (dbg_cmd_write && dbg_cmd_strb[CATCH_BIT/8]) - r_dbg_catch <= dbg_cmd_data[CATCH_BIT]; - - assign dbg_catch = r_dbg_catch; - end endgenerate - // }}} - - assign cpu_reset = (cmd_reset); - assign cpu_halt = (cmd_halt); - - // cpu_status - // {{{ - // Values: - // 0xxxxx_0000 -> External interrupt lines - // - // 0xffff_f000 -> (Unused / reserved) - // - // 0x0000_0800 -> cpu_break - // 0x0000_0400 -> Interrupt pending - // 0x0000_0200 -> User mode - // 0x0000_0100 -> Sleep (CPU is sleeping) - // - // 0x0000_00c0 -> (Unused/reserved) - // 0x0000_0020 -> dbg_catch - // 0x0000_0010 -> cmd_clear_cache - // - // 0x0000_0008 -> Reset - // 0x0000_0004 -> Step (auto clearing, write only) - // 0x0000_0002 -> Halt (status) - // 0x0000_0001 -> Halt (request) - generate - if (EXTERNAL_INTERRUPTS < 20) - begin : CPU_STATUS_NO_EXTRA_INTERRUPTS - assign cpu_status = { {(20-EXTERNAL_INTERRUPTS){1'b0}}, - i_ext_int, - cpu_break, pic_interrupt, cpu_dbg_cc[1:0], - 2'h0, dbg_catch, 1'b0, - cmd_reset, 1'b0, !cpu_dbg_stall, cmd_halt - }; - end else begin : CPU_STATUS_MAX_INTERRUPTS - assign cpu_status = { i_ext_int[19:0], - cpu_break, pic_interrupt, cpu_dbg_cc[1:0], - 2'h0, dbg_catch, 1'b0, - cmd_reset, 1'b0, !cpu_dbg_stall, cmd_halt - }; - end endgenerate - - // }}} - - assign cpu_gie = cpu_dbg_cc[1]; - - // cmd_write - // {{{ - initial cmd_write = 0; - always @(posedge i_clk) - if (i_reset || cpu_reset) - cmd_write <= 1'b0; - else if (!cmd_write || cpu_has_halted) - cmd_write <= dbg_cpu_write; - // }}} - - // cmd_read - // {{{ - reg cmd_read_ack; - - initial cmd_read = 0; - always @(posedge i_clk) - if (i_reset || !dbg_cyc || !OPT_DBGPORT) - cmd_read <= 1'b0; - else if (dbg_cpu_read) - cmd_read <= 1'b1; - else if (cmd_read) // cmd_read_ack == 1) - cmd_read <= 1'b0; - - generate if (OPT_DISTRIBUTED_REGS) - begin : GEN_CMD_READ_ACK - - initial cmd_read_ack = 0; - always @(posedge i_clk) - if (i_reset || !dbg_cyc || !OPT_DBGPORT) - cmd_read_ack <= 0; - else if (dbg_cpu_read) - cmd_read_ack <= 1; - else if (cmd_read_ack != 0) - cmd_read_ack <= 0; - - end else begin : GEN_FWD_CMDREAD_ACK - always @(*) - cmd_read_ack = cmd_read; - - end endgenerate - // }}} - - // cmd_waddr, cmd_wdata - // {{{ - always @(posedge i_clk) - if ((!cmd_write || cpu_has_halted) && dbg_cpu_write) - begin - cmd_waddr <= dbg_addr[4:0]; - cmd_wdata <= dbg_idata; - end - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The WATCHDOG Timer - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - ziptimer #( - .BW(32),.VW(31),.RELOADABLE(0) - ) u_watchdog ( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), - .i_ce(!cmd_halt), - .i_wb_cyc(sys_cyc), - .i_wb_stb((sys_stb)&&(sel_watchdog)), - .i_wb_we(sys_we), .i_wb_data(sys_data), .i_wb_sel(4'hf), - .o_wb_stall(wdt_stall), - .o_wb_ack(wdt_ack), - .o_wb_data(wdt_data), - .o_int(wdt_reset) - // }}} - ); - - // - // Position two, a second watchdog timer--this time for the wishbone - // bus, in order to tell/find wishbone bus lockups. In its current - // configuration, it cannot be configured and all bus accesses must - // take less than the number written to this register. - // - assign reset_wdbus_timer = (!o_wb_cyc)||(o_wb_stb)||(i_wb_ack); - - wbwatchdog #(14) - u_watchbus( - // {{{ - i_clk,(cpu_reset)||(reset_wdbus_timer), - 14'h2000, wdbus_int - // }}} - ); - - initial r_wdbus_data = 0; - always @(posedge i_clk) - if ((wdbus_int)||(cpu_err)) - r_wdbus_data <= o_wb_addr; - - assign wdbus_data = { {(32-PAW){1'b0}}, r_wdbus_data }; - initial wdbus_ack = 1'b0; - always @(posedge i_clk) - if (i_reset || !sys_cyc) - wdbus_ack <= 1'b0; - else - wdbus_ack <= (sys_stb)&&(sel_bus_watchdog); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Performance counters - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Here's the stuff we'll be counting .... - // - generate if (OPT_ACCOUNTING) - begin : ACCOUNTING_COUNTERS - // {{{ - // Local definitions - // {{{ - // Verilator lint_off UNUSED - wire mtc_stall, mtc_ack; - wire moc_stall, moc_ack; - wire mpc_stall, mpc_ack; - wire mic_stall, mic_ack; - wire utc_stall, utc_ack; - wire uoc_stall, uoc_ack; - wire upc_stall, upc_ack; - wire uic_stall, uic_ack; - // Verilator lint_on UNUSED - wire [DBG_WIDTH-1:0] mtc_data; - wire [DBG_WIDTH-1:0] moc_data; - wire [DBG_WIDTH-1:0] mpc_data; - wire [DBG_WIDTH-1:0] mic_data; - wire [DBG_WIDTH-1:0] utc_data; - wire [DBG_WIDTH-1:0] uoc_data; - wire [DBG_WIDTH-1:0] upc_data; - wire [DBG_WIDTH-1:0] uic_data; - reg [DBG_WIDTH-1:0] r_actr_data; - // }}} - - // Master counters - // {{{ - // The master counters will, in general, not be reset. They'll - // be used for an overall counter. - // - // Master task counter - zipcounter - mtask_ctr( - // {{{ - i_clk, 1'b0, (!cmd_halt), sys_cyc, - (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b000), - sys_we, sys_data, - mtc_stall, mtc_ack, mtc_data, mtc_int - // }}} - ); - - // Master Operand Stall counter - zipcounter - mmstall_ctr( - // {{{ - i_clk,1'b0, (cpu_op_stall), sys_cyc, - (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b001), - sys_we, sys_data, - moc_stall, moc_ack, moc_data, moc_int - // }}} - ); - - // Master PreFetch-Stall counter - zipcounter - mpstall_ctr( - // {{{ - i_clk,1'b0, (cpu_pf_stall), sys_cyc, - (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b010), - sys_we, sys_data, - mpc_stall, mpc_ack, mpc_data, mpc_int - // }}} - ); - - // Master Instruction counter - zipcounter - mins_ctr( - // {{{ - i_clk,1'b0, (cpu_i_count), sys_cyc, - (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b011), - sys_we, sys_data, - mic_stall, mic_ack, mic_data, mic_int - // }}} - ); - // }}} - // User counters - // {{{ - // The user counters are different from those of the master. - // They will be reset any time a task is given control of the - // CPU. - // - // User task counter - zipcounter - utask_ctr( - // {{{ - i_clk,1'b0, (!cmd_halt)&&(cpu_gie), sys_cyc, - (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b100), - sys_we, sys_data, - utc_stall, utc_ack, utc_data, utc_int - // }}} - ); - - // User Op-Stall counter - zipcounter - umstall_ctr( - // {{{ - i_clk,1'b0, (cpu_op_stall)&&(cpu_gie), sys_cyc, - (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b101), - sys_we, sys_data, - uoc_stall, uoc_ack, uoc_data, uoc_int - // }}} - ); - - // User PreFetch-Stall counter - zipcounter - upstall_ctr( - // {{{ - i_clk,1'b0, (cpu_pf_stall)&&(cpu_gie), sys_cyc, - (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b110), - sys_we, sys_data, - upc_stall, upc_ack, upc_data, upc_int - // }}} - ); - - // User instruction counter - zipcounter - uins_ctr( - // {{{ - i_clk,1'b0, (cpu_i_count)&&(cpu_gie), sys_cyc, - (sys_stb)&&(sel_counter)&&(sys_addr[2:0] == 3'b111), - sys_we, sys_data, - uic_stall, uic_ack, uic_data, uic_int - // }}} - ); - // }}} - - // A little bit of pre-cleanup (actr = accounting counters) - assign actr_ack = sel_counter; - assign actr_stall = 1'b0; - - // actr_data - // {{{ - always @(*) - begin - case(sys_addr[2:0]) - 3'h0: r_actr_data = mtc_data; - 3'h1: r_actr_data = moc_data; - 3'h2: r_actr_data = mpc_data; - 3'h3: r_actr_data = mic_data; - 3'h4: r_actr_data = utc_data; - 3'h5: r_actr_data = uoc_data; - 3'h6: r_actr_data = upc_data; - 3'h7: r_actr_data = uic_data; - endcase - end - - assign actr_data = r_actr_data; - // }}} - // }}} - end else begin : NO_ACCOUNTING_COUNTERS - // {{{ - - assign actr_stall = 1'b0; - assign actr_data = 32'h0000; - - assign mtc_int = 1'b0; - assign moc_int = 1'b0; - assign mpc_int = 1'b0; - assign mic_int = 1'b0; - assign utc_int = 1'b0; - assign uoc_int = 1'b0; - assign upc_int = 1'b0; - assign uic_int = 1'b0; - - assign actr_ack = sel_counter; - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The DMA Controller - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign dmac_int_vec = { 1'b0, alt_int_vector, 1'b0, - main_int_vector[14:1], 1'b0 }; - assign dmac_stb = (sys_stb)&&(sel_dmac); - - generate if (OPT_DMA) - begin : DMA - // {{{ - zipdma #( - // {{{ - .ADDRESS_WIDTH(ADDRESS_WIDTH), .LGMEMLEN(DMA_LGMEM), - .OPT_REGISTER_RAM(!OPT_DISTRIBUTED_REGS), - .BUS_WIDTH(DW), .OPT_LITTLE_ENDIAN(1'b0) - // }}} - ) dma_controller( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), - .i_swb_cyc(sys_cyc), .i_swb_stb(dmac_stb), - .i_swb_we(sys_we), .i_swb_addr(sys_addr[1:0]), - .i_swb_data(sys_data), .i_swb_sel(4'hf), - .o_swb_stall(dmac_stall), .o_swb_ack(dmac_ack), - .o_swb_data(dmac_data), - // Need the outgoing DMAC wishbone bus - .o_mwb_cyc(dc_cyc), .o_mwb_stb(dc_stb), - .o_mwb_we(dc_we), .o_mwb_addr(dc_addr), - .o_mwb_data(dc_data), .o_mwb_sel(dc_sel), - .i_mwb_stall(dc_stall), - .i_mwb_ack(dc_ack), .i_mwb_data(ext_idata), - .i_mwb_err(dc_err), - // External device interrupts - .i_dev_ints(dmac_int_vec), - // DMAC interrupt, for upon completion - .o_interrupt(dmac_int) - // }}} - ); - // }}} - end else begin : NO_DMA - // {{{ - reg r_dmac_ack; - - initial r_dmac_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_dmac_ack <= 1'b0; - else - r_dmac_ack <= (sys_cyc)&&(dmac_stb); - assign dmac_ack = r_dmac_ack; - assign dmac_data = 32'h000; - assign dmac_stall = 1'b0; - - assign dc_cyc = 1'b0; - assign dc_stb = 1'b0; - assign dc_we = 1'b0; - assign dc_addr = { (PAW) {1'b0} }; - assign dc_data = 32'h00; - assign dc_sel = 4'h0; - - assign dmac_int = 1'b0; - - // Make Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused_dmac; - assign unused_dmac = &{ 1'b0, dc_err, dc_ack, - dc_stall, dmac_int_vec }; - // Verilator lint_on UNUSED - // }}} - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The alternate interrupt controller - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign ctri_sel = (sys_stb)&&(sel_apic); - generate if (OPT_ACCOUNTING) - begin : PIC_WITH_ACCOUNTING - // - // Interrupt controller - // - if (EXTERNAL_INTERRUPTS <= 9) - begin : ALT_PIC - icontrol #(8) - ctri( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), - .i_wb_cyc(sys_cyc), .i_wb_stb(ctri_sel), - .i_wb_we(sys_we), .i_wb_data(sys_data), .i_wb_sel(4'hf), - .o_wb_stall(ctri_stall), .o_wb_ack(ctri_ack), - .o_wb_data(ctri_data), - .i_brd_ints(alt_int_vector[7:0]), .o_interrupt(ctri_int) - // }}} - ); - end else begin : ALT_PIC - icontrol #(8+(EXTERNAL_INTERRUPTS-9)) - ctri( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), - .i_wb_cyc(sys_cyc), .i_wb_stb(ctri_sel), - .i_wb_we(sys_we), .i_wb_data(sys_data), - .i_wb_sel(4'hf), - .o_wb_stall(ctri_stall), - .o_wb_ack(ctri_ack), - .o_wb_data(ctri_data), - .i_brd_ints(alt_int_vector[(EXTERNAL_INTERRUPTS-2):0]), - .o_interrupt(ctri_int) - // }}} - ); - end - end else begin : PIC_WITHOUT_ACCOUNTING - - if (EXTERNAL_INTERRUPTS <= 9) - begin : ALT_PIC - assign ctri_stall = 1'b0; - assign ctri_data = 32'h0000; - assign ctri_int = 1'b0; - end else begin : ALT_PIC - icontrol #(EXTERNAL_INTERRUPTS-9) - ctri( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), - .i_wb_cyc(sys_cyc), .i_wb_stb(ctri_sel), - .i_wb_we(sys_we), .i_wb_data(sys_data), - .i_wb_sel(4'hf), - .o_wb_stall(ctri_stall), - .o_wb_ack(ctri_ack), - .o_wb_data(ctri_data), - .i_brd_ints(alt_int_vector[(EXTERNAL_INTERRUPTS-10):0]), - .o_interrupt(ctri_int) - // }}} - ); - end - - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Timers - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // Timer A - // - ziptimer u_timer_a( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), .i_ce(!cmd_halt), - .i_wb_cyc(sys_cyc), - .i_wb_stb((sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b00)), - .i_wb_we(sys_we), .i_wb_data(sys_data), .i_wb_sel(4'hf), - .o_wb_stall(tma_stall), .o_wb_ack(tma_ack), - .o_wb_data(tma_data), - .o_int(tma_int) - // }}} - ); - - // - // Timer B - // - ziptimer u_timer_b( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), .i_ce(!cmd_halt), - .i_wb_cyc(sys_cyc), - .i_wb_stb((sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b01)), - .i_wb_we(sys_we), .i_wb_data(sys_data), .i_wb_sel(4'hf), - .o_wb_stall(tmb_stall), .o_wb_ack(tmb_ack), - .o_wb_data(tmb_data), - .o_int(tmb_int) - // }}} - ); - - // - // Timer C - // - ziptimer u_timer_c( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), .i_ce(!cmd_halt), - .i_wb_cyc(sys_cyc), - .i_wb_stb((sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b10)), - .i_wb_we(sys_we), .i_wb_data(sys_data), .i_wb_sel(4'hf), - .o_wb_stall(tmc_stall), .o_wb_ack(tmc_ack), - .o_wb_data(tmc_data), - .o_int(tmc_int) - // }}} - ); - - // - // JIFFIES - // - zipjiffies u_jiffies( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), .i_ce(!cmd_halt), - .i_wb_cyc(sys_cyc), - .i_wb_stb((sys_stb)&&(sel_timer)&&(sys_addr[1:0] == 2'b11)), - .i_wb_we(sys_we), .i_wb_data(sys_data), .i_wb_sel(4'hf), - .o_wb_stall(jif_stall), .o_wb_ack(jif_ack), - .o_wb_data(jif_data), - .o_int(jif_int) - // }}} - ); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The main (programmable) interrupt controller peripheral - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (EXTERNAL_INTERRUPTS < 9) - begin : MAIN_PIC - icontrol #(6+EXTERNAL_INTERRUPTS) - pic( - // {{{ - i_clk, cpu_reset, - sys_cyc, (sys_cyc)&&(sys_stb)&&(sel_pic),sys_we, - sys_data, 4'hf, pic_stall, pic_ack, pic_data, - main_int_vector[(6+EXTERNAL_INTERRUPTS-1):0], - pic_interrupt - // }}} - ); - - end else begin : MAIN_PIC - icontrol #(15) - pic( - // {{{ - i_clk, cpu_reset, - sys_cyc, (sys_cyc)&&(sys_stb)&&(sel_pic),sys_we, - sys_data, 4'hf, pic_stall, pic_ack, pic_data, - main_int_vector[14:0], pic_interrupt - // }}} - ); - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The CPU itself - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign cpu_clken = cmd_write || cmd_read || (dbg_stb && dbg_addr[6] == DBG_ADDR_CPU[1]); -`ifdef FORMAL - // {{{ - (* anyseq *) reg f_cpu_halted, f_cpu_data, f_cpu_stall, - f_cpu_break; - (* anyseq *) reg [1:0] f_cpu_dbg_cc; - (* anyseq *) reg [31:0] f_cpu_dbg_data; - wire cpu_dbg_we; - - assign cpu_dbg_we = ((dbg_stb)&&(dbg_we) - &&(dbg_addr[6:5] == DBG_ADDR_CPU)); - - assign cpu_dbg_stall = f_cpu_stall && !f_cpu_halted; - assign cpu_break = f_cpu_break; - assign cpu_dbg_cc = f_cpu_dbg_cc; - assign cpu_dbg_data = f_cpu_dbg_data; - assign cpu_has_halted= f_cpu_halted; - - fdebug #( - // {{{ - .OPT_START_HALTED(START_HALTED), - .OPT_DISTRIBUTED_RAM(OPT_DISTRIBUTED_REGS) - // }}} - ) fdbg ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - .i_cpu_reset(cpu_reset), - .i_halt(cpu_halt), - .i_halted(f_cpu_halted), - .i_clear_cache(cmd_clear_cache), - .i_dbg_we(cmd_write), - .i_dbg_reg(cmd_waddr), - .i_dbg_data(cmd_wdata), - .i_dbg_stall(cpu_dbg_stall), - .i_dbg_break(cpu_break), - .i_dbg_cc(cpu_dbg_cc) - // }}} - ); - - always @(*) - if (f_cpu_halted) - assume(!cpu_gbl_cyc && !cpu_gbl_stb); - // }}} -`else - zipwb #( - // {{{ - .RESET_ADDRESS(RESET_ADDRESS), - .ADDRESS_WIDTH(VIRTUAL_ADDRESS_WIDTH), - .BUS_WIDTH(BUS_WIDTH), - .OPT_PIPELINED(OPT_PIPELINED), - .OPT_EARLY_BRANCHING(OPT_EARLY_BRANCHING), - .OPT_LGICACHE(OPT_LGICACHE), - .OPT_LGDCACHE(OPT_LGDCACHE), - .OPT_MPY(OPT_MPY), - .OPT_DIV(OPT_DIV), - .OPT_SHIFTS(OPT_SHIFTS), - .IMPLEMENT_FPU(OPT_FPU), - .OPT_CIS(OPT_CIS), - .OPT_LOCK(OPT_LOCK), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_START_HALTED(START_HALTED), - .OPT_SIM(OPT_SIM), - .OPT_DBGPORT(OPT_DBGPORT), - .OPT_TRACE_PORT(OPT_TRACE_PORT), - .OPT_PROFILER(OPT_PROFILER), - .OPT_CLKGATE(OPT_CLKGATE), - .OPT_DISTRIBUTED_REGS(OPT_DISTRIBUTED_REGS), - .OPT_USERMODE(OPT_USERMODE), - .WITH_LOCAL_BUS(1'b1) - // }}} - ) thecpu( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), - .i_interrupt(pic_interrupt), - .i_cpu_clken(cpu_clken), - // Debug interface - // {{{ - .i_halt(cpu_halt), .i_clear_cache(cmd_clear_cache), - .i_dbg_wreg(cmd_waddr), .i_dbg_we(cmd_write), - .i_dbg_data(cmd_wdata), - .i_dbg_rreg(dbg_addr[4:0]), - .o_dbg_stall(cpu_dbg_stall), - .o_halted(cpu_has_halted), - .o_dbg_reg(cpu_dbg_data), - .o_dbg_cc(cpu_dbg_cc), - .o_break(cpu_break), - // }}} - // Wishbone bus interface - // {{{ - .o_wb_gbl_cyc(cpu_gbl_cyc), .o_wb_gbl_stb(cpu_gbl_stb), - .o_wb_lcl_cyc(cpu_lcl_cyc), - .o_wb_lcl_stb(cpu_lcl_stb), - .o_wb_we(cpu_we), .o_wb_addr(cpu_addr), - .o_wb_data(cpu_data), .o_wb_sel(cpu_sel), - // Return values from the Wishbone bus - .i_wb_stall(cpu_stall), .i_wb_ack(cpu_ack), - .i_wb_data(cpu_idata), .i_wb_err(cpu_err), - // }}} - .o_op_stall(cpu_op_stall), .o_pf_stall(cpu_pf_stall), - .o_i_count(cpu_i_count), - .o_debug(o_cpu_debug), - // - .o_prof_stb(o_prof_stb), - .o_prof_addr(o_prof_addr), - .o_prof_ticks(o_prof_ticks) - // }}} - ); -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The (unused) MMU - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // The mmu_cpu_ lines are the return bus lines from the MMU. They - // are separate from the cpu_'s lines simply because either the sys_ - // (local) bus or the mmu_cpu_ (global) bus might return a response to - // the CPU, and the responses haven't been merged back together again - // yet. - -`ifdef OPT_MMU - // Ok ... here's the MMU - zipmmu #( - // {{{ - .LGTBL(LGTLBSZ), - .ADDRESS_WIDTH(PHYSICAL_ADDRESS_WIDTH) - // }}} - ) themmu( - // {{{ - i_clk, cpu_reset, - // Slave interface - (sys_stb)&&(sel_mmus), - sys_we, sys_addr[7:0], sys_data, - mmus_stall, mmus_ack, mmus_data, - // CPU global bus master lines - cpu_gbl_cyc, cpu_gbl_stb, cpu_we, cpu_addr, - cpu_data, cpu_sel, - // MMU bus master outgoing lines - mmu_cyc, mmu_stb, mmu_we, mmu_addr, mmu_data, mmu_sel, - // .... and the return from the slave(s) - mmu_stall, mmu_ack, mmu_err, mmu_idata, - // CPU gobal bus master return lines - mmu_cpu_stall, mmu_cpu_ack, cpu_err, cpu_miss, mmu_cpu_idata, - pf_return_stb, pf_return_we, pf_return_p, pf_return_v, - pf_return_cachable - // }}} - ); - -`else - reg r_mmus_ack; - - assign mmu_cyc = cpu_gbl_cyc; - assign mmu_stb = cpu_gbl_stb; - assign mmu_we = cpu_we; - assign mmu_addr = cpu_addr; - assign mmu_data = cpu_data; - assign mmu_sel = cpu_sel; - assign cpu_miss = 1'b0; - assign cpu_err = (mmu_err)&&(cpu_gbl_cyc); - assign mmu_cpu_idata = mmu_idata; - assign mmu_cpu_stall = mmu_stall; - assign mmu_cpu_ack = mmu_ack; - - initial r_mmus_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_mmus_ack <= 1'b0; - else - r_mmus_ack <= (sys_stb)&&(sys_addr[7]); - - assign mmus_ack = r_mmus_ack; - assign mmus_stall = 1'b0; - assign mmus_data = 32'h0; - - assign pf_return_stb = 0; - assign pf_return_v = 0; - assign pf_return_p = 0; - assign pf_return_we = 0; - assign pf_return_cachable = 0; -`endif - // - // Responses from the MMU still need to be merged/muxed back together - // with the responses from the local bus - assign cpu_ack = ((cpu_lcl_cyc)&&(sys_ack)) - ||((cpu_gbl_cyc)&&(mmu_cpu_ack)); - assign cpu_stall = ((cpu_lcl_cyc)&&(sys_stall)) - ||((cpu_gbl_cyc)&&(mmu_cpu_stall)); - assign cpu_idata = (cpu_gbl_cyc)?mmu_cpu_idata - : { {(BUS_WIDTH-DBG_WIDTH){1'b0}}, sys_idata }; - - // The following lines (will be/) are used to allow the prefetch to - // snoop on any external interaction. Until this capability is - // integrated into the CPU, they are unused. Here we tell Verilator - // not to be surprised that these lines are unused: - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The internal sys bus - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Now, arbitrate the bus ... first for the local peripherals - // For the debugger to have access to the local system bus, the - // following must be true: - // (dbg_cyc) The debugger must request the bus - // (!cpu_lcl_cyc) The CPU cannot be using it (CPU gets priority) - // (dbg_addr) The debugger must be requesting its data - // register, not just the control register - // and one of two other things. Either - // ((cpu_halt)&&(!cpu_dbg_stall)) the CPU is completely halted, - // or - // (dbg_addr[6:5]==2'b01) we are trying to read a CPU register - // while in motion. Let the user beware that, - // by not waiting for the CPU to fully halt, - // his results may not be what he expects. - // - assign sys_cyc = (cpu_lcl_cyc)||(dbg_cyc); - assign sys_stb = (cpu_lcl_cyc) - ? (cpu_lcl_stb) - : ((dbg_stb)&&(dbg_addr[6:5]==DBG_ADDR_SYS)); - - assign sys_we = (cpu_lcl_cyc) ? cpu_we : dbg_we; - assign sys_addr= (cpu_lcl_cyc) ? cpu_addr[7:0] : { 3'h0, dbg_addr[4:0]}; - assign sys_data= (cpu_lcl_cyc) ? cpu_data[DBG_WIDTH-1:0] : dbg_idata; - - // tmr_data - // {{{ - always @(*) - begin - case(sys_addr[1:0]) - 2'b00: tmr_data = tma_data; - 2'b01: tmr_data = tmb_data; - 2'b10: tmr_data = tmc_data; - 2'b11: tmr_data = jif_data; - endcase - - // tmr_ack == sys_stb && sel_timer - end - // }}} - - // last_sys_stb - // {{{ - initial last_sys_stb = 0; - always @(posedge i_clk) - if (i_reset) - last_sys_stb <= 0; - else - last_sys_stb <= sys_stb; - // }}} - - // sys_ack, sys_idata - // {{{ - always @(posedge i_clk) - begin - case(ack_idx) - 3'h0: { sys_ack, sys_idata } <= { mmus_ack, mmus_data }; - 3'h1: { sys_ack, sys_idata } <= { last_sys_stb, wdt_data }; - 3'h2: { sys_ack, sys_idata } <= { last_sys_stb, wdbus_data }; - 3'h3: { sys_ack, sys_idata } <= { last_sys_stb, ctri_data };// A-PIC - 3'h4: { sys_ack, sys_idata } <= { last_sys_stb, tmr_data }; - 3'h5: { sys_ack, sys_idata } <= { last_sys_stb, actr_data };//countr - 3'h6: { sys_ack, sys_idata } <= { dmac_ack, dmac_data }; - 3'h7: { sys_ack, sys_idata } <= { last_sys_stb, pic_data }; - endcase - - if (i_reset || !sys_cyc) - sys_ack <= 1'b0; - end - // }}} - - // w_ack_idx - // {{{ - always @(*) - begin - w_ack_idx = 0; - if (sel_mmus) w_ack_idx = w_ack_idx | 3'h0; - if (sel_watchdog) w_ack_idx = w_ack_idx | 3'h1; - if (sel_bus_watchdog) w_ack_idx = w_ack_idx | 3'h2; - if (sel_apic) w_ack_idx = w_ack_idx | 3'h3; - if (sel_timer) w_ack_idx = w_ack_idx | 3'h4; - if (sel_counter) w_ack_idx = w_ack_idx | 3'h5; - if (sel_dmac) w_ack_idx = w_ack_idx | 3'h6; - if (sel_pic) w_ack_idx = w_ack_idx | 3'h7; - end - // }}} - - // ack_idx - // {{{ - always @(posedge i_clk) - if (sys_stb) - ack_idx <= w_ack_idx; - // }}} - assign sys_stall = 1'b0; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Return debug response values - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg dbg_pre_ack; - reg [1:0] dbg_pre_addr; - reg [DBG_WIDTH-1:0] dbg_cpu_status; - - always @(posedge i_clk) - dbg_pre_addr <= dbg_addr[6:5]; - - always @(posedge i_clk) - dbg_cpu_status <= cpu_status; - - initial dbg_pre_ack = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_dbg_cyc) - dbg_pre_ack <= 1'b0; - else - dbg_pre_ack <= dbg_stb && !dbg_stall && !dbg_cpu_read; - - // A return from one of three busses: - // CMD giving command instructions to the CPU (step, halt, etc) - // CPU-DBG-DATA internal register responses from within the CPU - // sys Responses from the front-side bus here in the ZipSystem - // assign dbg_odata = (!dbg_addr) ? cpu_status - // :((!cmd_addr[5])?cpu_dbg_data : sys_idata); - initial dbg_ack = 1'b0; - always @(posedge i_clk) - if (i_reset || !dbg_cyc) - dbg_ack <= 1'b0; - else - dbg_ack <= dbg_pre_ack || cmd_read_ack; - - always @(posedge i_clk) - if (!OPT_LOWPOWER || (dbg_cyc && (dbg_pre_ack || cmd_read))) - casez(dbg_pre_addr) - DBG_ADDR_CPU: dbg_odata <= cpu_dbg_data; - DBG_ADDR_CTRL: dbg_odata <= dbg_cpu_status; - // DBG_ADDR_SYS: - default: dbg_odata <= sys_idata; - endcase - - assign dbg_stall = cmd_read || (cmd_write && cpu_dbg_stall - && dbg_addr[6:5] == DBG_ADDR_CPU) - ||(dbg_addr[6]==DBG_ADDR_SYS[1] && cpu_lcl_cyc); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Arbitrate between CPU and DMA - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Now for the external wishbone bus - // Need to arbitrate between the flash cache and the CPU - // The way this works, though, the CPU will stall once the flash - // cache gets access to the bus--the CPU will be stuck until the - // flash cache is finished with the bus. - wbpriarbiter #( - // {{{ - .DW(BUS_WIDTH), - .AW(PAW) - // }}} - ) dmacvcpu( - // {{{ - i_clk, - mmu_cyc, mmu_stb, mmu_we, mmu_addr, mmu_data, mmu_sel, - mmu_stall, mmu_ack, mmu_err, - dc_cyc, dc_stb, dc_we, dc_addr, dc_data, dc_sel, - dc_stall, dc_ack, dc_err, - ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel, - ext_stall, ext_ack, ext_err - // }}} - ); - assign mmu_idata = ext_idata; -/* - assign ext_cyc = mmu_cyc; - assign ext_stb = mmu_stb; - assign ext_we = mmu_we; - assign ext_odata= mmu_data; - assign ext_addr = mmu_addr; - assign ext_sel = mmu_sel; - assign mmu_ack = ext_ack; - assign mmu_stall= ext_stall; - assign mmu_err = ext_err; -*/ - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Delay access to the external bus by one clock (if necessary) - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (DELAY_EXT_BUS) - begin : DELAY_EXTERNAL_BUS - // {{{ - busdelay #( - // {{{ - .AW(PAW), - .DW(BUS_WIDTH), - .DELAY_STALL(0) - // }}} - ) extbus( - // {{{ - i_clk, i_reset, - ext_cyc, ext_stb, ext_we, ext_addr, ext_odata, ext_sel, - ext_stall, ext_ack, ext_idata, ext_err, - o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, - o_wb_sel, - i_wb_stall, i_wb_ack, i_wb_data, (i_wb_err)||(wdbus_int) - // }}} - ); - // }}} - end else begin : NO_EXTERNAL_BUS_DELAY - // {{{ - assign o_wb_cyc = ext_cyc; - assign o_wb_stb = ext_stb; - assign o_wb_we = ext_we; - assign o_wb_addr = ext_addr; - assign o_wb_data = ext_odata; - assign o_wb_sel = ext_sel; - assign ext_stall = i_wb_stall; - assign ext_ack = i_wb_ack; - assign ext_idata = i_wb_data; - assign ext_err = (i_wb_err)||(wdbus_int); - // }}} - end endgenerate - // }}} - - assign o_ext_int = (cmd_halt) && (!cpu_stall); - - //////////////////////////////////////////////////////////////////////// - // - // Simulation only accesses, to make the simulation display work - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} - - // Make Verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, - cpu_dbg_cc[2], - pic_ack, pic_stall, cpu_clken, - tma_ack, tma_stall, tmb_ack, tmb_stall, tmc_ack, tmc_stall, - jif_ack, jif_stall, no_dbg_err, dbg_sel, - sel_mmus, ctri_ack, ctri_stall, mmus_stall, dmac_stall, - wdt_ack, wdt_stall, actr_ack, actr_stall, - wdbus_ack, i_dbg_sel, - // moc_ack, mtc_ack, mic_ack, mpc_ack, - // uoc_ack, utc_ack, uic_ack, upc_ack, - // moc_stall, mtc_stall, mic_stall, mpc_stall, - // uoc_stall, utc_stall, uic_stall, upc_stall, - // Unused MMU pins - pf_return_stb, pf_return_we, pf_return_p, pf_return_v, - pf_return_cachable, cpu_miss }; - // verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - wire [2:0] fdbg_nreqs, fdbg_nacks, fdbg_outstanding; - - fwb_slave #( - // {{{ - .AW(7), .DW(32), .F_LGDEPTH(3) - // }}} - ) dbg ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(i_dbg_cyc), .i_wb_stb(i_dbg_stb), - .i_wb_we(i_dbg_we), .i_wb_addr(i_dbg_addr), - .i_wb_data(i_dbg_data), .i_wb_sel(i_dbg_sel), - .i_wb_ack(o_dbg_ack), .i_wb_stall(o_dbg_stall), - .i_wb_idata(o_dbg_data), .i_wb_err(1'b0), - .f_nreqs(fdbg_nreqs), .f_nacks(fdbg_nacks), - .f_outstanding(fdbg_outstanding) - // }}} - ); - - fwb_slave #( - // {{{ - .AW(32), .DW(32), .F_LGDEPTH(3) - // }}} - ) fwb_cpu ( - // {{{ - .i_clk(i_clk), .i_reset(cpu_reset), - // - .i_wb_cyc(i_dbg_cyc), .i_wb_stb(i_dbg_stb), - .i_wb_we(i_dbg_we), .i_wb_addr(i_dbg_addr), - .i_wb_data(i_dbg_data), .i_wb_sel(i_dbg_sel), - .i_wb_ack(o_dbg_ack), .i_wb_stall(o_dbg_stall), - .i_wb_idata(o_dbg_data), .i_wb_err(1'b0), - .f_nreqs(fdbg_nreqs), .f_nacks(fdbg_nacks), - .f_outstanding(fdbg_outstanding) - // }}} - ); - - fwb_master #( - ) fsys ( - .i_clk(i_clk), .i_reset(i_reset), - ); - -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/ziptimer.v b/delete_later/rtl/cpu/ziptimer.v deleted file mode 100644 index 63410b6..0000000 --- a/delete_later/rtl/cpu/ziptimer.v +++ /dev/null @@ -1,357 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: ziptimer.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A lighter weight implementation of the Zip Timer. -// -// Interface: -// Two options: -// 1. One combined register for both control and value, and ... -// The reload value is set any time the timer data value is "set". -// Reading the register returns the timer value. Controls are -// set so that writing a value to the timer automatically starts -// it counting down. -// 2. Two registers, one for control one for value. -// The control register would have the reload value in it. -// On the clock when the interface is set to zero the interrupt is set. -// Hence setting the timer to zero will disable the timer without -// setting any interrupts. Thus setting it to five will count -// 5 clocks: 5, 4, 3, 2, 1, Interrupt. -// -// -// Control bits: -// (Start_n/Stop. This bit has been dropped. Writing to this -// timer any value but zero starts it. Writing a zero -// clears and stops it.) -// AutoReload. If set, then on reset the timer automatically -// loads the last set value and starts over. This is -// useful for distinguishing between a one-time interrupt -// timer, and a repetitive interval timer. -// (INTEN. Interrupt enable--reaching zero always creates an -// interrupt, so this control bit isn't needed. The -// interrupt controller can be used to mask the interrupt.) -// (COUNT-DOWN/UP: This timer is *only* a count-down timer. -// There is no means of setting it to count up.) -// WatchDog -// This timer can be implemented as a watchdog timer simply by -// connecting the interrupt line to the reset line of the CPU. -// When the timer then expires, it will trigger a CPU reset. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module ziptimer #( - // {{{ - parameter BW = 32, VW = (BW-1), - parameter [0:0] RELOADABLE = 1 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, i_ce, - // Wishbone inputs - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [BW-1:0] i_wb_data, - input wire [BW/8-1:0] i_wb_sel, - // Wishbone outputs - output wire o_wb_stall, - output reg o_wb_ack, - output wire [BW-1:0] o_wb_data, - // Interrupt line - output reg o_int - // }}} - ); - - // Local declarations - // {{{ - reg r_running; - reg r_zero = 1'b1; - reg [(VW-1):0] r_value; - - wire wb_write; - - wire auto_reload; - wire [(VW-1):0] interval_count; - // }}} - - assign wb_write = ((i_wb_stb)&&(i_wb_we)); - - // r_running - // {{{ - initial r_running = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_running <= 1'b0; - else if (wb_write) - r_running <= (|i_wb_data[(VW-1):0]); - else if ((r_zero)&&(!auto_reload)) - r_running <= 1'b0; - // }}} - - // r_auto_reload, r_interval_count - // {{{ - generate - if (RELOADABLE != 0) - begin : GEN_RELOAD - // {{{ - reg r_auto_reload; - reg [(VW-1):0] r_interval_count; - - // r_auto_reload - // {{{ - initial r_auto_reload = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_auto_reload <= 1'b0; - else if (wb_write) - r_auto_reload <= (i_wb_data[(BW-1)]) - &&(|i_wb_data[(VW-1):0]); - // }}} - - assign auto_reload = r_auto_reload; - - // r_interval_count - // {{{ - // If setting auto-reload mode, and the value to other - // than zero, set the auto-reload value - always @(posedge i_clk) - if (i_reset) - r_interval_count <= 0; - else if (wb_write) - r_interval_count <= i_wb_data[(VW-1):0]; - // }}} - - assign interval_count = r_interval_count; - // }}} - end else begin : NO_AUTO_RELOAD - // {{{ - assign auto_reload = 1'b0; - assign interval_count = 0; - // }}} - end endgenerate - // }}} - - // r_value - // {{{ - initial r_value = 0; - always @(posedge i_clk) - if (i_reset) - r_value <= 0; - else if (wb_write) - r_value <= i_wb_data[(VW-1):0]; - else if ((i_ce)&&(r_running)) - begin - if (!r_zero) - r_value <= r_value - 1'b1; - else if (auto_reload) - r_value <= interval_count; - end - // }}} - - // r_zero - // {{{ - always @(posedge i_clk) - if (i_reset) - r_zero <= 1'b1; - else if (wb_write) - r_zero <= (i_wb_data[(VW-1):0] == 0); - else if ((r_running)&&(i_ce)) - begin - if (r_value == { {(VW-1){1'b0}}, 1'b1 }) - r_zero <= 1'b1; - else if ((r_zero)&&(auto_reload)) - r_zero <= 1'b0; - end - // }}} - - // o_int - // {{{ - // Set the interrupt on our last tick, as we transition from one to - // zero. - initial o_int = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(wb_write)||(!i_ce)) - o_int <= 1'b0; - else // if (i_ce) - o_int <= (r_value == { {(VW-1){1'b0}}, 1'b1 }); - // }}} - - // o_wb_ack - // {{{ - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - o_wb_ack <= (!i_reset)&&(i_wb_stb); - // }}} - assign o_wb_stall = 1'b0; - - // o_wb_data - // {{{ - generate if (VW < BW-1) - begin : GEN_TRIM - assign o_wb_data = { auto_reload, {(BW-1-VW){1'b0}}, r_value }; - end else begin : NO_TRIM - assign o_wb_data = { auto_reload, r_value }; - end endgenerate - // }}} - - // Make verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_wb_data, i_wb_sel }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - initial assume(i_reset); - always @(*) - if (!f_past_valid) - assume(i_reset); - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))) - begin - assert(r_value == 0); - assert(r_running == 0); - assert(auto_reload == 0); - assert(r_zero == 1'b1); - end - - - always @(*) - if (i_wb_stb) - assume(i_wb_cyc); - - always @(*) - assert(r_zero == (r_value == 0)); - - always @(*) - if (r_value != 0) - assert(r_running); - - always @(*) - if (auto_reload) - assert(r_running); - - always @(*) - if (!RELOADABLE) - assert(auto_reload == 0); - - always @(*) - if (auto_reload) - assert(interval_count != 0); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(r_value)==0) - &&(!$past(wb_write))&&(!$past(auto_reload))) - assert(r_value == 0); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!$past(wb_write)) - &&($past(r_value)==0)&&($past(auto_reload))) - begin - if ($past(i_ce)) - begin - assert(r_value == interval_count); - end else - assert(r_value == $past(r_value)); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset)) - &&(!$past(wb_write))&&($past(r_value)!=0)) - begin - if ($past(i_ce)) - begin - assert(r_value == $past(r_value)-1'b1); - end else - assert(r_value == $past(r_value)); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(wb_write))) - assert(r_value == $past(i_wb_data[(VW-1):0])); - - // Check auto_reload - // {{{ - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset) || !RELOADABLE) - begin - assert(!auto_reload); - end else if ($past(wb_write)) - begin - if (!$past(i_wb_data[BW-1])) - begin - assert(!auto_reload); - end else - assert(auto_reload == $past(|i_wb_data[VW-1:0])); - end else - assert($stable(auto_reload)); - // }}} - - always @(posedge i_clk) - if (!(f_past_valid)||($past(i_reset))) - begin - assert(!o_int); - end else if (($past(wb_write))||(!$past(i_ce))) - begin - assert(!o_int); - end else - assert(o_int == ((r_running)&&(r_value == 0))); - - always @(posedge i_clk) - if ((!f_past_valid)||($past(i_reset))) - begin - assert(!o_wb_ack); - end else if ($past(i_wb_stb)) - assert(o_wb_ack); - - always @(*) - assert(!o_wb_stall); - always @(*) - assert(o_wb_data[BW-1] == auto_reload); - always @(*) - assert(o_wb_data[VW-1:0] == r_value); -`endif -// }}} -endmodule diff --git a/delete_later/rtl/cpu/zipwb.v b/delete_later/rtl/cpu/zipwb.v deleted file mode 100644 index 06fc789..0000000 --- a/delete_later/rtl/cpu/zipwb.v +++ /dev/null @@ -1,676 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: zipwb.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is the top level module holding the core of the Zip CPU -// together. The Zip CPU is designed to be as simple as possible. -// (actual implementation aside ...) The instruction set is about as -// RISC as you can get, with only 26 instruction types currently supported. -// (There are still 8-instruction Op-Codes reserved for floating point, -// and 5 which can be used for transactions not requiring registers.) -// Please see the accompanying spec.pdf file for a description of these -// instructions. -// -// All instructions are 32-bits wide. All bus accesses, both address and -// data, are 32-bits over a wishbone bus. -// -// The Zip CPU is fully pipelined with the following pipeline stages: -// -// 1. Prefetch, returns the instruction from memory. -// -// 2. Instruction Decode -// -// 3. Read Operands -// -// 4. Apply Instruction -// -// 4. Write-back Results -// -// Further information about the inner workings of this CPU, such as -// what causes pipeline stalls, may be found in the spec.pdf file. (The -// documentation within this file had become out of date and out of sync -// with the spec.pdf, so look to the spec.pdf for accurate and up to date -// information.) -// -// -// In general, the pipelining is controlled by three pieces of logic -// per stage: _ce, _stall, and _valid. _valid means that the stage -// holds a valid instruction. _ce means that the instruction from the -// previous stage is to move into this one, and _stall means that the -// instruction from the previous stage may not move into this one. -// The difference between these control signals allows individual stages -// to propagate instructions independently. In general, the logic works -// as: -// -// -// assign (n)_ce = (n-1)_valid && (!(n)_stall) -// -// -// always @(posedge i_clk) -// if ((i_reset)||(clear_pipeline)) -// (n)_valid = 0 -// else if (n)_ce -// (n)_valid = 1 -// else if (n+1)_ce -// (n)_valid = 0 -// -// assign (n)_stall = ( (n-1)_valid && ( pipeline hazard detection ) ) -// || ( (n)_valid && (n+1)_stall ); -// -// and ... -// -// always @(posedge i_clk) -// if (n)_ce -// (n)_variable = ... whatever logic for this stage -// -// Note that a stage can stall even if no instruction is loaded into -// it. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module zipwb #( - // {{{ - parameter [31:0] RESET_ADDRESS=32'h010_0000, - parameter ADDRESS_WIDTH=30, - BUS_WIDTH = 32, // Bus width - OPT_LGICACHE=12, - localparam DATA_WIDTH = 32, // CPU data width - parameter OPT_MPY = 3, - parameter [0:0] OPT_DIV = 1, - parameter [0:0] OPT_SHIFTS = 1, - parameter [0:0] IMPLEMENT_FPU = 0, - parameter [0:0] OPT_EARLY_BRANCHING = 1, - parameter [0:0] OPT_CIS = 1'b1, - parameter [0:0] OPT_DISTRIBUTED_REGS = 1'b1, - parameter [0:0] OPT_PIPELINED = 1'b1, - parameter [0:0] OPT_START_HALTED=1, - parameter [0:0] OPT_LOCK=1, - parameter [0:0] OPT_LOWPOWER = 1'b0, - parameter OPT_LGDCACHE = 10, - parameter [0:0] OPT_SIM = 1'b1, - parameter [0:0] OPT_CLKGATE = 1'b0, - parameter [0:0] WITH_LOCAL_BUS = 1'b1, - parameter [0:0] OPT_DBGPORT = 1'b1, - parameter [0:0] OPT_TRACE_PORT = 1'b0, - parameter [0:0] OPT_PROFILER = 1'b0, - parameter [0:0] OPT_USERMODE = 1'b1, - localparam AW=ADDRESS_WIDTH, - localparam WBLSB = $clog2(BUS_WIDTH/8) -`ifdef FORMAL - , parameter F_LGDEPTH=8 -`endif - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, i_interrupt, - input wire i_cpu_clken, - // Debug interface -- inputs - input wire i_halt, i_clear_cache, - input wire [4:0] i_dbg_wreg, - input wire i_dbg_we, - input wire [DATA_WIDTH-1:0] i_dbg_data, - input wire [4:0] i_dbg_rreg, - // Debug interface -- outputs - output wire o_dbg_stall, - output wire o_halted, - output wire [DATA_WIDTH-1:0] o_dbg_reg, - output wire [2:0] o_dbg_cc, - output wire o_break, - // CPU interface to the wishbone bus - // Wishbone interface -- outputs - output wire o_wb_gbl_cyc, o_wb_gbl_stb, - output wire o_wb_lcl_cyc, o_wb_lcl_stb, - o_wb_we, - output wire [AW-1:0] o_wb_addr, - output wire [BUS_WIDTH-1:0] o_wb_data, - output wire [BUS_WIDTH/8-1:0] o_wb_sel, - // Wishbone interface -- inputs - input wire i_wb_stall, i_wb_ack, - input wire [BUS_WIDTH-1:0] i_wb_data, - input wire i_wb_err, - // Accounting outputs ... to help us count stalls and usage - output wire o_op_stall, - output wire o_pf_stall, - output wire o_i_count, - // - output wire [31:0] o_debug, - output wire o_prof_stb, - output wire [AW+WBLSB-1:0] o_prof_addr, - output wire [31:0] o_prof_ticks - // }}} - ); - - // Declarations - // {{{ - localparam [0:0] OPT_DCACHE = (OPT_LGDCACHE > 2); - localparam [0:0] OPT_PIPELINED_BUS_ACCESS = (OPT_PIPELINED); - localparam [0:0] OPT_MEMPIPE = OPT_PIPELINED_BUS_ACCESS; - localparam INSN_WIDTH = 32; - - wire cpu_clken, cpu_clock, clk_gate; - wire [31:0] cpu_debug; - - // Fetch - // {{{ - wire pf_new_pc, clear_icache, pf_ready; - wire [AW+WBLSB-1:0] pf_request_address; - wire [INSN_WIDTH-1:0] pf_instruction; - wire [AW+WBLSB-1:0] pf_instruction_pc; - wire pf_valid, pf_illegal; - // - wire pf_cyc, pf_stb, pf_stall, pf_ack, pf_err; - wire [AW-1:0] pf_addr; - // verilator coverage_off - // Since we aren't writing, these values will be constants - wire pf_we; - wire [BUS_WIDTH-1:0] pf_data; - // verilator coverage_on - // }}} - // Memory - // {{{ - wire clear_dcache, mem_ce, bus_lock; - wire [2:0] mem_op; - wire [31:0] mem_cpu_addr; - wire [AW+WBLSB-1:0] mem_lock_pc; // Byte address - wire [DATA_WIDTH-1:0] mem_wdata; - wire [BUS_WIDTH-1:0] mem_data; - wire [4:0] mem_reg; - wire mem_busy, mem_rdbusy, mem_pipe_stalled, mem_valid, - mem_bus_err; - wire [4:0] mem_wreg; - wire [DATA_WIDTH-1:0] mem_result; - // - wire mem_stb_lcl, mem_stb_gbl, mem_cyc_lcl, mem_cyc_gbl; - wire [AW-1:0] mem_bus_addr; - wire mem_we, mem_stall, mem_ack, mem_err; - wire [BUS_WIDTH/8-1:0] mem_sel; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The ZipCPU Core - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - wire w_dbg_stall; - - zipcore #( - // {{{ - .RESET_ADDRESS(RESET_ADDRESS), - .ADDRESS_WIDTH(AW+WBLSB-$clog2(DATA_WIDTH/8)), - .OPT_MPY(OPT_MPY), - .OPT_DIV(OPT_DIV), - .OPT_SHIFTS(OPT_SHIFTS), - .IMPLEMENT_FPU(IMPLEMENT_FPU), - .OPT_EARLY_BRANCHING(OPT_EARLY_BRANCHING), - .OPT_START_HALTED(OPT_START_HALTED), - .OPT_CIS(OPT_CIS), - .OPT_SIM(OPT_SIM), - .OPT_CLKGATE(OPT_CLKGATE), - .OPT_PIPELINED(OPT_PIPELINED), - .OPT_PIPELINED_BUS_ACCESS(OPT_MEMPIPE), - .OPT_DISTRIBUTED_REGS(OPT_DISTRIBUTED_REGS), - .OPT_USERMODE(OPT_USERMODE), - .OPT_LOCK(OPT_LOCK), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_DBGPORT(OPT_DBGPORT), - .OPT_TRACE_PORT(OPT_TRACE_PORT), - .OPT_PROFILER(OPT_PROFILER) -`ifdef FORMAL - , .F_LGDEPTH(F_LGDEPTH) -`endif - // }}} - ) core ( - // {{{ - .i_clk(cpu_clock), .i_reset(i_reset), .i_interrupt(i_interrupt), - .o_clken(cpu_clken), - // Debug interface - // {{{ - .i_halt(i_halt), .i_clear_cache(i_clear_cache), - .i_dbg_wreg(i_dbg_wreg), .i_dbg_we(i_dbg_we), - .i_dbg_data(i_dbg_data), - .i_dbg_rreg(i_dbg_rreg), .o_dbg_stall(w_dbg_stall), - .o_dbg_reg(o_dbg_reg), .o_dbg_cc(o_dbg_cc), - .o_break(o_break), - // }}} - // Instruction fetch interface - // {{{ - .o_pf_new_pc(pf_new_pc), .o_clear_icache(clear_icache), - .o_pf_ready(pf_ready), - .o_pf_request_address(pf_request_address), - .i_pf_valid(pf_valid), .i_pf_illegal(pf_illegal), - .i_pf_instruction(pf_instruction), - .i_pf_instruction_pc(pf_instruction_pc), - // }}} - // Memory unit interface - // {{{ - .o_clear_dcache(clear_dcache), .o_mem_ce(mem_ce), - .o_bus_lock(bus_lock), - .o_mem_op(mem_op), .o_mem_addr(mem_cpu_addr), - .o_mem_data(mem_wdata), - .o_mem_lock_pc(mem_lock_pc), - .o_mem_reg(mem_reg), - .i_mem_busy(mem_busy), .i_mem_rdbusy(mem_rdbusy), - .i_mem_pipe_stalled(mem_pipe_stalled), - .i_mem_valid(mem_valid), - .i_bus_err(mem_bus_err), - .i_mem_wreg(mem_wreg), - .i_mem_result(mem_result), - // }}} - // Accounting/CPU usage interface - // {{{ - .o_op_stall(o_op_stall), .o_pf_stall(o_pf_stall), - .o_i_count(o_i_count), - // }}} - .o_debug(cpu_debug), - .o_prof_stb(o_prof_stb), - .o_prof_addr(o_prof_addr), - .o_prof_ticks(o_prof_ticks) - // }}} - ); - - assign o_dbg_stall = w_dbg_stall || !clk_gate; - assign o_halted = !w_dbg_stall; - // }}} - // o_debug -- the debugging bus input - // {{{ - assign o_debug = cpu_debug; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Instruction Fetch - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_LGICACHE <= 1) - begin : SINGLE_FETCH - - prefetch #( - // {{{ - .ADDRESS_WIDTH(ADDRESS_WIDTH+WBLSB), - .INSN_WIDTH(INSN_WIDTH), - .DATA_WIDTH(BUS_WIDTH), - // .OPT_LOWPOWER(OPT_LOWPOWER), (Unused) - .OPT_LITTLE_ENDIAN(1'b0) - // }}} - ) pf ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // CPU signals - // {{{ - .i_new_pc(pf_new_pc), .i_clear_cache(clear_icache), - .i_ready(pf_ready && clk_gate), - .i_pc(pf_request_address), - .o_valid(pf_valid), .o_illegal(pf_illegal), - .o_insn(pf_instruction), - .o_pc(pf_instruction_pc), - // }}} - // Wishbone signals - // {{{ - .o_wb_cyc(pf_cyc), .o_wb_stb(pf_stb), - .o_wb_we(pf_we), .o_wb_addr(pf_addr), - .o_wb_data(pf_data), - .i_wb_stall(pf_stall), .i_wb_ack(pf_ack), - .i_wb_err(pf_err), .i_wb_data(i_wb_data) - // }}} - // }}} - ); - - end else if (OPT_LGICACHE <= 2) - begin : DBLFETCH - - dblfetch #( - // {{{ - .ADDRESS_WIDTH(ADDRESS_WIDTH+WBLSB), - .DATA_WIDTH(BUS_WIDTH), - .INSN_WIDTH(INSN_WIDTH), - // .OPT_LOWPOWER(OPT_LOWPOWER), (Unused) - .OPT_LITTLE_ENDIAN(1'b0) - // }}} - ) pf ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // CPU signals - // {{{ - .i_new_pc(pf_new_pc), - .i_clear_cache(clear_icache), - .i_ready(pf_ready && clk_gate), - .i_pc(pf_request_address), - .o_valid(pf_valid), .o_illegal(pf_illegal), - .o_insn(pf_instruction), - .o_pc(pf_instruction_pc), - // }}} - // Wishbone signals - // {{{ - .o_wb_cyc(pf_cyc), .o_wb_stb(pf_stb), .o_wb_we(pf_we), - .o_wb_addr(pf_addr), .o_wb_data(pf_data), - .i_wb_stall(pf_stall), .i_wb_ack(pf_ack), - .i_wb_err(pf_err), .i_wb_data(i_wb_data) - // }}} - // }}} - ); - - end else begin : PFCACHE - - pfcache #( - // {{{ - .BUS_WIDTH(BUS_WIDTH), - // .INSN_WIDTH(INSN_WIDTH), - .LGCACHELEN(OPT_LGICACHE-WBLSB), - // .OPT_LOWPOWER(OPT_LOWPOWER), (Unused) - .ADDRESS_WIDTH(ADDRESS_WIDTH) - // }}} - ) pf( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // CPU signals - .i_new_pc(pf_new_pc), .i_clear_cache(clear_icache), - .i_ready(pf_ready && clk_gate), .i_pc(pf_request_address), - .o_valid(pf_valid), .o_illegal(pf_illegal), - .o_insn(pf_instruction), - .o_pc(pf_instruction_pc), - // Wishbone signals - .o_wb_cyc(pf_cyc), .o_wb_stb(pf_stb), - .o_wb_we(pf_we), .o_wb_addr(pf_addr), - .o_wb_data(pf_data), - .i_wb_stall(pf_stall), .i_wb_ack(pf_ack), - .i_wb_err(pf_err), .i_wb_data(i_wb_data) - // }}} - ); - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Memory Unit - // {{{ - //////////////////////////////////////////////////////////////////////// - // - generate if (OPT_DCACHE) - begin : DATA_CACHE - - dcache #( - // {{{ - .LGCACHELEN(OPT_LGDCACHE-WBLSB), - .ADDRESS_WIDTH(AW), - .BUS_WIDTH(BUS_WIDTH), - .LGNLINES(OPT_LGDCACHE-WBLSB-3), - .OPT_LOCAL_BUS(WITH_LOCAL_BUS), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_PIPE(OPT_MEMPIPE), - .OPT_LOCK(OPT_LOCK) -`ifdef FORMAL - , .OPT_FIFO_DEPTH(2) - , .F_LGDEPTH(F_LGDEPTH) -`endif - // }}} - ) mem( - // {{{ - .i_clk(cpu_clock), .i_reset(i_reset),.i_clear(clear_dcache), - // CPU interface - .i_pipe_stb(mem_ce), .i_lock(bus_lock && OPT_PIPELINED), - .i_op(mem_op), .i_addr(mem_cpu_addr),.i_data(mem_wdata), - .i_oreg(mem_reg), - .o_busy(mem_busy), .o_rdbusy(mem_rdbusy), - .o_pipe_stalled(mem_pipe_stalled), - .o_valid(mem_valid), .o_err(mem_bus_err), - .o_wreg(mem_wreg), .o_data(mem_result), - // Wishbone interface - .o_wb_cyc_gbl(mem_cyc_gbl), .o_wb_cyc_lcl(mem_cyc_lcl), - .o_wb_stb_gbl(mem_stb_gbl), .o_wb_stb_lcl(mem_stb_lcl), - .o_wb_we(mem_we), .o_wb_addr(mem_bus_addr), - .o_wb_data(mem_data),.o_wb_sel(mem_sel), - .i_wb_stall(mem_stall), .i_wb_ack(mem_ack), - .i_wb_err(mem_err),.i_wb_data(i_wb_data) - // }}} - ); - - end else if (OPT_MEMPIPE) - begin : PIPELINED_MEM - - pipemem #( - // {{{ - .ADDRESS_WIDTH(AW), - .BUS_WIDTH(BUS_WIDTH), - .OPT_LOCK(OPT_LOCK), - // .OPT_LOWPOWER(OPT_LOWPOWER), (Unused) - .WITH_LOCAL_BUS(WITH_LOCAL_BUS) -`ifdef FORMAL - , .OPT_MAXDEPTH(4'h3), - .F_LGDEPTH(F_LGDEPTH) -`endif - // }}} - ) domem( - // {{{ - .i_clk(cpu_clock), .i_reset(i_reset), - // CPU interface - .i_pipe_stb(mem_ce), .i_lock(bus_lock && OPT_PIPELINED), - .i_op(mem_op), .i_addr(mem_cpu_addr), - .i_data(mem_wdata), .i_oreg(mem_reg), - .o_busy(mem_busy), .o_rdbusy(mem_rdbusy), - .o_pipe_stalled(mem_pipe_stalled), - .o_valid(mem_valid), .o_err(mem_bus_err), - .o_wreg(mem_wreg), .o_result(mem_result), - // Wishbone interface - .o_wb_cyc_gbl(mem_cyc_gbl), .o_wb_cyc_lcl(mem_cyc_lcl), - .o_wb_stb_gbl(mem_stb_gbl), - .o_wb_stb_lcl(mem_stb_lcl), - .o_wb_we(mem_we), .o_wb_addr(mem_bus_addr), - .o_wb_data(mem_data),.o_wb_sel(mem_sel), - .i_wb_stall(mem_stall), .i_wb_ack(mem_ack), - .i_wb_err(mem_err),.i_wb_data(i_wb_data) - // }}} - ); - - end else begin : BARE_MEM - - memops #( - // {{{ - .ADDRESS_WIDTH(AW), - .BUS_WIDTH(BUS_WIDTH), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_LOCK(OPT_LOCK), - .WITH_LOCAL_BUS(WITH_LOCAL_BUS) -`ifdef FORMAL - , .F_LGDEPTH(F_LGDEPTH) -`endif // F_LGDEPTH - // }}} - ) domem( - // {{{ - .i_clk(cpu_clock), .i_reset(i_reset), - // CPU interface - .i_stb(mem_ce), .i_lock(bus_lock && OPT_PIPELINED), - .i_op(mem_op), .i_addr(mem_cpu_addr), - .i_data(mem_wdata), .i_oreg(mem_reg), - .o_busy(mem_busy), .o_rdbusy(mem_rdbusy), - .o_valid(mem_valid), .o_err(mem_bus_err), - .o_wreg(mem_wreg), .o_result(mem_result), - // Wishbone interface - .o_wb_cyc_gbl(mem_cyc_gbl), .o_wb_cyc_lcl(mem_cyc_lcl), - .o_wb_stb_gbl(mem_stb_gbl), .o_wb_stb_lcl(mem_stb_lcl), - .o_wb_we(mem_we), .o_wb_addr(mem_bus_addr), - .o_wb_data(mem_data), .o_wb_sel(mem_sel), - .i_wb_stall(mem_stall), .i_wb_ack(mem_ack), - .i_wb_err(mem_err), .i_wb_data(i_wb_data) - // }}} - ); - - assign mem_pipe_stalled = mem_busy; - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus arbiter - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // Either the prefetch or the instruction gets the memory bus, but - // never both under this arbitration scheme. - generate if (OPT_PIPELINED) - begin : PRIORITY_DATA - - wbdblpriarb #( - // {{{ - .AW(AW), - .DW(BUS_WIDTH), - .OPT_ZERO_ON_IDLE(OPT_LOWPOWER) - // }}} - ) pformem( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // Memory access to the arbiter, priority position - .i_a_cyc_a(mem_cyc_gbl), .i_a_cyc_b(mem_cyc_lcl), - .i_a_stb_a(mem_stb_gbl), .i_a_stb_b(mem_stb_lcl), - .i_a_we(mem_we), .i_a_adr(mem_bus_addr), - .i_a_dat(mem_data), .i_a_sel(mem_sel), - .o_a_stall(mem_stall), .o_a_ack(mem_ack), - .o_a_err(mem_err), - // Prefetch access to the arbiter - // - // At a first glance, we might want something like: - // - // pf_cyc, 1'b0, pf_stb, 1'b0, pf_we, pf_addr, pf_data, 4'hf, - // - // However, we know that the prefetch will not generate - // any writes. Therefore, the write specific lines - // (mem_data) can be shared with the memory in order to - // ease timing and LUT usage. This is not true of - // mem_sel, which may be used to know which bytes we are - // reading from. - .i_b_cyc_a(pf_cyc), .i_b_cyc_b(1'b0), - .i_b_stb_a(pf_stb), .i_b_stb_b(1'b0), - .i_b_we(pf_we), .i_b_adr(pf_addr), - .i_b_dat(mem_data), - .i_b_sel({(BUS_WIDTH/8){1'b1}}), - .o_b_stall(pf_stall), .o_b_ack(pf_ack), - .o_b_err(pf_err), - // Common wires, in and out, of the arbiter - .o_cyc_a(o_wb_gbl_cyc), .o_cyc_b(o_wb_lcl_cyc), - .o_stb_a(o_wb_gbl_stb), .o_stb_b(o_wb_lcl_stb), - .o_we(o_wb_we), .o_adr(o_wb_addr), - .o_dat(o_wb_data), .o_sel(o_wb_sel), - .i_stall(i_wb_stall), .i_ack(i_wb_ack), - .i_err(i_wb_err) - // }}} - ); - - end else begin : PRIORITY_PREFETCH - - wbdblpriarb #( - // {{{ - .DW(BUS_WIDTH), .AW(AW), - .OPT_ZERO_ON_IDLE(OPT_LOWPOWER) - // }}} - ) pformem( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // Prefetch access to the arbiter, priority position - // - .i_a_cyc_a(pf_cyc), .i_a_cyc_b(1'b0), - .i_a_stb_a(pf_stb), .i_a_stb_b(1'b0), - .i_a_we(pf_we), .i_a_adr(pf_addr), - .i_a_dat(mem_data), - .i_a_sel({(BUS_WIDTH/8){1'b1}}), - .o_a_stall(pf_stall), .o_a_ack(pf_ack), - .o_a_err(pf_err), - // Memory access to the arbiter - .i_b_cyc_a(mem_cyc_gbl), .i_b_cyc_b(mem_cyc_lcl), - .i_b_stb_a(mem_stb_gbl),.i_b_stb_b(mem_stb_lcl), - .i_b_we(mem_we), .i_b_adr(mem_bus_addr), - .i_b_dat(mem_data), .i_b_sel(mem_sel), - .o_b_stall(mem_stall), .o_b_ack(mem_ack), - .o_b_err(mem_err), - // Common wires, in and out, of the arbiter - .o_cyc_a(o_wb_gbl_cyc), .o_cyc_b(o_wb_lcl_cyc), - .o_stb_a(o_wb_gbl_stb), .o_stb_b(o_wb_lcl_stb), - .o_we(o_wb_we), .o_adr(o_wb_addr), - .o_dat(o_wb_data), .o_sel(o_wb_sel), - .i_stall(i_wb_stall), .i_ack(i_wb_ack), - .i_err(i_wb_err) - // }}} - ); - - end endgenerate - //}}} - //////////////////////////////////////////////////////////////////////// - // - // (Optional) Clock Gate - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_CLKGATE) - begin : GATE_CPU_CLOCK - // {{{ - reg gatep; - reg gaten /* verilator clock_enable */; - - initial gatep = 1'b1; - always @(posedge i_clk) - if (i_reset) - gatep <= 1'b1; - else - gatep <= cpu_clken || i_dbg_we || i_cpu_clken; - - initial gaten = 1'b1; - always @(negedge i_clk) - if (i_reset) - gaten <= 1'b1; - else - gaten <= gatep; - - assign cpu_clock = i_clk && gaten; - assign clk_gate = gatep; - // }}} - end else begin : NO_CLOCK_GATE - - assign cpu_clock = i_clk; - assign clk_gate = 1'b1; - - // Verilattor lint_off UNUSED - wire unused_clk; - assign unused_clk = &{ 1'b0, i_cpu_clken, cpu_clken }; - // Verilator lint_on UNUSED - end endgenerate - // }}} - - // Make Verilator happy - // {{{ - // verilator coverage_off - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, pf_data, mem_lock_pc, clear_dcache }; - // Verilator lint_on UNUSED - // verilator coverage_on - // }}} -endmodule diff --git a/delete_later/rtl/ddr3/ddr3_controller.v b/delete_later/rtl/ddr3/ddr3_controller.v deleted file mode 100644 index 932e3df..0000000 --- a/delete_later/rtl/ddr3/ddr3_controller.v +++ /dev/null @@ -1,3473 +0,0 @@ -// Background: -// This DDR3 controller will be used with a DDR3-1600 with Kintex 7 FPGA Board (XC7K160T-3FFG676E). -// The goal will be to: -// - Run this at 1600Mbps (Maximum Physical Interface (PHY) Rate for a 4:1 -// memory controller based on "DC and AC Switching Characteristics" for Kintex 7) -// - Parameterize everything -// - Interface should be (nearly) bus agnostic -// - High (sustained) data throughput. Sequential writes should be able to continue without interruption - -//`define MICRON_SIM //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW) -//`define FORMAL_COVER //change delay in reset sequence to fit in cover statement -//`define COVER_DELAY 1 //fixed delay used in formal cover for reset sequence -`default_nettype none -`timescale 1ps / 1ps - - -// THESE DEFINES WILL BE MODIFIED AS PARAMETERS LATER ON -`define DDR3_1600_11_11_11 // DDR3-1600 (11-11-11) speed bin -`define RAM_8Gb //DDR3 Capacity -//`define RAM_2Gb -//`define RAM_4Gb -//`define RAM_8Gb -`define x8 //DDR3 organization (DQ bus width) -//`define x4 -//`define x16 - -//NOTE IN FORMAL INDUCTION: Make formal induction finish in shorter time by lowering the delays between commands. -//A good basis on the formal depth is the value of PRE_STALL_DELAY. -//The value of prestall delay is the longest possible -//clock cycles needed to finish 2 requests. Since the -//fifo used in the formal induction has 2 locations -//only (pertains to the request stored on the two -// pipeline stages of bank access), we need to flush -// those two requests on the fifo first, and the max -// time for two request is also the value of -// PRE_STALL_DELAY - -module ddr3_controller #( - parameter real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module - DDR3_CLK_PERIOD = 2.5, //ns, period of clock input to DDR3 RAM device - parameter ROW_BITS = 14, //width of row address - COL_BITS = 10, //width of column address - BA_BITS = 3, //width of bank address - DQ_BITS = 8, //width of DQ - LANES = 8, //8 lanes of DQ - AUX_WIDTH = 16, - WB2_ADDR_BITS = 32, - WB2_DATA_BITS = 32, - parameter[0:0] OPT_LOWPOWER = 1, //1 = low power, 0 = low logic - OPT_BUS_ABORT = 1, //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction) - - parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration - serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD), - wb_data_bits = DQ_BITS*LANES*serdes_ratio*2, - wb_addr_bits = ROW_BITS + COL_BITS + BA_BITS - $clog2(wb_data_bits/ 8), - wb_sel_bits = wb_data_bits / 8, - wb2_sel_bits = WB2_DATA_BITS / 8, - //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits - cmd_len = 4 + 3 + BA_BITS + ROW_BITS - ) - ( - input wire i_controller_clk, //i_controller_clk has period of CONTROLLER_CLK_PERIOD - input wire i_rst_n, //200MHz input clock - // Wishbone inputs - input wire i_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) - input wire i_wb_stb, //request a transfer - input wire i_wb_we, //write-enable (1 = write, 0 = read) - input wire[wb_addr_bits - 1:0] i_wb_addr, //burst-addressable {row,bank,col} - input wire[wb_data_bits - 1:0] i_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device - input wire[wb_sel_bits - 1:0] i_wb_sel, //byte strobe for write (1 = write the byte) - input wire[AUX_WIDTH - 1:0] i_aux, //for AXI-interface compatibility (given upon strobe) - // Wishbone outputs - output reg o_wb_stall, //1 = busy, cannot accept requests - output wire o_wb_ack, //1 = read/write request has completed - output wire[wb_data_bits - 1:0] o_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device - output wire[AUX_WIDTH - 1:0] o_aux, //for AXI-interface compatibility (returned upon ack) - // - // Wishbone 2 (PHY) inputs - input wire i_wb2_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) - input wire i_wb2_stb, //request a transfer - input wire i_wb2_we, //write-enable (1 = write, 0 = read) - input wire[WB2_ADDR_BITS - 1:0] i_wb2_addr, //memory-mapped register to be accessed - input wire[wb2_sel_bits - 1:0] i_wb2_sel, //byte strobe for write (1 = write the byte) - input wire[WB2_DATA_BITS - 1:0] i_wb2_data, //write data - // Wishbone 2 (Controller) outputs - output reg o_wb2_stall, //1 = busy, cannot accept requests - output reg o_wb2_ack, //1 = read/write request has completed - output reg[WB2_DATA_BITS - 1:0] o_wb2_data, //read data - // - // PHY interface - input wire[DQ_BITS*LANES*8-1:0] i_phy_iserdes_data, - input wire[LANES*8-1:0] i_phy_iserdes_dqs, - input wire[LANES*8-1:0] i_phy_iserdes_bitslip_reference, - input wire i_phy_idelayctrl_rdy, - output wire[cmd_len*serdes_ratio-1:0] o_phy_cmd, - output wire o_phy_dqs_tri_control, o_phy_dq_tri_control, - output wire o_phy_toggle_dqs, - output wire[wb_data_bits-1:0] o_phy_data, - output wire[wb_sel_bits-1:0] o_phy_dm, - output wire[4:0] o_phy_odelay_data_cntvaluein, o_phy_odelay_dqs_cntvaluein, - output wire[4:0] o_phy_idelay_data_cntvaluein, o_phy_idelay_dqs_cntvaluein, - output reg[LANES-1:0] o_phy_odelay_data_ld, o_phy_odelay_dqs_ld, - output reg[LANES-1:0] o_phy_idelay_data_ld, o_phy_idelay_dqs_ld, - output reg[LANES-1:0] o_phy_bitslip - ); - - - /************************************************************* Command Parameters *************************************************************/ - //DDR3 commands {cs_n, ras_n, cas_n, we_n} (JEDEC DDR3 doc pg. 33 ) - localparam[3:0]CMD_MRS = 4'b0000, // Mode Register Set - CMD_REF = 4'b0001, // Refresh - CMD_PRE = 4'b0010, // Precharge (A10-AP: 0 = Single Bank Precharge, 1 = Precharge All Banks) - CMD_ACT = 4'b0011, // Bank Activate - CMD_WR = 4'b0100, // Write (A10-AP: 0 = no Auto-Precharge) (A12-BC#: 1 = Burst Length 8) - CMD_RD = 4'b0101, //Read (A10-AP: 0 = no Auto-Precharge) (A12-BC#: 1 = Burst Length 8) - CMD_NOP = 4'b0111, // No Operation - CMD_DES = 4'b1000, // Deselect command performs the same function as No Operation command (JEDEC DDR3 doc pg. 34 NOTE 11) - CMD_ZQC = 4'b0110; // ZQ Calibration (A10-AP: 0 = ZQ Calibration Short, 1 = ZQ Calibration Long) - - localparam RST_DONE = 27, // Command bit that determines if reset seqeunce had aready finished. non-persistent (only needs to be toggled once), - REF_IDLE = 27, // No refresh is about to start and no ongoing refresh. (same bit as RST_DONE) - USE_TIMER = 26, // Command bit that determines if timer will be used (if delay is zero, USE_TIMER must be LOW) - A10_CONTROL = 25, //Command bit that determines if A10 AutoPrecharge will be high - CLOCK_EN = 24, //Clock-enable to DDR3 - RESET_N = 23, //Reset_n to DDR3 - DDR3_CMD_START = 22, //Start of DDR3 command slot - DDR3_CMD_END = 19, //end of DDR3 command slot - MRS_BANK_START = 18; //start of bank value in MRS value - - // ddr3 command partitioning - localparam CMD_CS_N = cmd_len - 1, - CMD_RAS_N = cmd_len - 2, - CMD_CAS_N= cmd_len - 3, - CMD_WE_N = cmd_len - 4, - CMD_ODT = cmd_len - 5, - CMD_CKE = cmd_len - 6, - CMD_RESET_N = cmd_len - 7, - CMD_BANK_START = BA_BITS + ROW_BITS - 1, - CMD_ADDRESS_START = ROW_BITS - 1; - - localparam READ_SLOT = get_slot(CMD_RD), - WRITE_SLOT = get_slot(CMD_WR), - ACTIVATE_SLOT = get_slot(CMD_ACT), - PRECHARGE_SLOT = get_slot(CMD_PRE); - - // Data does not have to be delayed (DQS is the on that has to be - // delayed and center-aligned to the center eye of data) - localparam DATA_INITIAL_ODELAY_TAP = 0; - - //DQS needs to be edge-aligned to the center eye of the data. - //This means DQS needs to be delayed by a quarter of the ddr3 - //clk period relative to the data. Subtract by 600ps to include - //the IODELAY insertion delay. Divide by a delay resolution of - //78.125ps per tap to get the needed tap value. Then add the tap - //value used in data to have the delay relative to the data. - localparam DQS_INITIAL_ODELAY_TAP = $rtoi(((DDR3_CLK_PERIOD*1000/4))/78.125 + DATA_INITIAL_ODELAY_TAP); - - //Incoming DQS should be 90 degree delayed relative to incoming data - localparam DATA_INITIAL_IDELAY_TAP = 0; //600ps delay - localparam DQS_INITIAL_IDELAY_TAP = $rtoi(((DDR3_CLK_PERIOD*1000/4))/78.125 + DATA_INITIAL_IDELAY_TAP); - /*********************************************************************************************************************************************/ - - - /********************************************************** Timing Parameters ***********************************************************************************/ - localparam DELAY_SLOT_WIDTH = 19; //Bitwidth of the delay slot and mode register slot on the reset/refresh rom will be at the same size as the Mode Register - localparam POWER_ON_RESET_HIGH = 200_000; // 200us reset must be active at initialization - localparam INITIAL_CKE_LOW = 500_000; // 500us cke must be low before activating - `ifdef DDR3_1600_11_11_11 //DDR3-1600 (11-11-11) speed bin - localparam tRCD = 13.750; // ns Active to Read/Write command time - localparam tRP = 13.750; // ns Precharge command period - localparam tRAS = 35; // ns ACT to PRE command period - `endif - - `ifdef RAM_1Gb - localparam tRFC = 110.0; // ns Refresh command to ACT or REF - `elsif RAM_2Gb - localparam tRFC = 160.0; // ns Refresh command to ACT or REF - `elsif RAM_4Gb - localparam tRFC = 300.0; // ns Refresh command to ACT or REF - `else - localparam tRFC = 350.0; // ns Refresh command to ACT or REF - `endif - localparam tREFI = 7800; //ns Average periodic refresh interval - localparam tXPR = max(5*DDR3_CLK_PERIOD, tRFC+10); // ns Exit Reset from CKE HIGH to a valid command - localparam tMRD = 4; // nCK Mode Register Set command cycle time - localparam tWR = 15.0; // ns Write Recovery Time - localparam tWTR = max(nCK_to_ns(4), 7.5); //ns Delay from start of internal write transaction to internal read command - localparam[DELAY_SLOT_WIDTH - 1:0] tWLMRD = nCK_to_cycles(40); // nCK First DQS/DQS# rising edge after write leveling mode is programmed - localparam tWLO = 7.5; //ns Write leveling output delay - localparam tWLOE = 2; - localparam tRTP = max(nCK_to_ns(4), 7.5); //ns Internal Command to PRECHARGE Command delay - localparam tCCD = 4; //nCK CAS to CAS command delay - localparam tMOD = $rtoi(max(nCK_to_cycles(12), ns_to_cycles(15))); //cycles (controller) Mode Register Set command update delay - localparam tZQinit = $rtoi(max(nCK_to_cycles(512), ns_to_cycles(640)));//cycles (controller) Power-up and RESET calibration time - localparam CL_nCK = 6; //create a function for this - localparam CWL_nCK = 5; //create a function for this - localparam DELAY_MAX_VALUE = ns_to_cycles(INITIAL_CKE_LOW); //Largest possible delay needed by the reset and refresh sequence - localparam DELAY_COUNTER_WIDTH= $clog2(DELAY_MAX_VALUE); //Bitwidth needed by the maximum possible delay, this will be the delay counter width - localparam CALIBRATION_DELAY = 2; - - /*********************************************************************************************************************************************/ - - - /********************************************************** Computed Delay Parameters **********************************************************/ - localparam[3:0] PRECHARGE_TO_ACTIVATE_DELAY = find_delay(ns_to_nCK(tRP), PRECHARGE_SLOT, ACTIVATE_SLOT); //3 - localparam[3:0] ACTIVATE_TO_PRECHARGE_DELAY = find_delay(ns_to_nCK(tRAS), ACTIVATE_SLOT, PRECHARGE_SLOT); - localparam[3:0] ACTIVATE_TO_WRITE_DELAY = find_delay(ns_to_nCK(tRCD), ACTIVATE_SLOT, WRITE_SLOT); //3 - localparam[3:0] ACTIVATE_TO_READ_DELAY = find_delay(ns_to_nCK(tRCD), ACTIVATE_SLOT, READ_SLOT); //2 - localparam[3:0] READ_TO_WRITE_DELAY = find_delay((CL_nCK + tCCD + 2 - CWL_nCK), READ_SLOT, WRITE_SLOT); //2 - localparam[3:0] READ_TO_READ_DELAY = 0; - localparam[3:0] READ_TO_PRECHARGE_DELAY = find_delay(ns_to_nCK(tRTP), READ_SLOT, PRECHARGE_SLOT); //1 - localparam[3:0] WRITE_TO_WRITE_DELAY = 0; - localparam[3:0] WRITE_TO_READ_DELAY = find_delay((CWL_nCK + 4 + ns_to_nCK(tWTR)), WRITE_SLOT, READ_SLOT); //4 - localparam[3:0] WRITE_TO_PRECHARGE_DELAY = find_delay((CWL_nCK + 4 + ns_to_nCK(tWR)), WRITE_SLOT, PRECHARGE_SLOT); //5 - localparam PRE_REFRESH_DELAY = WRITE_TO_PRECHARGE_DELAY + 1; - - //MARGIN_BEFORE_ANTICIPATE is the number of columns before the column - //end when the anticipate can start - //the worst case scenario is when the anticipated bank needs to be precharged - //thus the margin must satisfy tRP (for precharge) and tRCD (for activate). - //Also, worscase is when the anticipated bank still has the leftover of the - //WRITE_TO_PRECHARGE_DELAY thus consider also this. - localparam MARGIN_BEFORE_ANTICIPATE = PRECHARGE_TO_ACTIVATE_DELAY + ACTIVATE_TO_WRITE_DELAY + WRITE_TO_PRECHARGE_DELAY; - localparam STAGE2_DATA_DEPTH = (CWL_nCK - (3 - WRITE_SLOT + 1))/4 + 1; //this is always >= 1 (5 - (3 - 3 + 1))/4.0 -> floor(1) + 1 = floor(4 - `ifdef FORMAL - wire stage2_data_depth; - assign stage2_data_depth = STAGE2_DATA_DEPTH; - always @* begin - assert(STAGE2_DATA_DEPTH-2 >= 0); - end - `endif - localparam READ_DELAY = $rtoi($floor((CL_nCK - (3 - READ_SLOT + 1))/4.0 )); - localparam READ_ACK_PIPE_WIDTH = READ_DELAY + 1 + 2 + 1 + 1; - localparam MAX_ADDED_READ_ACK_DELAY = 16; - localparam DELAY_BEFORE_WRITE_LEVEL_FEEDBACK = STAGE2_DATA_DEPTH + ns_to_cycles(tWLO+tWLOE) + 10; //plus 10 controller clocks for possible bus latency and - //the delay for receiving feedback DQ from IOBUF -> IDELAY -> ISERDES - /*********************************************************************************************************************************************/ - - - /********************************************************** Read/Write Calibration Parameters **********************************************************/ - localparam IDLE = 0, - BITSLIP_DQS_TRAIN_1 = 1, - MPR_READ = 2, - COLLECT_DQS = 3, - ANALYZE_DQS = 4, - CALIBRATE_DQS = 5, - BITSLIP_DQS_TRAIN_2 = 6, - START_WRITE_LEVEL = 7, - WAIT_FOR_FEEDBACK = 8, - ISSUE_WRITE_1 = 9, - ISSUE_WRITE_2 = 10, - ISSUE_READ = 11, - READ_DATA = 12, - ANALYZE_DATA = 13, - DONE_CALIBRATE = 14; - localparam STORED_DQS_SIZE = 5, //must be >= 2 - REPEAT_DQS_ANALYZE = 1; // repeat DQS read to find the accurate starting position of DQS - - /*********************************************************************************************************************************************/ - - - /************************************************************* Set Mode Registers Parameters *************************************************************/ - // MR2 (JEDEC DDR3 doc pg. 30) - localparam[2:0] PASR = 3'b000; //Partial Array Self-Refresh: Full Array - localparam[2:0] CWL = 3'b000; //CAS write Latency: 8 (1.5 ns > tCK(avg) >= 1.25 ns) CREATE A FUNCTION FOR THIS - localparam[0:0] ASR = 1'b1; //Auto Self-Refresh: on - localparam[0:0] SRT = 1'b0; //Self-Refresh Temperature Range:0 (If ASR = 1, SRT bit must be set to 0) - localparam[1:0] RTT_WR = 2'b00; //Dynamic ODT: off - localparam[2:0] MR2_SEL = 3'b010; //Selected Mode Register - localparam[18:0] MR2 = {MR2_SEL, 5'b00000, RTT_WR, 1'b0, SRT, ASR, CWL, PASR}; - - // MR3 (JEDEC DDR3 doc pg. 32) - localparam[1:0] MPR_LOC = 2'b00; //Data location for MPR Reads: Predefined Pattern 0_1_0_1_0_1_0_1 - localparam[0:0] MPR_EN = 1'b1; //MPR Enable: Enable MPR reads and calibration during initialization - localparam[0:0] MPR_DIS = 1'b0; //MPR Enable: Enable MPR reads and calibration during initialization - localparam[2:0] MR3_SEL = 3'b011; //MPR Selected - localparam[18:0] MR3_MPR_EN = {MR3_SEL, 13'b0_0000_0000_0000, MPR_EN, MPR_LOC}; - localparam[18:0] MR3_MPR_DIS = {MR3_SEL, 13'b0_0000_0000_0000, MPR_DIS, MPR_LOC}; - localparam[ROW_BITS+BA_BITS-1:0] MR3_RD_ADDR = 0; - - // MR1 (JEDEC DDR3 doc pg. 27) - localparam DLL_EN = 1'b0; //DLL Enable/Disable: Enabled(0) - localparam[1:0] DIC = 2'b00; //Output Driver Impedance Control (IS THIS THE SAME WITH RTT_NOM???????????? Search later) - localparam[2:0] RTT_NOM = 3'b011; //RTT Nominal: 40ohms (RQZ/6) is the impedance of the PCB trace - localparam[0:0] WL_EN = 1'b1; //Write Leveling Enable: Disabled - localparam[0:0] WL_DIS = 1'b0; //Write Leveling Enable: Disabled - localparam[1:0] AL = 2'b00; //Additive Latency: Disabled - localparam[0:0] TDQS = 1'b1; //Termination Data Strobe: Disabled (provides additional termination resistance outputs. - //When the TDQS function is disabled, the DM function is provided (vice-versa).TDQS function is only - //available for X8 DRAM and must be disabled for X4 and X16. - localparam[0:0] QOFF = 1'b0; //Output Buffer Control: Enabled - localparam[2:0] MR1_SEL = 3'b001; //Selected Mode Register - localparam[18:0] MR1_WL_EN = {MR1_SEL, 3'b000, QOFF, TDQS, 1'b0, RTT_NOM[2], 1'b0, WL_EN, RTT_NOM[1], DIC[1], AL, RTT_NOM[0], DIC[0], DLL_EN}; - localparam[18:0] MR1_WL_DIS = {MR1_SEL, 3'b000, QOFF, TDQS, 1'b0, RTT_NOM[2], 1'b0, WL_DIS, RTT_NOM[1], DIC[1], AL, RTT_NOM[0], DIC[0], DLL_EN}; - - //MR0 (JEDEC DDR3 doc pg. 24) - localparam[1:0] BL = 2'b00; //Burst Length: 8 (Fixed) - localparam[3:0] CL = 4'b0100; //CAS Read Latency: 10, can support DDR-1600 speedbin 8-8-8, 9-9-9, and 10-10-10 (Check JEDEC DDR doc pg. 162) CREATE A FUNCTION FOR THIS - localparam[0:0] RBT = 1'b0; //Read Burst Type: Nibble Sequential - localparam[0:0] DLL_RST = 1'b1; //DLL Reset: Yes (this is self-clearing and must be applied after DLL enable) - localparam[2:0] WR = WRA_mode_register_value($rtoi($ceil(tWR/DDR3_CLK_PERIOD))); //Write recovery for autoprecharge ( - localparam[0:0] PPD = 1'b0; //DLL Control for Precharge PD: Slow exit (DLL off) - localparam[2:0] MR0_SEL = 3'b000; - localparam[18:0] MR0 = {MR0_SEL, 3'b000, PPD, WR, DLL_RST, 1'b0, CL[3:1], RBT, CL[0], BL}; - /*********************************************************************************************************************************************/ - localparam INITIAL_RESET_INSTRUCTION = {5'b01000 , CMD_NOP , { {(DELAY_SLOT_WIDTH-3){1'b0}} , 3'd5} }; - - /************************************************************* Registers and Wires *************************************************************/ - integer index; - reg[4:0] instruction_address = 0; //address for accessing rom instruction - reg[27:0] instruction = INITIAL_RESET_INSTRUCTION; //instruction retrieved from reset instruction rom - reg[ DELAY_COUNTER_WIDTH - 1:0] delay_counter = INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0]; //counter used for delays - reg delay_counter_is_zero = (INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0] == 0); //counter is now zero so retrieve next delay - reg reset_done = 0; //high if reset has already finished - reg pause_counter = 0; - wire issue_read_command; - wire issue_write_command; - reg stage2_update = 1; - reg stage2_stall = 0; - reg stage1_stall = 0; - reg[(1< shiftreg(CWL) -> OSERDES(DDR) -> ODELAY -> RAM - end - - // when not in refresh, transaction can only be processed when i_wb_cyc is high and not stall - if(i_wb_cyc && !o_wb_stall) begin - //stage1 will not do the request (pending low) when the - //request is on the same bank as the current request. This - //will ensure stage1 bank will be different from stage2 bank - stage1_pending <= i_wb_stb;//actual request flag - stage1_aux <= i_aux; //aux ID for AXI compatibility - stage1_we <= i_wb_we; //write-enable - stage1_dm <= i_wb_sel; //byte selection - stage1_col <= { i_wb_addr[(COL_BITS- $clog2(wb_data_bits/8)-1):0], {{$clog2(wb_data_bits/8)}{1'b0}} }; //column address (n-burst word-aligned) - stage1_bank <= i_wb_addr[(BA_BITS + COL_BITS- $clog2(wb_data_bits/8) - 1) : (COL_BITS- $clog2(wb_data_bits/8))]; //bank_address - stage1_row <= i_wb_addr[ (ROW_BITS + BA_BITS + COL_BITS- $clog2(wb_data_bits/8) - 1) : (BA_BITS + COL_BITS- $clog2(wb_data_bits/8)) ]; //row_address - //stage1_next_bank will not increment unless stage1_next_col - //overwraps due to MARGIN_BEFORE_ANTICIPATE. Thus, anticipated - //precharge and activate will happen only at the end of the - //current column with a margin dictated by - //MARGIN_BEFORE_ANTICIPATE - /* verilator lint_off WIDTH */ - {stage1_next_row , stage1_next_bank} <= wb_addr_plus_anticipate[(ROW_BITS + BA_BITS + COL_BITS- $clog2(wb_data_bits/8) - 1) : (COL_BITS- $clog2(wb_data_bits/8))]; - //anticipated next row and bank to be accessed - /* verilator lint_on WIDTH */ - stage1_data <= i_wb_data; - end - else if(state_calibrate != DONE_CALIBRATE) begin - stage1_pending <= write_calib_stb;//actual request flag - stage1_we <= write_calib_we; //write-enable - stage1_dm <= 0; - stage1_aux <= write_calib_aux; //aux ID for AXI compatibility - stage1_col <= write_calib_col; //column address (n-burst word-aligned) - stage1_bank <= 0; //bank_address - stage1_row <= 0; //row_address - {stage1_next_row , stage1_next_bank} <= 0; //anticipated next row and bank to be accessed - stage1_data <= write_calib_data; - end - - for(index = 0; index < LANES; index = index + 1) begin - /* verilator lint_off WIDTH */ - {unaligned_data[index], { - stage2_data[0][((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*6 + 8*index) +: 8], - stage2_data[0][((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*4 + 8*index) +: 8], - stage2_data[0][((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*2 + 8*index) +: 8], - stage2_data[0][((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*0 + 8*index) +: 8] }} - <= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8], - stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8], - stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8], - stage2_data_unaligned[((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*0 + 8*index) +: 8] } - << data_start_index[index]) | unaligned_data[index]; - - {unaligned_dm[index], { - stage2_dm[0][LANES*7 + index], stage2_dm[0][LANES*6 + index], - stage2_dm[0][LANES*5 + index], stage2_dm[0][LANES*4 + index], - stage2_dm[0][LANES*3 + index], stage2_dm[0][LANES*2 + index], - stage2_dm[0][LANES*1 + index], stage2_dm[0][LANES*0 + index] }} - <= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index], - stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index], - stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index], - stage2_dm_unaligned[LANES*1 + index], stage2_dm_unaligned[LANES*0 + index] } - << (data_start_index[index]>>3)) | unaligned_dm[index]; - /* verilator lint_on WIDTH */ - end - for(index = 0; index < STAGE2_DATA_DEPTH-1; index = index+1) begin - stage2_data[index+1] <= stage2_data[index]; - stage2_dm[index+1] <= stage2_dm[index]; - end - - //abort any outgoing ack when cyc is low - if(!i_wb_cyc && state_calibrate == DONE_CALIBRATE) begin - stage2_pending <= 0; - stage1_pending <= 0; - end - end - end - assign o_phy_data = stage2_data[STAGE2_DATA_DEPTH-1]; - assign o_phy_dm = stage2_dm[STAGE2_DATA_DEPTH-1]; - /* verilator lint_off WIDTH */ - assign wb_addr_plus_anticipate = i_wb_addr + MARGIN_BEFORE_ANTICIPATE; - /* verilator lint_on WIDTH */ - // DIAGRAM FOR ALL RELEVANT TIMING PARAMETERS: - // - // tRTP - // ------------------------------------------------------------- - // | tCCD | - // | -----> Read ---------> Read - // v | ^ | - // Precharge ------> Activate -------->| | tWTR | tRTW - // ^ tRP tRCD | | v - // | ------> Write -------> Write - // | tCCD | - // ------------------------------------------------------------- - // tWR (after data burst) - //note: all delays after write counts only after the data burst (except for write-to-write tCCD) - // - //Pipeline Stages: - // wishbone inputs --> stage1 --> stage2 --> cmd - always @* begin - cmd_odt = cmd_odt_q || write_calib_odt; - cmd_ck_en = instruction[CLOCK_EN]; - cmd_reset_n = instruction[RESET_N]; - stage1_stall = 1'b0; - stage2_stall = 1'b0; - stage2_update = 1'b1; //always update stage 2 UNLESS it has a pending request (stage2_pending high) - o_wb_stall_d = 1'b0; //wb_stall going high is determined on stage 1 (higher priority), wb_stall going low is determined at stage2 (lower priority) - precharge_slot_busy = 0; //flag that determines if stage 2 is issuing precharge (thus stage 1 cannot issue precharge) - activate_slot_busy = 0; //flag that determines if stage 2 is issuing activate (thus stage 1 cannot issue activate) - write_dqs_d = write_calib_dqs; - write_dq_d = write_calib_dq; - for(index=0; index < (1<> 1); - end - if(shift_reg_read_pipe_q[1][0]) begin //delay is over and data is now starting to release from iserdes BUT NOT YET ALIGNED - index_read_pipe <= !index_read_pipe; //control which delay_read_pipe would get updated (we have 3 pipe to store read data)ss - delay_read_pipe[index_read_pipe][added_read_pipe_max] <= 1'b1; //update delay_read_pipe - end - for(index = 0; index < LANES; index = index + 1) begin - /* verilator lint_off WIDTH */ - if(delay_read_pipe[0][added_read_pipe_max != added_read_pipe[index]]) begin //same lane - /* verilator lint_on WIDTH */ - o_wb_data_q[0][((DQ_BITS*LANES)*0 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*0 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*1 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*1 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*2 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*2 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*3 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*3 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*4 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*4 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*5 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*5 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*6 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*6 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*7 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*7 + 8*index) +: 8]; //update each lane of the burst - end - /* verilator lint_off WIDTH */ - if(delay_read_pipe[1][added_read_pipe_max != added_read_pipe[index]]) begin - /* verilator lint_on WIDTH */ - o_wb_data_q[1][((DQ_BITS*LANES)*0 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*0 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*1 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*1 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*2 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*2 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*3 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*3 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*4 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*4 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*5 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*5 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*6 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*6 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*7 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*7 + 8*index) +: 8]; //update each lane of the burst - end - end - if(o_wb_ack_read_q[0][0]) begin - index_wb_data <= !index_wb_data; - end - for(index = 1; index < MAX_ADDED_READ_ACK_DELAY; index = index + 1) begin - o_wb_ack_read_q[index-1] <= o_wb_ack_read_q[index]; - end - o_wb_ack_read_q[MAX_ADDED_READ_ACK_DELAY-1] <= 0; - o_wb_ack_read_q[added_read_pipe_max] <= shift_reg_read_pipe_q[0]; - - //abort any outgoing ack when cyc is low - if(!i_wb_cyc && state_calibrate == DONE_CALIBRATE) begin - for(index = 0; index < MAX_ADDED_READ_ACK_DELAY; index = index + 1) begin - o_wb_ack_read_q[index] <= 0; - end - for(index = 0; index < READ_ACK_PIPE_WIDTH; index = index + 1) begin - shift_reg_read_pipe_q[index] <= 0; - end - end - end - end - assign o_wb_ack = o_wb_ack_read_q[0][0] && state_calibrate == DONE_CALIBRATE; - //o_wb_ack_read_q[0][0] is needed internally for write calibration but it must not go outside (since it is not an actual user wb request unless we are in DONE_CALIBRATE) - assign o_aux = o_wb_ack_read_q[0][AUX_WIDTH:1]; - assign o_wb_data = o_wb_data_q[index_wb_data]; - assign o_phy_dqs_tri_control = !write_dqs[STAGE2_DATA_DEPTH]; - assign o_phy_dq_tri_control = !write_dq[STAGE2_DATA_DEPTH+1]; - generate - if(STAGE2_DATA_DEPTH - 2 >= 0) - assign o_phy_toggle_dqs = write_dqs_val[STAGE2_DATA_DEPTH-2]; - else - assign o_phy_toggle_dqs = write_dqs_d || write_dqs_q[0]; - endgenerate - /*********************************************************************************************************************************************/ - - - /******************************************************* Read/Write Calibration Sequence *******************************************************/ - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - state_calibrate <= IDLE; - train_delay <= 0; - dqs_store <= 0; - dqs_count_repeat <= 0; - dqs_start_index <= 0; - dqs_target_index <= 0; - dqs_target_index_orig <= 0; - o_phy_bitslip <= 0; - o_phy_odelay_data_ld <= 0; - o_phy_odelay_dqs_ld <= 0; - o_phy_idelay_data_ld <= 0; - o_phy_idelay_dqs_ld <= 0; - lane_times_8 <= 0; - idelay_data_cntvaluein_prev <= 0; - initial_dqs <= 1; - lane <= 0; - dqs_bitslip_arrangement <= 0; - write_calib_dqs <= 0; - write_calib_dq <= 0; - write_calib_odt <= 0; - prev_write_level_feedback <= 1; - write_calib_stb <= 0;//actual request flag - write_calib_aux <= 0; //AUX ID - write_calib_we <= 0; //write-enable - write_calib_col <= 0; - write_calib_data <= 0; - pause_counter <= 0; - read_data_store <= 0; - write_pattern <= 0; - added_read_pipe_max <= 0; - dqs_start_index_stored <= 0; - dqs_start_index_repeat <= 0; - dq_target_index <= 0; - delay_before_write_level_feedback <= 0; - delay_before_read_data <= 0; - for(index = 0; index < LANES; index = index + 1) begin - added_read_pipe[index] <= 0; - data_start_index[index] <= 0; - odelay_data_cntvaluein[index] <= DATA_INITIAL_ODELAY_TAP[4:0]; - odelay_dqs_cntvaluein[index] <= DQS_INITIAL_ODELAY_TAP[4:0]; - idelay_data_cntvaluein[index] <= DATA_INITIAL_IDELAY_TAP[4:0]; - idelay_dqs_cntvaluein[index] <= DQS_INITIAL_IDELAY_TAP[4:0]; - end - end - else begin - write_calib_stb <= 0;//actual request flag - write_calib_aux <= 0; //AUX ID - write_calib_we <= 0; //write-enable - write_calib_col <= 0; - write_calib_data <= 0; - write_calib_dqs <= 0; - write_calib_dq <= 0; - train_delay <= (train_delay==0)? 0:(train_delay - 1); - delay_before_read_data <= (delay_before_read_data == 0)? 0: delay_before_read_data - 1; - delay_before_write_level_feedback <= (delay_before_write_level_feedback == 0)? 0: delay_before_write_level_feedback - 1; - o_phy_bitslip <= 0; - o_phy_odelay_data_ld <= 0; - o_phy_odelay_dqs_ld <= 0; - o_phy_idelay_data_ld <= 0; - o_phy_idelay_dqs_ld <= 0; - /* verilator lint_off WIDTH */ - lane_times_8 <= lane << 3; - /* verilator lint_on WIDTH */ - idelay_data_cntvaluein_prev <= idelay_data_cntvaluein[lane]; - - if(wb2_update) begin - odelay_data_cntvaluein[wb2_write_lane] <= wb2_phy_odelay_data_ld[wb2_write_lane]? wb2_phy_odelay_data_cntvaluein : odelay_data_cntvaluein[wb2_write_lane]; - odelay_dqs_cntvaluein[wb2_write_lane] <= wb2_phy_odelay_dqs_ld[wb2_write_lane]? wb2_phy_odelay_dqs_cntvaluein : odelay_dqs_cntvaluein[wb2_write_lane]; - idelay_data_cntvaluein[wb2_write_lane] <= wb2_phy_idelay_data_ld[wb2_write_lane]? wb2_phy_idelay_data_cntvaluein : idelay_data_cntvaluein[wb2_write_lane]; - idelay_dqs_cntvaluein[wb2_write_lane] <= wb2_phy_idelay_dqs_ld[wb2_write_lane]? wb2_phy_idelay_dqs_cntvaluein : idelay_dqs_cntvaluein[wb2_write_lane]; - o_phy_odelay_data_ld <= wb2_phy_odelay_data_ld; - o_phy_odelay_dqs_ld <= wb2_phy_odelay_dqs_ld; - o_phy_idelay_data_ld <= wb2_phy_idelay_data_ld; - o_phy_idelay_dqs_ld <= wb2_phy_idelay_dqs_ld; - lane <= wb2_write_lane; - end - else if(state_calibrate != DONE_CALIBRATE) begin - // increase cntvalue every load to prepare for possible next load - odelay_data_cntvaluein[lane] <= o_phy_odelay_data_ld[lane]? odelay_data_cntvaluein[lane] + 1: odelay_data_cntvaluein[lane]; - odelay_dqs_cntvaluein[lane] <= o_phy_odelay_dqs_ld[lane]? odelay_dqs_cntvaluein[lane] + 1: odelay_dqs_cntvaluein[lane]; - idelay_data_cntvaluein[lane] <= o_phy_idelay_data_ld[lane]? idelay_data_cntvaluein[lane] + 1: idelay_data_cntvaluein[lane]; - idelay_dqs_cntvaluein[lane] <= o_phy_idelay_dqs_ld[lane]? idelay_dqs_cntvaluein[lane] + 1: idelay_dqs_cntvaluein[lane]; - end - if(initial_dqs) begin - dqs_target_index <= dqs_target_index_value; - dq_target_index <= dqs_target_index_value; - dqs_target_index_orig <= dqs_target_index_value; - end - if(idelay_dqs_cntvaluein[lane] == 0) begin //go back to previous odd - dqs_target_index <= dqs_target_index_orig - 2; - end - if(idelay_data_cntvaluein[lane] == 0 && idelay_data_cntvaluein_prev == 31) begin - dq_target_index <= dqs_target_index_orig - 2; - end - - // FSM - case(state_calibrate) - IDLE: if(i_phy_idelayctrl_rdy && instruction_address == 13) begin //we are now inside instruction 15 with maximum delay - state_calibrate <= BITSLIP_DQS_TRAIN_1; - lane <= 0; - o_phy_odelay_data_ld <= {LANES{1'b1}}; - o_phy_odelay_dqs_ld <= {LANES{1'b1}}; - o_phy_idelay_data_ld <= {LANES{1'b1}}; - o_phy_idelay_dqs_ld <= {LANES{1'b1}}; - pause_counter <= 1; //pause instruction address @13 until read calibration finishes - end - else if(instruction_address == 13) begin - pause_counter <= 1; //pause instruction address @13 until read calibration finishes - end - BITSLIP_DQS_TRAIN_1: if(train_delay == 0) begin - /* Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip must be - deasserted for at least one CLKDIV cycle between two Bitslip assertions.The user - logic should wait for at least two CLKDIV cycles in SDR mode or three CLKDIV cycles - in DDR mode, before analyzing the received data pattern and potentially issuing - another Bitslip command. If the ISERDESE2 is reset, the Bitslip logic is also reset - and returns back to its initial state. - */ - if(i_phy_iserdes_bitslip_reference[lane*LANES +: 8] == 8'b0111_1000) begin //initial arrangement - state_calibrate <= MPR_READ; - initial_dqs <= 1; - dqs_start_index_repeat <= 0; - dqs_start_index_stored <= 0; - end - else begin - o_phy_bitslip[lane] <= 1; - train_delay <= 3; - end - end - - MPR_READ: begin //align the incoming DQS during reads to the controller clock - //issue_read_command = 1; - /* verilator lint_off WIDTH */ - delay_before_read_data <= READ_DELAY + 1 + 2 + 1; ///1=issue command delay (OSERDES delay), 2 = ISERDES delay - /* verilator lint_on WIDTH */ - state_calibrate <= COLLECT_DQS; - dqs_count_repeat <= 0; - end - - COLLECT_DQS: if(delay_before_read_data == 0) begin - dqs_store <= {i_phy_iserdes_dqs[LANES*lane +: 8], dqs_store[(STORED_DQS_SIZE*8-1):8]}; - dqs_count_repeat <= dqs_count_repeat + 1; - if(dqs_count_repeat == STORED_DQS_SIZE - 1) begin - state_calibrate <= ANALYZE_DQS; - dqs_start_index_stored <= dqs_start_index; - dqs_start_index <= 0; - end - end - - ANALYZE_DQS: if(dqs_store[dqs_start_index +: 10] == 10'b01_01_01_01_00) begin - dqs_start_index_repeat <= (dqs_start_index == dqs_start_index_stored)? dqs_start_index_repeat + 1: 0; //increase dqs_start_index_repeat when index is the same as before - if(dqs_start_index_repeat == REPEAT_DQS_ANALYZE) begin //the same index appeared REPEAT_DQS_ANALYZE times in a row, thus can proceed to CALIBRATE_DQS - initial_dqs <= 0; - dqs_start_index_repeat <= 0; - - state_calibrate <= CALIBRATE_DQS; - end - else begin - state_calibrate <= MPR_READ; - end - end - else begin - dqs_start_index <= dqs_start_index + 1; - end - - CALIBRATE_DQS: if(dqs_start_index_stored == dqs_target_index) begin - added_read_pipe[lane] <= dq_target_index[$clog2(STORED_DQS_SIZE*8)-1:3] + { {($clog2(STORED_DQS_SIZE*8)-3){1'b0}} , (dq_target_index[2:0] >= 5)}; - dqs_bitslip_arrangement <= 16'b0011_1100_0011_1100 >> dq_target_index[2:0]; - state_calibrate <= BITSLIP_DQS_TRAIN_2; - end - else begin - o_phy_idelay_data_ld[lane] <= 1; - o_phy_idelay_dqs_ld[lane] <= 1; - state_calibrate <= MPR_READ; - end - - BITSLIP_DQS_TRAIN_2: if(train_delay == 0) begin //train again the ISERDES to capture the DQ correctly - if(i_phy_iserdes_bitslip_reference[lane*LANES +: 8] == dqs_bitslip_arrangement[7:0]) begin - /* verilator lint_off WIDTH */ - if(lane == LANES - 1) begin - /* verilator lint_on WIDTH */ - pause_counter <= 0; //read calibration now complete so continue the reset instruction sequence - lane <= 0; - prev_write_level_feedback <= 1'b1; - state_calibrate <= START_WRITE_LEVEL; - end - else begin - lane <= lane + 1; - state_calibrate <= BITSLIP_DQS_TRAIN_1; - end - added_read_pipe_max <= added_read_pipe_max > added_read_pipe[lane]? added_read_pipe_max:added_read_pipe[lane]; - end - else begin - o_phy_bitslip[lane] <= 1; - train_delay <= 3; - end - end - - START_WRITE_LEVEL: if(instruction_address == 17) begin - write_calib_dqs <= 1'b1; - write_calib_odt <= 1'b1; - delay_before_write_level_feedback <= DELAY_BEFORE_WRITE_LEVEL_FEEDBACK[$clog2(DELAY_BEFORE_WRITE_LEVEL_FEEDBACK):0]; - state_calibrate <= WAIT_FOR_FEEDBACK; - pause_counter <= 1; // pause instruction address @17 until write calibration finishes - end - - WAIT_FOR_FEEDBACK: if(delay_before_write_level_feedback == 0) begin - /* verilator lint_off WIDTH */ //_verilator warning: Bit extraction of var[511:0] requires 9 bit index, not 3 bits (but [lane<<3] is much simpler and cleaner) - prev_write_level_feedback <= i_phy_iserdes_data[lane_times_8]; - if({prev_write_level_feedback, i_phy_iserdes_data[lane_times_8]} == 2'b01) begin - /* verilator lint_on WIDTH */ - /* verilator lint_off WIDTH */ - if(lane == LANES - 1) begin - /* verilator lint_on WIDTH */ - write_calib_odt <= 0; - pause_counter <= 0; //write calibration now complete so continue the reset instruction sequence - lane <= 0; - state_calibrate <= ISSUE_WRITE_1; - end - else begin - lane <= lane + 1; - prev_write_level_feedback <= 1'b1; - state_calibrate <= START_WRITE_LEVEL; - end - end - else begin - o_phy_odelay_data_ld[lane] <= 1; - o_phy_odelay_dqs_ld[lane] <= 1; - state_calibrate <= START_WRITE_LEVEL; - end - end - ISSUE_WRITE_1: if(instruction_address == 22 && !o_wb_stall_q) begin - write_calib_stb <= 1;//actual request flag - write_calib_aux <= 1; //AUX ID to determine later if ACK is for read or write - write_calib_we <= 1; //write-enable - write_calib_col <= 0; - write_calib_data <= { {LANES{8'h91}}, {LANES{8'h77}}, {LANES{8'h29}}, {LANES{8'h8c}}, {LANES{8'hd0}}, {LANES{8'had}}, {LANES{8'h51}}, {LANES{8'hc1}} }; - state_calibrate <= ISSUE_WRITE_2; - end - ISSUE_WRITE_2: begin - write_calib_stb <= 1;//actual request flag - write_calib_aux <= 1; //AUX ID to determine later if ACK is for read or write - write_calib_we <= 1; //write-enable - write_calib_col <= 8; - write_calib_data <= { {LANES{8'h80}}, {LANES{8'hdb}}, {LANES{8'hcf}}, {LANES{8'hd2}}, {LANES{8'h75}}, {LANES{8'hf1}}, {LANES{8'h2c}}, {LANES{8'h3d}} }; - state_calibrate <= ISSUE_READ; - end - ISSUE_READ: if(!o_wb_stall_q && write_calib_stb == 0) begin - write_calib_stb <= 1;//actual request flag - write_calib_aux <= 0; //AUX ID to determine later if ACK is for read or write - write_calib_we <= 0; //write-enable - state_calibrate <= READ_DATA; - end - - READ_DATA: if(o_wb_ack_read_q[0] == {{(AUX_WIDTH){1'b0}}, 1'b1}) begin //wait for the read ack (which has UAX ID of 0} - read_data_store <= o_wb_data; - state_calibrate <= ANALYZE_DATA; - data_start_index[lane] <= 0; - // Possible Patterns (strong autocorrel stat) - //0x80dbcfd275f12c3d - //0x9177298cd0ad51c1 - //0x01b79fa4ebe2587b - //0x22ee5319a15aa382 - write_pattern <= 128'h80dbcfd275f12c3d_9177298cd0ad51c1; - end - - //ANALYZE_DATA: if(write_pattern[data_start_index[lane] +: 64] == read_data_store[lane*DQ_BITS*8 +: DQ_BITS*8]) begin - ANALYZE_DATA: if(write_pattern[data_start_index[lane] +: 64] == {read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8], - read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8], - read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] }) begin - /* verilator lint_off WIDTH */ - if(lane == LANES - 1) begin - /* verilator lint_on WIDTH */ - state_calibrate <= DONE_CALIBRATE; - end - else begin - lane <= lane + 1; - data_start_index[lane+1] <= 0; - end - end - else begin - data_start_index[lane] <= data_start_index[lane] + 8; - end - DONE_CALIBRATE: begin - state_calibrate <= DONE_CALIBRATE; - if(instruction_address == 19) begin //pre-stall delay to finish all remaining requests - pause_counter <= 1; // pause instruction address until pre-stall delay before refresh sequence finishes - //skip to instruction address 20 (precharge all before refresh) when no pending requests anymore - //toggle it for 1 clk cycle only - if(!stage1_pending && !stage2_pending && o_wb_stall) begin - pause_counter <= 0; // pre-stall delay done since all remaining requests are completed - end - end - end - - endcase - `ifdef FORMAL_COVER - state_calibrate <= DONE_CALIBRATE; - `endif - end - end - assign issue_read_command = (state_calibrate == MPR_READ); - assign issue_write_command = 0; - assign o_phy_odelay_data_cntvaluein = odelay_data_cntvaluein[lane]; - assign o_phy_odelay_dqs_cntvaluein = odelay_dqs_cntvaluein[lane]; - assign o_phy_idelay_data_cntvaluein = idelay_data_cntvaluein[lane]; - assign o_phy_idelay_dqs_cntvaluein = idelay_dqs_cntvaluein[lane]; - assign dqs_target_index_value = dqs_start_index_stored[0]? dqs_start_index_stored + 2: dqs_start_index_stored + 1; - - /*********************************************************************************************************************************************/ - - - /******************************************************* Wishbone 2 (PHY) Interface *******************************************************/ - - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - wb2_stb <= 0; - wb2_we <= 0; //data to be written which must have high i_wb2_sel are: {LANE_NUMBER, CNTVALUEIN} - wb2_addr <= 0; - wb2_data <= 0; - wb2_sel <= 0; - end - else begin - if(i_wb2_cyc && !o_wb2_stall) begin - wb2_stb <= i_wb2_stb; - wb2_we <= i_wb2_we; //data to be written which must have high i_wb2_sel are: {LANE_NUMBER, CNTVALUEIN} - wb2_addr <= i_wb2_addr; - wb2_data <= i_wb2_data; - wb2_sel <= i_wb2_sel; - end - else if(!o_wb2_stall) begin - wb2_stb <= 0; - wb2_we <= 0; - wb2_addr <= 0; - wb2_data <= 0; - wb2_sel <= 0; - end - end - end - - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - wb2_phy_odelay_data_cntvaluein <= 0; - wb2_phy_odelay_data_ld <= 0; - wb2_phy_odelay_dqs_cntvaluein <= 0; - wb2_phy_odelay_dqs_ld <= 0; - wb2_phy_idelay_data_cntvaluein <= 0; - wb2_phy_idelay_data_ld <= 0; - wb2_phy_idelay_dqs_cntvaluein <= 0; - wb2_phy_idelay_dqs_ld <= 0; - wb2_update <= 0; - wb2_write_lane <= 0; - o_wb2_ack <= 0; - o_wb2_stall <= 1; - o_wb2_data <= 0; - end - else begin - wb2_phy_odelay_data_ld <= 0; - wb2_phy_odelay_dqs_ld <= 0; - wb2_phy_idelay_data_ld <= 0; - wb2_phy_idelay_dqs_ld <= 0; - wb2_update <= 0; - wb2_write_lane <= 0; - o_wb2_ack <= wb2_stb && i_wb2_cyc; //always ack right after request - o_wb2_stall <= 0; //never stall - if(wb2_stb && i_wb2_cyc) begin - case(wb2_addr[3:0]) - //read/write odelay cntvalue for DQ line - 0: if(wb2_we) begin - wb2_phy_odelay_data_cntvaluein <= wb2_data[4:0]; //save first 5 bits as CNTVALUEIN for the ODELAYE2 for DQ - wb2_phy_odelay_data_ld <= 1 << (wb2_data[5 +: $clog2(LANES)]); //raise the lane to be loaded with new cntvaluein - wb2_update <= wb2_sel[$rtoi($ceil( ($clog2(LANES) + 5)/8 )) - 1:0]; //only update when sel bit is high (data is valid) - end - else begin - o_wb2_data <= { {(WB2_DATA_BITS-5){1'b0}} , odelay_data_cntvaluein[wb2_addr[4 +: $clog2(LANES)]] };//use next bits of address as lane number to be read - end - - //read/write odelay cntvalue for DQS line - 1: if(wb2_we) begin - wb2_phy_odelay_dqs_cntvaluein <= wb2_data[4:0]; //save first 5 bits as CNTVALUEIN for the ODELAYE2 for DQS - wb2_phy_odelay_dqs_ld <= 1 << (wb2_data[5 +: $clog2(LANES)]); //raise the lane to be loaded with new cntvaluein - wb2_update <= wb2_sel[$rtoi($ceil( ($clog2(LANES) + 5)/8 )) - 1:0]; //only update when sel bit is high (data is valid) - end - else begin - o_wb2_data <= { {(WB2_DATA_BITS-5){1'b0}} , odelay_dqs_cntvaluein[wb2_addr[4 +: $clog2(LANES)]] };//use next bits of address as lane number to be read - end - - //read/write idelay cntvalue for DQ line - 2: if(wb2_we) begin - wb2_phy_idelay_data_cntvaluein <= wb2_data[4:0]; //save first 5 bits as CNTVALUEIN for the IDELAYE2 for DQ - wb2_phy_idelay_data_ld <= 1 << (wb2_data[5 +: $clog2(LANES)]); //save next 5 bits for lane number to be loaded with new delay - wb2_update <= wb2_sel[$rtoi($ceil( ($clog2(LANES) + 5)/8 )) - 1:0]; //only update when sel bit is high (data is valid) - end - else begin - o_wb2_data <= { {(WB2_DATA_BITS-5){1'b0}} , idelay_data_cntvaluein[wb2_addr[4 +: $clog2(LANES)]] }; //use next bits of address as lane number to be read - end - - //read/write idelay cntvalue for DQS line - 3: if(wb2_we) begin - wb2_phy_idelay_dqs_cntvaluein <= wb2_data[4:0]; //save first 5 bits as CNTVALUEIN for the IDELAYE2 for DQS - wb2_phy_idelay_dqs_ld <= 1 << (wb2_data[5 +: $clog2(LANES)]); //save next 5 bits for lane number to be loaded with new delay - wb2_update <= wb2_sel[$rtoi($ceil( ($clog2(LANES) + 5)/8 )) - 1:0]; //only update when sel bit is high (data is valid) - end - else begin - o_wb2_data <= { {(WB2_DATA_BITS-5){1'b0}} , idelay_dqs_cntvaluein[wb2_addr[4 +: $clog2(LANES)]] }; //use next bits of address as lane number to be read - end - - 4: if(!wb2_we) begin - o_wb2_data[0] <= i_phy_idelayctrl_rdy; //1 bit, should be high when IDELAYE2 is ready - o_wb2_data[1 +: 5] <= state_calibrate; //5 bits, FSM state of the calibration sequence - o_wb2_data[1 + 5 +: 5] <= instruction_address; //5 bits, address of the reset sequence - o_wb2_data[1 + 5 + 5 +: 4] <= added_read_pipe_max; //4 bit, max added read delay (must have a max value of 1) - end - - 5: if(!wb2_we) begin - o_wb2_data <= {added_read_pipe[7], added_read_pipe[6], added_read_pipe[5], added_read_pipe[4], - added_read_pipe[3], added_read_pipe[2], added_read_pipe[1], added_read_pipe[0]}; - //added read pipe delay for lanes 0-to-3 (4 bits each lane the max is just 1 for each) - end - - 6: if(!wb2_we) begin - o_wb2_data <= dqs_store[31:0]; //show last 4 sets of received 8-bit DQS during MPR (repeated 4 times, must have a value of 10'b01_01_01_01_00 somewhere) - end - - 7: if(!wb2_we) begin - o_wb2_data <= i_phy_iserdes_bitslip_reference[31:0]; //show the 8-bit bitslip reference for lanes 0[7:0], 1[15:8], 2[23:16], 3[31:24] - end - - 8: if(!wb2_we) begin - o_wb2_data <= read_data_store[31:0]; //first 32 bits of the data read after first write using the write_pattern 128'h80dbcfd275f12c3d_9177298cd0ad51c1 - end - - 9: if(!wb2_we) begin - o_wb2_data <= write_pattern[31:0]; //first 32 bit of the patern written on the first write just for checking (128'h80dbcfd275f12c3d_9177298cd0ad51c1) - end - - default: if(!wb2_we) begin //read - o_wb2_data <= {(WB2_DATA_BITS/2){2'b10}}; //return alternating 1s and 0s when address to be read is invalid - end - endcase - - wb2_write_lane <= wb2_data[5 +: $clog2(LANES)]; //save next 5 bits for lane number to be loaded with new delay - end //end of if(wb2_stb) - end//end of else - end//end of always - - /*********************************************************************************************************************************************/ - - - /******************************************************* Functions *******************************************************/ - //convert nanoseconds time input to number of controller clock cycles (referenced to CONTROLLER_CLK_PERIOD) - //output is set at same length as a MRS command (19 bits) to maximize the time slot - function [DELAY_SLOT_WIDTH - 1:0] ns_to_cycles ( -`ifdef YOSYS - input integer ns -`else - input real ns //YOSYS ERROR: syntax error, unexpected TOK_REAL -`endif - ); - integer result; - begin - result = $rtoi($ceil(ns*1.0/CONTROLLER_CLK_PERIOD)); - ns_to_cycles = result[DELAY_SLOT_WIDTH - 1:0]; - end - endfunction - - //convert nCK input (number of DDR3 clock cycles) to number of controller clock cycles (referenced to serdes_ratio) - function [DELAY_SLOT_WIDTH - 1:0] nCK_to_cycles (input integer nCK); - integer result; - begin - result = $rtoi($ceil(nCK*1.0/serdes_ratio)); - nCK_to_cycles = result[DELAY_SLOT_WIDTH - 1:0]; - end - endfunction - - - //convert nanoseconds time input to number of DDR clock cycles (referenced to DDR3_CLK_PERIOD) - function integer ns_to_nCK ( -`ifdef YOSYS - input integer ns -`else - input real ns //YOSYS ERROR: syntax error, unexpected TOK_REAL -`endif - ); begin - ns_to_nCK = $rtoi($ceil(ns*1.0/DDR3_CLK_PERIOD)); - end - endfunction - - //convert DDR clock cycles to nanoseconds (referenced to DDR3_CLK_PERIOD) -`ifdef YOSYS - function integer nCK_to_ns (input integer nCK); - nCK_to_ns = $rtoi($ceil(nCK*1.0*DDR3_CLK_PERIOD)); -`else - function real nCK_to_ns (input integer nCK); //YOSYS ERROR: syntax error, unexpected TOK_REAL - nCK_to_ns = $ceil(nCK*1.0*DDR3_CLK_PERIOD); -`endif - endfunction - - // functions used to infer some localparam values -`ifdef YOSYS - function integer max(input integer a, input integer b); -`else - function real max(input real a, input real b); //YOSYS ERROR: syntax error, unexpected TOK_REAL -`endif - if(a >= b) max = a; - else max = b; - endfunction - - //Find the 3-bit value for the Mode Register 0 WR (Write recovery for auto-precharge) - function[2:0] WRA_mode_register_value(input integer WRA); - //WR_min (write recovery for autoprecharge) in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer. - //The WR value in the mode register must be programmed to be equal or larger than WRmin. - case(WRA+1) - 1,2,3,4,5: WRA_mode_register_value = 3'b001; - 6: WRA_mode_register_value = 3'b010; - 7: WRA_mode_register_value = 3'b011; - 8: WRA_mode_register_value = 3'b100; - 9,10: WRA_mode_register_value = 3'b101; - 11,12: WRA_mode_register_value = 3'b110; - 13,14: WRA_mode_register_value = 3'b111; - 15,16: WRA_mode_register_value = 3'b000; - default: begin - WRA_mode_register_value = 3'b000; //defaulting to largest write recovery cycles: 16 cycles - end - endcase - endfunction - - function[1:0] get_slot (input[3:0] cmd); //cmd can either be CMD_PRE,CMD_ACT, CMD_WR, CMD_RD - integer delay; - reg[1:0] slot_number, read_slot, write_slot, anticipate_activate_slot, anticipate_precharge_slot; - begin - // find read command slot number - delay = CL_nCK; - for(slot_number = 0 ; delay != 0 ; delay = delay - 1) begin - slot_number = slot_number - 1'b1; - end - read_slot = slot_number; - - // find write command slot number - delay = CWL_nCK; - for(slot_number = 0 ; delay != 0; delay = delay - 1) begin - slot_number = slot_number - 1'b1; - end - write_slot = slot_number; - - // find anticipate activate command slot number - if(CL_nCK > CWL_nCK) slot_number = read_slot; - else slot_number = write_slot; - `ifdef SUPPORT_REAL - delay = ns_to_nCK(tRCD); - `else - delay = ns_to_nCK($rtoi(tRCD)); - `endif - for(slot_number = slot_number; delay != 0; delay = delay - 1) begin - slot_number = slot_number - 1'b1; - end - anticipate_activate_slot = slot_number; - // if computed anticipate_activate_slot is same with either write_slot or read_slot, decrement slot number until - while(anticipate_activate_slot == write_slot || anticipate_activate_slot == read_slot) begin - anticipate_activate_slot = anticipate_activate_slot - 1'b1; - end - - //the remaining slot will be for precharge command - anticipate_precharge_slot = 0; - while(anticipate_precharge_slot == write_slot || anticipate_precharge_slot == read_slot || anticipate_precharge_slot == anticipate_activate_slot) begin - anticipate_precharge_slot = anticipate_precharge_slot - 1'b1; - end - case(cmd) - CMD_RD: get_slot = read_slot; - CMD_WR: get_slot = write_slot; - CMD_ACT: get_slot = anticipate_activate_slot; - CMD_PRE: get_slot = anticipate_precharge_slot; - default: begin - `ifdef FORMAL - assert(0); //force FORMAL to fail if this is ever reached - `endif - end - endcase - end - endfunction - - //find the delay to be used by delay_before_xxxx_counter. - // - delay_nCK = delay required between the two commands in DDR3 clock cycles - // - start_slot = slot number of the first command - // - end_slot = slot number of the second command - // returns the number of controller clock cycles to satisfy the delay required between the two commands - function [3:0] find_delay(input integer delay_nCK, input reg[1:0] start_slot, input reg[1:0] end_slot); - integer k; //error: variable declaration assignments are only allowed at the module level - begin - k = 0; - /* verilator lint_off WIDTH */ - while( ((4 - start_slot) + end_slot + 4*k) < delay_nCK) begin - /* verilator lint_on WIDTH */ - k = k + 1; - end - find_delay = k[3:0]; - end - endfunction - /*********************************************************************************************************************************************/ - - -`ifndef YOSYS - ///YOSYS: System task `$display' called with invalid/unsupported format specifier - initial begin - $display("TEST FUNCTIONS\n-----------------------------\n"); - $display("Test ns_to_cycles() function:"); - $display("\tns_to_cycles(15) = %0d [exact]", ns_to_cycles(15) ); - $display("\tns_to_cycles(14.5) = %0d [round-off]", ns_to_cycles(14.5) ); - $display("\tns_to_cycles(11) = %0d [round-up]\n", ns_to_cycles(11) ); - - $display("Test nCK_to_cycles() function:"); - $display("\tns_to_cycles(16) = %0d [exact]", nCK_to_cycles(16) ); - $display("\tns_to_cycles(15) = %0d [round-off]", nCK_to_cycles(15) ); - $display("\tns_to_cycles(13) = %0d [round-up]\n", nCK_to_cycles(13) ); - - $display("Test ns_to_nCK() function:"); - $display("\tns_to_cycles(15) = %0d [exact]", ns_to_nCK(15) ); - $display("\tns_to_cycles(14.875) = %0d [round-off]", ns_to_nCK(14.875) ); - $display("\tns_to_cycles(13.875) = %0d [round-up] \n", ns_to_nCK(13.875) ); - - $display("Test nCK_to_ns() function:"); - $display("\tns_to_cycles(4) = %f [exact]", nCK_to_ns(4) ); - $display("\tns_to_cycles(14.875) = %f [round-off]", nCK_to_ns(3) ); - $display("\tns_to_cycles(13.875) = %f [round-up]\n", nCK_to_ns(5) ); - - $display("Test nCK_to_ns() function:"); - $display("\tns_to_cycles(4) = %f [exact]", nCK_to_ns(4) ); - $display("\tns_to_cycles(14.875) = %f [round-off]", nCK_to_ns(3) ); - $display("\tns_to_cycles(13.875) = %f [round-up]\n", nCK_to_ns(5) ); - - $display("Test $floor() function:"); - $display("\t$floor(5/2) = %f", $floor(5/2) ); - $display("\t$floor(9/4) = %f", $floor(9/4) ); - $display("\t$floor(9/4) = %f", $floor(8/4) ); - $display("\t$floor(9/5) = %f\n", $floor(9/5) ); - - $display("\nDISPLAY CONTROLLER PARAMETERS\n-----------------------------\n"); - $display("CONTROLLER_CLK_PERIOD = %.2f", CONTROLLER_CLK_PERIOD); - $display("DDR3_CLK_PERIOD = %.2f", DDR3_CLK_PERIOD); - $display("ROW_BITS = %0d", ROW_BITS); - $display("COL_BITS = %0d", COL_BITS); - $display("BA_BITS = %0d", BA_BITS); - $display("DQ_BITS = %0d", DQ_BITS); - $display("LANES = %0d", LANES); - $display("AUX_WIDTH = %0d", AUX_WIDTH); - $display("WB2_ADDR_BITS = %0d", WB2_ADDR_BITS); - $display("WB2_DATA_BITS = %0d", WB2_DATA_BITS); - - $display("serdes_ratio = %0d", serdes_ratio); - $display("wb_addr_bits = %0d", wb_addr_bits); - $display("wb_data_bits = %0d", wb_data_bits); - $display("wb_sel_bits = %0d", wb_sel_bits); - $display("wb2_sel_bits = %0d", wb2_sel_bits); - $display("cmd_len = %0d", cmd_len ); - $display("DELAY_COUNTER_WIDTH = %0d", DELAY_COUNTER_WIDTH); - $display("DELAY_SLOT_WIDTH = %0d", DELAY_SLOT_WIDTH); - - //$display("$bits(instruction):%0d - $bits(CMD_MRS):%0d - $bits(MR0):%0d = 5 = %0d", $bits(instruction), $bits(CMD_MRS) , $bits(MR0), ($bits(instruction) - $bits(CMD_MRS) - $bits(MR0))); - $display("serdes_ratio = %0d",serdes_ratio); - $display("wb_addr_bits = %0d",wb_addr_bits); - $display("wb_data_bits = %0d",wb_data_bits); - $display("wb_sel_bits = %0d\n\n",wb_sel_bits); - - $display("READ_SLOT = %0d", READ_SLOT); - $display("WRITE_SLOT = %0d", WRITE_SLOT); - $display("ACTIVATE_SLOT = %0d", ACTIVATE_SLOT); - $display("PRECHARGE_SLOT = %0d", PRECHARGE_SLOT); - - $display("\n\nDELAYS:"); - $display("\tns_to_nCK(tRCD): %0d", ns_to_nCK(tRCD)); - $display("\tns_to_nCK(tRP): %0d", ns_to_nCK(tRP)); - $display("\tns_to_nCK(tRTP): %0d", ns_to_nCK(tRTP)); - $display("\ttCCD: %0d", tCCD); - $display("\t(CL_nCK + tCCD + 2 - CWL_nCK): %0d", (CL_nCK + tCCD + 2 - CWL_nCK)); - $display("\t(CWL_nCK + 4 + ns_to_nCK(tWR)): %0d", (CWL_nCK + 4 + ns_to_nCK(tWR))); - $display("\t(CWL_nCK + 4 + ns_to_nCK(tWTR)): %0d", (CWL_nCK + 4 + ns_to_nCK(tWTR))); - - $display("\n\nPRECHARGE_TO_ACTIVATE_DELAY = %0d", PRECHARGE_TO_ACTIVATE_DELAY); - $display("ACTIVATE_TO_WRITE_DELAY = %0d", ACTIVATE_TO_WRITE_DELAY); - $display("ACTIVATE_TO_READ_DELAY = %0d", ACTIVATE_TO_READ_DELAY); - $display("READ_TO_WRITE_DELAY = %0d", READ_TO_WRITE_DELAY); - $display("READ_TO_READ_DELAY = %0d", READ_TO_READ_DELAY); - $display("READ_TO_PRECHARGE_DELAY = %0d", READ_TO_PRECHARGE_DELAY); - $display("WRITE_TO_WRITE_DELAY = %0d", WRITE_TO_WRITE_DELAY); - $display("WRITE_TO_READ_DELAY = %0d", WRITE_TO_READ_DELAY); - $display("WRITE_TO_PRECHARGE_DELAY = %0d", WRITE_TO_PRECHARGE_DELAY); - $display("STAGE2_DATA_DEPTH = %0d", STAGE2_DATA_DEPTH); - $display("READ_ACK_PIPE_WIDTH = %0d", READ_ACK_PIPE_WIDTH); - end -`endif - - -`ifdef FORMAL - `define TEST_CONTROLLER_PIPELINE - - `ifdef FORMAL_COVER - initial assume(!i_rst_n); - reg[24:0] f_wb_inputs[31:0]; - reg[9:0] f_reset_counter = 0; - reg[4:0] f_index = 0; - reg f_past_valid = 0; - initial begin - /* - // Sequential read to row 0 then jump to row 2 - f_wb_inputs[0] = {1'b0, {14'd0,3'd1, 7'd0}}; //read - f_wb_inputs[1] = {1'b0, {14'd0,3'd1, 7'd1}}; //read on same bank (tCCD) - f_wb_inputs[2] = {1'b0, {14'd0,3'd1, 7'd2}}; //write on same bank (tRTW) - f_wb_inputs[3] = {1'b0, {14'd0,3'd1, 7'd3}}; //write on same bank (tCCD) - f_wb_inputs[4] = {1'b0, {14'd0,3'd1, 7'd4}}; //read on different bank - f_wb_inputs[5] = {1'b0, {14'd0,3'd1, 7'd5}}; //write on same bank (tRTW) - f_wb_inputs[6] = {1'b0, {14'd2,3'd1, 7'd6}}; //write on different bank (already activated) - f_wb_inputs[7] = {1'b0, {14'd2,3'd1, 7'd7}}; //write (tCCD) - f_wb_inputs[8] = {1'b0, {14'd2,3'd1, 7'd8}}; //write on different bank (already activated but wrong row) - f_wb_inputs[9] = {1'b0, {14'd2,3'd1, 7'd9}}; //write (tCCD) - f_wb_inputs[10] = {1'b0, {14'd3,3'd1, 7'd10}}; //write (tCCD) - f_wb_inputs[11] = {1'b0, {14'd3,3'd1, 7'd11}}; //read (same bank but wrong row so precharge first) - f_wb_inputs[12] = {1'b0, {14'd3,3'd1, 7'd12}}; //read (tCCD) - f_wb_inputs[13] = {1'b0, {14'd3,3'd1, 7'd13}}; //read (tCCD) - */ - - f_wb_inputs[0] = {1'b0, {14'd0,3'd1, 7'd0}}; //read - f_wb_inputs[1] = {1'b0, {14'd0,3'd1, 7'd1}}; //read on same bank (tCCD) - f_wb_inputs[2] = {1'b1, {14'd0,3'd1, 7'd2}}; //write on same bank (tRTW) - f_wb_inputs[3] = {1'b1, {14'd0,3'd1, 7'd3}}; //write on same bank (tCCD) - f_wb_inputs[4] = {1'b0, {14'd0,3'd2, 7'd0}}; //read on different bank - f_wb_inputs[5] = {1'b1, {14'd0,3'd2, 7'd1}}; //write on same bank (tRTW) - f_wb_inputs[6] = {1'b1, {14'd0,3'd1, 7'd4}}; //write on different bank (already activated) - f_wb_inputs[7] = {1'b1, {14'd0,3'd1, 7'd5}}; //write (tCCD) - f_wb_inputs[8] = {1'b1, {14'd1,3'd2, 7'd0}}; //write on different bank (already activated but wrong row) - f_wb_inputs[9] = {1'b1, {14'd1,3'd2, 7'd1}}; //write (tCCD) - f_wb_inputs[10] = {1'b1, {14'd1,3'd2, 7'd2}}; //write (tCCD) - f_wb_inputs[11] = {1'b0, {14'd2,3'd2, 7'd0}}; //read (same bank but wrong row so precharge first) - f_wb_inputs[12] = {1'b0, {14'd2,3'd2, 7'd1}}; //read (tCCD) - f_wb_inputs[13] = {1'b0, {14'd2,3'd2, 7'd2}}; //read (tCCD) - /* - f_wb_inputs[0] = {1'b0, {14'd0,3'd1, 7'd0}}; //read - f_wb_inputs[1] = {1'b0, {14'd0,3'd1, 7'd1}}; //read on same bank (tCCD) - f_wb_inputs[2] = {1'b1, {14'd0,3'd2, 7'd0}}; //write on the anticipated bank - f_wb_inputs[3] = {1'b1, {14'd0,3'd2, 7'd1}}; //write on same bank (tCCD) - f_wb_inputs[4] = {1'b0, {14'd0,3'd3, 7'd0}}; //read on the anticipated bank - f_wb_inputs[5] = {1'b0, {14'd0,3'd3, 7'd1}}; //read on same bank (tCCD) - f_wb_inputs[6] = {1'b1, {14'd0,3'd7, 7'd0}}; //write on the un-anticipated idle bank (activate first) - f_wb_inputs[7] = {1'b1, {14'd0,3'd1, 7'd1}}; //write on the un-anticipated active bank and row (write) - f_wb_inputs[8] = {1'b1, {14'd1,3'd7, 7'd0}}; //write on the un-anticipated active bank but wrong row (precharge first) - */ - /* - f_wb_inputs[0] = {1'b0, {14'd0,3'd1, 7'd0}}; //read - f_wb_inputs[1] = {1'b0, {14'd0,3'd1, 7'd1}}; //read - f_wb_inputs[2] = {1'b0, {14'd0,3'd1, 7'd2}}; //read - f_wb_inputs[3] = {1'b0, {14'd0,3'd1, 7'd3}}; //read - f_wb_inputs[4] = {1'b0, {14'd0,3'd1, 7'd4}}; //read - f_wb_inputs[5] = {1'b0, {14'd0,3'd1, 7'd5}}; //read - f_wb_inputs[6] = {1'b0, {14'd0,3'd1, 7'd6}}; //write - f_wb_inputs[7] = {1'b0, {14'd0,3'd1, 7'd7}}; //write - f_wb_inputs[8] = {1'b0, {14'd0,3'd1, 7'd8}}; //write - f_wb_inputs[9] = {1'b0, {14'd0,3'd1, 7'd9}}; //write - f_wb_inputs[10] = {1'b0, {14'd0,3'd1, 7'd10}}; //write - f_wb_inputs[11] = {1'b0, {14'd0,3'd1, 7'd11}}; //write - */ - /* - f_wb_inputs[0] = {1'b0, {14'd1,3'd1, 7'd120}}; //write on same bank (tRTW) - f_wb_inputs[1] = {1'b0, {14'd1,3'd1, 7'd121}}; //write on different bank (already activated) - f_wb_inputs[2] = {1'b0, {14'd1,3'd1, 7'd122}}; //write (tCCD) - f_wb_inputs[3] = {1'b0, {14'd1,3'd1, 7'd123}}; //write on different bank (already activated but wrong row) - f_wb_inputs[4] = {1'b0, {14'd1,3'd1, 7'd124}}; //write (tCCD) - f_wb_inputs[5] = {1'b0, {14'd1,3'd1, 7'd125}}; //write (tCCD) - f_wb_inputs[6] = {1'b0, {14'd1,3'd1, 7'd126}}; //read (same bank but wrong row so precharge first) - f_wb_inputs[7] = {1'b0, {14'd1,3'd1, 7'd127}}; //read (tCCD) - f_wb_inputs[8] = {1'b0, {14'd1,3'd2, 7'd0}}; //read (tCCD) - f_wb_inputs[9] = {1'b0, {14'd1,3'd2, 7'd1}}; //read (tCCD) - f_wb_inputs[10] = {1'b0, {14'd1,3'd2, 7'd2}}; //read (tCCD) - */ - end - initial begin - f_reset_counter = 0; - end - always @(posedge i_controller_clk) begin - if(!o_wb_stall) begin - f_index <= f_index + 1; //number of requests accepted - end - f_reset_counter <= f_reset_counter + 1; - end - - always @(posedge i_controller_clk) begin - assume(i_wb_cyc == 1); - assume(i_wb_stb == 1); - if(f_past_valid) begin - assume(i_rst_n); - end - assume(i_wb_we == f_wb_inputs[f_index][24]); - assume(i_wb_addr == f_wb_inputs[f_index][23:0]); - cover(f_index == 10); - if(f_index != 0) begin - assume(i_rst_n); //dont reset just to skip a request forcefully - end - end - `endif //endif for FORMAL_COVER - - - `ifdef TEST_TIME_PARAMETERS - // Test time parameter violations - reg[6:0] f_precharge_time_stamp[(1<= tCCD); - end - - if(cmd_d[READ_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0101) begin //READ - f_read_time_stamp[cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] <= f_timer + READ_SLOT; - //Check tCCD (read-to-read delay) - assert((f_timer+READ_SLOT) - f_read_time_stamp[bank_const] >= tCCD); - end - end - end - - always @* begin - // make sure saved time stamp is valid - assert(f_precharge_time_stamp[bank_const] <= f_timer); - assert(f_activate_time_stamp[bank_const] <= f_timer); - assert(f_read_time_stamp[bank_const] <= f_timer); - assert(f_write_time_stamp[bank_const] <= f_timer); - - // Check tRTP (Internal READ Command to PRECHARGE Command delay in SAME BANK) - if(f_precharge_time_stamp[bank_const] > f_read_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_read_time_stamp[bank_const]) >= ns_to_nCK(10)); - end - - // Check tWTR (Delay from start of internal write transaction to internal read command) - if(f_read_time_stamp[bank_const] > f_write_time_stamp[bank_const]) begin - assert((f_read_time_stamp[bank_const] - f_write_time_stamp[bank_const]) >= (CWL_nCK + 3'd4 + ns_to_nCK(tWTR))); - end - - // Check tRCD (ACT to internal read delay time) - if(f_read_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_read_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRCD)); - end - - // Check tRCD (ACT to internal write delay time) - if(f_write_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_write_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRCD)); - end - - // Check tRP (PRE command period) - if(f_activate_time_stamp[bank_const] > f_precharge_time_stamp[bank_const]) begin - assert((f_activate_time_stamp[bank_const] - f_precharge_time_stamp[bank_const]) >= ns_to_nCK(tRP)); - end - - // Check tRAS (ACTIVE to PRECHARGE command period) - if(f_precharge_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRAS)); - end - - // Check tWR (WRITE recovery time for write-to-precharge) - if(f_precharge_time_stamp[bank_const] > f_write_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_write_time_stamp[bank_const]) >= (CWL_nCK + 3'd4 + ns_to_nCK(tWR))); - end - - // Check delay from read-to-write - if(f_write_time_stamp[bank_const] > f_read_time_stamp[bank_const]) begin - assert((f_write_time_stamp[bank_const] - f_read_time_stamp[bank_const]) >= (CL_nCK + tCCD + 3'd2 - CWL_nCK)); - end - - end - - // extra assertions to make sure engine starts properly - always @* begin - assert(instruction_address <= 22); - assert(state_calibrate <= DONE_CALIBRATE); - - if(!o_wb_stall) begin - assert(state_calibrate == DONE_CALIBRATE); - assert(instruction_address == 22 || (instruction_address == 19 && delay_counter == 0)); - end - - if(instruction_address == 19 && delay_counter != 0 && state_calibrate == DONE_CALIBRATE) begin - if(stage1_pending || stage2_pending) begin - assert(pause_counter); - end - end - - if(stage1_pending || stage2_pending) begin - assert(state_calibrate > ISSUE_WRITE_1); - assert(instruction_address == 22 || instruction_address == 19); - end - - if(instruction_address < 13) begin - assert(state_calibrate == IDLE); - end - - if(state_calibrate > IDLE && state_calibrate <= BITSLIP_DQS_TRAIN_2) begin - assert(instruction_address == 13); - assert(pause_counter); - end - - - if(state_calibrate > START_WRITE_LEVEL && state_calibrate <= WAIT_FOR_FEEDBACK) begin - assert(instruction_address == 17); - assert(pause_counter); - end - - if(pause_counter) begin - assert(delay_counter != 0); - end - - if(state_calibrate > ISSUE_WRITE_1 && state_calibrate < DONE_CALIBRATE) begin - assume(instruction_address == 22); //write-then-read calibration will not take more than tREFI (7.8us, delay a address 22) - assert(reset_done); - end - - if(state_calibrate == DONE_CALIBRATE) begin - assert(reset_done); - assert(instruction_address >= 19); - end - - if(reset_done) begin - assert(instruction_address >= 19); - end - - if(!reset_done) begin - assert(!stage1_pending && !stage2_pending); - assert(o_wb_stall); - end - if(reset_done) begin - assert(instruction_address >= 19 && instruction_address <= 22); - end - //delay_counter is zero at first clock of new instruction address, the actual delay_clock wil start at next clock cycle - if(instruction_address == 19 && delay_counter != 0) begin - assert(o_wb_stall); - end - - if(instruction_address == 19 && pause_counter) begin //pre-stall delay to finish all remaining requests - assert(delay_counter == PRE_REFRESH_DELAY); - assert(reset_done); - assert(DONE_CALIBRATE); - end - end - - /* - always @(posedge i_controller_clk) begin - if(f_past_valid) begin - if($past(instruction_address) == 22 && instruction_address == 19) begin - assert(state_calibrate == DONE_CALIBRATE); - end - end - end - */ - `endif //endif for TEST_TIME_PARAMETERS - - - `ifdef TEST_CONTROLLER_PIPELINE - // wires and registers used in this formal section - `ifdef TEST_DATA - localparam F_TEST_CMD_DATA_WIDTH = $bits(i_wb_data) + $bits(i_wb_sel) + $bits(i_aux) + $bits(i_wb_addr) + $bits(i_wb_we); - `else - localparam F_TEST_CMD_DATA_WIDTH = $bits(i_wb_addr) + $bits(i_wb_we); - `endif - localparam F_MAX_STALL = max(WRITE_TO_PRECHARGE_DELAY,READ_TO_PRECHARGE_DELAY) + 1 + PRECHARGE_TO_ACTIVATE_DELAY + 1 + max(ACTIVATE_TO_WRITE_DELAY,ACTIVATE_TO_READ_DELAY) + 1 ; - //worst case delay (Precharge -> Activate-> R/W) - //add 1 to each delay since they end at zero - localparam F_MAX_ACK_DELAY = F_MAX_STALL + (READ_ACK_PIPE_WIDTH + 2); //max_stall + size of shift_reg_read_pipe_q + o_wb_ack_read_q (assume to be two via read_pipe_max) - - (*keep*) wire[3:0] f_max_stall, f_max_ack_delay; - assign f_max_stall = F_MAX_STALL; - assign f_max_ack_delay = F_MAX_ACK_DELAY; - - reg f_past_valid = 0; - reg[$bits(instruction_address) - 1: 0] f_addr = 0, f_read = 0 ; - reg[$bits(instruction) - 1:0] f_read_inst = INITIAL_RESET_INSTRUCTION; - reg[3:0] f_count_refreshes = 0; //count how many refresh cycles had already passed - reg[24:0] f_wb_inputs[31:0]; - reg[4:0] f_index = 0; - reg[5:0] f_counter = 0; - - reg[4:0] f_index_1 = 0; - reg[4:0] f_index_2 = 0; - reg[F_TEST_CMD_DATA_WIDTH - 1:0] f_write_data; - reg f_write_fifo = 0, f_read_fifo = 0; - reg[ROW_BITS-1:0] f_bank_active_row[(1< nCK_to_cycles(tDLLK)); //Initialization sequence requires that tDLLK is satisfied after MRS to mode register 0 and ZQ calibration - assert(MR0[18] != 1'b1); //last Mode Register bit should never be zero - assert(MR1_WL_EN[18] != 1'b1); //(as this is used for A10-AP control for non-MRS - assert(MR1_WL_DIS[18] != 1'b1); //(as this is used for A10-AP control for non-MRS - assert(MR2[18] != 1'b1); //commands in the reset sequence) - assert(MR3_MPR_EN[18] != 1'b1); - assert(MR3_MPR_DIS[18] != 1'b1); - assert(DELAY_COUNTER_WIDTH <= $bits(MR0)); //bitwidth of mode register should be enough for the delay counter - //sanity checking to ensure 5 bits is allotted for extra instruction {reset_finished, use_timer , stay_command , cke , reset_n } - assert(($bits(instruction) - $bits(CMD_MRS) - $bits(MR0)) == 5 ); - assert(DELAY_SLOT_WIDTH >= DELAY_COUNTER_WIDTH); //width occupied by delay timer slot on the reset rom must be able to occupy the maximum possible delay value on the reset sequence - end - - always @(posedge i_controller_clk) f_past_valid <= 1; - - - //The idea below is sourced from https://zipcpu.com/formal/2019/11/18/genuctrlr.html - //We will form a packet of information describing each instruction as it goes through the pipeline and make assertions along the way. - //2-stage Pipeline: f_addr (update address) -> f_read (read instruction from rom) - - //pipeline stage logic: f_addr (update address) -> f_read (read instruction from rom) - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - f_addr <= 0; - f_read <= 0; - end - //move the pipeline forward when counter is about to go zero and we are not yet at end of reset sequence - else if((delay_counter == 1 || !instruction[USE_TIMER])) begin - f_addr <= (f_addr == 22)? 19:f_addr + 1; - f_read <= f_addr; - end - end - - // assert f_addr and f_read as shadows of next and current instruction address - always @* begin - assert(f_addr == instruction_address); //f_addr is the shadow of instruction_address (thus f_addr is the address of NEXT instruction) - f_read_inst = read_rom_instruction(f_read); //f_read is the address of CURRENT instruction - assert(f_read_inst == read_rom_instruction(f_read)); // needed for induction to make sure the engine will not create his own instruction - if(f_addr == 0) begin - f_read_inst = INITIAL_RESET_INSTRUCTION; //will only happen at the very start: f_addr (0) -> f_read (0) where we are reading the initial reset instruction and not the rom - end - assert(f_read_inst == instruction); // f_read_inst is the shadow of current instruction - end - - // main assertions for the reset sequence - always @(posedge i_controller_clk) begin - if(!i_rst_n || !$past(i_rst_n)) begin - assert(f_addr == 0); - assert(f_read == 0); - assert(instruction_address == 0); - assert(delay_counter == (INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0])); - assert(delay_counter_is_zero == (INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0] == 0)); - end - else if(f_past_valid) begin - //if counter is zero previously and current instruction needs timer delay, then this cycle should now have the new updated counter value - if( $past(delay_counter_is_zero) && $past(f_read_inst[USE_TIMER]) ) begin - assert(delay_counter == f_read_inst[DELAY_COUNTER_WIDTH - 1:0]); - end - //delay_counter_is_zero can be high when counter is zero and current instruction needs delay - if($past(f_read_inst[USE_TIMER]) && !$past(pause_counter) ) begin - assert( delay_counter_is_zero == (delay_counter == 0) ); - end - //delay_counter_is_zero will go high this cycle when we received a don't-use-timer instruction - else if(!$past(f_read_inst[USE_TIMER]) && !$past(pause_counter)) begin - assert(delay_counter_is_zero); - end - - //we are on the middle of a delay thus all values must remain constant while only delay_counter changes (decrement) - if(!delay_counter_is_zero) begin - assert(f_addr == $past(f_addr)); - assert(f_read == $past(f_read)); - assert(f_read_inst == $past(f_read_inst)); - end - - //if delay is not yet zero and timer delay is enabled, then delay_counter should decrement - if(!$past(delay_counter_is_zero) && $past(f_read_inst[USE_TIMER]) && !$past(pause_counter) ) begin - assert(delay_counter == $past(delay_counter) - 1); - assert(delay_counter < $past(delay_counter) ); //just to make sure delay_counter will never overflow back to all 1's - end - - //sanity checking for the comment "delay_counter will be zero AT NEXT CLOCK CYCLE when counter is now one" - if($past(delay_counter) == 1) begin - assert(delay_counter == 0 && delay_counter_is_zero); - end - //assert the relationship between the stages FOR RESET SEQUENCE - if(!reset_done) begin - if(f_addr == 0) begin - assert(f_read == 0); //will only happen at the very start: f_addr (0) -> f_read (0) - end - else if(f_read == 0) begin - assert(f_addr <= 1); //will only happen at the very first two cycles: f_addr (1) -> f_read (0) or f_addr (0) -> f_read (0) - end - //else if($past(reset_done)) assert(f_read == $past(f_read)); //reset instruction does not repeat after reaching end address thus it must saturate when pipeline reaches end - else begin - assert(f_read + 1 == f_addr); //address increments continuously - end - assert($past(f_read) < 21); //only instruction address 0-to-13 is for reset sequence (reset_done is asserted at address 14) - end - - //assert the relationship between the stages FOR REFRESH SEQUENCE - else begin - if(f_read == 22) begin - assert(f_addr == 19); //if current instruction is 22, then next instruction must be at 19 (instruction address wraps from 15 to 12) - end - else if(f_addr == 19) begin - assert(f_read == 22); //if next instruction is at 12, then current instruction must be at 15 (instruction address wraps from 15 to 12) - end - else begin - assert(f_read + 1 == f_addr); //if there is no need to wrap around, then instruction address must increment - end - assert((f_read >= 19 && f_read <= 22) ); //refresh sequence is only on instruction address 19,20,21,22 - end - - // reset_done must retain high when it was already asserted once - if($past(reset_done)) begin - assert(reset_done); - end - - // reset is already done at address 21 and up - if($past(f_read) >= 21 ) begin - assert(reset_done); - end - - //if reset is done, the REF_IDLE must only be high at instruction address 14 (on the middle of tREFI) - if(reset_done && f_read_inst[REF_IDLE]) begin - assert(f_read == 21); - end - - end - - end - - - // assertions on the instructions stored on the rom - always @* begin - //there MUST BE no instruction which USE_TIMER is high but delay is zero since it can cause the logic to lock-up (delay must be at least 1) - if(a[USE_TIMER]) begin - assert( a[DELAY_COUNTER_WIDTH - 1:0] > 0); - end - end - - // assertion on FSM calibration - always @* begin - if(instruction_address < 13) begin - assert(state_calibrate == IDLE); - end - - if(state_calibrate > IDLE && state_calibrate <= BITSLIP_DQS_TRAIN_2) begin - assert(instruction_address == 13); - assert(pause_counter); - end - - - if(state_calibrate > START_WRITE_LEVEL && state_calibrate <= WAIT_FOR_FEEDBACK) begin - assert(instruction_address == 17); - assert(pause_counter); - end - - if(pause_counter) begin - assert(delay_counter != 0); - end - - if(state_calibrate > ISSUE_WRITE_1 && state_calibrate < DONE_CALIBRATE) begin - assume(instruction_address == 22); //write-then-read calibration will not take more than tREFI (7.8us, delay a address 22) - assert(reset_done); - end - - if(state_calibrate == DONE_CALIBRATE) begin - assert(reset_done); - assert(instruction_address >= 19); - end - - if(reset_done) begin - assert(instruction_address >= 19); - end - end - - always @* begin - //make sure each command has distinct slot number (except for read/write which can have the same or different slot number) - //assert((WRITE_SLOT != ACTIVATE_SLOT != PRECHARGE_SLOT) && (READ_SLOT != ACTIVATE_SLOT != PRECHARGE_SLOT) ); - assert(WRITE_SLOT != ACTIVATE_SLOT); - assert(WRITE_SLOT != PRECHARGE_SLOT); - assert(READ_SLOT != ACTIVATE_SLOT); - assert(READ_SLOT != PRECHARGE_SLOT); - //make sure slot number for read command is correct - end - //create a formal assertion that says during refresh ack should be low always - //make an assertion that there will be no request pending before actual refresh starts at instruction 4'd12 - - - mini_fifo #( - .FIFO_WIDTH(1), //the fifo will have 2**FIFO_WIDTH positions - .DATA_WIDTH(F_TEST_CMD_DATA_WIDTH) //each FIFO position can store DATA_WIDTH bits - ) fifo_1 ( - .i_clk(i_controller_clk), - .i_rst_n(i_rst_n && i_wb_cyc), //reset outstanding request at reset or when cyc goes low - .read_fifo(f_read_fifo), - .write_fifo(f_write_fifo), - .empty(f_empty), - .full(f_full), - .write_data(f_write_data), - .read_data(f_read_data), - .read_data_next(f_read_data_next) - ); - - always @* begin - if(state_calibrate == DONE_CALIBRATE && i_wb_cyc) begin - if(f_full) begin - assert(stage1_pending && stage2_pending);//there are 2 contents - end - if(stage1_pending && stage2_pending) begin - assert(f_full); - end - - if(!f_empty && !f_full) begin - assert(stage1_pending ^ stage2_pending);//there is 1 content - end - if(stage1_pending ^ stage2_pending) begin - assert(!f_empty && !f_full); - end - - if(f_empty) begin - assert(stage1_pending == 0 && stage2_pending==0); //there is 0 content - end - if(stage1_pending == 0 && stage2_pending == 0) begin - assert(f_empty); - end - end - - if(state_calibrate < ISSUE_WRITE_1) begin - assert(!stage1_pending && !stage2_pending); - end - if(stage1_pending && state_calibrate == ISSUE_READ) begin - assert(stage1_we); - end - if(stage2_pending && state_calibrate == ISSUE_READ) begin - assert(stage2_we); - end - if(state_calibrate == ANALYZE_DATA) begin - assert(!stage1_pending && !stage2_pending); - end - end - - always @(posedge i_controller_clk) begin - if(f_past_valid) begin - //switch from calibrate to done - if(state_calibrate == DONE_CALIBRATE && $past(state_calibrate) != DONE_CALIBRATE) begin - assert($past(state_calibrate) == ANALYZE_DATA); - assert(f_empty); - assert(!stage1_pending); - assert(!stage2_pending); - //assert(f_bank_status == 1); //only first bank is activated - //assert(bank_status_q == 1); - end - if(stage1_pending && $past(state_calibrate) == READ_DATA && state_calibrate == READ_DATA) begin - assert(!stage1_we); - end - if(instruction_address == 21 || ($past(instruction_address) == 20 && $past(instruction_address,2) == 19) || instruction_address < 19) begin //not inside active or calibration - assert(f_bank_status == 0); - assert(bank_status_q == 0); - end - if(state_calibrate != DONE_CALIBRATE) begin - assert(f_bank_status == 0 || f_bank_status == 1); //only first bank is activated - assert(bank_status_q == 0 || f_bank_status == 1); - end - end - end - - //wishbone request should have a corresponding DDR3 command at the output - //wishbone request will be written to fifo, then once a DDR3 command is - //issued the fifo will be read to check if the DDR3 command matches the - //corresponding wishbone request - reg[ROW_BITS-1:0] f_read_data_col; - reg[BA_BITS-1:0] f_read_data_bank; - reg[AUX_WIDTH-1:0] f_read_data_aux; - reg[wb_sel_bits-1:0] f_read_data_wb_sel; - always @* begin - //write the wb request to fifo - if(i_wb_stb && i_wb_cyc && !o_wb_stall && state_calibrate == DONE_CALIBRATE) begin - f_write_fifo = 1; - `ifdef TEST_DATA - f_write_data = {i_wb_data, i_wb_sel, i_aux, i_wb_addr,i_wb_we}; - `else - f_write_data = {i_wb_addr,i_wb_we}; - `endif - end - else begin - f_write_fifo = 0; - end - f_read_fifo = 0; - //check if a DDR3 command is issued - if(i_wb_cyc) begin //only if already done calibrate and controller can accept wb request - - if(cmd_d[WRITE_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0100) begin //WRITE - if(state_calibrate == DONE_CALIBRATE) begin - assert(f_bank_status[cmd_d[WRITE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == 1'b1); //the bank that will be written must initially be active - f_read_data_col = {f_read_data[1 +: COL_BITS - $clog2(wb_data_bits/8)], {$clog2(wb_data_bits/8){1'b0}} }; //column address must match - assert(cmd_d[WRITE_SLOT][CMD_ADDRESS_START:0] == f_read_data_col); - - f_read_data_bank = f_read_data[(COL_BITS - $clog2(wb_data_bits/8)) + 1 +: BA_BITS]; //bank must match - assert(cmd_d[WRITE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1] == f_read_data_bank); - - `ifdef TEST_DATA - f_read_data_aux = f_read_data[$bits(i_wb_addr) + 1 +: AUX_WIDTH]; //UAX ID must match - assert(stage2_aux == f_read_data_aux); - - f_read_data_wb_sel = (f_read_data[$bits(i_wb_addr) + AUX_WIDTH + 1 +: $bits(i_wb_sel)]); - assert(stage2_dm_unaligned == ~f_read_data_wb_sel); //data mask mst match inverse of wb sel - assert(stage2_data_unaligned == f_read_data[$bits(i_wb_sel) + $bits(i_wb_addr) + AUX_WIDTH + 1 +: $bits(i_wb_data)]); //actual data must match - `endif - - assert(f_read_data[0]); //i_wb_we must be high - f_read_fifo = 1; //advance read pointer to prepare for next read - end - else if(state_calibrate > ISSUE_WRITE_1) begin - assert(stage2_aux == 1); - end - //assert(f_bank_active_row[cmd_d[WRITE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == current_row); //column to be written must be the current active row - end - - if(cmd_d[READ_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0101) begin //READ - if(state_calibrate == DONE_CALIBRATE) begin - assert(f_bank_status[cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == 1'b1); //the bank that will be read must initially be active - f_read_data_col = {f_read_data[1 +: COL_BITS - $clog2(wb_data_bits/8)], {$clog2(wb_data_bits/8){1'b0}}}; //column address must match - assert(cmd_d[READ_SLOT][CMD_ADDRESS_START:0] == f_read_data_col); - - f_read_data_bank = f_read_data[(COL_BITS - $clog2(wb_data_bits/8)) + 1 +: BA_BITS]; //bank must match - assert(cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1] == f_read_data_bank); - - `ifdef TEST_DATA - f_read_data_aux = f_read_data[$bits(i_wb_addr) + 1 +: AUX_WIDTH]; //UAX ID must match - assert(stage2_aux == f_read_data_aux); - `endif - - assert(!f_read_data[0]); //i_wb_we must be low - f_read_fifo = 1; //advance read pointer to prepare for next read - end - else if(state_calibrate > ISSUE_WRITE_1) begin - assert(stage2_aux == 0); - end - //assert(f_bank_active_row[cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == current_row);//column to be written must be the current active row - end - - if(cmd_d[PRECHARGE_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0010) begin //PRECHARGE - if(state_calibrate == DONE_CALIBRATE && (instruction_address == 22 || instruction_address == 19)) begin - assert(f_bank_status[cmd_d[PRECHARGE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == 1'b1); //the bank that should be precharged must initially be active - end - end - - if(cmd_d[ACTIVATE_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0011) begin //ACTIVATE - if(state_calibrate == DONE_CALIBRATE) begin - assert(f_bank_status[cmd_d[ACTIVATE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == 1'b0); //the bank that should be activated must initially be precharged - end - end - - if(reset_done) begin - assert(cmd_d[PRECHARGE_SLOT][CMD_CKE] && cmd_d[PRECHARGE_SLOT][CMD_RESET_N]); //cke and rst_n should stay high when reset sequence is already done - assert(cmd_d[ACTIVATE_SLOT][CMD_CKE] && cmd_d[ACTIVATE_SLOT][CMD_RESET_N]); //cke and rst_n should stay high when reset sequence is already done - assert(cmd_d[READ_SLOT][CMD_CKE] && cmd_d[READ_SLOT][CMD_RESET_N]); //cke and rst_n should stay high when reset sequence is already done - assert(cmd_d[WRITE_SLOT][CMD_CKE] && cmd_d[WRITE_SLOT][CMD_RESET_N]); //cke and rst_n should stay high when reset sequence is already done - end - end - if(state_calibrate == DONE_CALIBRATE) begin - assert(reset_done); - end - if(state_calibrate != DONE_CALIBRATE) begin - assert(o_wb_stall); //if not yet finished calibrating, stall should never go low - end - if(state_calibrate != DONE_CALIBRATE) begin - assert(f_empty); //if not yet finished calibrating, stall should never go low - end - if(!f_empty) begin - assert(state_calibrate == DONE_CALIBRATE); - end - end - - //`ifdef UNDER_CONSTRUCTION - //make assertions on what is inside the fifo - always @* begin - if(!f_empty && !f_full) begin //make assertion when there is only 1 data on the pipe - if(stage1_pending) begin //request is still on stage1 - assert(stage1_bank == f_read_data[(COL_BITS - $clog2(wb_data_bits/8)) + 1 +: BA_BITS]); //bank must match - assert(stage1_col == {f_read_data[1 +: COL_BITS - $clog2(wb_data_bits/8)], {$clog2(wb_data_bits/8){1'b0}}}); //column address must match - assert(stage1_we == f_read_data[0]); //i_wb_we must be high - end - if(stage2_pending) begin //request is now on stage2 - assert(stage2_bank == f_read_data[(COL_BITS - $clog2(wb_data_bits/8)) + 1 +: BA_BITS]); //bank must match - assert(stage2_col == {f_read_data[1 +: COL_BITS - $clog2(wb_data_bits/8)], {$clog2(wb_data_bits/8){1'b0}}}); //column address must match - assert(stage2_we == f_read_data[0]); //i_wb_we must be high - end - end - if(f_full) begin //both stages have request - //stage2 is the request on the tip of the fifo - assert(stage2_bank == f_read_data[(COL_BITS - $clog2(wb_data_bits/8)) + 1 +: BA_BITS]); //bank must match - assert(stage2_col == {f_read_data[1 +: COL_BITS - $clog2(wb_data_bits/8)], {$clog2(wb_data_bits/8){1'b0}}}); //column address must match - assert(stage2_we == f_read_data[0]); //i_wb_we must be high - //stage1 is the request on the other element of the fifo - //(since the fifo only has 2 elements, the other element that - //is not the tip will surely be the 2nd request that is being - //handles by stage1) - assert(stage1_bank == f_read_data_next[(COL_BITS - $clog2(wb_data_bits/8)) + 1 +: BA_BITS]); //bank must match - assert(stage1_col == {f_read_data_next[1 +: COL_BITS - $clog2(wb_data_bits/8)], {$clog2(wb_data_bits/8){1'b0}}}); //column address must match - assert(stage1_we == f_read_data_next[0]); //i_wb_we must be high - end - end - - //`endif - - always @* begin - assert(f_bank_status == bank_status_q); - end - - (*keep*) reg[31:0] bank; - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - //reset bank status and active row - for(index=0; index < (1< ISSUE_WRITE_1 && state_calibrate < DONE_CALIBRATE) begin - if(stage1_pending) begin - assert(stage1_we == stage1_aux); //if write, then aux id must be 1 else 0 - end - if(stage2_pending) begin - assert(stage2_we == stage2_aux); //if write, then aux id must be 1 else 0 - end - end - - assert(state_calibrate <= DONE_CALIBRATE); - end - - wire[3:0] f_nreqs, f_nacks, f_outstanding, f_ackwait_count, f_stall_count; - wire[3:0] f_nreqs_2, f_nacks_2, f_outstanding_2; - reg[READ_ACK_PIPE_WIDTH+1:0] f_ack_pipe_after_stage2; - reg[AUX_WIDTH:0] f_aux_ack_pipe_after_stage2[READ_ACK_PIPE_WIDTH+1:0]; - integer f_ack_pipe_marker; - - integer f_sum_of_pending_acks = 0; - always @* begin - if(!i_rst_n) begin - assume(f_nreqs == 0); - assume(f_nacks == 0); - end - - if(state_calibrate != IDLE) assume(added_read_pipe_max == 1); - f_sum_of_pending_acks = stage1_pending + stage2_pending; - for(index = 0; index < READ_ACK_PIPE_WIDTH; index = index + 1) begin - f_sum_of_pending_acks = f_sum_of_pending_acks + shift_reg_read_pipe_q[index][0] + 0; - end - for(index = 0; index < 2; index = index + 1) begin //since added_read_pipe_max is assumed to be one, only the first two bits of o_wb_ack_read_q is relevant - f_sum_of_pending_acks = f_sum_of_pending_acks + o_wb_ack_read_q[index][0] + 0; - end - - //the remaining o_wb_ack_read_q (>2) should stay zero at - //all instance - for(index = 2; index < MAX_ADDED_READ_ACK_DELAY ; index = index + 1) begin - assert(o_wb_ack_read_q[index] == 0); - end - f_aux_ack_pipe_after_stage2[READ_ACK_PIPE_WIDTH+1] = o_wb_ack_read_q[0]; //last stage of f_aux_ack_pipe_after_stage2 is also the last ack stage - f_aux_ack_pipe_after_stage2[READ_ACK_PIPE_WIDTH] = o_wb_ack_read_q[1]; - for(index = 0; index < READ_ACK_PIPE_WIDTH; index = index + 1) begin - f_aux_ack_pipe_after_stage2[READ_ACK_PIPE_WIDTH - 1 - index] = shift_reg_read_pipe_q[index]; - end - f_ack_pipe_after_stage2 = { - o_wb_ack_read_q[0][0], - o_wb_ack_read_q[1][0], - shift_reg_read_pipe_q[0][0], - shift_reg_read_pipe_q[1][0], - shift_reg_read_pipe_q[2][0], - shift_reg_read_pipe_q[3][0], - shift_reg_read_pipe_q[4][0] - }; - - if(f_ackwait_count > F_MAX_STALL) begin - assert(|f_ack_pipe_after_stage2[(READ_ACK_PIPE_WIDTH+1) : (f_ackwait_count - F_MAX_STALL - 1)]); //at least one stage must be high - end - - - if(i_rst_n && state_calibrate == DONE_CALIBRATE) begin - assert(f_outstanding == f_sum_of_pending_acks || !i_wb_cyc); - end - else if(!i_rst_n) begin - assert(f_sum_of_pending_acks == 0); - end - if(state_calibrate != DONE_CALIBRATE && i_rst_n) begin - assert(f_outstanding == 0 || !i_wb_cyc); - end - if(state_calibrate <= ISSUE_WRITE_1 && i_rst_n) begin - //not inside tREFI, prestall delay, nor precharge - assert(f_outstanding == 0 || !i_wb_cyc); - assert(f_sum_of_pending_acks == 0); - end - if(state_calibrate == READ_DATA && i_rst_n) begin - assert(f_outstanding == 0 || !i_wb_cyc); - assert(f_sum_of_pending_acks <= 3); - - if((f_sum_of_pending_acks > 1) && o_wb_ack_read_q[0]) begin - assert(o_wb_ack_read_q[0] == {1, 1'b1}); - end - - f_ack_pipe_marker = 0; - for(index = 0; index < READ_ACK_PIPE_WIDTH + 2; index = index + 1) begin //check each ack stage starting from last stage - if(f_aux_ack_pipe_after_stage2[index][0]) begin //if ack is high - if(f_aux_ack_pipe_after_stage2[index][AUX_WIDTH:1] == 0) begin //ack for read - assert(f_ack_pipe_marker == 0); //read ack must be the last ack on the pipe(f_pipe_marker must still be zero) - f_ack_pipe_marker = f_ack_pipe_marker + 1; - assert(!stage1_pending && !stage2_pending); //a single read request must be the last request on this calibration - end - else begin //ack for write - assert(f_aux_ack_pipe_after_stage2[index][AUX_WIDTH:1] == 1); - f_ack_pipe_marker = f_ack_pipe_marker + 1; - end - end - end - assert(f_ack_pipe_marker <= 3); - end - - if(state_calibrate == ANALYZE_DATA && i_rst_n) begin - assert(f_outstanding == 0 || !i_wb_cyc); - assert(f_sum_of_pending_acks == 0); - end - if(state_calibrate != DONE_CALIBRATE && i_rst_n) begin //if not yet done calibration, no request should be accepted - assert(f_nreqs == 0); - assert(f_nacks == 0); - assert(f_outstanding == 0 || !i_wb_cyc); - end - - if(state_calibrate == ISSUE_WRITE_2 || state_calibrate == ISSUE_READ) begin - if(write_calib_stb == 1) begin - assert(write_calib_aux == 1); - assert(write_calib_we == 1); - end - end - if(!stage1_pending) begin - assert(!stage1_stall); - end - - if(!stage2_pending) begin - assert(!stage2_stall); - end - end - always @(posedge i_controller_clk) begin - if(f_past_valid) begin - if(instruction_address != 22 && instruction_address != 19 && $past(i_wb_cyc) && i_rst_n) begin - assert(f_nreqs == $past(f_nreqs)); - end - if(state_calibrate == DONE_CALIBRATE && $past(state_calibrate) != DONE_CALIBRATE && i_rst_n) begin//just started DONE_CALBRATION - assert(f_nreqs == 0); - assert(f_nacks == 0); - assert(f_outstanding == 0); - assert(f_sum_of_pending_acks == 0); - end - if((!stage1_pending || !stage2_pending) && $past(state_calibrate) == DONE_CALIBRATE && state_calibrate == DONE_CALIBRATE - && instruction_address == 22 && $past(instruction_address == 22)) begin - assert(!o_wb_stall);//if even 1 of the stage is empty, o_wb_stall must be low - end - end - end - - //test the delay_before* - always @* begin - for(index=0; index< (1<= tCCD); - end - - if(cmd_d[READ_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0101) begin //READ - f_read_time_stamp[cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] <= f_timer + READ_SLOT; - //Check tCCD (read-to-read delay) - assert((f_timer+READ_SLOT) - f_read_time_stamp[bank_const] >= tCCD); - end - end - end - - always @* begin - // make sure saved time stamp is valid - assert(f_precharge_time_stamp[bank_const] <= f_timer); - assert(f_activate_time_stamp[bank_const] <= f_timer); - assert(f_read_time_stamp[bank_const] <= f_timer); - assert(f_write_time_stamp[bank_const] <= f_timer); - - // Check tRTP (Internal READ Command to PRECHARGE Command delay in SAME BANK) - if(f_precharge_time_stamp[bank_const] > f_read_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_read_time_stamp[bank_const]) >= ns_to_nCK(10)); - end - - // Check tWTR (Delay from start of internal write transaction to internal read command) - if(f_read_time_stamp[bank_const] > f_write_time_stamp[bank_const]) begin - assert((f_read_time_stamp[bank_const] - f_write_time_stamp[bank_const]) >= (CWL_nCK + 3'd4 + ns_to_nCK(tWTR))); - end - - // Check tRCD (ACT to internal read delay time) - if(f_read_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_read_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRCD)); - end - - // Check tRCD (ACT to internal write delay time) - if(f_write_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_write_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRCD)); - end - - // Check tRP (PRE command period) - if(f_activate_time_stamp[bank_const] > f_precharge_time_stamp[bank_const]) begin - assert((f_activate_time_stamp[bank_const] - f_precharge_time_stamp[bank_const]) >= ns_to_nCK(tRP)); - end - - // Check tRAS (ACTIVE to PRECHARGE command period) - if(f_precharge_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRAS)); - end - - // Check tWR (WRITE recovery time for write-to-precharge) - if(f_precharge_time_stamp[bank_const] > f_write_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_write_time_stamp[bank_const]) >= (CWL_nCK + 3'd4 + ns_to_nCK(tWR))); - end - - // Check delay from read-to-write - if(f_write_time_stamp[bank_const] > f_read_time_stamp[bank_const]) begin - assert((f_write_time_stamp[bank_const] - f_read_time_stamp[bank_const]) >= (CL_nCK + tCCD + 3'd2 - CWL_nCK)); - end - - end - - // extra assertions to make sure engine starts properly - always @* begin - assert(instruction_address <= 22); - assert(state_calibrate <= DONE_CALIBRATE); - - if(!o_wb_stall) begin - assert(state_calibrate == DONE_CALIBRATE); - assert(instruction_address == 22 || (instruction_address == 19 && delay_counter == 0)); - end - - if(instruction_address == 19 && delay_counter != 0 && state_calibrate == DONE_CALIBRATE) begin - if(stage1_pending || stage2_pending) begin - assert(pause_counter); - end - end - - if(stage1_pending || stage2_pending) begin - assert(state_calibrate > ISSUE_WRITE_1); - assert(instruction_address == 22 || instruction_address == 19); - end - - if(instruction_address < 13) begin - assert(state_calibrate == IDLE); - end - - if(state_calibrate > IDLE && state_calibrate <= BITSLIP_DQS_TRAIN_2) begin - assert(instruction_address == 13); - assert(pause_counter); - end - - - if(state_calibrate > START_WRITE_LEVEL && state_calibrate <= WAIT_FOR_FEEDBACK) begin - assert(instruction_address == 17); - assert(pause_counter); - end - - if(pause_counter) begin - assert(delay_counter != 0); - end - - if(state_calibrate > ISSUE_WRITE_1 && state_calibrate < DONE_CALIBRATE) begin - assume(instruction_address == 22); //write-then-read calibration will not take more than tREFI (7.8us, delay a address 22) - assert(reset_done); - end - - if(state_calibrate == DONE_CALIBRATE) begin - assert(reset_done); - assert(instruction_address >= 19); - end - - if(reset_done) begin - assert(instruction_address >= 19); - end - - if(!reset_done) begin - assert(!stage1_pending && !stage2_pending); - assert(o_wb_stall); - end - if(reset_done) begin - assert(instruction_address >= 19 && instruction_address <= 22); - end - //delay_counter is zero at first clock of new instruction address, the actual delay_clock wil start at next clock cycle - if(instruction_address == 19 && delay_counter != 0) begin - assert(o_wb_stall); - end - - if(instruction_address == 19 && pause_counter) begin //pre-stall delay to finish all remaining requests - assert(delay_counter == PRE_REFRESH_DELAY); - assert(reset_done); - assert(DONE_CALIBRATE); - end - end - - // verify the wishbone 2 - localparam F_TEST_WB2_DATA_WIDTH = wb2_sel_bits + 5 + $clog2(LANES) + 4 + 1; //WB2_SEL + CNTVALUEIN + LANE_NUMBER + MEMORY_MAPPED_ADDRESS + REQUEST_TYPE - reg f_read_fifo_2, f_write_fifo_2; - wire f_empty_2, f_full_2; - reg[F_TEST_WB2_DATA_WIDTH - 1:0] f_write_data_2 = 0; - reg[F_TEST_WB2_DATA_WIDTH - 1:0] f_read_data_2, f_read_data_2_q; - reg f_o_wb2_ack_q = 0; //registered o_wb2_ack - (*keep*) reg[LANES-1:0] f_delay_ld = 0; - - //accept request - always @* begin - if(f_empty_2 && i_wb2_cyc) begin - assert(!wb2_stb && !o_wb2_ack); - end - if(!wb2_stb && !o_wb2_ack) begin - assert(f_empty_2); - end - f_write_data_2 = 0; - f_write_fifo_2 = 0; - if(i_wb2_stb && !o_wb2_stall && i_wb2_cyc) begin //if there is request - if(i_wb2_we) begin //write request - f_write_data_2 = {i_wb2_sel, i_wb2_data[4:0], i_wb2_data[5 +: $clog2(LANES)], i_wb2_addr[3:0], i_wb2_we}; //CNTVALUEIN + LANE_NUMBER + MEMORY_MAPPED_ADDRESS + REQUEST_TYPE - end - else begin //read request - f_write_data_2 = {i_wb2_addr[4 +: $clog2(LANES)], i_wb2_addr[3:0], i_wb2_we}; //LANE_NUMBER + MEMORY_MAPPED_ADDRESS + REQUEST_TYPE - end - f_write_fifo_2 = 1; - end - - if(state_calibrate != DONE_CALIBRATE && i_wb2_stb) begin - /* must not be a read/write to delays when not yet done calibrating */ - assume(i_wb2_addr[3:0] > 3); - end - end - - //verify outcome of request - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - f_o_wb2_ack_q <= 0; - f_read_data_2_q <= 0; - end - else begin - f_o_wb2_ack_q <= o_wb2_ack && f_read_data_2[0] && i_wb2_cyc; - f_read_data_2_q <= f_read_data_2; - end - end - always @* begin - if(i_rst_n) begin - if(wb2_stb && o_wb2_ack) begin - assert(f_full_2 || !i_wb2_cyc); - end - if(f_full_2) begin - assert(wb2_stb && o_wb2_ack); - assert(f_outstanding_2 == 2 || !i_wb2_cyc); - end - if(f_outstanding_2 == 2) begin - assert(f_full_2 || !i_wb2_cyc); - end - if(f_empty_2) begin - assert(f_outstanding_2 == 0 || !i_wb2_cyc); - end - if(f_outstanding_2 == 0) begin - assert(f_empty_2 || !i_wb2_cyc); - end - end - assert(f_outstanding_2 <= 2); - f_read_fifo_2 = 0; - if(o_wb2_ack && !f_read_data_2[0] && i_rst_n) begin //read request - f_read_fifo_2 = 1; - end - - if(o_wb2_ack && f_read_data_2[0] && i_rst_n) begin - f_read_fifo_2 = 1; - end - end - - //check request action at wb_ack - always @(posedge i_controller_clk) begin - if(f_past_valid) begin - assert(!o_wb2_stall || !i_rst_n || !$past(i_rst_n)); //never stall - //write request - if(f_o_wb2_ack_q && i_rst_n && (&f_read_data_2_q[5 + $clog2(LANES) + 4 + 1 +: $rtoi($ceil( ($clog2(LANES) + 5)/8 ))])) begin //the sel bits must be high - case(f_read_data_2_q[4:1]) //memory-mapped address - 0: begin - assert(o_phy_odelay_data_ld == (1 << f_read_data_2_q[5 +: $clog2(LANES)])); //the phy lane to be loaded must be high - assert(o_phy_odelay_data_cntvaluein == f_read_data_2_q[(5 + $clog2(LANES)) +: 5]); //the phy interface for cntvalue must already be updated - assert($past(wb2_update)); - end - 1: begin - assert(o_phy_odelay_dqs_ld == (1 << f_read_data_2_q[5 +: $clog2(LANES)])); //the phy lane to be loaded must be high - assert(o_phy_odelay_dqs_cntvaluein == f_read_data_2_q[(5 + $clog2(LANES)) +: 5]); //the phy interface for cntvalue must already be updated - assert($past(wb2_update)); - end - 2: begin - assert(o_phy_idelay_data_ld == (1 << f_read_data_2_q[5 +: $clog2(LANES)])); //the phy lane to be loaded must be high - assert(o_phy_idelay_data_cntvaluein == f_read_data_2_q[(5 + $clog2(LANES)) +: 5]); //the phy interface for cntvalue must already be updated - assert($past(wb2_update)); - end - 3: begin - assert(o_phy_idelay_dqs_ld == (1 << f_read_data_2_q[5 +: $clog2(LANES)])); //the phy lane to be loaded must be high - assert(o_phy_idelay_dqs_cntvaluein == f_read_data_2_q[(5 + $clog2(LANES)) +: 5]); //the phy interface for cntvalue must already be updated - assert($past(wb2_update)); - end - endcase - end - else if(i_rst_n) begin - assert(!$past(wb2_update) || !$past(i_wb2_cyc)); - end - - //read request - if(o_wb2_ack && !f_read_data_2[0] && i_rst_n && i_wb2_cyc && !(f_o_wb2_ack_q && f_read_data_2_q[1 +: (4 + $clog2(LANES))] == f_read_data_2[1 +: (4 + $clog2(LANES))] )) begin - case(f_read_data_2[4:1]) //memory-mapped address - 0: begin - assert(o_wb2_data == odelay_data_cntvaluein[f_read_data_2[5 +: $clog2(LANES)]]); //the stored delay must match the wb2 output - end - 1: begin - assert(o_wb2_data == odelay_dqs_cntvaluein[f_read_data_2[5 +: $clog2(LANES)]]); //the stored delay must match the wb2 output - end - 2: begin - assert(o_wb2_data == idelay_data_cntvaluein[f_read_data_2[5 +: $clog2(LANES)]]); //the stored delay must match the wb2 output - end - 3: begin - assert(o_wb2_data == idelay_dqs_cntvaluein[f_read_data_2[5 +: $clog2(LANES)]]); //the stored delay must match the wb2 output - end - - 4: begin - assert(o_wb2_data[0] == $past(i_phy_idelayctrl_rdy)); - assert(o_wb2_data[5:1] == $past(state_calibrate)); - assert(o_wb2_data[10:6] == $past(instruction_address)); - assert(o_wb2_data[14:11] == $past(added_read_pipe_max)); - end - - 5: begin - assert(o_wb2_data[3:0] == $past(added_read_pipe[0])); - assert(o_wb2_data[7:4] == $past(added_read_pipe[1])); - assert(o_wb2_data[11:8] == $past(added_read_pipe[2])); - assert(o_wb2_data[15:12] == $past(added_read_pipe[3])); - assert(o_wb2_data[19:16] == $past(added_read_pipe[4])); - assert(o_wb2_data[23:20] == $past(added_read_pipe[5])); - assert(o_wb2_data[27:24] == $past(added_read_pipe[6])); - assert(o_wb2_data[31:28] == $past(added_read_pipe[7])); - end - - 6: begin - assert(o_wb2_data == $past(dqs_store[31:0])); - end - - 7: begin - assert(o_wb2_data == $past(i_phy_iserdes_bitslip_reference[31:0])); - end - - 8: begin - assert(o_wb2_data == $past(read_data_store[31:0])); - end - - 9: begin - assert(o_wb2_data == $past(write_pattern[31:0])); - end - endcase - end - end - end - - wire[2:0] f_read_data_2_lane; - assign f_read_data_2_lane = f_read_data_2[5 +: $clog2(LANES)]; - always @(posedge i_controller_clk) begin - if(f_past_valid) begin - for(index = 0; index < LANES; index = index + 1) begin - if(o_phy_bitslip[index]) begin - /* Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip must be - deasserted for at least one CLKDIV cycle between two Bitslip assertions. - */ - assert(!$past(o_phy_bitslip[index])); - end - end - end - end - - mini_fifo #( - .FIFO_WIDTH(1), //the fifo will have 2**FIFO_WIDTH positions - .DATA_WIDTH(F_TEST_WB2_DATA_WIDTH) //each FIFO position can store DATA_WIDTH bits - ) fifo_2 ( - .i_clk(i_controller_clk), - .i_rst_n(i_rst_n && i_wb2_cyc), //reset outstanding request at reset or when cyc goes low - .read_fifo(f_read_fifo_2), - .write_fifo(f_write_fifo_2), - .empty(f_empty_2), - .full(f_full_2), - .write_data(f_write_data_2), - .read_data(f_read_data_2) - ); - - //assumption on when to do request (so as not to violate the - //F_MAX_STALL property of fwb_slave) - always @* begin - if(!(state_calibrate == DONE_CALIBRATE && instruction_address == 22)) begin //if in initialization/refresh sequence, no request should come in to the controller wishbone - assume(!i_wb_stb); - end - end - fwb_slave #( - // {{{ - .AW(wb_addr_bits), - .DW(wb_data_bits), - .F_MAX_STALL(F_MAX_STALL), - .F_MAX_ACK_DELAY(F_MAX_ACK_DELAY), - .F_LGDEPTH(4), - .F_MAX_REQUESTS(10), - // OPT_BUS_ABORT: If true, the master can drop CYC at any time - // and must drop CYC following any bus error - .OPT_BUS_ABORT(1), - // - // If true, allow the bus to be kept open when there are no - // outstanding requests. This is useful for any master that - // might execute a read modify write cycle, such as an atomic - // add. - .F_OPT_RMW_BUS_OPTION(1), - // - // - // If true, allow the bus to issue multiple discontinuous - // requests. - // Unlike F_OPT_RMW_BUS_OPTION, these requests may be issued - // while other requests are outstanding - .F_OPT_DISCONTINUOUS(1), - // - // - // If true, insist that there be a minimum of a single clock - // delay between request and response. This defaults to off - // since the wishbone specification specifically doesn't - // require this. However, some interfaces do, so we allow it - // as an option here. - .F_OPT_MINCLOCK_DELAY(1), - // }}} - ) wb_properties ( - // {{{ - .i_clk(i_controller_clk), - .i_reset(!i_rst_n), - // The Wishbone bus - .i_wb_cyc(i_wb_cyc), - .i_wb_stb(i_wb_stb), - .i_wb_we(i_wb_we), - .i_wb_addr(i_wb_addr), - .i_wb_data(i_wb_data), - .i_wb_sel(i_wb_sel), - // - .i_wb_ack(o_wb_ack), - .i_wb_stall(o_wb_stall), - .i_wb_idata(o_wb_data), - .i_wb_err(1'b0), - // Some convenience output parameters - .f_nreqs(f_nreqs), - .f_nacks(f_nacks), - .f_outstanding(f_outstanding), - .f_ackwait_count(f_ackwait_count), - .f_stall_count(f_stall_count) - // }}} - // }}} - ); - - fwb_slave #( - // {{{ - .AW(WB2_ADDR_BITS), - .DW(WB2_DATA_BITS), - .F_MAX_STALL(2), - .F_MAX_ACK_DELAY(2), - .F_LGDEPTH(4), - .F_MAX_REQUESTS(10), - // OPT_BUS_ABORT: If true, the master can drop CYC at any time - // and must drop CYC following any bus error - .OPT_BUS_ABORT(1), - // - // If true, allow the bus to be kept open when there are no - // outstanding requests. This is useful for any master that - // might execute a read modify write cycle, such as an atomic - // add. - .F_OPT_RMW_BUS_OPTION(1), - // - // - // If true, allow the bus to issue multiple discontinuous - // requests. - // Unlike F_OPT_RMW_BUS_OPTION, these requests may be issued - // while other requests are outstanding - .F_OPT_DISCONTINUOUS(1), - // - // - // If true, insist that there be a minimum of a single clock - // delay between request and response. This defaults to off - // since the wishbone specification specifically doesn't - // require this. However, some interfaces do, so we allow it - // as an option here. - .F_OPT_MINCLOCK_DELAY(1), - // }}} - ) wb2_properties ( - // {{{ - .i_clk(i_controller_clk), - .i_reset(!i_rst_n), - // The Wishbone bus - .i_wb_cyc(i_wb2_cyc), - .i_wb_stb(i_wb2_stb), - .i_wb_we(i_wb2_we), - .i_wb_addr(i_wb2_addr), - .i_wb_data(i_wb2_data), - .i_wb_sel(i_wb2_sel), - // - .i_wb_ack(o_wb2_ack), - .i_wb_stall(o_wb2_stall), - .i_wb_idata(o_wb2_data), - .i_wb_err(1'b0), - // Some convenience output parameters - .f_nreqs(f_nreqs_2), - .f_nacks(f_nacks_2), - .f_outstanding(f_outstanding_2), - // }}} - // }}} - ); - `endif //endif for TEST_CONTROLLER_PIPELINE -`endif //endif for FORMAL -endmodule - -//FiFO with only 2 elements for verifying the contents of the controller -//2-stage pipeline -module mini_fifo #( - parameter FIFO_WIDTH = 1, //the fifo will have 2**FIFO_WIDTH positions - parameter DATA_WIDTH = 8 //each FIFO position can store DATA_WIDTH bits - )( - input wire i_clk, i_rst_n, - input wire read_fifo, write_fifo, - output reg empty, full, - input wire[DATA_WIDTH - 1:0] write_data, - output wire[DATA_WIDTH - 1:0] read_data, - output wire[DATA_WIDTH - 1:0] read_data_next - ); - reg[FIFO_WIDTH-1:0] write_pointer=0, read_pointer=0; - reg[DATA_WIDTH - 1:0] fifo_reg[2**FIFO_WIDTH-1:0]; - initial begin - empty = 1; - full = 0; - end - - always @(posedge i_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - empty <= 1; - full <=0; - read_pointer <= 0; - write_pointer <= 0; - end - else begin - if(read_fifo) begin - `ifdef FORMAL - assert(!empty); - `endif - if(!write_fifo) full <= 0; - //advance read pointer - read_pointer <= read_pointer + 1; - if(read_pointer + 1'b1 == write_pointer && !write_fifo) empty <= 1; - end - if(write_fifo) begin - `ifdef FORMAL - if(!read_fifo) assert(!full); - `endif - if(!read_fifo) empty <= 0; - //write to FiFo - fifo_reg[write_pointer] <= write_data; - //advance read pointer - write_pointer <= write_pointer + 1; - if(write_pointer + 1'b1 == read_pointer && !read_fifo) full <= 1'b1; //fifo should never be full - end - end - end - assign read_data = fifo_reg[read_pointer]; - assign read_data_next = fifo_reg[!read_pointer]; //data after current pointer - - `ifdef FORMAL - //mini-FiFo assertions - always @* begin - if(empty || full) begin - assert(write_pointer == read_pointer); - end - if(write_pointer == read_pointer) begin - assert(empty || full); - end - assert(!(empty && full)); - //TASK ADD MORE ASSERTIONS - end - `endif - -endmodule - - diff --git a/delete_later/rtl/ddr3/ddr3_phy.v b/delete_later/rtl/ddr3/ddr3_phy.v deleted file mode 100644 index 07ae6c3..0000000 --- a/delete_later/rtl/ddr3/ddr3_phy.v +++ /dev/null @@ -1,926 +0,0 @@ -`default_nettype none -`timescale 1ps / 1ps - -module ddr3_phy #( - parameter ROW_BITS = 14, - BA_BITS = 3, - DQ_BITS = 8, - LANES = 8, - CONTROLLER_CLK_PERIOD = 5, //ns, period of clock input to this DDR3 controller module - DDR3_CLK_PERIOD = 1.25, //ns, period of clock input to DDR3 RAM device - // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration - serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD), - wb_data_bits = DQ_BITS*LANES*serdes_ratio*2, - wb_sel_bits = wb_data_bits / 8, - //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits - cmd_len = 4 + 3 + BA_BITS + ROW_BITS - )( - input wire i_controller_clk, i_ddr3_clk, i_ref_clk, - input wire i_rst_n, - // Controller Interface - input wire[cmd_len*serdes_ratio-1:0] i_controller_cmd, - input wire i_controller_dqs_tri_control, i_controller_dq_tri_control, - input wire i_controller_toggle_dqs, - input wire[wb_data_bits-1:0] i_controller_data, - input wire[wb_sel_bits-1:0] i_controller_dm, - input wire[4:0] i_controller_odelay_data_cntvaluein,i_controller_odelay_dqs_cntvaluein, - input wire[4:0] i_controller_idelay_data_cntvaluein,i_controller_idelay_dqs_cntvaluein, - input wire[LANES-1:0] i_controller_odelay_data_ld, i_controller_odelay_dqs_ld, - input wire[LANES-1:0] i_controller_idelay_data_ld, i_controller_idelay_dqs_ld, - input wire[LANES-1:0] i_controller_bitslip, - output wire[DQ_BITS*LANES*8-1:0] o_controller_iserdes_data, - output wire[LANES*8-1:0] o_controller_iserdes_dqs, - output wire[LANES*8-1:0] o_controller_iserdes_bitslip_reference, - output wire o_controller_idelayctrl_rdy, - // DDR3 I/O Interface - output wire o_ddr3_clk_p,o_ddr3_clk_n, - output wire o_ddr3_reset_n, - output wire o_ddr3_cke, // CKE - output wire o_ddr3_cs_n, // chip select signal - output wire o_ddr3_ras_n, // RAS# - output wire o_ddr3_cas_n, // CAS# - output wire o_ddr3_we_n, // WE# - output wire[ROW_BITS-1:0] o_ddr3_addr, - output wire[BA_BITS-1:0] o_ddr3_ba_addr, - inout wire[(DQ_BITS*LANES)-1:0] io_ddr3_dq, - inout wire[(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs, io_ddr3_dqs_n, - output wire[LANES-1:0] o_ddr3_dm, - output wire o_ddr3_odt // on-die termination - ); - - // cmd bit assignment - localparam CMD_CS_N = cmd_len - 1, - CMD_RAS_N = cmd_len - 2, - CMD_CAS_N= cmd_len - 3, - CMD_WE_N = cmd_len - 4, - CMD_ODT = cmd_len - 5, - CMD_CKE = cmd_len - 6, - CMD_RESET_N = cmd_len - 7, - CMD_BANK_START = BA_BITS + ROW_BITS - 1, - CMD_ADDRESS_START = ROW_BITS - 1; - localparam SYNC_RESET_DELAY = $rtoi($ceil(52/CONTROLLER_CLK_PERIOD)); //52 ns of reset pulse width required for IDELAYCTRL - //cmd needs to be center-aligned to the positive edge of the - //ddr3_clk. This means cmd needs to be delayed by half the ddr3 - //clk period. Subtract by 600ps to include the IODELAY insertion - //delay. Divide by a delay resolution of 78.125ps per tap to get - //the needed tap value. - localparam CMD_ODELAY_TAP = ((DDR3_CLK_PERIOD*1000/2) - 600)/78.125; - - // Data does not have to be delayed (DQS is the on that has to be - // delayed and center-aligned to the center eye of data) - localparam DATA_ODELAY_TAP = 0; - - //DQS needs to be edge-aligned to the center eye of the data. - //This means DQS needs to be delayed by a quarter of the ddr3 - //clk period relative to the data. Subtract by 600ps to include - //the IODELAY insertion delay. Divide by a delay resolution of - //78.125ps per tap to get the needed tap value. Then add the tap - //value used in data to have the delay relative to the data. - localparam DQS_ODELAY_TAP = ((DDR3_CLK_PERIOD*1000/4))/78.125 + DATA_ODELAY_TAP; - - //Incoming DQS should be 90 degree delayed relative to incoming data - localparam DATA_IDELAY_TAP = 0; //600ps delay - localparam DQS_IDELAY_TAP = ((DDR3_CLK_PERIOD*1000/4))/78.125 + DATA_IDELAY_TAP; - - genvar gen_index; - wire[cmd_len-1:0] oserdes_cmd, //serialized(4:1) i_controller_cmd_slot_x - cmd;//delayed oserdes_cmd - wire[(DQ_BITS*LANES)-1:0] oserdes_data, odelay_data, idelay_data, read_dq; - wire[LANES-1:0] oserdes_dm, odelay_dm; - wire[LANES-1:0] odelay_dqs, read_dqs, idelay_dqs; - wire[DQ_BITS*LANES-1:0] oserdes_dq_tri_control; - wire[LANES-1:0] oserdes_dqs; - wire[LANES-1:0] oserdes_dqs_tri_control; - wire[LANES-1:0] oserdes_bitslip_reference; - reg[$clog2(SYNC_RESET_DELAY):0] delay_before_release_reset; - reg sync_rst = 0; - wire ddr3_clk; - reg toggle_dqs_q; //past value of i_controller_toggle_dqs - //synchronous reset - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - sync_rst <= 1'b1; - delay_before_release_reset <= SYNC_RESET_DELAY[$clog2(SYNC_RESET_DELAY):0]; - toggle_dqs_q <= 0; - end - else begin - delay_before_release_reset <= (delay_before_release_reset == 0)? 0: delay_before_release_reset - 1; - sync_rst <= !(delay_before_release_reset == 0); - toggle_dqs_q <= i_controller_toggle_dqs; - end - end - - //PHY cmd - generate - for(gen_index = 0; gen_index < cmd_len; gen_index = gen_index + 1) begin - // OSERDESE2: Output SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OSERDESE2 #( - .DATA_RATE_OQ("SDR"), // DDR, SDR - .DATA_RATE_TQ("SDR"), // DDR, SDR - .DATA_WIDTH(4), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1) - .TRISTATE_WIDTH(1) - ) - OSERDESE2_cmd( - .OFB(oserdes_cmd[gen_index]), // 1-bit output: Feedback path for data - .OQ(), // 1-bit output: Data path output - .CLK(i_ddr3_clk), // 1-bit input: High speed clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) - .D1(i_controller_cmd[cmd_len*0 + gen_index]), - .D2(i_controller_cmd[cmd_len*1 + gen_index]), - .D3(i_controller_cmd[cmd_len*2 + gen_index]), - .D4(i_controller_cmd[cmd_len*3 + gen_index]), - .OCE(1'b1), // 1-bit input: Output data clock enable - .RST(sync_rst), // 1-bit input: Reset - // unused signals but were added here to make vivado happy - .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) - .SHIFTOUT2(), - .TBYTEOUT(), // 1-bit output: Byte group tristate - .TFB(), // 1-bit output: 3-state control - .TQ(), // 1-bit output: 3-state control - .D5(), - .D6(), - .D7(), - .D8(), - // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - .SHIFTIN1(0), - .SHIFTIN2(0), - // T1 - T4: 1-bit (each) input: Parallel 3-state inputs - .T1(0), - .T2(0), - .T3(0), - .T4(0), - .TBYTEIN(0), - // 1-bit input: Byte group tristate - .TCE(0) - // 1-bit input: 3-state clock enable - ); - // End of OSERDESE2_inst instantiation - - - (* IODELAY_GROUP = 0 *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL - //Delay the DQ - // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps - ODELAYE2 #( - .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN) - .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE") - .ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE - .ODELAY_VALUE(CMD_ODELAY_TAP), // Output delay tap setting (0-31) - .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0). - .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal - ) - ODELAYE2_cmd ( - .CNTVALUEOUT(), // 5-bit output: Counter value output - .DATAOUT(cmd[gen_index]), // 1-bit output: Delayed data/clock output - .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV - .CE(1'b0), // 1-bit input: Active high enable increment/decrement input - .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input - .CLKIN(1'b0), // 1-bit input: Clock delay input - .CNTVALUEIN(5'd0), // 5-bit input: Counter value input - .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input - .LD(1'b0), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or - // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN - .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data - .ODATAIN(oserdes_cmd[gen_index]), // 1-bit input: Output delay data input - .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input - ); - end - endgenerate - - assign o_ddr3_cs_n = cmd[CMD_CS_N], - o_ddr3_ras_n = cmd[CMD_RAS_N], - o_ddr3_cas_n = cmd[CMD_CAS_N], - o_ddr3_we_n = cmd[CMD_WE_N], - o_ddr3_odt = cmd[CMD_ODT], - o_ddr3_cke = cmd[CMD_CKE], - o_ddr3_reset_n = cmd[CMD_RESET_N], - o_ddr3_ba_addr = cmd[CMD_BANK_START:CMD_ADDRESS_START+1], - o_ddr3_addr = cmd[CMD_ADDRESS_START:0]; - - // OSERDESE2: Output SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OSERDESE2 #( - .DATA_RATE_OQ("DDR"), // DDR, SDR - .DATA_RATE_TQ("SDR"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1) - .TRISTATE_WIDTH(1) - ) - OSERDESE2_clk( - .OFB(), // 1-bit output: Feedback path for data - .OQ(ddr3_clk), // 1-bit output: Data path output - .CLK(i_ddr3_clk), // 1-bit input: High speed clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) - .D1(1'b1), - .D2(1'b0), - .D3(1'b1), - .D4(1'b0), - .D5(1'b1), - .D6(1'b0), - .D7(1'b1), - .D8(1'b0), - .OCE(1'b1), // 1-bit input: Output data clock enable - .RST(sync_rst), // 1-bit input: Reset - // unused signals but were added here to make vivado happy - .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) - .SHIFTOUT2(), - .TBYTEOUT(), // 1-bit output: Byte group tristate - .TFB(), // 1-bit output: 3-state control - .TQ(), // 1-bit output: 3-state control - // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - .SHIFTIN1(0), - .SHIFTIN2(0), - // T1 - T4: 1-bit (each) input: Parallel 3-state inputs - .T1(0), - .T2(0), - .T3(0), - .T4(0), - .TBYTEIN(0), - // 1-bit input: Byte group tristate - .TCE(0) - // 1-bit input: 3-state clock enable - ); - // End of OSERDESE2_inst instantiation - - // OBUFDS: Differential Output Buffer - // 7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OBUFDS OBUFDS_inst ( - .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port) - .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port) - .I(ddr3_clk) // Buffer input - ); - // End of OBUFDS_inst instantiation - - // PHY data and dm - generate - // data: oserdes -> odelay -> iobuf - for(gen_index = 0; gen_index < (DQ_BITS*LANES); gen_index = gen_index + 1) begin - // OSERDESE2: Output SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OSERDESE2 #( - .DATA_RATE_OQ("DDR"), // DDR, SDR - .DATA_RATE_TQ("BUF"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1) - .TRISTATE_WIDTH(1) - ) - OSERDESE2_data( - .OFB(oserdes_data[gen_index]), // 1-bit output: Feedback path for data - .OQ(), // 1-bit output: Data path output - .TQ(oserdes_dq_tri_control[gen_index]), - .CLK(i_ddr3_clk), // 1-bit input: High speed clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) - .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]), - .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]), - .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]), - .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]), - .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]), - .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]), - .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]), - .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]), - .T1(i_controller_dq_tri_control), - .TCE(1'b1), - .OCE(1'b1), // 1-bit input: Output data clock enable - .RST(sync_rst), // 1-bit input: Reset - // unused signals but were added here to make vivado happy - .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) - .SHIFTOUT2(), - .TBYTEOUT(), // 1-bit output: Byte group tristate - .TFB(), // 1-bit output: 3-state control - // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - .SHIFTIN1(0), - .SHIFTIN2(0), - // T1 - T4: 1-bit (each) input: Parallel 3-state inputs - .T2(0), - .T3(0), - .T4(0), - .TBYTEIN(0) - // 1-bit input: Byte group tristate - ); - // End of OSERDESE2_inst instantiation - - // ODELAYE2: Output Fixed or Variable Delay Element - // 7 Series - // Xilinx HDL Libraries Guide, version 13.4 - //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US - (* IODELAY_GROUP = 0 *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL - //Delay the DQ - // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps - ODELAYE2 #( - .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN) - .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE") - .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE - .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31) - .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0). - .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal - ) - ODELAYE2_data ( - .CNTVALUEOUT(), // 5-bit output: Counter value output - .DATAOUT(odelay_data[gen_index]), // 1-bit output: Delayed data/clock output - .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV - .CE(1'b0), // 1-bit input: Active high enable increment/decrement input - .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input - .CLKIN(1'b0), // 1-bit input: Clock delay input - .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input - .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input - .LD(i_controller_odelay_data_ld[gen_index/8]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or - // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN - .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data - .ODATAIN(oserdes_data[gen_index]), // 1-bit input: Output delay data input - .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input - ); - - // IOBUF: Single-ended Bi-directional Buffer - //All devices - // Xilinx HDL Libraries Guide, version 13.4 - IOBUF #( - .DRIVE(12), // Specify the output drive strength - .IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE" - .IOSTANDARD("SSTL15"), // Specify the I/O standard - .SLEW("FAST") // Specify the output slew rate - ) IOBUF_data ( - .O(read_dq[gen_index]),// Buffer output - .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port) - .I(odelay_data[gen_index]), // Buffer input - .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write - ); - - // IDELAYE2: Input Fixed or Variable Delay Element - // 7 Series - // Xilinx HDL Libraries Guide, version 13.4 - (* IODELAY_GROUP = 0 *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL - IDELAYE2 #( - .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN) - .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE") - .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE - .IDELAY_VALUE(DATA_IDELAY_TAP), //Input delay tap setting (0-31) - .PIPE_SEL("FALSE"), //Select pipelined mode, FALSE, TRUE - .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0). - .SIGNAL_PATTERN("DATA") //DATA, CLOCK input signal - ) - IDELAYE2_data ( - .CNTVALUEOUT(), // 5-bit output: Counter value output - .DATAOUT(idelay_data[gen_index]), // 1-bit output: Delayed data output - .C(i_controller_clk), // 1-bit input: Clock input - .CE(1'b0), // 1-bit input: Active high enable increment/decrement input - .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input - .CNTVALUEIN(i_controller_idelay_data_cntvaluein), // 5-bit input: Counter value input - .DATAIN(), //1-bit input: Internal delay data input - .IDATAIN(read_dq[gen_index]), // 1-bit input: Data input from the I/O - .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input - .LD(i_controller_idelay_data_ld[gen_index/8]), // 1-bit input: Load IDELAY_VALUE input - .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input - .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input - ); - // End of IDELAYE2_inst instantiation - - // End of IOBUF_inst instantiation - // ISERDESE2: Input SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - ISERDESE2 #( - .DATA_RATE("DDR"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1) - .INIT_Q1(1'b0), - .INIT_Q2(1'b0), - .INIT_Q3(1'b0), - .INIT_Q4(1'b0), - .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE - .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD - .NUM_CE(1),// Number of clock enables (1,2) - .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE) - // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1) - .SRVAL_Q1(1'b0), - .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), - .SRVAL_Q4(1'b0) - ) - ISERDESE2_data ( - .O(), - // 1-bit output: Combinatorial output - // Q1 - Q8: 1-bit (each) output: Registered data outputs - .Q1(o_controller_iserdes_data[(DQ_BITS*LANES)*7 + gen_index]),//56 - .Q2(o_controller_iserdes_data[(DQ_BITS*LANES)*6 + gen_index]), //48 - .Q3(o_controller_iserdes_data[(DQ_BITS*LANES)*5 + gen_index]), - .Q4(o_controller_iserdes_data[(DQ_BITS*LANES)*4 + gen_index]), - .Q5(o_controller_iserdes_data[(DQ_BITS*LANES)*3 + gen_index]), - .Q6(o_controller_iserdes_data[(DQ_BITS*LANES)*2 + gen_index]), - .Q7(o_controller_iserdes_data[(DQ_BITS*LANES)*1 + gen_index]), - .Q8(o_controller_iserdes_data[(DQ_BITS*LANES)*0 + gen_index]), - // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports - .SHIFTOUT1(), - .SHIFTOUT2(), - .BITSLIP(i_controller_bitslip[gen_index/8]), - // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to - // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1 - // to Q8 output ports will shift, as in a barrel-shifter operation, one - // position every time Bitslip is invoked (DDR operation is different from - // SDR). - // CE1, CE2: 1-bit (each) input: Data register clock enable inputs - .CE1(1'b1), - .CE2(1'b1), - .CLKDIVP(), // 1-bit input: TBD - // Clocks: 1-bit (each) input: ISERDESE2 clock input ports - .CLK(i_ddr3_clk), // 1-bit input: High-speed clock - .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" - // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity - .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion - .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion - // Input Data: 1-bit (each) input: ISERDESE2 data input ports - .D(), // 1-bit input: Data input - .DDLY(idelay_data[gen_index]), // 1-bit input: Serial data from IDELAYE2 - .OFB(), // 1-bit input: Data feedback from OSERDESE2 - .OCLKB(), // 1-bit input: High speed negative edge output clock - .RST(sync_rst), // 1-bit input: Active high asynchronous reset - // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports - .SHIFTIN1(), - .SHIFTIN2() - ); - // End of ISERDESE2_inst instantiation - - end - - // data mask: oserdes -> odelay -> obuf - for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin - // OSERDESE2: Output SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OSERDESE2 #( - .DATA_RATE_OQ("DDR"), // DDR, SDR - .DATA_RATE_TQ("BUF"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1) - .TRISTATE_WIDTH(1) - ) - OSERDESE2_dm( - .OFB(oserdes_dm[gen_index]), // 1-bit output: Feedback path for data - .OQ(), // 1-bit output: Data path output - .CLK(i_ddr3_clk), // 1-bit input: High speed clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) - .D1(i_controller_dm[gen_index + LANES*0]), - .D2(i_controller_dm[gen_index + LANES*1]), - .D3(i_controller_dm[gen_index + LANES*2]), - .D4(i_controller_dm[gen_index + LANES*3]), - .D5(i_controller_dm[gen_index + LANES*4]), - .D6(i_controller_dm[gen_index + LANES*5]), - .D7(i_controller_dm[gen_index + LANES*6]), - .D8(i_controller_dm[gen_index + LANES*7]), - .TCE(1'b0), - .OCE(1'b1), // 1-bit input: Output data clock enable - .RST(sync_rst), // 1-bit input: Reset - // unused signals but were added here to make vivado happy - .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) - .SHIFTOUT2(), - .TBYTEOUT(), // 1-bit output: Byte group tristate - .TFB(), // 1-bit output: 3-state control - .TQ(), // 1-bit output: 3-state control - // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - .SHIFTIN1(0), - .SHIFTIN2(0), - // T1 - T4: 1-bit (each) input: Parallel 3-state inputs - .T1(0), - .T2(0), - .T3(0), - .T4(0), - .TBYTEIN(0) - // 1-bit input: Byte group tristate - ); - // End of OSERDESE2_inst instantiation - - // ODELAYE2: Output Fixed or Variable Delay Element - // 7 Series - // Xilinx HDL Libraries Guide, version 13.4 - //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US - (* IODELAY_GROUP = 0 *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL - //Delay the DQ - // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps - ODELAYE2 #( - .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN) - .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE") - .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE - .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31) - .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0). - .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal - ) - ODELAYE2_dm ( - .CNTVALUEOUT(), // 5-bit output: Counter value output - .DATAOUT(odelay_dm[gen_index]), // 1-bit output: Delayed data/clock output - .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV - .CE(1'b0), // 1-bit input: Active high enable increment/decrement input - .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input - .CLKIN(1'b0), // 1-bit input: Clock delay input - .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input - .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input - .LD(i_controller_odelay_data_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or - // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN - .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data - .ODATAIN(oserdes_dm[gen_index]), // 1-bit input: Output delay data input - .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input - ); - - // OBUF: Single-ended Output Buffer - // 7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OBUF #( - //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard - .SLEW("FAST") // Specify the output slew rate - ) OBUF_dm ( - .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port) - .I(odelay_dm[gen_index]) // Buffer input - ); - // End of OBUF_inst instantiation - end - - //800MHz = - // dqs: odelay -> iobuf - for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin - - // ODELAYE2: Output Fixed or Variable Delay Element - // 7 Series - // Xilinx HDL Libraries Guide, version 13.4 - (* IODELAY_GROUP = 0 *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL - //Delay the DQ - ODELAYE2 #( - .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN) - .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") - .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE - .ODELAY_VALUE(DQS_ODELAY_TAP), // delay to align odelay_dqs to oserdes_dqs due to 600ps insertion delay: (1/800MHz - 600ps)/78.125ps = 8.32 taps - .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0). - .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal - ) - ODELAYE2_dqs ( - .CNTVALUEOUT(), // 5-bit output: Counter value output - .DATAOUT(odelay_dqs[gen_index]), // 1-bit output: Delayed data/clock output - .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV - .CE(1'b0), // 1-bit input: Active high enable increment/decrement input - .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input - .CLKIN(1'b0), // 1-bit input: Clock delay input - .CNTVALUEIN(i_controller_odelay_dqs_cntvaluein), // 5-bit input: Counter value input - .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input - .LD(i_controller_odelay_dqs_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or - // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN - .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data - .ODATAIN(oserdes_dqs[gen_index]), // 1-bit input: Output delay data input - .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input - ); - - // OSERDESE2: Output SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OSERDESE2 #( - .DATA_RATE_OQ("DDR"), // DDR, SDR - .DATA_RATE_TQ("BUF"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1) - .TRISTATE_WIDTH(1) - ) - OSERDESE2_dqs( - .OFB(oserdes_dqs[gen_index]), // 1-bit output: Feedback path for data - .OQ(), // 1-bit output: Data path output - .TQ(oserdes_dqs_tri_control[gen_index]), - .CLK(i_ddr3_clk), // 1-bit input: High speed clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) - .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series - .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)), - .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), - .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)), - .D5(1'b1 && i_controller_toggle_dqs), - .D6(1'b0 && i_controller_toggle_dqs), - .D7(1'b1 && i_controller_toggle_dqs), - .D8(1'b0 && i_controller_toggle_dqs), - .T1(i_controller_dqs_tri_control), - .TCE(1'b1), - .OCE(1'b1), // 1-bit input: Output data clock enable - .RST(sync_rst), // 1-bit input: Reset - // unused signals but were added here to make vivado happy - .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) - .SHIFTOUT2(), - .TBYTEOUT(), // 1-bit output: Byte group tristate - .TFB(), // 1-bit output: 3-state control - // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - .SHIFTIN1(0), - .SHIFTIN2(0), - // T1 - T4: 1-bit (each) input: Parallel 3-state inputs - .T2(0), - .T3(0), - .T4(0), - .TBYTEIN(0) - // 1-bit input: Byte group tristate - ); - // End of OSERDESE2_inst instantiation - - // IOBUFDS: Differential Bi-directional Buffer - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - IOBUFDS #( - //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE") - //.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE" - .IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET - //.SLEW("FAST") // Specify the output slew rate - ) IOBUFDS_inst ( - .O(read_dqs[gen_index]), // Buffer output - .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port) - .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port) - .I(odelay_dqs[gen_index]), // Buffer input - .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output - ); // End of IOBUFDS_inst instantiation - - - // IDELAYE2: Input Fixed or Variable Delay Element - // 7 Series - // Xilinx HDL Libraries Guide, version 13.4 - (* IODELAY_GROUP = 0 *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL - IDELAYE2 #( - .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN) - .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE") - .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE - .IDELAY_VALUE(DQS_IDELAY_TAP), //Input delay tap setting (0-31) - .PIPE_SEL("FALSE"), //Select pipelined mode, FALSE, TRUE - .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0). - .SIGNAL_PATTERN("DATA") //DATA, CLOCK input signal - ) - IDELAYE2_dqs ( - .CNTVALUEOUT(), // 5-bit output: Counter value output - .DATAOUT(idelay_dqs[gen_index]), // 1-bit output: Delayed data output - .C(i_controller_clk), // 1-bit input: Clock input - .CE(1'b0), // 1-bit input: Active high enable increment/decrement input - .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input - .CNTVALUEIN(i_controller_idelay_dqs_cntvaluein), // 5-bit input: Counter value input - .DATAIN(), //1-bit input: Internal delay data input - .IDATAIN(read_dqs[gen_index]), // 1-bit input: Data input from the I/O - .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input - .LD(i_controller_idelay_dqs_ld[gen_index]), // 1-bit input: Load IDELAY_VALUE input - .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input - .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input - ); - // End of IDELAYE2_inst instantiation - - // End of IOBUF_inst instantiation - // ISERDESE2: Input SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - ISERDESE2 #( - .DATA_RATE("DDR"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1) - .INIT_Q1(1'b0), - .INIT_Q2(1'b0), - .INIT_Q3(1'b0), - .INIT_Q4(1'b0), - .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE - .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD - .NUM_CE(1),// Number of clock enables (1,2) - .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE) - // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1) - .SRVAL_Q1(1'b0), - .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), - .SRVAL_Q4(1'b0) - ) - ISERDESE2_dqs ( - .O(), - // 1-bit output: Combinatorial output - // Q1 - Q8: 1-bit (each) output: Registered data outputs - .Q1(o_controller_iserdes_dqs[LANES*gen_index + 7]), - .Q2(o_controller_iserdes_dqs[LANES*gen_index + 6]), - .Q3(o_controller_iserdes_dqs[LANES*gen_index + 5]), - .Q4(o_controller_iserdes_dqs[LANES*gen_index + 4]), - .Q5(o_controller_iserdes_dqs[LANES*gen_index + 3]), - .Q6(o_controller_iserdes_dqs[LANES*gen_index + 2]), - .Q7(o_controller_iserdes_dqs[LANES*gen_index + 1]), - .Q8(o_controller_iserdes_dqs[LANES*gen_index + 0]), - // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports - .SHIFTOUT1(), - .SHIFTOUT2(), - .BITSLIP(i_controller_bitslip[gen_index]), - // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to - // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1 - // to Q8 output ports will shift, as in a barrel-shifter operation, one - // position every time Bitslip is invoked (DDR operation is different from - // SDR). - // CE1, CE2: 1-bit (each) input: Data register clock enable inputs - .CE1(1'b1), - .CE2(1'b1), - .CLKDIVP(), // 1-bit input: TBD - // Clocks: 1-bit (each) input: ISERDESE2 clock input ports - .CLK(i_ddr3_clk), // 1-bit input: High-speed clock - .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" - // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity - .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion - .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion - // Input Data: 1-bit (each) input: ISERDESE2 data input ports - .D(), // 1-bit input: Data input - .DDLY(idelay_dqs[gen_index]), // 1-bit input: Serial data from IDELAYE2 - .OFB(), // 1-bit input: Data feedback from OSERDESE2 - .OCLKB(), // 1-bit input: High speed negative edge output clock - .RST(sync_rst), // 1-bit input: Active high asynchronous reset - // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports - .SHIFTIN1(), - .SHIFTIN2() - ); - // End of ISERDESE2_inst instantiation - - - //ISERDES train - // End of IOBUF_inst instantiation - // ISERDESE2: Input SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - ISERDESE2 #( - .DATA_RATE("DDR"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1) - .INIT_Q1(1'b0), - .INIT_Q2(1'b0), - .INIT_Q3(1'b0), - .INIT_Q4(1'b0), - .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE - .IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD - .NUM_CE(1),// Number of clock enables (1,2) - .OFB_USED("TRUE"), // Select OFB path (FALSE, TRUE) - // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1) - .SRVAL_Q1(1'b0), - .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), - .SRVAL_Q4(1'b0) - ) - ISERDESE2_train ( - .O(), - // 1-bit output: Combinatorial output - // Q1 - Q8: 1-bit (each) output: Registered data outputs - .Q1(o_controller_iserdes_bitslip_reference[gen_index*LANES + 7]), - .Q2(o_controller_iserdes_bitslip_reference[gen_index*LANES + 6]), - .Q3(o_controller_iserdes_bitslip_reference[gen_index*LANES + 5]), - .Q4(o_controller_iserdes_bitslip_reference[gen_index*LANES + 4]), - .Q5(o_controller_iserdes_bitslip_reference[gen_index*LANES + 3]), - .Q6(o_controller_iserdes_bitslip_reference[gen_index*LANES + 2]), - .Q7(o_controller_iserdes_bitslip_reference[gen_index*LANES + 1]), - .Q8(o_controller_iserdes_bitslip_reference[gen_index*LANES + 0]), - // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports - .SHIFTOUT1(), - .SHIFTOUT2(), - .BITSLIP(i_controller_bitslip[gen_index]), - // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to - // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1 - // to Q8 output ports will shift, as in a barrel-shifter operation, one - // position every time Bitslip is invoked (DDR operation is different from - // SDR). - // CE1, CE2: 1-bit (each) input: Data register clock enable inputs - .CE1(1'b1), - .CE2(1'b1), - .CLKDIVP(), // 1-bit input: TBD - // Clocks: 1-bit (each) input: ISERDESE2 clock input ports - .CLK(i_ddr3_clk), // 1-bit input: High-speed clock - .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" - // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity - .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion - .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion - // Input Data: 1-bit (each) input: ISERDESE2 data input ports - .D(), // 1-bit input: Data input - .DDLY(), // 1-bit input: Serial data from IDELAYE2 - .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit input: Data feedback from OSERDESE2 - .OCLKB(), // 1-bit input: High speed negative edge output clock - .RST(sync_rst), // 1-bit input: Active high asynchronous reset - // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports - .SHIFTIN1(), - .SHIFTIN2() - ); - // End of ISERDESE2_inst instantiation - - // OSERDESE2: Output SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OSERDESE2 #( - .DATA_RATE_OQ("DDR"), // DDR, SDR - .DATA_RATE_TQ("BUF"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1) - .TRISTATE_WIDTH(1) - ) - OSERDESE2_train( - .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit output: Feedback path for data - .OQ(), // 1-bit output: Data path output - .CLK(i_ddr3_clk), // 1-bit input: High speed clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) - .D1(1'b0), - .D2(1'b0), - .D3(1'b0), - .D4(1'b0), - .D5(1'b1), - .D6(1'b1), - .D7(1'b1), - .D8(1'b1), - .OCE(1'b1), // 1-bit input: Output data clock enable - .RST(sync_rst), // 1-bit input: Reset - // unused signals but were added here to make vivado happy - .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) - .SHIFTOUT2(), - .TBYTEOUT(), // 1-bit output: Byte group tristate - .TFB(), // 1-bit output: 3-state control - .TQ(), // 1-bit output: 3-state control - // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - .SHIFTIN1(0), - .SHIFTIN2(0), - // T1 - T4: 1-bit (each) input: Parallel 3-state inputs - .T1(0), - .T2(0), - .T3(0), - .T4(0), - .TBYTEIN(0), - // 1-bit input: Byte group tristate - .TCE(0) - // 1-bit input: 3-state clock enable - ); - // End of OSERDESE2_inst instantiation - - - end - endgenerate - - /* - // OSERDESE2: Output SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OSERDESE2 #( - .DATA_RATE_OQ("DDR"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b1) // Initial value of OQ output (1'b0,1'b1) - ) - OSERDESE2_train( - .OFB(test_OFB), // 1-bit output: Feedback path for data - .OQ(), // 1-bit output: Data path output - .CLK(i_ddr3_clk), // 1-bit input: High speed clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) - .D1(1'b0), - .D2(1'b0), - .D3(1'b0), - .D4(1'b0), - .D5(1'b1), - .D6(1'b1), - .D7(1'b1), - .D8(1'b1), - .OCE(1'b1), // 1-bit input: Output data clock enable - .RST(sync_rst) // 1-bit input: Reset - ); - // End of OSERDESE2_inst instantiation - */ - /* - // OSERDESE2: Output SERial/DESerializer with bitslip - //7 Series - // Xilinx HDL Libraries Guide, version 13.4 - OSERDESE2 #( - .DATA_RATE_OQ("DDR"), // DDR, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b1) // Initial value of OQ output (1'b0,1'b1) - ) - OSERDESE2_dqs( - .OFB(oserdes_dqs), // 1-bit output: Feedback path for data - .OQ(), // 1-bit output: Data path output - .CLK(i_ddr3_clk), // 1-bit input: High speed clock - .CLKDIV(i_controller_clk), // 1-bit input: Divided clock - // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) - .D1(1'b1 && i_controller_toggle_dqs), - .D2(1'b0 && i_controller_toggle_dqs), - .D3(1'b1 && i_controller_toggle_dqs), - .D4(1'b0 && i_controller_toggle_dqs), - .D5(1'b1 && i_controller_toggle_dqs), - .D6(1'b0 && i_controller_toggle_dqs), - .D7(1'b1 && i_controller_toggle_dqs), - .D8(1'b0 && i_controller_toggle_dqs), - .OCE(1'b1), // 1-bit input: Output data clock enable - .RST(sync_rst) // 1-bit input: Reset - ); - // End of OSERDESE2_inst instantiation - */ - // IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control - // 7 Series - // Xilinx HDL Libraries Guide, version 13.4 - (* IODELAY_GROUP = 0 *) // Specifies group name for associated IDELAYs/ODELAYs and IDELAYCTRL - IDELAYCTRL IDELAYCTRL_inst ( - .RDY(o_controller_idelayctrl_rdy), // 1-bit output: Ready output - .REFCLK(i_ref_clk), // 1-bit input: Reference clock input.The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet. - .RST(sync_rst) // 1-bit input: Active high reset input, To ,Minimum Reset pulse width is 52ns - ); - // End of IDELAYCTRL_inst instantiation - - - endmodule diff --git a/delete_later/rtl/genclk.v b/delete_later/rtl/genclk.v deleted file mode 100644 index 60b74c7..0000000 --- a/delete_later/rtl/genclk.v +++ /dev/null @@ -1,134 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: genclk.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: To generate a clock using digital logic, but one that switches -// at the right speed overall. -// -// This particular component takes the desired clock stepping word -// (2^32 / desired_frequency) and uses it to generate a clock at the -// desired_frequency rate. -// -// The output itself is 8 steps of that clock, necessitating an 8x -// output serdes to create a clock from this output word. As a result, -// the phase error on the output of this routine will be (at a maximum) -// 1/16th the duration of i_clk--allowing more flexibility in clock -// generation. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// }}} -module genclk #( - parameter BW=32, // The bus width - localparam UPSAMPLE=8 // Upsample factor - ) ( - // {{{ - input wire i_clk, - input wire [(BW-1):0] i_delay, - output reg [(UPSAMPLE-1):0] o_word, - output reg o_stb - // }}} - ); - - // Local declarations - // {{{ - reg [(BW-1):0] counter [0:(UPSAMPLE-1)]; - reg [(BW-1):0] r_delay; - - reg [(BW-1):0] times_three; - reg [(BW-1):0] times_five; - reg [(BW-1):0] times_seven; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Helpers: times_three, five, and seven - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - times_three <= { i_delay[(BW-2):0], 1'b0 } + i_delay; - - always @(posedge i_clk) - times_five <= { i_delay[(BW-3):0], 2'b0 } + i_delay; - - always @(posedge i_clk) - times_seven <= { i_delay[(BW-4):0], 3'b0 } - i_delay; - - // Keep these all aligned. - always @(posedge i_clk) - r_delay <= i_delay; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Generate 8-phases of a counter that adds i_delay on each 8th clock - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) // Times one - counter[1] <= counter[0] + r_delay; - - always @(posedge i_clk) // Times two - counter[2] <= counter[0] + { r_delay[(BW-2):0], 1'b0 }; - - always @(posedge i_clk) // Times three - counter[3] <= counter[0] + times_three; - - always @(posedge i_clk) // Times four - counter[4] <= counter[0] + { r_delay[(BW-3):0], 2'b0 }; - - always @(posedge i_clk) // Times five - counter[5] <= counter[0] + times_five; - - always @(posedge i_clk) - counter[6] <= counter[0] + { times_three[(BW-2):0], 1'b0 }; - - always @(posedge i_clk) - counter[7] <= counter[0] + times_seven; - - always @(posedge i_clk) // Times eight---and generating the next clk wrd - { o_stb, counter[0] } <= counter[0] + { r_delay[(BW-4):0], 3'h0 }; - - always @(posedge i_clk) - o_word <= { // High order bit is "first" - counter[1][(BW-1)], - counter[2][(BW-1)], - counter[3][(BW-1)], - counter[4][(BW-1)], - counter[5][(BW-1)], - counter[6][(BW-1)], - counter[7][(BW-1)], - counter[0][(BW-1)] - }; - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/axishdmi.v b/delete_later/rtl/hdmi/axishdmi.v deleted file mode 100644 index 295018b..0000000 --- a/delete_later/rtl/hdmi/axishdmi.v +++ /dev/null @@ -1,804 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: axishdmi -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Generates the timing signals (not the clock) for an outgoing -// video signal, and then encodes the incoming pixels into -// an HDMI data stream. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module axishdmi #( - // {{{ - parameter HW=12, - VW=12, - parameter [0:0] OPT_RESYNC_ON_VLAST = 1'b0, - // HDMI *only* works with 24-bit color, using 8-bits per color - localparam BITS_PER_COLOR = 8, - localparam BPC = BITS_PER_COLOR, - BITS_PER_PIXEL = 3 * BPC, - BPP = BITS_PER_PIXEL - // }}} - ) ( - // {{{ - input wire i_pixclk, - // Verilator lint_off SYNCASYNCNET - input wire i_reset, - // Verilator lint_on SYNCASYNCNET - // - // AXI Stream interface - // {{{ - input wire i_valid, - output reg o_ready, - input wire i_hlast, - input wire i_vlast, - input wire [BPP-1:0] i_rgb_pix, - // }}} - // - // Video mode information - // {{{ - input wire [HW-1:0] i_hm_width, - input wire [HW-1:0] i_hm_porch, - input wire [HW-1:0] i_hm_synch, - input wire [HW-1:0] i_hm_raw, - // - input wire [VW-1:0] i_vm_height, - input wire [VW-1:0] i_vm_porch, - input wire [VW-1:0] i_vm_synch, - input wire [VW-1:0] i_vm_raw, - // }}} - // - // HDMI outputs - // {{{ - output wire [9:0] o_red, - output wire [9:0] o_grn, - output wire [9:0] o_blu - // }}} - // }}} - ); - - // Register declarations - // {{{ - reg r_newline, r_newframe, lost_sync; - reg vsync, hsync; - reg [1:0] hdmi_type; - wire [3:0] hdmi_ctl; - reg [11:0] hdmi_data; - reg [7:0] red_pixel, grn_pixel, blu_pixel; - reg pre_line; - reg first_frame; - - wire w_rd; - wire [BPC-1:0] i_red, i_grn, i_blu; - assign i_red = i_rgb_pix[3*BPC-1:2*BPC]; - assign i_grn = i_rgb_pix[2*BPC-1: BPC]; - assign i_blu = i_rgb_pix[ BPC-1:0]; - - reg [HW-1:0] hpos; - reg [VW-1:0] vpos; - reg hrd, vrd; - reg pix_reset; - reg [1:0] pix_reset_pipe; - wire w_external_sync; -`ifdef FORMAL - wire [47:0] f_vmode, f_hmode; -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Synchronize the reset release - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial { pix_reset, pix_reset_pipe } = -1; - always @(posedge i_pixclk, posedge i_reset) - if (i_reset) - { pix_reset, pix_reset_pipe } <= -1; - else - { pix_reset, pix_reset_pipe } <= { pix_reset_pipe, 1'b0 }; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Horizontal line counting - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // hpos, r_newline, hsync, hrd - // {{{ - initial hpos = 0; - initial r_newline = 0; - initial hsync = 0; - initial hrd = 1; - always @(posedge i_pixclk) - if (pix_reset) - begin - // {{{ - hpos <= 0; - r_newline <= 1'b0; - hsync <= 1'b0; - hrd <= 1; - // }}} - end else if (w_external_sync) - begin - hpos <= i_hm_width-1; - r_newline <= 0; - hrd <= 0; - hsync <= 1'b0; - end else begin - // {{{ - hrd <= (hpos < i_hm_width-2) - ||(hpos >= i_hm_raw-2); - if (hpos < i_hm_raw-1'b1) - hpos <= hpos + 1'b1; - else - hpos <= 0; - r_newline <= (hpos == i_hm_width-3); - hsync <= (hpos >= i_hm_porch-1'b1)&&(hpos= i_vm_porch-1'b1)&&(vpos= i_hm_raw - 1) - hdmi_type <= VIDEO_DATA; - else if (hpos < i_hm_width - 1) - hdmi_type <= VIDEO_DATA; - else if (hpos >= i_hm_raw - 1-GUARD_PIXELS) - hdmi_type <= GUARD; - else - hdmi_type <= CTL_PERIOD; - end else - hdmi_type <= CTL_PERIOD; - - assign hdmi_ctl = 4'h1; - // }}} - - // hdmi_data - // {{{ - always @(*) - begin - hdmi_data[1:0] = { vsync, hsync }; - hdmi_data[11:2] = 0; - end - // }}} - - // TMDS encoding - // {{{ -`ifdef FORMAL - (* anyseq *) reg [9:0] w_blu, w_grn, w_red; - // - // Verific complains of logic loops within tmdsencode. Since the TMDS - // encoder isn't really a part of our formal proof, we can cut it out - // here and replace it's results with ... whatever we want ... just to - // get the proof to pass. - // - - assign o_red = w_red; - assign o_grn = w_grn; - assign o_blu = w_blu; -`else - // Channel 0 = blue - tmdsencode #(.CHANNEL(2'b00)) hdmi_encoder_ch0(i_pixclk, - hdmi_type, { vsync, hsync }, - hdmi_data[3:0], blu_pixel, o_blu); - - // Channel 1 = green - tmdsencode #(.CHANNEL(2'b01)) hdmi_encoder_ch1(i_pixclk, - hdmi_type, hdmi_ctl[1:0], - hdmi_data[7:4], grn_pixel, o_grn); - - // Channel 2 = red - tmdsencode #(.CHANNEL(2'b10)) hdmi_encoder_ch2(i_pixclk, - hdmi_type, hdmi_ctl[3:2], - hdmi_data[11:8], red_pixel, o_red); -`endif - // }}} - - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties for verification purposes -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam [1:0] DATA_ISLAND = 2'b10; - localparam PREGUARD_CONTROL = 6; - reg f_past_valid; - reg [47:0] f_last_vmode, f_last_hmode; - reg f_stable_mode; - reg [3:0] f_ctrl_length; - reg [1:0] f_video_start, f_packet_start; - - //////////////////////////////////////////////////////////////////////// - // - // Reset assumptions - // - initial f_past_valid = 1'b0; - always @(posedge i_pixclk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - //////////////////////////////////////////////////////////////////////// - // - // AXI Stream assumptions - // - always @(posedge i_pixclk) - if (f_past_valid && !$past(pix_reset)) - begin - if ($past(i_valid && !o_ready)) - begin - assume(i_valid); - assume($stable(i_hlast)); - assume($stable(i_vlast)); - assume($stable(i_rgb_pix)); - end - end - - generate if (OPT_RESYNC_ON_VLAST) - begin : GEN_VIDCHECK - // {{{ - localparam LGFRAME = (HW > VW) ? HW : VW; - wire f_vlast, f_hlast, f_sof, f_known_height; - wire [LGFRAME-1:0] f_xpos, f_ypos; - reg [LGFRAME-1:0] f_width, f_height; - - always @(posedge i_pixclk) - if (!pix_reset && $past(pix_reset)) - assume(!i_valid); - - always @(*) - begin - f_width = 0; f_height = 0; - f_width[HW-1:0] = i_hm_width; - f_height[VW-1:0] = i_vm_height; - end - - faxivideo #( - // {{{ - .LGDIM(LGFRAME), .PW(BPP), .OPT_TUSER_IS_SOF(1'b0), - .OPT_SOURCE(1'b0) - // }}} - ) fvid ( - // {{{ - .i_clk(i_pixclk), .i_reset_n(!pix_reset), - // - .S_VID_TVALID(i_valid && !lost_sync), .S_VID_TREADY(o_ready), - .S_VID_TDATA(i_rgb_pix),.S_VID_TLAST(i_hlast&& i_vlast), - .S_VID_TUSER(i_hlast), - .i_width(f_width), .i_height(f_height), - .o_xpos(f_xpos), .o_ypos(f_ypos), - .f_known_height(f_known_height), - .o_hlast(f_hlast), .o_vlast(f_vlast), .o_sof(f_sof) - // }}} - ); - - always @(posedge i_pixclk) - if (!i_reset && !lost_sync) - begin - if (w_rd) - assume(i_valid); - - if (f_xpos != 0) - begin - assert(hpos == f_xpos - 1); - assert(vpos == f_ypos); - end else begin - assert(hpos <= 1 || hpos >= f_width-1 - || vpos >= i_vm_height); - if (hpos < i_hm_width) - begin - assert(hpos == i_hm_width-1 - || vpos == f_ypos - || (f_ypos == 0 && vpos >= f_height)); - end else if (hpos < i_hm_porch) - begin - if (vpos < f_height-1) - begin - assert(vpos + 1== f_ypos); - end else begin - assert(f_ypos == 0); - end - end else begin - if (vpos <= f_height-1) - begin - assert(vpos == f_ypos); - end else begin - assert(f_ypos == 0); - end - end - end - - if (f_ypos != 0) - begin - end else - assert(vpos == 0 || vpos >= f_height -1); - end else if (!i_reset) - begin - assert(f_xpos == 0); - assert(f_ypos == 0); - end - - always @(posedge i_pixclk) - if (!i_reset && first_frame) - begin - assert(lost_sync); - assert(!f_known_height); - assert(f_xpos == 0); - assert(f_ypos == 0); - end - - always @(*) - assume(i_hlast == f_hlast); - - always @(*) - if (!f_vlast) - assume(!i_vlast); - else if (f_hlast) - assume(i_vlast == f_hlast); - // }}} - end endgenerate - - //////////////////////////////////////////////////////////////////////// - // - // Mode-line assumptions - // - always @(*) - begin - assume(12'h10 < i_hm_width); - assume(i_hm_width < i_hm_porch); - assume(i_hm_porch < i_hm_synch); - assume(i_hm_synch < i_hm_raw); - assume(i_hm_porch+14 < i_hm_raw); - - assume(12'h10 < i_vm_height); - assume(i_vm_height < i_vm_porch); - assume(i_vm_porch < i_vm_synch); - assume(i_vm_synch < i_vm_raw); - end - - assign f_hmode = { i_hm_width, i_hm_porch, i_hm_synch, i_hm_raw }; - assign f_vmode = { i_vm_height, i_vm_porch, i_vm_synch, i_vm_raw }; - - always @(posedge i_pixclk) - f_last_vmode <= f_vmode; - always @(posedge i_pixclk) - f_last_hmode <= f_hmode; - - always @(*) - f_stable_mode = (f_last_vmode == f_vmode)&&(f_last_hmode == f_hmode); - - always @(*) - if (!pix_reset) - assume(f_stable_mode); - - //////////////////////////////////////////////////////////////////////// - // - // Pixel counting - // - - always @(posedge i_pixclk) - if ((!f_past_valid)||($past(pix_reset))) - begin - assert(hpos == 0); - assert(vpos == 0); - assert(first_frame); - end - - always @(posedge i_pixclk) - if ((f_past_valid)&&(!$past(pix_reset))&&(!pix_reset) - &&(f_stable_mode)&&($past(f_stable_mode))) - begin - if ($past(w_external_sync)) - begin - assert(hpos == i_hm_width); - end else if ($past(hpos >= i_hm_raw-1'b1)) - begin - assert(hpos == 0); - end else - // The horizontal position counter should increment - assert(hpos == $past(hpos)+1'b1); - - // The vertical position counter should increment - if ($past(w_external_sync)) - begin - end else if (hpos == i_hm_porch) - begin - if ($past(vpos >= i_vm_raw-1'b1)) - begin - assert(vpos == 0); - end else - assert(vpos == $past(vpos)+1'b1); - end else - assert(vpos == $past(vpos)); - - // For induction purposes, we need to insist that both - // horizontal and vertical counters stay within their - // required ranges - assert(hpos < i_hm_raw); - assert(vpos < i_vm_raw); - - // If we are less than the data width for both horizontal - // and vertical, then we should be asserting we are in a - // valid data cycle - // if ((hpos < i_hm_width)&&(vpos < i_vm_height) - // &&(!first_frame)) - // assert(w_rd); - // else - // assert(!w_rd); - - // - // The horizontal sync should only be valid between positions - // i_hm_porch <= hpos < i_hm_sync, invalid at all other times - // - if (hpos < i_hm_porch) - begin - assert(!hsync); - end else if (hpos < i_hm_synch) - begin - assert(hsync); - end else - assert(!hsync); - - // Same thing for vertical - if (vpos < i_vm_porch) - begin - assert(!vsync); - end else if (vpos < i_vm_synch) - begin - assert(vsync); - end else - assert(!vsync); - - // At the end of every horizontal line cycle, we assert - // a new line - if (hpos == i_hm_width-2) - begin - assert(r_newline); - end else - assert(!r_newline); - - // At the end of every vertical frame cycle, we assert - // a new frame, but only on the newline measure - if ((vpos == i_vm_height-1'b1)&&(r_newline)) - begin - assert(r_newframe); - end else - assert(!r_newframe); - end - - ////////////////////////////// - // - // HDMI Specific properties - // - ////////////////////////////// - - always @(posedge i_pixclk) - if (pix_reset) - f_ctrl_length <= 4'hf; - else if (hdmi_type != CTL_PERIOD) - f_ctrl_length <= 0; - else if (f_ctrl_length < 4'hf) - f_ctrl_length <= f_ctrl_length + 1'b1; - - initial f_video_start = 2'b01; - always @(posedge i_pixclk) - if (pix_reset) - f_video_start = 2'b01; - else if ((f_video_start == 2'b00) - &&(f_ctrl_length >= 4'hc)&&(hdmi_type == GUARD) - &&(hdmi_ctl == 4'h1)) - f_video_start <= 2'b1; - else if ((f_video_start == 2'b01)&&(hdmi_type == GUARD) - &&(hdmi_ctl == 4'h1)) - f_video_start <= 2'b10; - else - f_video_start <= 2'b00; - - always @(posedge i_pixclk) - if ((f_ctrl_length >= 4'hc)&&(hdmi_type == GUARD)) - f_packet_start <= 2'b1; - else if ((f_packet_start == 2'b1)&&(hdmi_type == GUARD)) - f_packet_start <= 2'b10; - else - f_packet_start <= 2'b00; - - always @(posedge i_pixclk) - if ((f_past_valid)&&(!$past(pix_reset))) - begin - if (($past(hdmi_type != VIDEO_DATA)) - &&(f_video_start != 2'b10)) - assert(hdmi_type != VIDEO_DATA); - end - - always @(posedge i_pixclk) - if ((f_past_valid)&&(!$past(pix_reset))&&(!pix_reset)) - begin - if ($past(w_external_sync)) - begin - end else if ((hpos < i_hm_width)&&(vpos < i_vm_height)) - begin - assert(hdmi_type == VIDEO_DATA); - end else - assert(hdmi_type != VIDEO_DATA); - if (!$past(first_frame)) - assert($past(w_rd) == (hdmi_type == VIDEO_DATA)); - - if (vpos < i_vm_height) - begin - if (hpos < i_hm_width) - assert(hdmi_type == VIDEO_DATA); - if (hpos >= (i_hm_raw-GUARD_PIXELS)) - begin - assert(hdmi_type == GUARD); - end else if (hpos >= (i_hm_raw-GUARD_PIXELS-PREGUARD_CONTROL)) - assert((hdmi_type == CTL_PERIOD) - &&(hdmi_ctl == 4'h1)); - end - end - - // always @(posedge i_pixclk) - // if ((f_past_valid)&&(!$past(i_reset))) - // assert(o_rd == (hdmi_type == VIDEO_DATA)); - -`ifdef VERIFIC - // {{{ - sequence VIDEO_PREAMBLE; - (hdmi_type == CTL_PERIOD) [*2] - ##1 ((hdmi_type == CTL_PERIOD)&&(hdmi_ctl == 4'h1)) [*10] - ##1 (hdmi_type == GUARD) [*2]; - endsequence - - assume property (@(posedge i_pixclk) - VIDEO_PREAMBLE - |=> (hdmi_type == VIDEO_DATA)&&(hpos == 0)&&(vpos == 0)); - - // assert property (@(posedge i_pixclk) - // disable iff (pix_reset) - // ((hdmi_type != VIDEO_DATA) throughout (not VIDEO_PREAMBLE))); - - // - // Data Islands - // - sequence DATA_PREAMBLE; - (hdmi_type == CTL_PERIOD) [*2] - ##1 ((hdmi_type == CTL_PERIOD)&&(hdmi_ctl == 4'h5)) [*10] - ##1 (hdmi_type == GUARD) [*2]; - endsequence - - assert property (@(posedge i_pixclk) - disable iff (pix_reset) - (DATA_PREAMBLE) - |=> 0 && (hdmi_type == DATA_ISLAND)[*64] - ##1 0 && (hdmi_type == GUARD) [*2]); - - // assert property (@(posedge i_pixclk) - // disable iff (pix_reset) - // ((hdmi_type != DATA_ISLAND) throughout (not DATA_PREAMBLE)) - // |=> (hdmi_type != DATA_ISLAND)); - - // }}} -`endif -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/axisvoverlay.v b/delete_later/rtl/hdmi/axisvoverlay.v deleted file mode 100644 index 5ed75ed..0000000 --- a/delete_later/rtl/hdmi/axisvoverlay.v +++ /dev/null @@ -1,2070 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: axisvoverlay.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Overlay a second video stream on top of a first one, producing -// an outgoing video stream. -// -// Inputs: -// Primary video: -// Can be from a camera or a memory/frame buffer driving a display. -// The assumption is made that the speed can be controlled by -// the downstream/output video port. (i.e., hold READY high if -// this is coming from a camera, or toggle it if/when the outgoing -// display is/isn't ready.) -// Secondary (overlay) video -// May or may not be present. Must be able to handle stalls, so -// must be driven from memory. The primary video and associated -// output interface drives drive the speed of the interface. -// The design will report an error if the secondary video ever -// gets out of sync. -// -// Outputs: -// Outgoing AXI Stream video stream -// To be produced at all costs. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module axisvoverlay #( - // {{{ - // LGFRAME: Control the number of bits required in the two - // {{{ - // position counters. If there will never be more than 2047 - // horizontal positions, then this number never need be more - // than 11. - parameter LGFRAME = 11, - // }}} - // ALPHA_BITS: Number of alpha bits in the overlay channel - // {{{ - // If zero, the overlay will always replace the primary when - // present. If one, then the overlay will only replace the - // primary when the alpha bit is 1. If greater than 1, then - // the alpha bits are used to scale both primary, by 1-alpha, - // and overlay, by alpha, before summing the two together. - // This allows the generation of a gradient effect if desired. - parameter ALPHA_BITS = 1, - // }}} - // COLORS: Number of color components to apply alpha mixing to - // {{{ - // While you might think of this as nominally 3, REG+GRN+BLU, - // it could be set to 6 (RGB, RGB), or even 9 (RGB, RGB, RGB), - // if you want to share alpha across multiple pixels. - parameter COLORS = 3, - // }}} - // BITS_PER_PIXEL: Bits per color component - // {{{ - parameter BITS_PER_PIXEL = 8, - localparam BPP = BITS_PER_PIXEL, - parameter DATA_WIDTH = COLORS * BITS_PER_PIXEL, - localparam DW = DATA_WIDTH, - // }}} - // OPT_TUSER_IS_SOF: This is the normal video mode, as defined - // {{{ - // by Xilinx's documentation. TUSER = the start of frame - // signal. This makes TUSER true for the one pixel when - // X = Y == 0. TLAST is then used to reference the last item - // in a line. Set this to 1 for best compatibility with other - // video cores for this reason. Unfortunately, this makes - // our processing below more challenging. Therefore, I offer - // another option: TLAST == the last pixel in the frame, when - // X == WIDTH -1 && Y == HEIGHT-1. This is easier to work with - // internally, and requires less logic. Both are tested. - parameter [0:0] OPT_TUSER_IS_SOF = 1'b1, - // }}} - // OPT_LINE_BREAK: If set, then we force READY to be low for - // {{{ - // one clock cycle following every line break (HLAST). This - // allows our pointers to recover and the in_overlay flag to - // be calculated with seven fewer logic operations on the - // critical path between clock ticks. This should help the - // design pass timing in a high speed environment. - parameter [0:0] OPT_LINE_BREAK = 1'b0 - // }}} - // }}} - ) ( - // {{{ - input wire ACLK, ARESETN, - // Config inputs - // {{{ - // i_enable: if true, apply the overlay to the primary channel - // {{{ - input wire i_enable, - // }}} - // i_hpos, i_vpos: Describe the location of the top-left corner - // {{{ - // of the overlay. This will allow the overlay position to be - // adjusted as necessary. The design (currently) does not - // allow the overlay to be positioned partially off screen to - // either top or left, although running off screen to right or - // bottom should be okay as long as there's enough bandwidth - // to allow it. - input wire [LGFRAME-1:0] i_hpos, i_vpos, - // }}} - output wire o_err, - // }}} - // Primary video input - // {{{ - input wire S_PRI_TVALID, - output wire S_PRI_TREADY, - input wire [DW-1:0] S_PRI_TDATA, - input wire S_PRI_TLAST, // HLAST - input wire S_PRI_TUSER, // SOF - // }}} - // Secondary (overlap) video input - // {{{ - input wire S_OVW_TVALID, - output wire S_OVW_TREADY, - input wire [DW+ALPHA_BITS-1:0] S_OVW_TDATA, - input wire S_OVW_TLAST, // HLAST - input wire S_OVW_TUSER, // SOF - // }}} - // Video output - // {{{ - output reg M_VID_TVALID, - input wire M_VID_TREADY, - output reg [DW-1:0] M_VID_TDATA, - output reg M_VID_TLAST, // HLAST - output reg M_VID_TUSER // SOF - // }}} - // }}} - ); - - // Local declarations - // {{{ - localparam [ALPHA_BITS:0] // OPAQUE = (1< i_vpos) - ||(prvpos == i_vpos && prhpos > i_hpos))) - in_frame <= 0; - - if (pskd_valid && pskd_ready) - begin - if (pskd_vlast) - in_frame <= (i_vpos == 0); - else if (pskd_hlast && !in_frame) - in_frame <= (i_vpos == prvpos + 1); - end - end -`ifdef FORMAL - // {{{ - always @(posedge ACLK) - if (ARESETN && !frame_err) - begin - if (ovw_eof && f_pri_vpos != i_vpos) - assert(!in_frame || (i_hpos >= f_vid_width)); - end - - always @(posedge ACLK) - if (ARESETN && !frame_err // && !w_frame_err - && (f_pri_known && $past(f_pri_known)) - && (f_ovw_known && $past(f_ovw_known) - && !f_ovw_sof && !$past(f_ovw_sof) - && (lines_per_frame != 0) - && $stable(lines_per_frame)) - ) - begin - if (in_overlay) - assert(in_frame); - - if (f_pri_vpos < i_vpos) - begin - assert(!in_frame); - end else if (f_pri_vpos - >= { 1'b0, i_vpos } + { 1'b0, f_ovw_height }) - begin - // Was ... if (f_sum_ypos != prvpos) - assert(!in_frame - // It is possible that we passed the end of the - // primary line, but not (yet) the end of the - // overlay line. In this case, we'd be on the - // last overline of the overlay frame, and we - // wouldn't have come across the EOL yet. - || ((f_pri_vpos == { 1'b0, i_vpos } - + { 1'b0, f_ovw_height }) - && !ovw_eol)); - end else if ({ 1'b0, f_pri_vpos } + 1 - == { 1'b0, i_vpos }+{ 1'b0, f_ovw_height }) - begin - assert(in_frame != ovw_eof); - end else begin - assert(in_frame); - end - end - // }}} -`endif - // }}} - - // in_overlay - // {{{ - always @(posedge ACLK) - if (!ARESETN) - in_overlay <= 0; - else if (pskd_valid && pskd_ready) - begin - if (pskd_vlast) - in_overlay <= (i_hpos == 0) && (i_vpos == 0); - else if (pskd_hlast) - begin - in_overlay <= 0; - if (in_frame && !ovw_eof) - in_overlay <= !ovskd_vlast; - if (i_vpos == prvpos + 1) - in_overlay <= 1'b1; - - if (i_hpos != 0) - in_overlay <= 0; - end else if (ovskd_hlast && in_overlay) - in_overlay <= 0; - else if (prhpos + 1 == i_hpos) - in_overlay <= in_frame; - end - -`ifdef FORMAL - // {{{ - (* keep *) reg [LGFRAME:0] f_sum_xpos, f_sum_ypos; - always @(*) - begin - f_sum_xpos = { 1'b0, i_hpos } + { 1'b0, f_ovw_hpos }; - f_sum_ypos = { 1'b0, i_vpos } + { 1'b0, f_ovw_vpos }; - end - - always @(posedge ACLK) - if (ARESETN && !frame_err) - begin - if (f_pri_hpos != i_hpos && ovw_eol) - assert(!in_overlay); - - if (in_overlay && (f_pri_hpos != i_hpos || !w_frame_err)) - assert(f_pri_hpos == f_sum_xpos); - - if ((f_pri_hpos < i_hpos) - || f_pri_hpos >= { 1'b0, i_hpos } - + { 1'b0, f_ovw_width }) - begin - assert(!in_overlay); - end else if (!in_frame && f_pri_vpos > i_vpos) - begin - assert(!in_overlay); - end else if (f_pri_vpos < i_vpos) - begin - assert(!in_overlay); - end - - if (ovw_eof && (f_pri_vpos == i_vpos) - && (f_pri_hpos > { 1'b0, i_hpos })) - assert(!in_frame); - end - - always @(posedge ACLK) - if (ARESETN && !frame_err && !w_frame_err) - begin - if (f_pri_hpos != i_hpos && ovw_eol) - assert(!in_overlay); - - if ((f_pri_hpos < i_hpos) - || f_pri_hpos >= { 1'b0, i_hpos } - + { 1'b0, f_ovw_width }) - begin - // Was ... if (f_sum_xpos != { 1'b0, f_pri_hpos }) - assert(!in_overlay); - end else if (!in_frame && f_pri_vpos > i_vpos) - begin - assert(!in_overlay); - end else if (f_pri_vpos < i_vpos) - begin - assert(!in_overlay); - end else if (in_frame) - begin - assert(in_overlay); - end - end - // }}} -`endif - // }}} - - // o_err, frame_err - // {{{ - reg w_frame_err; - - always @(*) - begin - w_frame_err = 1'b0; - if (in_overlay) - w_frame_err = (!ovskd_valid || !ovskd_ready); - else begin - // if (prhpos >= i_hpos && !ovw_eol) - // w_frame_err = 1; - // if (prvpos >= i_vpos && !ovw_eof) - // w_frame_err = 1; - end - - if (prhpos == i_hpos) - begin - if (!ovw_eol) - w_frame_err = 1; - if (prvpos == i_vpos && !ovw_eof) - w_frame_err = 1; - end - end - - initial frame_err = OPT_TUSER_IS_SOF; - always @(posedge ACLK) - if (!ARESETN) - begin - frame_err <= OPT_TUSER_IS_SOF; - end else if (!frame_err && pskd_valid && pskd_ready) - begin - frame_err <= w_frame_err; - end else if ((ovw_eof || ovskd_valid && ovskd_ready && ovskd_vlast) - && ((pskd_valid && pskd_ready && pskd_vlast) - || (prvpos < i_vpos))) - begin - frame_err <= 0; - end - - assign o_err = frame_err && i_enable; -`ifdef FORMAL - reg f_ovw_recovering, - f_ovw_final_line, - f_offscreen; - (* keep *) reg [3:0] f_region; - - always @(*) - begin - f_ovw_final_line = 0; - if (((f_sum_ypos + 1 == f_vid_height) - || (f_ovw_vpos + 1 == f_ovw_height)) - && (f_sum_xpos >= f_vid_width)) - f_ovw_final_line = 1; - - f_ovw_recovering = f_ovw_final_line; - if (f_ovw_vpos + i_vpos >= f_vid_height) - f_ovw_recovering = 1; - - f_offscreen = (i_hpos >= f_vid_width); - end - - always @(posedge ACLK) - if (ARESETN && $past(ARESETN)) - begin - if (f_pri_hpos < i_hpos) - begin - // Left column - // {{{ - assert(!in_overlay); - - if (f_pri_vpos < i_vpos) - begin // #0: Top left corner - // {{{ - f_region <= 0; - assert(!in_frame); - assert(frame_err|| ovw_eof || f_ovw_recovering); - // }}} - end else if (f_pri_vpos < { 1'b0, i_vpos } + {1'b0, f_ovw_height}) - begin // #4: Left of overlay area - // {{{ - f_region <= 4; - if (f_pri_vpos == i_vpos) - assert(frame_err || in_frame); - - if (in_frame && !frame_err) - begin - if (f_pri_vpos == i_vpos) - begin - assert(ovw_eof // !!! - || f_ovw_recovering); - end else if (ovw_eol) - begin - assert(f_pri_vpos== f_sum_ypos - || f_offscreen); - end else if (ovw_eof) - begin - assert(f_pri_vpos == i_vpos); - end else if (f_pri_vpos == i_vpos) - begin - assert(f_ovw_recovering); - end else if (f_pri_vpos > i_vpos) - begin - assert(f_sum_ypos + 1 - == f_pri_vpos); - end - end - // }}} - end else begin // #8: Below the overlay area - // {{{ - f_region <= 8; - assert(frame_err || !in_frame - || i_hpos >= f_vid_width - || f_ovw_final_line); // !!! - if (!frame_err) - begin - assert(ovw_eof || f_offscreen - || (!ovw_eol && f_ovw_final_line)); - end - // }}} - end - // }}} - end else if (f_pri_hpos < { 1'b0, i_hpos }+{ 1'b0, f_ovw_width}) - begin - // Center column - // {{{ - if (f_pri_vpos < i_vpos) - begin - assert(!in_frame); - - // #1: Top middle section - f_region <= 1; - assert(frame_err|| ovw_eof || f_ovw_recovering); - end else if (f_pri_vpos < { 1'b0, i_vpos } + {1'b0, f_ovw_height}) - begin // #5: Valid middle section - // {{{ - f_region <= 5; - if (!frame_err) - begin - assert(in_frame); - assert(in_overlay); - if (ovw_eof) - begin - assert(f_pri_vpos == i_vpos - &&f_pri_hpos == i_hpos); - end - - if (ovw_eol) - begin - assert(f_pri_hpos == i_hpos); - end - - if (f_sum_xpos != f_pri_hpos) - begin - assert(w_frame_err); - assert(f_pri_hpos == i_hpos - && !ovw_eol); - end - - if (f_sum_ypos != f_pri_vpos) - begin - assert(w_frame_err); - assert(!ovw_eol - || (f_pri_vpos == i_vpos - && f_ovw_recovering)); - end - end - // }}} - end else begin - // #9: Bottom center section - f_region <= 9; - assert(frame_err || !in_frame - || (!ovw_eol && f_ovw_final_line)); - assert(frame_err || ovw_eof || f_offscreen - || (!ovw_eol && f_ovw_final_line)); - end - // }}} - end else begin - // Right column - // {{{ - assert(frame_err || !in_overlay); - - if (f_pri_vpos < i_vpos) - begin // #2: Top right corner - // {{{ - f_region <= 2; - assert(frame_err|| ovw_eof || f_ovw_recovering); - // }}} - end else if (f_pri_vpos < { 1'b0, i_vpos } + {1'b0, f_ovw_height}) - begin // #6: Right of overlay area - // {{{ - f_region <= 6; - assert(frame_err || ovw_eol); - assert(frame_err || in_frame - || (f_pri_vpos + 1 == { 1'b0, i_vpos } + { 1'b0, f_ovw_height })); - // }}} - end else begin // #10: Bottom right corner - // {{{ - f_region <= 10; - assert(frame_err || ovw_eof || f_offscreen - || (!ovw_eol && f_ovw_vpos + 1 == f_ovw_height - && f_ovw_hpos + i_hpos >= f_vid_width)); - assert(frame_err || !in_frame); - // }}} - end - // }}} - end - end else - f_region <= 12; - - always @(posedge ACLK) - if (ARESETN && $past(ARESETN) && !ovw_eof) - begin - if (f_pri_vpos >= i_vpos - && f_pri_vpos != f_sum_ypos) - begin - if (f_pri_hpos >= i_hpos - && f_pri_hpos != f_sum_xpos) - begin - assert(ovw_eol || frame_err || w_frame_err); - end - end - - /* - if (f_pri_vpos > i_vpos // && !ovw_eof - && ((ovw_eol && f_pri_hpos <= i_hpos - && f_pri_vpos != f_sum_ypos) - || (!ovw_eol && f_pri_hpos <= i_hpos - && f_pri_vpos != f_sum_ypos + 1) - || (!ovw_eol && f_pri_hpos > i_hpos - && f_pri_vpos != f_sum_ypos) - )) - assert(frame_err || w_frame_err); - */ - end - - always @(posedge ACLK) - if (ARESETN && OPT_TUSER_IS_SOF) - begin - if (!f_pri_known || lines_per_frame == 0) - assert(frame_err); - if (!f_ovw_known || f_ovw_lines_per_frame == 0) - assert(frame_err); - if (ovw_eof) - assert(f_ovw_lines_per_frame != 0); - end -`endif - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Mix the two channels together - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // mix_pixel - // {{{ - generate if (ALPHA_BITS == 0) - begin : NO_ALPHA - // {{{ - reg [DW-1:0] r_mix_pixel; - - always @(posedge ACLK) - if (pskd_valid && pskd_ready) - begin - r_mix_pixel <= pskd_data; - if (in_overlay && ovskd_valid && !frame_err - && i_enable) - r_mix_pixel <= ovskd_data; - end - - assign mix_pixel = r_mix_pixel; - // }}} - end else if (ALPHA_BITS == 1) - begin: ALPHA_MASK - // {{{ - reg [DW-1:0] r_mix_pixel; - - always @(posedge ACLK) - if (pskd_valid && pskd_ready) - begin - r_mix_pixel <= pskd_data; - if (in_overlay && ovskd_valid && i_enable - && !frame_err && ovskd_data[DW]) - r_mix_pixel <= ovskd_data[DW-1:0]; - end - - assign mix_pixel = r_mix_pixel; - // }}} - end else begin : ALPHA_MIXING - // {{{ - genvar clr; - reg [ALPHA_BITS:0] alpha, negalpha; - reg [DW-1:0] pri_pixel, ovw_pixel; - - // pri_pixel, ovw_pixel - // {{{ - always @(posedge ACLK) - if (!ARESETN) - begin - pri_pixel <= 0; - ovw_pixel <= 0; - alpha <= TRANSPARENT; - end else if (pskd_valid && pskd_ready) - begin - pri_pixel <= pskd_data; - ovw_pixel <= ovskd_data[DW-1:0]; - // Verilator lint_off WIDTH - alpha <= ovskd_data[ALPHA_BITS + DW-1 : DW] - + ovskd_data[ALPHA_BITS + DW-1]; - negalpha <= (1<= 4); - assume(f_vid_height>= 4); - - assume(f_ovw_width >= 2); - assume(f_ovw_height>= 2); - end - - // f_pri_?pos - // {{{ - faxivideo #( - // {{{ - .PW(DW), .LGDIM(LGFRAME), - .OPT_TUSER_IS_SOF(OPT_TUSER_IS_SOF) - // }}} - ) fpri ( - // {{{ - .i_clk(ACLK), .i_reset_n(ARESETN), - .S_VID_TVALID(S_PRI_TVALID), - .S_VID_TREADY(S_PRI_TREADY), - .S_VID_TDATA( S_PRI_TDATA), - .S_VID_TLAST( S_PRI_TLAST), - .S_VID_TUSER( S_PRI_TUSER), - // - .i_width(f_vid_width), .i_height(f_vid_height), - .o_xpos(f_pri_hpos), .o_ypos(f_pri_vpos), - .f_known_height(f_pri_known), - .o_hlast(f_pri_hlast), .o_vlast(f_pri_vlast), - .o_sof(f_pri_sof), - // }}} - ); - - always @(*) - if (ARESETN && S_PRI_TVALID) - begin - if (OPT_TUSER_IS_SOF) - begin - assume(S_PRI_TLAST == f_pri_hlast); - assume(S_PRI_TUSER == f_pri_sof); - end else begin - assume(S_PRI_TLAST == (f_pri_vlast && f_pri_hlast)); - assume(S_PRI_TUSER == f_pri_hlast); - end - end - // }}} - - // f_ovw_?pos - // {{{ - faxivideo #( - // {{{ - .PW(DW), .LGDIM(LGFRAME), - .OPT_TUSER_IS_SOF(OPT_TUSER_IS_SOF) - // }}} - ) fovw ( - // {{{ - .i_clk(ACLK), .i_reset_n(ARESETN), - .S_VID_TVALID(S_OVW_TVALID), - .S_VID_TREADY(S_OVW_TREADY), - .S_VID_TDATA( S_OVW_TDATA), - .S_VID_TLAST( S_OVW_TLAST), - .S_VID_TUSER( S_OVW_TUSER), - // - .i_width(f_ovw_width), .i_height(f_ovw_height), - .o_xpos(f_ovw_hpos), .o_ypos(f_ovw_vpos), - .f_known_height(f_ovw_known), - .o_hlast(f_ovw_hlast), .o_vlast(f_ovw_vlast), - .o_sof(f_ovw_sof), - // }}} - ); - - always @(*) - if (ARESETN && S_OVW_TVALID) - begin - if (OPT_TUSER_IS_SOF) - begin - assume(S_OVW_TLAST == f_ovw_hlast); - assume(S_OVW_TUSER == f_ovw_sof); - end else begin - assume(S_OVW_TLAST == (f_ovw_vlast && f_ovw_hlast)); - assume(S_OVW_TUSER == f_ovw_hlast); - end - end - // }}} - - // S_PRI_TLAST, S_PRI_TUSER - // {{{ - generate if (OPT_TUSER_IS_SOF) - begin : ASSUME_SOF - always @(*) - if (S_PRI_TVALID) - begin - assume(S_PRI_TLAST == (f_pri_hpos == f_vid_width-1)); - assume(S_PRI_TUSER == (f_pri_hpos == 0 && f_pri_vpos == 0)); - end - end else begin : ASSUME_VLAST - always @(*) - if (S_PRI_TVALID) - begin - assume(S_PRI_TUSER == (f_pri_hpos == f_vid_width-1)); - if (f_pri_vpos < f_vid_height-1) - assume(!S_PRI_TLAST); - else if (S_PRI_TUSER) - assume(S_PRI_TLAST == (f_pri_vpos == f_vid_height-1)); - end - end endgenerate - // }}} - - // S_OVW_TLAST, S_OVW_TUSER - // {{{ - generate if (OPT_TUSER_IS_SOF) - begin - always @(*) - if (S_OVW_TVALID) - begin - assume(S_OVW_TLAST == (f_ovw_hpos == f_ovw_width-1)); - assume(S_OVW_TUSER == (f_ovw_hpos == 0 && f_ovw_vpos == 0)); - end - end else begin - always @(*) - if (S_OVW_TVALID) - begin - assume(S_OVW_TUSER == (f_ovw_hpos == f_ovw_width-1)); - if (f_ovw_vpos < f_ovw_height-1) - assume(!S_OVW_TLAST); - else if (S_OVW_TUSER) - assume(S_OVW_TLAST == (f_ovw_vpos == f_ovw_height-1)); - end - end endgenerate - // }}} - - // f_vid_?pos - // {{{ - faxivideo #( - // {{{ - .PW(DW), .LGDIM(LGFRAME), - .OPT_TUSER_IS_SOF(OPT_TUSER_IS_SOF) - // }}} - ) fvid ( - // {{{ - .i_clk(ACLK), .i_reset_n(ARESETN), - .S_VID_TVALID(M_VID_TVALID), - .S_VID_TREADY(M_VID_TREADY), - .S_VID_TDATA( M_VID_TDATA), - .S_VID_TLAST( M_VID_TLAST), - .S_VID_TUSER( M_VID_TUSER), - // - .i_width(f_vid_width), .i_height(f_vid_height), - .o_xpos(f_vid_hpos), .o_ypos(f_vid_vpos), - .f_known_height(f_vid_known), - .o_hlast(f_vid_hlast), .o_vlast(f_vid_vlast), - .o_sof(f_vid_sof), - // }}} - ); - // }}} - - // f_mix_?pos - // {{{ - faxivideo #( - // {{{ - .PW(DW), .LGDIM(LGFRAME), - .OPT_TUSER_IS_SOF(OPT_TUSER_IS_SOF) - // }}} - ) fmix ( - // {{{ - .i_clk(ACLK), .i_reset_n(ARESETN), - .S_VID_TVALID(mix_valid), - .S_VID_TREADY(mix_ready), - .S_VID_TDATA( mix_pixel), - .S_VID_TLAST( (OPT_TUSER_IS_SOF) ? mix_hlast : mix_vlast), - .S_VID_TUSER( (OPT_TUSER_IS_SOF) ? mix_sof : mix_hlast), - // - .i_width(f_vid_width), .i_height(f_vid_height), - .o_xpos(f_mix_hpos), .o_ypos(f_mix_vpos), - .f_known_height(f_mix_known), - .o_hlast(f_mix_hlast), .o_vlast(f_mix_vlast), - .o_sof(f_mix_sof), - // }}} - ); - // }}} - - // f_mix_hlast, f_mix_sof, f_mix_vlast - // {{{ - always @(*) - if (ARESETN && mix_valid) - begin - assert(mix_hlast == (f_mix_hpos == f_vid_width-1)); - assert(mix_sof == (f_mix_vpos == 0 && f_mix_hpos == 0)); - if (mix_vlast || f_mix_known || f_pri_known) - assert(f_pri_sof || (mix_vlast == (mix_hlast && f_mix_vpos == f_vid_height-1))); - end - // }}} - - always @(*) - if (ARESETN) - begin - if (!M_VID_TVALID) - begin - assert(f_mix_hpos == f_vid_hpos); - assert(f_mix_vpos == f_vid_vpos); - end else if (f_vid_hpos < f_vid_width-1) - begin - assert(f_mix_hpos == f_vid_hpos + 1); - assert(f_mix_vpos == f_vid_vpos); - end else // if (f_vid_hpos == f_vid_width-1) - begin - assert(f_mix_hpos == 0); - if (f_vid_vpos == f_vid_height-1) - assert(f_mix_vpos == 0); - else - assert(f_mix_vpos == f_vid_vpos + 1); - end - end - - generate if (OPT_TUSER_IS_SOF) - begin : CHECK_VLAST - - always @(*) - if (ARESETN && lines_per_frame > 0) - begin - assert(lines_per_frame == f_vid_height); - if (pskd_valid) - assert(pskd_vlast == (pskd_hlast && f_pskd_vpos == f_vid_height-1)); - end else if (ARESETN) - begin - if (pskd_valid) - assert(!pskd_vlast); - if (mix_valid) - assert(!mix_vlast); - end - - end endgenerate - - // f_pskd_?pos - // {{{ - faxivideo #( - // {{{ - .PW(DW), .LGDIM(LGFRAME), - .OPT_TUSER_IS_SOF(OPT_TUSER_IS_SOF) - // }}} - ) fpskd ( - // {{{ - .i_clk(ACLK), .i_reset_n(ARESETN), - .S_VID_TVALID(pskd_valid), - .S_VID_TREADY(pskd_ready), - .S_VID_TDATA( pskd_data), - .S_VID_TLAST( (OPT_TUSER_IS_SOF) ? pskd_hlast : pskd_vlast), - .S_VID_TUSER( (OPT_TUSER_IS_SOF) ? pskd_sof : pskd_hlast), - // - .i_width(f_vid_width), .i_height(f_vid_height), - .o_xpos(f_pskd_hpos), .o_ypos(f_pskd_vpos), - .f_known_height(f_pskd_known), - .o_hlast(f_pskd_hlast), .o_vlast(f_pskd_vlast), - .o_sof(f_pskd_sof), - // }}} - ); - - always @(*) - begin - assert(f_pskd_sof == f_pri_sof); - assert(f_pskd_hpos == f_pri_hpos); - assert(f_pskd_vpos == f_pri_vpos); - assert(f_pskd_known == f_pri_known); - end - // }}} - - // Relate f_pskd to f_pri (they are the same) - // {{{ - always @(*) - if (ARESETN) - begin - if (1 || S_PRI_TREADY) - begin - assert(f_pskd_hpos == f_pri_hpos); - assert(f_pskd_vpos == f_pri_vpos); - end else if (f_vid_hpos > 0) - begin - assert(f_pskd_hpos + 1 == f_pri_hpos); - assert(f_pskd_vpos <= f_pri_vpos); - end else if (f_vid_vpos > 0) - begin - assert(f_pskd_hpos == f_vid_width -1); - assert(f_pskd_vpos + 1 == f_pri_vpos); - end else begin - assert(f_pskd_hpos == f_vid_width -1); - assert(f_pskd_vpos == f_vid_height - 1); - end - end - // }}} - - // pskd_hlast, pskd_sof - // {{{ - generate if (OPT_TUSER_IS_SOF) - begin : CHECK_LINES_PER_FRAME - always @(posedge ACLK) - if (f_past_valid && $past(ARESETN)) - begin - if ($past(lines_per_frame == f_vid_height)) - assert(lines_per_frame == f_vid_height); - if (lines_per_frame != 0) - assert(f_pri_known); - end - end endgenerate - - always @(*) - if (ARESETN) - begin - if (!f_pri_known) - begin - assert(lines_per_frame == 0); - end else begin - assert(lines_per_frame == f_vid_height - || lines_per_frame == 0); - end - end - - always @(*) - if (pskd_valid) - begin - assert(pskd_hlast == f_pskd_hlast); - assert(pskd_sof == f_pskd_sof); - if (lines_per_frame == f_vid_height) - begin - assert(f_pskd_known); - assert(pskd_vlast == (pskd_hlast && f_pskd_vlast)); - end - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - (* anyconst *) reg fc_check; - (* anyconst *) reg [LGFRAME-1:0] fc_pri_hpos, fc_pri_vpos; - (* anyconst *) reg [LGFRAME-1:0] fc_ovw_hpos, fc_ovw_vpos; - (* anyconst *) reg [LGFRAME-1:0] fc_off_hpos, fc_off_vpos; - (* anyconst *) reg [DW-1:0] fc_pri_pixel; - (* anyconst *) reg [DW+ALPHA_BITS-1:0] fc_ovw_pixel; - reg f_vid_err; - - always @(*) - begin - assume(fc_pri_hpos < f_vid_width); - assume(fc_pri_vpos < f_vid_height); - - assume(fc_off_hpos < f_vid_width); - assume(fc_off_vpos < f_vid_height); - - assume(fc_ovw_hpos < f_ovw_width); - assume(fc_ovw_vpos < f_ovw_height); - - end - - always @(posedge ACLK) - if (!ARESETN) - f_vid_err <= 0; - else if (!M_VID_TVALID || M_VID_TREADY) - f_vid_err <= f_mix_err; - - always @(*) - if (fc_check && ARESETN) - begin - if (S_PRI_TVALID && f_pri_hpos == fc_pri_hpos - && f_pri_vpos == fc_pri_vpos) - assume(S_PRI_TDATA == fc_pri_pixel); - if (S_OVW_TVALID && f_ovw_hpos == fc_ovw_hpos - && f_ovw_vpos == fc_ovw_vpos) - assume(S_OVW_TDATA == fc_ovw_pixel); - - assume(fc_off_hpos == i_hpos); - assume(fc_off_vpos == i_vpos); - - assume({ 1'b0, fc_pri_hpos } == { 1'b0, i_hpos } + { 1'b0, fc_ovw_hpos }); - assume({ 1'b0, fc_pri_vpos } == { 1'b0, i_vpos } + { 1'b0, fc_ovw_vpos }); - end - - always @(posedge ACLK) - if (ARESETN && fc_check) - assume(!$rose(frame_err)); - - always @(posedge ACLK) - if (ARESETN && fc_check && !frame_err) - begin - if (f_pri_known && $stable(f_pri_known) - && f_ovw_known && $stable(f_ovw_known) - && f_ovw_lines_per_frame == f_ovw_height - && (lines_per_frame > 0) - && $stable(lines_per_frame)) - begin - if (f_pri_hpos >= i_hpos && f_pri_vpos >= i_vpos - && f_pri_hpos < { 1'b0, i_hpos } + { 1'b0, f_ovw_width } - && f_pri_vpos < { 1'b0, i_vpos } + { 1'b0, f_ovw_height }) - begin - assert(in_overlay); - // {{{ - // assert({ 1'b0, f_pri_hpos } == { 1'b0, f_ovw_hpos } + { 1'b0, i_hpos }); - // assert({ 1'b0, f_pri_vpos } == { 1'b0, f_ovw_vpos } + { 1'b0, i_vpos }); - // }}} - end else begin - assert(!in_overlay); - // {{{ - if (ovw_eof) - begin - // {{{ - assert( - // Before/waiting 4 the frame - (f_pri_vpos < i_vpos - || (f_pri_vpos == i_vpos && f_pri_hpos < i_hpos)) - // or afterwards on the same line - ||(f_pri_hpos >= { 1'b0, i_hpos } + { 1'b0, f_ovw_width } - && { 1'b0, f_pri_vpos } == { 1'b0, i_vpos } + { 1'b0, f_ovw_height } - 1) - // or on following lines - ||({ 1'b0, f_pri_vpos } >= { 1'b0, i_vpos } + { 1'b0, f_ovw_height })); - // }}} - end else if (ovw_eol - && f_pri_vpos >= i_vpos - && f_pri_vpos < { 1'b0, i_vpos } + { 1'b0, f_ovw_height }) - begin - if (f_pri_hpos < i_hpos) - begin - assert({ 1'b0, f_pri_vpos } == { 1'b0, f_ovw_vpos } + { 1'b0, i_vpos }); - end else - assert({ 1'b0, f_pri_vpos } == { 1'b0, f_ovw_vpos } + { 1'b0, i_vpos } - 1); - end else if (f_pri_vpos >= i_vpos - && f_pri_vpos < { 1'b0, i_vpos } + { 1'b0, f_ovw_height }) - begin - if (f_pri_hpos <= i_hpos) - begin - assert({ 1'b0, f_pri_vpos } - == { 1'b0, f_ovw_vpos } - + { 1'b0, i_vpos } + 1); - end else - assert({ 1'b0, f_pri_vpos } - == { 1'b0, f_ovw_vpos } - + { 1'b0, i_vpos }); - end // else assert(ovw_eof); - // }}} - end - end - end - - generate if (ALPHA_BITS == 0) - begin : GEN_CONTRACT_A0 - // {{{ - always @(posedge ACLK) - if (ARESETN && fc_check && mix_valid - && (f_mix_hpos == fc_pri_hpos - && f_mix_vpos == fc_pri_vpos)) - begin - if (i_enable && !f_mix_err) - begin - assert(mix_pixel == fc_ovw_pixel); - end else begin - assert(mix_pixel == fc_pri_pixel); - end - end - - always @(posedge ACLK) - if (ARESETN && fc_check && M_VID_TVALID) - begin - if (f_vid_hpos == fc_pri_hpos - && f_vid_vpos == fc_pri_vpos) - begin - if (i_enable && !f_vid_err) - begin - assert(M_VID_TDATA == fc_ovw_pixel); - end else begin - assert(M_VID_TDATA == fc_pri_pixel); - end - end - end - // }}} - end else if (ALPHA_BITS == 1) - begin : GEN_CONTRACT_A1 - // {{{ - always @(posedge ACLK) - if (ARESETN && fc_check && mix_valid - && (f_mix_hpos == fc_pri_hpos - && f_mix_vpos == fc_pri_vpos)) - begin - if (fc_ovw_pixel[DW] && i_enable && !f_mix_err) - begin - assert(mix_pixel == fc_ovw_pixel[DW-1:0]); - end else begin - assert(mix_pixel == fc_pri_pixel[DW-1:0]); - end - end - - always @(posedge ACLK) - if (ARESETN && fc_check && M_VID_TVALID) - begin - if (f_vid_hpos == fc_pri_hpos - && f_vid_vpos == fc_pri_vpos) - begin - if (fc_ovw_pixel[DW] && i_enable && !f_vid_err) - begin - assert(M_VID_TDATA == fc_ovw_pixel[DW-1:0]); - end else begin - assert(M_VID_TDATA == fc_pri_pixel[DW-1:0]); - end - end - end - // }}} - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Overlay tracking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge ACLK) - if (ARESETN && (!OPT_LINE_BREAK || !pix_line_pause)) - begin - if (f_pskd_hpos < i_hpos) - begin - assert(!in_overlay); - end else if (f_pskd_vpos < i_vpos - && f_pskd_vpos == prvpos - && f_ovw_vpos == ovvpos - && f_pskd_hpos != 1) - assert(!in_overlay); - - if (!frame_err && !ovw_eof && in_frame && lines_per_frame > 0) - begin - if (ovw_eol && f_pri_hpos > i_hpos) - begin - assert(f_sum_ypos == f_pskd_vpos + 1); - /* - end else if (ovw_eol && f_pri_hpos <= i_hpos) - begin - assert(f_sum_ypos == f_pskd_vpos - || (f_ovw_vpos == 0 - && f_ovw_hpos == 0 - && f_ovw_lines_per_frame == 0 - && (f_sum_ypos == { 1'b0, i_vpos } + { 1'b0, f_ovw_height }) - && OPT_TUSER_IS_SOF)); - end - else if (f_pri_hpos <= i_hpos) - begin - assert(f_sum_ypos + 1 == f_pskd_vpos); - end else begin // if (!ovw_eol && f_pri_hpos > i_hpos) - assert(f_sum_ypos == f_pskd_vpos - || f_sum_ypos >= f_vid_height); - */ - end - end - - if (!frame_err && !ovw_eof && in_overlay - && lines_per_frame > 0) - begin - assert(w_frame_err || (i_hpos + f_ovw_hpos == f_pskd_hpos)); - end - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - reg [2:0] cvr_pframes, cvr_oframes; - - initial cvr_pframes = 0; - always @(posedge ACLK) - if (!ARESETN) - cvr_pframes <= 0; - else if (pskd_valid && pskd_ready && pskd_vlast && !cvr_pframes[2]) - cvr_pframes <= cvr_pframes + 1; - - initial cvr_oframes = 0; - always @(posedge ACLK) - if (!ARESETN) - cvr_oframes <= 0; - else if (ovskd_valid && ovskd_ready && ovskd_vlast && !cvr_oframes[2]) - cvr_oframes <= cvr_oframes + 1; - - always @(posedge ACLK) - if (ARESETN) - begin - cover(cvr_pframes == 1); - cover(cvr_oframes == 1); - - cover(cvr_pframes == 2); - cover(cvr_oframes == 2); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge ACLK) - if ((1||fc_check) && ARESETN && $past(ARESETN && !S_PRI_TVALID) - && $past(ARESETN && !S_PRI_TVALID, 2) - && $past(ARESETN && !S_PRI_TVALID, 3)) - begin - assume(S_PRI_TVALID); - end - - always @(*) - if (fc_check) - assume(M_VID_TREADY); - - always @(posedge ACLK) - if ((1||fc_check) && ARESETN && $past(ARESETN && !M_VID_TREADY) - && $past(ARESETN && !M_VID_TREADY, 2) - && $past(ARESETN && !M_VID_TREADY, 3)) - begin - assume(M_VID_TREADY); - end - - - always @(*) - assume(i_vpos == 0); - - always @(*) - if (!S_PRI_TVALID) - begin - assume(!S_PRI_TUSER); - assume(!S_PRI_TLAST); - end - - always @(*) - if (!S_OVW_TVALID) - begin - assume(!S_OVW_TUSER); - assume(!S_OVW_TLAST); - end - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/cecbridge.v b/delete_later/rtl/hdmi/cecbridge.v deleted file mode 100644 index e2427e0..0000000 --- a/delete_later/rtl/hdmi/cecbridge.v +++ /dev/null @@ -1,165 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: rtl/hdmi/crcbridge.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Connect the CEC lines together between master(driver) and slave. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module cecbridge( - // {{{ - input wire i_clk, - input wire i_txcec, - output reg o_txcec, - input wire i_rxcec, - output reg o_rxcec - // }}} - ); - - // Local declarations - // {{{ - reg owned; - reg [1:0] pipe_txcec, pipe_rxcec; - reg ck_txcec, ck_rxcec; - reg [12:0] timer; // Should be about 0.2ms/10 - reg timeout; - reg watchdog_err; - reg [19:0] watchdog_timer; // Should be about 5ms or more - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Synchronize inputs - // {{{ - always @(posedge i_clk) - { ck_txcec, pipe_txcec } <= { pipe_txcec, i_txcec }; - - always @(posedge i_clk) - { ck_rxcec, pipe_rxcec } <= { pipe_rxcec, i_rxcec }; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // State machine: the dev that pulls the CEC line low, owns the bus - // {{{ - - initial { owned, o_txcec, o_rxcec } = 3'h3; - always @(posedge i_clk) - if (watchdog_err) - { owned, o_txcec, o_rxcec } <= 3'h3; - else case({ ck_txcec, ck_rxcec }) - 2'b11:begin owned <= 1'b0; o_txcec <= 1; o_rxcec <= 1; end - 2'b10: if (timeout) - // {{{ - begin - if (!owned) - begin - owned <= 1'b1; - o_txcec <= 0; o_rxcec <= 1; - end else if (o_rxcec) - begin // RX OWNS, TX is Z - end else begin // TX OWNS, RX is Z -- do nothing - owned <= 0; - o_txcec <= 1; - o_rxcec <= 1; - end - end - // }}} - 2'b01: if (timeout) - // {{{ - begin - if (!owned) - begin - owned <= 1'b1; - o_txcec <= 1; - o_rxcec <= 0; - end else if (o_rxcec) - begin // RX OWNS, RX is Z - owned <= 0; - o_txcec <= 1; - o_rxcec <= 1; - end else begin // TX OWNS, RX is Z -- do nothing - end - end - // }}} - 2'b00: begin end - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Timeout, to prevent pulling low already pulled data - // {{{ - - // After we stop pulling something low, we need to allow time for it - // to rise, before we decide that the value we just pulled low is - // now pulling us low, instead of rising and not-yet risen - - initial { timeout, timer } = 1; - always @(posedge i_clk) - if (!timeout) - begin - { timeout, timer } <= timer + 1; - end else case({ ck_txcec, ck_rxcec }) - 2'b11: begin end - 2'b10: { timeout, timer } <= 1; - 2'b01: { timeout, timer } <= 1; - 2'b00: { timeout, timer } <= 1; - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Watchdog timeout -- in case something goes wrong, let the bus clear - // {{{ - - initial { watchdog_err, watchdog_timer } = 1; - always @(posedge i_clk) - if (ck_txcec && ck_rxcec) - // If both CECs are set, the bus is clear, and we can restart - // the watchdog. - { watchdog_err, watchdog_timer } <= 1; - else if (!watchdog_err) - { watchdog_err, watchdog_timer } <= watchdog_timer + 1; - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - always @(*) - assert(o_rxcec || o_txcec); - always @(*) - assert(owned == (o_rxcec != o_txcec)); - always @(*) - assert(timeout == (timer == 0)); -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/hdmi2vga.v b/delete_later/rtl/hdmi/hdmi2vga.v deleted file mode 100644 index 936dedd..0000000 --- a/delete_later/rtl/hdmi/hdmi2vga.v +++ /dev/null @@ -1,386 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: hdmi2vga.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Convert an HDMI input stream into an outgoing VGA stream, -// for further processing as a (nearly video format independent) -// stream. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// }}} -module hdmi2vga // #() // No parameters (yet) - ( - // {{{ - input wire i_clk, i_reset, - input wire [9:0] i_hdmi_blu, - input wire [9:0] i_hdmi_grn, - input wire [9:0] i_hdmi_red, - // - output reg o_pix_valid, - output reg o_vsync, - output reg o_hsync, - output reg [7:0] o_vga_red, o_vga_green, o_vga_blue - // }}} - ); - - // Register/wire definitions - // {{{ - wire [9:0] blu_word, grn_word, red_word; - // Decoded data, not yet word synchronized - wire [1:0] ublu_ctl, ugrn_ctl, ured_ctl; - wire [6:0] ublu_aux, ugrn_aux, ured_aux; - wire [7:0] ublu_pix, ugrn_pix, ured_pix; - // now synchronized word dsata - reg [1:0] sblu_ctl, sgrn_ctl, sred_ctl; - reg [6:0] sblu_aux, sgrn_aux, sred_aux; - reg [7:0] sblu_pix, sgrn_pix, sred_pix; - - reg [9:0] video_control_blu, video_control_grn, video_control_red; - reg [1:0] video_guard_blu, video_guard_grn, video_guard_red; - reg [2:0] video_start_blu, video_start_grn, video_start_red; - reg video_start, video_period; - - reg [9:0] data_control_blu, data_control_grn, data_control_red; - reg [1:0] data_guard_blu, data_guard_grn, data_guard_red; - reg [2:0] data_start_blu, data_start_grn, data_start_red; - reg data_start, data_guard; // data_period; - - reg lag_blu, lag_red, lag_grn; - reg [16:0] lag_data_blu, lag_data_red, lag_data_grn; - - reg non_video_data, control_sync; - reg [11:0] control_sync_sreg; - - wire [31:0] sync_word; - - reg [7:0] blu_pixel, grn_pixel, red_pixel; - - reg r_pix_valid; - reg [7:0] r_vga_red, r_vga_green, r_vga_blue; - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // Bit synchronization: [clr]_word and sync_word generation - // {{{ - hdmibitsync - bitsync(i_clk, i_reset, i_hdmi_blu, i_hdmi_grn, i_hdmi_red, - blu_word, grn_word, red_word, sync_word); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // TMDS decoding - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - tmdsdecode - decblu(i_clk, blu_word, ublu_ctl, ublu_aux, ublu_pix); - - tmdsdecode - decgrn(i_clk, grn_word, ugrn_ctl, ugrn_aux, ugrn_pix); - - tmdsdecode - decred(i_clk, red_word, ured_ctl, ured_aux, ured_pix); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Video data start detection, and channel sync - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // video_control_blu, video_guard_blu => video_start_blu - // {{{ - initial video_control_blu = 0; - always @(posedge i_clk) - video_control_blu <= {video_control_blu[8:0], ublu_aux[4] }; - - initial video_guard_blu = 0; - always @(posedge i_clk) - video_guard_blu <= {video_guard_blu[0], - ublu_aux[6] && !ublu_aux[0] }; - - initial video_start_blu = 0; - always @(posedge i_clk) - video_start_blu <= { video_start_blu[1:0], - (&video_control_blu[9:2])&&(&video_guard_blu) }; - // }}} - - // video_control_grn, video_guard_grn => video_start_grn - // {{{ - initial video_control_grn = 0; - always @(posedge i_clk) - video_control_grn <= {video_control_grn[8:0], - ugrn_aux[4] && ugrn_ctl == 2'b10 }; - - initial video_guard_grn = 0; - always @(posedge i_clk) - video_guard_grn <= {video_guard_grn[0], - ugrn_aux[6] && ugrn_aux[0] }; - - initial video_start_grn = 0; - always @(posedge i_clk) - video_start_grn <= { video_start_grn[1:0], - (&video_control_grn[9:2])&&(&video_guard_grn) }; - // }}} - - // video_control_red, video_guard_red => video_start_red - // {{{ - initial video_control_red = 0; - always @(posedge i_clk) - video_control_red <= {video_control_red[8:0], - ured_aux[4] && ured_ctl == 2'b00 }; - - initial video_guard_red = 0; - always @(posedge i_clk) - video_guard_red <= {video_guard_red[0], - ured_aux[6] && !ured_aux[0] }; - - initial video_start_red = 0; - always @(posedge i_clk) - video_start_red <= { video_start_red[1:0], - (&video_control_red[9:2])&&(&video_guard_red) }; - // }}} - - // video_start, lag_[clr] - // {{{ - initial video_start = 1'b0; - always @(posedge i_clk) - video_start <= (|video_start_red) && (|video_start_grn) - &&(|video_start_blu) - &&(|{ video_start_red[0], video_start_grn[0], - video_start_blu[0] }); - - always @(posedge i_clk) - if (video_start) - begin - lag_blu <= video_start_blu[1]; - lag_grn <= video_start_grn[1]; - lag_red <= video_start_red[1]; - end - // }}} - - // lag_data_[clr], s[clr]_[ctl,aux,pix]: Frame sync - // {{{ - // bit sync achieved above, now we align our various color channels - always @(posedge i_clk) - begin - lag_data_blu <= { ublu_ctl, ublu_aux, ublu_pix }; - lag_data_grn <= { ugrn_ctl, ugrn_aux, ugrn_pix }; - lag_data_red <= { ured_ctl, ured_aux, ured_pix }; - - if (lag_blu) - { sblu_ctl, sblu_aux, sblu_pix } - <= { ublu_ctl, ublu_aux, ublu_pix }; - else - { sblu_ctl, sblu_aux, sblu_pix } <= lag_data_blu; - - if (lag_grn) - { sgrn_ctl, sgrn_aux, sgrn_pix } - <= { ugrn_ctl, ugrn_aux, ugrn_pix }; - else - { sgrn_ctl, sgrn_aux, sgrn_pix } <= lag_data_grn; - - if (lag_red) - { sred_ctl, sred_aux, sred_pix } - <= { ured_ctl, ured_aux, ured_pix }; - else - { sred_ctl, sred_aux, sred_pix } <= lag_data_red; - end - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Data island start detection, post channel sync - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // data_control_blu, data_guard_blu => data_start_blu - // {{{ - always @(*) - data_control_blu = video_control_blu; - - // The blue (channel 0) data island guard bands is just a control - // word (not guard, not video, not data, etc) - initial data_guard_blu = 0; - always @(*) - data_guard_blu = data_control_blu[1:0]; - - initial data_start_blu = 0; - always @(posedge i_clk) - data_start_blu <= { data_start_blu[1:0], - (&data_control_blu[9:2])&&(&data_guard_blu) }; - // }}} - - // data_control_grn, data_guard_grn => data_start_grn - // {{{ - always @(*) - data_control_grn = video_control_grn; - - initial data_guard_grn = 0; - always @(posedge i_clk) - data_guard_grn <= {data_guard_grn[0], - ugrn_aux[6] && ugrn_aux[0] }; - - initial data_start_grn = 0; - always @(posedge i_clk) - data_start_grn <= { data_start_grn[1:0], - (&data_control_grn[9:2])&&(&data_guard_grn) }; - // }}} - - // data_control_red, data_guard_red => data_start_red - // {{{ - initial data_control_red = 0; - always @(posedge i_clk) - data_control_red <= {data_control_red[8:0], - ured_aux[4] && ured_ctl == 2'b10 }; - - initial data_guard_red = 0; - always @(posedge i_clk) - data_guard_red <= {data_guard_red[0], - ured_aux[6] && !ured_aux[0] }; - - initial data_start_red = 0; - always @(posedge i_clk) - data_start_red <= { data_start_red[1:0], - (&data_control_red[9:2])&&(&data_guard_red) }; - // }}} - - // data_start, data_guard, lag_[clr] - // {{{ - initial data_start = 1'b0; - always @(posedge i_clk) - data_start <= - ((lag_blu) ? data_guard_blu[1] : data_guard_blu[0]) && - ((lag_grn) ? data_guard_grn[1] : data_guard_grn[0]) && - ((lag_red) ? data_guard_red[1] : data_guard_red[0]); - - always @(*) - data_guard = data_start; - // }}} - - // }}} - - // non_video_data - // {{{ - always @(posedge i_clk) - non_video_data <= (sblu_aux[4])&&(sgrn_aux[4]) &&(sred_aux[4]); - // }}} - // control_sync_sreg - // {{{ - always @(posedge i_clk) - begin - control_sync_sreg[10:1] <= control_sync_sreg[ 9:0]; - control_sync_sreg[11] <= (&control_sync_sreg[10:0]); - control_sync_sreg[0] <= sblu_aux[4] && sgrn_aux[4] - && sred_aux[4]; - end - // }}} - // control_sync - // {{{ - always @(*) - control_sync = control_sync_sreg[11] && control_sync_sreg[0]; - // }}} - - always @(posedge i_clk) - begin - blu_pixel <= sblu_pix; - grn_pixel <= sgrn_pix; - red_pixel <= sred_pix; - end - - always @(posedge i_clk) - begin - // data_end <= data_period && data_guard; - if (control_sync) - begin - // data_period <= 0; - video_period <= 0; - end else begin - if (video_start) - video_period <= 1; - else if (non_video_data) - video_period <= 0; - /* - if (data_start) - data_period <= 1; - else if (data_end) - data_period <= 0; - */ - end - - // Outgoing pixels - // {{{ - r_pix_valid <= (video_start)||(video_period && !non_video_data); - - r_vga_red <= red_pixel; - r_vga_green <= grn_pixel; - r_vga_blue <= blu_pixel; - // }}} - - // Outgoing sync - // {{{ - if (sblu_aux[5:4] == 2'b01) - begin - o_vsync <= sblu_ctl[1]; - o_hsync <= sblu_ctl[0]; - end - // }}} - end - - always @(*) - begin - o_pix_valid = r_pix_valid; - - o_vga_red = r_vga_red; - o_vga_green = r_vga_green; - o_vga_blue = r_vga_blue; - end - - // Make verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, sblu_aux[3:0], sgrn_aux[3:0], sred_aux[3:0], - sgrn_ctl, sred_ctl, sync_word, control_sync, - non_video_data, - data_start_red[2], data_start_grn[2], data_start_blu[2], - data_control_red[1:0], data_control_grn[1:0], data_control_blu[1:0], - sred_aux[6:5], sgrn_aux[6:5], sblu_aux[6:5], - data_guard - }; - // Verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/hdmibitsync.v b/delete_later/rtl/hdmi/hdmibitsync.v deleted file mode 100644 index f1bf668..0000000 --- a/delete_later/rtl/hdmi/hdmibitsync.v +++ /dev/null @@ -1,98 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: hdmibitsync.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module hdmibitsync ( - // {{{ - input wire i_pix_clk, i_reset, - // - input wire [9:0] i_r, i_g, i_b, - output reg [9:0] o_r, o_g, o_b, - // - output wire [31:0] o_sync_word - // }}} - ); - - // Register/net declarations - // {{{ - wire [9:0] auto_r, auto_g, auto_b; - wire [4:0] auto_bitslip_r, auto_bitslip_g, auto_bitslip_b; - reg all_locked; - // }}} - - // Automatically synchronize to each color stream. - // {{{ - // It is possible that we'll lock up to one color on one word and - // another word on another cut. Hence, we may still need to lock - // the words together afterwards. - hdmipixelsync rasync(i_pix_clk, i_reset, i_r, auto_bitslip_r, auto_r); - hdmipixelsync gasync(i_pix_clk, i_reset, i_g, auto_bitslip_g, auto_g); - hdmipixelsync basync(i_pix_clk, i_reset, i_b, auto_bitslip_b, auto_b); - // }}} - - // all_locked - // {{{ - // True if all channels are locked. - initial all_locked = 0; - always @(posedge i_pix_clk) - all_locked <= ((auto_bitslip_r[4]) - &&(auto_bitslip_g[4])&&(auto_bitslip_b[4])); - // }}} - - // o_r, o_g, o_b --- our bit-synchronized output channels - // {{{ - always @(*) - begin - o_r = auto_r; - o_g = auto_g; - o_b = auto_b; - end - // }}} - - // o_sync_word - // {{{ - // For reporting on the control bus: are we locked? And if so, how? - assign o_sync_word = { 7'h0, !all_locked, - 3'h0, auto_bitslip_r, - 3'h0, auto_bitslip_g, - 3'h0, auto_bitslip_b }; - // }}} - - // Make Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0 }; - // Verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/hdmipixelsync.v b/delete_later/rtl/hdmi/hdmipixelsync.v deleted file mode 100644 index be79af2..0000000 --- a/delete_later/rtl/hdmi/hdmipixelsync.v +++ /dev/null @@ -1,165 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: hdmipixelsync.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Generate automatic synchronization information to sync to one of -// the three HDMI color channels. The output is a bit-synchronized -// channel word. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module hdmipixelsync ( - // {{{ - input wire i_clk, i_reset, - input wire [9:0] i_px, - output wire [4:0] o_sync, - output reg [9:0] o_pix - // }}} - ); - - // Register/wire declarations - // {{{ - integer ik; - genvar gk; - reg [2*10-2:0] pre_match_win; - wire [18:0] pre_pix; - // - reg valid_match; - reg [3:0] match_loc, w_match_loc; - // - wire [3:0] chosen_match_loc; - reg sync_valid; - reg [15:0] lost_sync_counter; - reg [9:0] sync; - // }}} - - always @(posedge i_clk) - pre_match_win <= { pre_match_win[8:0], i_px }; - - // Test all possible synchronizations for a match - // {{{ - generate for(gk=0; gk<10; gk=gk+1) - begin - reg control_word; - reg [5:0] control_matches; - - always @(posedge i_clk) - begin - control_word <= 1'b0; - if((pre_match_win[gk+9:gk]== 10'h0ab) // 354 - ||(pre_match_win[gk+9:gk]==10'h354) //0ab - ||(pre_match_win[gk+9:gk]==10'h0aa) //154 - ||(pre_match_win[gk+9:gk]==10'h355))//2ab - control_word <= 1'b1; - - if (control_word) - begin - if (!control_matches[5]) - control_matches <= control_matches + 1; - end else - control_matches <= 0; - - sync[gk] <= (control_matches >= 12); - end - end endgenerate - // }}} - - // w_match_loc - // {{{ - always @(*) - begin - w_match_loc = 0; - for(ik=0; ik<10; ik=ik+1) - if (sync[ik]) - w_match_loc = w_match_loc | ik[3:0]; - end - // }}} - - // valid_match, match_log - // {{{ - always @(posedge i_clk) - begin - // valid_match, match_loc - valid_match <= (!i_reset); - match_loc <= w_match_loc; - case(sync) - 10'h001: begin end // match_loc <= 4'h0; - 10'h002: begin end // match_loc <= 4'h1; - 10'h004: begin end // match_loc <= 4'h2; - 10'h008: begin end // match_loc <= 4'h3; - 10'h010: begin end // match_loc <= 4'h4; - 10'h020: begin end // match_loc <= 4'h5; - 10'h040: begin end // match_loc <= 4'h6; - 10'h080: begin end // match_loc <= 4'h7; - 10'h100: begin end // match_loc <= 4'h8; - 10'h200: begin end // match_loc <= 4'h9; - default: valid_match <= 1'b0; - endcase - end - // }}} - - // Declare no synch when ... we don't see anything for a long time - // {{{ - initial lost_sync_counter = 16'hffff; // Start with a lost synch - always @(posedge i_clk) - if (i_reset) - lost_sync_counter <= 16'hffff; - else if (valid_match && match_loc == chosen_match_loc) - lost_sync_counter <= 0; - else if (!(&lost_sync_counter)) - lost_sync_counter <= lost_sync_counter + 1'b1; - - initial sync_valid = 1'b0; - always @(posedge i_clk) - if (&lost_sync_counter) - sync_valid <= 1'b0; - else if (valid_match) - sync_valid <= (match_loc == chosen_match_loc); - // }}} - - // Check for and remove any glitches - // {{{ - synccount #(.NBITS(4), .OPT_BYPASS_TEST(1'b0)) - pixloc(i_clk, i_reset, valid_match, match_loc, chosen_match_loc); - // }}} - - assign o_sync = { (sync_valid), chosen_match_loc }; - assign pre_pix = pre_match_win >> chosen_match_loc; - - always @(posedge i_clk) - o_pix <= pre_pix[9:0]; - - // Make Verilator happy - // {{{ - // verilog lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, pre_pix[18:10] }; - // verilog lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/sync2stream.v b/delete_later/rtl/hdmi/sync2stream.v deleted file mode 100644 index a03930b..0000000 --- a/delete_later/rtl/hdmi/sync2stream.v +++ /dev/null @@ -1,364 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sync2stream.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Given a VGA input, synchronize to it, count its size, and then -// generate an AXI video stream output to encapsulate the stream. -// -// NOTE: There's no FIFO here. The outgoing video stream therefore -// cannot handle *ANY* backpressure. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// }}} -module sync2stream #( - // {{{ - parameter [0:0] OPT_INVERT_HSYNC = 0, - parameter [0:0] OPT_INVERT_VSYNC = 0, - parameter [0:0] OPT_TUSER_IS_SOF = 0, - parameter LGDIM = 16 - // }}} - ) ( - // {{{ - input wire i_clk, - input wire i_reset, - // - input wire i_pix_valid, - input wire i_hsync, - input wire i_vsync, - input wire [24-1:0] i_pixel, - // - output reg M_AXIS_TVALID, - input wire M_AXIS_TREADY, - output reg [24-1:0] M_AXIS_TDATA, // Color - output wire M_AXIS_TLAST, // Vsync - output wire M_AXIS_TUSER, // Hsync - // - output reg [LGDIM-1:0] o_width, - output reg [LGDIM-1:0] o_hfront, - output reg [LGDIM-1:0] o_hsync, - output reg [LGDIM-1:0] o_raw_width, - // - output reg [LGDIM-1:0] o_height, - output reg [LGDIM-1:0] o_vfront, - output reg [LGDIM-1:0] o_vsync, - output reg [LGDIM-1:0] o_raw_height, - // - output wire o_locked - // }}} - ); - - // Register/wire declarations - // {{{ - wire new_data_row, hsync, vsync; - reg [LGDIM:0] hcount_pix, hcount_shelf, hcount_sync, hcount_tot; - reg hin_shelf, last_pv, hlocked; - - reg linestart, has_pixels, has_vsync, newframe, last_hs, - this_line_had_vsync, this_line_had_pixels, last_line_had_pixels; - - reg [LGDIM:0] vcount_lines, vcount_shelf, vcount_sync, vcount_tot; - reg vin_shelf, vlost_lock, vlocked; - reg empty_row; - - reg M_AXIS_HLAST, M_AXIS_VLAST; - // }}} - - // Adjust for sync inversion (if necessary) - // {{{ - assign hsync = OPT_INVERT_HSYNC ^ i_hsync; - assign vsync = OPT_INVERT_VSYNC ^ i_vsync; - // }}} - - initial last_pv = 0; - always @(posedge i_clk) - last_pv <= i_pix_valid; - - assign new_data_row = (!last_pv)&&(i_pix_valid); - - //////////////////////////////////////////////////////////////////////// - // - // Horizontal mode line - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // hcount* _pix, _shelf, _sync, _tot - // {{{ - initial hcount_pix = 0; - initial hcount_shelf = 0; - initial hcount_sync = 0; - initial hcount_tot = 0; - initial hin_shelf = 1'b1; - initial empty_row = 1; - always @(posedge i_clk) - if (new_data_row) - begin - hcount_pix <= 1; - hcount_shelf <= 0; - hcount_sync <= 0; - hcount_tot <= 1; - hin_shelf <= 0; - empty_row <= 0; - end else begin - if (!hcount_tot[LGDIM]) - hcount_tot <= hcount_tot + 1'b1; - if ((!hcount_pix[LGDIM])&&(i_pix_valid)) - hcount_pix <= hcount_pix + 1'b1; - if ((!hcount_sync[LGDIM])&&(hsync)) - hcount_sync <= hcount_sync + 1'b1; - if ((!hcount_sync[LGDIM])&&(hsync && !last_hs) && hcount_sync != 0) - empty_row <= 1; - if ((!hcount_shelf[LGDIM])&&(!i_pix_valid) - &&(!hsync)&&(hin_shelf)) - hcount_shelf <= hcount_shelf + 1'b1; - if (hsync) - hin_shelf <= 1'b0; - end - // }}} - - // o_width, o_raw_width, o_hfront, o_hsync - // {{{ - initial o_width = 0; - initial o_raw_width = 0; - initial o_hfront = 0; - initial o_hsync = 0; - always @(posedge i_clk) - if (new_data_row && !empty_row) - begin - o_width <= hcount_pix[LGDIM-1:0]; // -16'd10; - o_raw_width <= hcount_tot[LGDIM-1:0]; // +16'd1; - o_hfront <= hcount_pix[LGDIM-1:0] + hcount_shelf[LGDIM-1:0]; // + 16'd11; - o_hsync <= hcount_pix[LGDIM-1:0] + hcount_shelf[LGDIM-1:0] + hcount_sync[LGDIM-1:0]; - end - // }}} - - // hlocked - // {{{ - always @(posedge i_clk) - begin - if (new_data_row && !empty_row) - begin - hlocked <= 1; - if ({ 1'b0, o_width } != hcount_pix) - hlocked <= 0; - if ({ 1'b0, o_raw_width } != hcount_tot) - hlocked <= 0; - end - - if (i_reset) - hlocked <= 0; - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Vertical mode line - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // last_hs - // {{{ - initial last_hs = 1'b0; - always @(posedge i_clk) - last_hs <= hsync; - // }}} - - // linestart, has_pixels, has_vsync, newframe - // {{{ - initial linestart = 1'b0; - initial has_pixels = 1'b0; - initial has_vsync = 1'b0; - initial newframe = 1'b0; - always @(posedge i_clk) - if ((!last_hs)&&(hsync)) - begin - linestart <= 1'b1; - has_pixels <= 1'b0; - has_vsync <= 1'b0; - this_line_had_vsync <= has_vsync; - this_line_had_pixels <= has_pixels; - last_line_had_pixels <= last_line_had_pixels; - newframe <= (has_pixels)&&(!this_line_had_pixels); - end else begin - linestart <= 1'b0; - newframe <= 1'b0; - if (i_pix_valid) - has_pixels <= 1'b1; - if (vsync) - has_vsync <= 1'b1; - end - // }}} - - // vcount* _lines, _shelf, _sync, _tot, _lock - // {{{ - initial vcount_lines = 1; - initial vcount_shelf = 0; - initial vcount_sync = 0; - initial vcount_tot = 1; - initial vlost_lock = 1; - always @(posedge i_clk) - if (linestart) - begin - if (newframe) - begin - // We'll get here *after* the first line of a new frame - // {{{ - vcount_lines <= 1; - vcount_shelf <= 0; - vcount_sync <= 0; - vcount_tot <= 1; - vin_shelf <= 1'b1; - vlost_lock <= !hlocked; - // }}} - end else begin - // Count up - // {{{ - if (!vcount_tot[LGDIM]) - vcount_tot <= vcount_tot + 1'b1; - if ((!vcount_lines[LGDIM])&&(this_line_had_pixels)) - vcount_lines <= vcount_lines + 1'b1; - if ((!vcount_sync[LGDIM])&&(this_line_had_vsync)) - vcount_sync <= vcount_sync + 1'b1; - if ((!vcount_shelf[LGDIM])&&(!this_line_had_pixels) - &&(!this_line_had_vsync)&&(vin_shelf)) - vcount_shelf <= vcount_shelf + 1'b1; - if (this_line_had_vsync) - vin_shelf <= 1'b0; - if (!hlocked) - vlost_lock <= 1; - // }}} - end - end - // }}} - - // o_height, o_raw_height, o_vfront, o_vsync - // {{{ - initial o_height = 0; - initial o_raw_height= 0; - initial o_vfront = 0; - initial o_vsync = 0; - always @(posedge i_clk) - if (newframe) - begin - o_height <= vcount_lines[LGDIM-1:0]; - o_raw_height <= vcount_tot[LGDIM-1:0]; - o_vfront <= vcount_shelf[LGDIM-1:0] + vcount_lines[LGDIM-1:0]; - o_vsync <= vcount_sync[LGDIM-1:0] + vcount_shelf[LGDIM-1:0] - + vcount_lines[LGDIM-1:0] - 1; - end - // }}} - - // vlocked, o_locked - // {{{ - initial vlocked = 0; - always @(posedge i_clk) - begin - if (newframe) - begin - vlocked <= !vlost_lock && !vcount_tot[LGDIM]; - if ({ 1'b0, o_height } != vcount_lines) - vlocked <= 0; - if ({ 1'b0, o_raw_height } != vcount_tot) - vlocked <= 0; - end - - if (!hlocked) - vlocked <= 0; - if (i_reset) - vlocked <= 0; - end - - assign o_locked = vlocked; - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Pixel stream outputs - // {{{ - - // M_AXIS_TVALID - // {{{ - always @(posedge i_clk) - M_AXIS_TVALID <= i_pix_valid; - // }}} - - // M_AXIS_TDATA - // {{{ - always @(posedge i_clk) - M_AXIS_TDATA <= i_pixel; - // }}} - - // M_AXIS_HLAST -- last data in line signal - // {{{ - always @(posedge i_clk) - M_AXIS_HLAST <= !i_reset && i_pix_valid && (hcount_pix == o_width-1); - // }}} - - // M_AXIS_VLAST -- last data in frame signal - // {{{ - always @(posedge i_clk) - M_AXIS_VLAST <= !i_reset && i_pix_valid - && (hcount_pix == o_width-1) - && (vcount_lines == o_height-1); - // }}} - - // Adjust between VLAST == TLAST and TUSER == start of frame encodings - // (I've chosen the former, Xilinx chose the latter) - generate if (OPT_TUSER_IS_SOF) - begin : XILINXS_ENCODING - reg sof; - - assign M_AXIS_TLAST = M_AXIS_HLAST; - - always @(posedge i_clk) - if (M_AXIS_TVALID) - sof <= M_AXIS_VLAST; - - assign M_AXIS_TUSER = sof; - - end else begin : VLAST_IS_TLAST - - assign M_AXIS_TLAST = M_AXIS_VLAST; - - assign M_AXIS_TUSER = M_AXIS_HLAST; - - end endgenerate - // }}} - - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, M_AXIS_TREADY }; - // Verilator lint_on UNUSED -endmodule diff --git a/delete_later/rtl/hdmi/synccount.v b/delete_later/rtl/hdmi/synccount.v deleted file mode 100644 index 5c79fd9..0000000 --- a/delete_later/rtl/hdmi/synccount.v +++ /dev/null @@ -1,119 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: synccount.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// }}} -module synccount #( - // {{{ - // (i_clk, i_reset, i_v, i_val, o_val); - // NBITS -- num bits required to desecribe the sync location - parameter NBITS=16, - // QUALITY_BITS --require 2^QUALITY_BITS successful observations - parameter QUALITY_BITS=3, - // INITIAL_GOOD -- do we expect a particular sync? Y/N - parameter [0:0] INITIAL_GOOD = 1'b0, - // INITIAL_VALUE-- what initial sync location is expected - parameter [(NBITS-1):0] INITIAL_VALUE = 0, - // INITIAL_COUNT-- how much credibility for initial location - parameter [QUALITY_BITS-1:0] INITIAL_COUNT = 0, - // Shall we just bypass the quality test completely? - parameter [0:0] OPT_BYPASS_TEST = 1'b0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - // i_v - valid sync indicator. If (whatever) synchronization - // is found at position i_val in the stream, then i_v will be - // set. We'll see how often it gets set to know if this is - // (or isn't) a repeatable measurement. - input wire i_v, - input wire [NBITS-1:0] i_val, - output reg [NBITS-1:0] o_val - // }}} - ); - - generate if (OPT_BYPASS_TEST) - begin : BYPASS_CHECK - always @(posedge i_clk) - if (i_v) - o_val <= i_val; - end else begin : REQUIRE_QUALITY - reg inc, dec; - reg [QUALITY_BITS-1:0] ngood; - reg [(NBITS-1):0] r_val; - - reg r_eq, no_val, r_v; - - initial r_v = 1'b0; - always @(posedge i_clk) - r_v <= i_v; - - initial r_eq = 1'b0; - always @(posedge i_clk) - r_eq <= (i_val == r_val); - - initial no_val = (!INITIAL_GOOD); - always @(posedge i_clk) - no_val <= (ngood == 0); - - initial r_val = INITIAL_VALUE; - always @(posedge i_clk) - if ((r_v)&&(no_val)) - r_val <= i_val; - - initial inc = 1'b0; - initial dec = 1'b0; - always @(posedge i_clk) - begin - inc <= (!i_reset)&&(r_v)&&((r_eq)||(no_val)); - dec <= (!i_reset)&&(r_v)&&(!r_eq); - end - - initial ngood = INITIAL_COUNT; - always @(posedge i_clk) - if (i_reset) - ngood <= 0; - else if ((inc)&&(!(&ngood))) - ngood <= ngood + 1'b1; - else if ((dec)&&(ngood != 0)) - ngood <= ngood - 1'b1; - - initial o_val = INITIAL_VALUE; - always @(posedge i_clk) - if (&ngood) - o_val <= r_val; - else if (ngood == 0) - o_val <= 0; - end endgenerate -endmodule diff --git a/delete_later/rtl/hdmi/tfrstb.v b/delete_later/rtl/hdmi/tfrstb.v deleted file mode 100644 index edd1ccc..0000000 --- a/delete_later/rtl/hdmi/tfrstb.v +++ /dev/null @@ -1,299 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: tfrstb.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Illustrates a slow method of moving data across clock domains, -// together with a formal proof of the same. This is the "faster" -// version of two methods, the second one given in tfrslow.v. This one -// is faster because it requires only a single round trip of the request -// and the acknowledgement. -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module tfrstb ( - // {{{ - input wire i_a_clk, - input wire i_a_reset_n, - input wire i_a_valid, - output wire o_a_ready, - // - input wire i_b_clk, - input wire i_b_reset_n, - output reg o_b_valid, - input wire i_b_ready - // }}} - ); - - // Register declarations - // {{{ - localparam NFF = 2; - reg a_req, a_ack; - reg [NFF-2:0] a_pipe; - - reg b_req, b_last, b_stb; - reg [NFF-2:0] b_pipe; - // }}} - - // Launch - // {{{ - initial a_req = 0; - always @(posedge i_a_clk, negedge i_a_reset_n) - if (!i_a_reset_n) - a_req <= 1'b0; - else if (i_a_valid && o_a_ready) - a_req <= !a_req; - // }}} - - // Request to B - // {{{ - initial { b_last, b_req, b_pipe } = 0; - always @(posedge i_b_clk, negedge i_b_reset_n) - if (!i_b_reset_n) - { b_last, b_req, b_pipe } <= 0; - else begin - { b_last, b_req, b_pipe } <= { b_req, b_pipe, a_req }; - if (o_b_valid && !i_b_ready) - b_last <= b_last; - end - // }}} - - // Return ACK - // {{{ - always @(posedge i_a_clk, negedge i_a_reset_n) - if (!i_a_reset_n) - { a_ack, a_pipe } <= 2'b0; - else - { a_ack, a_pipe } <= { a_pipe, b_last }; - // }}} - - // Return ready - assign o_a_ready = (a_ack == a_req); - - // Outgoing strobe and data - // {{{ - always @(*) - b_stb = (b_last != b_req); - - initial o_b_valid = 0; - always @(posedge i_b_clk, negedge i_b_reset_n) - if (!i_b_reset_n) - o_b_valid <= 1'b0; - else if (!o_b_valid || i_b_ready) - o_b_valid <= b_stb; - // }}} - -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Define our registers, and f_past_valid_* - // {{{ - (* gclk *) reg gbl_clk; - reg f_past_valid_gbl, f_past_valid_a, - f_past_valid_b; - localparam LGCLK = 5; - (* anyconst *) reg [LGCLK-2:0] f_step_a, f_step_b; - reg [LGCLK-1:0] f_count_a, f_count_b; - - initial f_past_valid_gbl = 0; - always @(posedge gbl_clk) - f_past_valid_gbl <= 1; - - initial f_past_valid_a = 0; - always @(posedge i_a_clk) - f_past_valid_a <= 1; - - initial f_past_valid_b = 0; - always @(posedge i_b_clk) - f_past_valid_b <= 1; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assume two clocks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge gbl_clk) - begin - f_count_a <= f_count_a + { 1'b0, f_step_a } + 1; - f_count_b <= f_count_b + { 1'b0, f_step_b } + 1; - end - - always @(*) - assume(i_a_clk == f_count_a[LGCLK-1]); - - always @(*) - assume(i_b_clk == f_count_b[LGCLK-1]); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Reset assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Start in reset - always @(*) - if (!f_past_valid_gbl) - assume(!i_a_reset_n && !i_b_reset_n); - - // Both resets will always fall together - always @(posedge gbl_clk) - assume($fell(i_b_reset_n) == $fell(i_a_reset_n)); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Stability properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // - // On clock A - // {{{ - always @(posedge gbl_clk) - if (!$rose(i_a_clk)) - begin - assume(!$rose(i_a_reset_n)); - assume($stable(i_a_valid)); - if (i_a_reset_n) - assert($stable(o_a_ready)); - end - // }}} - - // - // On clock B - // {{{ - always @(posedge gbl_clk) - if (!$rose(i_b_clk)) - begin - assume(!$rose(i_b_reset_n)); - if (i_b_reset_n) - assume($stable(i_b_ready)); - if (f_past_valid_b && i_b_reset_n && $stable(i_b_reset_n)) - begin - assert($stable(o_b_valid)); - end - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // AXI Stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_a_clk) - if (!f_past_valid_a || !i_a_reset_n) - assume(!i_a_valid); - else if ($past(i_a_valid && !o_a_ready)) - begin - assume(i_a_valid); - end - - always @(posedge i_b_clk) - if (!f_past_valid_b || !i_b_reset_n) - assert(!o_b_valid); - else if ($past(o_b_valid && !i_b_ready)) - begin - assert(o_b_valid); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Induction - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge gbl_clk) - case({ a_ack, a_pipe, b_last, b_req, b_pipe, a_req }) - 6'b000_000: begin end - 6'b000_001: begin end - 6'b000_011: begin end - 6'b000_111: begin end - 6'b001_111: begin end - 6'b011_111: begin end - 6'b111_111: begin end - 6'b111_110: begin end - 6'b111_100: begin end - 6'b111_000: begin end - 6'b110_000: begin end - 6'b100_000: begin end - 6'b000_000: begin end - default: assert(0); - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - reg [3:0] cvr_stbcount; - initial cvr_stbcount <= 0; - always @(posedge i_b_clk, negedge i_b_reset_n) - if (!i_b_reset_n) - cvr_stbcount <= 0; - else if (o_b_valid && i_b_ready) - cvr_stbcount <= cvr_stbcount + 1; - - always @(*) - begin - cover(cvr_stbcount == 1); - cover(cvr_stbcount == 2); - cover(cvr_stbcount == 3); - cover(cvr_stbcount == 4); - cover(cvr_stbcount == 5); - // - // These next two take too much CPU time, so we don't insist - // upon them here. - // cover(cvr_stbcount == 6); - // cover(cvr_stbcount[3]); - end - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/tfrvalue.v b/delete_later/rtl/hdmi/tfrvalue.v deleted file mode 100644 index 7999f2e..0000000 --- a/delete_later/rtl/hdmi/tfrvalue.v +++ /dev/null @@ -1,321 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: tfrvalu.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Illustrates a slow method of moving data across clock domains, -// together with a formal proof of the same. This is the "faster" -// version of two methods, the second one given in tfrslow.v. This one -// is faster because it requires only a single round trip of the request -// and the acknowledgement. -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module tfrvalue #( - parameter W = 32 - ) ( - // {{{ - input wire i_a_clk, - input wire i_a_reset_n, - input wire i_a_valid, - output wire o_a_ready, - input wire [W-1:0] i_a_data, - // - input wire i_b_clk, - input wire i_b_reset_n, - output reg o_b_valid, - input wire i_b_ready, - output reg [W-1:0] o_b_data - // }}} - ); - - // Register declarations - // {{{ - localparam NFF = 2; - reg a_req, a_ack; - reg [W-1:0] a_data; - reg [NFF-2:0] a_pipe; - - reg b_req, b_last, b_stb; - reg [NFF-2:0] b_pipe; - // }}} - - // Launch - // {{{ - initial a_req = 0; - always @(posedge i_a_clk, negedge i_a_reset_n) - if (!i_a_reset_n) - a_req <= 1'b0; - else if (i_a_valid && o_a_ready) - a_req <= !a_req; - - always @(posedge i_a_clk) - if (i_a_valid && o_a_ready) - a_data <= i_a_data; - // }}} - - // Request to B - // {{{ - initial { b_last, b_req, b_pipe } = 0; - always @(posedge i_b_clk, negedge i_b_reset_n) - if (!i_b_reset_n) - { b_last, b_req, b_pipe } <= 0; - else begin - { b_last, b_req, b_pipe } <= { b_req, b_pipe, a_req }; - if (o_b_valid && !i_b_ready) - b_last <= b_last; - end - // }}} - - // Return ACK - // {{{ - always @(posedge i_a_clk, negedge i_a_reset_n) - if (!i_a_reset_n) - { a_ack, a_pipe } <= 2'b0; - else - { a_ack, a_pipe } <= { a_pipe, b_last }; - // }}} - - // Return ready - assign o_a_ready = (a_ack == a_req); - - // Outgoing strobe and data - // {{{ - always @(*) - b_stb = (b_last != b_req); - - initial o_b_data = 0; - always @(posedge i_b_clk) - if (b_stb && (!o_b_valid || i_b_ready)) - o_b_data <= a_data; - - initial o_b_valid = 0; - always @(posedge i_b_clk, negedge i_b_reset_n) - if (!i_b_reset_n) - o_b_valid <= 1'b0; - else if (!o_b_valid || i_b_ready) - o_b_valid <= b_stb; - // }}} - -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Define our registers, and f_past_valid_* - // {{{ - (* gclk *) reg gbl_clk; - reg f_past_valid_gbl, f_past_valid_a, - f_past_valid_b; - localparam LGCLK = 5; - (* anyconst *) reg [LGCLK-2:0] f_step_a, f_step_b; - reg [LGCLK-1:0] f_count_a, f_count_b; - - initial f_past_valid_gbl = 0; - always @(posedge gbl_clk) - f_past_valid_gbl <= 1; - - initial f_past_valid_a = 0; - always @(posedge i_a_clk) - f_past_valid_a <= 1; - - initial f_past_valid_b = 0; - always @(posedge i_b_clk) - f_past_valid_b <= 1; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assume two clocks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge gbl_clk) - begin - f_count_a <= f_count_a + { 1'b0, f_step_a } + 1; - f_count_b <= f_count_b + { 1'b0, f_step_b } + 1; - end - - always @(*) - assume(i_a_clk == f_count_a[LGCLK-1]); - - always @(*) - assume(i_b_clk == f_count_b[LGCLK-1]); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Reset assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Start in reset - always @(*) - if (!f_past_valid_gbl) - assume(!i_a_reset_n && !i_b_reset_n); - - // Both resets will always fall together - always @(posedge gbl_clk) - assume($fell(i_b_reset_n) == $fell(i_a_reset_n)); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Stability properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // - // On clock A - // {{{ - always @(posedge gbl_clk) - if (!$rose(i_a_clk)) - begin - assume(!$rose(i_a_reset_n)); - assume($stable(i_a_valid)); - assume($stable(i_a_data)); - if (i_a_reset_n) - assert($stable(o_a_ready)); - end - // }}} - - // - // On clock B - // {{{ - always @(posedge gbl_clk) - if (!$rose(i_b_clk)) - begin - assume(!$rose(i_b_reset_n)); - if (i_b_reset_n) - assume($stable(i_b_ready)); - if (f_past_valid_b && i_b_reset_n && $stable(i_b_reset_n)) - begin - assert($stable(o_b_valid)); - assert($stable(o_b_data)); - end - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // AXI Stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_a_clk) - if (!f_past_valid_a || !i_a_reset_n) - assume(!i_a_valid); - else if ($past(i_a_valid && !o_a_ready)) - begin - assume(i_a_valid); - assume($stable(i_a_data)); - end - - always @(posedge i_b_clk) - if (!f_past_valid_b || !i_b_reset_n) - assert(!o_b_valid); - else if ($past(o_b_valid && !i_b_ready)) - begin - assert(o_b_valid); - assert($stable(o_b_data)); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Induction - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge gbl_clk) - case({ a_ack, a_pipe, b_last, b_req, b_pipe, a_req }) - 6'b000_000: begin end - 6'b000_001: begin end - 6'b000_011: begin end - 6'b000_111: begin end - 6'b001_111: begin end - 6'b011_111: begin end - 6'b111_111: begin end - 6'b111_110: begin end - 6'b111_100: begin end - 6'b111_000: begin end - 6'b110_000: begin end - 6'b100_000: begin end - 6'b000_000: begin end - default: assert(0); - endcase - - always @(posedge i_b_clk) - if ( (!(&{b_req, b_pipe})) && ({b_req, b_pipe} != 0) ) - assert($stable(a_data)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - reg [3:0] cvr_stbcount; - initial cvr_stbcount <= 0; - always @(posedge i_b_clk, negedge i_b_reset_n) - if (!i_b_reset_n) - cvr_stbcount <= 0; - else if (o_b_valid && i_b_ready && (o_b_data[3:0] == cvr_stbcount)) - cvr_stbcount <= cvr_stbcount + 1; - - always @(*) - begin - cover(cvr_stbcount == 1); - cover(cvr_stbcount == 2); - cover(cvr_stbcount == 3); - cover(cvr_stbcount == 4); - cover(cvr_stbcount == 5); - // - // These next two take too much CPU time, so we don't insist - // upon them here. - // cover(cvr_stbcount == 6); - // cover(cvr_stbcount[3]); - end - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/tmdsdecode.v b/delete_later/rtl/hdmi/tmdsdecode.v deleted file mode 100644 index 643cc9a..0000000 --- a/delete_later/rtl/hdmi/tmdsdecode.v +++ /dev/null @@ -1,142 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: tmdsdecode.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Convert incoming TMDS data into usable pixel and packet data. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module tmdsdecode( - // {{{ - input wire i_clk, - input wire [9:0] i_word, - output wire [1:0] o_ctl, - output wire [6:0] o_aux, - output wire [7:0] o_pix - // }}} - ); - - // Local declarations - // {{{ - reg [1:0] r_ctl; - reg [6:0] r_aux; - reg [7:0] r_pix; - wire [9:0] first_midp; - wire [9:0] brev_word; - // }}} - - // r_pix generation - // {{{ - assign first_midp = { - ((i_word[0]) ? (~i_word[9:2]) : (i_word[9:2])), - i_word[1:0] }; - - always @(posedge i_clk) - if (first_midp[1]) - begin - r_pix[0] <= (first_midp[9]); - r_pix[1] <= (first_midp[8] ^ first_midp[9]); - r_pix[2] <= (first_midp[7] ^ first_midp[8]); - r_pix[3] <= (first_midp[6] ^ first_midp[7]); - r_pix[4] <= (first_midp[5] ^ first_midp[6]); - r_pix[5] <= (first_midp[4] ^ first_midp[5]); - r_pix[6] <= (first_midp[3] ^ first_midp[4]); - r_pix[7] <= (first_midp[2] ^ first_midp[3]); - end else begin - r_pix[0] <= first_midp[9]; - r_pix[1] <= !(first_midp[8] ^ first_midp[9]); - r_pix[2] <= !(first_midp[7] ^ first_midp[8]); - r_pix[3] <= !(first_midp[6] ^ first_midp[7]); - r_pix[4] <= !(first_midp[5] ^ first_midp[6]); - r_pix[5] <= !(first_midp[4] ^ first_midp[5]); - r_pix[6] <= !(first_midp[3] ^ first_midp[4]); - r_pix[7] <= !(first_midp[2] ^ first_midp[3]); - end - // }}} - - // Bit-reverse i_word - // {{{ - genvar k; - generate for(k=0; k<10; k=k+1) - assign brev_word[k] = i_word[9-k]; - endgenerate - // }}} - - // AUX and control channel decoding - // {{{ - always @(posedge i_clk) - begin - r_aux <= 7'h0; - r_ctl <= 2'b00; - // - case(brev_word) - // 2-bit control period coding - 10'h354: begin r_aux <= 7'h10; r_ctl <= 2'h0; end - 10'h0ab: begin r_aux <= 7'h11; r_ctl <= 2'h1; end - 10'h154: begin r_aux <= 7'h12; r_ctl <= 2'h2; end - 10'h2ab: begin r_aux <= 7'h13; r_ctl <= 2'h3; end - // TERC4 coding - 10'h29c: begin r_aux <= 7'h20; r_ctl <= 2'h0; end - 10'h263: begin r_aux <= 7'h21; r_ctl <= 2'h1; end - 10'h2e4: begin r_aux <= 7'h22; r_ctl <= 2'h2; end - 10'h2e2: begin r_aux <= 7'h23; r_ctl <= 2'h3; end - 10'h171: begin r_aux <= 7'h24; r_ctl <= 2'h0; end - 10'h11e: begin r_aux <= 7'h25; r_ctl <= 2'h1; end - 10'h18e: begin r_aux <= 7'h26; r_ctl <= 2'h2; end - 10'h13c: begin r_aux <= 7'h27; r_ctl <= 2'h3; end - // This next pixel is also a guard pixel - 10'h2cc: begin r_aux <= 7'h68; r_ctl <= 2'h0; end - // - 10'h139: begin r_aux <= 7'h29; r_ctl <= 2'h1; end - 10'h19c: begin r_aux <= 7'h2a; r_ctl <= 2'h2; end - 10'h2c6: begin r_aux <= 7'h2b; r_ctl <= 2'h3; end - 10'h28e: begin r_aux <= 7'h2c; r_ctl <= 2'h0; end - 10'h271: begin r_aux <= 7'h2d; r_ctl <= 2'h1; end - 10'h163: begin r_aux <= 7'h2e; r_ctl <= 2'h2; end - 10'h2c3: begin r_aux <= 7'h2f; r_ctl <= 2'h3; end - // Guard band characters - //10'h2cc:r_aux<= 8'h38; // done above - 10'h133: begin r_aux <= 7'h41; r_ctl <= 2'h0; end - default: begin end - endcase - end - // }}} - - assign o_ctl = r_ctl; - assign o_aux = r_aux; - assign o_pix = r_pix; - - // Make verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = first_midp[0]; - // verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/tmdsencode.v b/delete_later/rtl/hdmi/tmdsencode.v deleted file mode 100644 index b4e6f00..0000000 --- a/delete_later/rtl/hdmi/tmdsencode.v +++ /dev/null @@ -1,246 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: tmdsencode.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Take pixel/packet data, and encode them into a TMDS signal -// for HDMI transport. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module tmdsencode ( - input wire i_clk, - input wire [1:0] i_dtype, - input wire [1:0] i_ctl, - input wire [3:0] i_aux, - input wire [7:0] i_data, - output wire [9:0] o_word - ); - - parameter [1:0] CHANNEL = 2'b00; - - // Data Types: - // 2'b00 Guard band - // 2'b01 Control period - // 2'b10 Data Island - // 2'b11 Pixel Data - // - - /////////////////////////////// - // - // Guard band - // - reg [9:0] guard_word; - always @(*) - case(CHANNEL) - 2'b00: guard_word = 10'b1011001100; - 2'b01: guard_word = 10'b0100110011; - default: guard_word = 10'b1011001100; - endcase - - reg [1:0] r_dtype; - always @(posedge i_clk) - r_dtype <= i_dtype[1:0]; - - /////////////////////////////// - // - // Control signal encoding - reg [9:0] ctrl_word; - reg [1:0] r_ctl; - - always @(posedge i_clk) - r_ctl <= i_ctl; - - - always @(posedge i_clk) - case(r_ctl[1:0]) - 2'b00: ctrl_word <= 10'b11_0101_0100; - 2'b01: ctrl_word <= 10'b00_1010_1011; - 2'b10: ctrl_word <= 10'b01_0101_0100; - 2'b11: ctrl_word <= 10'b10_1010_1011; - endcase - - /////////////////////////////// - // - // Auxilliary encoding - // - reg [9:0] aux_word; - reg [3:0] r_aux; - - always @(posedge i_clk) - r_aux <= i_aux; - - always @(posedge i_clk) - case(r_aux) - 4'b0000: aux_word <= 10'b10_1001_1100; - 4'b0001: aux_word <= 10'b10_0110_0011; - 4'b0010: aux_word <= 10'b10_1110_0100; - 4'b0011: aux_word <= 10'b10_1110_0010; - // - 4'b0100: aux_word <= 10'b01_0111_0001; - 4'b0101: aux_word <= 10'b01_0001_1110; - 4'b0110: aux_word <= 10'b01_1000_1110; - 4'b0111: aux_word <= 10'b01_0011_1100; - // - 4'b1000: aux_word <= 10'b10_1100_1100; - 4'b1001: aux_word <= 10'b01_0011_1001; - 4'b1010: aux_word <= 10'b01_1001_1100; - 4'b1011: aux_word <= 10'b10_1100_0110; - // - 4'b1100: aux_word <= 10'b10_1000_1110; - 4'b1101: aux_word <= 10'b10_0111_0001; - 4'b1110: aux_word <= 10'b01_0110_0011; - 4'b1111: aux_word <= 10'b10_1100_0011; - endcase - - /////////////////////////////// - // - // Pixel data encoding - // - reg [3:0] ones, ones_counter; - reg [3:0] qm_ones, qm_ones_counter; - reg [8:0] q_m; - reg [9:0] pix_word; - - integer k; - - always @(*) - begin - ones_counter = 0; - for(k=0; k<8; k=k+1) - if (i_data[k]) - ones_counter = ones_counter + 1; - ones = ones_counter; - end - - always @(*) - begin - qm_ones_counter = 0; - for(k=0; k<8; k=k+1) - if (q_m[k]) - qm_ones_counter = qm_ones_counter + 1; - qm_ones = ones_counter; - end - - wire [3:0] qm_zeros; - // assign zeros = 4'h8-ones; - assign qm_zeros = 4'h8-qm_ones; - - // Take one always block to generate q_m - // This is q_m(pre) - reg [8:0] q_mp; - - always @(*) - // 8-bit pixel data - if ((ones > 4)||((ones == 4)&&(i_data[7]))) - begin - q_mp[0] = i_data[0]; - q_mp[1] = !(q_mp[0] ^ i_data[1]); - q_mp[2] = !(q_mp[1] ^ i_data[2]); - q_mp[3] = !(q_mp[2] ^ i_data[3]); - q_mp[4] = !(q_mp[3] ^ i_data[4]); - q_mp[5] = !(q_mp[4] ^ i_data[5]); - q_mp[6] = !(q_mp[5] ^ i_data[6]); - q_mp[7] = !(q_mp[6] ^ i_data[7]); - q_mp[8] = 1'b0; - end else begin - q_mp[0] = i_data[0]; - q_mp[1] = q_mp[0] ^ i_data[1]; - q_mp[2] = q_mp[1] ^ i_data[2]; - q_mp[3] = q_mp[2] ^ i_data[3]; - q_mp[4] = q_mp[3] ^ i_data[4]; - q_mp[5] = q_mp[4] ^ i_data[5]; - q_mp[6] = q_mp[5] ^ i_data[6]; - q_mp[7] = q_mp[6] ^ i_data[7]; - q_mp[8] = 1'b1; - end - - always @(posedge i_clk) - q_m <= q_mp; - - reg signed [4:0] count; - initial count = 0; - - always @(posedge i_clk) - if ((count == 0)||(qm_ones == qm_zeros)) - begin - pix_word[9] <= !q_m[8]; - pix_word[8] <= q_m[8]; - pix_word[7:0]<= (q_m[8] ? q_m[7:0] : (~q_m[7:0])); - if (q_m[8]) - count <= count + (qm_ones - qm_zeros); - else - count <= count + (qm_zeros - qm_ones); - end else if (((count > 0)&&(qm_ones > qm_zeros)) - ||((count < 0)&&(qm_zeros > qm_ones))) - begin - pix_word[9] <= 1'b1; - pix_word[8] <= q_m[8]; - pix_word[7:0] <= ~q_m[7:0]; - count <= count + (q_m[8] ? 5'h2 : 0) - +(qm_zeros - qm_ones); - end else begin - pix_word[9] <= 1'b0; - pix_word[8] <= q_m[8]; - pix_word[7:0] <= q_m[7:0]; - count <= count - (q_m[8] ? 0 : 5'h2) - + (qm_ones - qm_zeros); - end - - reg [1:0] s_dtype; - always @(posedge i_clk) - s_dtype <= r_dtype; - - // 2'b00 Guard band - // 2'b01 Control period - // 2'b10 Data Island - // 2'b11 Pixel Data - // - reg [9:0] brv_word; - always @(posedge i_clk) - case(s_dtype) - 2'b00: brv_word <= guard_word; - 2'b01: brv_word <= ctrl_word; - 2'b10: brv_word <= aux_word; - 2'b11: brv_word <= pix_word; - endcase - - genvar gk; - generate for(gk=0; gk<10; gk=gk+1) - assign o_word[gk] = brv_word[9-gk]; - endgenerate - -`ifdef FORMAL - initial assert(CHANNEL < 2'b11); - - always @(*) - assert(count < 5'sd10); - always @(*) - assert(count > -5'sd10); -`endif -endmodule diff --git a/delete_later/rtl/hdmi/vid_empty.v b/delete_later/rtl/hdmi/vid_empty.v deleted file mode 100644 index d3345e1..0000000 --- a/delete_later/rtl/hdmi/vid_empty.v +++ /dev/null @@ -1,196 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: vid_empty.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Generates an outgoing video stream, having all the proper -// video stream signals, but with a constant pixel value. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module vid_empty #( - // {{{ - parameter PW = 24, - parameter LGFRAME = 12, - parameter [PW-1:0] PIXEL = 0, - parameter [0:0] OPT_TUSER_IS_SOF = 1 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire [LGFRAME-1:0] i_width, i_height, - // - output reg M_VID_VALID, - input wire M_VID_READY, - output wire [PW-1:0] M_VID_DATA, - output wire M_VID_LAST, - output wire M_VID_USER - // }}} - ); - - // Local declarations - // {{{ - reg hlast, vlast; - reg [LGFRAME-1:0] xpos, ypos; - // }}} - - // M_VID_VALID - // {{{ - always @(posedge i_clk) - if (i_reset) - M_VID_VALID <= 0; - else - M_VID_VALID <= 1; - // }}} - - assign M_VID_DATA = PIXEL; - - // xpos, ypos, hlast, vlast - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - xpos <= 0; - ypos <= 0; - hlast <= 0; - vlast <= 0; - end else if (M_VID_VALID && M_VID_READY) - begin - xpos <= xpos + 1; - hlast <= (xpos >= i_width-2); - - if (hlast) - begin - hlast <= 0; - xpos <= 0; - vlast <= (ypos >= i_height-2); - ypos <= ypos + 1; - - if (vlast) - begin - vlast <= 0; - ypos <= 0; - end - end - end - // }}} - - generate if (OPT_TUSER_IS_SOF) - begin - reg sof; - - always @(posedge i_clk) - if (i_reset) - sof <= 1; - else if (M_VID_VALID && M_VID_READY) - sof <= hlast && vlast; - - assign M_VID_LAST = hlast; - assign M_VID_USER = sof; -`ifdef FORMAL - always @(*) - if (!i_reset) - assert(sof == (xpos == 0 && ypos == 0)); -`endif - end else begin - assign M_VID_LAST = vlast & hlast; - assign M_VID_USER = hlast; - end endgenerate -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - wire [LGFRAME-1:0] f_xpos, f_ypos; - wire f_hlast, f_vlast, f_sof, f_known_height; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - always @(posedge i_clk) - if (!i_reset) - begin - assume($stable(i_width)); - assume($stable(i_height)); - - assume(i_width > 2); - assume(i_height > 2); - end - - faxivideo #( - // {{{ - .PW(PW), .LGDIM(LGFRAME), .OPT_TUSER_IS_SOF(OPT_TUSER_IS_SOF) - // }}} - ) fvid ( - // {{{ - .i_clk(i_clk), .i_reset_n(!i_reset), - .S_VID_TVALID(M_VID_VALID), - .S_VID_TREADY(M_VID_READY), - .S_VID_TDATA(M_VID_DATA), - .S_VID_TLAST(M_VID_LAST), - .S_VID_TUSER(M_VID_USER), - // - .i_width(i_width), .i_height(i_height), - .o_xpos(f_xpos), .o_ypos(f_ypos), - .f_known_height(f_known_height), - .o_hlast(f_hlast), .o_vlast(f_vlast), .o_sof(f_sof) - // }}} - ); - - always @(*) - if (!i_reset) - begin - assert(xpos == f_xpos); - assert(ypos == f_ypos); - assert(hlast == f_hlast); - assert(vlast == f_vlast); - end - - always @(*) - cover(!i_reset && M_VID_VALID && hlast && vlast); - - generate if (OPT_TUSER_IS_SOF) - begin - always @(posedge i_clk) - cover(!i_reset && M_VID_VALID && $rose(M_VID_USER)); - end endgenerate -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/vid_mux.v b/delete_later/rtl/hdmi/vid_mux.v deleted file mode 100644 index ae0cf83..0000000 --- a/delete_later/rtl/hdmi/vid_mux.v +++ /dev/null @@ -1,411 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: vid_mux.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: To select from among many potential video sources, and to do -// so without ever losing video sync. Hence, the source selection -// must take place between frames, and remain AXI stream compliant. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module vid_mux #( - // {{{ - parameter NIN = 5, - parameter LGDIM = 11, - parameter PW = 24, - parameter DEF_SELECT = 0, - parameter [0:0] OPT_TUSER_IS_SOF = 0 - // }}} - ) ( - // {{{ - input wire S_AXI_ACLK, S_AXI_ARESETN, - // - input wire [NIN-1:0] S_VID_VALID, - output reg [NIN-1:0] S_VID_READY, - input wire [NIN*PW-1:0] S_VID_DATA, - input wire [NIN-1:0] S_VID_LAST, // HLAST - input wire [NIN-1:0] S_VID_USER, // SOF - // - output reg M_VID_VALID, - input wire M_VID_READY, - output reg [PW-1:0] M_VID_DATA, - output reg M_VID_LAST, // HLAST - output reg M_VID_USER, // SOF - // - input wire [$clog2(NIN)-1:0] i_select - // }}} - ); - - // local declarations - // {{{ - localparam LGNIN = $clog2(NIN); - reg [LGNIN-1:0] r_framesel; - reg adjust_select; - reg M_VID_HLAST, M_VID_VLAST; - wire [NIN-1:0] S_VID_HLAST, S_VID_VLAST, S_VID_SOF; - wire [NIN-1:0] eof; - reg [NIN-1:0] new_frame; - genvar gk; - integer ik; - // }}} - - // r_framesel - // {{{ - initial r_framesel = ({ 1'b0, DEF_SELECT[LGNIN-1:0] } < NIN[LGNIN:0]) ? DEF_SELECT : 0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - r_framesel <= ({ 1'b0, DEF_SELECT[LGNIN-1:0] } < NIN[LGNIN:0]) ? DEF_SELECT : 0; - else if (adjust_select && { 1'b0, i_select } < NIN[LGNIN:0]) - r_framesel <= i_select; - // }}} - - // M_VID_VALID - // {{{ - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - M_VID_VALID <= 0; - else if (!M_VID_VALID || M_VID_READY) - M_VID_VALID <= S_VID_VALID[r_framesel]&&S_VID_READY[r_framesel]; - // }}} - - // M_VID_DATA - // {{{ - always @(posedge S_AXI_ACLK) - if (!M_VID_VALID || M_VID_READY) - begin - for(ik=0; ik < NIN; ik=ik+1) - if (r_framesel == ik[$clog2(NIN)-1:0]) - M_VID_DATA <= S_VID_DATA[ik * PW +: PW]; - end - // }}} - - // M_VID_LAST, M_VID_USER, M_VID_HLAST, M_VID_VLAST - // {{{ - always @(posedge S_AXI_ACLK) - if (!M_VID_VALID || M_VID_READY) - begin - M_VID_LAST <= S_VID_LAST[r_framesel]; - M_VID_USER <= S_VID_USER[r_framesel]; - M_VID_HLAST <= S_VID_HLAST[r_framesel]; - M_VID_VLAST <= S_VID_VLAST[r_framesel]; - end - // }}} - - // adjust_select - // {{{ - assign eof = S_VID_VALID & S_VID_READY & S_VID_HLAST & S_VID_VLAST; - - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - adjust_select <= 1; - else if (adjust_select) - begin - if ({ 1'b0, i_select } < NIN[LGNIN:0]) - adjust_select <= !new_frame[i_select]; - end else if (|(eof & (1<= 3 && f_height >= 1); - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Output stream assertions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - faxivideo #( - // {{{ - .PW(PW), .LGDIM(LGDIM), .OPT_SOURCE(1'b0), - .OPT_TUSER_IS_SOF(OPT_TUSER_IS_SOF) - // }}} - ) f_master ( - // {{{ - .i_clk(S_AXI_ACLK), .i_reset_n(S_AXI_ARESETN), - // - .S_VID_TVALID(M_VID_VALID), - .S_VID_TREADY(M_VID_READY), - .S_VID_TDATA(M_VID_DATA), - .S_VID_TLAST(M_VID_LAST), - .S_VID_TUSER(M_VID_USER), - .i_width(fm_width), .i_height(fm_height), - .o_xpos(fm_xpos), .o_ypos(fm_ypos), - .f_known_height(fm_known), - .o_hlast(fm_hlast), .o_vlast(fm_vlast), .o_sof(fm_sof) - // }}} - ); - - always @(*) - if (S_AXI_ARESETN && M_VID_VALID) - begin - assert(M_VID_LAST == (fm_hlast && fm_vlast)); - assert(M_VID_USER == fm_hlast); - end - - always @(*) - if (S_AXI_ARESETN && adjust_select) - begin - if (M_VID_VALID) - begin - assert(M_VID_HLAST); - if (!OPT_TUSER_IS_SOF) - assert(M_VID_VLAST); - end else begin - assert(fm_xpos == 0); - assert(fm_ypos == 0); - end - end - - always @(*) - if (S_AXI_ARESETN) - assert(r_framesel < NIN); - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/vid_wbframebuf.v b/delete_later/rtl/hdmi/vid_wbframebuf.v deleted file mode 100644 index 5941048..0000000 --- a/delete_later/rtl/hdmi/vid_wbframebuf.v +++ /dev/null @@ -1,802 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: vid_wbframebuf.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A video framebuffer. Reads data from the Wishbone bus, and -// uses it to generate an AXI video/pixel stream. -// -// This particular implementation was drawn from the waterfall reader, -// with modifications made so that: 1) lines are read in vertical order, -// starting at the *top*, and 2) there is no line wrapping. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module vid_wbframebuf #( - // {{{ - parameter AW = 28, DW = 32, - PW = 8, // Video pixel width - parameter LGFRAME = 11, - parameter LGFIFO = 9, - parameter LGBURST = LGFIFO-1, - parameter [0:0] OPT_MSB_FIRST = 1'b1, - parameter [0:0] OPT_TUSER_IS_SOF = 1'b1, -`ifdef FORMAL - parameter [0:0] OPT_ASYNC_CLOCKS = 1'b0 -`else - parameter [0:0] OPT_ASYNC_CLOCKS = 1'b1 -`endif - // }}} - ) ( - // {{{ -`ifdef FORMAL - input wire i_clk, -`else - input wire i_clk, i_pixclk, -`endif - // Verilator lint_off SYNCASYNCNET - input wire i_reset, - // Verilator lint_on SYNCASYNCNET - // Video information - // {{{ - input wire i_cfg_en, - input wire [LGFRAME-1:0] i_height, i_mem_words, - input wire [AW-1:0] i_baseaddr, - // }}} - // Wishbone bus master - // {{{ - output reg o_wb_cyc, o_wb_stb, - output wire o_wb_we, - output reg [AW-1:0] o_wb_addr, - output wire [DW-1:0] o_wb_data, - output wire [DW/8-1:0] o_wb_sel, - // - input wire i_wb_stall, - input wire i_wb_ack, - input wire [DW-1:0] i_wb_data, - input wire i_wb_err, - // }}} - // Outgoing video stream - // {{{ - output wire M_VID_TVALID, - input wire M_VID_TREADY, - output wire [PW-1:0] M_VID_TDATA, - output wire M_VID_TLAST, - output wire M_VID_TUSER - // }}} - // }}} - ); - - // Local declarations - // {{{ - wire wb_reset; - assign wb_reset = i_reset || (o_wb_cyc && i_wb_err); - - reg last_ack, last_request; - reg [LGBURST:0] wb_outstanding; - - wire ign_fifo_full, fifo_empty, afifo_empty; - wire [LGFIFO:0] fifo_fill; - wire [DW-1:0] fifo_data, afifo_data; - - wire fifo_read; - reg afifo_read; - reg [LGFRAME-1:0] m_hpos, m_vpos; - reg M_VID_HLAST, M_VID_VLAST; - - reg wb_hlast, wb_vlast; - reg [LGFRAME-1:0] wb_hpos, wb_vpos; // , line_step; - reg [AW-1:0] line_addr; - - reg rx_vlast, rx_hlast; - reg [LGFRAME-1:0] rx_hpos, rx_vpos; - wire fifo_vlast, fifo_hlast; - wire afifo_vlast, afifo_hlast; - -`ifdef FORMAL - wire i_pixclk = i_clk; -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // 1. Issue Wishbone read requests - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - // ... of length 1) a burst, 2) whatever keeps the - // FIFO from filling, and 3) up until the end of the line - - // o_wb_cyc, o_wb_stb - // {{{ - initial { o_wb_cyc, o_wb_stb } = 2'b00; - always @(posedge i_clk) - if (wb_reset || !i_cfg_en) - { o_wb_cyc, o_wb_stb } <= 2'b00; - else if (o_wb_cyc) - begin - if (!o_wb_stb || !i_wb_stall) - o_wb_stb <= !last_request; - - if (i_wb_ack && (!o_wb_stb || !i_wb_stall) - && last_request && last_ack) - o_wb_cyc <= 1'b0; - end else if (fifo_fill[LGFIFO:LGBURST] == 0) - { o_wb_cyc, o_wb_stb } <= 2'b11; - // }}} - - assign o_wb_we = 1'b0; - assign o_wb_data = 0; - assign o_wb_sel = -1; - - // wb_outstanding - // {{{ - always @(posedge i_clk) - if (i_reset || !o_wb_cyc || i_wb_err) - wb_outstanding <= 0; - else case({ o_wb_stb && !i_wb_stall, i_wb_ack }) - 2'b10: wb_outstanding <= wb_outstanding + 1; - 2'b01: wb_outstanding <= wb_outstanding - 1; - default: begin end - endcase - // }}} - - // last_ack - // {{{ - always @(posedge i_clk) - if (i_reset || !o_wb_cyc || i_wb_err) - last_ack <= 0; - else - last_ack <= (wb_outstanding + (o_wb_stb ? 1:0) - <= 1 +(i_wb_ack ? 1:0)); - // }}} - - // last_request - // {{{ - always @(posedge i_clk) - if (i_reset || !o_wb_cyc) - last_request <= 0; - else if (wb_outstanding+(o_wb_stb ? 1:0) >= { 1'b0, {(LGBURST){1'b1}} }) - last_request <= 1; - else if (wb_outstanding + fifo_fill + 1 + (o_wb_stb ? 1:0) >= (1<= i_mem_words); - - if (wb_hlast) - begin - wb_hlast<= 0; - wb_hpos <= 0; - wb_vpos <= wb_vpos + 1; - - o_wb_addr <= line_addr; - // Verilator lint_off WIDTH - line_addr <= line_addr + i_mem_words; - // Verilator lint_on WIDTH - wb_vlast <= (wb_vpos + 2>= i_height); - if (wb_vlast) - begin - // Verilator lint_off WIDTH - line_addr <= i_baseaddr + i_mem_words; - // Verilator lint_on WIDTH - o_wb_addr <= i_baseaddr; - wb_vlast <= 0; - wb_vpos <= 0; - end - end - // }}} - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // 2. Store the pixels into a FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // rx_[hv]pos, rx_[hv]last - always @(posedge i_clk) - if (wb_reset || !i_cfg_en) - begin - // {{{ - rx_hpos <= 0; - rx_vpos <= 0; - rx_hlast <= 0; - rx_vlast <= 0; - // }}} - end else if (!o_wb_cyc) - begin - // {{{ - rx_hpos <= wb_hpos; - rx_vpos <= wb_vpos; - rx_hlast <= wb_hlast; - rx_vlast <= wb_vlast; - // }}} - end else if (i_wb_ack) - begin - // {{{ - rx_hpos <= rx_hpos + 1; - rx_hlast <= (rx_hpos + 2 >= i_mem_words); - if (rx_hlast) - begin - // {{{ - rx_hpos <= 0; - rx_hlast <= 0; - - rx_vpos <= rx_vpos + 1; - rx_vlast <= (rx_vpos + 2 >= i_height); - if (rx_vlast) - begin - rx_vpos <= 0; - rx_vlast <= 0; - end - // }}} - end - // }}} - end - - sfifo #( - .BW(DW+2), .LGFLEN(LGFIFO), .OPT_ASYNC_READ(1'b0) - ) pxfifo ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wr(i_wb_ack), .i_data({ rx_vlast, rx_hlast, i_wb_data }), - .o_full(ign_fifo_full), .o_fill(fifo_fill), - .i_rd(fifo_read), - .o_data({ fifo_vlast, fifo_hlast, fifo_data }), - .o_empty(fifo_empty) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // 3. Cross clock domains - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wire pix_clk, pix_reset; - - generate if (OPT_ASYNC_CLOCKS) - begin : GEN_ASYNC_FIFO - // {{{ - reg r_pix_reset; - reg [2:0] r_pix_reset_pipe; - wire afifo_full; - - initial { r_pix_reset, r_pix_reset_pipe } = -1; - always @(posedge i_pixclk or posedge i_reset) - if (i_reset) - { r_pix_reset, r_pix_reset_pipe } <= -1; - else - { r_pix_reset, r_pix_reset_pipe } <= { r_pix_reset_pipe, 1'b0 }; - - afifo #( - .WIDTH(DW+2), .LGFIFO(3) - ) pxfifo ( - // {{{ - .i_wclk(i_clk), .i_wr_reset_n(!i_reset), - .i_wr(fifo_read), - .i_wr_data({ fifo_vlast,fifo_hlast,fifo_data }), - .o_wr_full(afifo_full), - .i_rclk(i_pixclk), .i_rd_reset_n(!pix_reset), - .i_rd(afifo_read), - .o_rd_data({ afifo_vlast, afifo_hlast, - afifo_data }), - .o_rd_empty(afifo_empty) - // }}} - ); - - assign fifo_read = !fifo_empty && !afifo_full; - assign pix_clk = i_pixclk; - assign pix_reset = r_pix_reset; - // }}} - end else begin - // {{{ - assign pix_clk = i_clk; - assign pix_reset = i_reset; - assign fifo_read = afifo_read; - assign afifo_empty = fifo_empty; - assign { afifo_vlast, afifo_hlast, afifo_data } - = { fifo_vlast, fifo_hlast, fifo_data }; - // }}} - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // 3. Unpack the FIFO words into pixels of PW bits each - // {{{ - // ... and generate an AXI-S video output stream - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (PW != DW) - begin : GEN_REWIDTH - // {{{ - reg px_valid; - reg [$clog2(DW+1)-1:0] px_count; - reg px_vlast, px_hlast, px_lost_sync; - reg [DW-1:0] px_data; - - // afifo_read - // {{{ - always @(*) - begin - afifo_read = (px_count <= PW || !px_valid - || (M_VID_TVALID && M_VID_TREADY && M_VID_HLAST)); - if (M_VID_TVALID && !M_VID_TREADY) - afifo_read = 1'b0; - - if (px_lost_sync && (!px_hlast || !px_vlast)) - afifo_read = 1'b1; - end - // }}} - - // px_valid - // {{{ - initial px_valid = 0; - always @(posedge pix_clk) - if (pix_reset) - px_valid <= 0; - else if (px_lost_sync || !M_VID_TVALID || M_VID_TREADY) - begin - if (afifo_read) - px_valid <= !afifo_empty; - else - px_valid <= 1; - end - // }}} - - // px_count - // {{{ - initial px_count = 0; - always @(posedge pix_clk) - if (pix_reset) - px_count <= DW; - else if (px_lost_sync || !M_VID_TVALID || M_VID_TREADY) - begin - if (afifo_read) - px_count <= (afifo_empty) ? 0 : DW; - else - px_count <= px_count - PW; - end - // }}} - - // px_hlast, px_vlast - // {{{ - initial { px_vlast, px_hlast } = 0; - always @(posedge pix_clk) - if (pix_reset) - begin - px_vlast <= 0; - px_hlast <= 0; - end else if (px_lost_sync || !M_VID_TVALID || M_VID_TREADY) - begin - if (afifo_read && !afifo_empty) - { px_vlast, px_hlast } - <= { afifo_vlast, afifo_hlast }; - end - // }}} - - // px_data - // {{{ - initial px_data = 0; - always @(posedge pix_clk) - if (pix_reset) - begin - px_data <= 0; - end else if (!M_VID_TVALID || M_VID_TREADY) - begin - if (afifo_read && !afifo_empty && !px_lost_sync) - px_data <= afifo_data; - else if (OPT_MSB_FIRST) - px_data <= { px_data[DW-PW-1:0], {(PW){1'b0}} }; - else - px_data <= { {(PW){1'b0}}, px_data[DW-1:PW] }; - end - // }}} - - // px_lost_sync - // {{{ - initial px_lost_sync = 0; - always @(posedge pix_clk) - if (pix_reset) - px_lost_sync <= 0; - else if (M_VID_TVALID && M_VID_TREADY && M_VID_HLAST) - begin - if (!px_hlast || (M_VID_VLAST && !px_vlast)) - begin -`ifdef VERILATOR - if (!px_lost_sync) - $display("Waterfall-R: Lost sync!"); -`endif - px_lost_sync <= 1'b1; - end else if (px_lost_sync && M_VID_VLAST && px_vlast) - begin -`ifdef VERILATOR - $display("Waterfall-R: Re-sync\'d"); -`endif - px_lost_sync <= 1'b0; - end - end - // }}} - - // M_VID_TVALID, M_VID_TDATA - // {{{ - assign M_VID_TVALID = px_valid; - - if (OPT_MSB_FIRST) - begin : MSB - assign M_VID_TDATA = px_data[DW-PW +: PW]; - end else begin - assign M_VID_TDATA = px_data[0 +: PW]; - end - // }}} - - // m_hpos, m_vpos - // {{{ - initial m_hpos = 0; - initial m_vpos = 0; - initial M_VID_HLAST = 0; - initial M_VID_VLAST = 0; - always @(posedge pix_clk) - if (pix_reset) - begin - m_hpos <= 0; - m_vpos <= 0; - M_VID_HLAST <= 0; - M_VID_VLAST <= 0; - end else if (M_VID_TVALID && M_VID_TREADY) - begin - m_hpos <= m_hpos + 1; - M_VID_HLAST <= (i_mem_words <= 1) || (m_hpos >= i_mem_words-2); - if (M_VID_HLAST) - begin - m_hpos <= 0; - m_vpos <= m_vpos + 1; - M_VID_VLAST <= (i_height <= 1) || (m_vpos == i_height-2); - if (M_VID_VLAST) - m_vpos <= 0; - end - end - // }}} - - // M_VID_TUSER, M_VID_TLAST - // {{{ - if (OPT_TUSER_IS_SOF) - begin : GEN_SOF - reg sof; - - always @(posedge pix_clk) - if (i_reset) - sof <= 1; - else if (M_VID_TVALID && M_VID_TREADY) - begin - sof <= M_VID_VLAST && M_VID_HLAST; - end - - assign M_VID_TLAST = M_VID_HLAST; - assign M_VID_TUSER = sof; - end else begin : NO_SOF - assign M_VID_TLAST = M_VID_HLAST && M_VID_VLAST; - assign M_VID_TUSER = M_VID_HLAST; - end - // }}} - // }}} - end else begin - // {{{ - always @(*) - afifo_read = M_VID_TVALID && M_VID_TREADY; - - initial { m_hpos, m_vpos } = 0; - - assign M_VID_TVALID = !afifo_empty; - assign M_VID_TDATA = afifo_data; - always @(*) - begin - M_VID_HLAST = afifo_hlast; - M_VID_VLAST = afifo_vlast; - end - - if (OPT_TUSER_IS_SOF) - begin : GEN_SOF - reg sof; - - always @(posedge pix_clk) - if (i_reset) - sof <= 1; - else if (M_VID_TVALID && M_VID_TREADY) - begin - sof <= M_VID_VLAST && M_VID_HLAST; - end - - assign M_VID_TLAST = M_VID_HLAST; - assign M_VID_TUSER = sof; - end else begin : NO_SOF - assign M_VID_TLAST = M_VID_HLAST && M_VID_VLAST; - assign M_VID_TUSER = M_VID_HLAST; - - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, pix_clk }; - // Verilator lint_on UNUSED - end - - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, m_vpos, m_hpos }; - // Verilator lint_on UNUSED - // }}} - end endgenerate - // }}} - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, ign_fifo_full }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Local declarations - // {{{ - reg f_past_valid; - localparam F_LGDEPTH = LGBURST+2; - wire [LGFRAME-1:0] f_xpos, f_ypos; - wire f_known_height; - wire f_hlast, f_vlast, f_sof; - wire [LGFRAME-1:0] fwb_xpos, fwb_ypos; - wire fwb_known_height; - wire fwb_hlast, fwb_vlast, fwb_sof; - wire [F_LGDEPTH-1:0] fwb_nreqs, fwb_nacks, fwb_outstanding; - wire [F_LGDEPTH:0] f_committed; - reg [AW-1:0] this_line; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - fwb_master #( - // {{{ - .AW(AW), .DW(DW), .F_LGDEPTH(F_LGDEPTH) - // }}} - ) fwb ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_wb_cyc(o_wb_cyc), .i_wb_stb(o_wb_stb), .i_wb_we(o_wb_we), - .i_wb_addr(o_wb_addr), .i_wb_data(o_wb_data), - .i_wb_sel(o_wb_sel), - .i_wb_stall(i_wb_stall), .i_wb_ack(i_wb_ack), - .i_wb_idata(i_wb_data), .i_wb_err(i_wb_err), - .f_nreqs(fwb_nreqs), .f_nacks(fwb_nacks), - .f_outstanding(fwb_outstanding) - // }}} - ); - - assign f_committed = fifo_fill + fwb_outstanding; - - always @(*) - if (!i_reset && o_wb_cyc) - begin - assert(wb_outstanding == fwb_outstanding); - if (wb_outstanding >= (1<= (1< 2); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Video interface properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (!i_reset) - begin - assume(i_mem_words > 2*(DW/PW)); - assume(i_height > 2); - end - - faxivideo #( - // {{{ - .PW(PW), - .LGDIM(LGFRAME), - .OPT_TUSER_IS_SOF(OPT_TUSER_IS_SOF), - .OPT_SOURCE(1'b0) - // }}} - ) fvid ( - // {{{ - .i_clk(i_clk), .i_reset_n(!i_reset), - .S_VID_TVALID(M_VID_TVALID), .S_VID_TREADY(M_VID_TREADY), - .S_VID_TDATA(M_VID_TDATA), .S_VID_TLAST(M_VID_TLAST), - .S_VID_TUSER(M_VID_TUSER), - .i_width(i_mem_words), .i_height(i_height), - .o_xpos(f_xpos), .o_ypos(f_ypos), - .f_known_height(f_known_height), - .o_hlast(f_hlast), .o_vlast(f_vlast), .o_sof(f_sof) - // }}} - ); - - always @(*) - if (!i_reset) - begin - assert(m_hpos == f_xpos); - assert(m_vpos == f_ypos); - assert(M_VID_VLAST == f_vlast); - assert(M_VID_HLAST == f_hlast); - if (OPT_TUSER_IS_SOF) - assert(M_VID_TUSER == f_sof); - end - - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Mode assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!i_reset) - begin - assume($stable(i_baseaddr)); - assume($stable(i_mem_words)); - - assume(i_baseaddr + { 1'b0, i_mem_words } <= (1<= i_baseaddr); // !!! (Induction) - end - - always @(posedge i_clk) - if (!i_reset) - begin - assert(o_wb_addr >= i_baseaddr); - - if (wb_hlast) - assert(line_addr >= i_baseaddr); - - assert(wb_vlast == (wb_vpos == i_height-1)); - end -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/vidpipe.v b/delete_later/rtl/hdmi/vidpipe.v deleted file mode 100644 index ccf566e..0000000 --- a/delete_later/rtl/hdmi/vidpipe.v +++ /dev/null @@ -1,955 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: vidpipe.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module vidpipe #( - // {{{ - parameter DW = 512, - parameter AW = 31-$clog2(DW/8), - parameter CLOCKFREQ_HZ = 100_000_000, - parameter LGDIM = 12 // Largest raw screen size = 4095x4095 - // }}} - ) ( - // {{{ - input wire i_clk, // System/Bus clock - input wire i_reset, // System Reset - // Wishbone Control ports - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [8:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // - // output wire o_int, - // }}} - // Incoming HDMI Video (if present) - // {{{ - input wire i_hdmiclk, i_siclk, i_pixclk, - input wire [9:0] i_hdmi_red, i_hdmi_grn, i_hdmi_blu, - // }}} - // (Wide) Wishbone DMA master - // {{{ - output wire o_dma_cyc, o_dma_stb, o_dma_we, - output wire [AW-1:0] o_dma_addr, - output wire [DW-1:0] o_dma_data, - output wire [DW/8-1:0] o_dma_sel, - input wire i_dma_stall, - input wire i_dma_ack, - input wire [DW-1:0] i_dma_data, - input wire i_dma_err, - // }}} - // Outgoing HDMI Video - // {{{ - output wire [9:0] o_hdmi_red, o_hdmi_grn, o_hdmi_blu, - // }}} - // Clock control - output reg [1:0] o_pxclk_sel, - output reg [14:0] o_iodelay, - input wire [14:0] i_iodelay - // }}} - ); - - // Local declarations - // {{{ - localparam CWID = $clog2(CLOCKFREQ_HZ); - localparam WBLSB = $clog2(DW/8); - localparam [3:0] ADR_CONTROL = 4'h0, - ADR_SIFREQ = 4'h1, - ADR_PXFREQ = 4'h2, - ADR_HDMIFREQ = 4'h3, - ADR_INSIZE = 4'h4, - ADR_INPORCH = 4'h5, - ADR_INSYNC = 4'h6, - ADR_INRAW = 4'h7, - ADR_SIZE = 4'h8, - ADR_PORCH = 4'h9, - ADR_SYNC = 4'ha, - ADR_RAW = 4'hb, - ADR_OVLYBASE = 4'hc, - ADR_OVLYSIZE = 4'hd, - ADR_OVLYOFFSET= 4'he, - ADR_FPS = 4'hf; - - // Verilator lint_off SYNCASYNCNET - reg pix_reset_sys, pix_reset; - reg [1:0] pix_reset_pipe; - wire pix_reset_n; - // Verilator lint_on SYNCASYNCNET - - // Video streams - // {{{ - wire vga_valid, vga_vsync, vga_hsync; - wire [7:0] vga_red, vga_grn, vga_blu; - - wire rx_valid, rx_ready, rx_hlast, rx_vlast; - wire [23:0] rx_data; - - wire pipe_valid, pipe_ready, pipe_hlast, pipe_vlast; - wire [23:0] pipe_data; - - wire empty_valid, empty_ready, empty_vlast, empty_hlast; - wire [23:0] empty_data; - - wire mem_valid, mem_ready, mem_vlast, mem_hlast; - wire [DW-1:0] mem_data; - - wire wbpx_valid, wbpx_ready, wbpx_vlast, wbpx_hlast; - wire [23:0] wbpx_data; - - wire out_valid, out_ready, out_vlast, out_hlast; - wire [23:0] out_data; - // }}} - - // Configuration registers - // {{{ - wire [1:0] cfg_alpha; - reg [1:0] cfg_alpha_sys; - reg [LGDIM-1:0] cfg_mem_words, - cfg_mem_height;// SYS clk domain - reg [LGDIM-1:0] cfg_mem_width_sys; - reg [AW-1:0] cfg_framebase; - reg cfg_ovly_enable_sys; - - // cfg_framebase // Base address of the frame buffer - // cfg_mem_words // Bus words per line - // cfg_cmap_mode // How are memory data translated to pixels? - // cfg_ovly_enable, - // cfg_ovly_hpos, cfg_ovly_vpos - // ovly_err - // [1:0] cfg_clk_src - // cfg_src_sel - // hm_width, hm_front, hm_synch, hm_raw, - // vm_height, vm_front, vm_synch, vm_raw, - // - // hin_width, hin_porch, hin_synch, hin_raw, - // vin_height, vin_porch, vin_synch, vin_raw, - // in_locked - - reg [2:0] cfg_cmap_mode_sys; - wire [2:0] cfg_cmap_mode; - reg cfg_src_sel_sys; - reg [LGDIM-1:0] vm_raw_sys, hm_raw_sys, - vm_synch_sys, hm_synch_sys, - vm_front_sys, hm_front_sys, - vm_height_sys, hm_width_sys; - wire [LGDIM-1:0] vm_raw, hm_raw, - vm_synch, hm_synch, - vm_front, hm_front, - vm_height, hm_width; - // }}} - - wire [LGDIM-1:0] cfg_mem_width; - wire [LGDIM-1:0] hin_width, hin_front, hin_synch, hin_raw; - wire [LGDIM-1:0] vin_height, vin_front, vin_synch, vin_raw; - wire in_locked; - - reg [8:0] frame_counter; - reg [7:0] frames_per_second; - wire new_frame_sys; - - reg [CWID-1:0] pps_counter; - reg sys_pps; - wire [31:0] pixck_counts, hdmick_counts, sick_counts; - - wire ovly_err, ovly_err_sys, in_locked_sys; - wire [LGDIM-1:0] hin_width_sys, hin_front_sys, - hin_synch_sys, hin_raw_sys; - wire [LGDIM-1:0] vin_height_sys, vin_front_sys, - vin_synch_sys, vin_raw_sys; - wire [LGDIM-1:0] vout_raw, hout_raw, - vout_synch, hout_synch, - vout_front, hout_front, - vout_height, hout_width; - wire cfg_src_sel; - wire cfg_ovly_enable; - wire [LGDIM-1:0] cfg_ovly_vpos, cfg_ovly_hpos; - reg [LGDIM-1:0] cfg_ovly_vpos_sys, cfg_ovly_hpos_sys; - - wire ign_px2sys_valid, ign_px2sys_ready; - wire ign_sys2px_valid, ign_sys2px_ready; - wire ign_frame_ready; - - wire [23:0] cmap_rdata; - - reg pre_ack, cmap_ack; - reg [31:0] pre_wb_data; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // WB Control signaling - // {{{ - // Configurable parameters ... - // cfg_framebase // Base address of the frame buffer - // cfg_mem_words // Bus words per line - // cfg_cmap_mode // How are memory data translated to pixels? - // cfg_ovly_enable, - // cfg_ovly_hpos, cfg_ovly_vpos - // ovly_err - // [1:0] cfg_clk_src -> o_pxclk_sel - // cfg_src_sel - // hm_width, hm_front, hm_synch, hm_raw, - // vm_height, vm_front, vm_synch, vm_raw, - // - // in_locked -// Register controls: -// 0. CONTROL: Pixel clock source, video rx and tx reset -// CMAP mode, HDMI RX locked, Overlay error -// -// FREQUENCY FEEDBACK -// 1. Measured (not commanded) Si5324 frequency -// 2. Measured pixel clock frequency -// 3. HDMIRX pixel clock frequency -// -// FRAME SIZE (4 regs each) -// 4-7: Measured HDMI incoming frame size -// 8-11: Commanded outgoing frame size -// -// 12. Overlay base address -// 13. Overlay size: vertical, width -// 14. Overlay position offset -// 15. Measured incoming frame rate -// - - initial pix_reset_sys = 1'b1; - always @(posedge i_clk) - begin - if (i_wb_stb && i_wb_we && i_wb_addr[8:4]==5'h0) - begin - case(i_wb_addr[3:0]) - ADR_CONTROL: begin - // {{{ - if (i_wb_sel[0]) - begin - cfg_src_sel_sys <= i_wb_data[6] - && i_wb_data[5]; - o_pxclk_sel <= i_wb_data[5:4]; - // tx_reset_sys <= i_wb_data[2]; - // rx_reset_sys <= i_wb_data[1]; - pix_reset_sys <= i_wb_data[0]; - end - if (i_wb_sel[1]) - begin - cfg_cmap_mode_sys <= i_wb_data[10:8]; - cfg_alpha_sys <= i_wb_data[15:14]; - end end - // }}} - // ADR_SIFREQ: begin end - // ADR_PXFREQ: begin end - // ADR_HDMIFREQ: begin end - // ADR_INSIZE: begin end - // ADR_INPORCH: begin end - // ADR_INSYNC: begin end - // ADR_INRAW: begin end - ADR_SIZE: begin - // {{{ - if (&i_wb_sel[1:0]) - hm_width_sys <= i_wb_data[0 +: LGDIM]; - if (&i_wb_sel[3:2]) - vm_height_sys<= i_wb_data[16 +: LGDIM]; - end - // }}} - ADR_PORCH: begin - // {{{ - if (&i_wb_sel[1:0]) - hm_front_sys <= i_wb_data[0 +: LGDIM]; - if (&i_wb_sel[3:2]) - vm_front_sys <= i_wb_data[16 +: LGDIM]; - end - // }}} - ADR_SYNC: begin - // {{{ - if (&i_wb_sel[1:0]) - hm_synch_sys <= i_wb_data[0 +: LGDIM]; - if (&i_wb_sel[3:2]) - vm_synch_sys <=i_wb_data[16 +: LGDIM]; - end - // }}} - ADR_RAW: begin - // {{{ - if (&i_wb_sel[1:0]) - hm_raw_sys <= i_wb_data[0 +: LGDIM]; - if (&i_wb_sel[3:2]) - vm_raw_sys <= i_wb_data[16 +: LGDIM]; - end - // }}} - ADR_OVLYBASE: begin - // {{{ - cfg_ovly_enable_sys <= (&i_wb_sel) - && (i_wb_data[WBLSB +: AW]!=0); - if (&i_wb_sel) - cfg_framebase <= i_wb_data[WBLSB +: AW]; - end - // }}} - ADR_OVLYSIZE: begin - // {{{ - if (&i_wb_sel[1:0]) - // cfg_mem_words <= { {(WBLSB){1'b0}}, i_wb_data[LGDIM-1:WBLSB] }; - cfg_mem_width_sys <= i_wb_data[LGDIM-1:0]; - if (&i_wb_sel[3:2]) - cfg_mem_height <= i_wb_data[16 +: LGDIM]; - end - // }}} - ADR_OVLYOFFSET: begin - // {{{ - if (&i_wb_sel[1:0]) - cfg_ovly_hpos_sys <= i_wb_data[ 0 +: LGDIM]; - if (&i_wb_sel[3:2]) - cfg_ovly_vpos_sys <= i_wb_data[16 +: LGDIM]; - end - // }}} - ADR_FPS: begin - // {{{ - if (i_wb_sel[1]) - o_iodelay[4:0] <= i_wb_data[ 8+:5]; - if (i_wb_sel[2]) - o_iodelay[9:5] <= i_wb_data[16+:5]; - if (i_wb_sel[3]) - o_iodelay[14:10]<=i_wb_data[24+:5]; - end - // }}} - default: begin end - endcase - end - - if (i_reset) - begin - cfg_src_sel_sys <= 1'b0; - o_pxclk_sel <= 2'b00; - cfg_ovly_enable_sys <= 1'b0; - cfg_framebase <= {(AW){1'b0}}; - - pix_reset_sys <= 1'b1; - end - end - - // cfg_mem_words - // {{{ - always @(posedge i_clk) - case(cfg_cmap_mode_sys) - 3'h0: // 1-bit pixels - cfg_mem_words <= (cfg_mem_width_sys + DW -1) / DW; - 3'h1: // 2-bit pixels - cfg_mem_words <= (cfg_mem_width_sys + (DW/2) -1) / (DW/2); - 3'h2: // 4-bit pixels - cfg_mem_words <= (cfg_mem_width_sys + (DW/4) -1) / (DW/4); - 3'h3: // 4-bit pixels - cfg_mem_words <= (cfg_mem_width_sys + (DW/4) -1) / (DW/4); - 3'h4: // 8-bit pixels - cfg_mem_words <= (cfg_mem_width_sys + (DW/8) -1) / (DW/8); - 3'h5: // 8-bit pixels - cfg_mem_words <= (cfg_mem_width_sys + (DW/8) -1) / (DW/8); - 3'h6: // 16-bit pixels - cfg_mem_words <= (cfg_mem_width_sys + (DW/16)-1) / (DW/16); - 3'h7: // 24-bit pixels, using 32b at a tim - cfg_mem_words <= (cfg_mem_width_sys + (DW/32)-1) / (DW/32); - endcase - // }}} - - // cmap_ack - // {{{ - // Reading the color map takes an extra clock cyle - always @(posedge i_clk) - cmap_ack <= !i_wb_we && i_wb_addr[8]; - // }}} - - // o_wb_data, pre_wb_data: Bus reads - // {{{ - always @(posedge i_clk) - if (i_wb_stb && !i_wb_we) - begin - pre_wb_data <= 0; - if (i_wb_data[8:4] == 5'h0) - case(i_wb_addr[3:0]) - ADR_CONTROL: begin - pre_wb_data[10:0] <= { cfg_cmap_mode_sys, - 1'b0, cfg_src_sel_sys, o_pxclk_sel, - 3'h0, pix_reset_sys }; - pre_wb_data[16] <= in_locked_sys; - pre_wb_data[17] <= ovly_err_sys; - end - ADR_SIFREQ: pre_wb_data <= sick_counts; - ADR_HDMIFREQ: pre_wb_data <= hdmick_counts; - ADR_PXFREQ: pre_wb_data <= pixck_counts; - ADR_INSIZE: begin - pre_wb_data[16 +: LGDIM] <= vin_height_sys; - pre_wb_data[ 0 +: LGDIM] <= hin_width_sys; - end - ADR_INPORCH: begin - pre_wb_data[16 +: LGDIM] <= vin_front_sys; - pre_wb_data[ 0 +: LGDIM] <= hin_front_sys; - end - ADR_INSYNC: begin - pre_wb_data[16 +: LGDIM] <= vin_synch_sys; - pre_wb_data[ 0 +: LGDIM] <= hin_synch_sys; - end - ADR_INRAW: begin - pre_wb_data[16 +: LGDIM] <= vin_raw_sys; - pre_wb_data[ 0 +: LGDIM] <= hin_raw_sys; - end - ADR_SIZE: begin - pre_wb_data[16 +: LGDIM] <= vm_height_sys; - pre_wb_data[ 0 +: LGDIM] <= hm_width_sys; - end - ADR_PORCH: begin - pre_wb_data[16 +: LGDIM] <= vm_front_sys; - pre_wb_data[ 0 +: LGDIM] <= hm_front_sys; - end - ADR_SYNC: begin - pre_wb_data[16 +: LGDIM] <= vm_synch_sys; - pre_wb_data[ 0 +: LGDIM] <= hm_synch_sys; - end - ADR_RAW: begin - pre_wb_data[16 +: LGDIM] <= vm_raw_sys; - pre_wb_data[ 0 +: LGDIM] <= hm_raw_sys; - end - ADR_OVLYBASE: begin - if (cfg_ovly_enable_sys) - pre_wb_data[WBLSB +: AW] <= cfg_framebase; - end - ADR_OVLYSIZE: begin - pre_wb_data[16 +: LGDIM] <= cfg_mem_height; - pre_wb_data[ 0 +: LGDIM] <= { - cfg_mem_width_sys[LGDIM-1:0] }; - end - ADR_OVLYOFFSET: begin end - ADR_FPS: begin - pre_wb_data[7:0] <= frames_per_second; - pre_wb_data[ 8 +: 5] <= i_iodelay[ 4: 0]; - pre_wb_data[16 +: 5] <= i_iodelay[ 9: 5]; - pre_wb_data[24 +: 5] <= i_iodelay[14:10]; - end - endcase - end - - always @(posedge i_clk) - if (pre_ack) - begin - if (cmap_ack) - o_wb_data <= { 8'h0, cmap_rdata }; - else - o_wb_data <= pre_wb_data; - end - // }}} - - assign o_wb_stall = 1'b0; - - // o_wb_ack - // {{{ - initial { o_wb_ack, pre_ack } = 2'b00; - always @(posedge i_clk) - if (i_reset || !i_wb_cyc) - { o_wb_ack, pre_ack } <= 2'b0; - else - { o_wb_ack, pre_ack } <= { pre_ack, i_wb_stb && !o_wb_stall }; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Video RESET - // {{{ - // pix_reset_sys <= changed parameters, or changed clock source - - always @(posedge i_pixclk or posedge pix_reset_sys) - if (pix_reset_sys) - { pix_reset, pix_reset_pipe } <= -1; - else - { pix_reset, pix_reset_pipe } <= { pix_reset_pipe, 1'b0 }; - - assign pix_reset_n = !pix_reset; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Convert from HDMI to an AXI (video) stream - // {{{ - - // hdmi2vga: Convert first to VGA - hdmi2vga - u_hdmi2vga ( - // {{{ - .i_clk(i_pixclk), .i_reset(pix_reset), - .i_hdmi_blu(i_hdmi_blu), .i_hdmi_grn(i_hdmi_grn), - .i_hdmi_red(i_hdmi_red), - // - .o_pix_valid(vga_valid), - .o_vsync(vga_vsync), .o_hsync(vga_hsync), - .o_vga_red(vga_red), .o_vga_green(vga_grn), .o_vga_blue(vga_blu) - // }}} - ); - - // sync2stream: VGA to AXI (video) stream - sync2stream #( - .OPT_TUSER_IS_SOF(1'b0), .LGDIM(LGDIM) - ) u_sync2stream ( - // {{{ - .i_clk(i_pixclk), .i_reset(pix_reset), - // The VGA input - // {{{ - .i_pix_valid(vga_valid), - .i_hsync(vga_hsync), - .i_vsync(vga_vsync), - .i_pixel({ vga_red, vga_grn, vga_blu }), - // }}} - // The AXI Video stream output - // {{{ - .M_AXIS_TVALID(rx_valid), .M_AXIS_TREADY(rx_ready), - .M_AXIS_TDATA(rx_data), .M_AXIS_TLAST(rx_vlast), - .M_AXIS_TUSER(rx_hlast), - // }}} - // Video parameters - // {{{ - .o_width(hin_width), .o_hfront(hin_front), - .o_hsync(hin_synch), .o_raw_width(hin_raw), - .o_height(vin_height), .o_vfront(vin_front), - .o_vsync(vin_synch), .o_raw_height(vin_raw), - .o_locked(in_locked) - // }}} - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Move the image meta data to (and from) the bus clock - // {{{ - - tfrvalue #( - .W(LGDIM*8+2) - ) u_px2sys ( - // {{{ - .i_a_clk(i_pixclk), .i_a_reset_n(pix_reset_n), - .i_a_valid(1'b1), .o_a_ready(ign_px2sys_ready), - .i_a_data({ - ovly_err, - in_locked, - vin_raw, hin_raw, - vin_synch, hin_synch, - vin_front, hin_front, - vin_height, hin_width - }), - // - .i_b_clk(i_clk), .i_b_reset_n(!pix_reset_sys), - .o_b_valid(ign_px2sys_valid), .i_b_ready(1'b1), - .o_b_data({ - ovly_err_sys, - in_locked_sys, - vin_raw_sys, hin_raw_sys, - vin_synch_sys, hin_synch_sys, - vin_front_sys, hin_front_sys, - vin_height_sys, hin_width_sys - }) - // }}} - ); - - tfrvalue #( - .W(LGDIM*11+3+4) - ) u_sys2px ( - // {{{ - .i_a_clk(i_clk), .i_a_reset_n(!pix_reset_sys), - .i_a_valid(1'b1), .o_a_ready(ign_sys2px_ready), - .i_a_data({ - cfg_ovly_enable_sys, - cfg_src_sel_sys, - cfg_alpha_sys, - cfg_cmap_mode_sys, - cfg_mem_width_sys, - cfg_ovly_hpos_sys, cfg_ovly_vpos_sys, - vm_raw_sys, hm_raw_sys, - vm_synch_sys, hm_synch_sys, - vm_front_sys, hm_front_sys, - vm_height_sys, hm_width_sys - }), - // - .i_b_clk(i_clk), .i_b_reset_n(!pix_reset_n), - .o_b_valid(ign_sys2px_valid), .i_b_ready(1'b1), - .o_b_data({ - cfg_ovly_enable, - cfg_src_sel, - cfg_alpha, - cfg_cmap_mode, - cfg_mem_width, - cfg_ovly_hpos, cfg_ovly_vpos, - vout_raw, hout_raw, - vout_synch, hout_synch, - vout_front, hout_front, - vout_height, hout_width - }) - // }}} - ); - - assign hm_width = (cfg_src_sel) ? hin_width : hout_width; - assign hm_front = (cfg_src_sel) ? hin_front : hout_front; - assign hm_synch = (cfg_src_sel) ? hin_synch : hout_synch; - assign hm_raw = (cfg_src_sel) ? hin_raw : hout_raw; - assign vm_height = (cfg_src_sel) ? vin_height : vout_height; - assign vm_front = (cfg_src_sel) ? vin_front : vout_front; - assign vm_synch = (cfg_src_sel) ? vin_synch : vout_synch; - assign vm_raw = (cfg_src_sel) ? vin_raw : vout_raw; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Measure the incoming pixel clock frame rate - // {{{ - - // Generate a once per second pulse - - // sys_pps - // {{{ - initial pps_counter = 0; - always @(posedge i_clk) - if (pps_counter >= CLOCKFREQ_HZ-1) - begin - pps_counter <= 0; - sys_pps <= 1; - end else begin - pps_counter <= pps_counter + 1; - sys_pps <= 0; - end - // }}} - - // pixck_counts - // {{{ - clkcounter #( - .CLOCKFREQ_HZ(0) - ) u_pixclk_counter ( - .i_sys_clk(i_clk), .i_tst_clk(i_pixclk), - .i_sys_pps(sys_pps), - .o_sys_counts(pixck_counts) - ); - // }}} - - // hdmick_counts - // {{{ - clkcounter #( - .CLOCKFREQ_HZ(0) - ) u_hdmiclk_counter ( - .i_sys_clk(i_clk), .i_tst_clk(i_hdmiclk), - .i_sys_pps(sys_pps), - .o_sys_counts(hdmick_counts) - ); - // }}} - - // sick_counts - // {{{ - clkcounter #( - .CLOCKFREQ_HZ(0) - ) u_siclk_counter ( - .i_sys_clk(i_clk), .i_tst_clk(i_siclk), - .i_sys_pps(sys_pps), - .o_sys_counts(sick_counts) - ); - // }}} - - // Measure the frame rate - - // Move new frame indicators across clock domains - // {{{ - tfrstb - u_new_frame ( - // {{{ - .i_a_clk(i_pixclk), .i_a_reset_n(pix_reset_n), - .i_a_valid(rx_valid && rx_ready && rx_vlast && rx_hlast), - .o_a_ready(ign_frame_ready), - // - .i_b_clk(i_clk), .i_b_reset_n(!pix_reset_sys), - .o_b_valid(new_frame_sys), .i_b_ready(1'b1) - // }}} - ); - // }}} - - // Frame counter - // {{{ - always @(posedge i_clk) - if (pix_reset_sys) - frame_counter <= 0; - else if (sys_pps) - frame_counter <= (new_frame_sys) ? 1:0; - else if (new_frame_sys && !frame_counter[8]) - frame_counter <= frame_counter + 1; - // }}} - - // frames_per_second <= frame_counter - // {{{ - always @(posedge i_clk) - if (pix_reset_sys) - frames_per_second <= 0; - else if (sys_pps) - begin - frames_per_second <= frame_counter[7:0]; - // UNLESS ... our frame counter overflowed - if (frame_counter[8]) - frames_per_second <= 8'hff; - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Generate an empty frame - // {{{ - localparam [23:0] TRANSPARENT = 24'h0; - - vid_empty #( - .PW(24), .PIXEL(TRANSPARENT), - .OPT_TUSER_IS_SOF(1'b0) - ) u_empty ( - // {{{ - .i_clk(i_pixclk), .i_reset(cfg_src_sel), - .i_width(hm_width), .i_height(vm_height), - // - .M_VID_VALID(empty_valid), - .M_VID_READY(empty_ready), - .M_VID_DATA(empty_data), - .M_VID_LAST(empty_vlast), - .M_VID_USER(empty_hlast) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Mux empty frame with the RX signal - // {{{ - - vid_mux #( - .NIN(2), .LGDIM(LGDIM), .DEF_SELECT(0), - .OPT_TUSER_IS_SOF(0) - ) u_src_mux ( - // {{{ - .S_AXI_ACLK(i_pixclk), .S_AXI_ARESETN(pix_reset_n), - // - .S_VID_VALID({ rx_valid, empty_valid }), - .S_VID_READY({ rx_ready, empty_ready }), - .S_VID_DATA({ rx_data, empty_data }), - .S_VID_LAST({ rx_vlast, empty_vlast }), // VLAST - .S_VID_USER({ rx_hlast, empty_hlast }), // HLAST - // - .M_VID_VALID(pipe_valid), .M_VID_READY(pipe_ready), - .M_VID_DATA(pipe_data), - .M_VID_LAST(pipe_vlast), .M_VID_USER(pipe_hlast), - // - .i_select(cfg_src_sel) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // wbdma: the WishBone Frame buffer - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - - vid_wbframebuf #( - // {{{ - .AW(AW), .DW(DW), .LGFRAME(LGDIM), .PW(DW), - .OPT_TUSER_IS_SOF(1'b0), - .OPT_ASYNC_CLOCKS(1'b1) - // }}} - ) u_framebuf ( - // {{{ - .i_clk(i_clk), .i_pixclk(i_pixclk), .i_reset(pix_reset_sys), - .i_cfg_en(cfg_ovly_enable_sys), - .i_height(cfg_mem_height), .i_mem_words(cfg_mem_words), - .i_baseaddr(cfg_framebase), - // Wishbone (DMA) bus master - // {{{ - .o_wb_cyc(o_dma_cyc), .o_wb_stb(o_dma_stb), - .o_wb_we(o_dma_we), - .o_wb_addr(o_dma_addr), - .o_wb_data(o_dma_data), .o_wb_sel(o_dma_sel), - .i_wb_stall(i_dma_stall), .i_wb_ack(i_dma_ack), - .i_wb_data(i_dma_data), .i_wb_err(i_dma_err), - // }}} - // Outgoing video stream - // {{{ - .M_VID_TVALID(mem_valid), - .M_VID_TREADY(mem_ready), - .M_VID_TDATA( mem_data), - .M_VID_TLAST( mem_vlast), - .M_VID_TUSER( mem_hlast) - // }}} - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // wbpix_: VidStream2Pix (for frame buffer input) - // {{{ - - vidstream2pix #( - // {{{ - .BUS_DATA_WIDTH(DW), - .HMODE_WIDTH(LGDIM), - .OPT_MSB_FIRST(1'b1), - .OPT_TUSER_IS_SOF(1'b0) - // }}} - ) u_mem2pix ( - // {{{ - .i_clk(i_pixclk), .i_reset(pix_reset), - // Incoming video data, w/ bus-sized pixels - // {{{ - .S_AXIS_TVALID(mem_valid), - .S_AXIS_TREADY(mem_ready), - .S_AXIS_TDATA(mem_data), - .S_AXIS_TLAST(mem_vlast), - .S_AXIS_TUSER(mem_hlast), - // }}} - // Outgoing video pixel data - // {{{ - .M_AXIS_TVALID(wbpx_valid), - .M_AXIS_TREADY(wbpx_ready), - .M_AXIS_TDATA(wbpx_data), - .M_AXIS_TLAST(wbpx_vlast), - .M_AXIS_TUSER(wbpx_hlast), - // }}} - .i_mode(cfg_cmap_mode), .i_pixels_per_line(cfg_mem_width), - // Colormap control - // {{{ - .i_cmap_clk(i_clk), - .i_cmap_rd(i_wb_stb && !i_wb_we && i_wb_addr[8]), - .i_cmap_raddr(i_wb_addr[7:0]), - .o_cmap_rdata(cmap_rdata[23:0]), - .i_cmap_we(i_wb_stb && i_wb_we && i_wb_addr[8]), - .i_cmap_waddr(i_wb_addr[7:0]), - .i_cmap_wdata(i_wb_data[23:0]), - .i_cmap_wstrb(i_wb_sel[2:0]) - // }}} - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Transparency - // {{{ - - // If the color == TRANSPARENT, alpha should be set to all 1'b1s, - // cfg_alpha otherwise. - - wire alph_valid, alph_ready, - alph_hlast, alph_vlast; - wire [26-1:0] alph_pixel; - - skidbuffer #( - .OPT_LOWPOWER(1'b0), .OPT_OUTREG(1'b1), - .DW(28) - ) alpha_skid ( - .i_clk(i_pixclk), .i_reset(pix_reset), - .i_valid(wbpx_valid), .o_ready(wbpx_ready), - .i_data({ wbpx_vlast, wbpx_hlast, - (wbpx_data == TRANSPARENT)? 2'b11 : cfg_alpha, - wbpx_data }), - .o_valid(alph_valid), .i_ready(alph_ready), - .o_data({ alph_vlast, alph_hlast, alph_pixel }) - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // out_*: Overlay WB Frame buffer onto the (empty or RX) stream - // {{{ - - - axisvoverlay #( - // {{{ - .LGFRAME(LGDIM), .ALPHA_BITS(2), - .OPT_TUSER_IS_SOF(1'b0), - .OPT_LINE_BREAK(1'b1) - // .TRANSPARENT(0) // Alpha == 0 is fully transparent - // }}} - ) u_overlay ( - // {{{ - .ACLK(i_pixclk), .ARESETN(pix_reset_n), - .i_enable(cfg_ovly_enable), - .i_hpos(cfg_ovly_hpos), .i_vpos(cfg_ovly_vpos), - .o_err(ovly_err), - .S_PRI_TVALID(pipe_valid), .S_PRI_TREADY(pipe_ready), - .S_PRI_TDATA(pipe_data), - .S_PRI_TLAST(pipe_vlast), .S_PRI_TUSER(pipe_hlast), - // - .S_OVW_TVALID(alph_valid), .S_OVW_TREADY(alph_ready), - .S_OVW_TDATA(alph_pixel), - .S_OVW_TLAST(alph_vlast), .S_OVW_TUSER(alph_hlast), - // - .M_VID_TVALID(out_valid), .M_VID_TREADY(out_ready), - .M_VID_TDATA(out_data), - .M_VID_TLAST(out_vlast), .M_VID_TUSER(out_hlast) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // axis2hdmi: Convert our AXI Video stream to HDMI - // {{{ - - axishdmi #( - .HW(LGDIM), .VW(LGDIM), - .OPT_RESYNC_ON_VLAST(1'b1) - ) genhdmi ( - // {{{ - .i_pixclk(i_pixclk), .i_reset(pix_reset), - // Incoming AXI video stream - // {{{ - .i_valid(out_valid), .o_ready(out_ready), - .i_hlast(out_hlast), .i_vlast(out_vlast), .i_rgb_pix(out_data), - // }}} - // Video mode information - // {{{ - .i_hm_width(hm_width), .i_hm_porch(hm_front), - .i_hm_synch(hm_synch), .i_hm_raw(hm_raw), - // - .i_vm_height(vm_height), .i_vm_porch(vm_front), - .i_vm_synch(vm_synch), .i_vm_raw(vm_raw), - // }}} - // HDMI outputs - .o_red(o_hdmi_red), .o_grn(o_hdmi_grn), .o_blu(o_hdmi_blu) - // }}} - ); - - // }}} - - // Keep Verilator happy - // {{{ - wire unused; - assign unused = &{ 1'b0, ign_px2sys_valid, ign_px2sys_ready, - ign_sys2px_valid, ign_sys2px_ready, ign_frame_ready, - i_wb_data }; - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/vidstream2pix.v b/delete_later/rtl/hdmi/vidstream2pix.v deleted file mode 100644 index b653c9c..0000000 --- a/delete_later/rtl/hdmi/vidstream2pix.v +++ /dev/null @@ -1,1062 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: vidstream2pix.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Converts an AXI-Stream of video data, packed into bus/memory -// words, into a second AXI-stream of 24-bit pixels only. -// -// Several color encodings are available: -// 3'b000: Black and white. -// 3'b001: 2-bit gray scale -// 3'b010: 4-bit gray scale -// 3'b011: 4-bit colormap, using the first 16-entries of the color mapping -// table -// 3'b100: 8-bit colormap -// 3'b101: 8-bit color, no color map, encoded as 3-bits of red, 3-bits of -// green, and 2-bits of blue -// 3'b110: 16-bit color, encoded as 5-bits red, 6-bits green and 5-bits blu -// 3'b111: 24-bit color. The upper 8-bits of every 32-bits are ignored -// in this encoding. (They are packed in other encodings) -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module vidstream2pix #( - // {{{ - parameter HMODE_WIDTH = 12, - parameter [0:0] OPT_MSB_FIRST = 1'b0, - parameter BUS_DATA_WIDTH = 32, - parameter [0:0] OPT_TUSER_IS_SOF = 1'b0 - // }}} - ) ( - // {{{ - input wire i_clk, - input wire i_reset, - // Incoming video data from the memory bus - // {{{ - input wire S_AXIS_TVALID, - output wire S_AXIS_TREADY, - input wire [BUS_DATA_WIDTH-1:0] S_AXIS_TDATA, - input wire S_AXIS_TLAST, - input wire S_AXIS_TUSER, - // }}} - // Outgoing video pixel data - // {{{ - output wire M_AXIS_TVALID, - input wire M_AXIS_TREADY, - output wire [23:0] M_AXIS_TDATA, // Color - output reg M_AXIS_TLAST, - output reg M_AXIS_TUSER, - // }}} - // Control information - // {{{ - input wire [2:0] i_mode, - input wire [HMODE_WIDTH-1:0] i_pixels_per_line, - // }}} - // Colormap control - // {{{ - input wire i_cmap_clk, - input wire i_cmap_rd, - input wire [7:0] i_cmap_raddr, - output reg [23:0] o_cmap_rdata, - input wire i_cmap_we, - input wire [7:0] i_cmap_waddr, - input wire [23:0] i_cmap_wdata, - input wire [2:0] i_cmap_wstrb - // }}} - // }}} - ); - - // Register/net/localparam declarations - // {{{ - localparam [2:0] MODE_BW = 3'b000, - MODE_GRAY2 = 3'b001, - MODE_GRAY4 = 3'b010, - MODE_CMAP4 = 3'b011, - MODE_CMAP8 = 3'b100, - MODE_CLR8 = 3'b101, - MODE_CLR16 = 3'b110, - MODE_DIRECT = 3'b111; - // Steps: - // t_ incoming data - // s_ Shift register - // c_ Colors - // m_ Outgoing data - localparam BASE_1 = (OPT_MSB_FIRST) ? (BUS_DATA_WIDTH- 1) : 0; - localparam BASE_2 = (OPT_MSB_FIRST) ? (BUS_DATA_WIDTH- 2) : 0; - localparam BASE_4 = (OPT_MSB_FIRST) ? (BUS_DATA_WIDTH- 4) : 0; - localparam BASE_8 = (OPT_MSB_FIRST) ? (BUS_DATA_WIDTH- 8) : 0; - localparam BASE16 = (OPT_MSB_FIRST) ? (BUS_DATA_WIDTH-16) : 0; - localparam BASE32 = (OPT_MSB_FIRST) ? (BUS_DATA_WIDTH-32) : 0; - - reg [23:0] cmap [0:255]; - - reg S_AXIS_HLAST, S_AXIS_FRAME; - - wire skd_valid, skd_hlast, skd_frame; - wire [BUS_DATA_WIDTH-1:0] skd_data; - reg [HMODE_WIDTH-1:0] s_remaining; - - reg s_valid, skd_ready, s_frame, s_hlast, - s_last_in_word, s_last_word_in_packet; - reg [$clog2(BUS_DATA_WIDTH)-1:0] scount; - reg [BUS_DATA_WIDTH-1:0] sreg; - wire s_step; - - reg c_hlast, c_valid, c_frame; - reg [23:0] bw_pix, gray_2, gray_4, cmap_4, cmap_8, clr_8, clr_16, - direct_clr; - wire c_step; - - reg [23:0] pix_data; - reg [HMODE_WIDTH-1:0] pix_count; - reg pix_frame, pix_hlast, pix_valid; - - // integer k; - - generate if (OPT_TUSER_IS_SOF) - begin - always @(*) - S_AXIS_HLAST = S_AXIS_TLAST; - always @(*) - S_AXIS_FRAME = S_AXIS_TUSER; - end else begin - always @(*) - S_AXIS_HLAST = S_AXIS_TUSER; - always @(*) - S_AXIS_FRAME = S_AXIS_TLAST; - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Colormap memory access (control interface) - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // o_cmap_rdata, reading from the colormap - // {{{ - always @(posedge i_cmap_clk) - if (i_cmap_rd) - o_cmap_rdata <= cmap[i_cmap_raddr]; - // }}} - - // Writes to the color map - // {{{ - always @(posedge i_cmap_clk) - if (i_cmap_we) - begin - if (i_cmap_wstrb[0]) - cmap[i_cmap_waddr][ 7: 0] <= i_cmap_wdata[ 7: 0]; - if (i_cmap_wstrb[1]) - cmap[i_cmap_waddr][15: 8] <= i_cmap_wdata[15: 8]; - if (i_cmap_wstrb[2]) - cmap[i_cmap_waddr][23:16] <= i_cmap_wdata[23:16]; - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Incoming skid buffer - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - skidbuffer #( - // {{{ - .OPT_OUTREG(1), - .DW(BUS_DATA_WIDTH+2) -`ifdef FORMAL - , .OPT_PASSTHROUGH(1'b1) -`endif - // }}} - ) tskd ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - .i_valid(S_AXIS_TVALID), .o_ready(S_AXIS_TREADY), - .i_data({ S_AXIS_TDATA, S_AXIS_FRAME, S_AXIS_HLAST }), - .o_valid(skd_valid), .i_ready(skd_ready), - .o_data({ skd_data, skd_frame, skd_hlast }) - // }}} - ); - - always @(*) - skd_ready = !s_valid || (s_step && s_last_in_word); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Shift register stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // sreg, s_valid, s_frame, scount, s_hlast, s_last_in_word, - // s_last_word_in_packet - // {{{ - initial s_valid = 0; - initial scount = 0; - initial s_hlast = 0; - always @(posedge i_clk) - begin - if (skd_ready) - begin - // Accept a new bus word to be processed - // {{{ - sreg <= skd_data; - s_valid <= skd_valid; - s_frame <= skd_frame && skd_valid; - - if (!skd_hlast) case(i_mode) - // Verilator lint_off WIDTH - MODE_BW: scount <= BUS_DATA_WIDTH - 1'b1; - MODE_GRAY2: scount <= BUS_DATA_WIDTH/2 - 1'b1; - MODE_GRAY4: scount <= BUS_DATA_WIDTH/4 - 1'b1; - MODE_CMAP4: scount <= BUS_DATA_WIDTH/4 - 1'b1; - MODE_CMAP8: scount <= BUS_DATA_WIDTH/8 - 1'b1; - MODE_CLR8: scount <= BUS_DATA_WIDTH/8 - 1'b1; - MODE_CLR16: scount <= BUS_DATA_WIDTH/16 - 1'b1; - MODE_DIRECT: scount <= BUS_DATA_WIDTH/32 - 1'b1; - endcase else - scount <= s_remaining - 1'b1; - // Verilator lint_on WIDTH - if (!skd_valid) - scount <= 0; - - s_last_word_in_packet <= (skd_valid) ? skd_hlast : 0; - if (!skd_valid) - begin - s_last_in_word <= 0; - s_hlast <= 0; - end else if (i_mode == MODE_DIRECT && BUS_DATA_WIDTH == 32) - begin - s_last_in_word <= 1; - s_hlast <= skd_hlast; - end else if (!skd_hlast) - begin - s_last_in_word <= 1'b0; - s_hlast <= 1'b0; - end else begin // if valid && read && hlast && ... - s_last_in_word <= (s_remaining == 1); - s_hlast <= (s_remaining == 1); - end - // }}} - end else if (s_valid && s_step) - begin - // Process the next pixel of the bus word - // {{{ - - // sreg - // {{{ - if (OPT_MSB_FIRST) - case(i_mode) - MODE_BW: sreg <= sreg << 1; - MODE_GRAY2: sreg <= sreg << 2; - MODE_GRAY4: sreg <= sreg << 4; - MODE_CMAP4: sreg <= sreg << 4; - MODE_CMAP8: sreg <= sreg << 8; - MODE_CLR8: sreg <= sreg << 8; - MODE_CLR16: sreg <= sreg << 16; - MODE_DIRECT: begin end - endcase else case(i_mode) - MODE_BW: sreg <= sreg >> 1; - MODE_GRAY2: sreg <= sreg >> 2; - MODE_GRAY4: sreg <= sreg >> 4; - MODE_CMAP4: sreg <= sreg >> 4; - MODE_CMAP8: sreg <= sreg >> 8; - MODE_CLR8: sreg <= sreg >> 8; - MODE_CLR16: sreg <= sreg >> 16; - MODE_DIRECT: sreg <= sreg >> 32; - endcase - // }}} - - if (scount == 0) - s_valid <= 0; - if (scount <= 1) - s_last_in_word <= 1; - if (scount <= 1) - s_hlast <= s_last_word_in_packet; - if (scount > 0) - scount <= scount - 1; - - if (OPT_TUSER_IS_SOF) - s_frame <= 0; - // }}} - end - - // Reset any values on i_reset - // {{{ - if (i_reset) - begin - s_valid <= 0; - s_last_in_word <= 1; - s_last_word_in_packet <= 0; - s_hlast <= 0; - scount <= 0; - end - // }}} - end - // }}} - - // s_remaining - // {{{ - always @(posedge i_clk) - if (i_reset) - s_remaining <= i_pixels_per_line; - else if (skd_valid && skd_ready) - begin - if (skd_hlast) - s_remaining <= i_pixels_per_line; - else case(i_mode) - // Verilator lint_off WIDTH - MODE_BW: s_remaining <= s_remaining - BUS_DATA_WIDTH; - MODE_GRAY2: s_remaining <= s_remaining - BUS_DATA_WIDTH/2; - MODE_GRAY4: s_remaining <= s_remaining - BUS_DATA_WIDTH/4; - MODE_CMAP4: s_remaining <= s_remaining - BUS_DATA_WIDTH/4; - MODE_CMAP8: s_remaining <= s_remaining - BUS_DATA_WIDTH/8; - MODE_CLR8: s_remaining <= s_remaining - BUS_DATA_WIDTH/8; - MODE_CLR16: s_remaining <= s_remaining - BUS_DATA_WIDTH/16; - MODE_DIRECT: s_remaining <= s_remaining - BUS_DATA_WIDTH/32; - // Verilator lint_on WIDTH - endcase - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The color stage selects from among the various color mappings - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // c_hlast, c_valid, c_frame - // {{{ - initial c_hlast = 1; - initial c_frame = (OPT_TUSER_IS_SOF); - initial c_valid = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - c_hlast <= 1; - c_valid <= 0; - c_frame <= (OPT_TUSER_IS_SOF); - end else if (s_step) - begin - c_hlast <= s_hlast; - c_valid <= s_valid; - if (OPT_TUSER_IS_SOF) - c_frame <= s_frame; - else - c_frame <= s_frame && s_hlast; - end - // }}} - - // bw_pix, gray_2 - // {{{ - always @(posedge i_clk) - if (s_step) - bw_pix <= sreg[BASE_1] ? 24'hFFFFFF : 24'h000000; - // }}} - - // gray_2 - // {{{ - always @(posedge i_clk) - if (s_step) - case(sreg[BASE_2 +: 2]) - 2'b00: gray_2 <= 24'h000000; - 2'b01: gray_2 <= 24'h555555; - 2'b10: gray_2 <= 24'haaaaaa; - 2'b11: gray_2 <= 24'hFFFFFF; - endcase - // }}} - - // gray_4 - // {{{ - always @(posedge i_clk) - if (s_step) - gray_4 <= {(6){sreg[BASE_4 +: 4]}}; - // }}} - - // cmap_4 - // {{{ - always @(posedge i_clk) - if (s_step) - cmap_4 <= cmap[{ 4'h0, sreg[BASE_4 +: 4] }]; - // }}} - - // cmap_8 - // {{{ - always @(posedge i_clk) - if (s_step) - cmap_8 <= cmap[sreg[BASE_8 +: 8]]; - // }}} - - // clr_8 - // {{{ - always @(posedge i_clk) - if (s_step) - begin // RRR.GGG.BB, 3R, 3G, 2B - clr_8[23:16] <= {{(2){ sreg[BASE_8+5 +:3]}},sreg[BASE_8+6 +:2]}; - clr_8[15: 8] <= {{(2){ sreg[BASE_8+2 +:3]}},sreg[BASE_8+3 +:2]}; - clr_8[ 7: 0] <= {(4){sreg[BASE_8 +: 2]} }; - end - // }}} - - // clr_16 - // {{{ - always @(posedge i_clk) - if (s_step) - begin // RRRRR.GGGGGG.BBBBB, 5R, 6G, 5B - clr_16[23:16] <= { sreg[BASE16+11 +: 5], sreg[BASE16+13 +: 3] }; - clr_16[15: 8] <= { sreg[BASE16+ 5 +: 6], sreg[BASE16+ 9 +: 2] }; - clr_16[ 7: 0] <= { sreg[BASE16 +: 5], sreg[BASE16+ 2 +: 3] }; - end - // }}} - - // direct_clr - // {{{ - always @(posedge i_clk) - if (s_step) - direct_clr <= sreg[BASE32 +: 24]; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Selection from among the various color maps - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // pix_data - // {{{ - always @(posedge i_clk) - if (c_step) - case(i_mode) - MODE_BW: pix_data <= bw_pix; - MODE_GRAY2: pix_data <= gray_2; - MODE_GRAY4: pix_data <= gray_4; - MODE_CMAP4: pix_data <= cmap_4; - MODE_CMAP8: pix_data <= cmap_8; - MODE_CLR8: pix_data <= clr_8; - MODE_CLR16: pix_data <= clr_16; - MODE_DIRECT: pix_data <= direct_clr; - endcase - // }}} - - // pix_valid, pix_frame - // {{{ - initial pix_valid = 1'b0; - initial pix_frame = OPT_TUSER_IS_SOF; - always @(posedge i_clk) - if (i_reset) - { pix_valid, pix_frame } <= { 1'b0, OPT_TUSER_IS_SOF }; - else if (!M_AXIS_TVALID || M_AXIS_TREADY) - begin - pix_valid <= c_valid; - pix_frame <= c_frame; - end - // }}} - - // pix_hlast, pix_count - // {{{ - initial pix_hlast = 1; - initial pix_count = 0; - always @(posedge i_clk) - if (i_reset) - begin - pix_hlast <= 1; - pix_count <= 0; - end else if ((!M_AXIS_TVALID || M_AXIS_TREADY) && c_valid) - begin - if (!c_hlast) - begin - pix_hlast <= 0; - pix_count <= pix_count - 1; - end else // if (!M_AXIS_TLAST) - begin - pix_hlast <= 1; - pix_count <= i_pixels_per_line - 1; - end - end - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Pipeline control, and final output settings - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign s_step = !c_valid || c_step; - assign c_step = (!M_AXIS_TVALID || M_AXIS_TREADY); - assign M_AXIS_TVALID = pix_valid; - assign M_AXIS_TDATA = pix_data; - - generate if (OPT_TUSER_IS_SOF) - begin - always @(*) - begin - M_AXIS_TLAST = pix_hlast; // HLAST - M_AXIS_TUSER = pix_frame; // SOF - end - end else begin - always @(*) - begin - M_AXIS_TLAST = pix_frame; // VLAST - M_AXIS_TUSER = pix_hlast; // HLAST - end - end endgenerate - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Register/net declarations necessary for formal - // {{{ - (* anyconst *) reg [15:0] f_lines_per_frame; - reg [HMODE_WIDTH-1:0] f_pixel_x, f_bus_x, f_s_x, f_c_x, - f_bus_words_per_line; - reg [15:0] f_bus_y, f_s_y, f_c_y; - reg [15:0] f_pixel_y; - reg f_past_valid; - reg M_AXIS_FRAME, M_AXIS_HLAST; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - M_AXIS_HLAST = pix_hlast; - - always @(*) - if (OPT_TUSER_IS_SOF) - M_AXIS_FRAME = M_AXIS_TUSER; - else - M_AXIS_FRAME = M_AXIS_TLAST; - - always @(*) - if (!f_past_valid) - assume(i_reset); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus (input) framing assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - case(i_mode) - MODE_BW: f_bus_words_per_line = (i_pixels_per_line + (BUS_DATA_WIDTH-1)) / BUS_DATA_WIDTH; - MODE_GRAY2: f_bus_words_per_line = (i_pixels_per_line + (BUS_DATA_WIDTH/2-1)) / (BUS_DATA_WIDTH/2); - MODE_GRAY4: f_bus_words_per_line = (i_pixels_per_line + (BUS_DATA_WIDTH/4-1)) / (BUS_DATA_WIDTH/4); - MODE_CMAP4: f_bus_words_per_line = (i_pixels_per_line + (BUS_DATA_WIDTH/4-1)) / (BUS_DATA_WIDTH/4); - MODE_CMAP8: f_bus_words_per_line = (i_pixels_per_line + (BUS_DATA_WIDTH/8-1)) / (BUS_DATA_WIDTH/8); - MODE_CLR8: f_bus_words_per_line = (i_pixels_per_line + (BUS_DATA_WIDTH/8-1)) / (BUS_DATA_WIDTH/8); - MODE_CLR16: f_bus_words_per_line = (i_pixels_per_line + (BUS_DATA_WIDTH/16-1)) / (BUS_DATA_WIDTH/16); - MODE_DIRECT: f_bus_words_per_line = (i_pixels_per_line + (BUS_DATA_WIDTH/32-1)) /(BUS_DATA_WIDTH/32); - endcase - - initial f_bus_x = 0; - initial f_bus_y = 0; - always @(posedge i_clk) - if (i_reset) - begin - f_bus_x <= 0; - f_bus_y <= 0; - end else if (S_AXIS_TVALID && S_AXIS_TREADY) - begin - f_bus_x <= f_bus_x + 1; - if (S_AXIS_HLAST) - begin - f_bus_x <= 0; - f_bus_y <= f_bus_y + 1; - if (f_bus_y + 1 == f_lines_per_frame) - f_bus_y <= 0; - end - end - - always @(*) - if (!i_reset && S_AXIS_TVALID) - begin - assume(S_AXIS_HLAST ==(f_bus_x == (f_bus_words_per_line - 1))); - if (OPT_TUSER_IS_SOF) - begin - assume(S_AXIS_FRAME == ((f_bus_x== 0)&&(f_bus_y == 0))); - end else - assume(S_AXIS_FRAME == (S_AXIS_HLAST - && (f_bus_y == f_lines_per_frame-1))); - end - // }}} - - always @(posedge i_clk) - if (!i_reset) - assert(f_bus_x < f_bus_words_per_line); - - always @(posedge i_clk) - if (!i_reset) - assert(f_bus_y < f_lines_per_frame); - - always @(*) - if (!f_past_valid) - assume(!S_AXIS_TVALID); - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && S_AXIS_TVALID && !S_AXIS_TREADY)) - begin - assume(S_AXIS_TVALID); - assume($stable(S_AXIS_TDATA)); - assume($stable(S_AXIS_TUSER)); - assume($stable(S_AXIS_TLAST)); - end - - //////////////////////////////////////////////////////////////////////// - // - // Pixel (output) framing assertions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - // Make sure N pixels per line turns into ... N pixels per line - // SOF is the first pixel of any group - - // Count pixels, f_pixel_* - // {{{ - initial f_pixel_x = 0; - initial f_pixel_y = 0; - always @(posedge i_clk) - if (i_reset) - begin - f_pixel_x <= 0; - f_pixel_y <= 0; - end else if (M_AXIS_TVALID && M_AXIS_TREADY) - begin - f_pixel_x <= f_pixel_x + 1; - if (M_AXIS_HLAST) - begin - f_pixel_x <= 0; - f_pixel_y <= f_pixel_y + 1; - if (f_pixel_y + 1 >= f_lines_per_frame) - f_pixel_y <= 0; - end - end - // }}} - - always @(posedge i_clk) - if (!i_reset) - assert(f_pixel_x < i_pixels_per_line); - - always @(posedge i_clk) - if (!i_reset && M_AXIS_TVALID) - begin - assert(M_AXIS_HLAST == (f_pixel_x+1 == i_pixels_per_line)); - if (!OPT_TUSER_IS_SOF) - begin - if (!M_AXIS_HLAST) - begin - assert(!M_AXIS_FRAME); - end - assert(f_pixel_y < f_lines_per_frame); - if (M_AXIS_FRAME) - begin - assert(f_pixel_y + 1 == f_lines_per_frame); - end else - assert(f_pixel_y <= f_lines_per_frame - 1); - end else begin - assert(f_pixel_y <= f_lines_per_frame); - assert(M_AXIS_FRAME == ((f_pixel_y == 0)&&(f_pixel_x == 0))); - end - - assert(M_AXIS_HLAST == (f_pixel_x+1 == i_pixels_per_line)); - end - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && M_AXIS_TVALID && !M_AXIS_TREADY)) - begin - assert(M_AXIS_TVALID); - assert($stable(M_AXIS_TDATA)); - assert($stable(M_AXIS_TUSER)); - assert($stable(M_AXIS_TLAST)); - end - - // always @(posedge i_clk) - // if (!i_reset && M_AXIS_TVALID &&) - // assert(f_pixel_x == i_pixels_per_line); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // s_* - // {{{ - - // s_remaining -- tied to f_bus_x and i_pixels_per_line - // {{{ - always @(posedge i_clk) - if (!i_reset) case(i_mode) - MODE_BW: assert(s_remaining + (f_bus_x * BUS_DATA_WIDTH) == i_pixels_per_line); - MODE_GRAY2: assert(s_remaining + (f_bus_x * BUS_DATA_WIDTH/2) == i_pixels_per_line); - MODE_GRAY4: assert(s_remaining + (f_bus_x * BUS_DATA_WIDTH/4) == i_pixels_per_line); - MODE_CMAP4: assert(s_remaining + (f_bus_x * BUS_DATA_WIDTH/4) == i_pixels_per_line); - MODE_CMAP8: assert(s_remaining + (f_bus_x * BUS_DATA_WIDTH/8) == i_pixels_per_line); - MODE_CLR8: assert(s_remaining + (f_bus_x * BUS_DATA_WIDTH/8) == i_pixels_per_line); - MODE_CLR16: assert(s_remaining + (f_bus_x * BUS_DATA_WIDTH/16) == i_pixels_per_line); - MODE_DIRECT: assert(s_remaining + (f_bus_x * BUS_DATA_WIDTH/32) == i_pixels_per_line); - endcase - // }}} - - // f_s_* - // {{{ - initial f_s_x = 0; - initial f_s_y = 0; - always @(posedge i_clk) - if (i_reset) - begin - f_s_x <= 0; - f_s_y <= 0; - end else if (s_valid && s_step) - begin - f_s_x <= f_s_x + 1; - if (s_hlast) - begin - f_s_x <= 0; - f_s_y <= f_s_y + 1; - if (f_s_y + 1 >= f_lines_per_frame) - f_s_y <= 0; - end - end - // }}} - - // s_hlast - // {{{ - always @(posedge i_clk) - if (!i_reset && s_valid) - assert(s_hlast == (f_s_x + 1 == i_pixels_per_line)); - // }}} - - // scount - // {{{ - always @(*) - if (scount > 0) - assert(s_valid); - - always @(posedge i_clk) - if (!i_reset) case(i_mode) - MODE_BW: assert(scount < BUS_DATA_WIDTH); - MODE_GRAY2: assert(scount < BUS_DATA_WIDTH/2); - MODE_GRAY4: assert(scount < BUS_DATA_WIDTH/4); - MODE_CMAP4: assert(scount < BUS_DATA_WIDTH/4); - MODE_CMAP8: assert(scount < BUS_DATA_WIDTH/8); - MODE_CLR8: assert(scount < BUS_DATA_WIDTH/8); - MODE_CLR16: assert(scount < BUS_DATA_WIDTH/16); - MODE_DIRECT: assert(scount < BUS_DATA_WIDTH/32); - endcase - // }}} - - // s_last_in_word - // {{{ - always @(posedge i_clk) - if (!i_reset && s_valid) - assert(s_last_in_word == (scount == 0)); - // }}} - - // s_last_word_in_packet - // {{{ - always @(posedge i_clk) - if (!i_reset && s_valid) - assert(s_last_word_in_packet == (f_bus_x == 0)); - // }}} - - // assert(f_s_x == - // {{{ - always @(posedge i_clk) - if (!i_reset) - begin - if (c_valid && !c_hlast) - begin - assert(f_s_x == f_c_x + 1); - end else if (c_valid && c_hlast) - begin - assert(f_s_x == 0); - end else - assert(f_s_x == f_c_x); - end - - always @(posedge i_clk) - if (!i_reset) - begin - if (f_bus_x != 0 || !s_valid) - begin - assert(f_s_y == f_bus_y); - end else if (f_bus_y == 0) - begin - assert(f_s_x == 0 || f_s_x + scount == i_pixels_per_line-1); - assert(f_s_y == 0 || f_s_y == f_lines_per_frame-1); - if (f_s_x > 0) - assert(f_s_y != 0); - end else begin - assert(f_s_x + scount + (s_valid ? 1:0) == i_pixels_per_line); - assert(f_s_y == f_bus_y-(s_valid ? 1:0)); - end - - // Relate f_s_x, scount, s_valid, and f_bus_x - // {{{ - if (f_bus_x != 0) - case(i_mode) - MODE_BW: assert(f_s_x + scount + (s_valid ? 1:0) == (f_bus_x * BUS_DATA_WIDTH)); - MODE_GRAY2: assert(f_s_x + scount + (s_valid ? 1:0) == (f_bus_x * BUS_DATA_WIDTH/2)); - MODE_GRAY4: assert(f_s_x + scount + (s_valid ? 1:0) == (f_bus_x * BUS_DATA_WIDTH/4)); - MODE_CMAP4: assert(f_s_x + scount + (s_valid ? 1:0) == (f_bus_x * BUS_DATA_WIDTH/4)); - MODE_CMAP8: assert(f_s_x + scount + (s_valid ? 1:0) == (f_bus_x * BUS_DATA_WIDTH/8)); - MODE_CLR8: assert(f_s_x + scount + (s_valid ? 1:0) == (f_bus_x * BUS_DATA_WIDTH/8)); - MODE_CLR16: assert(f_s_x + scount + (s_valid ? 1:0) == (f_bus_x * BUS_DATA_WIDTH/16)); - MODE_DIRECT: assert(f_s_x + scount + (s_valid ? 1:0) == (f_bus_x * BUS_DATA_WIDTH/32)); - endcase - // }}} - else if (f_s_x != 0) - begin - assert(f_s_x + scount + (s_valid ? 1:0) == i_pixels_per_line); - end else - assert(!s_valid); - end - // }}} - - // assert(f_s_y == - // {{{ - always @(*) - assert(f_s_y < f_lines_per_frame); - - always @(posedge i_clk) - if (!i_reset) - begin - if (c_valid && c_hlast) - begin - if (f_c_y >= f_lines_per_frame - 1) - begin - assert(f_s_y == 0); - end else - assert(f_s_y == f_c_y + 1); - end else - assert(f_s_y == f_c_y); - end - - always @(posedge i_clk) - if (!i_reset) - begin - if (!s_valid) - begin - assert(f_s_y == f_bus_y); - end else if (!s_last_word_in_packet) - begin - assert(f_s_y == f_bus_y); - end else if (f_bus_y > 0) - begin - assert(f_s_y == f_bus_y - 1); - end else - assert(f_s_y == 0 || f_s_y == f_lines_per_frame-1); - end - // }}} - - // assert(s_frame - // {{{ - always @(posedge i_clk) - if (!i_reset && s_valid) - begin - if (OPT_TUSER_IS_SOF) - begin - assert(s_frame == (f_s_y == 0 && f_s_x == 0)); - end else - assert(s_frame == (f_s_y == f_lines_per_frame - 1 - && f_s_x + (scount+(s_valid ? 1:0)) - >= i_pixels_per_line)); - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // c_* stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial f_c_x = 0; - initial f_c_y = 0; - always @(posedge i_clk) - if (i_reset) - begin - f_c_x <= 0; - f_c_y <= 0; - end else if (c_valid && c_step) - begin - f_c_x <= f_c_x + 1; - if (c_hlast) - begin - f_c_x <= 0; - f_c_y <= f_c_y + 1; - if (f_c_y + 1 >= f_lines_per_frame) - f_c_y <= 0; - end - end - - - // assert(f_c_x == - // {{{ - always @(posedge i_clk) - if (!i_reset) - begin - if (M_AXIS_TVALID && !M_AXIS_HLAST) - begin - assert(f_c_x == f_pixel_x + 1); - end else if (M_AXIS_TVALID && M_AXIS_HLAST) - begin - assert(f_c_x == 0); - end else - assert(f_c_x == f_pixel_x); - - assert(f_c_x < i_pixels_per_line); - end - // }}} - - // assert(f_c_y == - // {{{ - always @(posedge i_clk) - if (!i_reset) - assert(f_c_y < f_lines_per_frame); - - always @(posedge i_clk) - if (!i_reset) - begin - if (pix_valid && pix_hlast) - begin - if (f_pixel_y >= f_lines_per_frame - 1) - begin - assert(f_c_y == 0); - end else - assert(f_c_y == f_pixel_y + 1); - end else - assert(f_c_y == f_pixel_y); - end - // }}} - - // c_hlast && c_frame - // {{{ - always @(posedge i_clk) - if (!i_reset && c_valid) - begin - assert(c_hlast == (f_c_x + 1 == i_pixels_per_line)); - if (OPT_TUSER_IS_SOF) - begin - assert(c_frame == ((f_c_x == 0)&&(f_c_y == 0))); - end else - assert(c_frame == (c_hlast && (f_c_y + 1 == f_lines_per_frame))); - /* - if (OPT_TUSER_IS_SOF) - begin - assert(c_frame == ((f_c_x == 0)&&(f_c_y == 0))); - end else begin - if (!c_hlast) - assert(!c_frame); - else if (f_c_y != f_lines_per_frame - 1) - assert(!c_frame); - else - assert(c_frame); - end - */ - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Cover checking - // {{{ - - reg [3:0] cvr_frames; - - initial cvr_frames = 0; - always @(posedge i_clk) - if (i_reset) - cvr_frames = 0; - else if (M_AXIS_TVALID && M_AXIS_TREADY) - cvr_frames <= cvr_frames + M_AXIS_FRAME; - - always @(*) - if (!i_reset) - cover(cvr_frames > 2); - - always @(posedge i_clk) - if (!i_reset && cvr_frames > 2) - begin - // cover(i_mode == 3'b000); // These take too long - // cover(i_mode == 3'b001); // These take too long - cover(i_mode == 3'b010); // step 59, 13:38 - cover(i_mode == 3'b011); // step 59, 12:14 - cover(i_mode == 3'b100); // step 35 - cover(i_mode == 3'b101); // step 35 - cover(i_mode == 3'b110); // step 23 - cover(i_mode == 3'b111); // step 17 - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - assume(f_bus_words_per_line > 1); - - always @(*) - assume(f_lines_per_frame > 1); - - always @(posedge i_clk) - if (!i_reset) - assume($stable(i_mode)); - - always @(posedge i_clk) - if (!i_reset) - assume($stable(i_pixels_per_line)); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/hdmi/xclksw.v b/delete_later/rtl/hdmi/xclksw.v deleted file mode 100644 index 56f0930..0000000 --- a/delete_later/rtl/hdmi/xclksw.v +++ /dev/null @@ -1,190 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: xclksw.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A fault tolerant clock switch. -// -// Xilinx provides BUFGCTRL elements which we use here. We want a -// capability similar to a BUFGMUX, save that we want to be able to switch -// clocks even when one (or both) clocks are not present. Hence a system -// clock is required to drive a state machine and help guarantee a switch. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -module xclksw #( - parameter [0:0] DEF_CLK = 1'b0 - ) ( - // {{{ - input wire i_sys_clk, - input wire i_clk_sel, - input wire i_ck0, i_ck1, - output wire o_clk - // }}} - ); - - // Local declarations - // {{{ - localparam [2:0] CK_SET0 = 3'h0, - CK_REQ1 = 3'h1, - CK_FORCE1 = 3'h2, - CK_SET1 = 3'h3, - CK_REQ0 = 3'h4, - CK_FORCE0 = 3'h5; - reg [2:0] state; - reg [3:0] ctr; - reg hard_0, hard_1, r_sel; - // }}} - - BUFGCTRL #( - // {{{ - .INIT_OUT(1'b0), - .PRESELECT_I0(DEF_CLK ? "FALSE" : "TRUE"), - .PRESELECT_I1(DEF_CLK ? "TRUE" : "FALSE"), - .SIM_DEVICE("7SERIES") - // }}} - ) u_bufg ( - // {{{ - // Clock zero - .CE0(1'b1), // could also force w/ (!r_sel || !hard_0), - .IGNORE0(hard_0), - .S0(!r_sel), - .I0(i_ck0), - // - // Clock one - .CE1(1'b1), // could also force w/ ( r_sel || !hard_1), - .IGNORE1(hard_1), - .S1(r_sel), - .I1(i_ck1), - // - // Result - .O(o_clk) - // }}} - ); - - // State machine - // {{{ - initial begin - state = (DEF_CLK) ? CK_SET1 : CK_SET0; - r_sel = DEF_CLK; - hard_0 = 1'b0; - hard_1 = 1'b0; - ctr = 4'h0; - end - - always @(posedge i_sys_clk) - case(state) - CK_SET0: begin - // {{{ - hard_0 <= 1'b0; - hard_1 <= 1'b0; - if (ctr != 0) - ctr <= ctr - 1; - else if (i_clk_sel) - begin - state <= CK_REQ1; - r_sel <= 1'b1; - ctr <= 4'hf; - end else begin - state <= CK_SET0; - r_sel <= 1'b0; - ctr <= 4'h0; - end end - // }}} - CK_REQ1: begin - // {{{ - r_sel <= 1'b1; - hard_0 <= 1'b0; - hard_1 <= 1'b0; - ctr <= ctr - 1; - if (ctr == 0) - begin - state <= CK_FORCE1; - end end - // }}} - CK_FORCE1: begin - // {{{ - r_sel <= 1'b1; - hard_0 <= 1'b1; - hard_1 <= 1'b0; - ctr <= ctr - 1; - - if (ctr == 0) - state <= CK_SET1; - end - // }}} - CK_SET1: begin - // {{{ - hard_0 <= 1'b0; - hard_1 <= 1'b0; - if (ctr != 0) - ctr <= ctr - 1; - else if (!i_clk_sel) - begin - // Transition to clock 0 - state <= CK_REQ0; - r_sel <= 1'b0; - ctr <= 4'hf; - end else begin - // Stay at clock 1 - state <= CK_SET1; - r_sel <= 1'b1; - ctr <= 4'h0; - end end - // }}} - CK_REQ0: begin - // {{{ - r_sel <= 1'b0; - hard_0 <= 1'b0; - hard_1 <= 1'b0; - ctr <= ctr - 1; - if (ctr == 0) - begin - state <= CK_FORCE0; - end end - // }}} - CK_FORCE0: begin - // {{{ - r_sel <= 1'b0; - hard_0 <= 1'b0; - hard_1 <= 1'b1; - - ctr <= ctr - 1; - if (ctr == 0) - state <= CK_SET0; - end - // }}} - default: begin - // {{{ - state <= (i_clk_sel) ? CK_SET1 : CK_SET0; - hard_0 <= 1'b1; - hard_1 <= 1'b1; - ctr <= 4'hf; - end - // }}} - endcase - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/xhdmiin.v b/delete_later/rtl/hdmi/xhdmiin.v deleted file mode 100644 index 5f9f2d0..0000000 --- a/delete_later/rtl/hdmi/xhdmiin.v +++ /dev/null @@ -1,81 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: xhdmiin.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// }}} -module xhdmiin #( - parameter DC = 0 - ) ( - // {{{ - input wire i_clk, // Pixel clock - i_hsclk, // 10x pixel clock - i_ce, - input wire [4:0] i_delay, - output wire [4:0] o_delay, - input wire [1:0] i_hs_wire, - output wire [9:0] o_word - // }}} - ); - - // Local declarations - // {{{ - wire w_ignored; - wire [9:0] w_word; - - wire w_hs_wire, w_hs_delayed_wire; - // }}} - - // Convert from differential to internal - // {{{ - IBUFDS - hdmibuf( - .I(i_hs_wire[1]), .IB(i_hs_wire[0]), - .O(w_hs_wire) - ); - // }}} - - // Now separate us into the various bits - // {{{ - xhdmiin_deserdes - the_deserdes( - .i_clk(i_clk), - .i_hsclk(i_hsclk), - .i_ce(i_ce), - .i_delay(i_delay), - .o_delay(o_delay), - .i_pin(w_hs_wire), - .o_wire(w_ignored), - .o_word(o_word) // Decoded data to send to 10B/8B decode - ); - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/xhdmiin_deserdes.v b/delete_later/rtl/hdmi/xhdmiin_deserdes.v deleted file mode 100644 index 22a9a19..0000000 --- a/delete_later/rtl/hdmi/xhdmiin_deserdes.v +++ /dev/null @@ -1,245 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: xhdmiin_deserdes.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// }}} -module xhdmiin_deserdes #( - parameter DELAYSRC = "IDATAIN", IOBDELAY="IFD" - ) ( - // {{{ - input wire i_clk, - input wire i_hsclk, - input wire i_ce, - input wire [4:0] i_delay, - output wire [4:0] o_delay, - input wire i_pin, - output wire o_wire, - output reg [9:0] o_word - // }}} - ); - - // Local declarations - // {{{ - localparam [0:0] OPT_BITREVERSE = 1'b0; // (Not required) - - wire [5:0] ignored_data; - wire [1:0] master_to_slave; - wire ignored_output_hi; - - wire w_hs_delayed_wire, w_hs_wire; - wire [9:0] w_word; - - wire async_reset; - reg [2:0] reset_pipe; - - wire lcl_ce; - reg [1:0] syncd_ce; - wire [9:0] w_use_this_word; - // }}} - - // Turn i_ce into an async reset - // {{{ - always @(posedge i_clk, negedge i_ce) - if (!i_ce) - reset_pipe[2:0] <= 3'h7; - else - reset_pipe[2:0] <= { reset_pipe[1:0], 1'b0 }; - assign async_reset = reset_pipe[2]; - // }}} - - // Make sure i_ce is properly synchronized to the pixel clock - // {{{ - always @(posedge i_clk) - syncd_ce <= { syncd_ce[0], i_ce }; - assign lcl_ce = syncd_ce[1]; - // }}} - - // Optionally delay the incoming signal - // {{{ - generate if (IOBDELAY == "NONE") - begin - - assign w_hs_wire = i_pin; - assign w_hs_delayed_wire = 1'b0; - - end else begin - - assign w_hs_wire = 1'b0; - - IDELAYE2 #( - .CINVCTRL_SEL("FALSE"), - .DELAY_SRC(DELAYSRC), - .HIGH_PERFORMANCE_MODE("TRUE"), - .REFCLK_FREQUENCY(300.0), - .IDELAY_TYPE("VAR_LOAD") - ) delay( - .C(i_clk), - .CE(1'b1), - .CINVCTRL(1'b0), - // - .CNTVALUEIN(i_delay), - .CNTVALUEOUT(o_delay), - .LD(1'b1), - .LDPIPEEN(1'b0), - .REGRST(1'b0), - .DATAIN(), - .DATAOUT(w_hs_delayed_wire), - .INC(1'b0), - .IDATAIN(i_pin) - ); - - end endgenerate - // }}} - - ISERDESE2 #( // Master ISERDES for lower bits - // {{{ - .SERDES_MODE("MASTER"), - // - .DATA_RATE("DDR"), - .DATA_WIDTH(10), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY(IOBDELAY), - // - .NUM_CE(1), - .INIT_Q1(1'b0), .INIT_Q2(1'b0), - .INIT_Q3(1'b0), .INIT_Q4(1'b0), - .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0), - .DYN_CLKDIV_INV_EN("FALSE"), - .DYN_CLK_INV_EN("FALSE"), - .OFB_USED("FALSE") - // }}} - ) lowserdes( - // {{{ - .BITSLIP(1'b0), - .CE1(lcl_ce), .CE2(), - .CLK(i_hsclk), .CLKB(!i_hsclk), // HS clocks - .CLKDIV(i_clk), .CLKDIVP(1'b0), - .D(w_hs_wire), .DDLY(w_hs_delayed_wire), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), - .O(o_wire), .OCLK(1'b0), .OCLKB(1'b0), .OFB(1'b0), - .Q1(w_word[0]), - .Q2(w_word[1]), - .Q3(w_word[2]), - .Q4(w_word[3]), - .Q5(w_word[4]), - .Q6(w_word[5]), - .Q7(w_word[6]), - .Q8(w_word[7]), - .RST(async_reset), - .SHIFTIN1(1'h0), .SHIFTIN2(1'h0), - .SHIFTOUT1(master_to_slave[0]), .SHIFTOUT2(master_to_slave[1]) - // }}} - ); - - ISERDESE2 #( // Slave ISERDES for the upper bits - // {{{ - .SERDES_MODE("SLAVE"), - // - .DATA_RATE("DDR"), - .DATA_WIDTH(10), - .INTERFACE_TYPE("NETWORKING"), - .IOBDELAY("NONE"), - // - .NUM_CE(1), - .INIT_Q1(1'b0), .INIT_Q2(1'b0), - .INIT_Q3(1'b0), .INIT_Q4(1'b0), - .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0), - .DYN_CLKDIV_INV_EN("FALSE"), - .DYN_CLK_INV_EN("FALSE"), - .OFB_USED("FALSE") - // }}} - ) hiserdes( - // {{{ - .BITSLIP(1'b0), - .CE1(lcl_ce), .CE2(), - .CLK(i_hsclk), .CLKB(!i_hsclk), // HS clocks - .CLKDIV(i_clk), .CLKDIVP(1'b0), - .D(), .DDLY(), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), - .O(ignored_output_hi), .OCLK(1'b0), .OCLKB(1'b0), .OFB(1'b0), - .Q1(), - .Q2(), - .Q3(w_word[8]), - .Q4(w_word[9]), - .Q5(), - .Q6(), - .Q7(), - .Q8(), - // .Q7(w_word[8]), - // .Q8(w_word[9]), - .RST(async_reset), - .SHIFTIN1(master_to_slave[0]), .SHIFTIN2(master_to_slave[1]), - .SHIFTOUT1(), .SHIFTOUT2() - // }}} - ); - - // (Optionally) bit reverse our incoming data (we don't need to do this) - // {{{ - generate if (OPT_BITREVERSE) - begin - wire [9:0] w_brev; - - assign w_brev[9] = w_word[0]; - assign w_brev[8] = w_word[1]; - assign w_brev[7] = w_word[2]; - assign w_brev[6] = w_word[3]; - assign w_brev[5] = w_word[4]; - assign w_brev[4] = w_word[5]; - assign w_brev[3] = w_word[6]; - assign w_brev[2] = w_word[7]; - assign w_brev[1] = w_word[8]; - assign w_brev[0] = w_word[9]; - - assign w_use_this_word = w_brev; - end else begin - assign w_use_this_word = w_word; // w_brev; - end endgenerate - // }}} - - // Optionally delay align these bits. - // {{{ - // Turns out ... we don't need to do this here. - localparam [3:0] DLY = 0; - generate if (DLY != 0) - begin - reg [(DLY-1):0] r_word; - always @(posedge i_clk) - r_word <= w_use_this_word[(DLY-1):0]; - always @(posedge i_clk) - o_word <= { r_word[(DLY-1):0],w_use_this_word[9:(DLY)]}; - end else - always @(posedge i_clk) - o_word <= w_use_this_word; - endgenerate - // }}} -endmodule diff --git a/delete_later/rtl/hdmi/xhdmiout.v b/delete_later/rtl/hdmi/xhdmiout.v deleted file mode 100644 index 6e1edd8..0000000 --- a/delete_later/rtl/hdmi/xhdmiout.v +++ /dev/null @@ -1,183 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: xhdmiout.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// `define BYPASS_SERDES -// -// }}} -module xhdmiout ( - // {{{ - input wire i_clk, - input wire i_hsclk, - input wire i_ce, - input wire [9:0] i_word, - output wire [1:0] o_port - // }}} - ); - - // Local declarations - // {{{ - wire [5:0] ignored_data; - wire [1:0] slave_to_master; - - (* ASYNC_REG *) - reg sync_ce, q_ce, qq_ce; - reg reset; - - wire [9:0] w_word; - wire [9:0] w_in_word; - wire w_hs_wire; - - // }}} - - // Generate a synchronous reset and CE signals - // {{{ - always @(posedge i_clk) - { sync_ce, qq_ce, q_ce } <= { qq_ce, q_ce, i_ce }; - always @(posedge i_clk) - reset <= !sync_ce; - // }}} - - // (Optionally) bit reverse the input (not necessary) - // {{{ - localparam [0:0] OPT_BITREVERSE =1'b0; - generate if (OPT_BITREVERSE) - begin : GEN_BITREVERSE - // Arrange for (optionally) bit reversing the input - // - wire [9:0] brev_input; - - assign brev_input[0] = i_word[9]; - assign brev_input[1] = i_word[8]; - assign brev_input[2] = i_word[7]; - assign brev_input[3] = i_word[6]; - assign brev_input[4] = i_word[5]; - assign brev_input[5] = i_word[4]; - assign brev_input[6] = i_word[3]; - assign brev_input[7] = i_word[2]; - assign brev_input[8] = i_word[1]; - assign brev_input[9] = i_word[0]; - - assign w_in_word = brev_input; - end else begin : NO_BITREVERSE - assign w_in_word = i_word; - end endgenerate - // }}} - - // (Optionally) delay the output bits - // {{{ - localparam DLY = 0; - generate if (DLY != 0) - begin - reg [(DLY-1):0] r_word, d_word; - - always @(posedge i_clk) - r_word <= w_in_word[(DLY-1):0]; - always @(posedge i_clk) - d_word <= (i_ce) ? { r_word, w_in_word[9:DLY] }: 10'h00; - - assign w_word = d_word; - end else begin : ZERO_DELAY - assign w_word = w_in_word; - end endgenerate - // }}} - - OSERDESE2 #( // Master SERDES, for the upper bits - // {{{ - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("SDR"), - .DATA_WIDTH(10), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1) // Really ... this is unused - // }}} - ) lowserdes( - // {{{ - // Verilator lint_off PINCONNECTEMPTY - .OCE(sync_ce), .OFB(), - .TCE(1'b0), .TFB(), .TQ(), - .CLK(i_hsclk), // HS clock - .CLKDIV(i_clk), - .OQ(w_hs_wire), - .D1(w_word[9]), - .D2(w_word[8]), - .D3(w_word[7]), - .D4(w_word[6]), - .D5(w_word[5]), - .D6(w_word[4]), - .D7(w_word[3]), - .D8(w_word[2]), - .RST(reset), - .TBYTEIN(1'b0), .TBYTEOUT(), - .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), - .SHIFTIN1(slave_to_master[0]), .SHIFTIN2(slave_to_master[1]), - .SHIFTOUT1(), .SHIFTOUT2() - // Verilator lint_on PINCONNECTEMPTY - // }}} - ); - - OSERDESE2 #( // Slave SERDES, for the lower two bits - // {{{ - .DATA_RATE_OQ("DDR"), - .DATA_WIDTH(10), - .DATA_RATE_TQ("SDR"), - .SERDES_MODE("SLAVE"), - .TRISTATE_WIDTH(1) // Really ... this is unused - // }}} - ) hiserdes( - // {{{ - // Verilator lint_off PINCONNECTEMPTY - .OCE(sync_ce), .OFB(), .OQ(), - .TCE(1'b0), .TFB(), .TQ(), - .CLK(i_hsclk), // HS clock - .CLKDIV(i_clk), - .D1(1'h0), - .D2(1'h0), - .D3(w_word[1]), - .D4(w_word[0]), - .D5(1'h0), - .D6(1'h0), - .D7(1'h0), - .D8(1'h0), - .RST(reset), - .TBYTEIN(1'b0), .TBYTEOUT(), - .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), - .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), - .SHIFTOUT1(slave_to_master[0]), .SHIFTOUT2(slave_to_master[1]) - // Verilator lint_on PINCONNECTEMPTY - // }}} - ); - - // Turn this high speed output into a pair of differential pins - OBUFDS hdmibuf(.I(w_hs_wire), .O(o_port[1]), .OB(o_port[0])); - -endmodule diff --git a/delete_later/rtl/hdmi/xpxclk.v b/delete_later/rtl/hdmi/xpxclk.v deleted file mode 100644 index a2ff2f6..0000000 --- a/delete_later/rtl/hdmi/xpxclk.v +++ /dev/null @@ -1,141 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: xpxclk.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Contains the Xilinx specific portions of HDMI ingestion. -// -// Specifically, this includes: -// 1. Turning our incoming clocks from double ended to single ended via -// a Xilinx IBUFDS. -// 2. Selecting from among three clocks for our pixel clock. The pixel -// clock will therefore be one of: 1) an internal 40MHz reference, -// 2) an external reference from an Si5324 frequency generator, -// or 3) an external reference from an external/incoming HDMI RX -// port. -// 3. Once selected, pixel clock is then pushed into a PLL to generate the -// 5x pixel clock signal required for HDMI. (It's not 10x, since -// the HDMI input/output SERDES use DDR mode, so it only needs -// to be half that.) -// 4. The pixel clock and 5x clock are then pushed through BUFGs and -// output. -// -// NOTE this design uses 5 BUFGs. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module xpxclk ( - // {{{ - input wire i_sysclk, - input wire i_hdmirx_clk_p, i_hdmirx_clk_n, - input wire i_lcl_pixclk, - // input wire i_siclk_p, i_siclk_n, - input wire [1:0] i_cksel, - output wire o_hdmick_locked, - output wire o_siclk, - output wire o_hdmirx_clk, - output wire o_pixclk, o_hdmick - // }}} - ); - - // Local declarations - // {{{ - wire siclk, lclck, hdmirx_ck, preck; - wire clk_fbout, clk_fb, pixclk_nobuf, hdmi_ck; - // }}} - - // Select lclck from either i_lcl_pixclk or i_siclk - // {{{ -// `define SICLK - // This doesn't work b/c the SiCLK comes in via the MGT interface. - // It needs to run through a MGT clk handler first, before we can - // work with it here. -`ifdef SICLK - // {{{ - IBUFDS - ibuf_si_ck ( - .I(i_siclk_p), .IB(i_siclk_n), .O(siclk) - ); - - assign o_siclk = siclk; - - xclksw - lclpx ( - .i_sys_clk(i_sysclk), .i_clk_sel(i_cksel[0]), - .i_ck0(i_lcl_pixclk), .i_ck1(siclk), .o_clk(lclck) - ); - // }}} -`else - assign siclk = i_lcl_pixclk; - assign o_siclk = i_lcl_pixclk; // 1'b0; - assign lclck = i_lcl_pixclk; -`endif - // }}} - - // Select preck from either lclck or hdmirx_clk - // {{{ - IBUFDS - ibuf_hdmi_ck ( - .I(i_hdmirx_clk_p), .IB(i_hdmirx_clk_n), .O(hdmirx_ck) - ); - - assign o_hdmirx_clk = hdmirx_ck; - - xclksw - prepx ( - .i_sys_clk(i_sysclk), .i_clk_sel(i_cksel[1]), - .i_ck0(lclck), .i_ck1(hdmirx_ck), .o_clk(preck) - ); - // }}} - - PLLE2_BASE #( - // {{{ - .CLKFBOUT_MULT(20), - .CLKFBOUT_PHASE(0.0), - .CLKIN1_PERIOD(6.6), // Up to 200MHz input - .CLKOUT0_DIVIDE(20), - .CLKOUT1_DIVIDE(2) - // }}} - ) u_hdmi_pll ( - // {{{ - .CLKIN1(preck), // Incoming clock - .PWRDWN(1'b0), - .CLKFBIN(clk_fb), - .CLKFBOUT(clk_fbout), - .LOCKED(o_hdmick_locked), - // - .CLKOUT0(pixclk_nobuf), - .CLKOUT1(hdmi_ck) - // }}} - ); - - BUFG fdback_buf( .I(clk_fbout), .O(clk_fb)); - BUFG pixclk_buf( .I(pixclk_nobuf), .O(o_pixclk)); - BUFG hdmi_buf( .I(hdmi_ck), .O(o_hdmick)); - -endmodule diff --git a/delete_later/rtl/ledbouncer.v b/delete_later/rtl/ledbouncer.v deleted file mode 100644 index 700dc78..0000000 --- a/delete_later/rtl/ledbouncer.v +++ /dev/null @@ -1,120 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: ledbouncer.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module ledbouncer #( - parameter NLEDS=8, CTRBITS=25 - ) ( - input wire i_clk, - output reg[(NLEDS-1):0] o_leds - ); - - // Local declarations - // {{{ - genvar k; - - reg [(NLEDS-1):0] led_owner; - reg led_dir; - - reg [(CTRBITS-1):0] led_ctr; - reg led_clk; - - wire [4:0] br_ctr; - // }}} - - // led_clk/led_counter -- Controls overall speed - // {{{ - always @(posedge i_clk) - { led_clk, led_ctr } <= led_ctr + {{(CTRBITS-2){1'b0}},2'b11}; - - // Bit reverse the bottom five bits of this counter as well. - assign br_ctr = { led_ctr[0], led_ctr[1], led_ctr[2], led_ctr[3], - led_ctr[4] }; - // }}} - - // led_owner (strongest LED), led_dir(ection) - // {{{ - initial led_owner = { {(NLEDS-1){1'b0}}, 1'b1}; - always @(posedge i_clk) - if (led_owner == 0) - begin - led_owner <= { {(NLEDS-1){1'b0}}, 1'b1 }; - led_dir <= 1'b1; // Left, or shift up - end else if ((led_clk)&&(led_dir)) // Go left - begin - if (led_owner == { 1'b1, {(NLEDS-1){1'b0}} }) - led_dir <= !led_dir; - else - led_owner <= { led_owner[(NLEDS-2):0], 1'b0 }; - end else if (led_clk) - begin - if (led_owner == { {(NLEDS-1){1'b0}}, 1'b1 }) - led_dir <= !led_dir; - else - led_owner <= { 1'b0, led_owner[(NLEDS-1):1] }; - end - // }}} - - // per_LED: o_led and Brightness calculation - // {{{ - generate for(k=0; k<(NLEDS); k=k+1) - begin : GEN_BRIGHTNESS - reg [4:0] brightness; - - always@(posedge i_clk) - if (led_clk) - begin - if (led_owner[k]) brightness <= 5'h1f; - else if (brightness > 5'h1c) brightness <= 5'h1c; - else if (brightness > 5'h17) brightness <= 5'h17; - else if (brightness > 5'h0f) brightness <= 5'h0f; - else if (brightness > 5'h0b) brightness <= 5'h0b; - else if (brightness > 5'h07) brightness <= 5'h07; - else if (brightness > 5'h05) brightness <= 5'h05; - else if (brightness > 5'h03) brightness <= 5'h03; - else if (brightness > 5'h01) brightness <= 5'h01; - else - brightness <= 5'h00; - end - - always @(posedge i_clk) - if (brightness == 5'h1f) - o_leds[k] <= 1'b1; - else if (brightness == 5'h0) - o_leds[k] <= 1'b0; - else - o_leds[k] <= (br_ctr[4:0] <= brightness[4:0]); - end endgenerate - // }}} -endmodule - diff --git a/delete_later/rtl/main.v b/delete_later/rtl/main.v deleted file mode 100644 index 6e3eee7..0000000 --- a/delete_later/rtl/main.v +++ /dev/null @@ -1,2455 +0,0 @@ -`timescale 1ps / 1ps -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: ./main.v -// {{{ -// Project: 10Gb Ethernet switch -// -// DO NOT EDIT THIS FILE! -// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT. -// DO NOT EDIT THIS FILE! -// -// CmdLine: autofpga autofpga -I .: -d -o . allclocks.txt global.txt wbdown.txt icape.txt version.txt gpio.txt spio.txt wbuconsole.txt zipmaster.txt bkram.txt ddr3.txt sdio.txt emmc.txt sdioscope.txt emmcscope.txt mem_bkram_only.txt mem_flash_bkram.txt i2ccpu.txt fan.txt sirefclk.txt i2cscope.txt -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// }}} -`default_nettype none -//////////////////////////////////////////////////////////////////////////////// -// -// Macro defines -// {{{ -// -// -// Here is a list of defines which may be used, post auto-design -// (not post-build), to turn particular peripherals (and bus masters) -// on and off. In particular, to turn off support for a particular -// design component, just comment out its respective `define below. -// -// These lines are taken from the respective @ACCESS tags for each of our -// components. If a component doesn't have an @ACCESS tag, it will not -// be listed here. -// -// First, the independent access fields for any bus masters -`define WBUBUS_MASTER -// And then for the independent peripherals -`define EMMCSCOPE_SCOPC -`define SDIOSCOPE_SCOPC -`define DDR3_CONTROLLER_ACCESS -`define BKRAM_ACCESS -`define SIREFCLK_ACCESS -`define I2CDMA_ACCESS -`define DDR3_PHY_ACCESS -`define FAN_ACCESS -`define EMMC_ACCESS -`define I2CCPU_ACCESS -`define SDIO_ACCESS -`define BUSCONSOLE_ACCESS -`define INCLUDE_ZIPCPU -`define VERSION_ACCESS -`define I2CSCOPE_SCOPC -`define CFG_ACCESS -`define GPIO_ACCESS -`define SPIO_ACCESS -// -// End of dependency list -// -// -// }}} -//////////////////////////////////////////////////////////////////////////////// -// -// Any include files -// {{{ -// These are drawn from anything with a MAIN.INCLUDE definition. -`define INCLUDE_DMA_CONTROLLER -`define INCLUDE_ACCOUNTING_COUNTERS -`include "builddate.v" -// }}} -// -// Finally, we define our main module itself. We start with the list of -// I/O ports, or wires, passed into (or out of) the main function. -// -// These fields are copied verbatim from the respective I/O port lists, -// from the fields given by @MAIN.PORTLIST -// -module main(i_clk, i_reset, - // {{{ - // DDR3 Controller Interface - i_ddr3_controller_iserdes_data, i_ddr3_controller_iserdes_dqs, - i_ddr3_controller_iserdes_bitslip_reference, - i_ddr3_controller_idelayctrl_rdy, - o_ddr3_controller_cmd, - o_ddr3_controller_dqs_tri_control, o_ddr3_controller_dq_tri_control, - o_ddr3_controller_toggle_dqs, o_ddr3_controller_data, o_ddr3_controller_dm, - o_ddr3_controller_odelay_data_cntvaluein, o_ddr3_controller_odelay_dqs_cntvaluein, - o_ddr3_controller_idelay_data_cntvaluein, o_ddr3_controller_idelay_dqs_cntvaluein, - o_ddr3_controller_odelay_data_ld, o_ddr3_controller_odelay_dqs_ld, - o_ddr3_controller_idelay_data_ld, o_ddr3_controller_idelay_dqs_ld, - o_ddr3_controller_bitslip, - // Clock generator ports - o_sirefclk_word, o_sirefclk_ce, - i_fan_sda, i_fan_scl, - o_fan_sda, o_fan_scl, - o_fpga_pwm, o_sys_pwm, i_fan_tach, - // eMMC Card - o_emmc_clk, i_emmc_ds, -`ifdef VERILATOR - io_emmc_cmd_tristate, - o_emmc_cmd, i_emmc_cmd, - io_emmc_dat_tristate, - o_emmc_dat, i_emmc_dat, -`else - io_emmc_cmd, io_emmc_dat, -`endif - i_emmc_detect, - i_i2c_sda, i_i2c_scl, - o_i2c_sda, o_i2c_scl, - // SDIO SD Card - o_sdcard_clk, i_sdcard_ds, -`ifdef VERILATOR - io_sdcard_cmd_tristate, - o_sdcard_cmd, i_sdcard_cmd, - io_sdcard_dat_tristate, - o_sdcard_dat, i_sdcard_dat, -`else - io_sdcard_cmd, io_sdcard_dat, -`endif - i_sdcard_detect, - // Veri1ator only interface - cpu_sim_cyc, - cpu_sim_stb, - cpu_sim_we, - cpu_sim_addr, - cpu_sim_data, - cpu_sim_stall, - cpu_sim_ack, - cpu_sim_idata, -`ifdef VERILATOR - cpu_prof_stb, - cpu_prof_addr, - cpu_prof_ticks, -`endif - i_cpu_reset, - i_clk200, - // UART/host to wishbone interface - i_wbu_uart_rx, o_wbu_uart_tx, - o_wbu_uart_cts_n, - // GPIO ports - i_gpio, o_gpio, - // SPIO interface - i_sw, i_btn, o_led - // }}} - ); -//////////////////////////////////////////////////////////////////////////////// -// -// Any parameter definitions -// {{{ -// These are drawn from anything with a MAIN.PARAM definition. -// As they aren't connected to the toplevel at all, it would -// be best to use localparam over parameter, but here we don't -// check - localparam real DDR3_CONTROLLERCONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module - DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device - localparam DDR3_CONTROLLERROW_BITS = 14, // width of row address - DDR3_CONTROLLERCOL_BITS = 10, // width of column address - DDR3_CONTROLLERBA_BITS = 3, // width of bank address - DDR3_CONTROLLERDQ_BITS = 8, // Size of one octet - DDR3_CONTROLLERLANES = 8, //8 lanes of DQ - DDR3_CONTROLLERAUX_WIDTH = 1, - DDR3_CONTROLLERSERDES_RATIO = $rtoi(DDR3_CONTROLLERCONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD), - //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits - DDR3_CONTROLLERCMD_LEN = 4 + 3 + DDR3_CONTROLLERBA_BITS + DDR3_CONTROLLERROW_BITS; - - - //////////////////////////////////////////////////////////////////////// - // - // Variables/definitions/parameters used by the ZipCPU bus master - // {{{ - // - // A 32-bit address indicating where the ZipCPU should start running - // from -`ifdef BKROM_ACCESS - localparam RESET_ADDRESS = @$(/bkrom.BASE); -`else -`ifdef FLASH_ACCESS - localparam RESET_ADDRESS = @$RESET_ADDRESS; -`else - localparam RESET_ADDRESS = 67108864; -`endif // FLASH_ACCESS -`endif // BKROM_ACCESS - // - // The number of valid bits on the bus - localparam ZIP_ADDRESS_WIDTH = 22; // Zip-CPU address width - // - // Number of ZipCPU interrupts - localparam ZIP_INTS = 16; - // - // ZIP_START_HALTED - // - // A boolean, indicating whether or not the ZipCPU be halted on startup? -`ifdef BKROM_ACCESS - localparam ZIP_START_HALTED=1'b0; -`else - localparam ZIP_START_HALTED=1'b1; -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // WBUBUS parameters - // {{{ - // Baudrate : 1000000 - // Clock : 100000000 - localparam [23:0] BUSUART = 24'h64; // 1000000 baud - localparam DBGBUSBITS = $clog2(BUSUART); - // - // Maximum command is 6 bytes, where each byte takes 10 baud clocks - // and each baud clock requires DBGBUSBITS to represent. Here, - // we'll add one more for good measure. - localparam DBGBUSWATCHDOG_RAW = DBGBUSBITS + 9; - localparam DBGBUSWATCHDOG = (DBGBUSWATCHDOG_RAW > 19) - ? DBGBUSWATCHDOG_RAW : 19; - // }}} - localparam ICAPE_LGDIV=3; -// }}} -//////////////////////////////////////////////////////////////////////////////// -// -// Port declarations -// {{{ -// The next step is to declare all of the various ports that were just -// listed above. -// -// The following declarations are taken from the values of the various -// @MAIN.IODECL keys. -// - input wire i_clk; - // verilator lint_off UNUSED - input wire i_reset; - // verilator lint_on UNUSED - // DDR3 Controller I/O declarations - // {{{ - input wire [DDR3_CONTROLLERDQ_BITS*DDR3_CONTROLLERLANES*8-1:0] i_ddr3_controller_iserdes_data; - input wire [DDR3_CONTROLLERLANES*8-1:0] i_ddr3_controller_iserdes_dqs; - input wire [DDR3_CONTROLLERLANES*8-1:0] i_ddr3_controller_iserdes_bitslip_reference; - input wire i_ddr3_controller_idelayctrl_rdy; - output wire [DDR3_CONTROLLERCMD_LEN*DDR3_CONTROLLERSERDES_RATIO-1:0] o_ddr3_controller_cmd; - output wire o_ddr3_controller_dqs_tri_control, o_ddr3_controller_dq_tri_control; - output wire o_ddr3_controller_toggle_dqs; - output wire [512-1:0] o_ddr3_controller_data; - output wire [512/8-1:0] o_ddr3_controller_dm; - output wire [4:0] o_ddr3_controller_odelay_data_cntvaluein, o_ddr3_controller_odelay_dqs_cntvaluein; - output wire [4:0] o_ddr3_controller_idelay_data_cntvaluein, o_ddr3_controller_idelay_dqs_cntvaluein; - output wire [DDR3_CONTROLLERLANES-1:0] o_ddr3_controller_odelay_data_ld, o_ddr3_controller_odelay_dqs_ld; - output wire [DDR3_CONTROLLERLANES-1:0] o_ddr3_controller_idelay_data_ld, o_ddr3_controller_idelay_dqs_ld; - output wire [DDR3_CONTROLLERLANES-1:0] o_ddr3_controller_bitslip; - // }}} - output wire [7:0] o_sirefclk_word; - output wire o_sirefclk_ce; - // FAN Port declarations - // {{{ - input wire i_fan_sda, i_fan_scl; - output wire o_fan_sda, o_fan_scl; - output wire o_fpga_pwm, o_sys_pwm; - input wire i_fan_tach; - // }}} - // eMMC Card declarations - // {{{ - output wire o_emmc_clk; - input wire i_emmc_ds; -`ifdef VERILATOR - output wire io_emmc_cmd_tristate; - output wire o_emmc_cmd; - input wire i_emmc_cmd; - output wire [8-1:0] io_emmc_dat_tristate; - output wire [8-1:0] o_emmc_dat; - input wire [8-1:0] i_emmc_dat; -`else - inout wire io_emmc_cmd; - inout wire [8-1:0] io_emmc_dat; -`endif - input wire i_emmc_detect; - // }}} - // I2C Port declarations - // {{{ - input wire i_i2c_sda, i_i2c_scl; - output wire o_i2c_sda, o_i2c_scl; - // }}} - // SDIO SD Card declarations - // {{{ - output wire o_sdcard_clk; - input wire i_sdcard_ds; -`ifdef VERILATOR - output wire io_sdcard_cmd_tristate; - output wire o_sdcard_cmd; - input wire i_sdcard_cmd; - output wire [4-1:0] io_sdcard_dat_tristate; - output wire [4-1:0] o_sdcard_dat; - input wire [4-1:0] i_sdcard_dat; -`else - inout wire io_sdcard_cmd; - inout wire [4-1:0] io_sdcard_dat; -`endif - input wire i_sdcard_detect; - // }}} - input wire cpu_sim_cyc, cpu_sim_stb; - input wire cpu_sim_we; - input wire [6:0] cpu_sim_addr; - input wire [31:0] cpu_sim_data; - // - output wire cpu_sim_stall, cpu_sim_ack; - output wire [31:0] cpu_sim_idata; - // -`ifdef VERILATOR - output wire cpu_prof_stb; - output wire [22+$clog2(512/8)-1:0] cpu_prof_addr; - output wire [31:0] cpu_prof_ticks; -`endif - input wire i_cpu_reset; - input wire i_wbu_uart_rx; - output wire o_wbu_uart_tx; - // input wire i_wbu_uart_rts_n; // FT*'s perspective - output wire o_wbu_uart_cts_n; - localparam NGPI = 16, NGPO=8; - // GPIO ports - input [(NGPI-1):0] i_gpio; - output wire [(NGPO-1):0] o_gpio; - // SPIO interface - input wire [8-1:0] i_sw; - input wire [5-1:0] i_btn; - output wire [8-1:0] o_led; -// }}} - // Make Verilator happy - // {{{ - // Defining bus wires for lots of components often ends up with unused - // wires lying around. We'll turn off Ver1lator's lint warning - // here that checks for unused wires. - // }}} - // verilator lint_off UNUSED - //////////////////////////////////////////////////////////////////////// - // - // Declaring interrupt lines - // {{{ - // These declarations come from the various components values - // given under the @INT..WIRE key. - // - wire emmcscope_int; // emmcscope.INT.EMMCSCOPE.WIRE - wire sdioscope_int; // sdioscope.INT.SDIOSCOPE.WIRE - wire emmc_int; // emmc.INT.EMMC.WIRE - wire sdcard_int; // sdcard.INT.SDCARD.WIRE - wire uartrxf_int; // uart.INT.UARTRXF.WIRE - wire uarttx_int; // uart.INT.UARTTX.WIRE - wire uarttxf_int; // uart.INT.UARTTXF.WIRE - wire uartrx_int; // uart.INT.UARTRX.WIRE - wire i2cscope_int; // i2cscope.INT.I2CSCOPE.WIRE - wire gpio_int; // gpio.INT.GPIO.WIRE - wire spio_int; // spio.INT.SPIO.WIRE - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Component declarations - // {{{ - // These declarations come from the @MAIN.DEFNS keys found in the - // various components comprising the design. - // - // Verilator lint_off UNUSED - wire [DDR3_CONTROLLERAUX_WIDTH-1:0] ddr3_controller_aux_out; - // Verilator lint_on UNUSED - reg r_sirefclk_en; - reg [29:0] r_sirefclk_data; - wire w_sirefclk_unused_stb; - reg r_sirefclk_ack; - wire i2cdma_ready; - // FAN/fan Controller - // {{{ - // Verilator lint_off UNUSED - wire [31:0] fan_debug; - // Verilator lint_on UNUSED - // }}} - // eMMC Card definitions - // Verilator lint_off UNUSED - wire w_emmc_1p8v; - wire [31:0] emmc_debug; - // Verilator lint_on UNUSED - // I2C Controller - // {{{ - // Verilator lint_off UNUSED - localparam I2C_ID_WIDTH=(2 == 0) ? 1 : 2; - - wire i2c_valid, i2c_ready, i2c_last; - wire [7:0] i2c_data; - wire [I2C_ID_WIDTH-1:0] i2c_id; - - wire [31:0] i2c_debug; - // Verilator lint_on UNUSED - // }}} - // SDIO SD Card definitions - // Verilator lint_off UNUSED - wire w_sdcard_1p8v; - wire [31:0] sdcard_debug; - // Verilator lint_on UNUSED -// BUILDTIME doesnt need to include builddate.v a second time -// `include "builddate.v" - //////////////////////////////////////////////////////////////////////// - // - // WBUBUS: Console definitions - // {{{ - wire w_console_rx_stb, w_console_tx_stb, w_console_busy; - wire [6:0] w_console_rx_data, w_console_tx_data; - // Verilator lint_off UNUSED - wire [31:0] uart_debug; - // Verilator lint_on UNUSED - // }}} - //////////////////////////////////////////////////////////////////////// - // - // ZipSystem/ZipCPU connection definitions - // {{{ -`ifndef VERILATOR - wire cpu_prof_stb; - wire [22+$clog2(512/8)-1:0] cpu_prof_addr; - wire [31:0] cpu_prof_ticks; -`endif - // All we define here is a set of scope wires - // Verilator lint_off UNUSED - wire raw_cpu_dbg_stall, raw_cpu_dbg_ack; - wire [31:0] zip_debug; - wire zip_trigger; - // Verilator lint_on UNUSED - wire [ZIP_INTS-1:0] zip_int_vector; - wire zip_cpu_int; - // }}} - // Verilator lint_off UNUSED - input wire i_clk200; - // Verilator lint_on UNUSED - //////////////////////////////////////////////////////////////////////// - // - // WBUBUS: USB-UART interface declarations - // {{{ - // - wire [7:0] wbu_rx_data, wbu_tx_data; - wire wbu_rx_stb; - wire wbu_tx_stb, wbu_tx_busy; - - // Definitions for the WB-UART converter. We really only need one - // (more) non-bus wire--one to use to select if we are interacting - // with the ZipCPU or not. - // Verilator lint_off UNUSED - wire [0:0] wbubus_dbg; - // Verilator lint_on UNUSED - // }}} - // Verilator lint_off UNUSED - wire [31:0] cfg_debug; - // Verilator lint_on UNUSED - wire [8-1:0] w_led; - -// }}} - //////////////////////////////////////////////////////////////////////// - // - // Declaring interrupt vector wires - // {{{ - // These declarations come from the various components having - // PIC and PIC.MAX keys. - // - wire [14:0] sys_int_vector; - wire [14:0] alt_int_vector; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Declare bus signals - // {{{ - //////////////////////////////////////////////////////////////////////// - - // Bus wbwide - // {{{ - // Wishbone definitions for bus wbwide, component i2cdma - // Verilator lint_off UNUSED - wire wbwide_i2cdma_cyc, wbwide_i2cdma_stb, wbwide_i2cdma_we; - wire [21:0] wbwide_i2cdma_addr; - wire [511:0] wbwide_i2cdma_data; - wire [63:0] wbwide_i2cdma_sel; - wire wbwide_i2cdma_stall, wbwide_i2cdma_ack, wbwide_i2cdma_err; - wire [511:0] wbwide_i2cdma_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wbwide, component i2c - // Verilator lint_off UNUSED - wire wbwide_i2cm_cyc, wbwide_i2cm_stb, wbwide_i2cm_we; - wire [21:0] wbwide_i2cm_addr; - wire [511:0] wbwide_i2cm_data; - wire [63:0] wbwide_i2cm_sel; - wire wbwide_i2cm_stall, wbwide_i2cm_ack, wbwide_i2cm_err; - wire [511:0] wbwide_i2cm_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wbwide, component zip - // Verilator lint_off UNUSED - wire wbwide_zip_cyc, wbwide_zip_stb, wbwide_zip_we; - wire [21:0] wbwide_zip_addr; - wire [511:0] wbwide_zip_data; - wire [63:0] wbwide_zip_sel; - wire wbwide_zip_stall, wbwide_zip_ack, wbwide_zip_err; - wire [511:0] wbwide_zip_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wbwide, component wbu_arbiter - // Verilator lint_off UNUSED - wire wbwide_wbu_arbiter_cyc, wbwide_wbu_arbiter_stb, wbwide_wbu_arbiter_we; - wire [21:0] wbwide_wbu_arbiter_addr; - wire [511:0] wbwide_wbu_arbiter_data; - wire [63:0] wbwide_wbu_arbiter_sel; - wire wbwide_wbu_arbiter_stall, wbwide_wbu_arbiter_ack, wbwide_wbu_arbiter_err; - wire [511:0] wbwide_wbu_arbiter_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wbwide, component wbdown - // Verilator lint_off UNUSED - wire wbwide_wbdown_cyc, wbwide_wbdown_stb, wbwide_wbdown_we; - wire [21:0] wbwide_wbdown_addr; - wire [511:0] wbwide_wbdown_data; - wire [63:0] wbwide_wbdown_sel; - wire wbwide_wbdown_stall, wbwide_wbdown_ack, wbwide_wbdown_err; - wire [511:0] wbwide_wbdown_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wbwide, component bkram - // Verilator lint_off UNUSED - wire wbwide_bkram_cyc, wbwide_bkram_stb, wbwide_bkram_we; - wire [21:0] wbwide_bkram_addr; - wire [511:0] wbwide_bkram_data; - wire [63:0] wbwide_bkram_sel; - wire wbwide_bkram_stall, wbwide_bkram_ack, wbwide_bkram_err; - wire [511:0] wbwide_bkram_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wbwide, component ddr3_controller - // Verilator lint_off UNUSED - wire wbwide_ddr3_controller_cyc, wbwide_ddr3_controller_stb, wbwide_ddr3_controller_we; - wire [21:0] wbwide_ddr3_controller_addr; - wire [511:0] wbwide_ddr3_controller_data; - wire [63:0] wbwide_ddr3_controller_sel; - wire wbwide_ddr3_controller_stall, wbwide_ddr3_controller_ack, wbwide_ddr3_controller_err; - wire [511:0] wbwide_ddr3_controller_idata; - // Verilator lint_on UNUSED - // }}} - // Bus wb32 - // {{{ - // Wishbone definitions for bus wb32, component wbdown - // Verilator lint_off UNUSED - wire wb32_wbdown_cyc, wb32_wbdown_stb, wb32_wbdown_we; - wire [7:0] wb32_wbdown_addr; - wire [31:0] wb32_wbdown_data; - wire [3:0] wb32_wbdown_sel; - wire wb32_wbdown_stall, wb32_wbdown_ack, wb32_wbdown_err; - wire [31:0] wb32_wbdown_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32(SIO), component buildtime - // Verilator lint_off UNUSED - wire wb32_buildtime_cyc, wb32_buildtime_stb, wb32_buildtime_we; - wire [7:0] wb32_buildtime_addr; - wire [31:0] wb32_buildtime_data; - wire [3:0] wb32_buildtime_sel; - wire wb32_buildtime_stall, wb32_buildtime_ack, wb32_buildtime_err; - wire [31:0] wb32_buildtime_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32(SIO), component gpio - // Verilator lint_off UNUSED - wire wb32_gpio_cyc, wb32_gpio_stb, wb32_gpio_we; - wire [7:0] wb32_gpio_addr; - wire [31:0] wb32_gpio_data; - wire [3:0] wb32_gpio_sel; - wire wb32_gpio_stall, wb32_gpio_ack, wb32_gpio_err; - wire [31:0] wb32_gpio_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32(SIO), component sirefclk - // Verilator lint_off UNUSED - wire wb32_sirefclk_cyc, wb32_sirefclk_stb, wb32_sirefclk_we; - wire [7:0] wb32_sirefclk_addr; - wire [31:0] wb32_sirefclk_data; - wire [3:0] wb32_sirefclk_sel; - wire wb32_sirefclk_stall, wb32_sirefclk_ack, wb32_sirefclk_err; - wire [31:0] wb32_sirefclk_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32(SIO), component spio - // Verilator lint_off UNUSED - wire wb32_spio_cyc, wb32_spio_stb, wb32_spio_we; - wire [7:0] wb32_spio_addr; - wire [31:0] wb32_spio_data; - wire [3:0] wb32_spio_sel; - wire wb32_spio_stall, wb32_spio_ack, wb32_spio_err; - wire [31:0] wb32_spio_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32(SIO), component version - // Verilator lint_off UNUSED - wire wb32_version_cyc, wb32_version_stb, wb32_version_we; - wire [7:0] wb32_version_addr; - wire [31:0] wb32_version_data; - wire [3:0] wb32_version_sel; - wire wb32_version_stall, wb32_version_ack, wb32_version_err; - wire [31:0] wb32_version_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component emmcscope - // Verilator lint_off UNUSED - wire wb32_emmcscope_cyc, wb32_emmcscope_stb, wb32_emmcscope_we; - wire [7:0] wb32_emmcscope_addr; - wire [31:0] wb32_emmcscope_data; - wire [3:0] wb32_emmcscope_sel; - wire wb32_emmcscope_stall, wb32_emmcscope_ack, wb32_emmcscope_err; - wire [31:0] wb32_emmcscope_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component i2cscope - // Verilator lint_off UNUSED - wire wb32_i2cscope_cyc, wb32_i2cscope_stb, wb32_i2cscope_we; - wire [7:0] wb32_i2cscope_addr; - wire [31:0] wb32_i2cscope_data; - wire [3:0] wb32_i2cscope_sel; - wire wb32_i2cscope_stall, wb32_i2cscope_ack, wb32_i2cscope_err; - wire [31:0] wb32_i2cscope_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component sdioscope - // Verilator lint_off UNUSED - wire wb32_sdioscope_cyc, wb32_sdioscope_stb, wb32_sdioscope_we; - wire [7:0] wb32_sdioscope_addr; - wire [31:0] wb32_sdioscope_data; - wire [3:0] wb32_sdioscope_sel; - wire wb32_sdioscope_stall, wb32_sdioscope_ack, wb32_sdioscope_err; - wire [31:0] wb32_sdioscope_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component i2c - // Verilator lint_off UNUSED - wire wb32_i2cs_cyc, wb32_i2cs_stb, wb32_i2cs_we; - wire [7:0] wb32_i2cs_addr; - wire [31:0] wb32_i2cs_data; - wire [3:0] wb32_i2cs_sel; - wire wb32_i2cs_stall, wb32_i2cs_ack, wb32_i2cs_err; - wire [31:0] wb32_i2cs_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component i2cdma - // Verilator lint_off UNUSED - wire wb32_i2cdma_cyc, wb32_i2cdma_stb, wb32_i2cdma_we; - wire [7:0] wb32_i2cdma_addr; - wire [31:0] wb32_i2cdma_data; - wire [3:0] wb32_i2cdma_sel; - wire wb32_i2cdma_stall, wb32_i2cdma_ack, wb32_i2cdma_err; - wire [31:0] wb32_i2cdma_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component uart - // Verilator lint_off UNUSED - wire wb32_uart_cyc, wb32_uart_stb, wb32_uart_we; - wire [7:0] wb32_uart_addr; - wire [31:0] wb32_uart_data; - wire [3:0] wb32_uart_sel; - wire wb32_uart_stall, wb32_uart_ack, wb32_uart_err; - wire [31:0] wb32_uart_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component emmc - // Verilator lint_off UNUSED - wire wb32_emmc_cyc, wb32_emmc_stb, wb32_emmc_we; - wire [7:0] wb32_emmc_addr; - wire [31:0] wb32_emmc_data; - wire [3:0] wb32_emmc_sel; - wire wb32_emmc_stall, wb32_emmc_ack, wb32_emmc_err; - wire [31:0] wb32_emmc_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component fan - // Verilator lint_off UNUSED - wire wb32_fan_cyc, wb32_fan_stb, wb32_fan_we; - wire [7:0] wb32_fan_addr; - wire [31:0] wb32_fan_data; - wire [3:0] wb32_fan_sel; - wire wb32_fan_stall, wb32_fan_ack, wb32_fan_err; - wire [31:0] wb32_fan_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component sdcard - // Verilator lint_off UNUSED - wire wb32_sdcard_cyc, wb32_sdcard_stb, wb32_sdcard_we; - wire [7:0] wb32_sdcard_addr; - wire [31:0] wb32_sdcard_data; - wire [3:0] wb32_sdcard_sel; - wire wb32_sdcard_stall, wb32_sdcard_ack, wb32_sdcard_err; - wire [31:0] wb32_sdcard_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component wb32_sio - // Verilator lint_off UNUSED - wire wb32_sio_cyc, wb32_sio_stb, wb32_sio_we; - wire [7:0] wb32_sio_addr; - wire [31:0] wb32_sio_data; - wire [3:0] wb32_sio_sel; - wire wb32_sio_stall, wb32_sio_ack, wb32_sio_err; - wire [31:0] wb32_sio_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component cfg - // Verilator lint_off UNUSED - wire wb32_cfg_cyc, wb32_cfg_stb, wb32_cfg_we; - wire [7:0] wb32_cfg_addr; - wire [31:0] wb32_cfg_data; - wire [3:0] wb32_cfg_sel; - wire wb32_cfg_stall, wb32_cfg_ack, wb32_cfg_err; - wire [31:0] wb32_cfg_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wb32, component ddr3_phy - // Verilator lint_off UNUSED - wire wb32_ddr3_phy_cyc, wb32_ddr3_phy_stb, wb32_ddr3_phy_we; - wire [7:0] wb32_ddr3_phy_addr; - wire [31:0] wb32_ddr3_phy_data; - wire [3:0] wb32_ddr3_phy_sel; - wire wb32_ddr3_phy_stall, wb32_ddr3_phy_ack, wb32_ddr3_phy_err; - wire [31:0] wb32_ddr3_phy_idata; - // Verilator lint_on UNUSED - // }}} - // Bus wbu - // {{{ - // Wishbone definitions for bus wbu, component wbu - // Verilator lint_off UNUSED - wire wbu_cyc, wbu_stb, wbu_we; - wire [26:0] wbu_addr; - wire [31:0] wbu_data; - wire [3:0] wbu_sel; - wire wbu_stall, wbu_ack, wbu_err; - wire [31:0] wbu_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wbu, component wbu_arbiter - // Verilator lint_off UNUSED - wire wbu_wbu_arbiter_cyc, wbu_wbu_arbiter_stb, wbu_wbu_arbiter_we; - wire [26:0] wbu_wbu_arbiter_addr; - wire [31:0] wbu_wbu_arbiter_data; - wire [3:0] wbu_wbu_arbiter_sel; - wire wbu_wbu_arbiter_stall, wbu_wbu_arbiter_ack, wbu_wbu_arbiter_err; - wire [31:0] wbu_wbu_arbiter_idata; - // Verilator lint_on UNUSED - // Wishbone definitions for bus wbu, component zip - // Verilator lint_off UNUSED - wire wbu_zip_cyc, wbu_zip_stb, wbu_zip_we; - wire [26:0] wbu_zip_addr; - wire [31:0] wbu_zip_data; - wire [3:0] wbu_zip_sel; - wire wbu_zip_stall, wbu_zip_ack, wbu_zip_err; - wire [31:0] wbu_zip_idata; - // Verilator lint_on UNUSED - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Peripheral address decoding, bus handling - // {{{ - // - // BUS-LOGIC for wbwide - // {{{ - // - // No class SINGLE peripherals on the "wbwide" bus - // - - // - // No class DOUBLE peripherals on the "wbwide" bus - // - - // info: @ERROR.WIRE for wbdown matches the buses error name, wbwide_wbdown_err - assign wbwide_bkram_err= 1'b0; - assign wbwide_ddr3_controller_err= 1'b0; - // - // Connect the wbwide bus components together using the wbxbar() - // - // - wbxbar #( - .NM(4), .NS(3), .AW(22), .DW(512), - .SLAVE_ADDR({ - // Address width = 22 - // Address LSBs = 6 - // Slave name width = 15 - { 22'h200000 }, // ddr3_controller: 0x8000000 - { 22'h100000 }, // bkram: 0x4000000 - { 22'h080000 } // wbdown: 0x2000000 - }), - .SLAVE_MASK({ - // Address width = 22 - // Address LSBs = 6 - // Slave name width = 15 - { 22'h200000 }, // ddr3_controller - { 22'h380000 }, // bkram - { 22'h380000 } // wbdown - }), - .OPT_DBLBUFFER(1'b1)) - wbwide_xbar( - .i_clk(i_clk), .i_reset(i_reset), - .i_mcyc({ - wbwide_wbu_arbiter_cyc, - wbwide_zip_cyc, - wbwide_i2cm_cyc, - wbwide_i2cdma_cyc - }), - .i_mstb({ - wbwide_wbu_arbiter_stb, - wbwide_zip_stb, - wbwide_i2cm_stb, - wbwide_i2cdma_stb - }), - .i_mwe({ - wbwide_wbu_arbiter_we, - wbwide_zip_we, - wbwide_i2cm_we, - wbwide_i2cdma_we - }), - .i_maddr({ - wbwide_wbu_arbiter_addr, - wbwide_zip_addr, - wbwide_i2cm_addr, - wbwide_i2cdma_addr - }), - .i_mdata({ - wbwide_wbu_arbiter_data, - wbwide_zip_data, - wbwide_i2cm_data, - wbwide_i2cdma_data - }), - .i_msel({ - wbwide_wbu_arbiter_sel, - wbwide_zip_sel, - wbwide_i2cm_sel, - wbwide_i2cdma_sel - }), - .o_mstall({ - wbwide_wbu_arbiter_stall, - wbwide_zip_stall, - wbwide_i2cm_stall, - wbwide_i2cdma_stall - }), - .o_mack({ - wbwide_wbu_arbiter_ack, - wbwide_zip_ack, - wbwide_i2cm_ack, - wbwide_i2cdma_ack - }), - .o_mdata({ - wbwide_wbu_arbiter_idata, - wbwide_zip_idata, - wbwide_i2cm_idata, - wbwide_i2cdma_idata - }), - .o_merr({ - wbwide_wbu_arbiter_err, - wbwide_zip_err, - wbwide_i2cm_err, - wbwide_i2cdma_err - }), - // Slave connections - .o_scyc({ - wbwide_ddr3_controller_cyc, - wbwide_bkram_cyc, - wbwide_wbdown_cyc - }), - .o_sstb({ - wbwide_ddr3_controller_stb, - wbwide_bkram_stb, - wbwide_wbdown_stb - }), - .o_swe({ - wbwide_ddr3_controller_we, - wbwide_bkram_we, - wbwide_wbdown_we - }), - .o_saddr({ - wbwide_ddr3_controller_addr, - wbwide_bkram_addr, - wbwide_wbdown_addr - }), - .o_sdata({ - wbwide_ddr3_controller_data, - wbwide_bkram_data, - wbwide_wbdown_data - }), - .o_ssel({ - wbwide_ddr3_controller_sel, - wbwide_bkram_sel, - wbwide_wbdown_sel - }), - .i_sstall({ - wbwide_ddr3_controller_stall, - wbwide_bkram_stall, - wbwide_wbdown_stall - }), - .i_sack({ - wbwide_ddr3_controller_ack, - wbwide_bkram_ack, - wbwide_wbdown_ack - }), - .i_sdata({ - wbwide_ddr3_controller_idata, - wbwide_bkram_idata, - wbwide_wbdown_idata - }), - .i_serr({ - wbwide_ddr3_controller_err, - wbwide_bkram_err, - wbwide_wbdown_err - }) - ); - - // End of bus logic for wbwide - // }}} - // - // BUS-LOGIC for wb32 - // {{{ - // - // wb32 Bus logic to handle SINGLE slaves - // - reg r_wb32_sio_ack; - reg [31:0] r_wb32_sio_data; - - assign wb32_sio_stall = 1'b0; - - initial r_wb32_sio_ack = 1'b0; - always @(posedge i_clk) - r_wb32_sio_ack <= (wb32_sio_stb); - assign wb32_sio_ack = r_wb32_sio_ack; - - always @(posedge i_clk) - casez( wb32_sio_addr[2:0] ) - 3'h0: r_wb32_sio_data <= wb32_buildtime_idata; - 3'h1: r_wb32_sio_data <= wb32_gpio_idata; - 3'h2: r_wb32_sio_data <= wb32_sirefclk_idata; - 3'h3: r_wb32_sio_data <= wb32_spio_idata; - 3'h4: r_wb32_sio_data <= wb32_version_idata; - default: r_wb32_sio_data <= wb32_version_idata; - endcase - assign wb32_sio_idata = r_wb32_sio_data; - - - // - // Now to translate this logic to the various SIO slaves - // - // In this case, the SIO bus has the prefix wb32_sio - // and all of the slaves have various wires beginning - // with their own respective bus prefixes. - // Our goal here is to make certain that all of - // the slave bus inputs match the SIO bus wires - assign wb32_buildtime_cyc = wb32_sio_cyc; - assign wb32_buildtime_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h0); // 0x00 - assign wb32_buildtime_we = wb32_sio_we; - assign wb32_buildtime_data= wb32_sio_data; - assign wb32_buildtime_sel = wb32_sio_sel; - assign wb32_gpio_cyc = wb32_sio_cyc; - assign wb32_gpio_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h1); // 0x04 - assign wb32_gpio_we = wb32_sio_we; - assign wb32_gpio_data= wb32_sio_data; - assign wb32_gpio_sel = wb32_sio_sel; - assign wb32_sirefclk_cyc = wb32_sio_cyc; - assign wb32_sirefclk_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h2); // 0x08 - assign wb32_sirefclk_we = wb32_sio_we; - assign wb32_sirefclk_data= wb32_sio_data; - assign wb32_sirefclk_sel = wb32_sio_sel; - assign wb32_spio_cyc = wb32_sio_cyc; - assign wb32_spio_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h3); // 0x0c - assign wb32_spio_we = wb32_sio_we; - assign wb32_spio_data= wb32_sio_data; - assign wb32_spio_sel = wb32_sio_sel; - assign wb32_version_cyc = wb32_sio_cyc; - assign wb32_version_stb = wb32_sio_stb && (wb32_sio_addr[ 2: 0] == 3'h4); // 0x10 - assign wb32_version_we = wb32_sio_we; - assign wb32_version_data= wb32_sio_data; - assign wb32_version_sel = wb32_sio_sel; - // - // No class DOUBLE peripherals on the "wb32" bus - // - - assign wb32_emmcscope_err= 1'b0; - assign wb32_i2cscope_err= 1'b0; - assign wb32_sdioscope_err= 1'b0; - assign wb32_i2cs_err= 1'b0; - assign wb32_i2cdma_err= 1'b0; - assign wb32_uart_err= 1'b0; - assign wb32_emmc_err= 1'b0; - assign wb32_fan_err= 1'b0; - assign wb32_sdcard_err= 1'b0; - assign wb32_sio_err= 1'b0; - assign wb32_cfg_err= 1'b0; - assign wb32_ddr3_phy_err= 1'b0; - // - // Connect the wb32 bus components together using the wbxbar() - // - // - wbxbar #( - .NM(1), .NS(12), .AW(8), .DW(32), - .SLAVE_ADDR({ - // Address width = 8 - // Address LSBs = 2 - // Slave name width = 9 - { 8'h80 }, // ddr3_phy: 0x200 - { 8'h60 }, // cfg: 0x180 - { 8'h48 }, // wb32_sio: 0x120 - { 8'h40 }, // sdcard: 0x100 - { 8'h38 }, // fan: 0x0e0 - { 8'h30 }, // emmc: 0x0c0 - { 8'h28 }, // uart: 0x0a0 - { 8'h20 }, // i2cdma: 0x080 - { 8'h18 }, // i2c: 0x060 - { 8'h10 }, // sdioscope: 0x040 - { 8'h08 }, // i2cscope: 0x020 - { 8'h00 } // emmcscope: 0x000 - }), - .SLAVE_MASK({ - // Address width = 8 - // Address LSBs = 2 - // Slave name width = 9 - { 8'h80 }, // ddr3_phy - { 8'he0 }, // cfg - { 8'hf8 }, // wb32_sio - { 8'hf8 }, // sdcard - { 8'hf8 }, // fan - { 8'hf8 }, // emmc - { 8'hf8 }, // uart - { 8'hf8 }, // i2cdma - { 8'hf8 }, // i2c - { 8'hf8 }, // sdioscope - { 8'hf8 }, // i2cscope - { 8'hf8 } // emmcscope - }), - .OPT_DBLBUFFER(1'b1)) - wb32_xbar( - .i_clk(i_clk), .i_reset(i_reset), - .i_mcyc({ - wb32_wbdown_cyc - }), - .i_mstb({ - wb32_wbdown_stb - }), - .i_mwe({ - wb32_wbdown_we - }), - .i_maddr({ - wb32_wbdown_addr - }), - .i_mdata({ - wb32_wbdown_data - }), - .i_msel({ - wb32_wbdown_sel - }), - .o_mstall({ - wb32_wbdown_stall - }), - .o_mack({ - wb32_wbdown_ack - }), - .o_mdata({ - wb32_wbdown_idata - }), - .o_merr({ - wb32_wbdown_err - }), - // Slave connections - .o_scyc({ - wb32_ddr3_phy_cyc, - wb32_cfg_cyc, - wb32_sio_cyc, - wb32_sdcard_cyc, - wb32_fan_cyc, - wb32_emmc_cyc, - wb32_uart_cyc, - wb32_i2cdma_cyc, - wb32_i2cs_cyc, - wb32_sdioscope_cyc, - wb32_i2cscope_cyc, - wb32_emmcscope_cyc - }), - .o_sstb({ - wb32_ddr3_phy_stb, - wb32_cfg_stb, - wb32_sio_stb, - wb32_sdcard_stb, - wb32_fan_stb, - wb32_emmc_stb, - wb32_uart_stb, - wb32_i2cdma_stb, - wb32_i2cs_stb, - wb32_sdioscope_stb, - wb32_i2cscope_stb, - wb32_emmcscope_stb - }), - .o_swe({ - wb32_ddr3_phy_we, - wb32_cfg_we, - wb32_sio_we, - wb32_sdcard_we, - wb32_fan_we, - wb32_emmc_we, - wb32_uart_we, - wb32_i2cdma_we, - wb32_i2cs_we, - wb32_sdioscope_we, - wb32_i2cscope_we, - wb32_emmcscope_we - }), - .o_saddr({ - wb32_ddr3_phy_addr, - wb32_cfg_addr, - wb32_sio_addr, - wb32_sdcard_addr, - wb32_fan_addr, - wb32_emmc_addr, - wb32_uart_addr, - wb32_i2cdma_addr, - wb32_i2cs_addr, - wb32_sdioscope_addr, - wb32_i2cscope_addr, - wb32_emmcscope_addr - }), - .o_sdata({ - wb32_ddr3_phy_data, - wb32_cfg_data, - wb32_sio_data, - wb32_sdcard_data, - wb32_fan_data, - wb32_emmc_data, - wb32_uart_data, - wb32_i2cdma_data, - wb32_i2cs_data, - wb32_sdioscope_data, - wb32_i2cscope_data, - wb32_emmcscope_data - }), - .o_ssel({ - wb32_ddr3_phy_sel, - wb32_cfg_sel, - wb32_sio_sel, - wb32_sdcard_sel, - wb32_fan_sel, - wb32_emmc_sel, - wb32_uart_sel, - wb32_i2cdma_sel, - wb32_i2cs_sel, - wb32_sdioscope_sel, - wb32_i2cscope_sel, - wb32_emmcscope_sel - }), - .i_sstall({ - wb32_ddr3_phy_stall, - wb32_cfg_stall, - wb32_sio_stall, - wb32_sdcard_stall, - wb32_fan_stall, - wb32_emmc_stall, - wb32_uart_stall, - wb32_i2cdma_stall, - wb32_i2cs_stall, - wb32_sdioscope_stall, - wb32_i2cscope_stall, - wb32_emmcscope_stall - }), - .i_sack({ - wb32_ddr3_phy_ack, - wb32_cfg_ack, - wb32_sio_ack, - wb32_sdcard_ack, - wb32_fan_ack, - wb32_emmc_ack, - wb32_uart_ack, - wb32_i2cdma_ack, - wb32_i2cs_ack, - wb32_sdioscope_ack, - wb32_i2cscope_ack, - wb32_emmcscope_ack - }), - .i_sdata({ - wb32_ddr3_phy_idata, - wb32_cfg_idata, - wb32_sio_idata, - wb32_sdcard_idata, - wb32_fan_idata, - wb32_emmc_idata, - wb32_uart_idata, - wb32_i2cdma_idata, - wb32_i2cs_idata, - wb32_sdioscope_idata, - wb32_i2cscope_idata, - wb32_emmcscope_idata - }), - .i_serr({ - wb32_ddr3_phy_err, - wb32_cfg_err, - wb32_sio_err, - wb32_sdcard_err, - wb32_fan_err, - wb32_emmc_err, - wb32_uart_err, - wb32_i2cdma_err, - wb32_i2cs_err, - wb32_sdioscope_err, - wb32_i2cscope_err, - wb32_emmcscope_err - }) - ); - - // End of bus logic for wb32 - // }}} - // - // BUS-LOGIC for wbu - // {{{ - // - // No class SINGLE peripherals on the "wbu" bus - // - - // - // No class DOUBLE peripherals on the "wbu" bus - // - - // info: @ERROR.WIRE for wbu_arbiter matches the buses error name, wbu_wbu_arbiter_err - assign wbu_zip_err= 1'b0; - // - // Connect the wbu bus components together using the wbxbar() - // - // - wbxbar #( - .NM(1), .NS(2), .AW(27), .DW(32), - .SLAVE_ADDR({ - // Address width = 27 - // Address LSBs = 2 - // Slave name width = 11 - { 27'h4000000 }, // zip: 0x10000000 - { 27'h0000000 } // wbu_arbiter: 0x00000000 - }), - .SLAVE_MASK({ - // Address width = 27 - // Address LSBs = 2 - // Slave name width = 11 - { 27'h4000000 }, // zip - { 27'h4000000 } // wbu_arbiter - }), - .OPT_DBLBUFFER(1'b1)) - wbu_xbar( - .i_clk(i_clk), .i_reset(i_reset), - .i_mcyc({ - wbu_cyc - }), - .i_mstb({ - wbu_stb - }), - .i_mwe({ - wbu_we - }), - .i_maddr({ - wbu_addr - }), - .i_mdata({ - wbu_data - }), - .i_msel({ - wbu_sel - }), - .o_mstall({ - wbu_stall - }), - .o_mack({ - wbu_ack - }), - .o_mdata({ - wbu_idata - }), - .o_merr({ - wbu_err - }), - // Slave connections - .o_scyc({ - wbu_zip_cyc, - wbu_wbu_arbiter_cyc - }), - .o_sstb({ - wbu_zip_stb, - wbu_wbu_arbiter_stb - }), - .o_swe({ - wbu_zip_we, - wbu_wbu_arbiter_we - }), - .o_saddr({ - wbu_zip_addr, - wbu_wbu_arbiter_addr - }), - .o_sdata({ - wbu_zip_data, - wbu_wbu_arbiter_data - }), - .o_ssel({ - wbu_zip_sel, - wbu_wbu_arbiter_sel - }), - .i_sstall({ - wbu_zip_stall, - wbu_wbu_arbiter_stall - }), - .i_sack({ - wbu_zip_ack, - wbu_wbu_arbiter_ack - }), - .i_sdata({ - wbu_zip_idata, - wbu_wbu_arbiter_idata - }), - .i_serr({ - wbu_zip_err, - wbu_wbu_arbiter_err - }) - ); - - // End of bus logic for wbu - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Declare the interrupt busses - // {{{ - // Interrupt busses are defined by anything with a @PIC tag. - // The @PIC.BUS tag defines the name of the wire bus below, - // while the @PIC.MAX tag determines the size of the bus width. - // - // For your peripheral to be assigned to this bus, it must have an - // @INT.NAME.WIRE= tag to define the wire name of the interrupt line, - // and an @INT.NAME.PIC= tag matching the @PIC.BUS tag of the bus - // your interrupt will be assigned to. If an @INT.NAME.ID tag also - // exists, then your interrupt will be assigned to the position given - // by the ID# in that tag. - // - assign sys_int_vector = { - 1'b0, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - spio_int, - uarttxf_int, - uartrxf_int, - sdcard_int, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - 1'b0 - }; - assign alt_int_vector = { - gpio_int, - i2cscope_int, - uartrx_int, - uarttx_int, - emmc_int, - sdioscope_int, - emmcscope_int, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - 1'b0, - 1'b0 - }; - // }}} - //////////////////////////////////////////////////////////////////////// - //////////////////////////////////////////////////////////////////////// - // - // @MAIN.INSERT and @MAIN.ALT - // {{{ - //////////////////////////////////////////////////////////////////////// - //////////////////////////////////////////////////////////////////////// - // - // - // Now we turn to defining all of the parts and pieces of what - // each of the various peripherals does, and what logic it needs. - // - // This information comes from the @MAIN.INSERT and @MAIN.ALT tags. - // If an @ACCESS tag is available, an ifdef is created to handle - // having the access and not. If the @ACCESS tag is `defined above - // then the @MAIN.INSERT code is executed. If not, the @MAIN.ALT - // code is exeucted, together with any other cleanup settings that - // might need to take place--such as returning zeros to the bus, - // or making sure all of the various interrupt wires are set to - // zero if the component is not included. - // -`ifdef EMMCSCOPE_SCOPC - // {{{ - wbscopc #( - // {{{ - .LGMEM(12), - .SYNCHRONOUS(1), - .DEFAULT_HOLDOFF(2044) - // }}} - ) emmcscopei( - // {{{ - i_clk, 1'b1, emmc_debug[31], emmc_debug[30:0], - i_clk, - wb32_emmcscope_cyc, wb32_emmcscope_stb, wb32_emmcscope_we, - wb32_emmcscope_addr[1-1:0], - wb32_emmcscope_data, // 32 bits wide - wb32_emmcscope_sel, // 32/8 bits wide - wb32_emmcscope_stall, wb32_emmcscope_ack, wb32_emmcscope_idata, - emmcscope_int - // }}} - ); - // }}} -`else // EMMCSCOPE_SCOPC - // {{{ - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_emmcscope peripheral - // responding on the wb32 bus - assign wb32_emmcscope_ack = 1'b0; - assign wb32_emmcscope_err = (wb32_emmcscope_stb); - assign wb32_emmcscope_stall = 0; - assign wb32_emmcscope_idata = 0; - - // }}} - // Null interrupt definitions - // {{{ - assign emmcscope_int = 1'b0; // emmcscope.INT.EMMCSCOPE.WIRE - // }}} - // }}} -`endif // EMMCSCOPE_SCOPC - -`ifdef SDIOSCOPE_SCOPC - // {{{ - wbscopc #( - // {{{ - .LGMEM(12), - .SYNCHRONOUS(1), - .DEFAULT_HOLDOFF(2044) - // }}} - ) sdioscopei( - // {{{ - i_clk, 1'b1, sdcard_debug[31], sdcard_debug[30:0], - i_clk, - wb32_sdioscope_cyc, wb32_sdioscope_stb, wb32_sdioscope_we, - wb32_sdioscope_addr[1-1:0], - wb32_sdioscope_data, // 32 bits wide - wb32_sdioscope_sel, // 32/8 bits wide - wb32_sdioscope_stall, wb32_sdioscope_ack, wb32_sdioscope_idata, - sdioscope_int - // }}} - ); - // }}} -`else // SDIOSCOPE_SCOPC - // {{{ - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_sdioscope peripheral - // responding on the wb32 bus - assign wb32_sdioscope_ack = 1'b0; - assign wb32_sdioscope_err = (wb32_sdioscope_stb); - assign wb32_sdioscope_stall = 0; - assign wb32_sdioscope_idata = 0; - - // }}} - // Null interrupt definitions - // {{{ - assign sdioscope_int = 1'b0; // sdioscope.INT.SDIOSCOPE.WIRE - // }}} - // }}} -`endif // SDIOSCOPE_SCOPC - -`ifdef DDR3_CONTROLLER_ACCESS - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // DDR3 Controller instantiation - // {{{ - ddr3_controller #( - .CONTROLLER_CLK_PERIOD(DDR3_CONTROLLERCONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module - .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device - .ROW_BITS(DDR3_CONTROLLERROW_BITS), //width of row address - .COL_BITS(DDR3_CONTROLLERCOL_BITS), //width of column address - .BA_BITS(DDR3_CONTROLLERBA_BITS), //width of bank address - .DQ_BITS(DDR3_CONTROLLERDQ_BITS), //width of DQ - .LANES(DDR3_CONTROLLERLANES), //8 lanes of DQ - .AUX_WIDTH(DDR3_CONTROLLERAUX_WIDTH), // - .OPT_LOWPOWER(1), //1 = low power, 0 = low logic - .OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction) - ) ddr3_controller_inst ( - .i_controller_clk(i_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD - .i_rst_n(!i_reset), //200MHz input clock - // Wishbone 1 (Controller) - .i_wb_cyc(wbwide_ddr3_controller_cyc), .i_wb_stb(wbwide_ddr3_controller_stb), .i_wb_we(wbwide_ddr3_controller_we), - .i_wb_addr(wbwide_ddr3_controller_addr[21-1:0]), - .i_wb_data(wbwide_ddr3_controller_data), // 512 bits wide - .i_wb_sel(wbwide_ddr3_controller_sel), // 512/8 bits wide - .o_wb_stall(wbwide_ddr3_controller_stall),.o_wb_ack(wbwide_ddr3_controller_ack), .o_wb_data(wbwide_ddr3_controller_idata), - .i_aux(0), - .o_aux(ddr3_controller_aux_out), // Leaving this empty would've caused a Verilator warning - // Wishbone 2 (PHY) - .i_wb2_cyc(wb32_ddr3_phy_cyc), .i_wb2_stb(wb32_ddr3_phy_stb), .i_wb2_we(wb32_ddr3_phy_we), - .i_wb2_addr(wb32_ddr3_phy_addr[7-1:0]), - .i_wb2_data(wb32_ddr3_phy_data), // 32 bits wide - .i_wb2_sel(wb32_ddr3_phy_sel), // 32/8 bits wide - .o_wb2_stall(wb32_ddr3_phy_stall),.o_wb2_ack(wb32_ddr3_phy_ack), .o_wb2_data(wb32_ddr3_phy_idata), - // - // PHY interface - .i_phy_iserdes_data(i_ddr3_controller_iserdes_data), - .i_phy_iserdes_dqs(i_ddr3_controller_iserdes_dqs), - .i_phy_iserdes_bitslip_reference(i_ddr3_controller_iserdes_bitslip_reference), - .i_phy_idelayctrl_rdy(i_ddr3_controller_idelayctrl_rdy), - .o_phy_cmd(o_ddr3_controller_cmd), - .o_phy_dqs_tri_control(o_ddr3_controller_dqs_tri_control), - .o_phy_dq_tri_control(o_ddr3_controller_dq_tri_control), - .o_phy_toggle_dqs(o_ddr3_controller_toggle_dqs), - .o_phy_data(o_ddr3_controller_data), - .o_phy_dm(o_ddr3_controller_dm), - .o_phy_odelay_data_cntvaluein(o_ddr3_controller_odelay_data_cntvaluein), - .o_phy_odelay_dqs_cntvaluein(o_ddr3_controller_odelay_dqs_cntvaluein), - .o_phy_idelay_data_cntvaluein(o_ddr3_controller_idelay_data_cntvaluein), - .o_phy_idelay_dqs_cntvaluein(o_ddr3_controller_idelay_dqs_cntvaluein), - .o_phy_odelay_data_ld(o_ddr3_controller_odelay_data_ld), - .o_phy_odelay_dqs_ld(o_ddr3_controller_odelay_dqs_ld), - .o_phy_idelay_data_ld(o_ddr3_controller_idelay_data_ld), - .o_phy_idelay_dqs_ld(o_ddr3_controller_idelay_dqs_ld), - .o_phy_bitslip(o_ddr3_controller_bitslip) - ); - // }}} - // }}} -`else // DDR3_CONTROLLER_ACCESS - // {{{ - // Null bus slave - // {{{ - - // - // In the case that there is no wbwide_ddr3_controller peripheral - // responding on the wbwide bus - assign wbwide_ddr3_controller_ack = 1'b0; - assign wbwide_ddr3_controller_err = (wbwide_ddr3_controller_stb); - assign wbwide_ddr3_controller_stall = 0; - assign wbwide_ddr3_controller_idata = 0; - - // }}} - // }}} -`endif // DDR3_CONTROLLER_ACCESS - -`ifdef BKRAM_ACCESS - // {{{ - memdev #( - .LGMEMSZ(20), - .DW(512), - .EXTRACLOCK(1) - ) bkrami( - .i_clk(i_clk), - .i_reset(i_reset), - .i_wb_cyc(wbwide_bkram_cyc), .i_wb_stb(wbwide_bkram_stb), .i_wb_we(wbwide_bkram_we), - .i_wb_addr(wbwide_bkram_addr[14-1:0]), - .i_wb_data(wbwide_bkram_data), // 512 bits wide - .i_wb_sel(wbwide_bkram_sel), // 512/8 bits wide - .o_wb_stall(wbwide_bkram_stall),.o_wb_ack(wbwide_bkram_ack), .o_wb_data(wbwide_bkram_idata) - ); - // }}} -`else // BKRAM_ACCESS - // {{{ - // Null bus slave - // {{{ - - // - // In the case that there is no wbwide_bkram peripheral - // responding on the wbwide bus - assign wbwide_bkram_ack = 1'b0; - assign wbwide_bkram_err = (wbwide_bkram_stb); - assign wbwide_bkram_stall = 0; - assign wbwide_bkram_idata = 0; - - // }}} - // }}} -`endif // BKRAM_ACCESS - -`ifdef SIREFCLK_ACCESS - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // Generated clock handling - // {{{ - // - // Set to 0x2f85_1ec0 for 148.5MHz - // - initial r_sirefclk_en = 1'b0; - initial r_sirefclk_data = 30'd20000; - always @(posedge i_clk) - if (wb32_sirefclk_stb && wb32_sirefclk_we) - begin - if (wb32_sirefclk_sel[0]) - r_sirefclk_data[ 7: 0] <= wb32_sirefclk_data[ 7:0]; - if (wb32_sirefclk_sel[1]) - r_sirefclk_data[15: 8] <= wb32_sirefclk_data[15:8]; - if (wb32_sirefclk_sel[2]) - r_sirefclk_data[23:16] <= wb32_sirefclk_data[23:16]; - if (wb32_sirefclk_sel[3]) - begin - r_sirefclk_en <= !wb32_sirefclk_data[31]; - r_sirefclk_data[29:24]<= wb32_sirefclk_data[29:24]; - end - end - - always @(posedge i_clk) - if (i_reset) - r_sirefclk_ack <= 1'b0; - else - r_sirefclk_ack <= wb32_sirefclk_stb; - - assign wb32_sirefclk_ack = r_sirefclk_ack; - assign wb32_sirefclk_stall = 1'b0; - assign wb32_sirefclk_idata = { !r_sirefclk_en, - 1'b0, r_sirefclk_data }; - assign o_sirefclk_ce = r_sirefclk_en; - - genclk - clock_generator( - .i_clk(i_clk), - .i_delay({ 2'b00, r_sirefclk_data[29:0] }), - .o_word(o_sirefclk_word), - .o_stb(w_sirefclk_unused_stb) - ); - // }}} - // }}} -`else // SIREFCLK_ACCESS - // {{{ - // }}} -`endif // SIREFCLK_ACCESS - -`ifdef I2CDMA_ACCESS - // {{{ - wbi2cdma #( - .AW(22), .DW(512), .SW(8), - .OPT_LITTLE_ENDIAN(1'b0) - ) u_i2cdma ( - .i_clk(i_clk), - .i_reset(i_reset), - // - .i_wb_cyc(wb32_i2cdma_cyc), .i_wb_stb(wb32_i2cdma_stb), .i_wb_we(wb32_i2cdma_we), - .i_wb_addr(wb32_i2cdma_addr[2-1:0]), - .i_wb_data(wb32_i2cdma_data), // 32 bits wide - .i_wb_sel(wb32_i2cdma_sel), // 32/8 bits wide - .o_wb_stall(wb32_i2cdma_stall),.o_wb_ack(wb32_i2cdma_ack), .o_wb_data(wb32_i2cdma_idata), - .S_VALID(i2c_valid && i2c_id == 2), .S_READY(i2cdma_ready), - .S_DATA(i2c_data), .S_LAST(i2c_last), - .o_dma_cyc(wbwide_i2cdma_cyc), .o_dma_stb(wbwide_i2cdma_stb), .o_dma_we(wbwide_i2cdma_we), - .o_dma_addr(wbwide_i2cdma_addr[22-1:0]), - .o_dma_data(wbwide_i2cdma_data), // 512 bits wide - .o_dma_sel(wbwide_i2cdma_sel), // 512/8 bits wide - .i_dma_stall(wbwide_i2cdma_stall), .i_dma_ack(wbwide_i2cdma_ack), .i_dma_data(wbwide_i2cdma_idata), .i_dma_err(wbwide_i2cdma_err) - ); - - // }}} -`else // I2CDMA_ACCESS - // {{{ - assign @$(prefix)_ready = 1'b0; - // Null bus master - // {{{ - // }}} - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_i2cdma peripheral - // responding on the wb32 bus - assign wb32_i2cdma_ack = 1'b0; - assign wb32_i2cdma_err = (wb32_i2cdma_stb); - assign wb32_i2cdma_stall = 0; - assign wb32_i2cdma_idata = 0; - - // }}} - // }}} -`endif // I2CDMA_ACCESS - -`ifdef FAN_ACCESS - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // The FAN Controller: fan - // {{{ - - wbfan - u_fan ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - .i_wb_cyc(wb32_fan_cyc), .i_wb_stb(wb32_fan_stb), .i_wb_we(wb32_fan_we), - .i_wb_addr(wb32_fan_addr[3-1:0]), - .i_wb_data(wb32_fan_data), // 32 bits wide - .i_wb_sel(wb32_fan_sel), // 32/8 bits wide - .o_wb_stall(wb32_fan_stall),.o_wb_ack(wb32_fan_ack), .o_wb_data(wb32_fan_idata), - .i_temp_sda(i_fan_sda), .i_temp_scl(i_fan_scl), - .o_temp_sda(o_fan_sda), .o_temp_scl(o_fan_scl), - // - .o_fpga_pwm(o_fpga_pwm), .o_sys_pwm(o_sys_pwm), - .i_fan_tach(i_fan_tach), - // - .temp_debug(fan_debug) - // }}} - ); - // }}} - // }}} -`else // FAN_ACCESS - // {{{ - assign o_fan_scl = 1'b1; - assign o_fan_sda = 1'b1; - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_fan peripheral - // responding on the wb32 bus - assign wb32_fan_ack = 1'b0; - assign wb32_fan_err = (wb32_fan_stb); - assign wb32_fan_stall = 0; - assign wb32_fan_idata = 0; - - // }}} - // }}} -`endif // FAN_ACCESS - -`ifdef EMMC_ACCESS - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // eMMC Card handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - sdio_top #( - .NUMIO(8), - .OPT_SERDES(1'b0), - .OPT_DDR(1'b0), - .OPT_CARD_DETECT(1'b0), - .MW(32) - ) u_emmc( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - .i_hsclk(1'b0), - .i_wb_cyc(wb32_emmc_cyc), .i_wb_stb(wb32_emmc_stb), .i_wb_we(wb32_emmc_we), - .i_wb_addr(wb32_emmc_addr[3-1:0]), - .i_wb_data(wb32_emmc_data), // 32 bits wide - .i_wb_sel(wb32_emmc_sel), // 32/8 bits wide - .o_wb_stall(wb32_emmc_stall),.o_wb_ack(wb32_emmc_ack), .o_wb_data(wb32_emmc_idata), - .o_ck(o_emmc_clk), - .i_ds(i_emmc_ds), -`ifdef VERILATOR - .io_cmd_tristate(io_emmc_cmd_tristate), - .o_cmd(o_emmc_cmd), - .i_cmd(i_emmc_cmd), - .io_dat_tristate(io_emmc_dat_tristate), - .o_dat(o_emmc_dat), - .i_dat(i_emmc_dat), -`else - .io_cmd(io_emmc_cmd), - .io_dat(io_emmc_dat), -`endif - .i_card_detect(i_emmc_detect), - .o_1p8v(w_emmc_1p8v), - .o_int(emmc_int), - .o_debug(emmc_debug) - // }}} - ); - - // }}} - // }}} -`else // EMMC_ACCESS - // {{{ - assign o_emmc_clk = 1'b1; -`ifdef VERILATOR - assign io_emmc_cmd_tristate = 1'b1; - assign o_emmc_cmd = 1'b1; - assign io_emmc_data_tristate = -1; - assign o_emmc_data = -1; -`else // VERILATOR - assign io_emmc_cmd = 1'b1; - assign io_emmc_dat = -1; -`endif // VERILATOR - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_emmc peripheral - // responding on the wb32 bus - assign wb32_emmc_ack = 1'b0; - assign wb32_emmc_err = (wb32_emmc_stb); - assign wb32_emmc_stall = 0; - assign wb32_emmc_idata = 0; - - // }}} - // Null interrupt definitions - // {{{ - assign emmc_int = 1'b0; // emmc.INT.EMMC.WIRE - // }}} - // }}} -`endif // EMMC_ACCESS - -`ifdef I2CCPU_ACCESS - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // The I2C Controller - // {{{ - - wbi2ccpu #( - .ADDRESS_WIDTH(22), - .DATA_WIDTH(512), - .AXIS_ID_WIDTH(2) - ) i2ci ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(wb32_i2cs_cyc), .i_wb_stb(wb32_i2cs_stb), .i_wb_we(wb32_i2cs_we), - .i_wb_addr(wb32_i2cs_addr[2-1:0]), - .i_wb_data(wb32_i2cs_data), // 32 bits wide - .i_wb_sel(wb32_i2cs_sel), // 32/8 bits wide - .o_wb_stall(wb32_i2cs_stall),.o_wb_ack(wb32_i2cs_ack), .o_wb_data(wb32_i2cs_idata), - .o_pf_cyc(wbwide_i2cm_cyc), .o_pf_stb(wbwide_i2cm_stb), .o_pf_we(wbwide_i2cm_we), - .o_pf_addr(wbwide_i2cm_addr[22-1:0]), - .o_pf_data(wbwide_i2cm_data), // 512 bits wide - .o_pf_sel(wbwide_i2cm_sel), // 512/8 bits wide - .i_pf_stall(wbwide_i2cm_stall), .i_pf_ack(wbwide_i2cm_ack), .i_pf_data(wbwide_i2cm_idata), .i_pf_err(wbwide_i2cm_err), - .i_i2c_sda(i_i2c_sda), .i_i2c_scl(i_i2c_scl), - .o_i2c_sda(o_i2c_sda), .o_i2c_scl(o_i2c_scl), - .M_AXIS_TVALID(i2c_valid), .M_AXIS_TREADY(i2c_ready), - .M_AXIS_TDATA(i2c_data), .M_AXIS_TLAST(i2c_last), - .M_AXIS_TID(i2c_id), - .i_sync_signal(1'b0), - // - .o_debug(i2c_debug) - // }}} - ); - - assign i2c_ready = (!i2c_valid) || (1'b0 - || (i2c_id == 0) // NULL address -`ifdef EDID_ACCESS - || (i2c_id == 1 && edid_ready) -`else - || (i2c_id == 1) -`endif -`ifdef I2CDMA_ACCESS - || (i2c_id == 2 && i2cdma_ready) -`else - || (i2c_id == 2) -`endif - || (i2c_id > 2)); - - // }}} - // }}} -`else // I2CCPU_ACCESS - // {{{ - assign o_i2c_scl = 1'b1; - assign o_i2c_sda = 1'b1; - // Null bus master - // {{{ - // }}} - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_i2cs peripheral - // responding on the wb32 bus - assign wb32_i2cs_ack = 1'b0; - assign wb32_i2cs_err = (wb32_i2cs_stb); - assign wb32_i2cs_stall = 0; - assign wb32_i2cs_idata = 0; - - // }}} - // }}} -`endif // I2CCPU_ACCESS - - wbdown #( - // {{{ - .ADDRESS_WIDTH(8+$clog2(32/8)), - .WIDE_DW(512), - .SMALL_DW(32), - .OPT_LITTLE_ENDIAN(1'b0), - .OPT_LOWLOGIC(1'b0) - // }}} - ) u_wbdown ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - // Slave/incoming - // {{{ - .i_wcyc( wbwide_wbdown_cyc), - .i_wstb( wbwide_wbdown_stb), - .i_wwe( wbwide_wbdown_we), - .i_waddr( wbwide_wbdown_addr[4-1:0]), - .i_wdata( wbwide_wbdown_data), - .i_wsel( wbwide_wbdown_sel), - .o_wstall(wbwide_wbdown_stall), - .o_wack( wbwide_wbdown_ack), - .o_wdata( wbwide_wbdown_idata), - .o_werr( wbwide_wbdown_err), - // }}} - // Master/down-range/outgoing - // {{{ - .o_scyc( wb32_wbdown_cyc), - .o_sstb( wb32_wbdown_stb), - .o_swe( wb32_wbdown_we), - .o_saddr( wb32_wbdown_addr[8-1:0]), - .o_sdata( wb32_wbdown_data), - .o_ssel( wb32_wbdown_sel), - .i_sstall(wb32_wbdown_stall), - .i_sack( wb32_wbdown_ack), - .i_sdata( wb32_wbdown_idata), - .i_serr( wb32_wbdown_err) - // }}} - // }}} - ); -`ifdef SDIO_ACCESS - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // SDIO SD Card handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - sdio_top #( - .NUMIO(4), - .OPT_SERDES(1'b0), - .OPT_DDR(1'b1), - .OPT_CARD_DETECT(1'b1), - .MW(32) - ) u_sdcard( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - .i_hsclk(1'b0), - .i_wb_cyc(wb32_sdcard_cyc), .i_wb_stb(wb32_sdcard_stb), .i_wb_we(wb32_sdcard_we), - .i_wb_addr(wb32_sdcard_addr[3-1:0]), - .i_wb_data(wb32_sdcard_data), // 32 bits wide - .i_wb_sel(wb32_sdcard_sel), // 32/8 bits wide - .o_wb_stall(wb32_sdcard_stall),.o_wb_ack(wb32_sdcard_ack), .o_wb_data(wb32_sdcard_idata), - .o_ck(o_sdcard_clk), - .i_ds(i_sdcard_ds), -`ifdef VERILATOR - .io_cmd_tristate(io_sdcard_cmd_tristate), - .o_cmd(o_sdcard_cmd), - .i_cmd(i_sdcard_cmd), - .io_dat_tristate(io_sdcard_dat_tristate), - .o_dat(o_sdcard_dat), - .i_dat(i_sdcard_dat), -`else - .io_cmd(io_sdcard_cmd), - .io_dat(io_sdcard_dat), -`endif - .i_card_detect(i_sdcard_detect), - .o_1p8v(w_sdcard_1p8v), - .o_int(sdcard_int), - .o_debug(sdcard_debug) - // }}} - ); - - // }}} - // }}} -`else // SDIO_ACCESS - // {{{ - assign o_sdcard_clk = 1'b1; -`ifdef VERILATOR - assign io_sdcard_cmd_tristate = 1'b1; - assign o_sdcard_cmd = 1'b1; - assign io_sdcard_data_tristate = -1; - assign o_sdcard_data = -1; -`else // VERILATOR - assign io_sdcard_cmd = 1'b1; - assign io_sdcard_dat = -1; -`endif // VERILATOR - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_sdcard peripheral - // responding on the wb32 bus - assign wb32_sdcard_ack = 1'b0; - assign wb32_sdcard_err = (wb32_sdcard_stb); - assign wb32_sdcard_stall = 0; - assign wb32_sdcard_idata = 0; - - // }}} - // Null interrupt definitions - // {{{ - assign sdcard_int = 1'b0; // sdcard.INT.SDCARD.WIRE - // }}} - // }}} -`endif // SDIO_ACCESS - - assign wb32_buildtime_idata = `BUILDTIME; - assign wb32_buildtime_ack = wb32_buildtime_stb; - assign wb32_buildtime_stall = 1'b0; -`ifdef BUSCONSOLE_ACCESS - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // WBUBUS: Console instantiations - // {{{ - wbconsole #(.LGFLEN(6) - ) console( - // {{{ - .i_clk(i_clk), .i_reset(1'b0), - .i_wb_cyc(wb32_uart_cyc), .i_wb_stb(wb32_uart_stb), .i_wb_we(wb32_uart_we), - .i_wb_addr(wb32_uart_addr[2-1:0]), - .i_wb_data(wb32_uart_data), // 32 bits wide - .i_wb_sel(wb32_uart_sel), // 32/8 bits wide - .o_wb_stall(wb32_uart_stall),.o_wb_ack(wb32_uart_ack), .o_wb_data(wb32_uart_idata), - .o_uart_stb(w_console_tx_stb), .o_uart_data(w_console_tx_data), -`ifdef SMI_CONSOLE - .i_uart_busy(w_console_busy || smi_console_valid), -`else - .i_uart_busy(w_console_busy), -`endif - .i_uart_stb(w_console_rx_stb), .i_uart_data(w_console_rx_data), - .o_uart_rx_int(uartrx_int), .o_uart_tx_int(uarttx_int), - .o_uart_rxfifo_int(uartrxf_int),.o_uart_txfifo_int(uarttxf_int), - .o_debug(uart_debug) - // }}} - ); - // }}} - // }}} -`else // BUSCONSOLE_ACCESS - // {{{ - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_uart peripheral - // responding on the wb32 bus - assign wb32_uart_ack = 1'b0; - assign wb32_uart_err = (wb32_uart_stb); - assign wb32_uart_stall = 0; - assign wb32_uart_idata = 0; - - // }}} - // Null interrupt definitions - // {{{ - assign uartrxf_int = 1'b0; // uart.INT.UARTRXF.WIRE - assign uarttx_int = 1'b0; // uart.INT.UARTTX.WIRE - assign uarttxf_int = 1'b0; // uart.INT.UARTTXF.WIRE - assign uartrx_int = 1'b0; // uart.INT.UARTRX.WIRE - // }}} - // }}} -`endif // BUSCONSOLE_ACCESS - -`ifdef INCLUDE_ZIPCPU - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // The ZipCPU/ZipSystem BUS master - // {{{ - // - assign zip_int_vector = { alt_int_vector[14:8], sys_int_vector[14:6] }; - zipsystem #( - // {{{ - .RESET_ADDRESS(RESET_ADDRESS), - .ADDRESS_WIDTH(ZIP_ADDRESS_WIDTH + $clog2(512/8)), - .BUS_WIDTH(512), - .OPT_LGICACHE(12), - .OPT_LGDCACHE(12), - .START_HALTED(ZIP_START_HALTED), - .RESET_DURATION(20), - .OPT_PIPELINED(1), -`ifdef INCLUDE_DMA_CONTROLLER - .OPT_DMA(1'b1), -`else - .OPT_DMA(1'b0), -`endif -`ifdef INCLUDE_ACCOUNTING_COUNTERS - .OPT_ACCOUNTING(1'b1), -`else - .OPT_ACCOUNTING(1'b0), -`endif -`ifdef VERILATOR - .OPT_PROFILER(1'b1), -`else - .OPT_PROFILER(1'b0), -`endif -`ifdef ZIPSCOPE_SCOPE - .OPT_TRACE_PORT(1'b1), -`else - .OPT_TRACE_PORT(1'b0), -`endif - .OPT_DISTRIBUTED_REGS(1), - .EXTERNAL_INTERRUPTS(ZIP_INTS) - // }}} - ) swic( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || i_cpu_reset), - // Zipsys wishbone interface - .o_wb_cyc(wbwide_zip_cyc), .o_wb_stb(wbwide_zip_stb), .o_wb_we(wbwide_zip_we), - .o_wb_addr(wbwide_zip_addr[22-1:0]), - .o_wb_data(wbwide_zip_data), // 512 bits wide - .o_wb_sel(wbwide_zip_sel), // 512/8 bits wide - .i_wb_stall(wbwide_zip_stall), .i_wb_ack(wbwide_zip_ack), .i_wb_data(wbwide_zip_idata), .i_wb_err(wbwide_zip_err), - .i_ext_int(zip_int_vector), .o_ext_int(zip_cpu_int), - // Debug wishbone interface - .i_dbg_cyc(wbu_zip_cyc || cpu_sim_cyc), - .i_dbg_stb(cpu_sim_cyc ? cpu_sim_stb : wbu_zip_stb), - .i_dbg_we( cpu_sim_cyc ? cpu_sim_we : wbu_zip_we), - .i_dbg_addr(cpu_sim_cyc? cpu_sim_addr : wbu_zip_addr[6:0]), - .i_dbg_data (cpu_sim_cyc? cpu_sim_data : wbu_zip_data), - .i_dbg_sel (cpu_sim_cyc? 4'hf : wbu_zip_sel), - .o_dbg_stall(raw_cpu_dbg_stall), - .o_dbg_ack (raw_cpu_dbg_ack), - .o_dbg_data (wbu_zip_idata), - // - .o_cpu_debug(zip_debug), - .o_prof_stb(cpu_prof_stb), - .o_prof_addr(cpu_prof_addr), - .o_prof_ticks(cpu_prof_ticks) - // }}} - ); - assign zip_trigger = zip_debug[31]; - - assign wbu_zip_stall = cpu_sim_cyc || raw_cpu_dbg_stall; - assign wbu_zip_ack = !cpu_sim_cyc && raw_cpu_dbg_ack; - assign cpu_sim_stall = !cpu_sim_cyc || raw_cpu_dbg_stall; - assign cpu_sim_ack = cpu_sim_cyc && raw_cpu_dbg_ack; - assign cpu_sim_idata = wbu_zip_idata; - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire zip_unused; - assign zip_unused = &{ 1'b0, - alt_int_vector[7:0], sys_int_vector[5:0]}; - // Verilator lint_on UNUSED - // }}} - // }}} - // }}} -`else // INCLUDE_ZIPCPU - // {{{ - // Null bus master - // {{{ - // }}} - // Null bus slave - // {{{ - - // - // In the case that there is no wbu_zip peripheral - // responding on the wbu bus - assign wbu_zip_ack = 1'b0; - assign wbu_zip_err = (wbu_zip_stb); - assign wbu_zip_stall = 0; - assign wbu_zip_idata = 0; - - // }}} - // }}} -`endif // INCLUDE_ZIPCPU - -`ifdef VERSION_ACCESS - // {{{ - assign wb32_version_idata = `DATESTAMP; - assign wb32_version_ack = wb32_version_stb; - assign wb32_version_stall = 1'b0; - // }}} -`else // VERSION_ACCESS - // {{{ - // }}} -`endif // VERSION_ACCESS - -`ifdef I2CSCOPE_SCOPC - // {{{ - wbscopc #( - // {{{ - .LGMEM(10), - .SYNCHRONOUS(1), - .DEFAULT_HOLDOFF(508) - // }}} - ) i2cscopei( - // {{{ - i_clk, 1'b1, i2c_debug[31], i2c_debug[30:0], - i_clk, - wb32_i2cscope_cyc, wb32_i2cscope_stb, wb32_i2cscope_we, - wb32_i2cscope_addr[1-1:0], - wb32_i2cscope_data, // 32 bits wide - wb32_i2cscope_sel, // 32/8 bits wide - wb32_i2cscope_stall, wb32_i2cscope_ack, wb32_i2cscope_idata, - i2cscope_int - // }}} - ); - // }}} -`else // I2CSCOPE_SCOPC - // {{{ - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_i2cscope peripheral - // responding on the wb32 bus - assign wb32_i2cscope_ack = 1'b0; - assign wb32_i2cscope_err = (wb32_i2cscope_stb); - assign wb32_i2cscope_stall = 0; - assign wb32_i2cscope_idata = 0; - - // }}} - // Null interrupt definitions - // {{{ - assign i2cscope_int = 1'b0; // i2cscope.INT.I2CSCOPE.WIRE - // }}} - // }}} -`endif // I2CSCOPE_SCOPC - -`ifdef WBUBUS_MASTER - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // WBUBUS: USB-UART driven bus master and console - // {{{ - // The Host USB interface, to be used by the WB-UART bus - rxuartlite #( - // {{{ - .TIMER_BITS(DBGBUSBITS), - .CLOCKS_PER_BAUD(BUSUART[DBGBUSBITS-1:0]) - // }}} - ) rcv( - // {{{ - .i_clk( i_clk), - .i_uart_rx(i_wbu_uart_rx), - .o_wr( wbu_rx_stb), - .o_data( wbu_rx_data) - // }}} - ); - - txuartlite #( - // {{{ - .TIMING_BITS(DBGBUSBITS[4:0]), - .CLOCKS_PER_BAUD(BUSUART[DBGBUSBITS-1:0]) - // }}} - ) txv( - // {{{ - .i_clk( i_clk), - .i_wr( wbu_tx_stb), - .i_data( wbu_tx_data), - .o_uart_tx(o_wbu_uart_tx), - .o_busy( wbu_tx_busy) - // }}} - ); - - assign o_wbu_uart_cts_n = 1'b0; - -`ifndef BUSPIC_ACCESS - wire w_bus_int; -`ifdef INCLUDE_ZIPCPU - assign w_bus_int = zip_cpu_int; -`else - assign w_bus_int = 1'b0; -`endif -`endif - // Verilator lint_off UNUSED - wire [29:0] wbu_tmp_addr; - // Verilator lint_on UNUSED - wbuconsole #( - // {{{ - .LGWATCHDOG(DBGBUSWATCHDOG) - // }}} - ) genbus( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_rx_stb(wbu_rx_stb), .i_rx_data(wbu_rx_data), - .o_wb_cyc(wbu_cyc), .o_wb_stb(wbu_stb), - .o_wb_we(wbu_we), - .o_wb_addr(wbu_tmp_addr), - .o_wb_data(wbu_data), - .i_wb_stall(wbu_stall), - .i_wb_ack(wbu_ack), - .i_wb_data(wbu_idata), - .i_wb_err(wbu_err), - .i_interrupt(w_bus_int), - .o_tx_stb(wbu_tx_stb), .o_tx_data(wbu_tx_data), - .i_tx_busy(wbu_tx_busy), - // -`ifdef SMI_CONSOLE - .i_console_stb(w_console_tx_stb || smi_console_valid), - .i_console_data(smi_console_valid ? smi_console_data[6:0] - : w_console_tx_data), -`else - .i_console_stb(w_console_tx_stb), - .i_console_data(w_console_tx_data), -`endif - .o_console_busy(w_console_busy), - .o_console_stb(w_console_rx_stb), - .o_console_data(w_console_rx_data), - // - .o_dbg(wbubus_dbg[0]) - // }}} - ); - -`ifdef SMI_CONSOLE - assign smi_console_ready = !w_console_busy; -`endif - - assign wbu_sel = 4'hf; - assign wbu_addr = wbu_tmp_addr[(27-1):0]; - // }}} - // }}} -`else // WBUBUS_MASTER - // {{{ - // Null bus master - // {{{ - // }}} - // }}} -`endif // WBUBUS_MASTER - -`ifdef CFG_ACCESS - // {{{ -`ifdef VERILATOR - reg r_cfg_ack; - - initial r_cfg_ack = 1'b0; - always @(posedge i_clk) - r_cfg_ack <= wb32_cfg_stb; - assign wb32_cfg_ack = r_cfg_ack; - assign wb32_cfg_stall = 1'b0; - assign wb32_cfg_idata = 32'h00; - - assign cfg_debug = 32'h00; - - // Verilator lint_off UNUSED - wire cfg_unused; - assign cfg_unused = &{ 1'b0, ICAPE_LGDIV[31:0] }; - // Verilator lint_on UNUSED -`else - wbicapetwo #( - .LGDIV(ICAPE_LGDIV) - ) u_cfgport( - .i_clk(i_clk), - .i_wb_cyc(wb32_cfg_cyc), .i_wb_stb(wb32_cfg_stb), .i_wb_we(wb32_cfg_we), - .i_wb_addr(wb32_cfg_addr[5-1:0]), - .i_wb_data(wb32_cfg_data), // 32 bits wide - .i_wb_sel(wb32_cfg_sel), // 32/8 bits wide - .o_wb_stall(wb32_cfg_stall),.o_wb_ack(wb32_cfg_ack), .o_wb_data(wb32_cfg_idata), - .o_dbg(cfg_debug) - ); -`endif - // }}} -`else // CFG_ACCESS - // {{{ - // Null bus slave - // {{{ - - // - // In the case that there is no wb32_cfg peripheral - // responding on the wb32 bus - assign wb32_cfg_ack = 1'b0; - assign wb32_cfg_err = (wb32_cfg_stb); - assign wb32_cfg_stall = 0; - assign wb32_cfg_idata = 0; - - // }}} - // }}} -`endif // CFG_ACCESS - -`ifdef GPIO_ACCESS - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // GPIO - // {{{ - // This interface should allow us to control up to 16 GPIO inputs, - // and another 16 GPIO outputs. The interrupt trips when any of - // the inputs changes. (Sorry, which input isn't (yet) selectable.) - // - // Initially set: - // 4x Test points to zero - // SI5324 reset to 0 (active) - // HDMI RX as *not* present - // *TRACE* defaults to OFF - // *ERROR* defaults to NONE (0) - localparam [NGPO-1:0] INITIAL_GPIO = 8'h20; - - wbgpio #( - .NIN(NGPI), .NOUT(NGPO), .DEFAULT(INITIAL_GPIO) - ) gpioi( - // {{{ - i_clk, wb32_gpio_cyc, wb32_gpio_stb, wb32_gpio_we, - wb32_gpio_data, // 32 bits wide - wb32_gpio_sel, // 32/8 bits wide - wb32_gpio_stall, wb32_gpio_ack, wb32_gpio_idata, - i_gpio, o_gpio, gpio_int - // }}} - ); - - // }}} - // }}} -`else // GPIO_ACCESS - // {{{ - // Null interrupt definitions - // {{{ - assign gpio_int = 1'b0; // gpio.INT.GPIO.WIRE - // }}} - // }}} -`endif // GPIO_ACCESS - -`ifdef SPIO_ACCESS - // {{{ - // - // Special purpose I/O driver (buttons, LEDs, and switches) - // - - spio #( - .NBTN(5), .NLEDS(8), .NSW(8) - ) spioi( - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(wb32_spio_cyc), .i_wb_stb(wb32_spio_stb), .i_wb_we(wb32_spio_we), - .i_wb_data(wb32_spio_data), // 32 bits wide - .i_wb_sel(wb32_spio_sel), // 32/8 bits wide - .o_wb_stall(wb32_spio_stall),.o_wb_ack(wb32_spio_ack), .o_wb_data(wb32_spio_idata), - .i_sw(i_sw), .i_btn(i_btn), .o_led(w_led), - .o_int(spio_int) - ); - - assign o_led = w_led; - - // }}} -`else // SPIO_ACCESS - // {{{ - assign w_btn = 0; - assign o_led = 0; - // Null interrupt definitions - // {{{ - assign spio_int = 1'b0; // spio.INT.SPIO.WIRE - // }}} - // }}} -`endif // SPIO_ACCESS - - //////////////////////////////////////////////////////////////////////// - // - // WBUBUS "wbu_arbiter" master->slave connection - // {{{ - wbupsz #( - // {{{ - .ADDRESS_WIDTH(22+$clog2(512/8)), - .SMALL_DW(32), - .WIDE_DW(512), - .OPT_LITTLE_ENDIAN(1'b0) - // }}} - ) wbu_arbiter_upsz ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - .i_scyc(wbu_wbu_arbiter_cyc), .i_sstb(wbu_wbu_arbiter_stb), .i_swe(wbu_wbu_arbiter_we), - .i_saddr(wbu_wbu_arbiter_addr[26-1:0]), - .i_sdata(wbu_wbu_arbiter_data), // 32 bits wide - .i_ssel(wbu_wbu_arbiter_sel), // 32/8 bits wide - .o_sstall(wbu_wbu_arbiter_stall),.o_sack(wbu_wbu_arbiter_ack), .o_sdata(wbu_wbu_arbiter_idata), .o_serr(wbu_wbu_arbiter_err), - .o_wcyc(wbwide_wbu_arbiter_cyc), .o_wstb(wbwide_wbu_arbiter_stb), .o_wwe(wbwide_wbu_arbiter_we), - .o_waddr(wbwide_wbu_arbiter_addr[22-1:0]), - .o_wdata(wbwide_wbu_arbiter_data), // 512 bits wide - .o_wsel(wbwide_wbu_arbiter_sel), // 512/8 bits wide - .i_wstall(wbwide_wbu_arbiter_stall), .i_wack(wbwide_wbu_arbiter_ack), .i_wdata(wbwide_wbu_arbiter_idata), .i_werr(wbwide_wbu_arbiter_err) - // }}} - ); - // }}} - // }}} -endmodule // main.v diff --git a/delete_later/rtl/make.inc b/delete_later/rtl/make.inc deleted file mode 100644 index 4141fc5..0000000 --- a/delete_later/rtl/make.inc +++ /dev/null @@ -1,69 +0,0 @@ -################################################################################ -## -## Filename: ./rtl.make.inc -## {{{ -## Project: 10Gb Ethernet switch -## -## DO NOT EDIT THIS FILE! -## Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT. -## DO NOT EDIT THIS FILE! -## -## CmdLine: autofpga autofpga -I .: -d -o . allclocks.txt global.txt wbdown.txt icape.txt version.txt gpio.txt spio.txt wbuconsole.txt zipmaster.txt bkram.txt ddr3.txt sdio.txt emmc.txt sdioscope.txt emmcscope.txt mem_bkram_only.txt mem_flash_bkram.txt i2ccpu.txt fan.txt sirefclk.txt i2cscope.txt -## -## Creator: Dan Gisselquist, Ph.D. -## Gisselquist Technology, LLC -## -################################################################################ -## }}} -## Copyright (C) 2023, Gisselquist Technology, LLC -## {{{ -## This file is part of the ETH10G project. -## -## The ETH10G project contains free software and gateware, licensed under the -## Apache License, Version 2.0 (the "License"). You may not use this project, -## or this file, except in compliance with the License. You may obtain a copy -## of the License at -## }}} -## http://www.apache.org/licenses/LICENSE-2.0 -## {{{ -## Unless required by applicable law or agreed to in writing, files -## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -## License for the specific language governing permissions and limitations -## under the License. -## -################################################################################ -## -## }}} -SCOPCD := wbscope -SCOPC := $(addprefix $(SCOPCD)/,wbscopc.v) -SCOPCD := wbscope -SCOPC := $(addprefix $(SCOPCD)/,wbscopc.v) -BKRAM := memdev.v - -GENCLKD := . -GENCLK := $(addprefix $(GENCLKD)/,genclk.v xgenclk.v) -I2CDMAD := wbi2c -I2CDMA := $(addprefix $(I2CDMAD)/,wbi2cdma.v) -FAN := wbfan.v - -EMMCD := sdspi -EMMC := $(addprefix $(EMMCD)/,sdio_top.v sdio.v sdfrontend.v sdckgen.v sdwb.v sdtxframe.v sdrxframe.v) -I2CCPUD := wbi2c -I2CCPU := $(addprefix $(I2CCPUD)/,wbi2ccpu.v axisi2c.v) -SDIOD := sdspi -SDIO := $(addprefix $(SDIOD)/,sdio_top.v sdio.v sdfrontend.v sdckgen.v sdwb.v sdtxframe.v sdrxframe.v) -CONSOLED := wbuart -CONSOLE := $(addprefix $(CONSOLED)/,txuartlite.v rxuartlite.v ufifo.v) -ZIPCPUD := cpu -ZIPCPU := $(addprefix $(ZIPCPUD)/,zipsystem.v zipcore.v zipwb.v cpuops.v pfcache.v pipemem.v pfcache.v idecode.v wbpriarbiter.v zipsystem.v zipcounter.v zipjiffies.v ziptimer.v icontrol.v wbwatchdog.v zipdma_ctrl.v zipdma_fsm.v zipdma_mm2s.v zipdma_rxgears.v zipdma_s2mm.v zipdma_txgears.v zipdma.v busdelay.v) -SCOPCD := wbscope -SCOPC := $(addprefix $(SCOPCD)/,wbscopc.v) -WBUBUSD := wbubus -WBUBUS := $(addprefix $(WBUBUSD)/,wbuconsole.v wbufifo.v wbucompactlines.v wbucompress.v wbudecompress.v wbudeword.v wbuexec.v wbuidleint.v wbuinput.v wbuoutput.v wbureadcw.v wbusixchar.v wbutohex.v wbconsole.v) -ICAP := wbicapetwo.v - -GPIO := wbgpio.v - -VFLIST := main.v $(SCOPC) $(BKRAM) $(GENCLK) $(I2CDMA) $(FAN) $(EMMC) $(I2CCPU) $(SDIO) $(CONSOLE) $(ZIPCPU) $(WBUBUS) $(ICAP) $(GPIO) -AUTOVDIRS := -y wbscope -y . -y wbi2c -y sdspi -y wbuart -y cpu -y wbubus diff --git a/delete_later/rtl/memdev.v b/delete_later/rtl/memdev.v deleted file mode 100644 index 69b2535..0000000 --- a/delete_later/rtl/memdev.v +++ /dev/null @@ -1,280 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sim/rtl/memdev.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This file is really simple: it creates an on-chip memory, -// accessible via the wishbone bus, that can be used in this -// project. The memory has single cycle pipeline access, although the -// memory pipeline here still costs a cycle and there may be other cycles -// lost between the ZipCPU (or whatever is the master of the bus) and this, -// thus costing more cycles in access. Either way, operations can be -// pipelined for single cycle access on subsequent transactions. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module memdev #( - // {{{ - parameter LGMEMSZ=15, DW=32, EXTRACLOCK= 1, - parameter HEXFILE="", - parameter [0:0] OPT_ROM = 1'b0, - localparam AW = LGMEMSZ - $clog2(DW/8) - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [(AW-1):0] i_wb_addr, - input wire [(DW-1):0] i_wb_data, - input wire [(DW/8-1):0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [(DW-1):0] o_wb_data - // }}} - ); - - // Local declarations - // {{{ - wire w_wstb, w_stb; - wire [(DW-1):0] w_data; - wire [(AW-1):0] w_addr; - wire [(DW/8-1):0] w_sel; - - reg [(DW-1):0] mem [0:((1< 0) - assert(o_wb_ack); - - always @(posedge i_clk) - assert(f_outstanding <= 1); - always @(posedge i_clk) - if ((f_past_valid)&&(!i_reset)&&(i_wb_cyc)&&($past(i_wb_stb))) - assert(f_outstanding == 1); - - end endgenerate - - always @(*) - assert(!o_wb_stall); - - assign f_addr = $anyconst; - initial assume(mem[f_addr] == f_data); - - generate if (!OPT_ROM) - begin : F_MATCH_WRITES - integer ik; - - always @(posedge i_clk) - if (w_wstb && f_addr == w_addr) - for(ik=0; ik < DW/8; ik=ik+1) - if (w_sel[ik]) - f_data[ik * 8 +: 8] <= w_data[ik*8 +: 8]; - - end endgenerate - - always @(*) - assert(mem[f_addr] == f_data); - - always @(posedge i_clk) - if ((f_past_valid)&&(OPT_ROM)) - assert($stable(f_data)); - -`endif -// }}} -endmodule diff --git a/delete_later/rtl/micron.hex b/delete_later/rtl/micron.hex deleted file mode 100644 index 239d335..0000000 --- a/delete_later/rtl/micron.hex +++ /dev/null @@ -1,32 +0,0 @@ -7ff -7ff -0ff -0ff -7ff -006 -404 -081 -083 -404 -006 -404 -061 -0e7 -7ff -0ec -200 -200 -200 -200 -2a0 -200 -300 -300 -300 -300 -300 -300 -300 -300 -7ff -7ff diff --git a/delete_later/rtl/net/axinarbiter.v b/delete_later/rtl/net/axinarbiter.v deleted file mode 100644 index e701e56..0000000 --- a/delete_later/rtl/net/axinarbiter.v +++ /dev/null @@ -1,386 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: axinarbiter.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Arbitrates from among NIN packet sources to select and forward -// one of those sources forward. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module axinarbiter #( - // {{{ - parameter NIN = 4, // Number of incoming eth ports - parameter DW = 64, // Bits per clock cycle - parameter WBITS = $clog2(DW/8), - parameter [0:0] OPT_SKIDBUFFER = 1, - parameter [0:0] OPT_LOWPOWER = 0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Incoming packets from all interfaces - // {{{ - input wire [NIN-1:0] S_VALID, - output wire [NIN-1:0] S_READY, - input wire [NIN*DW-1:0] S_DATA, - input wire [NIN*WBITS-1:0] S_BYTES, - input wire [NIN-1:0] S_LAST, - input wire [NIN-1:0] S_ABORT, - // }}} - // Outgoing packet - // {{{ - output reg M_VALID, - input wire M_READY, - output reg [DW-1:0] M_DATA, - output reg [WBITS-1:0] M_BYTES, - output reg M_LAST, - output reg M_ABORT - // }}} - // }}} - ); - - // Local declarations - // {{{ - genvar gk; - integer ik; - - wire [NIN-1:0] grant; - wire [NIN-1:0] midpkt; - reg [DW-1:0] merged_data; - reg [WBITS-1:0] merged_bytes; - reg merged_last; - wire stalled; - - wire [NIN-1:0] skd_valid, skd_ready; - wire [NIN*DW-1:0] skd_data; - wire [NIN*WBITS-1:0] skd_bytes; - wire [NIN-1:0] skd_last, skd_abort; - // }}} - - pktarbiter #( - .W(NIN) - ) u_arbiter ( - // {{{ - .i_clk(i_clk), .i_reset_n(!i_reset), - .i_req(S_VALID), .i_stall(stalled), - .o_grant(grant) - // }}} - ); - - generate if (OPT_SKIDBUFFER) - begin : GEN_SKIDBUFFER - - for(gk=0; gk 0) - begin - assert(grant[gk]); - assert(midpkt[gk]); - end - - always @(*) - if (!i_reset && grant[gk]) - begin - if (M_VALID && !M_ABORT) - assert(M_LAST || fslv_word != 0); - - if (M_ABORT || (M_VALID && M_LAST)) - begin - assert(fslv_word == 0); - assert(!midpkt[gk] || (S_VALID && S_ABORT)); - end else begin - assert(midpkt[gk] == (fslv_word != 0)); - assert(fslv_word - == (fmst_word + (M_VALID ? 1:0))); - end - end - - always @(*) - if (!i_reset && S_VALID[gk]) - assume({ S_LAST[gk],S_DATA[DW*gk +: DW] } != fnvr_data); - end endgenerate - - faxin_master #( - .DATA_WIDTH(DW), .WBITS(WBITS) - ) fslv ( - // {{{ - .S_AXI_ACLK(i_clk), .S_AXI_ARESETN(!i_reset), - // - .S_AXIN_VALID(M_VALID), - .S_AXIN_READY(M_READY), - .S_AXIN_DATA(M_DATA), - .S_AXIN_BYTES(M_BYTES), - .S_AXIN_LAST(M_LAST), - .S_AXIN_ABORT(M_ABORT), - // - .f_stream_word(fmst_word), - .f_packets_rcvd(fmst_packets) - // }}} - ); - - always @(*) - if (!i_reset && grant == 0) - assert(!M_VALID && fmst_word == 0); - - always @(posedge i_clk) - if (!i_reset && $rose(M_VALID) && fmst_word == 0) - assert(!M_ABORT); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Never properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - (* anyconst *) reg fnvr_abort; - - always @(*) - if (!i_reset && fnvr_abort) - assume(0 == ((S_VALID | midpkt) & S_ABORT)); - - always @(*) - if (!i_reset && fnvr_abort) - assert(!M_ABORT); - - always @(*) - if (!i_reset && M_VALID && !M_ABORT) - assert({ M_LAST,M_DATA } != fnvr_data); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Low power checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (!i_reset && OPT_LOWPOWER && !M_VALID) - begin - assert(M_DATA == 0); - assert(M_BYTES == 0); - assert(M_LAST == 0); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - cover(!i_reset && M_VALID && M_READY && M_LAST && !M_ABORT); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Careless assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/axinbroadcast.v b/delete_later/rtl/net/axinbroadcast.v deleted file mode 100644 index dffd7b6..0000000 --- a/delete_later/rtl/net/axinbroadcast.v +++ /dev/null @@ -1,463 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: axinbroadcast.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Broadcasts a packet from a single source to NOUT destinations. -// Actual chosen destination is selectable. Does not include -// any FIFOs--those can follow if necessary. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module axinbroadcast #( - // {{{ - parameter NOUT = 4, // Number of incoming eth ports - parameter DW = 64, // Bits per clock cycle - parameter WBITS = $clog2(DW/8), - parameter [0:0] OPT_SKIDBUFFER = 0, - parameter [0:0] OPT_LOWPOWER = 0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - input wire [NOUT-1:0] i_cfg_active, - // Incoming packet interface - // {{{ - input wire S_VALID, - output wire S_READY, - input wire [DW-1:0] S_DATA, - input wire [WBITS-1:0] S_BYTES, - input wire S_LAST, - input wire S_ABORT, - // - // S_PORT tells us which port or port(s) we wish to forward - // this packet to. For true broadcasting, S_PORT should be - // all ones. For routing, S_PORT should be $onehot(). - input wire [NOUT-1:0] S_PORT, - // }}} - // Outgoing packet, forwarded to NOUT interfaces - // {{{ - output reg [NOUT-1:0] M_VALID, - input wire [NOUT-1:0] M_READY, - output reg [NOUT*DW-1:0] M_DATA, - output reg [NOUT*WBITS-1:0] M_BYTES, - output reg [NOUT-1:0] M_LAST, - output reg [NOUT-1:0] M_ABORT - // }}} - // }}} - ); - - // Local declarations - // {{{ - genvar gk; - wire skd_valid, skd_ready, - skd_last, skd_abort; - wire [DW-1:0] skd_data; - wire [WBITS-1:0] skd_bytes; - wire [NOUT-1:0] skd_port; - - reg s_midpkt; - reg [NOUT-1:0] midpkt; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Start with a skidbuffer - // {{{ - generate if (OPT_SKIDBUFFER) - begin : GEN_SKIDBUFFER - - netskid #( - .DW(NOUT+DW+WBITS) - ) u_skidbuffer ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .S_AXIN_VALID(S_VALID), .S_AXIN_READY(S_READY), - .S_AXIN_DATA({ S_PORT, S_BYTES, S_DATA }), - .S_AXIN_LAST(S_LAST), .S_AXIN_ABORT(S_ABORT), - // - .M_AXIN_VALID(skd_valid), .M_AXIN_READY(skd_ready), - .M_AXIN_DATA({ skd_port, skd_bytes, skd_data }), - .M_AXIN_LAST(skd_last), .M_AXIN_ABORT(skd_abort) - // }}} - ); - end else begin : NO_SKIDBUFFER - - assign skd_valid = S_VALID; - assign S_READY = skd_ready; - assign skd_data = S_DATA; - assign skd_bytes = S_BYTES; - assign skd_last = S_LAST; - assign skd_abort = S_ABORT; - assign skd_port = S_PORT; - - end endgenerate - - assign skd_ready = (0 == (M_VALID & ~M_READY & S_PORT)); - // }}} - - always @(posedge i_clk) - if (i_reset) - s_midpkt <= 0; - else if (skd_abort && (!skd_valid || skd_ready)) - s_midpkt <= 1'b0; - else if (skd_valid && skd_ready && !skd_abort) - s_midpkt <= !skd_last; - - //////////////////////////////////////////////////////////////////////// - // - // Generate the outputs - // {{{ - - // M_* - initial M_VALID = 0; - initial M_DATA = 0; - initial M_BYTES = 0; - initial M_LAST = 0; - initial M_ABORT = 0; - generate for(gk=0; gk 0) ? $clog2(MAX_LENGTH+1):1; - - // Pick two arbitrary values - (* anyconst *) reg [7:0] fc_first, fc_next; - wire [7:0] fm_first, fm_next; - // Pick an arbitrary position - (* anyconst *) reg [LGMX-1:0] fc_posn; - wire [LGMX-1:0] fc_nxtposn; - - (* keep *) wire [LGMX-$clog2(OW/8)-1:0] fm_first_word_cnt, fm_next_word_cnt; - (* keep *) wire [$clog2(OW/8)-1:0] fm_first_byte, fm_next_byte; - (* keep *) wire [LGMX-$clog2(IW/8)-1:0] fs_first_word_cnt, fs_next_word_cnt; - (* keep *) wire [$clog2(IW/8)-1:0] fs_first_byte, fs_next_byte; - - wire [LGMX-1:0] f_s_stream_word, f_m_stream_word; - wire [12-1:0] f_s_packets_rcvd, f_m_packets_rcvd; -`endif - - generate if (IW == OW) - begin : EQUAL - // {{{ - assign S_AXIN_READY = M_AXIN_READY; - assign M_AXIN_DATA = S_AXIN_DATA; - - always @(posedge ACLK) - if (!ARESETN) - begin - M_AXIN_VALID <= 0; - M_AXIN_LAST <= 0; - M_AXIN_BYTES <= 0; - M_AXIN_ABORT <= 0; - end else begin - M_AXIN_VALID <= S_AXIN_VALID; - M_AXIN_LAST <= S_AXIN_LAST; - M_AXIN_BYTES <= S_AXIN_BYTES; - M_AXIN_ABORT <= S_AXIN_ABORT; - end - // }}} - end else if (IW < OW) - begin : IW_SMALLER - // {{{ - // Try IW = 8, OW = 32 (You need this for verification) - // Also try IW = 32, OW = 64 (I need this for project) - // Also try IW = 64, OW = 512 (I need this for project) - // localparam SHIFT = IW; - localparam WIDE_COUNT = (OW/IW); - localparam LGWIDE_COUNT = $clog2(WIDE_COUNT); - - integer i; - reg [OW-1:0] data_concat; - reg [LGWIDE_COUNT-1:0] wide_counter; - reg mid_packet; - - initial mid_packet = 0; - always @(posedge ACLK) - if (!ARESETN) - mid_packet <= 0; - else if (S_AXIN_ABORT && !S_AXIN_VALID) - mid_packet <= 0; - else if (S_AXIN_VALID && S_AXIN_READY) - mid_packet <= !S_AXIN_LAST && !S_AXIN_ABORT; - - // M_AXIN_ABORT - initial M_AXIN_ABORT = 0; - always @(posedge ACLK) - if (!ARESETN) - M_AXIN_ABORT <= 0; - else if (M_AXIN_VALID && !M_AXIN_READY - && (M_AXIN_ABORT || (S_AXIN_ABORT && mid_packet))) - M_AXIN_ABORT <= 1; - else if (S_AXIN_ABORT && mid_packet) - M_AXIN_ABORT <= 1; - else if (!M_AXIN_VALID || M_AXIN_READY) - M_AXIN_ABORT <= 0; - - // M_AXIN_DATA, S_AXIN_READY - assign S_AXIN_READY = !M_AXIN_VALID || M_AXIN_READY || S_AXIN_ABORT; - assign M_AXIN_DATA = data_concat; - - // M_AXIN_VALID - initial M_AXIN_VALID = 0; - always @(posedge ACLK) - if (!ARESETN) - M_AXIN_VALID <= 0; - else if (!S_AXIN_ABORT && (S_AXIN_VALID && S_AXIN_READY) - // Verilator lint_off WIDTH - &&((wide_counter == WIDE_COUNT-1)||S_AXIN_LAST)) - // Verilator lint_on WIDTH - M_AXIN_VALID <= 1; - else if (M_AXIN_READY) - M_AXIN_VALID <= 0; - - // M_AXIN_BYTES, M_AXIN_LAST, wide_counter, data_concat - initial M_AXIN_BYTES = 0; - initial M_AXIN_LAST = 0; - initial wide_counter = 0; - initial data_concat = 0; - always @(posedge ACLK) - if (!ARESETN) - begin - M_AXIN_BYTES <= 0; - M_AXIN_LAST <= 0; - wide_counter <= 0; - data_concat <= 0; - end else begin - if (M_AXIN_VALID && M_AXIN_READY) - data_concat <= 0; - - if (S_AXIN_VALID && S_AXIN_READY && !S_AXIN_ABORT) - begin - M_AXIN_LAST <= S_AXIN_LAST; - - // *_VALID and *_READY can be set at the same time - // Verilator lint_off WIDTH - if (M_AXIN_VALID && M_AXIN_READY) - M_AXIN_BYTES <= S_AXIN_BYTES; - else - M_AXIN_BYTES <= M_AXIN_BYTES + S_AXIN_BYTES; - // Verilator lint_on WIDTH - - for(i=0; i < OW/IW; i=i+1) - begin - // Verilator lint_off WIDTH - if (wide_counter == i) - // Verilator lint_on WIDTH - data_concat[i*IW +: IW] - <= S_AXIN_DATA; - end - - if (!S_AXIN_LAST) - wide_counter <= wide_counter + 1; - else - wide_counter <= 0; - end else if ((M_AXIN_VALID && M_AXIN_READY) - || (!M_AXIN_VALID - && (M_AXIN_ABORT || S_AXIN_ABORT))) - begin - M_AXIN_BYTES <= 0; - M_AXIN_LAST <= 0; - wide_counter <= 0; - data_concat <= 0; - end - end - //////////////////////////////////////////////////////////////// - // - // Formal properties - // {{{ - //////////////////////////////////////////////////////////////// -`ifdef FORMAL - always @(*) - if (ARESETN) - begin - if (M_AXIN_VALID && M_AXIN_LAST) - assert(f_s_stream_word == 0); - assert(f_m_stream_word < (MAX_LENGTH / (OW/IW))); - assert(mid_packet == (f_s_stream_word != 0)); - if (!M_AXIN_LAST && !M_AXIN_ABORT) - begin - assert(f_m_stream_word <= f_s_stream_word); - assert(f_s_stream_word - == ((f_m_stream_word + (M_AXIN_VALID ? 1:0)) * WIDE_COUNT) - + wide_counter); - end - assert(!M_AXIN_LAST || M_AXIN_VALID); // ? - assert(M_AXIN_BYTES <= OW/8); - if (M_AXIN_BYTES == OW/8) - assert(M_AXIN_VALID); - if (!M_AXIN_LAST && !M_AXIN_VALID) - assert(wide_counter * IW/8 == M_AXIN_BYTES); - if (M_AXIN_VALID) - assert(wide_counter == 0); - assert(data_concat == M_AXIN_DATA); - end - - assign fm_first = M_AXIN_DATA >> (8*fc_posn[$clog2(OW/8)-1:0]); - assign fm_next = M_AXIN_DATA >> (8*fc_nxtposn[$clog2(OW/8)-1:0]); - always @(*) - if (ARESETN && !M_AXIN_ABORT - && ((f_s_stream_word > fs_first_word_cnt) - || M_AXIN_LAST) - && (f_m_stream_word * (OW/8) <= fc_posn) - && (fc_posn < (f_m_stream_word * (OW/8)) - + (wide_counter*IW/8) - + (M_AXIN_VALID ? M_AXIN_BYTES : 0))) - begin - // Assert the first data - assert(fm_first == fc_first); - end - - always @(*) - if (ARESETN && !M_AXIN_ABORT - && ((f_s_stream_word > fs_next_word_cnt) - || M_AXIN_LAST) - && (f_m_stream_word * (OW/8) <= fc_nxtposn) - && (fc_nxtposn < (f_m_stream_word * (OW/8)) - + (wide_counter*IW/8) - + (M_AXIN_VALID ? M_AXIN_BYTES : 0))) - begin - // Assert the next data - assert(fm_next == fc_next); - end - -`endif - // }}} - // }}} - end else begin : IW_GREATER - // {{{ - // Try IW=64, OW=32 (I need this for the project) - // Verilator lint_off WIDTH - localparam [$clog2(IW/8):0] FULL_OUTWORD = OW/8; - // Verilator lint_on WIDTH - - reg [IW-OW-1:0] data_parse; - reg [$clog2(IW/8):0] remaining_bytes; - reg remaining_last, mid_packet; - reg [OW-1:0] mdata; - - initial mid_packet = 0; - always @(posedge ACLK) - if (!ARESETN) - mid_packet <= 0; - else if (S_AXIN_ABORT && !S_AXIN_VALID) - mid_packet <= 0; - else if (S_AXIN_VALID && S_AXIN_READY) - mid_packet <= !S_AXIN_LAST && !S_AXIN_ABORT; - - // M_AXIN_ABORT - initial M_AXIN_ABORT = 0; - always @(posedge ACLK) - if (!ARESETN) - M_AXIN_ABORT <= 0; - else if (M_AXIN_VALID && !M_AXIN_READY - && (M_AXIN_ABORT || (S_AXIN_ABORT && mid_packet))) - M_AXIN_ABORT <= 1; - else if (S_AXIN_ABORT && mid_packet) - M_AXIN_ABORT <= 1; - else if (!M_AXIN_VALID || M_AXIN_READY) - M_AXIN_ABORT <= 0; - - // S_AXIN_READY - // We shouldn't get the data unless we convey all the - // incoming data from slave (check!) - - // Don't register s_ready !!! - assign S_AXIN_READY = S_AXIN_ABORT || (!M_AXIN_ABORT && - (!M_AXIN_VALID - || (M_AXIN_READY && remaining_bytes == 0))); - - // Which word (32-bit) should we send first ? - // Little endian => sends 0 first - always @(posedge ACLK) - if (!ARESETN) - mdata <= 0; - else if (S_AXIN_VALID && S_AXIN_READY && !S_AXIN_ABORT) - mdata <= S_AXIN_DATA[0 +: OW]; - else if (M_AXIN_VALID && M_AXIN_READY && !M_AXIN_ABORT) - mdata <= data_parse[0 +: OW]; - - assign M_AXIN_DATA = mdata; - - // M_AXIN_VALID - initial M_AXIN_VALID = 0; - always @(posedge ACLK) - if (!ARESETN) - M_AXIN_VALID <= 0; - else if (S_AXIN_VALID && S_AXIN_READY && !S_AXIN_ABORT) - M_AXIN_VALID <= 1; - else if (M_AXIN_READY && (remaining_bytes == 0 || M_AXIN_LAST || M_AXIN_ABORT)) - M_AXIN_VALID <= 0; - - // M_AXIN_BYTES, M_AXIN_LAST, data_parse, remaining_* - // {{{ - initial remaining_last = 0; - initial remaining_bytes = 0; - initial M_AXIN_BYTES = 0; - initial M_AXIN_LAST = 0; - initial data_parse = 0; - always @(posedge ACLK) - if (!ARESETN) - begin - remaining_last <= 0; - remaining_bytes <= 0; - M_AXIN_BYTES <= 0; - M_AXIN_LAST <= 0; - data_parse <= 0; - end else if (S_AXIN_VALID && S_AXIN_READY && !S_AXIN_ABORT) - begin - // Verilator lint_off WIDTH - remaining_bytes <= (S_AXIN_BYTES > FULL_OUTWORD) ? (S_AXIN_BYTES - FULL_OUTWORD) : 0; - M_AXIN_BYTES <= (S_AXIN_BYTES > FULL_OUTWORD) ? FULL_OUTWORD : S_AXIN_BYTES[$clog2(OW/8):0]; - M_AXIN_LAST <= S_AXIN_LAST && (S_AXIN_BYTES <= FULL_OUTWORD); - remaining_last <= (S_AXIN_LAST && S_AXIN_BYTES > FULL_OUTWORD); - // Verilator lint_on WIDTH - data_parse <= S_AXIN_DATA[IW-1 : OW]; - end else if (M_AXIN_ABORT && (!M_AXIN_VALID || M_AXIN_READY)) - begin - remaining_bytes <= 0; - M_AXIN_BYTES <= 0; - M_AXIN_LAST <= 0; - remaining_last <= 0; - data_parse <= 0; - end else if (M_AXIN_VALID && M_AXIN_READY) - begin - // Verilator lint_off WIDTH - remaining_bytes <= (remaining_bytes <= FULL_OUTWORD) ? 0 : (remaining_bytes - FULL_OUTWORD); - M_AXIN_BYTES <= (remaining_bytes > FULL_OUTWORD) ? FULL_OUTWORD : remaining_bytes; - M_AXIN_LAST <= (remaining_bytes > FULL_OUTWORD) ? 0 : remaining_last; - remaining_last <= (remaining_bytes <= FULL_OUTWORD) ? 0 : remaining_last; - data_parse <= data_parse >> OW; - // Verilator lint_on WIDTH - end - // }}} - - //////////////////////////////////////////////////////////////// - // - // Formal properties - // {{{ - //////////////////////////////////////////////////////////////// -`ifdef FORMAL - always @(*) - if (ARESETN) - begin - assert(FULL_OUTWORD == OW/8); - if (M_AXIN_VALID && M_AXIN_LAST) - begin - assert(f_s_stream_word == 0); - assert(remaining_bytes == 0); - end else begin - if (!M_AXIN_ABORT) - assert(mid_packet == (f_s_stream_word > 0)); - if (remaining_last) - assert(f_s_stream_word == 0); - else begin - if (!M_AXIN_ABORT) - assert((f_s_stream_word * IW/OW) == (f_m_stream_word + remaining_bytes/(OW/8) + (M_AXIN_VALID ? 1:0))); - end - end - - assert(remaining_bytes <= (IW-OW)/8); - assert(f_m_stream_word < (MAX_LENGTH * (IW/OW))); - if (M_AXIN_ABORT) - assert(!mid_packet || (S_AXIN_VALID && S_AXIN_ABORT)); - if (!M_AXIN_ABORT) - assert(mid_packet == (f_s_stream_word != 0)); - if (!mid_packet) - assert(f_s_stream_word == 0); - if (!mid_packet && !remaining_last && !M_AXIN_LAST && !M_AXIN_ABORT) - assert(f_m_stream_word == 0); - assert(f_s_stream_word <= f_m_stream_word + 1); // +1 is for first word of slave - assert(!M_AXIN_LAST || M_AXIN_VALID); // !!! - assert(M_AXIN_BYTES <= OW/8); - if (M_AXIN_BYTES == OW/8) - assert(M_AXIN_VALID); - if (remaining_bytes > 0 && !S_AXIN_ABORT) - assert(!S_AXIN_READY); - if (mid_packet) - assert(remaining_last == 0); - if(!mid_packet && !M_AXIN_VALID && !M_AXIN_ABORT) - assert(f_m_stream_word == 0); - if(!remaining_last && (OW > 8)) - assert(remaining_bytes[$clog2(OW/8)-1:0] == 0); - if (remaining_bytes > 0) - assert(M_AXIN_VALID); - if (M_AXIN_VALID && remaining_last) - assert(f_m_stream_word + 1 >= (MIN_LENGTH * (IW/OW))); - if(remaining_bytes == 0) - assert(!remaining_last); - if(M_AXIN_VALID && remaining_last) - assert(((f_m_stream_word[$clog2(IW/OW)-1 : 0] * OW/8) + (OW/8 * ((remaining_bytes + (M_AXIN_VALID ? OW/8 : 0) + (OW/8)-1) / (OW/8)))) <= (IW/8)); - end - - always @(*) - if (ARESETN && !M_AXIN_ABORT - && ((f_s_stream_word > fs_first_word_cnt) - || M_AXIN_LAST || remaining_last) - && (f_m_stream_word <= fm_first_word_cnt) - && ((fm_first_word_cnt * (OW/8)) < f_m_stream_word * (OW/8) + remaining_bytes + (M_AXIN_VALID ? OW/8 : 0))) - begin - // Assert the first data - assert(fm_first == fc_first); - end - - always @(*) - if (ARESETN && !M_AXIN_ABORT - && ((f_s_stream_word > fs_next_word_cnt) - || M_AXIN_LAST || remaining_last) - && (f_m_stream_word <= fm_next_word_cnt) - && ((fm_next_word_cnt * (OW/8)) < f_m_stream_word * (OW/8) + remaining_bytes + (M_AXIN_VALID ? OW/8 : 0))) - begin - // Assert the next data - assert(fm_next == fc_next); - end - - assign fm_first = { data_parse, M_AXIN_DATA } - >> ((8*fc_posn[$clog2(IW/8)-1:0]) - - (f_m_stream_word[$clog2(IW/OW)-1:0]*OW)); - assign fm_next = { data_parse, M_AXIN_DATA } - >> ((8*fc_nxtposn[$clog2(IW/8)-1:0]) - - (f_m_stream_word[$clog2(IW/OW)-1:0]*OW)); -`endif - // }}} - // }}} - end endgenerate - -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - - // Let the solver pick whether or not we allow aborts - (* anyconst *) reg fc_allow_aborts; - reg f_past_valid; - - initial f_past_valid = 0; - always @(posedge ACLK) - f_past_valid <= 1; - - always @(posedge ACLK) - if (!f_past_valid) - assume(!ARESETN); - - // fc_first_word_cnt, fc_next_word_cnt - // fc_first_byte, fc_next_byte - assign fs_first_word_cnt = fc_posn[$clog2(MAX_LENGTH):$clog2(IW/8)]; - assign fs_next_word_cnt = fc_nxtposn[$clog2(MAX_LENGTH):$clog2(IW/8)]; - assign fs_first_byte = (IW <= 8) ? 0 : fc_posn[$clog2(IW/8)-1:0]; - assign fs_next_byte = (IW <= 8) ? 0 : fc_nxtposn[$clog2(IW/8)-1:0]; - assign fm_first_word_cnt = fc_posn[$clog2(MAX_LENGTH):$clog2(OW/8)]; - assign fm_next_word_cnt = fc_nxtposn[$clog2(MAX_LENGTH):$clog2(OW/8)]; - assign fm_first_byte = (OW <= 8) ? 0 : fc_posn[$clog2(OW/8)-1:0]; - assign fm_next_byte = (OW <= 8) ? 0 : fc_nxtposn[$clog2(OW/8)-1:0]; - - // fc_nxtposn - assign fc_nxtposn = fc_posn + 1; - always @(*) - assume(fc_nxtposn != 0); - - //////////////////////////////////////////////////////////////////////// - // - // Slave stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // assume properties of the inputs - - // faxin_slave - // {{{ - faxin_slave #( - .DATA_WIDTH(IW), - .MIN_LENGTH(MIN_LENGTH_I), - .MAX_LENGTH(MAX_LENGTH_I), - .LGMX(LGMX), - .WBITS($clog2(IW+1)) - ) fslave ( - .S_AXI_ACLK(ACLK), .S_AXI_ARESETN(ARESETN), - .S_AXIN_VALID(S_AXIN_VALID), - .S_AXIN_READY(S_AXIN_READY), - .S_AXIN_DATA(S_AXIN_DATA), - .S_AXIN_BYTES(S_AXIN_BYTES), - .S_AXIN_LAST(S_AXIN_LAST), - .S_AXIN_ABORT(S_AXIN_ABORT), - .f_stream_word(f_s_stream_word), - .f_packets_rcvd(f_s_packets_rcvd) - ); - // }}} - - // S_AXIN_BYTES - // {{{ - always @(*) - if (ARESETN && S_AXIN_VALID) - begin - assume(S_AXIN_BYTES > 0); - assume(S_AXIN_BYTES <= IW/8); - if (!S_AXIN_LAST) - assume(S_AXIN_BYTES == (IW/8)); - end - // }}} - - // MIN_LENGTH & S_AXIN_LAST - // {{{ - always @(*) - if (f_s_stream_word < MIN_LENGTH) - assume(!S_AXIN_LAST); - // }}} - - // S_AXIN_ABORT - always @(*) - if (ARESETN && !fc_allow_aborts) - assume(!S_AXIN_ABORT); - - always @(*) - if (ARESETN && S_AXIN_VALID && f_s_stream_word == fs_first_word_cnt) - begin - // Assume the first data - if (IW == 8) - begin - assume(S_AXIN_DATA == fc_first); - end else begin - assume(S_AXIN_DATA[fs_first_byte*8 +: 8] == fc_first); - end - end - - always @(*) - if (ARESETN && S_AXIN_VALID && f_s_stream_word == fs_next_word_cnt) - begin - // Assume the next data - if (IW == 8) - begin - assume(S_AXIN_DATA == fc_next); - end else begin - assume(S_AXIN_DATA[fs_next_byte*8 +: 8] == fc_next); - end - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Master stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // assert properties of the outputs - - // faxin_master - faxin_master #( - .DATA_WIDTH(OW), - .MIN_LENGTH(MIN_LENGTH_O), - .MAX_LENGTH(MAX_LENGTH_O), - .LGMX(LGMX), - .WBITS($clog2(OW+1)) - ) fmaster ( - .S_AXI_ACLK(ACLK), .S_AXI_ARESETN(ARESETN), - .S_AXIN_VALID(M_AXIN_VALID), - .S_AXIN_READY(M_AXIN_READY), - .S_AXIN_DATA(M_AXIN_DATA), - .S_AXIN_BYTES(M_AXIN_BYTES), - .S_AXIN_LAST(M_AXIN_LAST), - .S_AXIN_ABORT(M_AXIN_ABORT), - .f_stream_word(f_m_stream_word), - .f_packets_rcvd(f_m_packets_rcvd) - ); - - // M_AXIN_ABORT - always @(*) - if (ARESETN && !fc_allow_aborts) - assert(!M_AXIN_ABORT); - - always @(*) - if (ARESETN && M_AXIN_ABORT) - assert(f_s_stream_word == 0); - - always @(*) - if (ARESETN && !M_AXIN_ABORT && ((f_s_stream_word > fs_first_word_cnt) || M_AXIN_LAST) - && (f_m_stream_word * (OW/8) <= fc_posn) - && (fc_posn < (f_m_stream_word * (OW/8)) + (M_AXIN_VALID ? M_AXIN_BYTES : 0))) - begin - // Assert the first data - assert(fm_first == fc_first); - end - - always @(*) - if (ARESETN && !M_AXIN_ABORT - && ((f_s_stream_word > fs_next_word_cnt) - || M_AXIN_LAST) - && (f_m_stream_word * (OW/8) <= fc_nxtposn) - && (fc_nxtposn < (f_m_stream_word * (OW/8)) + (M_AXIN_VALID ? M_AXIN_BYTES : 0))) - begin - // Assert the next data - assert(fm_next == fc_next); - end - - // M_AXIN_BYTES - // {{{ - always @(*) - if (M_AXIN_VALID) - begin - assert(M_AXIN_BYTES > 0); - assert(M_AXIN_BYTES <= OW/8); - if (!M_AXIN_LAST) - assert(M_AXIN_BYTES == OW/8); - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Low power rules (if we wish to use them) - // {{{ - //////////////////////////////////////////////////////////////////////// - - /* - // Power is used every time a register toggles - // So, if OPT_LOWPOWER is set -- we keep registers from toggling - // (by pinning them to zero) - always @(*) - if (OPT_LOWPOWER && !M_AXIN_VALID) - begin - // Can't assert these first two, since you are building - // in M_AXIN_DATA while !M_AXIN_VALID, so we won't assert - // these at all. - // - // assert(M_AXIN_DATA == 0); - // assert(M_AXIN_BYTES == 0); - // - - if (WIDE_COUNT == 0) - assert(M_AXIN_DATA == 0); - - assert(M_AXIN_LAST == 0); - end - - always @(*) - if (OPT_LOWPOWER && M_AXIN_VALID) - begin - for(i=0; i= M_AXIN_BYTES) - assert(M_AXIN_DATA[8*i +: 8] == 0); - end - */ - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/crc_axin.v b/delete_later/rtl/net/crc_axin.v deleted file mode 100644 index 50738da..0000000 --- a/delete_later/rtl/net/crc_axin.v +++ /dev/null @@ -1,503 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: crc_axin.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Checks incoming packets for valid CRCs. Any incoming packet -// arriving with a bad CRC should be ABORTed on or before the LAST -// signal--in this case, concurrent with the LAST signal. (The ABORT -// signal will need to be raised coincident with the final outgoing LAST -// signal, so subsequent components know not to store the packet into -// memory, or to forward it through the network.) -// -// Creator: Sukru Uzun. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module crc_axin #( - // {{{ - parameter DATA_WIDTH = 64, - parameter [0:0] OPT_SKIDBUFFER = 1'b0, - parameter [0:0] OPT_LOWPOWER = 1'b0, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b1 - // }}} - ) ( - // {{{ - // clk and low reset - input wire ACLK, ARESETN, - // calculate crc if enable - input wire i_cfg_en, - - // S_AXIN_*: Incoming data - // {{{ - input wire S_AXIN_VALID, - output wire S_AXIN_READY, - input wire [DATA_WIDTH-1:0] S_AXIN_DATA, - // Byte counter - input wire [$clog2(DATA_WIDTH/8):0] S_AXIN_BYTES, - // Indicates boundary of last packet - input wire S_AXIN_LAST, - input wire S_AXIN_ABORT, - // }}} - - // M_AXIN_*: Outgoing data - output reg M_AXIN_VALID, - input wire M_AXIN_READY, - output reg [DATA_WIDTH-1:0] M_AXIN_DATA, - output reg [$clog2(DATA_WIDTH/8):0] M_AXIN_BYTES, - // Indicates boundary of last packet - output reg M_AXIN_LAST, - output reg M_AXIN_ABORT - // }}} - ); - - // Local declarations - // {{{ - localparam DW = DATA_WIDTH; - localparam CRC_BITS = 32; - localparam [CRC_BITS-1:0] POLY = 32'hedb88320; // 04C11DB7; - localparam [CRC_BITS-1:0] INIT = 32'hFFFFFFFF; - localparam [CRC_BITS-1:0] XOR_OUT = 32'hFFFFFFFF; - localparam INDEX_OFFSET = (DW - CRC_BITS)/8; - - genvar gk; - integer ik; - - // All declarations go at the top ... - reg [CRC_BITS-1:0] crc32 [0:(DW/8)-1]; - reg [CRC_BITS-1:0] next_crc [0:(DW/8)-1]; - - wire skd_valid, skd_ready, - skd_last, skd_abort; - wire [DW-1:0] skd_data; - wire [$clog2(DW/8):0] skd_bytes; - - wire [$clog2(DW/8):0] crc_index; - wire [CRC_BITS-1:0] crc_value; - reg [DW-1:0] last_axin_data; - wire [2*DW-1:0] wide_word, end_word; - - // }}} - - // swap endianness - function [DW-1:0] SWAP_ENDIANNESS(input [DW-1:0] data); - // {{{ - integer s; - reg [DW-1:0] tmp; - begin - if(OPT_LITTLE_ENDIAN) - SWAP_ENDIANNESS = data; - else begin - tmp = 0; - for(s=0; s> ((skd_bytes + INDEX_OFFSET[$clog2(DW/8):0]) * 8); - // }}} - - // M_AXIN_ABORT - // {{{ - assign crc_index = (skd_bytes - 1) + { 1'b0, INDEX_OFFSET[$clog2(DW/8)-1:0] }; - assign crc_value = (skd_bytes <= CRC_BITS[$clog2(DW):$clog2(DW/8)]) ? - crc32[crc_index[$clog2(DW/8)-1:0]] ^ XOR_OUT : - next_crc[crc_index[$clog2(DW/8)-1:0]] ^ XOR_OUT; - initial M_AXIN_ABORT = 0; - always @(posedge ACLK) - if (!ARESETN) begin - M_AXIN_ABORT <= 0; - end else if (skd_abort && (!M_AXIN_VALID || !M_AXIN_LAST)) - begin - // Abort if the incoming signal aborts - // This will likely happen if skd_abort drops mid-packet - // But ... don't abort the packet once - // M_AXIN_VALID && M_AXIN_LAST are set. - M_AXIN_ABORT <= 1'b1; - end else if (i_cfg_en && skd_valid && skd_ready && !M_AXIN_ABORT) - begin - if (skd_last) // Should we check M_AXIN_LAST - M_AXIN_ABORT <= (crc_value != end_word[CRC_BITS-1:0]); - end else if (M_AXIN_READY || !M_AXIN_VALID) - M_AXIN_ABORT <= 1'b0; - // }}} - - // Keep Verilator -Wall happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, end_word[2*DW-1:CRC_BITS], crc_index[$clog2(DW/8)] }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -// -`ifdef FORMAL -// Verification -// 1. When using SBY, ... -// -- Only this file, faxin_slave, and faxin_master are needed -// (initially) -// -- Data can be anything--it might have a good CRC, it might not -// -- This will find/fix any signaling errors, but do nothing for CRC -// validation. (You have signaling errors still ...) -// -// 2. SBY step #2 ... -// -- You could use an external environment to generate a good CRC, and -// then *prove* that M_AXIN_ABORT does not get set. -// -- You'd then need something to create a packet for you. addecrc -// could help. -// - *ALTERNATIVELY* you could use rxecrc to process a packet side by -// side with crc_axin. -// -- If rxecrc doesn't fail, then prove crc_axin doesn't fail either -// -- If rxecrc succeeds, then prove crc_axin succeeds as well -// -// 3. Simulation -// -- Could still use addecrc. Would need to ... -// 1. Pick a random packet length -// Be sure to pick one with all remainders mod 8 -// i.e. 64-bytes, 65bytes, 66, 67, but 68 would be a repeat -// 2. Randomly decide if you will (or won't) abort the packet -// 3. Use addecrc to generate a packet, 8'bits at a time -// 4. Combine those 8'bits to 32'bits, for crc_axin's input -// 5. Verify that crc_axin doesn't abort -// -- This would help to verify that the CRC works -// -- Would do nothing to verify signaling -// -- Depending on how set up, might or might not verify CRC failures -// are properly flagged. -// - // These parameters are only used when we do our formal proof - parameter F_MIN_LENGTH = (8*8)/DW; - parameter F_MAX_LENGTH = (512*8)/DW; - localparam LGMX = (F_MAX_LENGTH > 0) ? $clog2(F_MAX_LENGTH+1):1; - - reg f_past_valid; - (* anyconst *) reg f_no_abort, f_never_abort_slave; - - wire F_SLAVE_ARESETN; - reg [LGMX-1:0] f_s_stream_word, f_m_stream_word; - reg [12-1:0] f_s_packets_rcvd, f_m_packets_rcvd; - - initial f_past_valid = 0; - always @(posedge ACLK) - f_past_valid = 1; - - always @(posedge ACLK) - if (!f_past_valid) - assume(!ARESETN); - - always @(posedge ACLK) - if (f_never_abort_slave) - assume(!S_AXIN_ABORT); - - //////////////////////////////////////////////////////////////////////// - // Slave stream properties - //////////////////////////////////////////////////////////////////////// - - // assign F_SLAVE_ARESETN = ARESETN || !M_AXIN_ABORT; - - faxin_slave #( - .DATA_WIDTH(DATA_WIDTH), - .MIN_LENGTH(F_MIN_LENGTH), - .MAX_LENGTH(F_MAX_LENGTH), - .WBITS($clog2(DATA_WIDTH/8)+1) - ) fslave ( - .S_AXI_ACLK(ACLK), .S_AXI_ARESETN(ARESETN), - .S_AXIN_VALID(S_AXIN_VALID), - .S_AXIN_READY(S_AXIN_READY), - .S_AXIN_DATA(S_AXIN_DATA), - .S_AXIN_BYTES(S_AXIN_BYTES), - .S_AXIN_LAST(S_AXIN_LAST), - .S_AXIN_ABORT(S_AXIN_ABORT), - .f_stream_word(f_s_stream_word), - .f_packets_rcvd(f_s_packets_rcvd) - ); - - // S_AXIN_BYTES - // {{{ - always @(*) - if (ARESETN && S_AXIN_VALID) - begin - assume(S_AXIN_BYTES > 0); - assume(S_AXIN_BYTES <= (DW/8)); - if (!S_AXIN_LAST) - assume(S_AXIN_BYTES == (DW/8)); - end - // }}} - - // F_MIN_LENGTH & S_AXIN_LAST - // {{{ - always @(*) - if (f_s_stream_word < F_MIN_LENGTH) - assume(!S_AXIN_LAST); - // }}} - - always @(*) - if (f_no_abort) - begin - assume(!S_AXIN_ABORT && !i_cfg_en); - end - - //////////////////////////////////////////////////////////////////////// - // Master stream properties - //////////////////////////////////////////////////////////////////////// - - faxin_master #( - .DATA_WIDTH(DATA_WIDTH), - .MIN_LENGTH(F_MIN_LENGTH), - .MAX_LENGTH(F_MAX_LENGTH), - .WBITS($clog2(DATA_WIDTH/8)+1) - ) fmaster ( - .S_AXI_ACLK(ACLK), .S_AXI_ARESETN(ARESETN), - .S_AXIN_VALID(M_AXIN_VALID), - .S_AXIN_READY(M_AXIN_READY), - .S_AXIN_DATA(M_AXIN_DATA), - .S_AXIN_BYTES(M_AXIN_BYTES), - .S_AXIN_LAST(M_AXIN_LAST), - .S_AXIN_ABORT(M_AXIN_ABORT), - .f_stream_word(f_m_stream_word), - .f_packets_rcvd(f_m_packets_rcvd) - ); - - // M_AXIN_BYTES - // {{{ - always @(*) - if (M_AXIN_VALID) - begin - assert(M_AXIN_BYTES > 0); - assert(M_AXIN_BYTES <= DW/8); - if (!M_AXIN_LAST) - assert(M_AXIN_BYTES == DW/8); - end - // }}} - - integer i; - always @(posedge ACLK) - if (ARESETN) - begin - if (M_AXIN_VALID && M_AXIN_LAST) begin - for(i=0; i < DW/8; i=i+1) begin - assert(crc32[i] == INIT); - end - end - end - - always @(*) begin - if (f_never_abort_slave) - assert((M_AXIN_VALID && M_AXIN_LAST) || !M_AXIN_ABORT); - if (f_no_abort) - assert(!M_AXIN_ABORT); - end - - always @(*) - if (ARESETN) begin - if (f_s_stream_word == 0) - assert ((!M_AXIN_VALID && f_m_stream_word == 0) || (M_AXIN_VALID && M_AXIN_LAST) || M_AXIN_ABORT); - if (f_s_stream_word != 0 && !M_AXIN_ABORT) begin - assert(f_s_stream_word == f_m_stream_word + (M_AXIN_VALID ? 1 : 0)); - end - if (M_AXIN_ABORT || M_AXIN_LAST) - assert((f_s_stream_word == 0) || S_AXIN_ABORT); - if (M_AXIN_VALID && M_AXIN_LAST) begin - assert(f_s_stream_word == 0); - end - end - - // Cover - // {{{ - always @(*) begin - cover(f_never_abort_slave && M_AXIN_VALID && M_AXIN_LAST && !M_AXIN_ABORT); - cover(f_never_abort_slave && M_AXIN_VALID && M_AXIN_LAST && M_AXIN_ABORT); - cover(f_never_abort_slave && M_AXIN_VALID && M_AXIN_LAST && f_m_stream_word == 16); - end - // }}} - - // "Careless" assumptions - // {{{ - // always @(*) - // assume(!S_AXIN_ABORT); - // }}} - -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/dropshort.v b/delete_later/rtl/net/dropshort.v deleted file mode 100644 index 43c715e..0000000 --- a/delete_later/rtl/net/dropshort.v +++ /dev/null @@ -1,335 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: dropshort.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Drops short packets by raising the ABORT flag if LAST arrives -// too early. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module dropshort #( - // {{{ - parameter DW=32, // Bits per beat - parameter [0:0] OPT_LOWPOWER = 0, - parameter MINBYTES = 64 - // }}} - ) ( - // {{{ - input wire S_CLK, S_ARESETN, - // - // Incoming packet data - // {{{ - input wire S_VALID, - output wire S_READY, - input wire [DW-1:0] S_DATA, - input wire [$clog2(DW/8)-1:0] S_BYTES, - input wire S_ABORT, - input wire S_LAST, - // }}} - // Outgoing packet data - // {{{ - output reg M_VALID, - input wire M_READY, - output reg [DW-1:0] M_DATA, - output reg [$clog2(DW/8)-1:0] M_BYTES, - output reg M_ABORT, - output reg M_LAST - // }}} - // }}} - ); - - localparam LENBITS = $clog2(MINBYTES+1)+1, - MSB = LENBITS-1, - BW = $clog2(DW/8); - reg [MSB:0] pktlen; - reg midpacket; - reg [$clog2(DW/8):0] i_bytes; - - // pktlen - // {{{ - always @(posedge S_CLK) - if (!S_ARESETN) - pktlen <= 0; - else if (S_ABORT && (!S_VALID || S_READY)) - pktlen <= 0; - else if (S_VALID && S_READY) - begin - if (S_LAST) - pktlen <= 0; - else if (!pktlen[MSB]) - pktlen <= pktlen + 1; - end - // }}} - - // midpacket - // {{{ - always @(posedge S_CLK) - if (!S_ARESETN) - midpacket <= 0; - else if (S_ABORT && (!S_VALID || S_READY)) - midpacket <= 0; - else if (S_VALID && S_READY) - begin - if (S_LAST) - midpacket <= 0; - else - midpacket <= 1; - end - // }}} - - // i_bytes - // {{{ - always @(*) - if (S_BYTES[$clog2(DW/8)-1] == 0) - i_bytes = { 1'b1, {($clog2(DW/8)){1'b0}} }; - else - i_bytes = { 1'b0, S_BYTES }; - // }}} - - // M_VALID - // {{{ - initial M_VALID = 1'b0; - always @(posedge S_CLK) - if (!S_ARESETN) - M_VALID <= 0; - else if (!M_VALID || M_READY) - M_VALID <= S_VALID && !S_ABORT; - // }}} - - // M_DATA, M_BYTES, M_LAST - // {{{ - always @(posedge S_CLK) - if (OPT_LOWPOWER && !S_ARESETN) - { M_DATA, M_BYTES, M_LAST } <= 0; - else if (!M_VALID || M_READY) - begin - M_DATA <= S_DATA; - M_BYTES <= S_BYTES; - M_LAST <= S_LAST; - if (OPT_LOWPOWER && (!S_VALID || S_ABORT)) - { M_DATA, M_BYTES, M_LAST } <= 0; - end - // }}} - - // M_ABORT - // {{{ - initial M_ABORT = 1'b0; - always @(posedge S_CLK) - if (!S_ARESETN) - M_ABORT <= 0; - else if (S_ABORT && midpacket && (!M_VALID || !M_LAST)) - M_ABORT <= 1; - else if (!M_VALID || M_READY) - begin - M_ABORT <= 0; - // Verilator lint_off WIDTH - if (S_VALID && S_READY && S_LAST && !pktlen[MSB]) - M_ABORT <= ({ pktlen,{(BW){1'b0}} } + i_bytes - < MINBYTES); - // Verilator lint_on WIDTH - end - // }}} - - assign S_READY = (!M_VALID || M_READY); - -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - wire [12-1:0] fslv_packets, fmst_packets; - wire [11-1:0] fslv_word, fmst_word; - (* anyconst *) reg [DW:0] fnvr_data; - (* anyconst *) reg f_nvr_abort; - - //////////////////////////////////////////////////////////////////////// - // - // Interface checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - faxin_slave #( - .DATA_WIDTH(DW), - .MIN_LENGTH(0) - ) fslv ( - // {{{ - .S_AXI_ACLK(S_CLK), .S_AXI_ARESETN(S_ARESETN), - .S_AXIN_VALID(S_VALID), - .S_AXIN_READY(S_READY), - .S_AXIN_DATA(S_DATA), - .S_AXIN_BYTES(S_BYTES), - .S_AXIN_LAST(S_LAST), - .S_AXIN_ABORT(S_ABORT), - .f_stream_word(fslv_word), - .f_packets_rcvd(fslv_packets) - // }}} - ); - - faxin_master #( - .DATA_WIDTH(DW), - .MIN_LENGTH(0) - ) fmst ( - // {{{ - .S_AXI_ACLK(S_CLK), .S_AXI_ARESETN(S_ARESETN), - .S_AXIN_VALID(M_VALID), - .S_AXIN_READY(M_READY), - .S_AXIN_DATA(M_DATA), - .S_AXIN_BYTES(M_BYTES), - .S_AXIN_LAST(M_LAST), - .S_AXIN_ABORT(M_ABORT), - .f_stream_word(fmst_word), - .f_packets_rcvd(fmst_packets) - // }}} - ); - - always @(*) - if (S_ARESETN && !M_ABORT && (!M_VALID || !M_LAST)) - begin - assert(fslv_word == fmst_word + (M_VALID ? 1:0)); - end - - always @(*) - if (S_ARESETN) - begin - if (M_ABORT || (M_VALID && M_LAST)) - begin - assert(fslv_word == 0); - if (!S_VALID || !S_ABORT) - assert(!midpacket); - end else if (M_VALID) - begin - assert(fslv_word > 0); - assert(midpacket); - end - - if (!pktlen[MSB]) - begin - assert(M_ABORT || pktlen == fslv_word); - end else begin - assert(M_ABORT || pktlen <= fslv_word); - end - - assert(midpacket == (pktlen != 0)); - end - - always @(*) - if (S_VALID && !S_ABORT) - assume({ S_LAST, S_DATA } != fnvr_data); - - always @(*) - if (S_ARESETN && M_VALID && !M_ABORT) - assert({ M_LAST, M_DATA } != fnvr_data); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Never abort checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - always @(*) - if (f_nvr_abort) - assume(!midpacket || !S_ABORT); - - always @(*) - if (S_ARESETN && f_nvr_abort) - assume(!S_VALID || !S_LAST || (S_BYTES + pktlen >= MINBYTES)); - - always @(*) - if (S_ARESETN && f_nvr_abort) - assert(!M_ABORT); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Lowpower checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (S_ARESETN && OPT_LOWPOWER && !M_VALID) - begin - assert(M_DATA == 0); - assert(M_BYTES == 0); - assert(M_LAST == 0); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - always @(*) - if (S_ARESETN) - begin - cover(M_ABORT); - cover(M_ABORT && M_VALID); - cover(M_ABORT && !M_VALID); - cover(M_VALID && M_LAST && M_READY); - end - - always @(posedge S_CLK) - if (S_ARESETN) - begin - cover($rose(M_ABORT) && !$past(S_ABORT)); - cover($rose(M_ABORT) && $past(S_ABORT && !S_LAST)); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" (?) assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - begin - assume(fmst_packets < 12'h3fe); - assume(!fslv_word[10]); - end - - // }}} -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/net/mem2pkt.v b/delete_later/rtl/net/mem2pkt.v deleted file mode 100644 index e1c524e..0000000 --- a/delete_later/rtl/net/mem2pkt.v +++ /dev/null @@ -1,1492 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: mem2pkt.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This module is designed to allow a CPU to send packets from -// a circular buffer region in memory. To use: -// -// 1. Allocate a region in memory. Make sure the base address and the -// size of the region are both word aligned. -// 2. Write this base address and memory size to the controller, followed -// by a "write address" equal to the base address (at first). -// 3. The memory size available is given by the write address minus the -// read address, modulo the memory size. -// -// if (write_address > read_address) -// space_available = write_address - read_address; -// else -// space_available = memsize + write_address - read_address -// -// 4. If there's no space available, you can poll the device and wait for -// sufficient space to become available, or wait for an interrupt. -// On an interrupt, the entire memory should be available. -// -// 5. Once you have sufficient memory to send a packet plus its length, -// write the packet to memory and determine its length: -// -// if (space_available > size(word) + packet_length) -// pkt_length = generate_packet(write_address); -// -// 6. Follow the packet with a null pointer -// -// writeptr[pkt_length / sizeof(word)] = 0 -// -// 7. Write the packet length to memory -// -// *writeptr = pkt_length -// -// 8. Go back to step 3 and repeat. -// -// An error will be generated if the DMA attempts to access an invalid -// memory region. The module will then stop and wait for its memory -// region to be updated. Once a valid region is given to it, packets -// may start flowing into memory again. -// -// Either a base address of zero or a memory size of zero will disable -// the module. -// -// If circular addressing is too cumbersome, you can always: -// 1. Wait for the readptr to equal the writeptr. The interrupt will be -// set at this time, so you can also wait for an interrupt. -// 2. Set memsize to zero -// 3. Set the write pointer to the base address -// 4. Restore memsize -// .. and then start working from the base pointer again. -// -// Registers: -// 0: Base address -// Will be rounded up to the nearest word -// A base address of zero will turn the packet DMA off -// 4: {ERR, Memory size } -// Will be rounded down to the nearest word size -// A size of zero will turn the packet DMA off -// A Wishbone (bus) error will also turn the packet DMA -// off. Errors may be cleared and the DMA restarted by -// writing a new base address or size. -// 8: Write pointer (Read/write, controlled by the CPU) -// 12: Read pointer (Read/write, controlled by CPU) -// Set to zero on error or when idle. At all other times, -// the read pointer will be somewhere between the base -// address and the base address plus the allocated memory -// size. -// -// All addresses must be word aligned--not 32b aligned, but word aligned -// to whatever the bus size is. To discover word alignment, write an -// unaligned word, and see what alignment it is given. -// -// Status: -// Has not (yet) been attempted in simulation or hardware. Has also just -// been rewritten for a pkt data width greater than 32 bits. -// -// QUESTION: What will happen if the user adjusts the write pointer so that -// it is inside the (current) read packet? Will this be caught? -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module mem2pkt #( - // {{{ - parameter DW = 512, - parameter AW = 31-$clog2(DW/8), - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter LGFIFO = 7, - parameter PKTDW = 128, - parameter BURSTSZ = (1<<(LGFIFO-1)) // In bus words - // parameter [0:0] OPT_ABORT_ON_EMPTY = 1'b1, - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Incoming bus (slave) control interface - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [1:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - // - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // }}} - // Outgoing bus (master) DMA interface - // {{{ - output reg o_dma_cyc, - output reg o_dma_stb, - output wire o_dma_we, - output reg [AW-1:0] o_dma_addr, - output wire [DW-1:0] o_dma_data, - output wire [DW/8-1:0] o_dma_sel, - input wire i_dma_stall, - input wire i_dma_ack, - input wire [DW-1:0] i_dma_data, - input wire i_dma_err, - // }}} - // Outgoing packets - // {{{ - output wire M_AXIN_VALID, - input wire M_AXIN_READY, - output wire [PKTDW-1:0] M_AXIN_DATA, - output wire [$clog2(PKTDW/8)-1:0] M_AXIN_BYTES, - output wire M_AXIN_LAST, - output wire M_AXIN_ABORT, - // }}} - output reg o_int - // }}} - ); - - // Local declarations - // {{{ - localparam [2:0] S_IDLE = 3'b000, - S_LENGTH = 3'b001, - S_PKTACTIVE = 3'b010, - S_PKTPAUSED = 3'b011, - S_RUNDOWN = 3'b100; - - localparam [1:0] ADR_BASEADDR = 2'b00, - ADR_SIZE = 2'b01, - ADR_WRITEPTR = 2'b10, - ADR_READPTR = 2'b11; - - localparam BLSB = $clog2(DW/8), // Bus LSB - LSB = $clog2(DW/32), // Bits between BLSB & 32b words - WBLSB=2, - FULL_LOAD = DW/PKTDW; - - wire [AW-1:0] i_bus_addr; - wire [AW+LSB-1:0] i_word_addr; - wire [AW+BLSB-1:0] full_baseaddr, - full_writeptr, full_readptr; - wire [AW+BLSB:0] full_lastaddr; - wire [AW-1:0] bus_readptr; // bus_writeptr; - - - reg r_err, r_dma_reset, r_validptr; - reg [AW-1:0] r_baseaddr, r_memsize, next_dma_addr; - reg [AW+LSB-1:0] r_writeptr, r_readptr; - reg [AW+LSB:0] next_rdptr, w_next_rdptr; - reg [AW:0] r_lastaddr; - - wire w_dma_abort; - reg dma_abort; - - reg [LGFIFO:0] wb_outstanding; - - reg [2:0] rd_state; - - wire sfifo_reset; - wire sfifo_read, sfifo_full, sfifo_empty; - wire [DW-1:0] sfifo_data; - wire [LGFIFO:0] sfifo_fill; - - reg [LGFIFO:0] fifo_committed; - - reg [AW-1:0] pkt_words; - - reg [AW+BLSB-1:0] space_committed; - reg [31:0] i_dma_pktlen; - reg [DW-1:0] wide_pktlen; - wire w_invalid_packet; - - reg [AW-1:0] w_pkt_words; - - reg pkd_valid, pkd_last; - wire pkd_ready; - reg [$clog2(DW/PKTDW):0] pkd_load; - reg [AW+BLSB-1:0] pkd_len, pkd_remaining; - reg [$clog2(PKTDW/8)-1:0] pkd_bytes; - reg [DW-1:0] pkd_wide; - wire [PKTDW-1:0] pkd_data; - - reg release_packet; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone control handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // r_dma_reset, r_baseaddr, r_memsize, r_lastaddr, r_err, r_writeptr - // {{{ - assign i_bus_addr = i_wb_data[AW+BLSB-1:BLSB]; - assign i_word_addr = i_wb_data[AW+BLSB-1:WBLSB]; - - assign full_baseaddr = { r_baseaddr, {(BLSB){1'b0}} }; - assign full_lastaddr = { r_lastaddr, {(BLSB){1'b0}} }; - assign full_writeptr = { r_writeptr, {(WBLSB){1'b0}} }; - assign full_readptr = { r_readptr, {(WBLSB){1'b0}} }; - // assign bus_writeptr = full_writeptr[AW+BLSB-1:BLSB]; - assign bus_readptr = full_readptr[AW+BLSB-1:BLSB]; - - initial r_dma_reset = 1; - initial r_baseaddr = 0; - initial r_memsize = 0; - initial r_lastaddr = 0; - initial r_validptr = 0; - always @(posedge i_clk) - begin - r_dma_reset <= r_err || (r_baseaddr == 0)||(r_memsize == 0); - if (full_writeptr < full_baseaddr) - r_dma_reset <= 1'b1; - if ({ 1'b0, full_writeptr } >= full_lastaddr) - r_dma_reset <= 1'b1; - if (r_lastaddr > (1<= r_baseaddr) - && ({ 1'b0, r_writeptr[AW+LSB-1:LSB] } < r_lastaddr); - - if (i_wb_stb && i_wb_we) - begin - case(i_wb_addr) - ADR_BASEADDR: begin - // {{{ - if (i_wb_sel == 4'hf) - begin - r_baseaddr <= i_bus_addr; - r_lastaddr <= i_bus_addr - + r_memsize; - end else if (i_wb_sel != 0) - begin - r_baseaddr <= 0; - r_lastaddr <= { 1'b0, r_memsize }; - end - r_dma_reset <= 1'b1; - r_err <= 0; - end - // }}} - ADR_SIZE: begin - // {{{ - if (i_wb_sel == 4'hf) - begin - r_memsize <= i_bus_addr; - r_lastaddr <= r_baseaddr + i_bus_addr; - end else if (i_wb_sel != 0) - begin - r_memsize <= 0; - r_lastaddr <= { 1'b0, r_baseaddr }; - end - r_dma_reset <= 1'b1; - r_err <= 0; - end - // }}} - ADR_WRITEPTR: begin - // {{{ - // Word accesses, round down to nearest word - if (i_wb_sel == 4'hf) - begin - r_writeptr <= i_word_addr; - r_validptr <= (i_bus_addr >= r_baseaddr) - && ({ 1'b0, i_bus_addr } < r_lastaddr); - end end - // }}} - ADR_READPTR: begin end // Read only register - endcase - end - - if (o_dma_cyc && i_dma_err) - r_err <= 1'b1; - - if (release_packet && (r_dma_reset || dma_abort)) - r_dma_reset <= 1'b1; - - if (i_reset) - begin - // {{{ - r_dma_reset <= 1'b1; - r_baseaddr <= 0; - r_memsize <= 0; - r_lastaddr <= 0; - r_err <= 0; - r_validptr <= 0; - // }}} - end - end - // }}} - - // o_wb_data - // {{{ - initial o_wb_data = 0; - always @(posedge i_clk) - if (i_wb_stb && !i_wb_we) - begin - o_wb_data <= 0; - case(i_wb_addr) - ADR_BASEADDR: o_wb_data[AW+BLSB-1:BLSB] <= r_baseaddr; - ADR_SIZE: begin - o_wb_data[31] <= r_err; - o_wb_data[AW+BLSB-1:BLSB] <= r_memsize; - end - ADR_WRITEPTR: o_wb_data[AW+BLSB-1:WBLSB] <= r_writeptr; - ADR_READPTR: o_wb_data[AW+BLSB-1:WBLSB] <= r_readptr; - endcase - end - // }}} - - assign o_wb_stall = 1'b0; - - // o_wb_ack - // {{{ - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_ack <= 1'b0; - else - o_wb_ack <= i_wb_stb && !o_wb_stall; - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Read packets from memory into our local buffer - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // 1. Issue a single read, get packet length - // 2. If packet length is believable, start decomposing the packet - // No further reads issue until this read returns - // 3. Issue additional reads, up to the full packet length - // Issue burst of (half FIFO length) reads, whenever the FIFO - // (+ outstanding) is less than half full, and the full packet - // has no (yet) been read. - // - // First burst will be of the whole FIFO length (up to the - // packet length). - // 4. Read results go into a FIFO - // 5. FIFO reads go into the decomposition circuit, breaking packets - // into 32-bit words - // 6. 32-bit words (packet length first) go into a pkt2stream interface - // 7. Then into an ASYNC FIFO (in the network controller) - // - - // next_dma_addr -- circular buffer addressing - // {{{ - // We make this slightly more complex by allowing the base address - // to start on any word boundary, and by allowing the memory size - // to be anything - always @(*) - begin - next_dma_addr = o_dma_addr + 1; - if (o_dma_addr + 1 >= r_lastaddr) - next_dma_addr = r_baseaddr; - end - // }}} - - - // i_dma_pktlen - // {{{ - wire w_pkt_extra; - - generate if (DW == 32) - begin : SAME_WIDTH - always @(*) - begin - i_dma_pktlen = i_dma_data; - wide_pktlen = i_dma_data; - w_pkt_words = i_dma_pktlen[31:2] - + (|i_dma_pktlen[1:0]) - 1; - end - - assign w_pkt_extra = 1'b0; - - end else begin : FIND_PKT_LEN - - reg [AW+BLSB:0] w_pkt_end; - wire [LSB-1:0] w_readptr_plus_one; - - always @(*) - begin - wide_pktlen = i_dma_data; - if (OPT_LITTLE_ENDIAN) - begin - wide_pktlen = i_dma_data >> (32*r_readptr[LSB-1:0]); - i_dma_pktlen = wide_pktlen[31:0]; - end else begin - wide_pktlen = i_dma_data << (32*r_readptr[LSB-1:0]); - i_dma_pktlen = wide_pktlen[DW-1:DW-32]; - end - - // Verilator lint_off WIDTH - w_pkt_end = i_dma_pktlen - 1 - + { {(AW){1'b0}}, r_readptr[LSB-1:0], {(WBLSB){1'b0}} }; - // Verilator lint_on WIDTH - - w_pkt_words = w_pkt_end[AW+BLSB-1:BLSB]; - end - - assign w_readptr_plus_one = r_readptr[LSB-1:0] + 1; - - assign w_pkt_extra = !(&r_readptr[LSB-1:0]) - && (w_pkt_end[LSB-1:0] >= w_readptr_plus_one); - - - // Verilator lint_off UNUSED - wire unused_pktlen; - assign unused_pktlen = &{ 1'b0, w_pkt_end, - wide_pktlen[DW-1:32] }; - // Verilator lint_on UNUSED - end endgenerate - // }}} - - assign w_invalid_packet = (i_dma_pktlen <= 4) - || (|i_dma_pktlen[31:AW+BLSB]) - || (i_dma_pktlen[AW+BLSB-1:0] >= space_committed); - - // space_committed - // {{{ - // Units: Bytes - always @(posedge i_clk) - if (i_reset || r_dma_reset || !r_validptr) - space_committed <= 0; - else if (r_readptr <= r_writeptr) - // Verilator lint_off WIDTH - space_committed <= (r_writeptr - r_readptr) << WBLSB; - else - space_committed <= ({ r_memsize, {(LSB){1'b0}} } - + r_writeptr - r_readptr) << WBLSB; - // Verilator lint_on WIDTH - // }}} - - // fifo_committed - // {{{ - always @(posedge i_clk) - if (i_reset || (o_dma_cyc && i_dma_err) || dma_abort || r_dma_reset - || r_err) - fifo_committed <= 0; - else case({ (o_dma_stb && !i_dma_stall), - ((i_dma_ack && rd_state == S_LENGTH) || sfifo_read) }) - 2'b10: fifo_committed <= fifo_committed + 1; - 2'b01: fifo_committed <= fifo_committed - 1; - default: - fifo_committed <= sfifo_fill + wb_outstanding; - endcase - -`ifdef FORMAL - always @(*) - if (!i_reset && !r_err && !r_dma_reset) - begin - assert(fifo_committed == sfifo_fill + wb_outstanding); - assert(fifo_committed >= wb_outstanding); - assert(fifo_committed >= sfifo_fill); - end - - always @(*) - if (!i_reset) - assert(fifo_committed + (o_dma_stb ? 1:0) <= (1< (i_dma_ack ? 1:0)); - o_dma_stb <= 1'b0; - if (o_dma_stb) - begin - o_dma_addr <= next_dma_addr; - pkt_words <= pkt_words - 1; - end - - case(rd_state) - S_IDLE: begin - // {{{ - o_dma_stb <= 1'b0; - - pkt_words <= 0; - - o_dma_addr <= bus_readptr; - if (r_validptr && r_readptr != r_writeptr - && sfifo_empty) - begin - o_dma_cyc <= 1'b1; - o_dma_stb <= 1'b1; - // o_dma_addr <= o_dma_addr; - rd_state <= S_LENGTH; - end end - // }}} - S_LENGTH: begin - // {{{ - // o_dma_cyc <= 1'b0; - // o_dma_stb <= 1'b0; - if (i_dma_ack) - begin - rd_state <= S_PKTACTIVE; - pkt_words <= w_pkt_words; - // Verilator lint_off WIDTH - if (w_invalid_packet || w_pkt_words == 0) - begin - // This is either a packet length error, - // or the last word in the set. - // Quietly reset. - o_dma_addr <= bus_readptr; - rd_state <= (w_invalid_packet) ? S_IDLE - : S_RUNDOWN; - end - // Verilator lint_on WIDTH - end end - // }}} - S_PKTACTIVE: begin // Issue read requests - // {{{ - if (pkt_words > (o_dma_stb ? 1:0)) - begin - if (fifo_committed + 1 + (o_dma_stb ? 1:0) >= (1<= r_lastaddr) - w_next_rdptr[AW+LSB:LSB] = next_rdptr[AW+LSB:LSB] - - { 1'b0, r_memsize }; - end - - always @(posedge i_clk) - if (i_reset || (o_dma_cyc && i_dma_err)) - begin - // {{{ - // HALT, and wait for a new or updated configuration - r_readptr <= 0; - next_rdptr <= 0; - // }}} - end else if (r_dma_reset) - begin - // {{{ - // A new configuration exists, start from the initial - // baseaddr - r_readptr <= full_baseaddr[AW+BLSB-1:WBLSB]; - next_rdptr <= { 1'b0, full_baseaddr[AW+BLSB-1:WBLSB] }; - // }}} - end else if (dma_abort) - begin - // {{{ - // A user error has occurred. Restart from r_writeptr, - // discarding any potential packets that may have existed in - // memory. - r_readptr <= r_writeptr; - next_rdptr <= { 1'b0, r_writeptr }; - // }}} - end else if (rd_state == S_LENGTH && i_dma_ack) - begin - // We are starting a new packet. - if (w_invalid_packet) - begin - // On an invalid packet length, abandon the packet - r_readptr <= r_writeptr; - next_rdptr <= { 1'b0, r_writeptr }; - end else begin - // Otherwise record where the end of the packet would be - // We do nothing for (potential) wrap-around here. - // (For timing reasons ... as I might imagine them.) - next_rdptr <= r_readptr + i_dma_pktlen[AW+BLSB-1:WBLSB] - + ((|i_dma_pktlen[WBLSB-1:0]) ? 1:0); - end - end else if (rd_state == S_RUNDOWN && !o_dma_cyc) - begin - r_readptr <= w_next_rdptr[AW+LSB-1:0]; - end - // }}} - - // wb_outstanding - // {{{ - initial wb_outstanding = 0; - always @(posedge i_clk) - if (i_reset || r_dma_reset || !o_dma_cyc || i_dma_err) - begin - wb_outstanding <= 0; - end else case({ (o_dma_stb && !i_dma_stall), i_dma_ack }) - 2'b10: wb_outstanding <= wb_outstanding + 1; - 2'b01: wb_outstanding <= wb_outstanding - 1; - default: begin end - endcase - // }}} - - // o_int - // {{{ - always @(posedge i_clk) - if (i_reset || r_dma_reset) - o_int <= 1'b0; - else begin - o_int <= 1'b0; - if (r_err) - o_int <= 1'b1; - if (rd_state == S_IDLE && (r_readptr == r_writeptr)) - o_int <= 1'b1; - end - // }}} - - // Are our pointers out of order? - // {{{ - // FAIL if: (final_size - readptr) < (write_ptr - readptr) - // - // That's not quite right, though, since we wrap around a base address. - // - // space_committed = (writeptr > readptr) ? writeptr - readptr - // else - // (lastaddr - readptr) + (writeptr - baseptr) - // = (writeptr-readptr + memsz) - // - // pkt_used = full_pktlen - // - // FAIL IF: pkt_used > mem_authorized - // }}} - - // dma_abort - // {{{ - assign w_dma_abort = r_dma_reset || (o_dma_cyc && i_dma_err) - || (pkd_len > space_committed); - - always @(posedge i_clk) - if (i_reset) - dma_abort <= 0; - else if (dma_abort) - dma_abort <= (pkd_remaining > 0); - else if (w_dma_abort) - dma_abort <= release_packet; - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Gearbox return - // {{{ - - reg [DW-1:0] gearbox_data, gearbox_next; - reg [2*DW-1:0] next_gb_data; - reg gearbox_valid, gearbox_primed, gearbox_extra; - reg [1:0] gearbox_last; - reg [$clog2(DW/PKTDW)-1:0] gearbox_addr; - - // gearbox_valid, gearbox_primed - // {{{ - always @(posedge i_clk) - if (!i_reset || rd_state == S_IDLE || (o_dma_cyc && i_dma_err)) - begin - gearbox_valid <= 1'b0; - gearbox_primed <= (r_readptr[$clog2(DW/PKTDW)-1:0] != 0); - end else if (o_dma_cyc && i_dma_ack) - begin - gearbox_valid <= gearbox_primed; - gearbox_primed <= 1'b1; - end else if (gearbox_valid) - gearbox_valid <= gearbox_last[0]; - // }}} - - // gearbox_last - // {{{ - always @(posedge i_clk) - if (!i_reset || rd_state == S_IDLE || (o_dma_cyc && i_dma_err)) - begin - gearbox_last <= 2'b0; - end else if (o_dma_cyc && i_dma_ack) - begin - gearbox_last <= { !gearbox_extra, 1'b1}; - if (rd_state != S_RUNDOWN || wb_outstanding > 1) - gearbox_last <= 2'b00; - end else if (gearbox_valid) - gearbox_last <= gearbox_last << 1; - // }}} - - always @(posedge i_clk) - if (rd_state == S_IDLE) - gearbox_addr <= r_readptr[$clog2(DW/PKTDW)-1:0]+1; - - always @(posedge i_clk) - if (rd_state == S_IDLE) - gearbox_extra <= 1'b0; - else if (rd_state == S_LENGTH && o_dma_cyc && i_dma_ack) - gearbox_extra <= w_pkt_extra; - - // gearbox_data, gearbox_next - // {{{ - always @(*) - if (OPT_LITTLE_ENDIAN) - begin - next_gb_data = { {(DW){1'b0}}, gearbox_next } - | ({ {(DW){1'b0}}, i_dma_data } << (gearbox_addr*32)); - end else begin - next_gb_data = { gearbox_next, {(DW){1'b0}} } - | ({ i_dma_data,{(DW){1'b0}} } - >> (gearbox_addr*32)); - end - - always @(posedge i_clk) - if (!i_reset || (o_dma_cyc && i_dma_err)) - begin - gearbox_data <= 0; - gearbox_next <= 0; - end else if (o_dma_cyc && i_dma_ack) - begin - if (OPT_LITTLE_ENDIAN) - begin - { gearbox_next, gearbox_data } <= next_gb_data; - end else begin - { gearbox_data, gearbox_next } <= next_gb_data; - end - end else if (gearbox_valid && gearbox_last[0]) - begin - if (OPT_LITTLE_ENDIAN) - begin - { gearbox_next, gearbox_data } <= { {(DW){1'b0}}, gearbox_next }; - end else begin - { gearbox_data, gearbox_next } <= { gearbox_next, {(DW){1'b0}} }; - end - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign sfifo_reset = i_reset || dma_abort || r_dma_reset; - - // Synchronous FIFO - sfifo #( - .BW(DW), .LGFLEN(LGFIFO) - ) u_pktfifo ( - // {{{ - .i_clk(i_clk), .i_reset(sfifo_reset), - .i_wr(gearbox_valid), - .i_data(gearbox_data), - .o_full(sfifo_full), .o_fill(sfifo_fill), - .i_rd(sfifo_read), .o_data( sfifo_data ), - .o_empty(sfifo_empty) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Unpack bus words into stream words - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign sfifo_read = !sfifo_empty && !dma_abort && release_packet - && (!pkd_valid || (pkd_ready && pkd_load <= 1)); - - // pkd_len, pkd_last - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - pkd_remaining <= 0; - pkd_len <= 0; - pkd_last <= 0; - pkd_bytes <= 0; - end else if (!release_packet && (r_dma_reset || dma_abort - || rd_state == S_IDLE)) - begin - pkd_remaining <= 0; - pkd_len <= 0; - pkd_last <= 0; - pkd_bytes <= 0; - end else if (rd_state == S_LENGTH) - begin - pkd_remaining <= 0; - pkd_len <= 0; - pkd_last <= 0; - pkd_bytes <= 0; - if (i_dma_ack && !w_invalid_packet) - begin - pkd_len <= i_dma_pktlen[AW+BLSB-1:0]; - pkd_remaining <= i_dma_pktlen[AW+BLSB-1:0]; - end - end else if (pkd_valid && pkd_ready) - begin - pkd_last <= (pkd_remaining <= (PKTDW/8)); - pkd_bytes <= (pkd_remaining < (PKTDW/8)) - ? pkd_remaining[$clog2(PKTDW/8)-1:0] - : {($clog2(PKTDW/8)){1'b0}}; - if (pkd_remaining >= (PKTDW/8)) - pkd_remaining <= pkd_remaining - (PKTDW/8); - else - pkd_remaining <= 0; - end - // }}} - - // pkd_valid, pkd_load (in PKTDW-bit words) - // {{{ - initial pkd_valid = 0; - initial pkd_load = 0; - always @(posedge i_clk) - begin - if (i_reset) - begin - // {{{ - pkd_valid <= 0; // == Something is in our register - pkd_load <= 0; // == How many somethings in our reg - // }}} - end else if (!release_packet && (r_dma_reset - || dma_abort || rd_state == S_IDLE)) - begin - // {{{ - pkd_valid <= 0; - pkd_load <= 0; - // }}} - end else if (sfifo_read) - begin - // {{{ - pkd_valid <= 1; - pkd_load <= FULL_LOAD[$clog2(DW/PKTDW):0]; -`ifdef FORMAL - assert(!dma_abort); -`endif - // }}} - end else if ((pkd_valid && pkd_ready) - || (dma_abort && (!pkd_valid || pkd_ready))) - begin - // {{{ - if (pkd_load > 0) - pkd_load <= pkd_load - 1; - pkd_valid <= (pkd_load > 1)||dma_abort; - - if (pkd_remaining <= (PKTDW/8)) - begin // END OF PACKET - pkd_valid <= 0; - pkd_load <= 0; - end - // }}} - end - - pkd_load[1:0] <= 2'b00; - end - -`ifdef FORMAL - always @(*) - if (!i_reset) - begin - assert(pkd_load <= DW/8); - assert(pkd_load[1:0] == 2'b00); - end - - always @(*) - if (!i_reset && !r_dma_reset && rd_state != S_IDLE) - begin - assert(pkd_valid == (pkd_load > 0 && pkd_remaining > 0)); - end -`endif - // }}} - - // pkd_wide - // {{{ - always @(posedge i_clk) - if (sfifo_read) - begin - pkd_wide <= sfifo_data; - end else if (pkd_valid && pkd_ready) - begin - // {{{ - if (OPT_LITTLE_ENDIAN) - pkd_wide <= pkd_wide >> PKTDW; - else - pkd_wide <= pkd_wide << PKTDW; - // }}} - end - // }}} - - // pkd_data -- picked off the ending bits of pkd_wide - // {{{ - generate if (OPT_LITTLE_ENDIAN) - begin - assign pkd_data = pkd_wide[PKTDW-1:0]; - end else begin - assign pkd_data = pkd_wide[DW-1:DW-PKTDW]; - end endgenerate - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Format for a final output - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Questions: - // ---------------- - // 1. What should our output format be? - // Abortable AXI stream, or AXI (length + data, no last) stream? - // - // CHOICE: AXI (length+data, no last) stream - // - // 2. Can we ever abort? - // - What if we receive a bus error? - // - What if the packet buffer can't be kept full at the output? - // - What if the user reconfigures the port mid-transaction, and - // so we get an r_dma_reset? - // - // CHOICE: Complete the stream packet once started. No ABORTs allowed. - // - // 3. How can we guarantee a full packet will always be ready? - // and that the network interface will never run dry? - // We have enough bandwidth that this shouldn't be an issue - // ... once we get the FIFO filled and the pkd_ fsm going. - // Can we wait to start transmitting the packet until either - // a full packet is in the FIFO and pkd_ fsm, or until the - // pkd_ FSM is full and the FIFO is fully charged? - // - // CHOICE: Wait til the FIFO has either 1) a full packet within it, or - // 2) it's half full, before releasing VALID - // - - initial release_packet = 1'b0; - always @(posedge i_clk) - if (i_reset) - release_packet <= 1'b0; - else if (!release_packet) - begin - if (rd_state == S_RUNDOWN && !o_dma_cyc) - release_packet <= 1'b1; - if (pkd_valid && sfifo_fill[LGFIFO-2]) - release_packet <= 1'b1; - if (!pkd_valid || r_dma_reset || pkd_len > space_committed) - release_packet <= 1'b0; - end else if (pkd_remaining == 0) - release_packet <= 1'b0; - - assign M_AXIN_VALID = pkd_valid && release_packet; - assign pkd_ready = M_AXIN_READY && release_packet; - assign M_AXIN_DATA = pkd_data; - assign M_AXIN_BYTES = pkd_bytes; - assign M_AXIN_LAST = pkd_last; - assign M_AXIN_ABORT = 1'b0; - // }}} - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_wb_data[31:AW], i_wb_data[1:0], - full_readptr[BLSB-1:0], sfifo_full, w_next_rdptr[AW+LSB] - }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Local declarations - // {{{ - localparam FSLV_LGDEPTH = 3; - localparam F_LGDEPTH = LGFIFO+1; - localparam F_MAXPKT = (1<<20)-5; - localparam F_LGMXPKT = $clog2(F_MAXPKT); - - reg f_past_valid; - wire [FSLV_LGDEPTH-1:0] fslv_nreqs, fslv_nacks, - fslv_outstanding; - wire [F_LGDEPTH-1:0] fdma_nreqs, fdma_nacks, - fdma_outstanding; - wire [F_LGMXPKT-1:0] fpkt_word; - wire [11:0] fpkt_count; - wire M_AXIN_LAST; - wire [AW+BLSB-1:0] full_memsize; - - assign full_memsize = { r_memsize, {(BLSB){1'b0}} }; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Outgoing network properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign M_AXIN_LAST = (pkd_remaining <= 4); - - // Stream properties - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assert(!M_AXIN_VALID); - else if ($past(M_AXIN_VALID && !M_AXIN_READY)) - begin - assert(M_AXIN_VALID); - assert($stable(M_AXIN_DATA)); - assert($stable(M_AXIN_LAST)); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - fwb_slave #( - .AW(2), .DW(32) - ) fslv ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(i_wb_cyc), .i_wb_stb(i_wb_stb), .i_wb_we(i_wb_we), - .i_wb_addr(i_wb_addr), .i_wb_data(i_wb_data), - .i_wb_sel(i_wb_sel), - .i_wb_ack(o_wb_ack), .i_wb_stall(o_wb_stall), - .i_wb_idata(o_wb_data), .i_wb_err(1'b0), - .f_nreqs(fslv_nreqs), .f_nacks(fslv_nacks), - .f_outstanding(fslv_outstanding) - // }}} - ); - - always @(*) - if (i_wb_cyc) - assert(fslv_outstanding == (o_wb_ack ? 1:0)); - - fwb_master #( - .AW(AW), .DW(DW), .F_LGDEPTH(F_LGDEPTH) - ) fdma ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(o_dma_cyc), .i_wb_stb(o_dma_stb), .i_wb_we(o_dma_we), - .i_wb_addr(o_dma_addr), .i_wb_data(o_dma_data), - .i_wb_sel(o_dma_sel), - .i_wb_ack(i_dma_ack), .i_wb_stall(i_dma_stall), - .i_wb_idata(i_dma_data), .i_wb_err(i_dma_err), - .f_nreqs(fdma_nreqs), .f_nacks(fdma_nacks), - .f_outstanding(fdma_outstanding) - // }}} - ); - - always @(*) - if (o_dma_cyc) - assert(fdma_outstanding == wb_outstanding); - - always @(*) - if (!o_dma_stb && fdma_outstanding == 0) - assert(!o_dma_cyc); - - always @(*) - if (!i_reset) - begin - if (r_baseaddr == 0) - assert(r_dma_reset); - if (r_memsize == 0) - assert(r_dma_reset); - // if (r_err) assert(r_dma_reset); - end - - always @(posedge i_clk) - if (!i_reset) - begin - case(rd_state) - S_IDLE: begin - // {{{ - if (!r_err && !r_dma_reset) - assert(!o_dma_cyc && !release_packet); - end - // }}} - S_LENGTH: begin - // {{{ - assert(o_dma_cyc); - assert(!release_packet); - assert(!pkd_valid); - assert(pkd_load == 0); - assert(pkd_remaining == 0); - assert(fdma_outstanding == (o_dma_stb ? 0:1)); - assert(!dma_abort); - end - // }}} - S_PKTACTIVE: begin - // {{{ - assert(pkt_words >= (o_dma_stb ? 1:0)); - assert(o_dma_cyc || $changed(rd_state)); - assert(pkd_len <= space_committed || dma_abort - || w_dma_abort || r_dma_reset); - if (!r_dma_reset) - assert(full_memsize >= pkd_len); - end - // }}} - S_PKTPAUSED: begin - assert(pkt_words > (o_dma_stb ? 1:0)); - assert(pkd_len <= space_committed || dma_abort - || w_dma_abort || r_dma_reset); - if (!r_dma_reset) - assert(full_memsize >= pkd_len); - end - S_RUNDOWN: begin - assert(pkt_words == (o_dma_stb ? 1:0)); - assert(!$rose(o_dma_stb)); - // assert(o_dma_cyc || ($changed(rd_state)) || $fell(o_dma_cyc)); - assert(pkd_len <= space_committed || dma_abort - || w_dma_abort || r_dma_reset); - if (!r_dma_reset) - assert(full_memsize >= pkd_len); - end - default: assert(0); - endcase - end - - always @(posedge i_clk) - if (!i_reset && !r_dma_reset && (o_dma_stb || !r_err)) - begin - assert(o_dma_addr >= r_baseaddr); - assert(o_dma_addr < r_lastaddr); - - assert(r_readptr[AW+LSB-1:LSB] >= r_baseaddr); - assert(r_readptr[AW+LSB-1:LSB] < r_lastaddr); - - assert(w_next_rdptr[AW+LSB-1:LSB] >= r_baseaddr); - assert(w_next_rdptr[AW+LSB-1:LSB] < r_lastaddr); - end - - always @(*) - assert(r_lastaddr == r_baseaddr + r_memsize); - - always @(*) - if (!r_dma_reset) - begin - assert(r_validptr == (r_writeptr[AW+LSB-1:LSB] >= r_baseaddr - && r_writeptr[AW+LSB-1:LSB] < r_lastaddr)); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Induction properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Count data from r_readptr to r_nextptr via pkd_len, pkd_remaining, - // and pkd_words - reg [AW-1:0] f_total_pkt_words; - reg [AW:0] f_addr, f_lastaddr; - reg [AW+LSB:0] f_lastword; - reg [AW+BLSB:0] f_pkt_end; - reg [AW+BLSB-1:0] f_bytes_sent; - reg [BLSB-1:0] f_lastword_fraction; - reg [AW-1:0] f_words_in_pipe; - reg [AW+BLSB-1:0] f_bytes_in_pipe; - reg [AW+LSB-1:0] f_readptr; - - always @(posedge i_clk) - if (!i_reset && !r_dma_reset && !dma_abort && rd_state == S_IDLE) - f_readptr <= r_readptr; - - always @(posedge i_clk) - if (!i_reset && !r_dma_reset && !dma_abort && !r_err) - begin - case(rd_state) - S_IDLE: begin - assert(sfifo_fill == 0); - end - S_LENGTH: begin - assert(f_readptr == r_readptr); - assert(sfifo_fill == 0); - assert(wb_outstanding == (o_dma_stb ? 0:1)); - end - S_PKTACTIVE: assert(f_readptr == r_readptr); - S_PKTPAUSED: assert(f_readptr == r_readptr); - S_RUNDOWN: begin end - default: begin end - endcase - end - - always @(*) - begin - f_pkt_end = pkd_len - 1 - + { {(AW){1'b0}}, f_readptr[LSB-1:0], {(WBLSB){1'b0}} }; - f_total_pkt_words = f_pkt_end[AW+BLSB-1:BLSB] + 1; - - f_bytes_sent = pkd_len - pkd_remaining; - - // Lastword fraction is the number of extra bytes we read - // by reading words at a time instead of bytes at a time. As - // a result, the last word might include more than we want. - f_lastword_fraction = f_pkt_end[BLSB-1:0] + 1; - if (f_lastword_fraction != 0) - f_lastword_fraction = (DW/8) - f_lastword_fraction; - - f_words_in_pipe = pkt_words + wb_outstanding + sfifo_fill; - // if (rd_state != S_LENGTH && rd_state != S_LENGTH) - // f_words_in_pipe = f_words_in_pipe + pkt_words; - f_bytes_in_pipe = { f_words_in_pipe, {(BLSB){1'b0}} }; - if (f_words_in_pipe > 0) - f_bytes_in_pipe = f_bytes_in_pipe - f_lastword_fraction; - end - - always @(*) - if (!i_reset && !r_dma_reset && !dma_abort && !r_err - && rd_state != S_IDLE && rd_state != S_LENGTH) - begin - assert(f_words_in_pipe >= pkt_words); - assert(f_words_in_pipe >= wb_outstanding); - assert(f_words_in_pipe >= sfifo_fill); - - assert(pkd_len >= pkd_remaining); - if (pkd_load >= pkd_remaining) - begin - assert(f_words_in_pipe == 0); - end else begin - assert(f_bytes_in_pipe + pkd_load == pkd_remaining); - end - end - - // Track o_dma_addr - always @(*) - begin - f_addr = f_readptr[AW+LSB-1:LSB] - + (f_total_pkt_words - pkt_words); - if (rd_state == S_IDLE) - f_addr = f_readptr[AW+LSB-1:LSB]; - else if (rd_state == S_LENGTH) - f_addr = f_readptr[AW+LSB-1:LSB] + (o_dma_stb ? 0:1); - - if (f_addr >= r_lastaddr) - f_addr = f_addr - r_memsize; - - f_lastword = f_readptr + pkd_len[AW+BLSB-1:WBLSB] - + ((|pkd_len[WBLSB-1:0]) ? 1:0); - if (f_lastword >= { r_lastaddr, {(LSB){1'b0}} }) - f_lastword = f_lastword - { 1'b0, r_memsize, {(LSB){1'b0}} }; - f_lastaddr = f_lastword[AW+LSB-1:LSB]; - end - -// END = READPTR * 4 + 0x17068000 - always @(*) - if (!i_reset && !r_dma_reset && rd_state != S_IDLE) - begin - if (rd_state != S_LENGTH) - begin - if (next_rdptr < { r_lastaddr, {(LSB){1'b0}} }) - begin - assert(f_lastword == next_rdptr); - end else begin - assert(f_lastword == next_rdptr - { 1'b0, r_memsize, {(LSB){1'b0}} }); - end - end - - if (rd_state == S_LENGTH) - begin - if (o_dma_stb) - begin - assert(o_dma_addr == f_readptr[AW+LSB-1:LSB]); - end else if (f_readptr[AW+LSB-1:LSB] + 1 < r_lastaddr) - begin - assert(o_dma_addr == f_readptr[AW+LSB-1:LSB]+1); - end else begin - assert(o_dma_addr == r_baseaddr); - end - end else if (rd_state == S_RUNDOWN) - begin - // assert(o_dma_addr == f_lastaddr); - end else begin - assert(o_dma_addr == f_addr); - end - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Never" data checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // -`ifdef FNEVER - // Given a position in a packet doesn't have a particular value in it, - // assert that value is not returned. - // - // How would we do this? We'd need to know the return address of every - // packet - (* anyconst *) reg fnvr_check; - (* anyconst *) reg [DW-1:0] fnvr_data; - - always @(*) - if (fnvr_check && o_dma_cyc && i_dma_ack) - assume(i_dma_data != fnvr_data); - - always @(*) - if (fnvr_check && !sfifo_empty) - assert(sfifo_data != fnvr_data); - - always @(*) - if (fnvr_check && !sfifo_empty) - assert((&fifo_keep) || fifo_last); -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Pick a position in a stream, and a byte at that position. Then - // prove that, if (fpkt_word == fc_addr), then (M_AXIN_DATA == fc_data). - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - reg [3:0] cvr_packets; - - initial cvr_packets = 0; - always @(posedge i_clk) - if (i_reset) - cvr_packets <= 0; - else if (M_AXIN_VALID && M_AXIN_READY && M_AXIN_LAST) - cvr_packets <= cvr_packets + 1; - - always @(*) - begin - cover(cvr_packets == 1); - cover(cvr_packets == 2); - cover(cvr_packets == 3); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - -// always @(*) -// begin -// assume(r_baseaddr[19:0] == 0); -// assume(r_memsize[19:0] == 0); -// assume(r_writeptr[LSB-1:0] == 0); -// end - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/netfifo.v b/delete_later/rtl/net/netfifo.v deleted file mode 100644 index 3f9cc1a..0000000 --- a/delete_later/rtl/net/netfifo.v +++ /dev/null @@ -1,661 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: netfifo.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Abortable packet FIFO. Does not include native support for the -// BYTES field, however the data field can be expanded for this -// purpose. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module netfifo #( - // {{{ - parameter BW=8, // Byte/data width - parameter LGFLEN=4, - parameter [0:0] OPT_ASYNC_READ = 1'b1, - parameter [0:0] OPT_WRITE_ON_FULL = 1'b0, - parameter [0:0] OPT_READ_ON_EMPTY = 1'b0, - localparam FLEN=(1< (1+s_abort)))); - wire s_abort = S_AXIN_ABORT && s_midpacket; - // wire w_abort = lastv && S_AXIN_ABORT; - // }}} - - // fill - // {{{ - assign fill = wr_addr - rd_addr; - // }}} - - // r_full - // {{{ - assign r_full = fill[LGFLEN]; - // }}} - - // S_AXIN_READY - // {{{ - always @(*) - if (OPT_WRITE_ON_FULL && M_AXIN_READY) - S_AXIN_READY = 1'b1; - else if (S_AXIN_ABORT) - S_AXIN_READY = 1'b1; - else - S_AXIN_READY = !r_full; - // }}} - - // lastv - // {{{ - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - lastv <= 0; // End of packet pointer is invalid - else if (S_AXIN_VALID && S_AXIN_READY && !S_AXIN_ABORT && S_AXIN_LAST - && (!r_empty || !M_AXIN_READY)) - lastv <= 1; // EOP points to valid spot in the FIFO - else if (w_rd && eop_next) - lastv <= 0; // Packet was read, EOP is now invalid - // }}} - - // eop_addr - // {{{ - initial eop_addr = 0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - eop_addr <= 0; - else if (S_AXIN_VALID && S_AXIN_READY && !S_AXIN_ABORT && S_AXIN_LAST) - eop_addr <= wr_addr; - // }}} - - // eop_next - // {{{ - assign eop_next = lastv && (eop_addr == rd_addr); - // }}} - - // wr_addr, the write address pointer - // {{{ - initial wr_addr = 0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - wr_addr <= 0; - else if (s_abort) - begin - if (lastv) - wr_addr <= eop_addr + 1; // Back up to last pkt - else if (M_AXIN_VALID) - wr_addr <= rd_addr + 1; // Empty FIFO, no pkts within it - end else if (w_wr) - wr_addr <= wr_addr + 1'b1; - // }}} - - // Write to memory - // {{{ - always @(posedge S_AXI_ACLK) - if (w_wr) - mem[wr_addr[(LGFLEN-1):0]] <= { S_AXIN_LAST, S_AXIN_DATA }; - // }}} - - // rd_addr, the read address pointer - // {{{ - initial rd_addr = 0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - rd_addr <= 0; - else if (w_rd) - rd_addr <= rd_addr + 1; - // }}} - - // r_empty - // {{{ - assign r_empty = (wr_addr == rd_addr); - // }}} - - // M_AXIN_VALID - // {{{ - always @(*) - if (OPT_READ_ON_EMPTY && S_AXIN_VALID && !S_AXIN_ABORT) - M_AXIN_VALID = 1'b1; - else - M_AXIN_VALID = !r_empty; - // }}} - - // M_AXIN_LAST, M_AXIN_DATA: Read from the FIFO - // {{{ - generate if (OPT_ASYNC_READ && OPT_READ_ON_EMPTY) - begin : ASYNCHRONOUS_READ_ON_EMPTY - // M_AXIN_LAST, M_AXIN_DATA - // {{{ - reg r_last, last_override; - - always @(*) - begin - { r_last, M_AXIN_DATA } = mem[rd_addr[LGFLEN-1:0]]; - if (r_empty) - { r_last, M_AXIN_DATA } = { S_AXIN_LAST, S_AXIN_DATA }; - end - - always @(posedge S_AXI_ACLK) - last_override <= 0 && (M_AXIN_VALID && !M_AXIN_READY && M_AXIN_LAST); - - always @(*) - M_AXIN_LAST = r_last || last_override; - // }}} - end else if (OPT_ASYNC_READ) - begin : ASYNCHRONOUS_READ - // M_AXIN_LAST, M_AXIN_DATA - // {{{ - always @(*) - { M_AXIN_LAST, M_AXIN_DATA } = mem[rd_addr[LGFLEN-1:0]]; - // }}} - end else begin : REGISTERED_READ - // {{{ - reg bypass_valid; - reg [BW:0] bypass_data, rd_data; - reg [LGFLEN-1:0] rd_next; - - always @(*) - rd_next = rd_addr[LGFLEN-1:0] + 1; - - // Memory read, bypassing it if we must - // {{{ - initial bypass_valid = 0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - bypass_valid <= 0; - else begin - bypass_valid <= 1'b0; - if (S_AXIN_VALID - && (r_empty || (M_AXIN_READY && (fill == 1)))) - bypass_valid <= 1'b1; - if (s_abort && !lastv) - bypass_valid <= 1'b1; - end - - always @(posedge S_AXI_ACLK) - bypass_data <= { (S_AXIN_LAST || S_AXIN_ABORT), S_AXIN_DATA }; - - initial mem[0] = 0; - initial rd_data = 0; - always @(posedge S_AXI_ACLK) - if (bypass_valid || w_rd) - // (!M_AXIN_VALID || M_AXIN_READY || (M_AXIN_ABORT && !M_AXIN_LAST))) - rd_data <= mem[(w_rd)?rd_next : rd_addr[LGFLEN-1:0]]; - - always @(*) - if (OPT_READ_ON_EMPTY && r_empty) - { M_AXIN_LAST, M_AXIN_DATA } = { S_AXIN_LAST, S_AXIN_DATA }; - else if (bypass_valid) - { M_AXIN_LAST, M_AXIN_DATA } = bypass_data; - else - { M_AXIN_LAST, M_AXIN_DATA } = rd_data; - // }}} - // }}} - end endgenerate - // }}} - - // M_AXIN_ABORT - // {{{ - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - r_midpacket <= 0; - else if (M_AXIN_VALID) - r_midpacket <= (!M_AXIN_READY || !M_AXIN_LAST); - - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - s_midpacket <= 0; - else if (S_AXIN_ABORT) - s_midpacket <= 0; - else if (S_AXIN_VALID && S_AXIN_READY) - s_midpacket <= !S_AXIN_LAST; - - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - M_AXIN_ABORT <= 1'b0; - else if (!M_AXIN_ABORT) - begin - if (!lastv) - M_AXIN_ABORT <= S_AXIN_ABORT && (M_AXIN_VALID || r_midpacket) && s_midpacket; - end else if (!M_AXIN_VALID || M_AXIN_READY) - M_AXIN_ABORT <= 1'b0; - // }}} - - // Make Verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, fill, r_empty }; - // verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// FORMAL METHODS -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -`ifdef FORMAL - -// -// Assumptions about our input(s) -// -// -`ifdef SFIFO -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - wire [LGFLEN:0] f_fill, f_next; - wire f_full, f_empty; - - initial f_past_valid = 1'b0; - always @(posedge S_AXI_ACLK) - f_past_valid <= 1'b1; - - //////////////////////////////////////////////////////////////////////// - // - // Interface properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wire [9:0] faxin_swords, faxin_mwords; - wire [11:0] faxin_spkts, faxin_mpkts; - - faxin_slave #( - // {{{ - .DATA_WIDTH(BW), - .MIN_LENGTH(0) - // }}} - ) faxins ( - // {{{ - .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), - // - .S_AXIN_VALID(S_AXIN_VALID), .S_AXIN_READY(S_AXIN_READY), - .S_AXIN_DATA(S_AXIN_DATA), .S_AXIN_LAST(S_AXIN_LAST), - .S_AXIN_ABORT(S_AXIN_ABORT), - // - .f_stream_word(faxin_swords), - .f_packets_rcvd(faxin_spkts) - // }}} - ); - - faxin_master #( - // {{{ - .DATA_WIDTH(BW), - .MIN_LENGTH(0), .MAX_LENGTH(0) - // }}} - ) faxinm ( - // {{{ - .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), - // - .S_AXIN_VALID(M_AXIN_VALID), .S_AXIN_READY(M_AXIN_READY), - .S_AXIN_DATA(M_AXIN_DATA), .S_AXIN_LAST(M_AXIN_LAST), - .S_AXIN_ABORT(M_AXIN_ABORT), - // - .f_stream_word(faxin_mwords), - .f_packets_rcvd(faxin_mpkts) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about our flags and counters - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign f_fill = wr_addr - rd_addr; - assign f_empty = (wr_addr == rd_addr); - assign f_full = (f_fill >= (1< M_* processing - // {{{ - - p64bscrambler #( - .OPT_RX(1'b1) - ) u_descrambler ( - // {{{ - .i_clk(i_rx_clk), .i_reset_n(rx_reset_n), - .i_valid(i_raw_valid), - .o_ready(ign_rx_raw_ready), - .i_data(i_raw_data), - // - .o_valid(rx_valid), - .i_ready(rx_ready), - .o_data(rx_data) - // }}} - ); - - p642pkt - u_p642pkt ( - // {{{ - .RX_CLK(i_rx_clk), .S_ARESETN(rx_reset_n), - // - .i_phy_fault(i_phy_fault), - .o_remote_fault(remote_fault), - .o_local_fault(local_fault), - .o_link_up(rx_link_up), - // - .RX_VALID(rx_valid), - .RX_DATA(rx_data), - // - .M_VALID(SRC_VALID), - .M_READY(SRC_READY), - .M_DATA(SRC_DATA), - .M_BYTES(SRC_BYTES), - .M_ABORT(SRC_ABORT), - .M_LAST(SRC_LAST) - // }}} - ); - - assign rx_ready = 1'b1; - - dropshort #( - .DW(64) - ) u_dropshort ( - // {{{ - .S_CLK(i_rx_clk), .S_ARESETN(rx_reset_n), - // - .S_VALID(SRC_VALID), - .S_READY(SRC_READY), - .S_DATA( SRC_DATA), - .S_BYTES(SRC_BYTES), - .S_ABORT(SRC_ABORT), - .S_LAST( SRC_LAST), - // - .M_VALID(PKT_VALID), - .M_READY(PKT_READY), - .M_DATA( PKT_DATA), - .M_BYTES(PKT_BYTES), - .M_ABORT(PKT_ABORT), - .M_LAST( PKT_LAST) - // }}} - ); - - crc_axin #( - .DATA_WIDTH(64), .OPT_SKIDBUFFER(1'b1), .OPT_LOWPOWER(1'b0) - ) u_check_crc ( - // {{{ - .ACLK(i_rx_clk), .ARESETN(rx_reset_n), - .i_cfg_en(1'b1), - // - .S_AXIN_VALID(PKT_VALID), - .S_AXIN_READY(PKT_READY), - .S_AXIN_DATA( PKT_DATA), - .S_AXIN_BYTES({ (PKT_BYTES==0), PKT_BYTES }), - .S_AXIN_LAST( PKT_LAST), - .S_AXIN_ABORT(PKT_ABORT), - // - .M_AXIN_VALID(CRC_VALID), - .M_AXIN_READY(CRC_READY), - .M_AXIN_DATA( CRC_DATA), - .M_AXIN_BYTES({ ign_high, CRC_BYTES }), - .M_AXIN_LAST( CRC_LAST), - .M_AXIN_ABORT(CRC_ABORT) - // }}} - ); - - axinwidth #( - .IW(64), .OW(128) - ) u_rxwidth ( - // {{{ - .ACLK(i_rx_clk), .ARESETN(rx_reset_n), - // - .S_AXIN_VALID(CRC_VALID), - .S_AXIN_READY(CRC_READY), - .S_AXIN_DATA( CRC_DATA), - .S_AXIN_BYTES({ (CRC_BYTES==0), CRC_BYTES }), - .S_AXIN_LAST( CRC_LAST), - .S_AXIN_ABORT(CRC_ABORT), - // - .M_AXIN_VALID(RXWD_VALID), - .M_AXIN_READY(RXWD_READY), - .M_AXIN_DATA( RXWD_DATA), - .M_AXIN_BYTES({ ign_rx_high, RXWD_BYTES }), - .M_AXIN_LAST( RXWD_LAST), - .M_AXIN_ABORT(RXWD_ABORT) - // }}} - ); - - axincdc #( - .DW(128), - .LGFIFO(5) // Sweet spot for Xilinx distributed RAM - ) u_rxcdc ( - // {{{ - .S_CLK(i_rx_clk), .S_ARESETN(rx_reset_n), - // - .S_VALID(RXWD_VALID), - .S_READY(RXWD_READY), - .S_DATA( RXWD_DATA), - .S_BYTES(RXWD_BYTES), - .S_LAST( RXWD_LAST), - .S_ABORT(RXWD_ABORT), - // - .M_CLK(i_sys_clk), .M_ARESETN(i_reset_n), - // - .M_VALID(M_VALID), - .M_READY(M_READY), - .M_DATA( M_DATA), - .M_BYTES(M_BYTES), - .M_LAST( M_LAST), - .M_ABORT(M_ABORT) - // }}} - ); - - always @(posedge i_rx_clk or negedge rx_reset_n) - if (!rx_reset_n) - rx_activity <= 0; - else if (M_VALID && M_LAST && !M_ABORT) - rx_activity <= -1; - else if (rx_activity != 0) - rx_activity <= rx_activity - 1; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Outgoing S_* -> packet processing - // {{{ - - axincdc #( - .DW(128), - .LGFIFO(5) // Sweet spot for Xilinx distributed RAM - ) u_txcdc ( - // {{{ - .S_CLK(i_sys_clk), .S_ARESETN(i_reset_n), - // - .S_VALID(S_VALID), - .S_READY(S_READY), - .S_DATA( S_DATA), - .S_BYTES(S_BYTES), - .S_LAST( S_LAST), - .S_ABORT(S_ABORT), - // - .M_CLK(i_tx_clk), .M_ARESETN(tx_reset_n), - // - .M_VALID(TXCK_VALID), - .M_READY(TXCK_READY), - .M_DATA( TXCK_DATA), - .M_BYTES(TXCK_BYTES), - .M_LAST( TXCK_LAST), - .M_ABORT(TXCK_ABORT) - // }}} - ); - - axinwidth #( - .IW(128), .OW(64) - ) u_txwidth ( - // {{{ - .ACLK(i_sys_clk), .ARESETN(tx_reset_n), - // - .S_AXIN_VALID(TXCK_VALID), - .S_AXIN_READY(TXCK_READY), - .S_AXIN_DATA( TXCK_DATA), - .S_AXIN_BYTES({ (TXCK_BYTES==0), TXCK_BYTES }), - .S_AXIN_LAST( TXCK_LAST), - .S_AXIN_ABORT(TXCK_ABORT), - // - .M_AXIN_VALID(TXWD_VALID), - .M_AXIN_READY(TXWD_READY), - .M_AXIN_DATA( TXWD_DATA), - .M_AXIN_BYTES({ ign_tx_high, TXWD_BYTES }), - .M_AXIN_LAST( TXWD_LAST), - .M_AXIN_ABORT(TXWD_ABORT) - // }}} - ); - - pktgate #( - .DW(64), .LGFLEN(LGPKTGATE) - ) u_pktgate ( - // {{{ - .S_AXI_ACLK(i_tx_clk), .S_AXI_ARESETN(tx_reset_n), - // - .S_AXIN_VALID(TXWD_VALID), - .S_AXIN_READY(TXWD_READY), - .S_AXIN_DATA( TXWD_DATA), - .S_AXIN_BYTES(TXWD_BYTES), - .S_AXIN_LAST( TXWD_LAST), - .S_AXIN_ABORT(TXWD_ABORT), - // - .M_AXIN_VALID(FULL_VALID), - .M_AXIN_READY(FULL_READY), - .M_AXIN_DATA( FULL_DATA), - .M_AXIN_BYTES(FULL_BYTES), - .M_AXIN_LAST( FULL_LAST), - .M_AXIN_ABORT(FULL_ABORT) - // }}} - ); - - pkt2p64b - u_pkt2p64b ( - // {{{ - .TX_CLK(i_tx_clk), .S_ARESETN(tx_reset_n), - // - .i_remote_fault(remote_fault), - .i_local_fault(local_fault || rx_reset_n), - // - .S_VALID(FULL_VALID), - .S_READY(FULL_READY), - .S_DATA( FULL_DATA), - .S_BYTES(FULL_BYTES), - .S_LAST( FULL_LAST), - .S_ABORT(FULL_ABORT), - // - .TXREADY(tx_ready), - .TXDATA(tx_data) - // }}} - ); - - p64bscrambler #( - .OPT_RX(1'b0) - ) u_scrambler ( - // {{{ - .i_clk(i_tx_clk), .i_reset_n(tx_reset_n), - // - .i_valid(1'b1), - .o_ready(tx_ready), - .i_data( tx_data), - // - .o_valid(ign_tx_raw_valid), - .i_ready(i_raw_ready), - .o_data( o_raw_data) - // }}} - ); - - assign tx_link_up = tx_reset_n; - - always @(posedge i_tx_clk or negedge tx_reset_n) - if (!tx_reset_n) - tx_activity <= 0; - else if (S_VALID) - tx_activity <= -1; - else if (tx_activity != 0) - tx_activity <= tx_activity - 1; - - // }}} - - assign o_link_up = rx_link_up && tx_link_up; - assign o_activity = rx_activity[ACTMSB] || tx_activity[ACTMSB]; - - // Keep Verilator happy - // {{{ - // Verilator lint_on UNUSED - // Verilator coverage_off - wire unused; - assign unused = &{ 1'b0, ign_high, ign_rx_raw_ready, - ign_tx_raw_valid, ign_tx_high, ign_rx_high }; - // Verilator coverage_on - // Verialtor lint_off UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/net/netskid.v b/delete_later/rtl/net/netskid.v deleted file mode 100644 index 98f5874..0000000 --- a/delete_later/rtl/net/netskid.v +++ /dev/null @@ -1,201 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: netskid.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: An abortable skid buffer, using our network protocol. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module netskid #( - parameter DW = 32 - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire S_AXIN_VALID, - output wire S_AXIN_READY, - input wire [DW-1:0] S_AXIN_DATA, - input wire S_AXIN_LAST, - input wire S_AXIN_ABORT, - // - output reg M_AXIN_VALID, - input wire M_AXIN_READY, - output reg [DW-1:0] M_AXIN_DATA, - output reg M_AXIN_LAST, - output reg M_AXIN_ABORT - // }}} - ); - - // Local declarations - // {{{ - reg r_valid, r_last, r_abort; - reg [DW-1:0] r_data; - // }}} - - // r_valid - // {{{ - initial r_valid = 0; - always @(posedge i_clk) - if (i_reset) - r_valid <= 0; - else - r_valid <= M_AXIN_VALID && !M_AXIN_READY; - // }}} - - // r_data, r_last - // {{{ - - always @(posedge i_clk) - if (S_AXIN_READY) - { r_data, r_last } <= { S_AXIN_DATA, S_AXIN_LAST }; - // }}} - - // r_abort - // {{{ - initial r_abort = 0; - always @(posedge i_clk) - if (i_reset) - r_abort <= 0; - else if (M_AXIN_VALID && !M_AXIN_READY) - // If we are stalled - r_abort <= M_AXIN_ABORT; - else if (M_AXIN_READY) - r_abort <= 0; - // }}} - - assign S_AXIN_READY = !r_valid; - - // M_AXIN_* - // {{{ - always @(*) - begin - if (r_valid) - begin - M_AXIN_VALID = 1'b1; - M_AXIN_DATA = r_data; - M_AXIN_LAST = r_last; - - M_AXIN_ABORT = r_abort || (!r_last && S_AXIN_ABORT); - end else begin - M_AXIN_VALID = S_AXIN_VALID; - M_AXIN_DATA = S_AXIN_DATA; - M_AXIN_LAST = S_AXIN_LAST; - M_AXIN_ABORT = S_AXIN_ABORT; - end - - /* - if (i_reset) - begin - M_AXIN_VALID = 1'b0; - M_AXIN_ABORT = 1'b0; - end - */ - end - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - wire [10:0] fslv_word, fmst_word; - wire [11:0] fslv_packets, fmst_packets; - (* anyconst *) reg [DW:0] f_never_data_last; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - faxin_slave #( - .DATA_WIDTH(DW) - ) fslv ( - // {{{ - .S_AXI_ACLK(i_clk), .S_AXI_ARESETN(!i_reset), - // - .S_AXIN_VALID(S_AXIN_VALID), - .S_AXIN_READY(S_AXIN_READY), - .S_AXIN_DATA( S_AXIN_DATA), - .S_AXIN_LAST( S_AXIN_LAST), - .S_AXIN_ABORT(S_AXIN_ABORT), - // - .f_stream_word(fslv_word), - .f_packets_rcvd(fslv_packets) - // }}} - ); - - faxin_master #( - .DATA_WIDTH(DW) - ) fmst ( - // {{{ - .S_AXI_ACLK(i_clk), .S_AXI_ARESETN(!i_reset), - // - .S_AXIN_VALID(M_AXIN_VALID), - .S_AXIN_READY(M_AXIN_READY), - .S_AXIN_DATA( M_AXIN_DATA), - .S_AXIN_LAST( M_AXIN_LAST), - .S_AXIN_ABORT(M_AXIN_ABORT), - // - .f_stream_word(fmst_word), - .f_packets_rcvd(fmst_packets) - // }}} - ); - - always @(*) - if (!i_reset) - begin - if ((r_valid && r_last) || r_abort) - assert(fslv_word == 0); - else - assert(fslv_word == fmst_word + r_valid); - - if (!r_valid) - assert(!r_abort); - end - - always @(*) - if (S_AXIN_VALID) - assume({ S_AXIN_LAST, S_AXIN_DATA } != f_never_data_last); - - always @(*) - if (f_past_valid && M_AXIN_VALID) - assert({ M_AXIN_LAST, M_AXIN_DATA } != f_never_data_last); - - -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/p642pkt.v b/delete_later/rtl/net/p642pkt.v deleted file mode 100644 index de582fd..0000000 --- a/delete_later/rtl/net/p642pkt.v +++ /dev/null @@ -1,543 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: rtl/net/p642pkt.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Convert from the format at the output of the PHY (66 bits -// per clock) to an outgoing AXI network packet protocol. -// -// Note that because Xilinx GTX will be generating 66-bits at a time, -// we're skipping the 32-bit XGMII interface and going directly from a -// 66-bit interface to a 64-bit AXI network interface. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -module p642pkt ( - // {{{ - input wire RX_CLK, S_ARESETN, - // - input wire i_phy_fault, - output reg o_remote_fault, - output wire o_local_fault, - output wire o_link_up, - // - input wire RX_VALID, - input wire [65:0] RX_DATA, - // - output reg M_VALID, - input wire M_READY, - output reg [63:0] M_DATA, - output reg [2:0] M_BYTES, - output reg M_ABORT, - output reg M_LAST - // }}} - ); - - // Local declarations - // {{{ - localparam [1:0] SYNC_CONTROL = 2'b10, - SYNC_DATA = 2'b01; - localparam PRE_IDLE = 1'b0, - PRE_DATA = 1'b1; - - localparam [65:0] R_PREAMBLE = { 32'habaa_aaaa, 32'haaaa_aa1e, - SYNC_CONTROL }, - R_HALF_PREAMBLE = { 24'haaaa_aa,4'h0,28'h0000_00, 8'h33, - SYNC_CONTROL }, - R_HALF_MASK = { 24'hff_ffff, 4'h0, 28'h000_0000, 8'hff, - SYNC_CONTROL }; - // R_IDLE = { 32'h00000000, 32'h0000001e, - // SYNC_CONTROL }, - // R_LPIDLE = { 32'h06060606, 32'h0606061e, - // SYNC_CONTROL }; - localparam [23:0] REMOTE_FAULT = 24'h02; - localparam LNKMSB = 26; - - reg pstate, phalf, poffset; - - reg dly_valid, dly_last; - reg [63:0] dly_data; - reg [31:0] dly_half; - reg [3:0] dly_bytes; - - // Fault detection registers - reg r_local_fault; - reg [6:0] watchdog_counter; - reg watchdog_timeout; - reg [LNKMSB:0] link_up_counter; - - reg max_packet_fault; - reg [18:0] max_packet_counter; - - reg powering_up; - // }}} - - // Processing steps: - // (0) Unscramble the payload - // 1. Unpack control and data characters - // 2. Check control characters for validity - // 3. Classify packets - // 4. Generate START/STOP characters - // 5. Pack data words - // 6. Generate LAST and flush the packing circuit - - // pstate - // {{{ - always @(posedge RX_CLK) - if (!S_ARESETN || i_phy_fault) - pstate <= PRE_IDLE; - else if (RX_VALID) - case(pstate) - PRE_IDLE: begin - // {{{ - pstate <= PRE_IDLE; - if (RX_DATA == R_PREAMBLE - || ((RX_DATA & R_HALF_MASK) == R_HALF_PREAMBLE)) - pstate <= PRE_DATA; - if (M_VALID && !M_READY) - // Output is still hung with the previous packet. - // Drop this one and wait for the next preamble. - pstate <= PRE_IDLE; - end - // }}} - PRE_DATA: begin - if (RX_DATA[1:0] == SYNC_DATA) - pstate <= PRE_DATA; - // else if (RX_DATA == R_IDLE) - // pstate <= PRE_DATA; - else - pstate <= PRE_IDLE; - end - endcase - // }}} - - // phalf, poffset - // {{{ - // phalf == discard the first half of the next word. - // poffset == we are off-set from true. Each new data word will bring - // four bytes to output, and four bytes to reserve for the next - // cycle. - always @(posedge RX_CLK) - if (!S_ARESETN || i_phy_fault) - { phalf, poffset } <= 2'b00; - else if (RX_VALID) - case(pstate) - PRE_IDLE: begin - // {{{ - if (RX_DATA == R_PREAMBLE) - { phalf, poffset } <= 2'b00; - else if ((RX_DATA & R_HALF_MASK) == R_HALF_PREAMBLE) - { phalf, poffset } <= 2'b11; - end - // }}} - PRE_DATA: phalf <= 1'b0; - endcase - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // dly_*: The delay stage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // We need this stage because XGMII sends an "end-of-packet" indicator - // one byte after the last character, whereas our AXI-network protocol - // is supposed to guarantee M_LAST on the last beat of the packet. - // Hence, if the "end-of-packet" character shows up on byte-0, then - // we'd set M_LAST one beat too late if we didn't have this delay stage. - - // One problem: there's no guarantee of receiving 8-bytes per clock. - // The following assuming we either have 8-bytes per clock or its the - // last beat in the packet. The protocol doesn't require this. Rather, - // the protocol only requires 4-bytes per beat, allowing for the other - // 4-bytes to be stuff bytes (i.e. idles, either low-power or otherwise) - // in order to deal with clock mismatch issues. - - // Not quite. It's illegal to send IDLEs during a packet. If the - // transmitted can't keep up with the packet, the packet will be - // ABORTed. (Otherwise, we might be confuse an all IDLE control stream - // with a response to an remote_fault packet.) - - // During an packet, we should be able to expect code words: - // ALL DATA - // 8'h87 - // 8'h99 - // 8'haa - // 8'hb4 - // 8'hcc - // 8'hd2 - // 8'he1 - // 8'hff - // All but the all-data control word indicate the end of the packet. - // Any other control words will need to result in an aborted packet - - // dly_valid - // {{{ - always @(posedge RX_CLK) - if (!S_ARESETN) - dly_valid <= 0; - else if (RX_VALID) - begin - if (RX_DATA[1:0] == SYNC_DATA) - dly_valid <= 1'b1; - else if (RX_DATA[1:0] != SYNC_CONTROL) - dly_valid <= 1'b0; - else if (RX_DATA[9:2] == 8'h87) - // Unless this is a completely control frame, we're - // valid - dly_valid <= 1'b1; - else - dly_valid <= poffset; - - if (pstate != PRE_DATA || phalf) - dly_valid <= 1'b0; - end else - dly_valid <= 1'b0; - // }}} - - // dly_half - // {{{ - // Since it's posible for a packet to start on a half-64-bit boundary, - // we need a bit of a gearbox to realign the packet back onto a 64bit - // boundary. dly_half is where we stuff that extra data. - always @(posedge RX_CLK) - if (!S_ARESETN || !poffset) - dly_half <= 0; - else if (RX_VALID) - begin - dly_half <= RX_DATA[65:34]; // D4, D5, D6, D7 - - // If the word is a control word, then we're offset, based upon - // the 8'bits necessary to specify the type of control word. - // That puts our first bit at (2+32+8 = 42), not 34. So, let's - // adjust that here. - if (RX_DATA[1:0] == SYNC_CONTROL) - case(RX_DATA[9:2]) - // 8'h99: - // 8'haa: - // 8'hb4: - // 8'hcc: - 8'hd2: dly_half <= { 24'h0, RX_DATA[49:42] }; - 8'he1: dly_half <= { 16'h0, RX_DATA[57:42] }; - 8'hff: dly_half <= { 8'h0, RX_DATA[65:42] }; - default: dly_half <= 32'h0; - endcase - end - // }}} - - // dly_data - // {{{ - always @(posedge RX_CLK) - if (!S_ARESETN) - dly_data <= 0; - else if (RX_VALID) - begin - if (poffset) - begin // Gearbox. Use 32-bits from before, and up to 32-bits - // {{{ - // from the current word - dly_data <= { RX_DATA[33:2], dly_half }; - if (RX_DATA[1:0] == SYNC_CONTROL) - case(RX_DATA[9:2]) - 8'h99: dly_data[63:32] <= { 24'h0, RX_DATA[17:10] }; - 8'haa: dly_data[63:32] <= { 16'h0, RX_DATA[25:10] }; - 8'hb4: dly_data[63:32] <= { 8'h0, RX_DATA[33:10] }; - 8'hcc: dly_data[63:32] <= { RX_DATA[41:10] }; - // The rest of these have more than 32bits defined, - // but we only need 32 of the incoming bits. The other - // 32bits will be in dly_half for the next clock cycle. - 8'hd2: dly_data[63:32] <= { RX_DATA[41:10] }; - 8'he1: dly_data[63:32] <= { RX_DATA[41:10] }; - 8'hff: dly_data[63:32] <= { RX_DATA[41:10] }; - default: dly_data[63:32] <= 32'h0; - endcase - // }}} - end else begin // No gearbox, direct map 64bits to output - // {{{ - dly_data <= RX_DATA[65:2]; - if (RX_DATA[1:0] == SYNC_CONTROL) - case(RX_DATA[9:2]) - 8'h99: dly_data <= { 56'h0, RX_DATA[17:10] }; - 8'haa: dly_data <= { 48'h0, RX_DATA[25:10] }; - 8'hb4: dly_data <= { 40'h0, RX_DATA[33:10] }; - 8'hcc: dly_data <= { 32'h0, RX_DATA[41:10] }; - 8'hd2: dly_data <= { 24'h0, RX_DATA[49:10] }; - 8'he1: dly_data <= { 16'h0, RX_DATA[57:10] }; - 8'hff: dly_data <= { 8'h0, RX_DATA[65:10] }; - default: begin end - endcase - - if (pstate != PRE_DATA) - dly_data <= 0; - // }}} - end - end - // }}} - - // dly_bytes - // {{{ - // Number of valid bytes in the delay cell. - always @(posedge RX_CLK) - if (!S_ARESETN) - dly_bytes <= 0; - else if (RX_VALID) - begin - if (phalf) - dly_bytes <= 4; // These bytes are in dly_half - else if (poffset) - begin - // {{{ - dly_bytes <= 12; // dly_half + dly_data - if (RX_DATA[1:0] == SYNC_CONTROL) - case(RX_DATA[9:2]) - 8'h99: dly_bytes <= 4'd4 + 4'd1; - 8'haa: dly_bytes <= 4'd4 + 4'd2; - 8'hb4: dly_bytes <= 4'd4 + 4'd3; - 8'hcc: dly_bytes <= 4'd4 + 4'd4; - 8'hd2: dly_bytes <= 4'd4 + 4'd5; - 8'he1: dly_bytes <= 4'd4 + 4'd6; - 8'hff: dly_bytes <= 4'd4 + 4'd7; - default: begin end - endcase - - if (pstate != PRE_DATA) - dly_bytes<=(dly_bytes <= 8) ? 0 : (dly_bytes-8); - // }}} - end else begin - dly_bytes <= 4'd8; // 64 incoming bits => 8bytes - if (RX_DATA[1:0] == SYNC_CONTROL) - case(RX_DATA[9:2]) - 8'h99: dly_bytes <= 4'd1; - 8'haa: dly_bytes <= 4'd2; - 8'hb4: dly_bytes <= 4'd3; - 8'hcc: dly_bytes <= 4'd4; - 8'hd2: dly_bytes <= 4'd5; - 8'he1: dly_bytes <= 4'd6; - 8'hff: dly_bytes <= 4'd7; - default: begin end - endcase - end - end else if (dly_valid && dly_last) - dly_bytes <= 0; - // }}} - - // dly_last - // {{{ - always @(posedge RX_CLK) - if (!S_ARESETN) - dly_last <= 0; - else if (RX_VALID) - begin - dly_last <= 1'b0; - if (pstate != PRE_DATA) - dly_last <= poffset; - else if (RX_DATA[1:0] == SYNC_CONTROL && !poffset) - dly_last <= 1'b1; - end else - dly_last <= 1'b0; - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Fault detection - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - // Local & Remote fault detection - // {{{ - // These faults are all determined by the data sent. If no data - // gets sent, or if we never lock (and hence RX_VALID stays low), - // then we'll never know a fault - initial o_remote_fault = 1'b0; - always @(posedge RX_CLK) - if (!S_ARESETN) - begin - o_remote_fault <= 1'b0; - r_local_fault <= 1'b0; - end else if (RX_VALID) - begin - case(RX_DATA[9:2]) - 8'h2d: o_remote_fault <= (RX_DATA[65:42] == REMOTE_FAULT); - // 8'h66: // The fault must've been cleared by data start, - // or data wouldn't be starting - 8'h55: o_remote_fault <= (RX_DATA[65:42] == REMOTE_FAULT); - 8'h4b: o_remote_fault <= (RX_DATA[33:10] == REMOTE_FAULT); - default: o_remote_fault <= 1'b0; - endcase - - if (RX_DATA[1:0] != SYNC_CONTROL) - o_remote_fault <= 1'b0; - - case(RX_DATA[9:2]) - 8'h1e: r_local_fault <= 1'b0; - 8'h2d: r_local_fault <= (RX_DATA[65:42] != REMOTE_FAULT); - 8'h33: r_local_fault <= 1'b0; - 8'h66: r_local_fault <= (RX_DATA[33:10] != REMOTE_FAULT); - 8'h55: r_local_fault <= (RX_DATA[65:42] != REMOTE_FAULT); - 8'h78: r_local_fault <= 1'b0; - 8'h4b: r_local_fault <= (RX_DATA[33:10] != REMOTE_FAULT); - 8'h87: r_local_fault <= 1'b0; - 8'h99: r_local_fault <= 1'b0; - 8'haa: r_local_fault <= 1'b0; - 8'hb4: r_local_fault <= 1'b0; - 8'hcc: r_local_fault <= 1'b0; - 8'hd2: r_local_fault <= 1'b0; - 8'he1: r_local_fault <= 1'b0; - 8'hff: r_local_fault <= 1'b0; - default: r_local_fault <= 1'b1; - endcase - - if (RX_DATA[1:0] != SYNC_CONTROL) - r_local_fault <= 1'b0; - end - // }}} - - // watchdog_timeout - // {{{ - // If the PHY never produces any data for us, then we have a watchdog - // error condition. - always @(posedge RX_CLK) - if (!S_ARESETN) - begin - watchdog_counter <= -1; - watchdog_timeout <= 0; - end else if (RX_VALID) - begin - watchdog_counter <= -1; - watchdog_timeout <= 0; - end else begin - if (watchdog_counter > 0) - watchdog_counter <= watchdog_counter - 1; - watchdog_timeout <= (watchdog_counter <= 1); - end - // }}} - - // max_packet_fault - // {{{ - // It is a fault to have a continuous packet with no control characters. - // In this case, our maximum packet length is still excessively large, - // set (above) at 2^19 words, or 2^22 (4MB) bytes. - always @(posedge RX_CLK) - if (!S_ARESETN) - begin - max_packet_counter <= 0; - max_packet_fault <= 0; - end else if (RX_VALID) - begin - if (RX_DATA[1:0] == SYNC_CONTROL) - begin - max_packet_counter <= -1; - max_packet_fault <= 0; - end else if (max_packet_counter != 0) - begin - max_packet_counter <= max_packet_counter - 1; - max_packet_fault <= (max_packet_counter <= 1); - end - end - // }}} - - // link_up_counter--used to stretch faults and errors so the eye can - // see them - // {{{ - always @(posedge RX_CLK or negedge S_ARESETN) - if (!S_ARESETN) - link_up_counter <= 0; - else if (watchdog_timeout || o_remote_fault || o_local_fault - || max_packet_fault || powering_up) - link_up_counter <= 0; - else if (!link_up_counter[LNKMSB]) - link_up_counter <= link_up_counter+1; - // else - // link is solidly good - // }}} - - always @(posedge RX_CLK or negedge S_ARESETN) - if (!S_ARESETN) - powering_up <= 1'b1; - else if (RX_VALID) - powering_up <= 1'b0; - - assign o_link_up = link_up_counter[LNKMSB]; - - assign o_local_fault = (powering_up || r_local_fault - || watchdog_timeout); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // M_*: The final output - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge RX_CLK) - if (!S_ARESETN) - M_VALID <= 0; - else if (!M_VALID || M_READY) - M_VALID <= dly_valid && (RX_VALID || dly_last); - - always @(posedge RX_CLK) - if (!M_VALID || M_READY) - begin - M_DATA <= dly_data; - M_BYTES<= dly_bytes[2:0]; - M_LAST <= dly_last || (RX_DATA[9:0] == { 8'h87, SYNC_CONTROL }); - end - - always @(posedge RX_CLK) - if (!S_ARESETN) - M_ABORT <= 1'b0; - else if (RX_VALID && dly_valid && M_VALID && !M_READY) - M_ABORT <= 1'b1; - else if (i_phy_fault && ((dly_valid && !dly_last) - || (M_VALID && !M_READY && !M_LAST))) - M_ABORT <= 1'b1; - else if (dly_valid && !M_ABORT) - begin - if (dly_last) - M_ABORT <= 1'b0; - else if (RX_DATA[1:0] == SYNC_CONTROL) - begin - case(RX_DATA[9:2]) - 8'h87: begin end - 8'h99: begin end - 8'haa: begin end - 8'hb4: begin end - 8'hcc: begin end - 8'hd2: begin end - 8'he1: begin end - 8'hff: begin end - default: M_ABORT <= 1'b1; - endcase - end - end else if (!M_VALID || M_READY) - M_ABORT <= 1'b0; - // }}} -endmodule diff --git a/delete_later/rtl/net/p64bscrambler.v b/delete_later/rtl/net/p64bscrambler.v deleted file mode 100644 index 02fe9ef..0000000 --- a/delete_later/rtl/net/p64bscrambler.v +++ /dev/null @@ -1,130 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: rtl/net/p64bscrambler.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// ETHERNET is an LSB first protocol. Bit 0 of byte 0 is always "first". -// This scrambler preserves that ordering, but does expect bit 0 of byte 0 -// to be found in position [0]. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -module p64bscrambler #( - // {{{ - localparam POLYNOMIAL_BITS=58, - // Poly = (1<<38) ^ (1<<57) - localparam [POLYNOMIAL_BITS-1:0] POLYNOMIAL - = 58'h200_0040_0000_0000, - localparam DATA_WIDTH=66, - parameter [0:0] OPT_RX = 0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset_n, - // - input wire i_valid, - output wire o_ready, - input wire [DATA_WIDTH-1:0] i_data, - // - output reg o_valid, - input wire i_ready, - output reg [DATA_WIDTH-1:0] o_data - // }}} - ); - - // Local declarations - // {{{ - localparam PB = POLYNOMIAL_BITS; - localparam DW = DATA_WIDTH; - - reg [PB-1:0] r_fill; - wire [PB-1:0] next_fill; - wire [DW-1:0] scrambled; - // }}} - - assign { next_fill, scrambled } = SCRAMBLE(r_fill, i_data); - - // r_fill - // {{{ - always @(posedge i_clk) - if (!i_reset_n) - r_fill <= 0; - else if (i_ready) - // Self synchronizing - r_fill <= next_fill; - // }}} - - // o_valid - // {{{ - always @(posedge i_clk) - if (!i_reset_n) - o_valid <= 0; - else if (i_valid) - o_valid <= 1'b1; - else if (o_ready) - o_valid <= 1'b0; - // }}} - - // o_data - // {{{ - always @(posedge i_clk) - if (!i_reset_n) - o_data <= 0; - else if (i_ready) - o_data <= scrambled; - // }}} - - assign o_ready = !o_valid || i_ready; - - function automatic [PB+DW-1:0] SCRAMBLE( - // {{{ - input [PB-1:0] s_fill, - input [DW-1:0] s_data); - - integer ik; - reg [DW-1:0] data_out; - reg [PB-1:0] state; - begin - data_out = 0; - data_out[1:0] = s_data[1:0]; - state = s_fill; - for(ik=2; ik= *readptr) -// no more chunks follow -// else -// chunk_two_size = *readptr - chunk_one_size -// chunk_two_addr = baseaddr -// -// 5. Once you are done processing the packet, set your readptr address to -// -// readptr += *readptr; -// if (readptr >= baseaddr + memsize) -// readptr -= memsize; -// -// This is essentially a call to free(), and lets the controller -// know it has more memory available to put packets into. -// -// 6. Next, read the new packet length from this address. -// If it is != 0, there's another packet--process as in #4 above. -// If it is == 0, there are no more packets. Return to #3 above -// to wait for the next packet. -// -// The network will go into an error condition should it ever receive a -// bus error while writing to the memory range given to it. On an error -// condition, simply adjust the range to something valid and start over. -// -// Registers: -// 0: Base address -// Will be rounded up to the nearest word. Therefore, -// this address must be aligned to the bus width. (Not -// always the neareset 32-bits.) A base address of zero -// will turn the packet DMA off -// 4: {ERR, Memory size } -// As with the base address, this value needs to be aligned -// to the nearest bus word--which won't always be 32-bits. -// A size of zero will turn the packet DMA off. A -// Wishbone (bus) error will also turn the packet DMA off. -// Errors may be cleared and the DMA restarted by writing -// a new base address or size. -// 8: Write pointer (read only) -// Set to zero on error or when idle. At all other times, -// the write pointer will be somewhere between the base -// address and the base address plus the allocated memory -// size. -// 12: Read pointer (Read/write, controlled by CPU) -// This is the CPU's half of the FIFO pointers. It is -// primarily used to keep the FIFO from being overrun. -// Once the CPU finishes reading/processing a packet, it -// should set this address to the pointer address following -// the packet. This way, if a new packet arrives that -// would overwrite the memory at the read pointer's -// address, then that packet will be dropped. -// -// This value will be reset to the base address any time -// the base address or memory size are updated. -// -// All addresses must be 32b aligned. -// -// Status: The formal proof below (was at one time) full and complete. -// It's only fault was that it didn't track the packet word -// through the FIFO during induction. With a more open FIFO model, or -// the commercial front end, this could be fixed. This design has not -// (yet) been tested in either hardware or simulation. -// -// Since that time, the design has been modified to handle packet widths -// larger than 32-bits. No attempt has been made to redo the proof since. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module pkt2mem #( - // {{{ - parameter DW = 512, - parameter AW = 31-$clog2(DW/8),// Max address width is 2GB - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter [0:0] OPT_LOWPOWER = 1'b0, - parameter LGFIFO = 7, - parameter PKTDW = 128, // Must be PKTDW <= DW - parameter BURSTSZ = (1<<(LGFIFO-1)), - parameter LGPIPE = 7 // Allow 128 outstanding beats - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Incoming bus (slave) control interface - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [1:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - // - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // }}} - // Incoming packets - // {{{ - input wire S_AXIN_VALID, - output wire S_AXIN_READY, - input wire [PKTDW-1:0] S_AXIN_DATA, - input wire [$clog2(PKTDW/8)-1:0] S_AXIN_BYTES, - input wire S_AXIN_LAST, - input wire S_AXIN_ABORT, - // }}} - // Outgoing bus (master) DMA interface - // {{{ - output reg o_dma_cyc, - output reg o_dma_stb, - output wire o_dma_we, - output reg [AW-1:0] o_dma_addr, - output reg [DW-1:0] o_dma_data, - output reg [DW/8-1:0] o_dma_sel, - input wire i_dma_stall, - input wire i_dma_ack, - input wire [DW-1:0] i_dma_data, - input wire i_dma_err, - // }}} - output reg o_int - // }}} - ); - - // Local declarations - // {{{ - localparam [2:0] S_CLEARPTR = 3'b000, - S_IDLE = 3'b001, - S_PKTACTIVE = 3'b010, - S_PKTPAUSED = 3'b011, - S_NULL = 3'b100, - S_LENGTH = 3'b101; - - localparam BLSB = $clog2(DW/8), // Bus LSB - LSB = $clog2(DW/32), - WBLSB = 2; - localparam [1:0] ADR_BASEADDR = 2'b00, - ADR_SIZE = 2'b01, - ADR_WRITEPTR = 2'b10, - ADR_READPTR = 2'b11; - integer ik; - - reg r_err, r_dma_reset, r_validptr; - reg [AW-1:0] r_baseaddr, r_memsize, next_dma_addr; - reg [AW+LSB-1:0] r_writeptr, r_readptr, r_newstart; - reg [AW:0] space_available, r_lastaddr; - reg [AW+LSB:0] first_dma_addr; - reg [AW+LSB:0] next_start_addr; - - reg wfifo_write; - reg [3+LSB+(DW/32)+DW-1:0] wfifo_data; - - reg pkt_valid, pkt_abort, pkt_midpacket; - reg [1:0] pkt_last; - reg [LSB-1:0] pkt_start; - reg [LSB:0] pkt_addr; - reg [(DW/32)-1:0] pkt_keep; - reg [DW-1:0] pkt_data; - reg [(PKTDW/32)-1:0] pkt_nxkp; - reg [PKTDW-1:0] pkt_next; - - - reg [LGPIPE:0] wb_outstanding; - reg wb_pipeline_full, abort_write_packet, - mem_exhausted; - wire mem_full; - - reg [2:0] wr_state; - // reg mid_packet; - wire start_burst; - - reg [LGFIFO:0] fifo_pkts; - reg [AW+BLSB-1:0] pkt_length; - - wire fifo_read, fifo_valid; - - wire fif_full, fif_empty; - wire [LGFIFO:0] fif_fill; - wire fif_abort, fif_last; - wire [LSB:0] fif_addr; - wire [DW-1:0] fif_data; - wire [DW/32-1:0] fif_keep; - reg [DW/8-1:0] fif_sel; - - - wire [AW-1:0] i_bus_addr; - wire [AW+BLSB-WBLSB-1:0] i_word_addr; - wire [AW+BLSB-1:0] full_baseaddr; - wire [AW+BLSB-1:0] full_writeptr, full_readptr; - wire [AW+BLSB:0] full_lastaddr; - wire [AW-1:0] bus_writeptr, bus_readptr; - reg pre_wfifo_write; - wire wfifo_last, wfifo_abort; - reg r_wfifo_midpacket; - wire wfifo_midpacket; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone control handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // r_dma_reset, r_baseaddr, r_memsize, r_err, r_readptr - // {{{ - - assign i_bus_addr = i_wb_data[AW+BLSB-1:BLSB]; - assign i_word_addr = i_wb_data[AW+BLSB-1:WBLSB]; - - assign full_baseaddr = { r_baseaddr, {(BLSB){1'b0}} }; - assign full_lastaddr = { r_lastaddr, {(BLSB){1'b0}} }; - assign full_writeptr = { r_writeptr, {(WBLSB){1'b0}} }; - assign full_readptr = { r_readptr, {(WBLSB){1'b0}} }; - assign bus_writeptr = full_writeptr[AW+BLSB-1:BLSB]; - assign bus_readptr = full_readptr[AW+BLSB-1:BLSB]; - - initial r_dma_reset = 1; - initial r_baseaddr = 0; - initial r_memsize = 0; - initial r_lastaddr = 0; - initial r_validptr = 0; - always @(posedge i_clk) - begin - // We are in reset following an error, or any time the - // read pointer is out of bounds. - // {{{ - r_dma_reset <= r_err || (r_baseaddr == 0)||(r_memsize == 0); - if (r_readptr[AW+LSB-1:LSB] < r_baseaddr) - r_dma_reset <= 1'b1; - if ({ 1'b0, r_readptr[AW+LSB-1:LSB] } >= r_lastaddr) - r_dma_reset <= 1'b1; - if (r_lastaddr >= (1<= r_baseaddr) - && ({ 1'b0, r_readptr[AW+LSB-1:LSB] } < r_lastaddr ); - - if (i_wb_stb && i_wb_we) - begin - case(i_wb_addr) - ADR_BASEADDR: begin - // {{{ - if (i_wb_sel == 4'hf) - begin - r_baseaddr <= i_bus_addr; - r_lastaddr <= i_bus_addr - + r_memsize; - end else if (i_wb_sel != 0) - begin - r_baseaddr <= 0; - r_lastaddr <= { 1'b0, r_memsize }; - end - - if (i_wb_sel != 0) - begin - r_dma_reset <= 1'b1; - r_err <= 0; - end end - // }}} - ADR_SIZE: begin - // {{{ - if (i_wb_sel == 4'hf) - begin - r_memsize <= i_bus_addr; - r_lastaddr <= r_baseaddr + i_bus_addr; - end else if (i_wb_sel != 0) - begin - r_memsize <= 0; - r_lastaddr <= { 1'b0, r_baseaddr }; - end - - if (i_wb_sel != 0) - begin - r_dma_reset <= 1'b1; - r_err <= 0; - end end - // }}} - ADR_WRITEPTR: begin end // Read only register - ADR_READPTR: begin - // {{{ - if (i_wb_sel == 4'hf) - begin - r_readptr <= i_word_addr; - r_validptr <= (i_bus_addr >= r_baseaddr) - && ({ 1'b0, i_bus_addr } < r_lastaddr); - end end - // }}} - endcase - end - - if (o_dma_cyc && i_dma_err) - r_err <= 1'b1; - - if (i_reset) - begin - // {{{ - r_dma_reset <= 1'b1; - r_baseaddr <= 0; - r_memsize <= 0; - r_lastaddr <= 0; - r_err <= 0; - r_validptr <= 0; - // }}} - end - end - // }}} - - // o_wb_data - // {{{ - initial o_wb_data = 0; - always @(posedge i_clk) - if (!OPT_LOWPOWER || (i_wb_stb && !i_wb_we)) - begin - o_wb_data <= 0; - case(i_wb_addr) - ADR_BASEADDR: o_wb_data[AW+BLSB-1:BLSB] <= r_baseaddr; - ADR_SIZE: begin - o_wb_data[31] <= r_err; - o_wb_data[AW+BLSB-1:BLSB] <= r_memsize; - end - ADR_WRITEPTR: o_wb_data[AW+BLSB-1:WBLSB] <= r_writeptr; - ADR_READPTR: o_wb_data[AW+BLSB-1:WBLSB] <= r_readptr; - endcase - end - // }}} - - assign o_wb_stall = 1'b0; - - // o_wb_ack - // {{{ - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_ack <= 1'b0; - else - o_wb_ack <= i_wb_stb && !o_wb_stall; - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Pack 32-bit-wide packets into bus words - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - begin - pre_wfifo_write = 1'b0; - if (pkt_valid && pkt_last != 2'b00 && !pkt_abort) - pre_wfifo_write = 1'b1; - if (OPT_LITTLE_ENDIAN && pkt_keep[0]) - pre_wfifo_write = 1'b1; - if (!OPT_LITTLE_ENDIAN && pkt_keep[(DW/32)-1]) - pre_wfifo_write = 1'b1; - end - - // pkt_midpacket - // {{{ - always @(posedge i_clk) - if (i_reset) - pkt_midpacket <= 1'b0; - else if (S_AXIN_ABORT && (!S_AXIN_VALID || S_AXIN_READY)) - pkt_midpacket <= 1'b0; - else if (S_AXIN_VALID && S_AXIN_READY) - pkt_midpacket <= !S_AXIN_LAST && !S_AXIN_ABORT; - // }}} - - // pkt_* - // {{{ - reg [$clog2(PKTDW/8)-1:0] s_words; - reg [PKTDW/32-1:0] s_mask; - reg [DW+PKTDW-1:0] next_data_sreg; - reg [(DW+PKTDW)/32-1:0] next_keep_sreg; - - always @(*) - begin - s_words = S_AXIN_BYTES + 1; - s_words = s_words >> 2; - - s_mask = ({ {(PKTDW/32-1){1'b0}}, 1'b1 } << s_words) - 1; - if (S_AXIN_LAST) - s_mask = {(PKTDW/32){1'b1}}; - end - - always @(*) - if (OPT_LITTLE_ENDIAN) - begin - next_data_sreg = { {(DW){1'b0}}, pkt_next } - | { {(DW){1'b0}}, S_AXIN_DATA } - << (pkt_addr*32); - next_keep_sreg = { {(DW/32){1'b0}}, pkt_nxkp } - | ({ {(DW/32){1'b0}}, s_mask } << pkt_addr); - end else begin - next_data_sreg = { pkt_next, {(DW){1'b0}} } - | { S_AXIN_DATA, {(DW){1'b0}} } - >> (pkt_addr*32); - - next_keep_sreg = { pkt_nxkp, {(DW/32){1'b0}} } - | ({ s_mask, {(DW/32){1'b0}} } >> pkt_addr); - end - - initial pkt_valid = 0; - initial pkt_keep = 0; - initial pkt_data = 0; - initial pkt_addr = 0; - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - pkt_valid <= 0; - pkt_start <= 1; - pkt_addr <= 1; // First data has position '1' in the word - pkt_keep <= 0; - pkt_data <= 0; - pkt_next <= 0; - pkt_nxkp <= 0; - pkt_last <= 2'b00; - // }}} - end else if (r_dma_reset || (pkt_abort && pkt_midpacket)) - begin - // {{{ - pkt_valid <= 0; - pkt_abort <= pkt_midpacket || (S_AXIN_VALID && S_AXIN_READY - && !S_AXIN_LAST && !S_AXIN_ABORT); - pkt_addr <= 1; - pkt_start <= 1; - - pkt_keep <= 0; - pkt_data <= 0; - pkt_next <= 0; - pkt_nxkp <= 0; - pkt_last <= 2'b00; - // }}} - end else if (S_AXIN_VALID && S_AXIN_READY) - begin - // {{{ - pkt_valid <= 1; - pkt_last <= 2'b00; - - // Clear on any new word - // {{{ - if (pkt_last[1] - || (OPT_LITTLE_ENDIAN && pkt_keep[0]) - || (!OPT_LITTLE_ENDIAN && pkt_keep[(DW/32)-1])) - begin - pkt_addr <= 0; - pkt_keep <= 0; - pkt_data <= 0; - end - // }}} - - pkt_addr <= pkt_addr[LSB-1:0] + 1; - - // Add to pkt_data and pkt_keep - // {{{ - if (OPT_LITTLE_ENDIAN) - begin - { pkt_next, pkt_data } <= next_data_sreg; - { pkt_nxkp, pkt_keep } <= next_keep_sreg; - end else begin - { pkt_data, pkt_next } <= next_data_sreg; - { pkt_keep, pkt_nxkp } <= next_keep_sreg; - end - // }}} - - if (S_AXIN_ABORT) - begin - // {{{ - pkt_abort <= 1'b1; - pkt_addr <= { 1'b0, pkt_start }; - pkt_keep <= 0; - pkt_data <= 0; - pkt_last <= 2'b10; - // }}} - end else if (S_AXIN_LAST) - begin - // {{{ - pkt_start <= pkt_addr[LSB-1:0]+2; - pkt_addr <= pkt_addr[LSB-1:0]+2; - if (OPT_LITTLE_ENDIAN) - begin - pkt_last <= (next_keep_sreg[(PKTDW+DW)/32-1:DW/32-1] != 0) ? 2'b01 : 2'b10; - end else begin - pkt_last <= (next_keep_sreg[PKTDW/32-1:0] != 0) ? 2'b01 : 2'b10; - end - // }}} - end - // }}} - end else if (pre_wfifo_write) - begin - // {{{ - pkt_valid <= !pkt_abort && (pkt_nxkp != 0); - pkt_abort <= pkt_midpacket; - pkt_last[0]<= 1'b0; - pkt_last[1]<= pkt_last[0] && (pkt_nxkp != 0); - - if (OPT_LITTLE_ENDIAN) - begin - { pkt_next, pkt_data }<= { {(DW){1'b0}}, pkt_next }; - { pkt_nxkp, pkt_keep }<= { {(DW/32){1'b0}},pkt_nxkp }; - end else begin - { pkt_data, pkt_next }<= { pkt_next,{(DW ){1'b0}} }; - { pkt_keep, pkt_nxkp }<= { pkt_nxkp,{(DW/32){1'b0}} }; - end - // }}} - end - // }}} - - // wfif_* - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - wfifo_write <= 1'b0; - end else if (pre_wfifo_write - || ((pkt_abort || r_dma_reset) && wfifo_midpacket)) - begin - wfifo_write <= 1'b1; - end else if (!fif_full) - wfifo_write <= 0; - - always @(posedge i_clk) - if (pre_wfifo_write || pkt_abort || r_dma_reset) - begin - wfifo_data <= { (pkt_abort || r_dma_reset),pkt_last[1],pkt_addr, - pkt_keep, pkt_data }; - end - - always @(posedge i_clk) - if (i_reset) - r_wfifo_midpacket <= 1'b0; - else if (wfifo_write) - r_wfifo_midpacket <= !wfifo_last && !wfifo_abort; - - assign wfifo_midpacket = r_wfifo_midpacket - || (wfifo_write && !wfifo_last && !wfifo_abort); - assign wfifo_last = wfifo_data[DW+(DW/32)+LSB+1]; - assign wfifo_abort = wfifo_data[DW+(DW/32)+LSB+2]; - // }}} - - assign S_AXIN_READY = !fif_full || !wfifo_write; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Push data to a (Synchronous) FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - sfifo #( - .BW(3+LSB+(DW/32)+DW), .LGFLEN(LGFIFO), .OPT_ASYNC_READ(1'b0) - ) u_fifo ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_wr(wfifo_write), .i_data(wfifo_data), - .o_full(fif_full), .o_fill(fif_fill), - // - .i_rd(fifo_read), - .o_data({ fif_abort, fif_last, fif_addr, fif_keep, fif_data }), - .o_empty(fif_empty) - // }}} - ); - - assign fifo_valid = !fif_empty; - assign fifo_read = abort_write_packet || ((wr_state == S_PKTACTIVE) - && (!o_dma_stb || !i_dma_stall) && !fif_empty - && !wb_pipeline_full && !mem_full); - - // fif_sel, expand fif_keep by swapping every 1'b1 for a 4'hf - // {{{ - always @(*) - begin - fif_sel = 0; - for(ik=0; ik= r_lastaddr) - next_dma_addr = r_baseaddr; - - first_dma_addr = { 1'b0, r_writeptr } + 1; - if (first_dma_addr >= { r_lastaddr, {(LSB){1'b0}} }) - first_dma_addr = { 1'b0, r_baseaddr, {(LSB){1'b0}} }; - - next_start_addr = 0; - next_start_addr[AW+LSB:LSB] = r_newstart[AW+LSB-1:LSB] - + (fif_addr[LSB] ? 1:0); - next_start_addr[LSB-1:0] = fif_addr[LSB-1:0]; - if (next_start_addr[AW+LSB:LSB] >= r_lastaddr) - next_start_addr[AW+LSB:LSB] = r_lastaddr; - end - - // Verilator lint_off WIDTH - assign start_burst = (fifo_valid - && (fifo_pkts >0 || fif_fill >= BURSTSZ) - && !wb_pipeline_full && !mem_full); - // Verilator lint_on WIDTH - - initial wr_state = S_IDLE; - initial o_dma_cyc = 1'b0; - initial o_dma_stb = 1'b0; - initial o_dma_addr = 0; - initial o_dma_data = 0; - initial r_writeptr = 0; - initial pkt_length = 0; - always @(posedge i_clk) - if (i_reset || (o_dma_cyc && i_dma_err)) - begin - // {{{ - wr_state <= S_IDLE; - o_dma_cyc <= 1'b0; - o_dma_stb <= 1'b0; - o_dma_addr <= 0; - o_dma_data <= 0; - r_writeptr <= 0; - pkt_length <= 0; - r_newstart <= 0; - // }}} - end else if (r_dma_reset) - begin // Like reset, save we allow ourselves to restart from r_baseaddr - // {{{ - wr_state <= S_CLEARPTR; - o_dma_cyc <= 1'b0; - o_dma_stb <= 1'b0; - o_dma_addr <= r_baseaddr; - r_writeptr <= { r_baseaddr, {(BLSB-WBLSB){1'b0}} }; - r_newstart <= { r_baseaddr, {(BLSB-WBLSB){1'b0}} }; - o_dma_data <= 0; - pkt_length <= 0; - // }}} - end else if (abort_write_packet) - begin - // {{{ - wr_state <= S_IDLE; - o_dma_cyc <= 1'b0; - o_dma_stb <= 1'b0; - o_dma_addr <= bus_writeptr; - o_dma_data <= 0; - pkt_length <= 0; - r_newstart <= r_writeptr; - // }}} - end else if (!o_dma_stb || !i_dma_stall) - begin - o_dma_cyc <= o_dma_cyc && (wb_outstanding + (o_dma_stb ? 1:0) > (i_dma_ack ? 1:0)); - o_dma_stb <= 1'b0; - o_dma_data <= fif_data; - o_dma_sel <= fif_sel; - - case(wr_state) - S_CLEARPTR: begin - // {{{ - // Clear the write pointer at the beginning of the - // packet to zero. This isn't strictly necessary, - // since the CPU can read our writeptr and know we - // haven't gone past it, but it is a secondary - // indication of the packet length, and should allow the - // CPU to operate on a linked list basis without - // reading the writeptr as often. - wr_state <= S_IDLE; - o_dma_cyc <= 1'b1; - o_dma_stb <= 1'b1; - o_dma_addr <= bus_writeptr; - o_dma_data <= 0; - r_newstart <= r_writeptr; - pkt_length <= 0; - if (LSB == 0) - begin - o_dma_sel <= {(DW/8){1'b1}}; - end else if (OPT_LITTLE_ENDIAN) - begin - o_dma_sel <= { {(DW/8-4){1'b0}}, 4'hf } << (4*r_writeptr[LSB-1:0]); - end else begin - o_dma_sel <= { 4'hf, {(DW/8-4){1'b0}} } >> (4*r_writeptr[LSB-1:0]); - end end - // }}} - S_IDLE: begin - // {{{ - o_dma_stb <= 1'b0; - o_dma_addr <= first_dma_addr[AW+LSB-1:LSB]; - // o_dma_data <= fif_data; - // o_dma_sel <= fif_sel; - r_newstart <= r_writeptr; - - pkt_length <= 4; // Allocate room for the pointer - - if (start_burst) - begin - wr_state <= S_PKTACTIVE; - end end - // }}} - S_PKTACTIVE: begin - // {{{ - if (o_dma_stb) - o_dma_addr <= next_dma_addr; - // o_dma_data <= fif_data; - // o_dma_sel <= fif_sel; - - if (!fifo_read) - begin - o_dma_stb <= 0; - // o_dma_addr <= o_dma_addr; - wr_state <= S_PKTPAUSED; - pkt_length <= pkt_length; - end else begin - o_dma_cyc <= 1'b1; - o_dma_stb <= 1'b1; - - r_newstart <= next_start_addr[AW+LSB-1:0]; - // Verilator lint_off WIDTH - pkt_length <= pkt_length + COUNTONES(fif_keep); - // Verilator lint_on WIDTH - - if (fif_last) - wr_state <= S_NULL; - end end - // }}} - S_PKTPAUSED: begin // Wait to be able to continue again - // {{{ - o_dma_stb <= 1'b0; - o_dma_addr <= o_dma_addr; - o_dma_data <= fif_data; - o_dma_sel <= fif_sel; - - if (start_burst) - begin - wr_state <= S_PKTACTIVE; - end end - // }}} - S_NULL: begin // Write the NULL length byte for the next packet - // {{{ - o_dma_data <= 0; - if (LSB == 0) - begin - o_dma_sel <= {(DW/8){1'b1}}; - end else if (OPT_LITTLE_ENDIAN) - begin - o_dma_sel <= { {(DW/8-4){1'b0}}, 4'hf } << (4*r_newstart[BLSB-WBLSB-1:0]); - end else begin - o_dma_sel <= { 4'hf, {(DW/8-4){1'b0}} } >> (4*r_newstart[BLSB-WBLSB-1:0]); - end - - if (!mem_full && !wb_pipeline_full) - begin - o_dma_cyc <= 1'b1; - o_dma_stb <= 1'b1; - o_dma_addr <= r_newstart[AW+LSB-1:LSB]; - wr_state <= S_LENGTH; - { o_dma_cyc, o_dma_stb } <= 2'b11; - end end - // }}} - S_LENGTH: begin // Go back & write the len word for this pkt - // {{{ - if (!wb_pipeline_full) - begin - o_dma_cyc <= 1'b1; - o_dma_stb <= 1'b1; - end - o_dma_addr <= bus_writeptr; - o_dma_data <= {(DW/32){ {(32-AW-BLSB){1'b0}}, pkt_length}}; - if (LSB == 0) - begin - o_dma_sel <= {(DW/8){1'b1}}; - end else if (OPT_LITTLE_ENDIAN) - begin - o_dma_sel <= { {(DW/8-4){1'b0}}, 4'hf } << (4*r_writeptr[LSB-1:0]); - end else begin - o_dma_sel <= { 4'hf, {(DW/8-4){1'b0}} } >> (4*r_writeptr[LSB-1:0]); - end - - if (!wb_pipeline_full) - begin - r_writeptr <= r_newstart; - - wr_state <= S_IDLE; - pkt_length <= 0; - end end - // }}} - default: begin // Duplicate S_IDLE - // {{{ - o_dma_stb <= 1'b0; - o_dma_addr <= bus_writeptr; - r_newstart <= r_writeptr; - o_dma_data <= fif_data; - - pkt_length <= 0; - wr_state <= S_IDLE; - end - // }}} - endcase - end - - // wb_outstanding, wb_pipeline_full - // {{{ - localparam WBLIMIT = (1<= WBLIMIT-1); - end - 2'b01: begin - wb_outstanding <= wb_outstanding - 1; - wb_pipeline_full <= (wb_outstanding > WBLIMIT); - end - default: begin end - endcase - // }}} - - assign o_dma_we = 1'b1; - - // space_available - // {{{ - always @(posedge i_clk) - begin - if (r_dma_reset || r_readptr == r_writeptr) - space_available <= { 1'b0, r_memsize }; - else if (!r_validptr) - space_available <= 0; - else if (r_readptr > r_writeptr) - // Verilator lint_off WIDTH - space_available <= (r_readptr - r_writeptr) >> (BLSB-WBLSB); - else - space_available <= r_memsize - + ((r_readptr - r_writeptr) >> (BLSB-WBLSB)); - // Verilator lint_on WIDTH - - mem_exhausted <= pkt_length[AW+BLSB-1:BLSB] - + (|pkt_length[BLSB-1:0] ? 1:0) + 2 > r_memsize; - end - // }}} - - assign mem_full = pkt_length[AW+BLSB-1:BLSB] + 2 > space_available; - - // abort_write_packet - // {{{ - always @(posedge i_clk) - if (i_reset || r_dma_reset) - abort_write_packet <= 0; - else if (abort_write_packet) - begin - if (fifo_valid && fifo_read && (fif_last || fif_abort)) - abort_write_packet <= 0; - end else if (mem_exhausted || (o_dma_cyc && i_dma_err)) - abort_write_packet <= 1; - // }}} - - // o_int - // {{{ - always @(posedge i_clk) - if (i_reset || r_dma_reset) - o_int <= 0; - else - o_int <= (r_readptr != r_writeptr) || r_err; - // }}} - - // }}} - - function automatic [$clog2(DW/32):0] COUNTONES(input [(DW/32)-1:0] kp); - integer ck; - reg [$clog2(DW/32):0] cnt; - begin - cnt=0; - for(ck=0; ck<(DW/32); ck=ck+1) - if (kp[ck]) - cnt=cnt+1; - COUNTONES = cnt; - end endfunction - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_dma_data, i_wb_data, - full_readptr[5:0], bus_readptr, - full_baseaddr, full_writeptr, full_lastaddr }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`ifdef BMC -`define BMC_ASSERT assert -`else -`define BMC_ASSERT assume -`endif - reg f_past_valid; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - begin - assume(i_reset); - end - - //////////////////////////////////////////////////////////////////////// - // - // Incoming network stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - localparam F_MAXPKT = (1<<20)-5; // An arbitrary number - localparam F_LGMXPKT = $clog2(F_MAXPKT); - - wire [F_LGMXPKT-1:0] fnet_word; - wire [12-1:0] fnet_packets; - - faxin_slave #( - .DATA_WIDTH(32), .MAX_LENGTH(F_MAXPKT), .MIN_LENGTH(5) - ) fnet ( - // {{{ - .S_AXI_ACLK(i_clk), .S_AXI_ARESETN(!i_reset), - // - .S_AXIN_VALID(S_AXIN_VALID), - .S_AXIN_READY(S_AXIN_READY), - .S_AXIN_DATA( S_AXIN_DATA), - .S_AXIN_LAST( S_AXIN_LAST), - .S_AXIN_ABORT(S_AXIN_ABORT), - // - .f_stream_word(fnet_word), - .f_packets_rcvd(fnet_packets) - // }}} - ); - -/* - always @(posedge i_clk) - if (fnet_word == 0 && !S_AXIN_ABORT) - begin - assert(pkt_keep == 0); - assert(pkt_addr == 0); - end -*/ - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone bus properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - localparam F_LGDEPTH = LGPIPE+1; - wire [1:0] fwb_nreqs, fwb_nacks, fwb_outstanding; - wire [F_LGDEPTH-1:0] fdma_nreqs, fdma_nacks, fdma_outstanding; - - fwb_slave #( - .DW(32), .AW(2), .F_LGDEPTH(2) - ) fwb ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(i_wb_cyc), .i_wb_stb(i_wb_stb), .i_wb_we(i_wb_we), - .i_wb_addr(i_wb_addr), .i_wb_data(i_wb_data), - .i_wb_sel(i_wb_sel), - .i_wb_stall(o_wb_stall), .i_wb_ack(o_wb_ack), - .i_wb_data(o_wb_data), .i_wb_err(1'b0), - // - .f_nreqs(fwb_nreqs), .f_nacks(fwb_nacks), - .f_outstanding(fwb_outstanding) - // }}} - ); - - always @(*) - if (i_wb_cyc) - assert(fwb_outstanding == (o_wb_ack ? 1:0)); - - - fwb_master #( - .DW(DW), .AW(AW), .F_LGDEPTH(F_LGDEPTH) - ) fdma ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(o_dma_cyc), .i_wb_stb(o_dma_stb), .i_wb_we(o_dma_we), - .i_wb_addr(o_dma_addr), .i_wb_data(o_dma_data), - .i_wb_sel(o_dma_sel), - .i_wb_stall(i_dma_stall), .i_wb_ack(i_dma_ack), - .i_wb_idata(i_dma_data), .i_wb_err(i_dma_err), - // - .f_nreqs(fdma_nreqs), .f_nacks(fdma_nacks), - .f_outstanding(fdma_outstanding) - // }}} - ); - - always @(*) - if (o_dma_cyc) - assert(fdma_outstanding == wb_outstanding); - - always @(*) - if (!o_dma_stb && fdma_outstanding == 0) - assert(!o_dma_cyc); - - always @(*) - if(o_dma_cyc) - begin - assert(wb_pipeline_full == (wb_outstanding >= WBLIMIT)); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Induction properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - case(wr_state) - S_CLEARPTR: begin end - S_IDLE: begin end - S_PKTACTIVE: begin end - S_PKTPAUSED: begin end - S_NULL: begin end - S_LENGTH: begin end - default: assert(0); - endcase - - always @(posedge i_clk) - if (!i_reset && !r_dma_reset) - assert(pkt_length < (r_memsize << BLSB)); - -/* - always @(posedge i_clk) - if (!i_reset && $past(fifo_read && !fifo_empty && !i_reset)) - begin - if ($past(o_dma_cyc && i_dma_err)) - begin - assert(r_err); - if ($past(!fif_abort && !fif_last)) - assert(abort_write_packet); - end else if ($past(fif_abort || abort_write_packet || r_dma_reset)) - begin - assert(wr_state == S_IDLE); - assert(!o_dma_stb); - if ($past(!fif_abort && !fif_last)) - assert(abort_write_packet); - end else begin - assert(o_dma_cyc); - assert(o_dma_stb); - assert(o_dma_data == $past(fif_data)); - - if ($past(fif_last)) - assert(wr_state == S_NULL); - else - assert(wr_state == S_PKTACTIVE); - end - end -*/ - - always @(*) - if (!i_reset && !r_dma_reset && !r_err) - begin - assert(o_dma_addr >= r_baseaddr); - assert({ 1'b0, o_dma_addr } < r_lastaddr); - - assert({ r_writeptr } >= { r_baseaddr, {(LSB){1'b0}} }); - assert({ 1'b0, r_writeptr } < { r_lastaddr, {(LSB){1'b0}} }); - end - - always @(*) - assert(r_lastaddr == r_baseaddr + r_memsize); - - always @(*) - if (!r_dma_reset) - begin - assert(r_validptr==((r_readptr >= { r_baseaddr, {(LSB){1'b0}} }) - &&(r_readptr < { r_lastaddr, {(LSB){1'b0}} }))); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract check - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // -`ifdef FNVR_CHECK - (* anyconst *) reg fnvr_abort, fc_check; - (* anyconst *) reg [F_LGMXPKT-1:0] fc_pktaddr; - (* anyconst *) reg [8-1:0] fc_pktdata; - reg [AW-1:0] f_run_start; - // wire [F_LGMXPKT-1:0] fpkt_word; - reg [F_LGMXPKT-1:0] ffifo_word, fdma_word; - reg [AW:0] fdma_addr; - - always @(*) - if (fnvr_abort) - assume(!S_AXIN_ABORT); - - // Contract assumption: assume the given address is valid - always @(*) - if (fc_check && fnet_word== fc_pktaddr) - assume(!S_AXIN_VALID || S_AXIN_DATA == fc_pktdata); - - always @(*) - if (fc_check && fnet_word < fc_pktaddr) - assume(!S_AXIN_VALID || !S_AXIN_LAST || S_AXIN_ABORT); - - // Verify pkt_* via contract - // {{{ - always @(*) - if (!i_reset && fc_check - && fnet_word[F_LGMXPKT-1:LSB] == fc_pktaddr[F_LGMXPKT-1:LSB]) - begin - // if (fnet_word[$clog2(DW)-1:0] == 0) - if (fnet_word > fc_pktaddr) - begin - integer ik; - - for(ik=0; ik> LSB) + (o_dma_stb ? 1:0); - if (fdma_addr >= r_lastaddr) - fdma_addr = fdma_addr - r_memsize; - end - - always @(*) - if (!i_reset && fc_check && wr_state != S_IDLE && wr_state < S_NULL && !r_dma_reset) - begin - if (o_dma_stb) - assert(ffifo_word > 0); - assert(o_dma_addr == fdma_addr); - assert(f_run_start >= r_baseaddr); - assert(f_run_start < r_lastaddr); - assert(r_writeptr == f_run_start); - end - - // }}} - - // Pkts mustbe less than r_memsize, or abort_write_packet must be set - // {{{ - // It is possible that the user will adjust r_readptr along the way in - // an inappropriate manner. Until we assume this never happens, the - // following won't work - // - // always @(*) - // if (!i_reset && !r_err && !abort_write_packet && !r_dma_reset - // && (wr_state > S_IDLE && wr_state < S_NULL)) - // assert(fdma_word < ({ r_memsize, {(LSB){1'b0}} })); - // }}} -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - (* anyconst *) reg fcvr_different; - reg [3:0] cvr_packets; - - initial cvr_packets = 0; - always @(posedge i_clk) - if (i_reset || abort_write_packet || r_dma_reset) - cvr_packets <= 0; - else if ((!o_dma_stb || !i_dma_stall) && wr_state == S_LENGTH) - cvr_packets <= cvr_packets + 1; - - always @(posedge i_clk) - if (fcvr_different && $past(S_AXIN_VALID && S_AXIN_READY)) - assume($changed(S_AXIN_DATA)); - - always @(posedge i_clk) - if (fcvr_different) - begin - cover(cvr_packets == 1); - cover(cvr_packets == 2); - cover(cvr_packets == 3); - cover(cvr_packets == 4); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - -/* - always @(*) - if (!i_reset && !fifo_empty && { fif_abort, fif_last } == 2'b00) - assume(&fif_keep); - - always @(*) - if (!i_reset && !fif_empty && !fifo_abort) - case(fif_keep) - // 4'b0000: begin end - 4'b1000: begin end - 4'b1100: begin end - 4'b1110: begin end - 4'b1111: begin end - default: assume(0); - endcase -*/ - - // Pkts mustbe less than r_memsize, or abort_write_packet must be set - // {{{ - // It is possible that the user will adjust r_readptr along the way in - // an inappropriate manner. Until we assume this never happens, the - // following will need to be assumed rather than asserted. Otherwise - // ... induction fails after the packet wraps around memory more than - // once. - // -// always @(*) -// if (!i_reset && !r_err && !abort_write_packet && !r_dma_reset -// && (wr_state > S_IDLE && wr_state < S_NULL)) -// assume(fdma_word < ({ r_memsize, {(LSB){1'b0}} })); - // }}} - - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/pkt2p64b.v b/delete_later/rtl/net/pkt2p64b.v deleted file mode 100644 index afdc3e7..0000000 --- a/delete_later/rtl/net/pkt2p64b.v +++ /dev/null @@ -1,206 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: rtl/net/pkt2p64b.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Converts from our AXI network protocol to the 64bit payload -// required by the PCS layer in the IEEE standard, while bypassing -// the XGMII layer in the process. -// -// Why bypass the 32-bit XGMII? 1) Because the Xilinx PHY operates at -// 64-bits at a time, not 32. 2) Because the 64b/66b encoder requires -// 64 bits at a time. Other projects still call this an XGMII interface. -// This interface is close, though not quite there, since the IEEE -// requires XSGMII to be 32-bits per cycle. -// -// By convention, ethernet sends the two sync bits first, followed by -// bit 0 of byte 0 first. This IP, therefore, assumes a little endian -// byte order, with S_DATA[7:0] being the *first* byte in any packet. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -module pkt2p64b ( - // {{{ - input wire TX_CLK, S_ARESETN, - // - input wire i_remote_fault, i_local_fault, - // - input wire S_VALID, - output wire S_READY, - input wire [63:0] S_DATA, - input wire [2:0] S_BYTES, - input wire S_LAST, - input wire S_ABORT, - // - // output wire TXVALID=1 is assumed - // Ideally, we wouldn't need TXREADY, *but* the FPGA operates - // at a faster clock rate (at one clock per 64 outputs, not - // 1 clock per 66 inputs), so we need it here. - input wire TXREADY, - output reg [65:0] TXDATA - // }}} - ); - - // Local declarations - // {{{ - localparam [1:0] TX_IDLE = 2'h0, - TX_DATA = 2'h1, - TX_LAST = 2'h2, - TX_PAUSE = 2'h3; - localparam [1:0] SYNC_CONTROL = 2'b10, - SYNC_DATA = 2'b01; - - // FIXME! "The 10GBASE-R PCS encodes the start and terminate control - // characters implicitly by the block type field. ... The 10GBASE-R PCS - // encodes each of the other control characters into a 7-bit C code. - // - localparam [65:0] P_IDLE = { {(8){7'h07}}, 8'h1e, SYNC_CONTROL }, - // Indicate a remote fault - P_FAULT = { 24'h02, 8'h0, 24'h02, 8'h55, SYNC_CONTROL }, - // Start a packet--always on a 64b boundary - P_START = { 8'hab, {(6){8'haa}}, 8'h78, SYNC_CONTROL }, - P_LAST = { {(8){7'h07}}, 8'h87, SYNC_CONTROL }; - // "They [idles] shall not be added while data is being received. When - // deleting /I/s, the first four characters after a /T/ shall not be - // deleted. - - reg r_ready, flushing; - reg [1:0] state; - // }}} - - initial r_ready = 1'b0; - initial TXDATA = P_IDLE; - always @(posedge TX_CLK) - if (!S_ARESETN) - begin - // {{{ - r_ready <= 1'b0; - state <= TX_IDLE; - TXDATA <= P_IDLE; - flushing <= 1'b0; - // }}} - end else if (i_remote_fault || i_local_fault || flushing) - begin - // {{{ - if (TXREADY) - begin - if (i_remote_fault || !i_local_fault) - TXDATA <= P_IDLE; - else // if !i_remote_fault && i_local_fault - TXDATA <= P_FAULT; - end - - if (state == TX_DATA) - flushing <= 1'b1; - - state <= TX_PAUSE; - - if (S_VALID && S_READY && S_LAST) - begin - r_ready <= 1'b0; - state <= TX_PAUSE; - flushing<= 1'b0; - end else // Flush any ongoing packet - r_ready <= flushing || (state == TX_DATA); - // }}} - end else case(state) - TX_IDLE: begin - // {{{ - r_ready <= 1'b0; - TXDATA <= P_IDLE; - if (S_VALID) - begin - if (!S_ABORT && TXREADY) - begin - state <= TX_DATA; - TXDATA <= P_START; - r_ready <= 1'b1; - end else begin - // Accept the ABORT flag and continue - r_ready <= 1'b1; - end - end end - // }}} - TX_DATA: begin - // {{{ - r_ready <= 1'b1; - if (TXREADY) - begin - TXDATA <= { S_DATA, SYNC_DATA }; - if (S_ABORT || !S_VALID) - begin - // ERROR!! Send error code, then terminate - state <= TX_PAUSE; - TXDATA <= P_FAULT; - r_ready <= 1'b0; - end else if (S_LAST) - begin - r_ready <= 1'b0; - state <= TX_PAUSE; - case(S_BYTES) - 3'h0: state <= TX_LAST; - 3'h1: TXDATA <= { 48'h0000_0000_0000, - S_DATA[7:0], 8'h99, SYNC_CONTROL }; - 3'h2: TXDATA <= { 40'h0000_0000_00, - S_DATA[15:0], 8'haa, SYNC_CONTROL }; - 3'h3: TXDATA <= { 32'h0000_0000, S_DATA[23:0], - 8'hb4, SYNC_CONTROL }; - 3'h4: TXDATA <= { 24'h0000_00, - S_DATA[31:0], 8'hcc, SYNC_CONTROL }; - 3'h5: TXDATA <= { 16'h0000, - S_DATA[39:0], 8'hd2, SYNC_CONTROL }; - 3'h6: TXDATA <= { 8'h00, - S_DATA[47:0], 8'he1, SYNC_CONTROL }; - 3'h7: TXDATA <= { - S_DATA[55:0], 8'hff, SYNC_CONTROL}; - // No default needed - endcase - end - end end - // }}} - TX_LAST: begin - // {{{ - r_ready <= 1'b0; - if (TXREADY) - begin - TXDATA <= P_LAST; - state <= TX_PAUSE; - end end - // }}} - TX_PAUSE: begin // Ensure interframe gaps - // {{{ - r_ready <= 1'b0; - if (TXREADY) - begin - TXDATA <= P_IDLE; - state <= TX_IDLE; - end end - // }}} - // default: begin end - endcase - - assign S_READY = r_ready && (TXREADY || flushing); -endmodule diff --git a/delete_later/rtl/net/pktarbiter.v b/delete_later/rtl/net/pktarbiter.v deleted file mode 100644 index fd066b5..0000000 --- a/delete_later/rtl/net/pktarbiter.v +++ /dev/null @@ -1,158 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: pktarbiter.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A simple arbiter. Has nothing to do with packets really. Takes -// a series of requests for access, and provides that only one -// has said access in a round robin fashion. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) (None) -// {{{ -// The algorithm described in this file was copied from a stack overflow -// article: -// -// https://stackoverflow.com/questions/55015328/understanding-a-simple-round-robin-arbiter-verilog-code -// -// The formal properties, if present, are Copyright (C) 2021, Gisselquist -// Technology, LLC, and proprietary to Gisselquist Technology. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module pktarbiter #( - parameter W = 4 - ) ( - // {{{ - input wire i_clk, i_reset_n, - input wire [W-1:0] i_req, // Incoming request - input wire i_stall, // Request is busy - output wire [W-1:0] o_grant // Outgoing grant/access - // }}} - ); - - // Declarations - // {{{ - wire [2*W-1:0] w_req; - wire [2*W-1:0] w_grant; - wire [W-1:0] new_grant; - wire [2*W-1:0] req_diff; - reg [W-1:0] last, grant; - // }}} - - assign w_req = { i_req, i_req }; - assign req_diff = w_req - { {(W){1'b0}}, last }; - assign w_grant = w_req & ~req_diff; - assign new_grant = w_grant[W-1:0] | w_grant[2*W-1:W]; - - // o_grant, grant and last - // {{{ - always @(posedge i_clk) - if (!i_reset_n) - begin - grant <= 0; - last <= 1; - end else if (grant == 0 || !i_stall) - begin - grant <= new_grant; - if (last == 0) - last <= 1; - if (i_req != 0) - last <= { new_grant[W-2:0], new_grant[W-1] }; - end - - assign o_grant = grant; - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations - // {{{ - reg f_past_valid; - wire [W-1:0] not_granted; - - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(!i_reset_n); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Input assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign not_granted = (i_stall) ? {(W){1'b1}} : (i_req & (~o_grant)); - - always @(posedge i_clk) - if (!i_reset_n || $past(!i_reset_n)) - begin - assume(i_req == 0); - end else - assume((i_req & $past(not_granted)) == $past(not_granted)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Output assertions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (i_reset_n) - assert($onehot(last)); - - always @(*) - if (i_reset_n) - assert($onehot0(o_grant)); - - always @(posedge i_clk) - if (i_reset_n && $past(i_reset_n)) - begin - if ($past(i_req) != 0) - assert($onehot(o_grant)); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg [$clog2(W+2)-1:0] cvr_count; - - always @(posedge i_clk or negedge i_reset_n) - if (!i_reset_n) - cvr_count <= 0; - else if (&i_req) - cvr_count <= cvr_count + 1; - - always @(*) - cover(i_reset_n && (&cvr_count)); - - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/pktgate.v b/delete_later/rtl/net/pktgate.v deleted file mode 100644 index fc0bf4d..0000000 --- a/delete_later/rtl/net/pktgate.v +++ /dev/null @@ -1,735 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: pktgate.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: The packet gate has a simple purpose: buffer a whole packet, -// and don't release that packet until either an entire packet -// has been buffered, or the buffer has filled up. This is to help -// guarantee that once we start transmitting a packet (the next step), -// that the packet will be able to complete its transmission without -// any cycles where !M_AXIN_VALID between the first VALID and LAST. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module pktgate #( - // {{{ - parameter DW=8, // Byte/data width - parameter LGFLEN=4, - parameter [0:0] OPT_ASYNC_READ = 1'b1, - parameter [0:0] OPT_WRITE_ON_FULL = 1'b0, - parameter [0:0] OPT_READ_ON_EMPTY = 1'b0, - localparam FLEN=(1< 0) - output_active <= 1'b1; - end - // }}} - - // abort_output - // {{{ - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - abort_output <= 0; - else if (!output_active ||(M_AXIN_VALID && M_AXIN_READY && M_AXIN_LAST)) - abort_output <= 0; - else if (output_active && !M_AXIN_VALID) - abort_output <= 1; - // }}} - - // M_AXIN_VALID - // {{{ - always @(*) - if (OPT_READ_ON_EMPTY && S_AXIN_VALID && !S_AXIN_ABORT) - m_valid = 1'b1; - else - m_valid = !r_empty && output_active && !abort_output; - - assign M_AXIN_VALID = m_valid; - // }}} - - // M_AXIN_LAST, M_AXIN_BYTES, M_AXIN_DATA: Read from the FIFO - // {{{ - generate if (OPT_ASYNC_READ && OPT_READ_ON_EMPTY) - begin : ASYNCHRONOUS_READ_ON_EMPTY - // M_AXIN_LAST, M_AXIN_DATA - // {{{ - reg r_last, last_override; - reg [FW-1:0] memv; - - always @(*) - begin - memv = mem[rd_addr[LGFLEN-1:0]]; - if (r_empty) - memv = { S_AXIN_LAST, - S_AXIN_BYTES[$clog2(DW/8)-1:0], - S_AXIN_DATA }; - end - - always @(posedge S_AXI_ACLK) - last_override <= 0 && (M_AXIN_VALID && !M_AXIN_READY && M_AXIN_LAST); - - assign M_AXIN_DATA = memv[DW-1:0]; - assign M_AXIN_BYTES = memv[DW +: $clog2(DW/8)]; - - assign M_AXIN_LAST = memv[FW-1] || last_override; - // }}} - end else if (OPT_ASYNC_READ) - begin : ASYNCHRONOUS_READ - // M_AXIN_LAST, M_AXIN_DATA - // {{{ - reg [FW-1:0] memv; - - always @(*) - memv = mem[rd_addr[LGFLEN-1:0]]; - - assign M_AXIN_DATA = memv[DW-1:0]; - assign M_AXIN_BYTES = memv[DW +: $clog2(DW/8)]; - - assign M_AXIN_LAST = memv[FW-1]; - // }}} - end else begin : REGISTERED_READ - // {{{ - reg bypass_valid; - reg [FW-1:0] bypass_data, rd_data, rdval; - reg [LGFLEN-1:0] rd_next; - - always @(*) - rd_next = rd_addr[LGFLEN-1:0] + 1; - - // Memory read, bypassing it if we must - // {{{ - initial bypass_valid = 0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - bypass_valid <= 0; - else begin - bypass_valid <= 1'b0; - if (S_AXIN_VALID - && (r_empty || (M_AXIN_READY && (fill == 1)))) - bypass_valid <= 1'b1; - if (s_abort && !lastv) - bypass_valid <= 1'b1; - end - - always @(posedge S_AXI_ACLK) - bypass_data <= { (S_AXIN_LAST || S_AXIN_ABORT), - S_AXIN_BYTES[$clog2(DW/8)-1:0], S_AXIN_DATA }; - - initial mem[0] = 0; - initial rd_data = 0; - always @(posedge S_AXI_ACLK) - if (bypass_valid || w_rd) - // (!M_AXIN_VALID || M_AXIN_READY || (M_AXIN_ABORT && !M_AXIN_LAST))) - rd_data <= mem[(w_rd)?rd_next : rd_addr[LGFLEN-1:0]]; - - always @(*) - if (OPT_READ_ON_EMPTY && r_empty) - rdval = { S_AXIN_LAST, S_AXIN_BYTES[$clog2(DW/8)-1:0], - S_AXIN_DATA }; - else if (bypass_valid) - rdval = bypass_data; - else - rdval = rd_data; - - assign M_AXIN_DATA = rdval[DW-1:0]; - assign M_AXIN_BYTES = rdval[DW +: $clog2(DW/8)]; - assign M_AXIN_LAST = rdval[FW-1]; - // }}} - // }}} - end endgenerate - // }}} - - // M_AXIN_ABORT - // {{{ - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - r_midpacket <= 0; - else if (M_AXIN_VALID) - r_midpacket <= (!M_AXIN_READY || !M_AXIN_LAST); - - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - s_midpacket <= 0; - else if (S_AXIN_ABORT) - s_midpacket <= 0; - else if (S_AXIN_VALID && S_AXIN_READY) - s_midpacket <= !S_AXIN_LAST; - - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - M_AXIN_ABORT <= 1'b0; - else if (!M_AXIN_ABORT) - begin - if (!lastv && S_AXIN_ABORT && s_midpacket) - M_AXIN_ABORT <= (M_AXIN_VALID || r_midpacket); - if (output_active && r_empty) - M_AXIN_ABORT <= 1'b1; - end else if (!M_AXIN_VALID || M_AXIN_READY) - M_AXIN_ABORT <= 1'b0; - // }}} - - // Make Verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, fill, r_empty }; - // verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// FORMAL METHODS -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -`ifdef FORMAL - -// -// Assumptions about our input(s) -// -// -`ifdef SFIFO -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - wire [LGFLEN:0] f_fill, f_next; - wire f_full, f_empty; - - initial f_past_valid = 1'b0; - always @(posedge S_AXI_ACLK) - f_past_valid <= 1'b1; - - //////////////////////////////////////////////////////////////////////// - // - // Interface properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wire [9:0] faxin_swords, faxin_mwords; - wire [11:0] faxin_spkts, faxin_mpkts; - - faxin_slave #( - // {{{ - .DATA_WIDTH(DW), - .MIN_LENGTH(0) - // }}} - ) faxins ( - // {{{ - .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), - // - .S_AXIN_VALID(S_AXIN_VALID), .S_AXIN_READY(S_AXIN_READY), - .S_AXIN_DATA(S_AXIN_DATA), .S_AXIN_LAST(S_AXIN_LAST), - .S_AXIN_ABORT(S_AXIN_ABORT), - // - .f_stream_word(faxin_swords), - .f_packets_rcvd(faxin_spkts) - // }}} - ); - - faxin_master #( - // {{{ - .DATA_WIDTH(DW), - .MIN_LENGTH(0), .MAX_LENGTH(0) - // }}} - ) faxinm ( - // {{{ - .S_AXI_ACLK(S_AXI_ACLK), .S_AXI_ARESETN(S_AXI_ARESETN), - // - .S_AXIN_VALID(M_AXIN_VALID), .S_AXIN_READY(M_AXIN_READY), - .S_AXIN_DATA(M_AXIN_DATA), .S_AXIN_LAST(M_AXIN_LAST), - .S_AXIN_ABORT(M_AXIN_ABORT), - // - .f_stream_word(faxin_mwords), - .f_packets_rcvd(faxin_mpkts) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assertions about our flags and counters - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign f_fill = wr_addr - rd_addr; - assign f_empty = (wr_addr == rd_addr); - assign f_full = (f_fill >= (1<= (1< 1) - begin : GEN_NETFIFO - netfifo #( - .BW(BUSDW + WBLSB), .LGFLEN(LGFIFO) - ) u_prefifo ( - // {{{ - .S_AXI_ACLK(i_clk), .S_AXI_ARESETN(!i_reset), - // - .S_AXIN_VALID(ipkt_valid), - .S_AXIN_READY(ipkt_ready), - .S_AXIN_DATA({ ipkt_bytes[$clog2(BUSDW/8)-1:0], - ipkt_data }), - .S_AXIN_LAST( ipkt_last), - .S_AXIN_ABORT(ipkt_abort), - // - .M_AXIN_VALID(wide_valid), - .M_AXIN_READY(wide_ready), - .M_AXIN_DATA({ wide_bytes, wide_data }), - .M_AXIN_LAST( wide_last), - .M_AXIN_ABORT(wide_abort) - // }}} - ); - end else begin : NO_NETFIFO - assign wide_valid = ipkt_valid; - assign ipkt_ready = wide_valid; - assign wide_data = ipkt_data; - assign wide_bytes = ipkt_bytes; - assign wide_last = ipkt_last; - assign wide_abort = ipkt_abort; - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Write incoming packets to memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - pktvfifowr #( - // {{{ - .AW(AW), .BUSDW(BUSDW), .LGPIPE(LGPIPE), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN) - // }}} - ) vfifo_wr ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_cfg_reset_fifo(reset_fifo), .i_cfg_mem_err(mem_err), - .i_cfg_baseaddr(r_baseaddr), .i_cfg_memsize(r_memsize), - .i_readptr(w_readptr), // .i_mempkts(mempkts), - .o_writeptr(w_writeptr), // .o_pktwr_stb(pktwr_stb), - // - .S_VALID(wide_valid), .S_READY(wide_ready), - .S_DATA(wide_data), .S_BYTES(wide_bytes), - .S_LAST(wide_last), .S_ABORT(wide_abort), - // - .o_wb_cyc( wr_wb_cyc), .o_wb_stb( wr_wb_stb), - .o_wb_we( wr_wb_we), - .o_wb_addr(wr_wb_addr), .o_wb_data( wr_wb_data), - .o_wb_sel( wr_wb_sel), .i_wb_stall(wr_wb_stall), - .i_wb_ack( wr_wb_ack), // .i_wb_data( wr_wb_idata), - .i_wb_err( wr_wb_err) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Count available packets in memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Not needed. Now doing (readptr != writeptr) to tell us if packets - // are available. - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Read packets back out from memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - wire ack_valid, ack_last; - wire [BUSDW-1:0] ack_data; - wire [$clog2(BUSDW/8)-1:0] ack_bytes; - wire ackfifo_read, ackfifo_rd; - - pktvfiford #( - // {{{ - .AW(AW), .BUSDW(BUSDW), .LGPIPE(LGPIPE), - .OPT_LOWPOWER(OPT_LOWPOWER), - .OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN) - // }}} - ) vfifo_rd ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_cfg_reset_fifo(reset_fifo), // .i_cfg_mem_err(mem_err), - .i_cfg_baseaddr(r_baseaddr), .i_cfg_memsize(r_memsize), - .i_writeptr(w_writeptr), .o_readptr(w_readptr), - .o_fifo_err(rd_fifo_err), - // - .o_wb_cyc( rd_wb_cyc), .o_wb_stb( rd_wb_stb), - .o_wb_we( rd_wb_we), - .o_wb_addr(rd_wb_addr), .o_wb_data( rd_wb_data), - .o_wb_sel( rd_wb_sel), .i_wb_stall(rd_wb_stall), - .i_wb_ack( rd_wb_ack), .i_wb_data( rd_wb_idata), - .i_wb_err( rd_wb_err), - // - .M_VALID(ack_valid), // .M_READY(ack_ready), - .M_DATA(ack_data), .M_BYTES(ack_bytes), - .M_LAST(ack_last), // .M_ABORT(ack_abort) - .i_fifo_rd(ackfifo_rd) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Arbitrate between the two packet handlers - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wbmarbiter #( - .DW(BUSDW), .AW(AW), .NIN(2), .LGFIFO(LGFIFO) - ) u_bus_arbiter ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .s_cyc( { wr_wb_cyc, rd_wb_cyc }), - .s_stb( { wr_wb_stb, rd_wb_stb }), - .s_we( { wr_wb_we, rd_wb_we }), - .s_addr({ wr_wb_addr, rd_wb_addr }), - .s_data({(2){wr_wb_data}}), - .s_sel( { wr_wb_sel, rd_wb_sel }), - .s_stall({ wr_wb_stall, rd_wb_stall }), - .s_ack( { wr_wb_ack, rd_wb_ack }), - .s_idata({ wr_wb_idata, rd_wb_idata }), - .s_err({ wr_wb_err, rd_wb_err }), - // - .m_cyc( o_wb_cyc ), - .m_stb( o_wb_stb ), - .m_we( o_wb_we ), - .m_addr( o_wb_addr), - .m_data( o_wb_data), - .m_sel( o_wb_sel ), - .m_stall(i_wb_stall), - .m_ack( i_wb_ack), - .m_idata(i_wb_data), - .m_err( i_wb_err) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Return data FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wire ign_ackfifo_full, ackfifo_empty, ackfifo_last; - wire [LGFIFO:0] ign_ackfifo_fill; - wire [BUSDW-1:0] ackfifo_data; - wire [$clog2(BUSDW/8)-1:0] ackfifo_bytes; - - // We can't skip on the ACK FIFO. We need it to handle backpressure. - // The FIFO helps us guarantee that we don't overload this in back - // pressure. - sfifo #( - .BW(BUSDW + $clog2(BUSDW/8) + 1), .LGFLEN(LGFIFO) - ) u_ackfifo ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wr(ack_valid), .i_data({ ack_last, ack_bytes, ack_data }), - .o_full(ign_ackfifo_full), .o_fill(ign_ackfifo_fill), - .i_rd(ackfifo_rd), - .o_data({ ackfifo_last, ackfifo_bytes, ackfifo_data }), - .o_empty(ackfifo_empty) - // }}} - ); - - assign ackfifo_rd = ackfifo_read && !ackfifo_empty; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Outgoing width adjustment - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - wire ign_bytes; - - always @(posedge i_clk) - if (i_reset) - M_ABORT <= 1'b0; - else if (reset_fifo) - M_ABORT <= 1'b1; - - axinwidth #( - .IW(BUSDW), .OW(PKTDW) - ) u_outwidth ( - // {{{ - .ACLK(i_clk), .ARESETN(!i_reset && !reset_fifo), - // - .S_AXIN_VALID(!ackfifo_empty), - .S_AXIN_READY(ackfifo_read), - .S_AXIN_DATA(ackfifo_data), - .S_AXIN_BYTES({ (ackfifo_bytes== 0), ackfifo_bytes }), - .S_AXIN_LAST(ackfifo_last), - .S_AXIN_ABORT(1'b0), - // - .M_AXIN_VALID(M_VALID), - .M_AXIN_READY(M_READY), - .M_AXIN_DATA(M_DATA), - .M_AXIN_BYTES({ ign_bytes, M_BYTES }), - .M_AXIN_LAST(M_LAST), - .M_AXIN_ABORT(ign_outw_abort) - // }}} - ); - - // }}} - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, ign_bytes, new_memsize, new_baseaddr, - ipkt_bytes[$clog2(BUSDW/8)], - ign_ackfifo_full, ign_ackfifo_fill, - wr_wb_idata, ign_outw_abort, rd_wb_data }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/pktvfiford.v b/delete_later/rtl/net/pktvfiford.v deleted file mode 100644 index d88ddb3..0000000 --- a/delete_later/rtl/net/pktvfiford.v +++ /dev/null @@ -1,1248 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: rtl/net/pktvfiford.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is the second half, the *read* half of the Virtual Packet -// FIFO. Packets are defined by some number of bytes, with both -// start and LAST (i.e. end). Packets are assumed to be stored in memory, -// starting with a 32-bit word containing the number of bytes in the -// packet, followed by the packet data and then the 32-bit length word of -// the next packet. A length word of zero is evidence there are no (more) -// packets present in memory. The memory region is circular, so packets -// may start before the end of the memory, and end after wrapping around -// from the beginning. This IP depends upon knowing where the write -// pointer is (from the write half of the Virtual Packet FIFO) know when -// to read the packet length from memory. Hence, the write pointer must -// always point to a valid (or empty) packet length word. -// -// Configuration: -// i_cfg_reset_fifo True if/when the FIFO is being reconfigured, -// or the base address or memory size are not (yet) -// valid. -// -// i_cfg_baseaddr Points to the word address (bus aligned) of the -// beginning of the memory region. -// -// i_cfg_memsize This size of the allocated memory region, in bus words. -// (Not bytes) The memory region must be bus aligned. -// The base address plus the memory size shall point to -// one word past the end of memory. Hence, if memory has -// only two words (really too small), the base address -// might be zero and the memsize two. -// -// Operation: -// o_readptr A memory pointer to a 32-bit word in memory. The 2 LSBs -// are inferred, but not included. The pointer is used by -// the other half (the write half) of the FIFO to -// determine when/if the FIFO is full. Hence, the write -// half will never pass the read pointer. The two -// pointers, o_readptr and i_writeptr, will only ever be -// equal when the FIFO is empty. -// -// i_writeptr Points to the length word the virtual packet FIFO -// write half is looking at. This length word will be -// zero. A new packet may be read if ever 1) the read -// half is idle, and waiting to read a new packet length, -// and 2) the write pointer is not equal to the read -// pointer. -// -// o_fifo_err This is a check on the packet length. Should an invalid -// packet length ever be read, this FIFO error flag will -// be set. Examples of invalid lengths include zero length -// packets, packet lengths longer than the memory size, -// or even packet lengths longer than the distance to the -// write pointer. -// -// WB A Wishbone master interface, used to read from memory. -// -// M_* The outgoing AXI network packet stream interface. -// Unlike a full featured network packet stream, this -// interface does not support READY, nor does it ever -// generate an ABORT. -// -// i_fifo_rd The output of this module goes directly into a FIFO. -// Since Wishbone has no ability to handle back pressure, -// we have to guarantee (internally) that we never issue -// more WB requests than the FIFO can hold. Hence, we -// keep track of how much space is available in the FIFO. -// When a read request is issued, we decrement from the -// space available, and when *i_fifo_rd* is true we add -// one to the space available. -// -// Incidentally, when i_cfg_reset_fifo is true, the FIFO -// will be cleared and partial packets ABORTed (further -// down in the pipeline.) -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module pktvfiford #( - // {{{ - parameter BUSDW = 512, - parameter AW = 30-$clog2(BUSDW/8), - parameter LGFIFO = 5, - parameter LGPIPE = 6, - // MINLEN: A minimum packet length. Packets lengths shorter - // than MINLEN will generate a FIFO error. - parameter MINLEN = 64, // Must be > 0 - // MAXLEN: A maximum packet length. Packets lengths greater - // than MAXLEN will generate a FIFO error. - parameter MAXLEN = 256, // (1<<(AW+$clog2(BUSDW/8))), - parameter [0:0] OPT_LOWPOWER = 1, - parameter [0:0] OPT_LITTLE_ENDIAN = 0, - localparam WBLSB = $clog2(BUSDW/8) - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Control port - // {{{ - input wire i_cfg_reset_fifo, - input wire [AW-1:0] i_cfg_baseaddr, - input wire [AW-1:0] i_cfg_memsize, - input wire [AW+WBLSB-3:0] i_writeptr, - output wire [AW+WBLSB-3:0] o_readptr, - output reg o_fifo_err, - // }}} - // DMA bus interface - // {{{ - output reg o_wb_cyc, o_wb_stb, - output wire o_wb_we, - output wire [AW-1:0] o_wb_addr, - output wire [BUSDW-1:0] o_wb_data, - output reg [BUSDW/8-1:0] o_wb_sel, - input wire i_wb_stall, - // - input wire i_wb_ack, - input wire [BUSDW-1:0] i_wb_data, - input wire i_wb_err, - // }}} - // Outgoing packet - // {{{ - output reg M_VALID, - // input wire M_READY, // No backpressure supt - output reg [BUSDW-1:0] M_DATA, - output reg [$clog2(BUSDW/8)-1:0] M_BYTES, - output reg M_LAST, - // output wire M_ABORT, // No ABORT support - input wire i_fifo_rd - // }}} - // }}} - ); - - // Local declarations - // {{{ - // Local parameters - // {{{ - localparam [1:0] RD_IDLE = 2'h0, - RD_SIZE = 2'h1, - RD_PACKET = 2'h2, - RD_CLEARBUS = 2'h3; - // }}} - - // Because we work with so many different types of pointers here, - // the units are different all over the place, those with the wide_* - // prefix are *octet* (i.e. 8-bit) pointers. - reg [AW+WBLSB-1:0] wide_baseaddr, wide_memsize, // wide_writeptr - wide_readptr; - - // The end of memory may require an extra bit, to capture the case where - // we run right up to the last word in memory. - reg [AW+WBLSB:0] end_of_memory; - - // The following three pointers are 32-bit word pointers, so the - // bottom 2-LSBs are assumed to be zero, and not included in the - // pointer. - reg [AW+(WBLSB-2)-1:0] r_readptr, rd_wb_addr, r_endptr; - - reg [LGPIPE:0] rd_outstanding; - reg r_lastack, lastack; - - reg [LGFIFO:0] fifo_space; - - reg [AW+WBLSB-1:0] rd_pktlen; - reg [31:0] next_rdlen; - reg [1:0] rd_state; - reg [BUSDW-1:0] wide_next_rdlen; - - reg [AW+WBLSB:0] next_rdaddr, next_rdptr, - next_endptr, step_rdptr; - - reg dly_check, dly_fifo_err; - reg [AW+WBLSB-1:0] mem_fill; - - wire full_return, false_ack; - reg [AW+WBLSB-1:0] return_len, next_return_len; - wire [BUSDW/8-1:0] ptrsel; - - wire fifo_commit; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Control logic - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Most of our control logic is found in the parent module. Expanding - // our pointers to full byte-addresses is all that's left for us to do - // here. This just converts us to a common set of units, for following - // pointer arithmetic. - // - - always @(*) - begin - wide_baseaddr = 0; - wide_baseaddr = { i_cfg_baseaddr, {(WBLSB){1'b0}} }; - - wide_memsize = 0; - wide_memsize = { i_cfg_memsize, {(WBLSB){1'b0}} }; - - wide_readptr = 0; - wide_readptr = { r_readptr, 2'b00 }; - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Read packets back out from memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // This is our main read-from-memory FSM handling section. We start - // with some combinatorial pointer math, before getting to the FSM - // itself. - - generate if (BUSDW == 3) - begin - always @(*) - wide_next_rdlen = i_wb_data; - end else if (OPT_LITTLE_ENDIAN) - begin - always @(*) - wide_next_rdlen = i_wb_data >> (32*r_readptr[WBLSB-3:0]); - end else begin - always @(*) - wide_next_rdlen = i_wb_data << (32*r_readptr[WBLSB-3:0]); - end endgenerate - - always @(*) - if (OPT_LITTLE_ENDIAN) - next_rdlen = wide_next_rdlen[31:0]; - else - next_rdlen = wide_next_rdlen[BUSDW-32 +: 32]; - - // next_rdaddr = rd_wb_addr + BUSDW/8 - // {{{ - // This is a full (octet) address width pointer to the read address - // plus one bus word (i.e. BUSDW/8 octets). As with all of the pointers - // used here, this pointer wraps around the end of memory if necessary. - // Unlike the next_rdptr, which is very similar, this one is based - // off of the current read request address, rd_wb_addr, from which we - // grab the top AW bits to get o_wb_addr. - always @(*) - begin - next_rdaddr = { rd_wb_addr, 2'b00 } + BUSDW/8; - - if (next_rdaddr >= end_of_memory) - next_rdaddr = next_rdaddr - { i_cfg_memsize, {(WBLSB){1'b0}} }; - end - // }}} - - // next_rdptr = r_readptr + BUSDW/8 - // {{{ - // A full (octet) address width pointer for the next address in memory, - // following r_readptr, plus one (full) bus word. The read pointer will - // either be set to this address (while reading through packets), or its - // address plus 4 (via step_rdptr). Either way, the read pointer wraps - // around the end of memory in (what should be) an operation transparent - // to any user. - always @(*) - begin - next_rdptr = { 1'b0, r_readptr, 2'b00 } + BUSDW/8; - - if (next_rdptr >= end_of_memory) - next_rdptr = next_rdptr - - { i_cfg_memsize, {(WBLSB){1'b0}} }; - if (next_rdptr[WBLSB +: AW] == r_endptr[WBLSB-2 +: AW]) - next_rdptr = { 1'b0, r_endptr, 2'b00 }; - end - // }}} - - // r_endptr, next_endptr - // {{{ - // A helper to calculate the full byte pointer, pointing to the last - // valid 32-bit word of the packet in memory. Since next_rdlen is - // only valid when (rd_state == RD_SIZE && o_wb_cyc && i_wb_ack), - // this value will also only be valid at the same time. - always @(*) - begin - next_endptr = { r_readptr, 2'b00 } + next_rdlen[0+: AW+WBLSB] - + 3; // Plus the size of the pointer,-1 - next_endptr[1:0] = 2'b00; - if (next_endptr >= end_of_memory) - next_endptr = next_endptr - - { i_cfg_memsize, {(WBLSB){1'b0}} }; - end - - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || (o_wb_cyc && i_wb_err)) - r_endptr <= { i_cfg_baseaddr, {(WBLSB-2){1'b0}} }; - else if (rd_state == RD_IDLE) - r_endptr <= r_readptr; - else if (rd_state == RD_SIZE && i_wb_ack) - r_endptr <= next_endptr[AW+WBLSB-1:2]; - // }}} - - // step_rdptr = r_readptr + 4 - // {{{ - // step_rdptr is a full (octet) address width. Here, we calculate - // the circular pointer address to add one 32-bit value to r_readptr. - // This can move us from the end of the packet to the length pointer - // of the packet, or again from the length to the first word of the - // packet. - always @(*) - begin - step_rdptr = { r_readptr, 2'b00 } + 4; - - if (step_rdptr >= end_of_memory) - step_rdptr = step_rdptr - { i_cfg_memsize, {(WBLSB){1'b0}} }; - end - // }}} - - // ptrsel = (first o_wb_sel) - // {{{ - generate if (BUSDW==32) - begin - assign ptrsel = 4'hf; - end else if (OPT_LITTLE_ENDIAN) - begin - assign ptrsel = { {(BUSDW/8-4){1'b0}}, 4'hf } - << (4*r_readptr[WBLSB-3:0]); - end else begin - assign ptrsel = { 4'hf, {(BUSDW/8-4){1'b0}} } - >> (4*r_readptr[WBLSB-3:0]); - end endgenerate - // }}} - - initial { o_wb_cyc, o_wb_stb } = 2'b0; - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || o_fifo_err || (o_wb_cyc && i_wb_err)) - begin - // {{{ - o_wb_cyc <= 0; - o_wb_stb <= 0; - rd_wb_addr <= 0; - o_wb_sel <= 0; - r_readptr <= { i_cfg_baseaddr, {(WBLSB-2){1'b0}} }; - rd_state <= RD_IDLE; - rd_pktlen <= 0; - // }}} - end else case(rd_state) - RD_IDLE: begin - // {{{ - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - rd_wb_addr <= r_readptr; - rd_pktlen <= 0; - - o_wb_sel <= ptrsel; - - if (i_writeptr != r_readptr) - begin - // Issue a read command to capture the packet length - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - rd_state <= RD_SIZE; - end end - // }}} - RD_SIZE: begin - // {{{ - rd_pktlen <= 0; - - if (!i_wb_stall) - o_wb_stb <= 1'b0; - if (i_wb_ack) - begin - o_wb_cyc <= 1'b0; - rd_state <= RD_PACKET; - - rd_pktlen <= next_rdlen[AW+WBLSB-1:0]; - - r_readptr <= step_rdptr[AW+WBLSB-1:2]; - rd_wb_addr <= step_rdptr[AW+WBLSB-1:2]; - end end - // }}} - RD_PACKET: begin - // {{{ - o_wb_sel <= {(BUSDW/8){1'b1}}; - if (!i_wb_stall) - o_wb_stb <= 1'b0; - if (lastack) - o_wb_cyc <= 1'b0; - - // Don't increment the read pointer until the data comes back. - // That way the writer will know it has clear access to this - // data, now that it's been fully read and acknowledge. - if (i_wb_ack) - r_readptr <= next_rdptr[2 +: AW+(WBLSB-2)]; - - if (o_wb_stb && !i_wb_stall) - begin - // This address may go too far, stepping once too - // many times after the last address is corrected. - // We'll come back and fix this in RD_IDLE later. - rd_wb_addr <= next_rdaddr[AW+WBLSB-1:2]; - end - - if (o_wb_stb && o_wb_addr == r_endptr[WBLSB-2 +: AW]) - begin - rd_state <= RD_CLEARBUS; - end else if (!o_wb_stb || !i_wb_stall) - begin - if (!rd_outstanding[LGPIPE] - && (fifo_space > (o_wb_stb ? 1:0))) - { o_wb_cyc, o_wb_stb } <= 2'b11; - - end end - // }}} - RD_CLEARBUS: begin - // {{{ - // We come in here with the last request on the bus, either - // with o_wb_stb high or it having already been issued. Our - // goal here is to deactivate the bus once the entire packet - // has been requested, and then to go back to wait for the - // next packet. - o_wb_sel <= {(BUSDW/8){1'b1}}; - if (!i_wb_stall) - o_wb_stb <= 1'b0; - if (lastack) - begin - o_wb_cyc <= 1'b0; - rd_state <= RD_IDLE; - r_readptr <= step_rdptr[AW+WBLSB-1:2]; - end end - // }}} - default: begin end - endcase -`ifdef FORMAL - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || (o_wb_cyc && i_wb_err)) - begin - end else case(rd_state) - RD_IDLE: begin - assert(!o_wb_cyc); - assert(rd_outstanding == 0); - // assert(!i_wb_ack); - end - RD_SIZE: begin - assert(rd_outstanding + (o_wb_stb ? 1:0) == 1); - if (i_wb_ack) - begin - // We don't need to assume a valid length here. - // The FIFO error logic following will validate - // it, and generate an error if it's not a valid - // length. - // - // assume(next_rdlen[31:0] > 0); - // assume(next_rdlen[31:0] + 8 - // <= { fc_memsize, {(WBLSB){1'b0}} }); - end end - RD_PACKET: begin end - RD_CLEARBUS: begin - assert(o_wb_addr == r_endptr[WBLSB-2 +: AW]); - end - endcase - // }}} -`endif - - // rd_outstanding - // {{{ - initial rd_outstanding = 0; - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || !o_wb_cyc) - rd_outstanding <= 0; - else case ({ o_wb_stb && !i_wb_stall, i_wb_ack }) - 2'b10: rd_outstanding <= rd_outstanding + 1; - 2'b01: rd_outstanding <= rd_outstanding - 1; - default: begin end - endcase - // }}} - - // fifo_space - // {{{ - generate if (BUSDW == 32) - begin : NO_LAST_COMMIT - assign fifo_commit = (o_wb_stb && !i_wb_stall) - &&(rd_state == RD_PACKET); - end else begin : GEN_LAST_COMMIT - assign fifo_commit = (o_wb_stb && !i_wb_stall) - &&((rd_state == RD_CLEARBUS&& r_readptr[WBLSB-3:0] != 0) - ||(rd_state == RD_PACKET)); - end endgenerate - - initial fifo_space = 1<= (1< 0); - // }}} -`endif - // }}} - - assign o_wb_we = 1'b0; - assign o_wb_data = {(BUSDW){1'b0}}; - assign o_wb_addr = rd_wb_addr[AW+(WBLSB-2)-1:(WBLSB-2)]; - - assign o_readptr = r_readptr; - - // Last ack -- true when we need to drop CYC - // {{{ - // We drop CYC for 3 reasons (other than memory errors, resets, etc.) - // 1. We've read the packet size (CYC is dropped for one cycle) - // 2. We've reached the end of the packet, and may need to wait for - // another packet - // 3. The FIFO has no space left in it - // - // Here, we judge whether we've reached the last acknowledgment - // before one of these reasons. - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || !o_wb_cyc) - r_lastack <= 1; - else - r_lastack <= (rd_outstanding + ((o_wb_stb && !i_wb_stall) ? 1:0) - <= (i_wb_ack ? 2:1)); - always @(*) - lastack = r_lastack && (rd_outstanding[0] + (o_wb_stb ? 1:0) - == (i_wb_ack ? 1:0)); - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Memory size handling/checking, fifo error generation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // o_fifo_err - // {{{ - // Two causes of FIFO errors: - // 1. A zero length, after we've been told there's something there - // 2. A packet that passes the write pointer - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo) - o_fifo_err <= 1'b0; - else begin - o_fifo_err <= 1'b0; - if (dly_fifo_err) - o_fifo_err <= 1'b1; - if (o_wb_cyc && i_wb_ack && rd_state == RD_SIZE) - begin - if (next_rdlen + 1 >= wide_memsize) - o_fifo_err <= 1'b1; - if (next_rdlen < MINLEN) - o_fifo_err <= 1'b1; - if (next_rdlen >= MAXLEN) - o_fifo_err <= 1'b1; - end - end - // }}} - - // dly_check - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo) - dly_check <= 1'b0; - else if (i_wb_ack && rd_state == RD_SIZE) - begin - dly_check <= 1'b1; - end else - dly_check <= 1'b0; -`ifdef FORMAL - always @(*) - if (!i_reset && (rd_state == RD_IDLE || rd_state == RD_SIZE)) - assert(!dly_check); -`endif - // }}} - - // mem_fill - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo) - mem_fill <= 0; - else if (i_writeptr < r_readptr) - mem_fill <= { i_writeptr, 2'b00 } - { r_readptr, 2'b00 } - + wide_memsize; - else - mem_fill <= { i_writeptr, 2'b00 } - { r_readptr, 2'b00 }; - // }}} - - // dly_fifo_err - // {{{ - // Packet length verification check: Packets may not be larger than - // the memory size available to them. If they are, we declare an - // error (o_fifo_err), and the controller will cause both write and - // reader to abort and reset. - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || !dly_check) - dly_fifo_err <= 1'b0; - else - dly_fifo_err <= (mem_fill < rd_pktlen + 4); - // }}} - - always @(posedge i_clk) - end_of_memory <= wide_baseaddr + wide_memsize; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Realign data, push return results out - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // M_VALID - // {{{ - initial M_VALID = 1'b0; - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || rd_state == RD_SIZE) - M_VALID <= 1'b0; - else if ((i_wb_ack && full_return) || false_ack) - M_VALID <= 1'b1; - else // if (M_READY) -- backpressure not supported - M_VALID <= 1'b0; - // }}} - - generate if (BUSDW == 32) - begin : NO_REALIGNMENT - assign full_return = 1'b1; // All returns are full - assign false_ack = 1'b0; // No flushing returns - - // M_DATA (and sreg) - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || rd_state == RD_IDLE - || rd_state == RD_SIZE) - M_DATA <= 0; - else if (!OPT_LOWPOWER || i_wb_ack) - M_DATA <= i_wb_data; - // }}} - - // next_return_len -- how many bytes are left? - // {{{ - always @(*) - if (return_len >= BUSDW/8) - next_return_len = return_len - BUSDW/8; - else - next_return_len = 0; - // }}} - - end else begin: GEN_REALIGNMENT - reg r_full_return, r_false_ack; - reg [BUSDW-1:0] sreg; - - // full_return: Should an ACK trigger a full DW/8 output? - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || rd_state == RD_IDLE - || rd_state == RD_SIZE) - // We only generate a FIFO write on the first return - // if the lower bits of the read pointer are zero. - // HOWEVER ... the readptr in both IDLE and RD_SIZE - // states points to the length word, not the first - // data word, so we really need to add one, hence - // we check for all bits being one here. - r_full_return <= (&r_readptr[WBLSB-3:2]); - else if (i_wb_ack) - r_full_return <= 1'b1; - - assign full_return = r_full_return; - // }}} - - // false_ack: When do we flush our shift register? - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || rd_state == RD_SIZE - || !i_wb_ack) - // Wrong time to flush, so ... don't - r_false_ack <= 0; - else if (!lastack || o_wb_addr != r_endptr[WBLSB-2 +: AW]) - // Can't flush yet, we're not done - r_false_ack <= 0; - else - // NOW. Flush is there's more data to return. - r_false_ack <= (next_return_len != 0) - && (next_return_len < BUSDW/8); - - assign false_ack = r_false_ack; - // }}} - - // M_DATA (and sreg) - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || rd_state == RD_IDLE - || rd_state == RD_SIZE) - { M_DATA, sreg } <= 0; - else if (i_wb_ack) - begin - if (r_readptr[WBLSB-3:0] == 0) - { sreg, M_DATA } <= { {(BUSDW){1'b0}}, i_wb_data }; - else if (OPT_LITTLE_ENDIAN) - { sreg, M_DATA } - <= ({ {(BUSDW){1'b0}}, i_wb_data } - << (32*r_readptr[WBLSB-3:0])) - | { {(BUSDW){1'b0}}, sreg }; - else // if (!OPT_LITTLE_ENDIAN) - { M_DATA, sreg } - <= ({ i_wb_data, {(BUSDW){1'b0}} } - >> (32*r_readptr[WBLSB-3:0])) - | { sreg, {(BUSDW){1'b0}} }; - - if (!full_return && OPT_LOWPOWER) - M_DATA <= 0; - end else if (false_ack) - begin - M_DATA <= sreg; - sreg <= {(BUSDW){1'b0}}; - end -`ifdef FORMAL - // {{{ - reg [BUSDW-1:0] f_chkzero; - - always @(*) - if (OPT_LITTLE_ENDIAN) - begin - f_chkzero = (sreg >> (32*r_readptr[WBLSB-3:0])); - end else begin - f_chkzero = (sreg << (32*r_readptr[WBLSB-3:0])); - end - - always @(*) - if (!i_reset && (rd_state == RD_PACKET || rd_state == RD_CLEARBUS)) - begin - assert(0 == f_chkzero); - end else if (!i_reset && rd_state == RD_SIZE) - assert(sreg == 0); - // }}} -`endif - // }}} - - // next_return_len -- how many bytes are left? - // {{{ - always @(*) - if (!full_return) - next_return_len = return_len - (BUSDW/8) - + { {(AW){1'b0}}, r_readptr[WBLSB-3:0],2'b0 }; - else if (return_len >= BUSDW/8) - next_return_len = return_len - BUSDW/8; - else - next_return_len = 0; - // }}} - - end endgenerate - - // return_len: How many more bytes are to be expected? - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || rd_state == RD_IDLE) - return_len <= 0; - else if (o_wb_cyc && i_wb_ack && rd_state == RD_SIZE) - return_len <= next_rdlen[AW+WBLSB-1:0]; - else if (o_wb_cyc && i_wb_ack) - return_len <= next_return_len; -`ifdef FORMAL - // {{{ - // Relate return_len to the difference between r_readptr and r_endptr - reg [AW+WBLSB-1:0] f_endptr, f_startptr; - - // f_startptr -- points to the length word's address of the current pkt - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo) - f_startptr <= { i_cfg_baseaddr, {(WBLSB){1'b0}} }; - else if (rd_state == RD_IDLE || rd_state == RD_SIZE) - f_startptr <= { r_readptr, 2'b00 }; - // }}} - - always @(*) - begin - f_endptr = { r_readptr, 2'b00 } + return_len - 1; - if (full_return && r_readptr[WBLSB-3:0] != 0) - begin - f_endptr = f_endptr - + (BUSDW/8) - { r_readptr[WBLSB-3:0], 2'b00 }; - end - - if (f_endptr >= end_of_memory) - begin - f_endptr = f_endptr- { i_cfg_memsize, {(WBLSB){1'b0}} }; - end - - f_endptr[1:0] = 2'b00; - end - - always @(*) - if (!i_reset && !i_cfg_reset_fifo && !o_fifo_err && !dly_fifo_err) - case(rd_state) - RD_IDLE: begin end - RD_SIZE: begin - assert(return_len == 0); - assert(r_endptr == r_readptr); - end - default: begin - assert(dly_check || { r_endptr, 2'b00 } == f_endptr); - end - endcase - // }}} -`endif - // }}} - - // M_BYTE - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || rd_state == RD_SIZE) - M_BYTES <= 0; - else if (return_len >= BUSDW/8) - M_BYTES <= 0; - else - M_BYTES <= return_len[WBLSB-1:0]; - // }}} - - // M_LAST - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo) - M_LAST <= 0; - else - M_LAST <= (return_len <= BUSDW/8); - // }}} - - // }}} - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, wide_readptr, rd_wb_addr, wide_next_rdlen, - next_endptr }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH = LGPIPE+1; - reg f_past_valid; - wire [F_LGDEPTH-1:0] frd_nreqs, frd_nacks, frd_outstanding; - (* anyconst *) reg [AW-1:0] fc_baseaddr, fc_memsize; - reg [AW+WBLSB:0] wide_end_of_packet, wide_committed, - wide_writeptr;; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - //////////////////////////////////////////////////////////////////////// - // - // Configuration interface - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - begin - assume({ 1'b0, fc_baseaddr } + { 1'b0, fc_memsize } <= (1<= 8); - end else if (BUSDW == 64) - begin - assume(fc_memsize >= 4); - end else begin - assume(fc_memsize >= 2); - end - end - - always @(*) - begin - wide_writeptr = 0; - wide_writeptr = { i_writeptr, 2'b00 }; - end - - always @(*) - if (!i_reset && !i_cfg_reset_fifo) - begin - assume(i_cfg_baseaddr == fc_baseaddr); - assume(i_cfg_memsize == fc_memsize); - - assume(wide_writeptr >= wide_baseaddr); - assume(wide_writeptr < wide_baseaddr + wide_memsize); - end - - always @(*) - if (i_reset) - assume(i_cfg_reset_fifo); - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset)) - begin - if ($past(o_fifo_err) || $past(o_wb_cyc && i_wb_err)) - begin - assume(i_cfg_reset_fifo); - end - end - - - always @(posedge i_clk) - if (f_past_valid && $past(i_cfg_reset_fifo) && !i_cfg_reset_fifo) - begin - assume($stable(i_cfg_baseaddr)); - assume($stable(i_cfg_memsize)); - end - - always @(*) - begin - wide_committed = wide_writeptr - wide_readptr; - if (i_writeptr < r_readptr) - wide_committed = wide_committed - + { fc_memsize, {(WBLSB){1'b0}} }; - assume(wide_committed <= { fc_memsize, {(WBLSB){1'b0}} }); - - wide_end_of_packet = { 1'b0, r_endptr, 2'b00 } + 4; - if (wide_end_of_packet >= end_of_memory) - wide_end_of_packet = wide_end_of_packet - wide_memsize; - - // f_wide_pktfill = wide_writeptr - wide_end_of_packet; - // if (wide_writeptr < wide_end_of_packet) - // f_wide_pktfill = f_wide_pktfill - // + { fc_memsize, {(WBLSB){1'b0}} }; - end - - always @(posedge i_clk) - if (f_past_valid && !i_cfg_reset_fifo && !$past(i_cfg_reset_fifo)) - begin - assert(end_of_memory == wide_baseaddr + wide_memsize); - - assert(wide_end_of_packet >= wide_baseaddr); - assert(wide_end_of_packet < end_of_memory); - - // assert(f_wide_pktfill <= wide_committed); - - if ($stable(r_readptr)) - begin - assume($past(wide_committed) <= wide_committed); - end else begin - assume($past(wide_committed) <= wide_committed - (BUSDW/8)); - end - end - - always @(posedge i_clk) - if (f_past_valid && !i_cfg_reset_fifo && !$past(i_cfg_reset_fifo)) - assert($stable(end_of_memory)); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone properties - // {{{ - - fwb_master #( - .AW(AW), .DW(BUSDW), .F_LGDEPTH(F_LGDEPTH) - ) fwb ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - // - .i_wb_cyc( o_wb_cyc), - .i_wb_stb( o_wb_stb), - .i_wb_we( 1'b0 ), - .i_wb_addr( o_wb_addr), - .i_wb_data( o_wb_data), - .i_wb_sel( o_wb_sel ), - .i_wb_stall(i_wb_stall), - .i_wb_ack( i_wb_ack), - .i_wb_idata(i_wb_data), - .i_wb_err( i_wb_err), - // - .f_nreqs(frd_nreqs), - .f_nacks(frd_nacks), - .f_outstanding(frd_outstanding) - // }}} - ); - - always @(*) - if (!i_reset && o_wb_cyc) - assert(frd_outstanding == rd_outstanding); - - always @(*) - if (!i_reset && o_wb_stb) - assert(rd_outstanding <= (1<= end_of_memory) - fwb_next_addr = fwb_next_addr - wide_memsize; - fwb_next_addr[1:0] = 2'b00; - end - - always @(*) - if (!i_reset && !i_cfg_reset_fifo && rd_state != RD_IDLE - && rd_state != RD_SIZE && !o_fifo_err) - begin - assert(fwb_next_addr[AW+WBLSB-1:2] == rd_wb_addr); - assert(r_readptr[WBLSB-3:0] == rd_wb_addr[WBLSB-3:0]); - end - // }}} - - // Verify relationship between f_startptr, r_readptr && return_len - // {{{ - - // fwb_bytes_requested - // {{{ - // These are bytes that have been requested, ackd, and so returned, - // and may have even been sent across the bus - always @(*) - if (i_reset || rd_state == RD_IDLE || rd_state == RD_SIZE - || r_readptr[WBLSB-3 +: AW] == f_startptr[WBLSB +: AW]) - begin - fwb_bytes_requested = 0; - end else if (r_readptr[WBLSB-3 +: AW] >= f_startptr[WBLSB +: AW]) - begin - fwb_bytes_requested = - { r_readptr[WBLSB-3 +: AW], {(WBLSB){1'b0}} } - - f_startptr - 4; - end else begin - fwb_bytes_requested = wide_memsize - + { o_wb_addr, {(WBLSB){1'b0}} } - f_startptr - 4; - end - // }}} - - // fwb_wide_request : Packet length rounded up to the last word - // {{{ - always @(*) - if (i_reset || rd_pktlen == 0) - fwb_wide_request = 0; - else begin - fwb_wide_request = {r_endptr, 2'b00 } - f_startptr; - fwb_wide_request[WBLSB-1:0] = 0; - fwb_wide_request = fwb_wide_request - + BUSDW/8 - f_startptr[WBLSB-3:0]; - end - // }}} - - // fwb_bytes_outstanding : Bytes that have been requested, but not ackd - // {{{ - // These bytes are those that haven't yet been returned on the bus. - always @(*) - if (rd_outstanding == 0) - fwb_bytes_outstanding = 0; - else if (!full_return) - begin - fwb_bytes_outstanding = BUSDW/8 - rd_wb_addr[WBLSB-3:0]; - fwb_bytes_outstanding = fwb_bytes_requested - + { rd_outstanding, {(WBLSB){1'b0}} } - - (BUSDW/8); - end else begin - fwb_bytes_outstanding = { rd_outstanding, {(WBLSB){1'b0}} }; - end - // }}} - - always @(*) - if (!i_reset && !i_cfg_reset_fifo - && (rd_state == RD_PACKET || rd_state == RD_CLEARBUS) - && !o_fifo_err && !dly_check && !dly_fifo_err) - begin - assert(fwb_bytes_requested <= wide_memsize); - assert(fwb_bytes_outstanding <= wide_memsize); - assert(fwb_bytes_requested + fwb_bytes_outstanding - <= wide_memsize); - - assert(fwb_bytes_requested + fwb_bytes_outstanding - + return_len >= rd_pktlen); - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // (* anyconst *) reg [AW+WBLSB-1:0] fc_posn; - // (* anyconst *) reg [7:0] fc_byte; - // reg [BUSDW-1:0] f_byte_wide; - - // Pick a byte position within a packet. - // always @(*) - // if (rd_state == RD_PACKET || rd_state == RD_CLEARBUS) - // assume(fc_posn < rd_pktlen); - // - - // Pick a value to be at that byte. - // Assume that value gets returned, when i_wb_ack is high - // {{{ - - // ... ?? - // bus_byte = - // always @(*) - // if (!i_reset && o_wb_cyc && i_wb_ack && - // assume(bus_byte == fc_byte); - // }}} - - // *PROVE* that value is set in M_DATA when the byte is sent. - // {{{ - // generate if (OPT_LITTLE_ENDIAN) - // begin - // - // always @(*) - // f_byte_wide = M_DATA >> (fc_posn[WBLSB-1:0] * 8); - // assign f_byte = f_byte_wide[7:0]; - // - // end else begin - // always @(*) - // f_byte_wide = M_DATA << (fc_posn[WBLSB-1:0] * 8); - // assign f_byte = f_byte_wide[BUSDW-8 +: 8]; - // end endgenerate - - // always @(*) - // if (!i_reset && M_VALID && { fs_word, {(WBLSB){1'b0}} } <= fc_posn - // && fc_posn < { fs_word, {(WBLSB){1'b0}} }) - // assert(f_byte == fc_byte); - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) assume(fc_baseaddr == 0); - always @(*) assume(fc_memsize == { 1'b1, {(AW-1){1'b0}} }); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/pktvfifowr.v b/delete_later/rtl/net/pktvfifowr.v deleted file mode 100644 index bb3944a..0000000 --- a/delete_later/rtl/net/pktvfifowr.v +++ /dev/null @@ -1,1151 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: rtl/net/pktvfifowr.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: The is the first half, the *write* half, of the Virtual Packet -// FIFO. Packets enter into here as an AXI network packet stream, -// and may be aborted at any time up until the end of the packet. -// Operation works as follows: -// 1. A 32-bit zero (null packet length) is written to memory. -// 2. As a packet arrives, it is written to memory, following the null -// packet length word. The packet length is accumulated. -// 3. If the packet is aborted, the pointers are returned to the beginning -// of step 2, and we start over with the next packet. -// -// If there's no room for the packet in memory (currently), the -// incoming network SLAVE path will be stalled. If it stalls too -// long, the master will abort the packet. Similarly, if the -// memory is empty and the packet currently being written to -// memory would overflow it, then the packet is aborted internally. -// 4. Once LAST is received, and the beat associated with LAST written to -// memory, the packet is complete and may no more be aborted. -// 5. A 32-bit null is written to the 32-bit word following the packet. -// 6. The length of the packet is then written to the original packet -// length position. -// 7. At this point, the FSM moves forward by one packet, and we go back -// to step two--this time from a new memory location. -// -// It is understood that packets will not be read until they have been -// entirely written to memory. -// -// Configuration: -// i_cfg_reset_fifo -// -// i_cfg_mem_err -// -// i_cfg_baseaddr The first (valid) address of memory. This is a word -// address, and must be bus aligned. (An associated -// wide_baseaddr, used internally, is a byte address.) -// -// i_cfg_memsize The number of words available for writing to memory. -// This size must be bus aligned. This number may be -// as large as the number of words in memory. This -// size is unconstrained, but must be greater than zero. -// (Practically, it must be greater than about 4-5 or so, -// and is assumed to be greater than (or equal to) a -// reference to 1500 Bytes.) -// -// Operation: -// i_readptr This is the address of the next word to be read -// from memory. It is the address of a 32-bit word, -// and may be the address of a word within a bus word. -// The bottom two LSB's are not included, and are assumed -// to be zero. -// -// o_writeptr The address of a 32-bit word, where the bottom two -// address bits are assumed to be zero, that points to -// a null packet address. This is our indication, to the -// read half of the FIFO, of where we are at working -// through memory. -// -// S_AXIN_* An incoming (slave) AXI stream network packet interface. -// (AXI stream w/ BYTES and ABORT fields.) -// -// WB Wishbone bus interface, used to write packets to memory. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module pktvfifowr #( - // {{{ - parameter BUSDW = 512, - parameter AW = 30-$clog2(BUSDW/8), - parameter LGPIPE = 6, - parameter [0:0] OPT_LOWPOWER = 1, - parameter [0:0] OPT_LITTLE_ENDIAN = 0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Control port - // {{{ - input wire i_cfg_reset_fifo, i_cfg_mem_err, - input wire [AW-1:0] i_cfg_baseaddr, - input wire [AW-1:0] i_cfg_memsize, - input wire [AW+WBLSB-3:0] i_readptr, - output wire [AW+WBLSB-3:0] o_writeptr, - // output wire o_pktwr_stb, - // }}} - // Incoming packet - // {{{ - input wire S_VALID, - output wire S_READY, - input wire [BUSDW-1:0] S_DATA, - input wire [$clog2(BUSDW/8)-1:0] S_BYTES, - input wire S_LAST, - input wire S_ABORT, - // }}} - // DMA bus interface - // {{{ - output reg o_wb_cyc, o_wb_stb, - output wire o_wb_we, - output wire [AW-1:0] o_wb_addr, - output reg [BUSDW-1:0] o_wb_data, - output reg [BUSDW/8-1:0] o_wb_sel, - input wire i_wb_stall, - input wire i_wb_ack, - // input wire [BUSDW-1:0] i_wb_data, - input wire i_wb_err - // }}} - // }}} - ); - - // Local declarations - // {{{ - // Local parameters - // {{{ - localparam WBLSB = $clog2(BUSDW/8); - - localparam [2:0] WR_CLEARPTR = 3'h0, - WR_PUSH = 3'h1, - WR_FLUSH = 3'h2, - WR_NULL = 3'h3, - WR_LENGTH = 3'h4, - WR_CLEARBUS = 3'h5, - WR_OVERFLOW = 3'h6; - // }}} - - reg [AW+WBLSB-1:0] wide_baseaddr, wide_memsize, - wide_writeptr, wide_bytes; - reg [AW+WBLSB:0] wide_end_of_memory; - reg [31:0] wide_pktlen; - - // r_writeptr always points to the length word of a packet, minus - // the last two bits (which are assumed to be zero, as the length - // is guaranteed to be 32b aligned). - reg [AW+(WBLSB-2)-1:0] r_writeptr; - - reg [AW:0] end_of_memory; - - reg [LGPIPE:0] wr_outstanding; - reg [2*BUSDW-1:0] next_dblwide_data; - reg [(2*BUSDW/8)-1:0] next_dblwide_sel; - reg [BUSDW-1:0] next_wr_data; - reg [BUSDW/8-1:0] next_wr_sel; - reg [$clog2(BUSDW/8)-1:0] wide_words, wide_shift; - - wire lastack; - - reg [AW+WBLSB-3:0] wr_wb_addr; - - reg [AW+WBLSB:0] next_wbaddr, next_wbfirst, next_wbnull; - reg [AW+WBLSB-1:0] wr_pktlen; - reg [2:0] wr_state; - reg wr_midpkt; - - reg [AW+WBLSB:0] wide_mem_fill; - reg mem_full, mem_overflow; - reg syncd; - wire [((WBLSB<3) ? 0 : (WBLSB-3)):0] dshift; - reg r_lastack; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Control logic - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - begin - // Base address and memsize are both bus word aligned - wide_baseaddr = 0; - wide_baseaddr = { i_cfg_baseaddr, {(WBLSB){1'b0}} }; - - wide_memsize = 0; - wide_memsize = { i_cfg_memsize, {(WBLSB){1'b0}} }; - - // Write and read pointers are 32-bit aligned - wide_writeptr = 0; - wide_writeptr = { r_writeptr, 2'b00 }; - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Write incoming packets to memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - begin - wide_words = (S_BYTES + 3) >> 2; - wide_shift = -wide_words; - wide_shift[$clog2(BUSDW/8)-1:0] = 0; - end - - // next_wbaddr - // {{{ - // Full ADDRESS_WIDTH, AW + WBLSB - always @(*) - begin - next_wbaddr = { wr_wb_addr, 2'b00 } + (BUSDW/8); - if (next_wbaddr[WBLSB +: AW] >= (i_cfg_baseaddr+i_cfg_memsize)) - next_wbaddr = { wr_wb_addr, 2'b00 } - + (BUSDW/8) - wide_memsize; - next_wbaddr[WBLSB-1:0] = { wr_wb_addr[WBLSB-3:0], 2'b00 }; - end - // }}} - - // next_wbnull - // {{{ - always @(*) - begin - // Points to the length word following the current packet. - // Given that writeptr points to the length word of the - // current packet, we need to add both the packet length - // and the 4-byte length word to get to this location. - next_wbnull = wide_writeptr + wr_pktlen + 4 + 3; - next_wbnull[1:0] = 2'b00; - if (next_wbnull[WBLSB +: AW+1]>=wide_end_of_memory[WBLSB +: AW+1]) - next_wbnull[WBLSB +: AW+1] = next_wbnull[WBLSB +: AW+1] - - { 1'b0, i_cfg_memsize }; - end - // }}} - - // next_wbfirst - // {{{ - // Full byte address - always @(*) - begin - // r_writeptr points to the length word of a packet, so we - // need something to point us to the first data word of - // the packet. That's next_wbfirst. - next_wbfirst = wide_writeptr + 4; - next_wbfirst[1:0] = 2'b00; // Shouldn't need saying - if (next_wbfirst >= wide_end_of_memory) - next_wbfirst = { 1'b0, i_cfg_baseaddr, {(WBLSB){1'b0}} }; - end - // }}} - - // next_dblwide_data, next_dblwide_sel - // {{{ - generate if (WBLSB < 3) - begin - assign dshift = 0; - end else begin - assign dshift = r_writeptr[WBLSB-3:0] + 1; - end endgenerate - - generate if (WBLSB == 2) - begin : NO_ALIGNMENT - // {{{ - always @(*) - begin - next_dblwide_data = {{(BUSDW){1'b0}}, S_DATA }; - next_dblwide_sel={{(BUSDW/8){1'b0}},{(BUSDW/8){1'b1}} }; - end - // }}} - end else if (OPT_LITTLE_ENDIAN) - begin : GEN_LITTLE_ENDIAN_ALIGNMENT - // {{{ - always @(*) - if (OPT_LITTLE_ENDIAN) - begin - next_dblwide_data = { {(BUSDW){1'b0}}, S_DATA } - << (wr_wb_addr[WBLSB-3:0] * 32); - if (S_BYTES == 0) - next_dblwide_sel = { {(BUSDW/8){1'b0}}, - {(BUSDW/8){1'b1}} }; - else - next_dblwide_sel[BUSDW/8-1:0] - = {(BUSDW/8){1'b1}} >> (4*wide_shift); - next_dblwide_sel = next_dblwide_sel << (dshift * 4); - - next_dblwide_data[BUSDW-1:0] - = next_dblwide_data[BUSDW-1:0] | next_wr_data; - - next_dblwide_sel[BUSDW/8-1:0] - = next_dblwide_sel[BUSDW/8-1:0] | next_wr_sel; - end - // }}} - end else begin : GEN_ALIGNMENT - always @(*) - begin - next_dblwide_data = { S_DATA, {(BUSDW){1'b0}} } - >> (dshift * 32); - - next_dblwide_sel = {(BUSDW/4){1'b0}}; - if (S_BYTES == 0) - next_dblwide_sel = { {(BUSDW/8){1'b1}}, - {(BUSDW/8){1'b0}} }; - else - next_dblwide_sel[2*BUSDW/8-1:BUSDW/8] - = {(BUSDW/8){1'b1}} << (4*wide_shift); - next_dblwide_sel = next_dblwide_sel >> (dshift * 4); - - next_dblwide_data[BUSDW-1:0] - = next_dblwide_data[BUSDW-1:0] | next_wr_data; - - next_dblwide_sel[2*BUSDW/8-1:BUSDW/8] - = next_dblwide_sel[2*BUSDW/8-1:BUSDW/8] | next_wr_sel; - end - end endgenerate - // }}} - - // wr_pktlen - // {{{ - always @(*) - begin - wide_bytes = 0; - wide_bytes[$clog2(BUSDW/8)-1:0] = S_BYTES; - end - - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || i_cfg_mem_err - || (wr_state == WR_OVERFLOW)) - begin - wr_pktlen <= 0; - end else if (S_ABORT && (!S_VALID || S_READY)) - begin - wr_pktlen <= 0; - end else if (S_VALID && S_READY) - begin - if (!wr_midpkt) - wr_pktlen <= (BUSDW/8); - else if (S_BYTES == 0) - wr_pktlen <= wr_pktlen + (BUSDW/8); - else - wr_pktlen <= wr_pktlen + wide_bytes; - end - - always @(*) - begin - wide_pktlen = 0; - wide_pktlen[AW+WBLSB-1:0] = wr_pktlen; - end - // }}} - - // syncd - // {{{ - always @(posedge i_clk) - if (i_reset) - syncd <= 1'b1; - else if (S_ABORT && (!S_VALID || S_READY)) - syncd <= 1'b1; - else if (S_VALID && S_READY) - syncd <= S_LAST; - // }}} - - initial o_wb_cyc = 1'b0; - initial o_wb_stb = 1'b0; - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || i_cfg_mem_err - || (o_wb_cyc && i_wb_err)) - begin - // {{{ - o_wb_cyc <= 0; - o_wb_stb <= 0; - wr_wb_addr <= 0; - o_wb_data <= 0; - o_wb_sel <= 0; - r_writeptr <= { i_cfg_baseaddr, {(WBLSB-2){1'b0}} }; - wr_state <= WR_CLEARPTR; - wr_midpkt <= 1'b0; - // wr_pktstart <= i_cfg_baseaddr; - // }}} - end else case(wr_state) - WR_CLEARPTR: begin - // {{{ - wr_midpkt <= 1'b0; - if (!o_wb_stb || !i_wb_stall) - begin - // Write a NULL word to the beginning of memory - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - wr_wb_addr <= r_writeptr; - // r_pktstart <= r_writeptr; - o_wb_data <= 0; - if (BUSDW < 64) - begin - o_wb_sel <= {(BUSDW/8){1'b1}}; - end else if (OPT_LITTLE_ENDIAN) - begin - o_wb_sel <= { {(BUSDW/8-4){1'b0}}, 4'hf } - << (4*r_writeptr[WBLSB-3:0]); - end else begin - o_wb_sel <= { 4'hf, {(BUSDW/8-4){1'b0}} } - >> (4*r_writeptr[WBLSB-3:0]); - end - wr_state <= WR_PUSH; - next_wr_data <= 0; - next_wr_sel <= 0; - end end - // }}} - WR_PUSH: begin - // {{{ - if (S_ABORT && (!S_VALID || S_READY)) - wr_midpkt <= 1'b0; - - if (!o_wb_stb || !i_wb_stall) - begin - if (lastack) - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - - if (S_ABORT || !wr_midpkt) - begin - wr_wb_addr <= next_wbfirst[AW+WBLSB-1:2]; - wr_midpkt <= 1'b0; - end else if (o_wb_stb) - wr_wb_addr <= next_wbaddr[AW+WBLSB-1:2]; - end - - if ((!o_wb_stb || !i_wb_stall) && (wr_midpkt || syncd) - && S_VALID && S_READY && !S_ABORT) - begin - wr_midpkt <= 1'b1; - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - - if (BUSDW < 64 || OPT_LITTLE_ENDIAN) - begin - { next_wr_data, o_wb_data} <= next_dblwide_data; - { next_wr_sel, o_wb_sel } <= next_dblwide_sel; - end else begin - { o_wb_data, next_wr_data }<=next_dblwide_data; - { o_wb_sel, next_wr_sel }<=next_dblwide_sel; - end - - if (S_LAST) - wr_state <= WR_FLUSH; - end else if (mem_overflow) - wr_state <= WR_OVERFLOW; - end - // }}} - WR_FLUSH: begin - // {{{ - wr_midpkt <= 1'b1; - - if (!o_wb_stb || !i_wb_stall) - begin - if (o_wb_stb) - wr_wb_addr <= next_wbaddr[AW+WBLSB-1:2]; - - if (lastack) - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - - if (BUSDW < 64) - begin - o_wb_data <= {(BUSDW ){1'b0}}; - o_wb_sel <= {(BUSDW/8){1'b0}}; - end else begin - if (!mem_full && next_wr_sel != 0) - { o_wb_cyc, o_wb_stb } <= 2'b11; - - o_wb_data <= next_wr_data; - o_wb_sel <= next_wr_sel; - end - next_wr_data <= {(BUSDW ){1'b0}}; - next_wr_sel <= {(BUSDW/8){1'b0}}; - - wr_state <= WR_NULL; - end end - // }}} - WR_NULL: begin // Write a concluding 32-bit NULL word - // {{{ - wr_midpkt <= 1'b1; - next_wr_data <= {(BUSDW ){1'b0}}; - next_wr_sel <= {(BUSDW/8){1'b0}}; - - if (!o_wb_stb || !i_wb_stall) - begin - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - wr_wb_addr <= next_wbnull[AW+WBLSB-1:2]; - o_wb_data <= {(BUSDW){1'b0}}; - if (BUSDW < 64) - begin - o_wb_sel <= {(BUSDW/8){1'b1}}; - end else if (OPT_LITTLE_ENDIAN) - begin - o_wb_sel <= { {(BUSDW/8-4){1'b0}}, 4'hf } - << (4*next_wbnull[WBLSB-1:2]); - end else begin - o_wb_sel <= { 4'hf, {(BUSDW/8-4){1'b0}} } - >> (4*next_wbnull[WBLSB-1:2]); - end - next_wr_data <= {(BUSDW ){1'b0}}; - next_wr_sel <= {(BUSDW/8){1'b0}}; - - wr_state <= WR_LENGTH; - end end - // }}} - WR_LENGTH: begin // Write the length word for the packet - // {{{ - wr_midpkt <= 1'b1; - next_wr_data <= {(BUSDW ){1'b0}}; - next_wr_sel <= {(BUSDW/8){1'b0}}; - - if (!o_wb_stb || !i_wb_stall) - begin - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - wr_wb_addr <= r_writeptr; - - if (!OPT_LOWPOWER || BUSDW < 64) - o_wb_data <= {(BUSDW/32){wide_pktlen}}; - else if (OPT_LITTLE_ENDIAN) - o_wb_data <= { {(BUSDW-32){1'b0}}, wide_pktlen } << (32*r_writeptr[WBLSB-3:0]); - else - o_wb_data <= { wide_pktlen, {(BUSDW-32){1'b0}} } >> (32*r_writeptr[WBLSB-3:0]); - - if (BUSDW < 64) - begin - o_wb_sel <= {(BUSDW/8){1'b1}}; - end else if (OPT_LITTLE_ENDIAN) - begin - o_wb_sel <= { {(BUSDW/8-4){1'b0}}, 4'hf } - << (r_writeptr[WBLSB-3:0] * 4); - end else begin - o_wb_sel <= { 4'hf, {(BUSDW/8-4){1'b0}} } - >> (r_writeptr[WBLSB-3:0] * 4); - end - - wr_state <= WR_CLEARBUS; - end end - // }}} - WR_CLEARBUS: begin // Write for last ACK to know the packet was written - // {{{ - wr_midpkt <= 1'b1; - next_wr_data <= {(BUSDW ){1'b0}}; - next_wr_sel <= {(BUSDW/8){1'b0}}; - if (!o_wb_stb || !i_wb_stall) - begin - if (lastack) - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - - if (OPT_LOWPOWER) - begin - o_wb_data <= {(BUSDW ){1'b0}}; - o_wb_sel <= {(BUSDW/8){1'b0}}; - end - end - if (!o_wb_stb && (wr_outstanding == (i_wb_ack ? 1:0))) - begin - wr_state <= WR_PUSH; - wr_midpkt <= 1'b0; - r_writeptr <= next_wbnull[AW+WBLSB-1:2]; - end end - // }}} - WR_OVERFLOW: begin // No room in memory. Wait for the pkt to complete - // {{{ - next_wr_data <= {(BUSDW ){1'b0}}; - next_wr_sel <= {(BUSDW/8){1'b0}}; - if (S_VALID && S_READY && S_LAST) - wr_midpkt <= 1'b0; - if (S_ABORT && (!S_VALID || S_READY)) - wr_midpkt <= 1'b0; - if (!o_wb_stb || !i_wb_stall) - begin - if (lastack) - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - end - - if (!wr_midpkt && !o_wb_stb - && (wr_outstanding == (i_wb_ack ? 1:0))) - wr_state <= WR_PUSH; - end - // }}} - default: begin - // {{{ -`ifdef FORMAL - assert(0); -`endif - end - // }}} - endcase - - // lastack - // {{{ - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || i_cfg_mem_err || !o_wb_cyc) - r_lastack <= 1; - else - r_lastack <= (wr_outstanding + (o_wb_stb && !i_wb_stall ? 1:0) - <= (i_wb_ack ? 2:1)); - - assign lastack = r_lastack - // && ((wr_outstanding[0] && !o_wb_stb && i_wb_ack) - // ||(!wr_outstanding[0] - // && (!o_wb_stb || (!i_wb_stall && i_wb_ack)))); - && (wr_outstanding[0] + (o_wb_stb ? 1:0) == (i_wb_ack ? 1:0)); -`ifdef FORMAL - // Should always be true when we need to drop CYC, on the cycle - // containing the last acknowledgment associated with all of our - // requests. - always @(*) - if (o_wb_cyc && i_wb_ack) - assert(lastack == (wr_outstanding + (o_wb_stb ? 1:0) - <= (i_wb_ack ? 1:0))); - always @(*) - if (!i_reset && wr_outstanding == 0 && o_wb_cyc) - begin - if (!o_wb_stb) - begin - assert(lastack); - end else if (i_wb_ack && !i_wb_stall) - begin - assert(lastack); - end else begin - assert(!lastack); - end - end - always @(*) if (o_wb_cyc) assert(r_lastack == (wr_outstanding <= 1)); -`endif - // }}} - - // wr_outstanding - // {{{ - initial wr_outstanding = 0; - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || i_cfg_mem_err || !o_wb_cyc) - wr_outstanding <= 0; - else case ({ o_wb_stb && !i_wb_stall, i_wb_ack }) - 2'b10: wr_outstanding <= wr_outstanding + 1; - 2'b01: wr_outstanding <= wr_outstanding - 1; - default: begin end - endcase -`ifdef FORMAL - always @(*) - if (!o_wb_stb && wr_outstanding == 0) - assert(!o_wb_cyc); -`endif - // }}} - - assign S_READY = ((wr_state == WR_PUSH) - && (!o_wb_stb || !i_wb_stall) - && !mem_full && !wr_outstanding[LGPIPE]) - || (wr_state == WR_OVERFLOW && wr_midpkt); - - assign o_wb_addr = wr_wb_addr[AW+(WBLSB-2)-1:(WBLSB-2)]; - assign o_wb_we = 1'b1; - assign o_writeptr = r_writeptr; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Memory fill tracking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - end_of_memory <= i_cfg_baseaddr + i_cfg_memsize; - - always @(*) - wide_end_of_memory = { end_of_memory, {(WBLSB){1'b0}} }; - - always @(*) - begin - // Calculate memory fill in bytes - wide_mem_fill = ({r_writeptr, 2'b00 }-{ i_readptr, 2'b00 }); - if (r_writeptr < i_readptr) - wide_mem_fill = wide_mem_fill + wide_memsize; - // Add two pointer words, 4-bytes each, and round up to the - // nearest 4-byte boundary - wide_mem_fill = wide_mem_fill + 11; - if (wr_midpkt && wr_state != WR_OVERFLOW) - wide_mem_fill = wide_mem_fill + wr_pktlen; - wide_mem_fill[1:0] = 2'b00; - if (S_VALID && S_READY) - wide_mem_fill = wide_mem_fill + BUSDW/8; - // if (o_wb_stb) - // wide_mem_fill = wide_mem_fill + BUSDW/8; - // Make sure we always have room for one more word - // since it will take at least one clock cycle for this - // to take effect - wide_mem_fill = wide_mem_fill + (BUSDW/8); - wide_mem_fill[WBLSB-1:0] = 0; - end - - always @(posedge i_clk) - if (i_cfg_reset_fifo) - mem_full <= 0; - else - mem_full <= (wide_mem_fill[WBLSB +: AW+1] >= { 1'b0, i_cfg_memsize }); - - // always @(posedge i_clk) - // if (i_reset || i_cfg_reset_fifo || wr_state != WR_PUSH) - // mem_overflow <= 1'b0; - // else - // mem_overflow <= mem_full && S_VALID; - always @(*) - mem_overflow = mem_full && S_VALID; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Count available packets in memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // No longer needed - // assign o_pktwr_stb = (wr_state == WR_CLEARBUS && !o_wb_stb) - // && (wr_outstanding == (i_wb_ack ? 1:0)); - - // }}} - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, wide_baseaddr, next_wbaddr, - next_wbnull[AW+WBLSB] }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH = LGPIPE+1; - reg f_past_valid; - reg [AW+WBLSB-1:0] wide_readptr; - wire [F_LGDEPTH-1:0] fwr_nreqs, fwr_nacks, - frd_nreqs, frd_nacks, - fwr_outstanding, frd_outstanding; - (* anyconst *) reg [AW-1:0] fc_baseaddr, fc_memsize; - reg [AW+WBLSB:0] wide_committed, f_wide_pktfill; - reg [AW:0] f_end_of_memory; - wire [WBLSB-3:0] f_pkt_alignment; - - localparam LGMX = 11; - wire [LGMX-1:0] fs_word; - wire [12-1:0] fs_packets; - wire [BUSDW/8-1:0] full_sel; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - always @(*) - begin - wide_readptr = 0; - wide_readptr = { i_readptr, 2'b00 }; - end - //////////////////////////////////////////////////////////////////////// - // - // Config: Base address, memsize, memfull - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (i_reset) - assume(i_cfg_reset_fifo); - - always @(posedge i_clk) - if (i_reset || $past(i_reset)) - begin - assume(!i_cfg_mem_err); - end else if ($past(i_cfg_reset_fifo)) - begin - assume(i_cfg_reset_fifo || !i_cfg_mem_err); - assume(!$rose(i_cfg_mem_err)); - end else if ($past(i_cfg_mem_err)) - assume(i_cfg_reset_fifo); - - - always @(*) - assert(BUSDW >= 32); - - always @(*) - begin - assume({ 1'b0, fc_baseaddr } + { 1'b0, fc_memsize } <= (1<= 8); - else if (BUSDW == 64) - assume(fc_memsize >= 4); - else - assume(fc_memsize >= 2); - - wide_committed = wide_writeptr - wide_readptr; - if (wide_writeptr < wide_readptr) - wide_committed = wide_committed - + { fc_memsize, {(WBLSB){1'b0}} }; - - f_wide_pktfill = wide_writeptr - wide_readptr; - if (wide_readptr > wide_writeptr) - f_wide_pktfill = f_wide_pktfill + wide_memsize; - if ((wr_state != WR_PUSH || wr_midpkt) - && wr_state != WR_OVERFLOW) - f_wide_pktfill = f_wide_pktfill + wr_pktlen; - if (wr_state != WR_CLEARBUS) - f_wide_pktfill = f_wide_pktfill + 4; - end - - always @(*) - if (!i_reset && !i_cfg_reset_fifo) - begin - assume(i_cfg_baseaddr == fc_baseaddr); - assume(i_cfg_memsize == fc_memsize); - assume(wide_readptr >= wide_baseaddr); - assume(wide_readptr < wide_baseaddr + wide_memsize); - end - - always @(posedge i_clk) - if (f_past_valid && $past(i_cfg_reset_fifo) && !i_cfg_reset_fifo) - begin - assume($stable(i_cfg_baseaddr)); - assume($stable(i_cfg_memsize)); - end - - always @(posedge i_clk) - if (f_past_valid && $past(i_cfg_reset_fifo)) - begin - assume(wide_readptr == wide_baseaddr); - end else if (!i_reset && !i_cfg_reset_fifo && !$past(i_cfg_reset_fifo)) - begin - assume(wide_readptr <= $past(wide_readptr) + (BUSDW/8)); - if ($past(wide_readptr)+(BUSDW/8) >= wide_baseaddr+wide_memsize) - begin - assume((wide_readptr >= $past(wide_readptr)) - || wide_readptr <= $past(wide_readptr) + (BUSDW/8) - - wide_memsize); - end else begin - assume(wide_readptr >= $past(wide_readptr)); - end - - assert(wide_committed <= wide_memsize); - assert(mem_full || (f_wide_pktfill <= wide_memsize)); - assert(f_wide_pktfill >= wide_committed); - - if ($past(wide_readptr == wide_writeptr)) - assume($stable(wide_readptr)); - - if ($past(wide_readptr) < $past(wide_writeptr)) - begin - assume($past(wide_readptr) <= wide_readptr); - assume(wide_readptr <= $past(wide_writeptr)); - end else begin - assume((wide_readptr >= $past(wide_readptr) - && wide_readptr < wide_end_of_memory) - || wide_readptr <= $past(wide_writeptr)); - end - - if ($past(o_wb_cyc && i_wb_err)) - assume(i_cfg_mem_err); - end - - always @(posedge i_clk) - if (!i_reset && $past(i_reset || i_cfg_reset_fifo) && !i_cfg_reset_fifo) - begin - assume(wide_readptr == wide_baseaddr); - assert(wide_writeptr == wide_baseaddr); - assert(wide_committed == 0); - end - - // Always need at least 8-bytes of room for two packet pointers. - always @(*) - if (!i_reset && !i_cfg_reset_fifo && wr_state != WR_OVERFLOW) - begin - assert(wr_pktlen + 8 <= wide_memsize); - if (wr_pktlen + wide_writeptr < wide_end_of_memory - && wr_state != WR_CLEARPTR) - begin - if (wr_midpkt) - assert(1 || { wr_wb_addr, 2'b00 } == wr_pktlen+ wide_writeptr - + 4 - (BUSDW/8)); - end - if (wr_midpkt && wr_state == WR_PUSH && !S_ABORT) - assert({ fs_word, {(WBLSB){1'b0}} } == wr_pktlen); - end - - always @(*) - if (i_cfg_mem_err) - assume(i_cfg_reset_fifo); - - always @(*) - if (!i_reset && ((i_cfg_baseaddr == 0) || (i_cfg_memsize == 0))) - assume(i_cfg_mem_err); - - always @(*) - f_end_of_memory = i_cfg_baseaddr + i_cfg_memsize; - - always @(*) - if (!i_reset && !i_cfg_reset_fifo) - begin - assert(f_end_of_memory[AW-1:0] == end_of_memory); - if (f_end_of_memory[AW]) - assert(f_end_of_memory[AW-1:0] == 0); - end - - always @(posedge i_clk) - if (!i_reset && !i_cfg_reset_fifo) - begin - assert(wide_writeptr >= wide_baseaddr); - assert(wide_writeptr < wide_end_of_memory); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Packet stream - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - faxin_slave #( - .DATA_WIDTH(BUSDW), - .MIN_LENGTH(2), - .MAX_LENGTH(1<<(LGMX-1)), - .LGMX(LGMX) - ) faxin ( - .S_AXI_ACLK(i_clk), - .S_AXI_ARESETN(!i_reset), - .S_AXIN_VALID(S_VALID), - .S_AXIN_READY(S_READY), - .S_AXIN_DATA(S_DATA), - .S_AXIN_BYTES(S_BYTES), - .S_AXIN_LAST(S_LAST), - .S_AXIN_ABORT(S_ABORT), - // - .f_stream_word(fs_word), - .f_packets_rcvd(fs_packets) - ); - - always @(posedge i_clk) - if (!i_reset && !S_ABORT) - assert(syncd == (fs_word == 0)); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // WB - // {{{ - - fwb_master #( - .AW(AW), .DW(BUSDW), .F_LGDEPTH(F_LGDEPTH) - ) fwb_wr ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - // - .i_wb_cyc( o_wb_cyc), - .i_wb_stb( o_wb_stb), - .i_wb_we( 1'b1 ), - .i_wb_addr( o_wb_addr), - .i_wb_data( o_wb_data), - .i_wb_sel( o_wb_sel ), - .i_wb_stall(i_wb_stall), - .i_wb_ack( i_wb_ack), - .i_wb_idata({(BUSDW){1'b0}}), - .i_wb_err( i_wb_err), - // - .f_nreqs(fwr_nreqs), - .f_nacks(fwr_nacks), - .f_outstanding(fwr_outstanding) - // }}} - ); - - always @(*) - if (!i_reset && o_wb_cyc) - assert(wr_outstanding == fwr_outstanding); - - always @(*) - if (!i_reset && o_wb_stb) - assert(o_wb_sel != 0); - - generate if (OPT_LITTLE_ENDIAN) - begin : FGEN_FULL_SELLE - wire [2*BUSDW/8-1:0] fdbl_sel; - assign fdbl_sel = { {(BUSDW/8){1'b0}}, {(BUSDW/8){1'b1}} } - >> (dshift[WBLSB-3:0]*4); - - assign full_sel = fdbl_sel[2*BUSDW/8-1:BUSDW/8]; - end else begin : FGEN_FULL_SEL - assign full_sel = { {(BUSDW/8){1'b1}}, {(BUSDW/8){1'b0}} } - >> (dshift[WBLSB-3:0]*4); - end endgenerate - - always @(*) - if (!i_reset) - begin - if (&r_writeptr[WBLSB-3:0]) - assert(next_wr_sel == 0); - else if (wr_midpkt && wr_state == WR_PUSH && fs_word > 1) - assert(next_wr_sel == full_sel); // !!! - end - - always @(posedge i_clk) - if (!i_reset && !i_cfg_reset_fifo - && (o_wb_stb || wr_state != WR_CLEARPTR)) - begin - assert(o_wb_addr >= i_cfg_baseaddr); // !!! - assert(o_wb_addr < (i_cfg_baseaddr + i_cfg_memsize)); - end - - assign f_pkt_alignment = r_writeptr + 1; - always @(posedge i_clk) - if (!i_reset && !i_cfg_reset_fifo && o_wb_stb && wr_state == WR_PUSH) - begin - if (wr_midpkt && fs_word > 0 && (f_pkt_alignment == 0)) - assert(&o_wb_sel); - end - - always @(posedge i_clk) - if (!i_reset && !i_cfg_reset_fifo) - case(wr_state) - WR_CLEARPTR: begin - assert(!wr_midpkt); - assert(!o_wb_cyc); - assert(!o_wb_stb); - assert(o_wb_addr == 0); - assert(o_wb_data == 0); - assert(o_wb_sel == 0); - assert(r_writeptr == { i_cfg_baseaddr, {(WBLSB-2){1'b0}} }); - assert(i_readptr == r_writeptr); - assert(wr_pktlen == 0); - // assert(fs_word == 0); - end - WR_PUSH: assert(!wr_midpkt || !syncd); - WR_FLUSH: begin - assert(fs_word == 0); - assert(wr_midpkt); - end - WR_NULL: begin - assert(fs_word == 0); - assert(wr_midpkt); - end - WR_LENGTH: begin - assert(fs_word == 0); - assert(wr_midpkt); - end - WR_CLEARBUS: begin - assert(fs_word == 0); - assert(wr_midpkt); - end - WR_OVERFLOW: begin end - default: assert(0); - endcase - - always @(*) - if (!i_reset && !i_cfg_reset_fifo && wr_midpkt && wr_state == WR_PUSH) - begin - assert(next_wr_sel == next_dblwide_sel[BUSDW/8-1:0]); - end - - always @(*) - if (!i_reset && !i_cfg_reset_fifo - && wr_state != WR_PUSH && wr_state != WR_OVERFLOW) - begin - assert(wide_committed <= wide_memsize); - assert(wr_pktlen + 8 <= wide_memsize); - assert(wide_committed + wr_pktlen + 8 <= wide_memsize); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg [3:0] cvr_packets; - - initial cvr_packets = 0; - always @(posedge i_clk) - if (i_reset || i_cfg_reset_fifo || i_wb_err || i_cfg_mem_err) - cvr_packets <= 0; - else if (!cvr_packets[3] && wr_state == WR_CLEARBUS && !o_wb_stb - && (wr_outstanding == (i_wb_ack ? 1:0))) - cvr_packets <= cvr_packets + 1; - - always @(posedge i_clk) - if (!i_reset && !i_cfg_reset_fifo) - begin - cover(cvr_packets == 1); - cover(cvr_packets == 2); - cover(cvr_packets == 3); - // - cover(wr_state == WR_NULL && mem_full); - cover(wr_state == WR_LENGTH && mem_full); - cover(wr_state == WR_CLEARBUS && mem_full); - cover(wr_state == WR_OVERFLOW); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Careless assumptions - // {{{ - - // always @(*) assume(!mem_full); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/net/routecore.v b/delete_later/rtl/net/routecore.v deleted file mode 100644 index 85b1ae8..0000000 --- a/delete_later/rtl/net/routecore.v +++ /dev/null @@ -1,863 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: routecore.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is intended to be the core of the network router: the -// routing table. When a packet is received, from any interface, -// it is registered in this table together with the interface it comes -// from. Then, when we later want to transmit a packet, the table can be -// queried for which port the given MAC address was last seen on. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module routecore #( - // {{{ - parameter [0:0] OPT_SKIDBUFFER = 1'b0, - parameter [0:0] OPT_LOWPOWER = 1'b1, - parameter [0:0] OPT_LITTLE_ENDIAN= 1'b0, - // parameter [0:0] OPT_DEFBROADCAST = 1'b0 - // parameter [0:0] OPT_ONE_TO_MANY = 1'b0 - parameter NETH = 4, // Number of incoming eth ports - // PKTDW is the # of bits per clock cycle or beat of both the - // {{{ - // incoming and outgoing packet data. In order to properly - // cross clock domains, PKTDW must be greater than the - // original source & sink. So if the Ethernet interface will - // generate (roughly) 32'bits per clock, PKTDW must be at least - // 64-bits per clock. - parameter PKTDW = 128, - // }}} - localparam PKTBYW = $clog2(PKTDW/8), - // BUSDW is the bits per clock cycle or beat of the WB memory - // {{{ - // bus. A width conversion may need to take place within the - // PKTVFIFO to adjust from PKTDW to BUSDW and back again. - parameter BUSDW = 512, // Bits per clock cycle - // }}} - // parameter BROADCAST_PORT = NETH, - // parameter DEFAULT_PORT = BROADCAST_PORT, - // parameter LGTBL = 6, // Log_2(NTBL entries) - // localparam NTBL = (1<rxtbl: Broadcast Rx MACs to each channel's router - // {{{ - axisbroadcast #( - .C_AXIS_DATA_WIDTH(MACW), .NM(NETH) - ) u_rxtbl_broadcast ( - // {{{ - .S_AXI_ACLK(i_clk), - .S_AXI_ARESETN(i_reset || ETH_RESET[geth]), - // - .S_AXIS_TVALID(smac_valid), - .S_AXIS_TREADY(smac_ready), - .S_AXIS_TDATA(smac_data), - // - .M_AXIS_TVALID(rxtbl_valid[geth * NETH +: NETH]), - .M_AXIS_TREADY(rxtbl_ready[geth * NETH +: NETH] | ETH_RESET), - .M_AXIS_TDATA(rxtbl_data[geth * MACW * NETH +: MACW * NETH]) - // }}} - ); - // }}} - - // All packets go to memory: tomem -> (dma_wb) -> mmout - // {{{ - assign ctrl_stb[geth] = i_ctrl_stb - && i_ctrl_addr[2 +: $clog2(NMEM)] == geth; - - if (OPT_VFIFO) - begin : GEN_VFIFO - - pktvfifo #( - // {{{ - .AW(AW), // Bus address width - .PKTDW(PKTDW), // Packet data width - .BUSDW(BUSDW), // Bus width - // DEF_BASEADDR: The VFIFO default base - // address -- set this and the default memory - // size to nonzero in order to cause the VFIFO - // to start automaticallt w/o CPU intervention. - // Both addresses are *WORD* addresses, so need - // to be shifted by $clog2(BUSDW/8) to get - // their proper bus address location. - .DEF_BASEADDR(DEF_BASEADDR + geth*DEF_SUBSIZE), - .DEF_MEMSIZE(DEF_SUBSIZE), - .OPT_LITTLE_ENDIAN(OPT_LITTLE_ENDIAN), - .OPT_LOWPOWER(OPT_LOWPOWER) - // }}} - ) u_pktvfifo ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset || ETH_RESET[geth]), - // Bus control port - // {{{ - .i_ctrl_cyc(i_ctrl_cyc), .i_ctrl_stb(i_ctrl_stb - && i_ctrl_addr[2 +: $clog2(NMEM)] == geth), - .i_ctrl_we(i_ctrl_we), .i_ctrl_addr(i_ctrl_addr[1:0]), - .i_ctrl_data(i_ctrl_data), .i_ctrl_sel(i_ctrl_sel), - .o_ctrl_stall(ctrl_stall[geth]), - .o_ctrl_ack( ctrl_ack[ geth]), - .o_ctrl_data( ctrl_data[ geth * 32 +: 32]), - // }}} - // Incoming packet - // {{{ - .S_VALID(tomem_valid[geth]), - .S_READY(tomem_ready[geth]), - .S_DATA( tomem_data[ geth * PKTDW +: PKTDW]), - .S_BYTES(tomem_bytes[geth * PKTBYW +: PKTBYW]), - .S_LAST( tomem_last[geth]), - .S_ABORT(tomem_abort[geth]), - // }}} - // DMA bus interface - // {{{ - .o_wb_cyc(vfifo_cyc[ geth]), - .o_wb_stb(vfifo_stb[ geth]), - .o_wb_we(vfifo_we[ geth]), - .o_wb_addr(vfifo_addr[ geth * AW +: AW]), - .o_wb_data(vfifo_data[ geth * BUSDW +: BUSDW ]), - .o_wb_sel(vfifo_sel[ geth * BUSDW/8 +: BUSDW/8]), - .i_wb_stall(vfifo_stall[geth]), - .i_wb_ack(vfifo_ack[ geth]), - .i_wb_data(vfifo_idata[ geth * BUSDW +: BUSDW]), - .i_wb_err(vfifo_err[ geth]), - // This needs to go to a crossbar next ... - // }}} - // Outgoing packet - // {{{ - .M_VALID(mmout_valid), - .M_READY(mmout_ready), - .M_DATA( mmout_data), - .M_BYTES(mmout_bytes), - .M_LAST( mmout_last), - .M_ABORT(mmout_abort) - // }}} - // }}} - ); - - end else begin : NO_VFIFO - reg r_ctrl_ack; - - netfifo #( - // {{{ - .BW(PKTDW + $clog2(PKTDW/8)), - .LGFLEN(10) - // }}} - ) u_netfifo ( - // {{{ - .S_AXI_ACLK(i_clk), - .S_AXI_ARESETN(!i_reset && !ETH_RESET[geth]), - // Incoming packet - // {{{ - .S_AXIN_VALID(tomem_valid[geth]), - .S_AXIN_READY(tomem_ready[geth]), - .S_AXIN_DATA({ tomem_bytes[geth * PKTBYW +: PKTBYW], - tomem_data[ geth * PKTDW +: PKTDW] }), - .S_AXIN_LAST( tomem_last[geth]), - .S_AXIN_ABORT(tomem_abort[geth]), - // }}} - // (No) DMA bus interface - // Outgoing packet - // {{{ - .M_AXIN_VALID(mmout_valid), - .M_AXIN_READY(mmout_ready), - .M_AXIN_DATA({ mmout_bytes, mmout_data }), - .M_AXIN_LAST( mmout_last), - .M_AXIN_ABORT(mmout_abort) - // }}} - // }}} - ); - - assign vfifo_cyc[geth] = 1'b0; - assign vfifo_stb[geth] = 1'b0; - assign vfifo_we[geth] = 1'b0; - assign vfifo_addr[geth * AW +: AW]= {(AW){1'b0}}; - assign vfifo_data[geth * BUSDW +: BUSDW]= {(BUSDW){1'b0}}; - assign vfifo_sel[geth * BUSDW/8 +: BUSDW/8] = {(BUSDW/8){1'b0}}; - - initial r_ctrl_ack = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_ctrl_cyc) - r_ctrl_ack <= 1'b0; - else - r_ctrl_ack <= i_ctrl_stb - && i_ctrl_addr[2 +: $clog2(NMEM)]==geth; - - assign ctrl_stall[geth] = 1'b0; - assign ctrl_ack[geth] = r_ctrl_ack; - assign ctrl_data[ geth * 32 +: 32] = 32'h0; - end - // }}} - - // mmout->rtd, On return from memory, lookup the destinations - // {{{ - txgetports #( - // {{{ - .OPT_SKIDBUFFER(OPT_SKIDBUFFER), - .OPT_LOWPOWER(OPT_LOWPOWER), - .NETH(NETH), .DW(PKTDW), .MACW(MACW) - // }}} - ) u_txgetports ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .S_VALID(mmout_valid), .S_READY(mmout_ready), - .S_DATA(mmout_data), .S_BYTES(mmout_bytes), - .S_LAST(mmout_last), .S_ABORT(mmout_abort), - // - // - .TBL_REQUEST(lkup_request), .TBL_VALID(lkup_valid), - .TBL_MAC(lkup_dstmac),.TBL_PORT(lkup_port & ~THIS_PORT), - // - .M_VALID(rtd_valid), .M_READY(rtd_ready), - .M_DATA(rtd_data), .M_BYTES(rtd_bytes), - .M_LAST(rtd_last), .M_ABORT(rtd_abort), - .M_PORT(rtd_port) - // - // }}} - ); - // }}} - - // rtd->txx Broadcast our packet to all interested ports - // {{{ - axinbroadcast #( - .OPT_SKIDBUFFER(OPT_SKIDBUFFER), - .OPT_LOWPOWER(OPT_LOWPOWER), - .NOUT(NETH), .DW(PKTDW) - ) u_rtdbroadcast ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - // - .i_cfg_active(~ETH_RESET), - // rtd_*, packet with routing - // {{{ - .S_VALID(rtd_valid), - .S_READY(rtd_ready), - .S_DATA(rtd_data), - .S_PORT(rtd_port), - .S_BYTES(rtd_bytes), - .S_LAST(rtd_last), - .S_ABORT(rtd_abort), - // }}} - // txx_* - // {{{ - .M_VALID(txx_valid[geth * NETH +: NETH]), - .M_READY(txx_ready[geth * NETH +: NETH] | ETH_RESET), - .M_DATA(txx_data[geth * PKTDW * NETH +: PKTDW * NETH]), - .M_BYTES(txx_bytes[geth * PKTBYW * NETH - +: PKTBYW * NETH]), - .M_LAST(txx_last[geth * NETH +: NETH]), - .M_ABORT(txx_abort[geth * NETH +: NETH]) - // }}} - // }}} - ); - // }}} - - // Arbitrate from among packets from other ports - // {{{ - always @(*) - for(iport=0; iportrxtbl: Broadcast Rx MACs to each channel's router - // {{{ - axisbroadcast #( - .C_AXIS_DATA_WIDTH(MACW), .NM(NETH) - ) u_rxtbl_broadcast ( - // {{{ - .S_AXI_ACLK(i_clk), - .S_AXI_ARESETN(i_reset || ETH_RESET[NETH-1]), - // - .S_AXIS_TVALID(smac_valid), - .S_AXIS_TREADY(smac_ready), - .S_AXIS_TDATA(smac_data), - // - .M_AXIS_TVALID(rxtbl_valid[(NETH-1) * NETH +: NETH]), - .M_AXIS_TREADY(rxtbl_ready[(NETH-1) * NETH +: NETH] | ETH_RESET), - .M_AXIS_TDATA(rxtbl_data[(NETH-1) * MACW * NETH +: MACW * NETH]) - // }}} - ); - // }}} - - // The big difference--incoming CPU pkts do *not* go to memory - - // mmout->rtd, On return from memory, lookup the destinations - // {{{ - txgetports #( - // {{{ - .OPT_SKIDBUFFER(OPT_SKIDBUFFER), - .OPT_LOWPOWER(OPT_LOWPOWER), - .NETH(NETH), .DW(PKTDW), .MACW(MACW) - // }}} - ) u_txgetports ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .S_VALID(mmout_valid), .S_READY(mmout_ready), - .S_DATA(mmout_data), .S_BYTES(mmout_bytes), - .S_LAST(mmout_last), .S_ABORT(mmout_abort), - // - // - .TBL_REQUEST(lkup_request), .TBL_VALID(lkup_valid), - .TBL_MAC(lkup_dstmac),.TBL_PORT(lkup_port & ~THIS_PORT), - // - .M_VALID(rtd_valid), .M_READY(rtd_ready), - .M_DATA(rtd_data), .M_BYTES(rtd_bytes), - .M_LAST(rtd_last), .M_ABORT(rtd_abort), - .M_PORT(rtd_port) - // - // }}} - ); - // }}} - - // rtd->txx Broadcast our packet to all interested ports - // {{{ - axinbroadcast #( - .OPT_SKIDBUFFER(OPT_SKIDBUFFER), - .OPT_LOWPOWER(OPT_LOWPOWER), - .NOUT(NETH), .DW(PKTDW) - ) u_rtdbroadcast ( - // {{{ - .i_clk(i_clk), - .i_reset(i_reset), - // - .i_cfg_active(~ETH_RESET), - // rtd_*, packet with routing - // {{{ - .S_VALID(rtd_valid), - .S_READY(rtd_ready), - .S_DATA(rtd_data), - .S_PORT(rtd_port), - .S_BYTES(rtd_bytes), - .S_LAST(rtd_last), - .S_ABORT(rtd_abort), - // }}} - // txx_* - // {{{ - .M_VALID(txx_valid[(NETH-1) * NETH +: NETH]), - .M_READY(txx_ready[(NETH-1) * NETH +: NETH] | ETH_RESET), - .M_DATA(txx_data[(NETH-1) * PKTDW * NETH +: PKTDW * NETH]), - .M_BYTES(txx_bytes[(NETH-1) * PKTBYW * NETH - +: PKTBYW * NETH]), - .M_LAST(txx_last[(NETH-1) * NETH +: NETH]), - .M_ABORT(txx_abort[(NETH-1) * NETH +: NETH]) - // }}} - // }}} - ); - // }}} - - // Arbitrate from among packets from other ports - // {{{ - always @(*) - for(iport=0; iport 1); - tbl_age[gk] <= tbl_age[gk] - 1; - end - - always @(posedge i_clk) - if (tbl_write[gk]) - begin - tbl_mac[gk] <= rxarb_srcmac; - tbl_port[gk] <= rxarb_port; - end - - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Look up which request a transmit port should get sent to - // {{{ - - generate for(gk=0; gk BUFG -> MMCM -> TXUSRCLK2 -> BUFG - // TXUSRCLK -> BUFG - // TXUSRCLK2 = TXUSRCLK / 2 - // Since TX_INT_DATA_WIDTH=1, required for high speed - // or other 8-byte modes - // }}} - - assign S_READY[gk] = tx_reset_done && tx_gearbox_ready; - - assign gtx_rx_fault = gtx_reset || !rx_cdr_lock; - - always @(posedge M_CLK[gk] or posedge gtx_rx_fault) - if (gtx_rx_fault) - { r_phy_fault, rx_fault_pipe } <= -1; - else - { r_phy_fault, rx_fault_pipe } <= { rx_fault_pipe, 1'b0 }; - - assign o_phy_fault[gk] = r_phy_fault; - - BUFG rxbuf(.I(unbuf_rx_clk[gk]), .O(M_CLK[gk])); - BUFG txbuf(.I(unbuf_tx_clk[gk]), .O(S_CLK[gk])); - end endgenerate -endmodule diff --git a/delete_later/rtl/netled.v b/delete_later/rtl/netled.v deleted file mode 100644 index f0406b5..0000000 --- a/delete_later/rtl/netled.v +++ /dev/null @@ -1,164 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: netled -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Produce an LED sequence onto the Ethernet 10Gb LEDs which can -// be used to demonstrate that the LEDs work as desired. This -// is scaffolding IP, and will be tossed rather than used in operation. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -`default_nettype none -// }}} -module netled #( - parameter NLINKS=4 - ) ( - input wire i_clk, - output reg [NLINKS-1:0] o_linkup, - output reg [NLINKS-1:0] o_activity - ); - - reg r_pps; - reg [39:0] rtl_counter; - reg [6:0] s_counter; - - initial rtl_counter = 0; - always @(posedge i_clk) - { r_pps, rtl_counter } <= rtl_counter + 40'd10_995; - - always @(posedge i_clk) - if (r_pps) - { s_counter } <= s_counter + 1; - - - always @(posedge i_clk) - case(s_counter[6:4]) - 3'h0: begin - o_linkup[0] <= s_counter[2:0] == 3'h0; - o_linkup[1] <= s_counter[2:0] == 3'h1; - o_linkup[2] <= s_counter[2:0] == 3'h2; - o_linkup[3] <= s_counter[2:0] == 3'h3; - - o_activity <= 4'h0; - end - 3'h1: begin - o_linkup <= 4'h0; - - o_activity[0] <= s_counter[2:0] == 3'h0; - o_activity[1] <= s_counter[2:0] == 3'h1; - o_activity[2] <= s_counter[2:0] == 3'h2; - o_activity[3] <= s_counter[2:0] == 3'h3; - end - 3'h2: begin - o_linkup[0] <= s_counter[2:0] == 3'h0; - o_linkup[1] <= s_counter[2:0] == 3'h1; - o_linkup[2] <= s_counter[2:0] == 3'h2; - o_linkup[3] <= s_counter[2:0] == 3'h3; - - o_activity[0] <= s_counter[2:0] == 3'h0; - o_activity[1] <= s_counter[2:0] == 3'h1; - o_activity[2] <= s_counter[2:0] == 3'h2; - o_activity[3] <= s_counter[2:0] == 3'h3; - end - 3'h3: begin - o_linkup[0] <= rtl_counter[37]; - o_linkup[1] <= rtl_counter[37]; - o_linkup[2] <= rtl_counter[37]; - o_linkup[3] <= rtl_counter[37]; - - o_activity[0] <= rtl_counter[37] ^ s_counter[3]; - o_activity[1] <= rtl_counter[37] ^ s_counter[3]; - o_activity[2] <= rtl_counter[37] ^ s_counter[3]; - o_activity[3] <= rtl_counter[37] ^ s_counter[3]; - end - 3'h4: begin - o_linkup[0] <= rtl_counter[38]; - o_linkup[1] <= rtl_counter[38]; - o_linkup[2] <= rtl_counter[38]; - o_linkup[3] <= rtl_counter[38]; - - o_activity[0] <= rtl_counter[38] ^ s_counter[3]; - o_activity[1] <= rtl_counter[38] ^ s_counter[3]; - o_activity[2] <= rtl_counter[38] ^ s_counter[3]; - o_activity[3] <= rtl_counter[38] ^ s_counter[3]; - end - 3'h5: begin - o_linkup[0] <= rtl_counter[39]; - o_linkup[1] <= rtl_counter[39]; - o_linkup[2] <= rtl_counter[39]; - o_linkup[3] <= rtl_counter[39]; - - o_activity[0] <= rtl_counter[39] ^ s_counter[3]; - o_activity[1] <= rtl_counter[39] ^ s_counter[3]; - o_activity[2] <= rtl_counter[39] ^ s_counter[3]; - o_activity[3] <= rtl_counter[39] ^ s_counter[3]; - end - 3'h6: begin - case({ s_counter[2:0], rtl_counter[39:38] }) - 5'h00: { o_linkup, o_activity } <= { 4'h1, 4'h0 }; - 5'h01: { o_linkup, o_activity } <= { 4'h2, 4'h1 }; - 5'h02: { o_linkup, o_activity } <= { 4'h4, 4'h2 }; - 5'h03: { o_linkup, o_activity } <= { 4'h8, 4'h4 }; - 5'h04: { o_linkup, o_activity } <= { 4'h4, 4'h8 }; - 5'h05: { o_linkup, o_activity } <= { 4'h2, 4'h4 }; - 5'h06: { o_linkup, o_activity } <= { 4'h1, 4'h2 }; - 5'h07: { o_linkup, o_activity } <= { 4'h0, 4'h1 }; - // - 5'h08: { o_linkup, o_activity } <= { 4'h1, 4'h0 }; - 5'h09: { o_linkup, o_activity } <= { 4'h2, 4'h0 }; - 5'h0a: { o_linkup, o_activity } <= { 4'h4, 4'h1 }; - 5'h0b: { o_linkup, o_activity } <= { 4'h8, 4'h2 }; - 5'h0c: { o_linkup, o_activity } <= { 4'h4, 4'h4 }; - 5'h0d: { o_linkup, o_activity } <= { 4'h2, 4'h8 }; - 5'h0e: { o_linkup, o_activity } <= { 4'h1, 4'h4 }; - 5'h0f: { o_linkup, o_activity } <= { 4'h0, 4'h2 }; - // - 5'h10: { o_linkup, o_activity } <= { 4'h1, 4'h0 }; - 5'h11: { o_linkup, o_activity } <= { 4'h2, 4'h0 }; - 5'h12: { o_linkup, o_activity } <= { 4'h4, 4'h0 }; - 5'h13: { o_linkup, o_activity } <= { 4'h8, 4'h0 }; - 5'h14: { o_linkup, o_activity } <= { 4'h8, 4'h1 }; - 5'h15: { o_linkup, o_activity } <= { 4'h8, 4'h2 }; - 5'h16: { o_linkup, o_activity } <= { 4'h8, 4'h4 }; - 5'h17: { o_linkup, o_activity } <= { 4'h8, 4'h8 }; - // - 5'h18: { o_linkup, o_activity } <= { 4'h8, 4'h4 }; - 5'h19: { o_linkup, o_activity } <= { 4'h8, 4'h2 }; - 5'h1a: { o_linkup, o_activity } <= { 4'h8, 4'h1 }; - 5'h1b: { o_linkup, o_activity } <= { 4'h8, 4'h0 }; - 5'h1c: { o_linkup, o_activity } <= { 4'h4, 4'h0 }; - 5'h1d: { o_linkup, o_activity } <= { 4'h2, 4'h0 }; - 5'h1e: { o_linkup, o_activity } <= { 4'h1, 4'h0 }; - 5'h1f: { o_linkup, o_activity } <= { 4'h0, 4'h0 }; - // - endcase end - default: begin - o_linkup <= 0; - o_activity <= 0; - end - endcase - -endmodule diff --git a/delete_later/rtl/obj_dir/Vmain.cpp b/delete_later/rtl/obj_dir/Vmain.cpp deleted file mode 100644 index 427d4e3..0000000 --- a/delete_later/rtl/obj_dir/Vmain.cpp +++ /dev/null @@ -1,208 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Model implementation (design independent parts) - -#include "Vmain.h" -#include "Vmain__Syms.h" -#include "verilated_vcd_c.h" -#include "verilated_dpi.h" - -//============================================================ -// Constructors - -Vmain::Vmain(VerilatedContext* _vcontextp__, const char* _vcname__) - : VerilatedModel{*_vcontextp__} - , vlSymsp{new Vmain__Syms(contextp(), _vcname__, this)} - , i_clk{vlSymsp->TOP.i_clk} - , i_reset{vlSymsp->TOP.i_reset} - , i_ddr3_controller_idelayctrl_rdy{vlSymsp->TOP.i_ddr3_controller_idelayctrl_rdy} - , o_ddr3_controller_dqs_tri_control{vlSymsp->TOP.o_ddr3_controller_dqs_tri_control} - , o_ddr3_controller_dq_tri_control{vlSymsp->TOP.o_ddr3_controller_dq_tri_control} - , o_ddr3_controller_toggle_dqs{vlSymsp->TOP.o_ddr3_controller_toggle_dqs} - , o_ddr3_controller_odelay_data_cntvaluein{vlSymsp->TOP.o_ddr3_controller_odelay_data_cntvaluein} - , o_ddr3_controller_odelay_dqs_cntvaluein{vlSymsp->TOP.o_ddr3_controller_odelay_dqs_cntvaluein} - , o_ddr3_controller_idelay_data_cntvaluein{vlSymsp->TOP.o_ddr3_controller_idelay_data_cntvaluein} - , o_ddr3_controller_idelay_dqs_cntvaluein{vlSymsp->TOP.o_ddr3_controller_idelay_dqs_cntvaluein} - , o_ddr3_controller_odelay_data_ld{vlSymsp->TOP.o_ddr3_controller_odelay_data_ld} - , o_ddr3_controller_odelay_dqs_ld{vlSymsp->TOP.o_ddr3_controller_odelay_dqs_ld} - , o_ddr3_controller_idelay_data_ld{vlSymsp->TOP.o_ddr3_controller_idelay_data_ld} - , o_ddr3_controller_idelay_dqs_ld{vlSymsp->TOP.o_ddr3_controller_idelay_dqs_ld} - , o_ddr3_controller_bitslip{vlSymsp->TOP.o_ddr3_controller_bitslip} - , o_sirefclk_word{vlSymsp->TOP.o_sirefclk_word} - , o_sirefclk_ce{vlSymsp->TOP.o_sirefclk_ce} - , i_fan_sda{vlSymsp->TOP.i_fan_sda} - , i_fan_scl{vlSymsp->TOP.i_fan_scl} - , o_fan_sda{vlSymsp->TOP.o_fan_sda} - , o_fan_scl{vlSymsp->TOP.o_fan_scl} - , o_fpga_pwm{vlSymsp->TOP.o_fpga_pwm} - , o_sys_pwm{vlSymsp->TOP.o_sys_pwm} - , i_fan_tach{vlSymsp->TOP.i_fan_tach} - , o_emmc_clk{vlSymsp->TOP.o_emmc_clk} - , i_emmc_ds{vlSymsp->TOP.i_emmc_ds} - , io_emmc_cmd_tristate{vlSymsp->TOP.io_emmc_cmd_tristate} - , o_emmc_cmd{vlSymsp->TOP.o_emmc_cmd} - , i_emmc_cmd{vlSymsp->TOP.i_emmc_cmd} - , io_emmc_dat_tristate{vlSymsp->TOP.io_emmc_dat_tristate} - , o_emmc_dat{vlSymsp->TOP.o_emmc_dat} - , i_emmc_dat{vlSymsp->TOP.i_emmc_dat} - , i_emmc_detect{vlSymsp->TOP.i_emmc_detect} - , i_i2c_sda{vlSymsp->TOP.i_i2c_sda} - , i_i2c_scl{vlSymsp->TOP.i_i2c_scl} - , o_i2c_sda{vlSymsp->TOP.o_i2c_sda} - , o_i2c_scl{vlSymsp->TOP.o_i2c_scl} - , o_sdcard_clk{vlSymsp->TOP.o_sdcard_clk} - , i_sdcard_ds{vlSymsp->TOP.i_sdcard_ds} - , io_sdcard_cmd_tristate{vlSymsp->TOP.io_sdcard_cmd_tristate} - , o_sdcard_cmd{vlSymsp->TOP.o_sdcard_cmd} - , i_sdcard_cmd{vlSymsp->TOP.i_sdcard_cmd} - , io_sdcard_dat_tristate{vlSymsp->TOP.io_sdcard_dat_tristate} - , o_sdcard_dat{vlSymsp->TOP.o_sdcard_dat} - , i_sdcard_dat{vlSymsp->TOP.i_sdcard_dat} - , i_sdcard_detect{vlSymsp->TOP.i_sdcard_detect} - , cpu_sim_cyc{vlSymsp->TOP.cpu_sim_cyc} - , cpu_sim_stb{vlSymsp->TOP.cpu_sim_stb} - , cpu_sim_we{vlSymsp->TOP.cpu_sim_we} - , cpu_sim_addr{vlSymsp->TOP.cpu_sim_addr} - , cpu_sim_stall{vlSymsp->TOP.cpu_sim_stall} - , cpu_sim_ack{vlSymsp->TOP.cpu_sim_ack} - , cpu_prof_stb{vlSymsp->TOP.cpu_prof_stb} - , i_cpu_reset{vlSymsp->TOP.i_cpu_reset} - , i_clk200{vlSymsp->TOP.i_clk200} - , i_wbu_uart_rx{vlSymsp->TOP.i_wbu_uart_rx} - , o_wbu_uart_tx{vlSymsp->TOP.o_wbu_uart_tx} - , o_wbu_uart_cts_n{vlSymsp->TOP.o_wbu_uart_cts_n} - , o_gpio{vlSymsp->TOP.o_gpio} - , i_sw{vlSymsp->TOP.i_sw} - , i_btn{vlSymsp->TOP.i_btn} - , o_led{vlSymsp->TOP.o_led} - , i_gpio{vlSymsp->TOP.i_gpio} - , i_ddr3_controller_iserdes_data{vlSymsp->TOP.i_ddr3_controller_iserdes_data} - , o_ddr3_controller_cmd{vlSymsp->TOP.o_ddr3_controller_cmd} - , o_ddr3_controller_data{vlSymsp->TOP.o_ddr3_controller_data} - , cpu_sim_data{vlSymsp->TOP.cpu_sim_data} - , cpu_sim_idata{vlSymsp->TOP.cpu_sim_idata} - , cpu_prof_addr{vlSymsp->TOP.cpu_prof_addr} - , cpu_prof_ticks{vlSymsp->TOP.cpu_prof_ticks} - , i_ddr3_controller_iserdes_dqs{vlSymsp->TOP.i_ddr3_controller_iserdes_dqs} - , i_ddr3_controller_iserdes_bitslip_reference{vlSymsp->TOP.i_ddr3_controller_iserdes_bitslip_reference} - , o_ddr3_controller_dm{vlSymsp->TOP.o_ddr3_controller_dm} - , rootp{&(vlSymsp->TOP)} -{ - // Register model with the context - contextp()->addModel(this); -} - -Vmain::Vmain(const char* _vcname__) - : Vmain(Verilated::threadContextp(), _vcname__) -{ -} - -//============================================================ -// Destructor - -Vmain::~Vmain() { - delete vlSymsp; -} - -//============================================================ -// Evaluation function - -#ifdef VL_DEBUG -void Vmain___024root___eval_debug_assertions(Vmain___024root* vlSelf); -#endif // VL_DEBUG -void Vmain___024root___eval_static(Vmain___024root* vlSelf); -void Vmain___024root___eval_initial(Vmain___024root* vlSelf); -void Vmain___024root___eval_settle(Vmain___024root* vlSelf); -void Vmain___024root___eval(Vmain___024root* vlSelf); - -void Vmain::eval_step() { - VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vmain::eval_step\n"); ); -#ifdef VL_DEBUG - // Debug assertions - Vmain___024root___eval_debug_assertions(&(vlSymsp->TOP)); -#endif // VL_DEBUG - vlSymsp->__Vm_activity = true; - vlSymsp->__Vm_deleter.deleteAll(); - if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) { - vlSymsp->__Vm_didInit = true; - VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n");); - Vmain___024root___eval_static(&(vlSymsp->TOP)); - Vmain___024root___eval_initial(&(vlSymsp->TOP)); - Vmain___024root___eval_settle(&(vlSymsp->TOP)); - } - // MTask 0 start - VL_DEBUG_IF(VL_DBG_MSGF("MTask0 starting\n");); - Verilated::mtaskId(0); - VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n");); - Vmain___024root___eval(&(vlSymsp->TOP)); - // Evaluate cleanup - Verilated::endOfThreadMTask(vlSymsp->__Vm_evalMsgQp); - Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp); -} - -//============================================================ -// Events and timing -bool Vmain::eventsPending() { return false; } - -uint64_t Vmain::nextTimeSlot() { - VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: No delays in the design"); - return 0; -} - -//============================================================ -// Utilities - -const char* Vmain::name() const { - return vlSymsp->name(); -} - -//============================================================ -// Invoke final blocks - -void Vmain___024root___eval_final(Vmain___024root* vlSelf); - -VL_ATTR_COLD void Vmain::final() { - Vmain___024root___eval_final(&(vlSymsp->TOP)); -} - -//============================================================ -// Implementations of abstract methods from VerilatedModel - -const char* Vmain::hierName() const { return vlSymsp->name(); } -const char* Vmain::modelName() const { return "Vmain"; } -unsigned Vmain::threads() const { return 1; } -std::unique_ptr Vmain::traceConfig() const { - return std::unique_ptr{new VerilatedTraceConfig{false, false, false}}; -}; - -//============================================================ -// Trace configuration - -void Vmain___024root__trace_init_top(Vmain___024root* vlSelf, VerilatedVcd* tracep); - -VL_ATTR_COLD static void trace_init(void* voidSelf, VerilatedVcd* tracep, uint32_t code) { - // Callback from tracep->open() - Vmain___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast(voidSelf); - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - if (!vlSymsp->_vm_contextp__->calcUnusedSigs()) { - VL_FATAL_MT(__FILE__, __LINE__, __FILE__, - "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); - } - vlSymsp->__Vm_baseCode = code; - tracep->scopeEscape(' '); - tracep->pushNamePrefix(std::string{vlSymsp->name()} + ' '); - Vmain___024root__trace_init_top(vlSelf, tracep); - tracep->popNamePrefix(); - tracep->scopeEscape('.'); -} - -VL_ATTR_COLD void Vmain___024root__trace_register(Vmain___024root* vlSelf, VerilatedVcd* tracep); - -VL_ATTR_COLD void Vmain::trace(VerilatedVcdC* tfp, int levels, int options) { - if (tfp->isOpen()) { - vl_fatal(__FILE__, __LINE__, __FILE__,"'Vmain::trace()' shall not be called after 'VerilatedVcdC::open()'."); - } - if (false && levels && options) {} // Prevent unused - tfp->spTrace()->addModel(this); - tfp->spTrace()->addInitCb(&trace_init, &(vlSymsp->TOP)); - Vmain___024root__trace_register(&(vlSymsp->TOP), tfp->spTrace()); -} diff --git a/delete_later/rtl/obj_dir/Vmain.mk b/delete_later/rtl/obj_dir/Vmain.mk deleted file mode 100644 index 36dd8a3..0000000 --- a/delete_later/rtl/obj_dir/Vmain.mk +++ /dev/null @@ -1,55 +0,0 @@ -# Verilated -*- Makefile -*- -# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable -# -# Execute this makefile from the object directory: -# make -f Vmain.mk - -default: Vmain__ALL.a - -### Constants... -# Perl executable (from $PERL) -PERL = perl -# Path to Verilator kit (from $VERILATOR_ROOT) -VERILATOR_ROOT = /home/angelo/Documents/verilator -# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) -SYSTEMC_INCLUDE ?= -# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) -SYSTEMC_LIBDIR ?= - -### Switches... -# C++ code coverage 0/1 (from --prof-c) -VM_PROFC = 0 -# SystemC output mode? 0/1 (from --sc) -VM_SC = 0 -# Legacy or SystemC output mode? 0/1 (from --sc) -VM_SP_OR_SC = $(VM_SC) -# Deprecated -VM_PCLI = 1 -# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) -VM_SC_TARGET_ARCH = linux - -### Vars... -# Design prefix (from --prefix) -VM_PREFIX = Vmain -# Module prefix (from --prefix) -VM_MODPREFIX = Vmain -# User CFLAGS (from -CFLAGS on Verilator command line) -VM_USER_CFLAGS = \ - -# User LDLIBS (from -LDFLAGS on Verilator command line) -VM_USER_LDLIBS = \ - -# User .cpp files (from .cpp's on Verilator command line) -VM_USER_CLASSES = \ - -# User .cpp directories (from .cpp's on Verilator command line) -VM_USER_DIR = \ - - -### Default rules... -# Include list of all generated classes -include Vmain_classes.mk -# Include global rules -include $(VERILATOR_ROOT)/include/verilated.mk - -# Verilated -*- Makefile -*- diff --git a/delete_later/rtl/obj_dir/Vmain__ConstPool_0.cpp b/delete_later/rtl/obj_dir/Vmain__ConstPool_0.cpp deleted file mode 100644 index 7ce3ad8..0000000 --- a/delete_later/rtl/obj_dir/Vmain__ConstPool_0.cpp +++ /dev/null @@ -1,910 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Constant pool -// - -#include "verilated.h" - -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0 = {{ - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000 -}}; - -extern const VlWide<18>/*575:0*/ Vmain__ConstPool__CONST_hb679b2e5_0 = {{ - 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000 -}}; - -extern const VlWide<15>/*479:0*/ Vmain__ConstPool__CONST_hbd99daea_0 = {{ - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000 -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_h02e0efbb_0 = {{ - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, - 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, - 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_h13ae860a_0 = {{ - 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, - 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, - 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, - 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, - 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, - 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, - 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, - 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_h164a10d3_0 = {{ - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x01U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x00U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, - 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U, 0x02U -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_h179527bd_0 = {{ - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x01U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, - 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U, 0x03U -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_h3e5c4ef2_0 = {{ - 0x00U, 0xb0U, 0x00U, 0xd0U, 0x00U, 0x00U, 0x00U, 0xa0U, - 0x00U, 0x81U, 0x00U, 0x30U, 0x00U, 0x90U, 0x00U, 0x30U, - 0x00U, 0x00U, 0x00U, 0x13U, 0x00U, 0x91U, 0x00U, 0x45U, - 0x00U, 0x21U, 0x00U, 0x30U, 0x00U, 0x92U, 0x00U, 0x30U, - 0x00U, 0x00U, 0x00U, 0x13U, 0x00U, 0x93U, 0x00U, 0x47U, - 0x00U, 0x2cU, 0x00U, 0xb0U, 0x00U, 0xa0U, 0x00U, 0x81U, - 0x00U, 0x30U, 0x00U, 0x92U, 0x00U, 0x30U, 0x00U, 0x00U, - 0x00U, 0x13U, 0x00U, 0x93U, 0x00U, 0x47U, 0x00U, 0x2cU -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_h40cc9f5d_0 = {{ - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 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0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U, 0x01U -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_h9becc847_0 = {{ - 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x03U, 0x00U, 0x00U, 0x00U, 0x03U, 0x00U, 0x03U, - 0x00U, 0x00U, 0x00U, 0x02U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x03U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x01U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x02U, 0x00U, 0x00U, 0x00U, 0x02U, 0x00U, 0x02U -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_h9e411d43_0 = {{ - 0x00U, 0x01U, 0x00U, 0x02U, 0x00U, 0x03U, 0x00U, 0x04U, - 0x00U, 0x05U, 0x00U, 0x06U, 0x00U, 0x07U, 0x00U, 0x08U, - 0x00U, 0x09U, 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU, - 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU, - 0x00U, 0x01U, 0x00U, 0x02U, 0x00U, 0x03U, 0x00U, 0x04U, - 0x00U, 0x05U, 0x00U, 0x06U, 0x00U, 0x07U, 0x00U, 0x08U, - 0x00U, 0x09U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x00U, 0x01U, 0x00U, 0x02U, 0x00U, 0x03U, 0x00U, 0x04U, - 0x00U, 0x05U, 0x00U, 0x06U, 0x00U, 0x07U, 0x00U, 0x08U, - 0x00U, 0x09U, 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU, - 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU, - 0x00U, 0x01U, 0x00U, 0x02U, 0x00U, 0x03U, 0x00U, 0x04U, - 0x00U, 0x05U, 0x00U, 0x06U, 0x00U, 0x07U, 0x00U, 0x08U, - 0x00U, 0x09U, 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU, - 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU, 0x00U, 0x0fU -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_hd397e023_0 = {{ - 0x01U, 0x00U, 0x01U, 0x01U, 0x01U, 0x00U, 0x01U, 0x00U, - 0x01U, 0x01U, 0x01U, 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x00U, 0x01U, 0x01U, 0x01U, 0x00U, 0x01U, 0x00U, - 0x01U, 0x01U, 0x01U, 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x00U, 0x01U, 0x01U, 0x01U, 0x00U, 0x01U, 0x00U, - 0x01U, 0x01U, 0x01U, 0x00U, 0x01U, 0x01U, 0x01U, 0x01U, - 0x01U, 0x00U, 0x01U, 0x01U, 0x01U, 0x00U, 0x01U, 0x00U, - 0x01U, 0x01U, 0x01U, 0x00U, 0x01U, 0x01U, 0x01U, 0x01U -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_hdf55cab5_0 = {{ - 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U -}}; - -extern const VlUnpacked Vmain__ConstPool__TABLE_heed7669e_0 = {{ - 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, - 0x01U, 0x01U, 0x00U, 0x00U, 0x01U, 0x01U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x00U, 0x00U, 0x01U, 0x00U, 0x00U, 0x00U, - 0x01U, 0x01U, 0x00U, 0x00U, 0x01U, 0x01U, 0x00U, 0x00U, - 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U, 0x01U, 0x00U -}}; diff --git a/delete_later/rtl/obj_dir/Vmain__Dpi.cpp b/delete_later/rtl/obj_dir/Vmain__Dpi.cpp deleted file mode 100644 index de65ae5..0000000 --- a/delete_later/rtl/obj_dir/Vmain__Dpi.cpp +++ /dev/null @@ -1,16 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Implementation of DPI export functions. -// -// Verilator compiles this file in when DPI functions are used. -// If you have multiple Verilated designs with the same DPI exported -// function names, you will get multiple definition link errors from here. -// This is an unfortunate result of the DPI specification. -// To solve this, either -// 1. Call Vmain::{export_function} instead, -// and do not even bother to compile this file -// or 2. Compile all __Dpi.cpp files in the same compiler run, -// and #ifdefs already inserted here will sort everything out. - -#include "Vmain__Dpi.h" -#include "Vmain.h" - diff --git a/delete_later/rtl/obj_dir/Vmain__Dpi.h b/delete_later/rtl/obj_dir/Vmain__Dpi.h deleted file mode 100644 index c3f75b8..0000000 --- a/delete_later/rtl/obj_dir/Vmain__Dpi.h +++ /dev/null @@ -1,22 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Prototypes for DPI import and export functions. -// -// Verilator includes this file in all generated .cpp files that use DPI functions. -// Manually include this file where DPI .c import functions are declared to ensure -// the C functions match the expectations of the DPI imports. - -#ifndef VERILATED_VMAIN__DPI_H_ -#define VERILATED_VMAIN__DPI_H_ // guard - -#include "svdpi.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -#ifdef __cplusplus -} -#endif - -#endif // guard diff --git a/delete_later/rtl/obj_dir/Vmain__Syms.cpp b/delete_later/rtl/obj_dir/Vmain__Syms.cpp deleted file mode 100644 index d4becfb..0000000 --- a/delete_later/rtl/obj_dir/Vmain__Syms.cpp +++ /dev/null @@ -1,41 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table implementation internals - -#include "Vmain__Syms.h" -#include "Vmain.h" -#include "Vmain___024root.h" - -// FUNCTIONS -Vmain__Syms::~Vmain__Syms() -{ -} - -Vmain__Syms::Vmain__Syms(VerilatedContext* contextp, const char* namep, Vmain* modelp) - : VerilatedSyms{contextp} - // Setup internal state of the Syms class - , __Vm_modelp{modelp} - // Setup module instances - , TOP{this, namep} -{ - // Configure time unit / time precision - _vm_contextp__->timeunit(-12); - _vm_contextp__->timeprecision(-12); - // Setup each module's pointers to their submodules - // Setup each module's pointer back to symbol table (for public functions) - TOP.__Vconfigure(true); - // Setup scopes - __Vscope_main__swic__thecpu__core.configure(this, name(), "main.swic.thecpu.core", "core", 0, VerilatedScope::SCOPE_OTHER); - __Vscope_main__swic__thecpu__core__instruction_decoder.configure(this, name(), "main.swic.thecpu.core.instruction_decoder", "instruction_decoder", 0, VerilatedScope::SCOPE_OTHER); - // Setup export functions - for (int __Vfinal = 0; __Vfinal < 2; ++__Vfinal) { - __Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"alu_ce", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0); - __Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"alu_sim", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0); - __Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"alu_sim_immv", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,1 ,22,0); - __Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"dcd_pc", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,1 ,27,0); - __Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"op_sim", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0); - __Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"op_sim_immv", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,1 ,22,0); - __Vscope_main__swic__thecpu__core.varInsert(__Vfinal,"op_valid", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0); - __Vscope_main__swic__thecpu__core__instruction_decoder.varInsert(__Vfinal,"o_sim", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim), false, VLVT_UINT8,VLVD_NODIR|VLVF_PUB_RW,0); - __Vscope_main__swic__thecpu__core__instruction_decoder.varInsert(__Vfinal,"o_sim_immv", &(TOP.main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim_immv), false, VLVT_UINT32,VLVD_NODIR|VLVF_PUB_RW,1 ,22,0); - } -} diff --git a/delete_later/rtl/obj_dir/Vmain__Syms.h b/delete_later/rtl/obj_dir/Vmain__Syms.h deleted file mode 100644 index 45c34e7..0000000 --- a/delete_later/rtl/obj_dir/Vmain__Syms.h +++ /dev/null @@ -1,46 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Symbol table internal header -// -// Internal details; most calling programs do not need this header, -// unless using verilator public meta comments. - -#ifndef VERILATED_VMAIN__SYMS_H_ -#define VERILATED_VMAIN__SYMS_H_ // guard - -#include "verilated.h" - -// INCLUDE MODEL CLASS - -#include "Vmain.h" - -// INCLUDE MODULE CLASSES -#include "Vmain___024root.h" - -// DPI TYPES for DPI Export callbacks (Internal use) - -// SYMS CLASS (contains all model state) -class alignas(VL_CACHE_LINE_BYTES)Vmain__Syms final : public VerilatedSyms { - public: - // INTERNAL STATE - Vmain* const __Vm_modelp; - bool __Vm_activity = false; ///< Used by trace routines to determine change occurred - uint32_t __Vm_baseCode = 0; ///< Used by trace routines when tracing multiple models - VlDeleter __Vm_deleter; - bool __Vm_didInit = false; - - // MODULE INSTANCE STATE - Vmain___024root TOP; - - // SCOPE NAMES - VerilatedScope __Vscope_main__swic__thecpu__core; - VerilatedScope __Vscope_main__swic__thecpu__core__instruction_decoder; - - // CONSTRUCTORS - Vmain__Syms(VerilatedContext* contextp, const char* namep, Vmain* modelp); - ~Vmain__Syms(); - - // METHODS - const char* name() { return TOP.name(); } -}; - -#endif // guard diff --git a/delete_later/rtl/obj_dir/Vmain__Trace__0.cpp b/delete_later/rtl/obj_dir/Vmain__Trace__0.cpp deleted file mode 100644 index 0222331..0000000 --- a/delete_later/rtl/obj_dir/Vmain__Trace__0.cpp +++ /dev/null @@ -1,4850 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Tracing implementation internals -#include "verilated_vcd_c.h" -#include "Vmain__Syms.h" - - -void Vmain___024root__trace_chg_sub_0(Vmain___024root* vlSelf, VerilatedVcd::Buffer* bufp); - -void Vmain___024root__trace_chg_top_0(void* voidSelf, VerilatedVcd::Buffer* bufp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root__trace_chg_top_0\n"); ); - // Init - Vmain___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast(voidSelf); - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - if (VL_UNLIKELY(!vlSymsp->__Vm_activity)) return; - // Body - Vmain___024root__trace_chg_sub_0((&vlSymsp->TOP), bufp); -} - -extern const VlWide<15>/*479:0*/ Vmain__ConstPool__CONST_hbd99daea_0; -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0; -extern const VlWide<18>/*575:0*/ Vmain__ConstPool__CONST_hb679b2e5_0; - -void Vmain___024root__trace_chg_sub_0(Vmain___024root* vlSelf, VerilatedVcd::Buffer* bufp) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root__trace_chg_sub_0\n"); ); - // Init - uint32_t* const oldp VL_ATTR_UNUSED = bufp->oldp(vlSymsp->__Vm_baseCode + 1); - VlWide<16>/*511:0*/ __Vtemp_h053daff0__0; - VlWide<16>/*511:0*/ __Vtemp_h3711b190__0; - VlWide<16>/*511:0*/ __Vtemp_h58eb921b__0; - VlWide<16>/*511:0*/ __Vtemp_hc1d82fb0__0; - VlWide<16>/*511:0*/ __Vtemp_hc1851150__0; - VlWide<16>/*511:0*/ __Vtemp_hd1e4c677__0; - VlWide<16>/*511:0*/ __Vtemp_h6ddae8d1__0; - VlWide<16>/*511:0*/ __Vtemp_hc1d82fb0__1; - VlWide<16>/*511:0*/ __Vtemp_h6d0d1506__0; - VlWide<17>/*543:0*/ __Vtemp_h6b3f223d__0; - VlWide<16>/*511:0*/ __Vtemp_h01ff8f7b__0; - VlWide<16>/*511:0*/ __Vtemp_he3c3974d__0; - VlWide<16>/*511:0*/ __Vtemp_hcfafa750__0; - VlWide<3>/*95:0*/ __Vtemp_h708d16f1__0; - VlWide<64>/*2047:0*/ __Vtemp_h95b27ed2__0; - VlWide<8>/*255:0*/ __Vtemp_h7cab7483__0; - VlWide<16>/*511:0*/ __Vtemp_h53a5df10__0; - VlWide<19>/*607:0*/ __Vtemp_hb52cb2db__0; - VlWide<16>/*511:0*/ __Vtemp_hebded4b4__0; - VlWide<19>/*607:0*/ __Vtemp_h0a2cdfa5__0; - VlWide<19>/*607:0*/ __Vtemp_he57bd368__0; - VlWide<16>/*511:0*/ __Vtemp_h0964a254__0; - VlWide<19>/*607:0*/ __Vtemp_h925b4b87__0; - VlWide<16>/*511:0*/ __Vtemp_h5b5f8605__0; - VlWide<19>/*607:0*/ __Vtemp_hfe9179b2__0; - VlWide<12>/*383:0*/ __Vtemp_ha40692d2__0; - VlWide<48>/*1535:0*/ __Vtemp_h8a06d21b__0; - VlWide<16>/*511:0*/ __Vtemp_hc035b709__1; - VlWide<16>/*511:0*/ __Vtemp_hf82de6ac__0; - VlWide<16>/*511:0*/ __Vtemp_hf74e670c__0; - VlWide<16>/*511:0*/ __Vtemp_h21e563ec__0; - // Body - if (VL_UNLIKELY(vlSelf->__Vm_traceActivity[0U])) { - bufp->chgIData(oldp+0,(vlSelf->main__DOT__ddr3_controller_inst__DOT__nCK_to_cycles__Vstatic__result),32); - bufp->chgIData(oldp+1,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k),32); - bufp->chgCData(oldp+2,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv),7); - bufp->chgIData(oldp+3,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k),32); - bufp->chgCData(oldp+4,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__newv),7); - bufp->chgIData(oldp+5,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k),32); - bufp->chgIData(oldp+6,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__ik),32); - bufp->chgSData(oldp+7,(vlSelf->main__DOT__wb32_xbar__DOT__requested[0]),12); - bufp->chgBit(oldp+8,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[0])); - bufp->chgBit(oldp+9,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[1])); - bufp->chgBit(oldp+10,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[2])); - bufp->chgBit(oldp+11,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[3])); - bufp->chgBit(oldp+12,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[4])); - bufp->chgBit(oldp+13,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[5])); - bufp->chgBit(oldp+14,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[6])); - bufp->chgBit(oldp+15,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[7])); - bufp->chgBit(oldp+16,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[8])); - bufp->chgBit(oldp+17,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[9])); - bufp->chgBit(oldp+18,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[10])); - bufp->chgBit(oldp+19,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[11])); - bufp->chgBit(oldp+20,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[12])); - bufp->chgBit(oldp+21,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[13])); - bufp->chgBit(oldp+22,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[14])); - bufp->chgBit(oldp+23,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[15])); - bufp->chgIData(oldp+24,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM),32); - bufp->chgCData(oldp+25,(vlSelf->main__DOT__wbu_xbar__DOT__requested[0]),2); - bufp->chgBit(oldp+26,(vlSelf->main__DOT__wbu_xbar__DOT__sindex[0])); - bufp->chgBit(oldp+27,(vlSelf->main__DOT__wbu_xbar__DOT__sindex[1])); - bufp->chgBit(oldp+28,(vlSelf->main__DOT__wbu_xbar__DOT__sindex[2])); - bufp->chgBit(oldp+29,(vlSelf->main__DOT__wbu_xbar__DOT__sindex[3])); - bufp->chgIData(oldp+30,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM),32); - bufp->chgIData(oldp+31,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM),32); - bufp->chgIData(oldp+32,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__iM),32); - bufp->chgIData(oldp+33,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__iM),32); - bufp->chgIData(oldp+34,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__iM),32); - } - if (VL_UNLIKELY((vlSelf->__Vm_traceActivity[1U] - | vlSelf->__Vm_traceActivity[2U]))) { - bufp->chgIData(oldp+35,((((IData)(vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3) - << 0x1fU) | vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4)),32); - bufp->chgIData(oldp+36,((((IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted) - << 0x1fU) | vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4)),32); - bufp->chgIData(oldp+37,(vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4),31); - bufp->chgIData(oldp+38,((((IData)(vlSelf->main__DOT__i2ci__DOT__half_insn) - << 0x1cU) | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual) - << 0x18U) - | vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0))),32); - bufp->chgBit(oldp+39,(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)); - bufp->chgBit(oldp+40,(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset)); - bufp->chgIData(oldp+41,(vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4),31); - bufp->chgBit(oldp+42,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc)); - bufp->chgBit(oldp+43,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb)); - bufp->chgBit(oldp+44,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_we)); - bufp->chgCData(oldp+45,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr),7); - bufp->chgIData(oldp+46,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_data),32); - bufp->chgBit(oldp+47,(vlSelf->main__DOT__swic__DOT__cpu_op_stall)); - bufp->chgBit(oldp+48,(((IData)(vlSelf->main__DOT__swic__DOT__cpu_op_stall) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))); - bufp->chgBit(oldp+49,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready)); - bufp->chgBit(oldp+50,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce)); - bufp->chgBit(oldp+51,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance)); - bufp->chgBit(oldp+52,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall)); - bufp->chgBit(oldp+53,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)); - bufp->chgBit(oldp+54,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce)); - bufp->chgBit(oldp+55,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U))) | - (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U) & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)))))); - bufp->chgBit(oldp+56,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)) - & (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI)) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - == (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR)) - | (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - | ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg) - == - (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U)))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U) & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)))))); - bufp->chgBit(oldp+57,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)); - bufp->chgIData(oldp+58,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v),32); - bufp->chgIData(oldp+59,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v),32); - bufp->chgBit(oldp+60,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce)); - bufp->chgBit(oldp+61,(((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0)))); - bufp->chgBit(oldp+62,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce)); - bufp->chgBit(oldp+63,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled)); - bufp->chgBit(oldp+64,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce)); - bufp->chgBit(oldp+65,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional)); - bufp->chgBit(oldp+66,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset)); - bufp->chgCData(oldp+67,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc),3); - bufp->chgCData(oldp+68,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc),3); - bufp->chgCData(oldp+69,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc),3); - bufp->chgBit(oldp+70,(((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim) - & ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((0xfU - == - (0xfU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))) - & ((1U - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie))))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu))))))))); - bufp->chgBit(oldp+71,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op)); - bufp->chgBit(oldp+72,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset)); - bufp->chgBit(oldp+73,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)); - bufp->chgBit(oldp+74,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset)); - bufp->chgBit(oldp+75,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin)); - bufp->chgBit(oldp+76,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in)); - bufp->chgBit(oldp+77,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin)); - bufp->chgBit(oldp+78,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in)); - bufp->chgBit(oldp+79,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin)); - bufp->chgBit(oldp+80,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in)); - bufp->chgBit(oldp+81,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin)); - bufp->chgBit(oldp+82,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in)); - bufp->chgBit(oldp+83,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in)); - bufp->chgBit(oldp+84,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset)); - bufp->chgBit(oldp+85,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset)); - bufp->chgCData(oldp+86,(vlSelf->main__DOT__wbu_xbar__DOT__s_stall),4); - bufp->chgBit(oldp+87,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb)); - bufp->chgBit(oldp+88,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid)); - bufp->chgCData(oldp+89,((((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 2U) | ((- (IData)((IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid))) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)))),3); - bufp->chgCData(oldp+90,(((- (IData)((IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid))) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest))),2); - bufp->chgBit(oldp+91,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->chgBit(oldp+92,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->chgBit(oldp+93,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)); - bufp->chgBit(oldp+94,(vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+95,(vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+96,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb)); - bufp->chgBit(oldp+97,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid)); - bufp->chgCData(oldp+98,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 3U) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),4); - bufp->chgCData(oldp+99,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),3); - bufp->chgBit(oldp+100,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->chgBit(oldp+101,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->chgBit(oldp+102,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)); - bufp->chgBit(oldp+103,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb)); - bufp->chgBit(oldp+104,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid)); - bufp->chgCData(oldp+105,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 3U) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),4); - bufp->chgCData(oldp+106,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),3); - bufp->chgBit(oldp+107,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->chgBit(oldp+108,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->chgBit(oldp+109,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset)); - bufp->chgBit(oldp+110,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb)); - bufp->chgBit(oldp+111,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid)); - bufp->chgCData(oldp+112,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 3U) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),4); - bufp->chgCData(oldp+113,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),3); - bufp->chgBit(oldp+114,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->chgBit(oldp+115,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->chgBit(oldp+116,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset)); - bufp->chgBit(oldp+117,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb)); - bufp->chgBit(oldp+118,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid)); - bufp->chgCData(oldp+119,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 3U) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),4); - bufp->chgCData(oldp+120,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),3); - bufp->chgBit(oldp+121,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->chgBit(oldp+122,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->chgBit(oldp+123,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset)); - } - if (VL_UNLIKELY((vlSelf->__Vm_traceActivity[1U] - | vlSelf->__Vm_traceActivity[5U]))) { - bufp->chgBit(oldp+124,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request)); - bufp->chgBit(oldp+125,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request)); - bufp->chgBit(oldp+126,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request)); - bufp->chgBit(oldp+127,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request)); - bufp->chgBit(oldp+128,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request)); - bufp->chgBit(oldp+129,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request)); - bufp->chgBit(oldp+130,(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset)); - bufp->chgBit(oldp+131,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb)); - bufp->chgBit(oldp+132,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid)); - bufp->chgSData(oldp+133,((((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 0xcU) | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),13); - bufp->chgSData(oldp+134,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),12); - bufp->chgBit(oldp+135,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->chgBit(oldp+136,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->chgBit(oldp+137,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)); - bufp->chgBit(oldp+138,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+139,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+140,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+141,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+142,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+143,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+144,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+145,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+146,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+147,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+148,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+149,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+150,(vlSelf->main__DOT__wbu_xbar__DOT__m_stall)); - bufp->chgBit(oldp+151,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)); - bufp->chgBit(oldp+152,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall)); - bufp->chgBit(oldp+153,((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall))))); - bufp->chgBit(oldp+154,(vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+155,(vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant)); - bufp->chgBit(oldp+156,(vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant)); - } - if (VL_UNLIKELY(vlSelf->__Vm_traceActivity[2U])) { - bufp->chgBit(oldp+157,(vlSelf->main__DOT__emmcscope_int)); - bufp->chgBit(oldp+158,(vlSelf->main__DOT__sdioscope_int)); - bufp->chgBit(oldp+159,(vlSelf->main__DOT__emmc_int)); - bufp->chgBit(oldp+160,(vlSelf->main__DOT__sdcard_int)); - bufp->chgBit(oldp+161,((1U & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - >> 5U)))); - bufp->chgBit(oldp+162,((1U & (~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow))))); - bufp->chgBit(oldp+163,((1U & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - >> 5U)))); - bufp->chgBit(oldp+164,((1U & (~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow))))); - bufp->chgBit(oldp+165,(vlSelf->main__DOT__i2cscope_int)); - bufp->chgBit(oldp+166,(vlSelf->main__DOT__gpio_int)); - bufp->chgBit(oldp+167,(vlSelf->main__DOT__spio_int)); - bufp->chgBit(oldp+168,(vlSelf->main__DOT__r_sirefclk_en)); - bufp->chgIData(oldp+169,(vlSelf->main__DOT__r_sirefclk_data),30); - bufp->chgBit(oldp+170,(vlSelf->main__DOT__w_sirefclk_unused_stb)); - bufp->chgBit(oldp+171,(vlSelf->main__DOT__r_sirefclk_ack)); - bufp->chgBit(oldp+172,((1U & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid))))); - bufp->chgBit(oldp+173,(vlSelf->main__DOT__i2c_valid)); - bufp->chgBit(oldp+174,(vlSelf->main__DOT__i2c_ready)); - bufp->chgBit(oldp+175,(vlSelf->main__DOT__i2c_last)); - bufp->chgCData(oldp+176,(vlSelf->main__DOT__i2c_data),8); - bufp->chgCData(oldp+177,(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid),2); - bufp->chgIData(oldp+178,((((IData)(vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3) - << 0x1fU) | vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4)),32); - bufp->chgBit(oldp+179,(vlSelf->main__DOT__w_console_rx_stb)); - bufp->chgBit(oldp+180,((1U & (~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow))))); - bufp->chgBit(oldp+181,(vlSelf->main__DOT__w_console_busy)); - bufp->chgCData(oldp+182,(vlSelf->main__DOT__w_console_rx_data),7); - bufp->chgCData(oldp+183,(vlSelf->main__DOT__w_console_tx_data),7); - bufp->chgIData(oldp+184,(vlSelf->main__DOT__uart_debug),32); - bufp->chgBit(oldp+185,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)); - bufp->chgBit(oldp+186,(vlSelf->main__DOT__raw_cpu_dbg_ack)); - bufp->chgSData(oldp+187,((((IData)(vlSelf->main__DOT__gpio_int) - << 0xfU) | (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0xeU) - | ((0x2000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0xdU)) - | ((0x1000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0xcU)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0xbU) - | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 0xaU) - | (((IData)(vlSelf->main__DOT__emmcscope_int) - << 9U) - | (IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0))))))))),16); - bufp->chgBit(oldp+188,(vlSelf->main__DOT__zip_cpu_int)); - bufp->chgCData(oldp+189,(vlSelf->main__DOT__wbu_rx_data),8); - bufp->chgCData(oldp+190,(vlSelf->main__DOT__genbus__DOT__ps_data),8); - bufp->chgBit(oldp+191,(vlSelf->main__DOT__wbu_rx_stb)); - bufp->chgBit(oldp+192,(vlSelf->main__DOT__genbus__DOT__ps_full)); - bufp->chgBit(oldp+193,(vlSelf->main__DOT__txv__DOT__r_busy)); - bufp->chgBit(oldp+194,(vlSelf->main__DOT__genbus__DOT__r_wdt_reset)); - bufp->chgCData(oldp+195,(vlSelf->main__DOT__w_led),8); - bufp->chgSData(oldp+196,((((IData)(vlSelf->main__DOT__spio_int) - << 9U) | ((0x100U - & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - << 3U)) - | ((0x80U - & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - << 2U)) - | ((IData)(vlSelf->main__DOT__sdcard_int) - << 6U))))),15); - bufp->chgSData(oldp+197,((((IData)(vlSelf->main__DOT__gpio_int) - << 0xeU) | (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0xdU) - | ((0x1000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0xcU)) - | ((0x800U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0xbU)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0xaU) - | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 9U) - | ((IData)(vlSelf->main__DOT__emmcscope_int) - << 8U)))))))),15); - bufp->chgBit(oldp+198,(vlSelf->main__DOT__wbwide_i2cdma_cyc)); - bufp->chgBit(oldp+199,(vlSelf->main__DOT__wbwide_i2cdma_stb)); - bufp->chgIData(oldp+200,(vlSelf->main__DOT__wbwide_i2cdma_addr),22); - bufp->chgWData(oldp+201,(vlSelf->main__DOT__wbwide_i2cdma_data),512); - bufp->chgQData(oldp+217,(vlSelf->main__DOT__wbwide_i2cdma_sel),64); - bufp->chgBit(oldp+219,((1U & (IData)(vlSelf->__VdfgTmp_h503d14d1__0)))); - bufp->chgBit(oldp+220,((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))); - bufp->chgBit(oldp+221,((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))); - __Vtemp_h053daff0__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0U]; - __Vtemp_h053daff0__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[1U]; - __Vtemp_h053daff0__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[2U]; - __Vtemp_h053daff0__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[3U]; - __Vtemp_h053daff0__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[4U]; - __Vtemp_h053daff0__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[5U]; - __Vtemp_h053daff0__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[6U]; - __Vtemp_h053daff0__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[7U]; - __Vtemp_h053daff0__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[8U]; - __Vtemp_h053daff0__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[9U]; - __Vtemp_h053daff0__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xaU]; - __Vtemp_h053daff0__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xbU]; - __Vtemp_h053daff0__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xcU]; - __Vtemp_h053daff0__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xdU]; - __Vtemp_h053daff0__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xeU]; - __Vtemp_h053daff0__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xfU]; - bufp->chgWData(oldp+222,(__Vtemp_h053daff0__0),512); - bufp->chgBit(oldp+238,(vlSelf->main__DOT__wbwide_i2cm_cyc)); - bufp->chgBit(oldp+239,(vlSelf->main__DOT__wbwide_i2cm_stb)); - bufp->chgIData(oldp+240,(vlSelf->main__DOT__wbwide_i2cm_addr),22); - bufp->chgBit(oldp+241,((1U & ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 1U)))); - bufp->chgBit(oldp+242,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U)))); - bufp->chgBit(oldp+243,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 1U)))); - __Vtemp_h3711b190__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x10U]; - __Vtemp_h3711b190__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x11U]; - __Vtemp_h3711b190__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x12U]; - __Vtemp_h3711b190__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x13U]; - __Vtemp_h3711b190__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x14U]; - __Vtemp_h3711b190__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x15U]; - __Vtemp_h3711b190__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x16U]; - __Vtemp_h3711b190__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x17U]; - __Vtemp_h3711b190__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x18U]; - __Vtemp_h3711b190__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x19U]; - __Vtemp_h3711b190__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1aU]; - __Vtemp_h3711b190__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1bU]; - __Vtemp_h3711b190__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1cU]; - __Vtemp_h3711b190__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1dU]; - __Vtemp_h3711b190__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1eU]; - __Vtemp_h3711b190__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1fU]; - bufp->chgWData(oldp+244,(__Vtemp_h3711b190__0),512); - bufp->chgBit(oldp+260,(vlSelf->main__DOT__wbwide_zip_cyc)); - bufp->chgBit(oldp+261,(vlSelf->main__DOT__wbwide_zip_stb)); - bufp->chgBit(oldp+262,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__cpu_we) - : (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)))))); - bufp->chgIData(oldp+263,(vlSelf->main__DOT__wbwide_zip_addr),22); - if (vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) { - __Vtemp_h58eb921b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - __Vtemp_h58eb921b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U]; - __Vtemp_h58eb921b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U]; - __Vtemp_h58eb921b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U]; - __Vtemp_h58eb921b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U]; - __Vtemp_h58eb921b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U]; - __Vtemp_h58eb921b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U]; - __Vtemp_h58eb921b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U]; - __Vtemp_h58eb921b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U]; - __Vtemp_h58eb921b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U]; - __Vtemp_h58eb921b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU]; - __Vtemp_h58eb921b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU]; - __Vtemp_h58eb921b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU]; - __Vtemp_h58eb921b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU]; - __Vtemp_h58eb921b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU]; - __Vtemp_h58eb921b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU]; - } else { - __Vtemp_h58eb921b__0[0U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0U]; - __Vtemp_h58eb921b__0[1U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[1U]; - __Vtemp_h58eb921b__0[2U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[2U]; - __Vtemp_h58eb921b__0[3U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[3U]; - __Vtemp_h58eb921b__0[4U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[4U]; - __Vtemp_h58eb921b__0[5U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[5U]; - __Vtemp_h58eb921b__0[6U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[6U]; - __Vtemp_h58eb921b__0[7U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[7U]; - __Vtemp_h58eb921b__0[8U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[8U]; - __Vtemp_h58eb921b__0[9U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[9U]; - __Vtemp_h58eb921b__0[0xaU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xaU]; - __Vtemp_h58eb921b__0[0xbU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xbU]; - __Vtemp_h58eb921b__0[0xcU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xcU]; - __Vtemp_h58eb921b__0[0xdU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xdU]; - __Vtemp_h58eb921b__0[0xeU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xeU]; - __Vtemp_h58eb921b__0[0xfU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xfU]; - } - bufp->chgWData(oldp+264,(__Vtemp_h58eb921b__0),512); - bufp->chgQData(oldp+280,(((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel))),64); - bufp->chgBit(oldp+282,((1U & ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 2U)))); - bufp->chgBit(oldp+283,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U)))); - bufp->chgBit(oldp+284,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 2U)))); - __Vtemp_hc1d82fb0__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U]; - __Vtemp_hc1d82fb0__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U]; - __Vtemp_hc1d82fb0__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U]; - __Vtemp_hc1d82fb0__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U]; - __Vtemp_hc1d82fb0__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U]; - __Vtemp_hc1d82fb0__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U]; - __Vtemp_hc1d82fb0__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U]; - __Vtemp_hc1d82fb0__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U]; - __Vtemp_hc1d82fb0__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U]; - __Vtemp_hc1d82fb0__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U]; - __Vtemp_hc1d82fb0__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU]; - __Vtemp_hc1d82fb0__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU]; - __Vtemp_hc1d82fb0__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU]; - __Vtemp_hc1d82fb0__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU]; - __Vtemp_hc1d82fb0__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU]; - __Vtemp_hc1d82fb0__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU]; - bufp->chgWData(oldp+285,(__Vtemp_hc1d82fb0__0),512); - bufp->chgBit(oldp+301,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)); - bufp->chgBit(oldp+302,(vlSelf->main__DOT__wbwide_wbu_arbiter_stb)); - bufp->chgBit(oldp+303,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we)); - bufp->chgIData(oldp+304,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr),22); - bufp->chgWData(oldp+305,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data),512); - bufp->chgQData(oldp+321,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel),64); - bufp->chgBit(oldp+323,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)); - bufp->chgBit(oldp+324,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U)))); - bufp->chgBit(oldp+325,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 3U)))); - __Vtemp_hc1851150__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x30U]; - __Vtemp_hc1851150__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x31U]; - __Vtemp_hc1851150__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x32U]; - __Vtemp_hc1851150__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x33U]; - __Vtemp_hc1851150__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x34U]; - __Vtemp_hc1851150__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x35U]; - __Vtemp_hc1851150__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x36U]; - __Vtemp_hc1851150__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x37U]; - __Vtemp_hc1851150__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x38U]; - __Vtemp_hc1851150__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x39U]; - __Vtemp_hc1851150__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3aU]; - __Vtemp_hc1851150__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3bU]; - __Vtemp_hc1851150__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3cU]; - __Vtemp_hc1851150__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3dU]; - __Vtemp_hc1851150__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3eU]; - __Vtemp_hc1851150__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3fU]; - bufp->chgWData(oldp+326,(__Vtemp_hc1851150__0),512); - bufp->chgBit(oldp+342,(vlSelf->main__DOT__wbwide_wbdown_stall)); - bufp->chgBit(oldp+343,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack)); - bufp->chgWData(oldp+344,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data),512); - bufp->chgBit(oldp+360,(vlSelf->main__DOT__wbwide_bkram_ack)); - bufp->chgWData(oldp+361,(vlSelf->main__DOT__wbwide_bkram_idata),512); - bufp->chgBit(oldp+377,(vlSelf->main__DOT__wb32_wbdown_stb)); - bufp->chgBit(oldp+378,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_we)); - bufp->chgCData(oldp+379,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr),8); - bufp->chgIData(oldp+380,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xfU]),32); - bufp->chgCData(oldp+381,((0xfU & (IData)((vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel - >> 0x3cU)))),4); - bufp->chgBit(oldp+382,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)); - bufp->chgBit(oldp+383,(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - bufp->chgIData(oldp+384,(vlSelf->main__DOT__wb32_wbdown_idata),32); - bufp->chgIData(oldp+385,((((~ (IData)(vlSelf->main__DOT__r_sirefclk_en)) - << 0x1fU) | vlSelf->main__DOT__r_sirefclk_data)),32); - bufp->chgBit(oldp+386,(vlSelf->main__DOT__wb32_spio_ack)); - bufp->chgIData(oldp+387,((((IData)(vlSelf->main__DOT__spioi__DOT__led_demo) - << 0x18U) | (((IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn) - << 0x10U) - | (((IData)(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw) - << 8U) - | (IData)(vlSelf->main__DOT__spioi__DOT__r_led))))),32); - bufp->chgBit(oldp+388,(vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack)); - bufp->chgIData(oldp+389,(vlSelf->main__DOT__emmcscopei__DOT__o_bus_data),32); - bufp->chgBit(oldp+390,(vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack)); - bufp->chgIData(oldp+391,(vlSelf->main__DOT__i2cscopei__DOT__o_bus_data),32); - bufp->chgBit(oldp+392,(vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack)); - bufp->chgIData(oldp+393,(vlSelf->main__DOT__sdioscopei__DOT__o_bus_data),32); - bufp->chgBit(oldp+394,(vlSelf->main__DOT__wb32_i2cs_ack)); - bufp->chgIData(oldp+395,(vlSelf->main__DOT__i2ci__DOT__bus_read_data),32); - bufp->chgBit(oldp+396,(vlSelf->main__DOT__wb32_i2cdma_ack)); - bufp->chgIData(oldp+397,(vlSelf->main__DOT__wb32_i2cdma_idata),32); - bufp->chgBit(oldp+398,(vlSelf->main__DOT__wb32_uart_ack)); - bufp->chgIData(oldp+399,(vlSelf->main__DOT__wb32_uart_idata),32); - bufp->chgBit(oldp+400,(vlSelf->main__DOT__wb32_emmc_ack)); - bufp->chgIData(oldp+401,(vlSelf->main__DOT__wb32_emmc_idata),32); - bufp->chgBit(oldp+402,(vlSelf->main__DOT__wb32_fan_ack)); - bufp->chgIData(oldp+403,(vlSelf->main__DOT__wb32_fan_idata),32); - bufp->chgBit(oldp+404,(vlSelf->main__DOT__wb32_sdcard_ack)); - bufp->chgIData(oldp+405,(vlSelf->main__DOT__wb32_sdcard_idata),32); - bufp->chgBit(oldp+406,(vlSelf->main__DOT__r_wb32_sio_ack)); - bufp->chgIData(oldp+407,(vlSelf->main__DOT__r_wb32_sio_data),32); - bufp->chgBit(oldp+408,(vlSelf->main__DOT__r_cfg_ack)); - bufp->chgBit(oldp+409,(vlSelf->main__DOT__wbu_cyc)); - bufp->chgBit(oldp+410,(vlSelf->main__DOT__wbu_stb)); - bufp->chgBit(oldp+411,(vlSelf->main__DOT__wbu_we)); - bufp->chgIData(oldp+412,((0x7ffffffU & vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr)),27); - bufp->chgIData(oldp+413,(vlSelf->main__DOT__wbu_data),32); - bufp->chgBit(oldp+414,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)); - bufp->chgBit(oldp+415,(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - bufp->chgBit(oldp+416,(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - bufp->chgIData(oldp+417,(vlSelf->main__DOT__wbu_idata),32); - bufp->chgBit(oldp+418,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)))); - bufp->chgBit(oldp+419,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb)))); - bufp->chgBit(oldp+420,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe)))); - bufp->chgIData(oldp+421,((0x7ffffffU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr))),27); - bufp->chgIData(oldp+422,((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata)),32); - bufp->chgCData(oldp+423,((0xfU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel))),4); - bufp->chgBit(oldp+424,(vlSelf->main__DOT__wbu_wbu_arbiter_stall)); - bufp->chgBit(oldp+425,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack)); - bufp->chgBit(oldp+426,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err)); - bufp->chgIData(oldp+427,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xfU]),32); - bufp->chgBit(oldp+428,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - >> 1U)))); - bufp->chgBit(oldp+429,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - >> 1U)))); - bufp->chgBit(oldp+430,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe) - >> 1U)))); - bufp->chgIData(oldp+431,((0x7ffffffU & (IData)( - (vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - >> 0x1bU)))),27); - bufp->chgIData(oldp+432,((IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - >> 0x20U))),32); - bufp->chgCData(oldp+433,((0xfU & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel) - >> 4U))),4); - bufp->chgIData(oldp+434,(vlSelf->main__DOT__wbu_zip_idata),32); - bufp->chgIData(oldp+435,((0x3fffffffU & vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr)),30); - bufp->chgBit(oldp+436,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_wstb)); - bufp->chgBit(oldp+437,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_stb)); - bufp->chgWData(oldp+438,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data),512); - bufp->chgSData(oldp+454,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr),14); - bufp->chgQData(oldp+455,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel),64); - bufp->chgIData(oldp+457,(vlSelf->main__DOT__bkrami__DOT__WRITE_TO_MEMORY__DOT__ik),32); - bufp->chgIData(oldp+458,(vlSelf->main__DOT__r_sirefclk_data),32); - bufp->chgIData(oldp+459,(vlSelf->main__DOT__clock_generator__DOT__counter[0]),32); - bufp->chgIData(oldp+460,(vlSelf->main__DOT__clock_generator__DOT__counter[1]),32); - bufp->chgIData(oldp+461,(vlSelf->main__DOT__clock_generator__DOT__counter[2]),32); - bufp->chgIData(oldp+462,(vlSelf->main__DOT__clock_generator__DOT__counter[3]),32); - bufp->chgIData(oldp+463,(vlSelf->main__DOT__clock_generator__DOT__counter[4]),32); - bufp->chgIData(oldp+464,(vlSelf->main__DOT__clock_generator__DOT__counter[5]),32); - bufp->chgIData(oldp+465,(vlSelf->main__DOT__clock_generator__DOT__counter[6]),32); - bufp->chgIData(oldp+466,(vlSelf->main__DOT__clock_generator__DOT__counter[7]),32); - bufp->chgIData(oldp+467,(vlSelf->main__DOT__clock_generator__DOT__r_delay),32); - bufp->chgIData(oldp+468,(vlSelf->main__DOT__clock_generator__DOT__times_three),32); - bufp->chgIData(oldp+469,(vlSelf->main__DOT__clock_generator__DOT__times_five),32); - bufp->chgIData(oldp+470,(vlSelf->main__DOT__clock_generator__DOT__times_seven),32); - bufp->chgBit(oldp+471,(vlSelf->main__DOT__console__DOT__rx_uart_reset)); - bufp->chgBit(oldp+472,(((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__w_console_rx_stb)))); - bufp->chgCData(oldp+473,(vlSelf->main__DOT__console__DOT__rxf_wb_data),7); - bufp->chgSData(oldp+474,(vlSelf->main__DOT__console__DOT__rxf_status),16); - bufp->chgBit(oldp+475,(vlSelf->main__DOT__console__DOT__rxf_wb_read)); - bufp->chgIData(oldp+476,(((((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__w_console_rx_stb)) - << 0xcU) | (((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow) - << 8U) - | (IData)(vlSelf->main__DOT__console__DOT__rxf_wb_data)))),32); - bufp->chgBit(oldp+477,(((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__console__DOT__txf_wb_write)))); - bufp->chgSData(oldp+478,(vlSelf->main__DOT__console__DOT__txf_status),16); - bufp->chgBit(oldp+479,(vlSelf->main__DOT__console__DOT__txf_wb_write)); - bufp->chgBit(oldp+480,(vlSelf->main__DOT__console__DOT__tx_uart_reset)); - bufp->chgCData(oldp+481,(vlSelf->main__DOT__console__DOT__txf_wb_data),7); - bufp->chgIData(oldp+482,((((IData)(vlSelf->__VdfgTmp_ha46ae6a3__0) - << 0xdU) | ((((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__console__DOT__txf_wb_write)) - << 0xcU) - | ((0x400U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)) - << 0xaU)) - | (((IData)(vlSelf->main__DOT__console__DOT____VdfgTmp_h60af6732__0) - << 8U) - | ((IData)(vlSelf->main__DOT__console__DOT____VdfgTmp_h60af6732__0) - ? (IData)(vlSelf->main__DOT__console__DOT__txf_wb_data) - : 0U)))))),32); - bufp->chgIData(oldp+483,((((IData)(vlSelf->main__DOT__console__DOT__txf_status) - << 0x10U) | (IData)(vlSelf->main__DOT__console__DOT__rxf_status))),32); - bufp->chgCData(oldp+484,(vlSelf->main__DOT__console__DOT__r_wb_addr),2); - bufp->chgBit(oldp+485,(vlSelf->main__DOT__console__DOT__r_wb_ack)); - bufp->chgCData(oldp+486,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_data),7); - bufp->chgCData(oldp+487,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__last_write),7); - bufp->chgCData(oldp+488,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr),6); - bufp->chgCData(oldp+489,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr),6); - bufp->chgCData(oldp+490,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next),6); - bufp->chgBit(oldp+491,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow)); - bufp->chgBit(oldp+492,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)); - bufp->chgBit(oldp+493,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__osrc)); - bufp->chgCData(oldp+494,((0x3fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr)))),6); - bufp->chgCData(oldp+495,((0x3fU & ((IData)(2U) - + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr)))),6); - bufp->chgBit(oldp+496,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write)); - bufp->chgBit(oldp+497,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read)); - bufp->chgCData(oldp+498,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill),6); - bufp->chgSData(oldp+499,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill),10); - bufp->chgBit(oldp+500,(vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6)); - bufp->chgCData(oldp+501,(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_data),7); - bufp->chgCData(oldp+502,(vlSelf->main__DOT__console__DOT__txfifo__DOT__last_write),7); - bufp->chgCData(oldp+503,(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr),6); - bufp->chgCData(oldp+504,(vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr),6); - bufp->chgCData(oldp+505,(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next),6); - bufp->chgBit(oldp+506,(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)); - bufp->chgBit(oldp+507,(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)); - bufp->chgBit(oldp+508,(vlSelf->main__DOT__console__DOT__txfifo__DOT__osrc)); - bufp->chgCData(oldp+509,((0x3fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr)))),6); - bufp->chgCData(oldp+510,((0x3fU & ((IData)(2U) - + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr)))),6); - bufp->chgBit(oldp+511,(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write)); - bufp->chgBit(oldp+512,(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read)); - bufp->chgCData(oldp+513,(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill),6); - bufp->chgSData(oldp+514,(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill),10); - bufp->chgBit(oldp+515,(vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3)); - bufp->chgBit(oldp+516,(vlSelf->main__DOT__emmcscopei__DOT__read_address)); - bufp->chgSData(oldp+517,(vlSelf->main__DOT__emmcscopei__DOT__raddr),12); - bufp->chgSData(oldp+518,(vlSelf->main__DOT__emmcscopei__DOT__waddr),12); - bufp->chgBit(oldp+519,((1U & (~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U))))); - bufp->chgBit(oldp+520,((1U & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 1U)))); - bufp->chgBit(oldp+521,((1U & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config)))); - bufp->chgCData(oldp+522,(vlSelf->main__DOT__emmcscopei__DOT__br_config),3); - bufp->chgIData(oldp+523,(vlSelf->main__DOT__emmcscopei__DOT__br_holdoff),20); - bufp->chgIData(oldp+524,(vlSelf->main__DOT__emmcscopei__DOT__holdoff_counter),20); - bufp->chgBit(oldp+525,(vlSelf->main__DOT__emmcscopei__DOT__dr_triggered)); - bufp->chgBit(oldp+526,(vlSelf->main__DOT__emmcscopei__DOT__dr_primed)); - bufp->chgBit(oldp+527,(vlSelf->main__DOT__emmcscopei__DOT__dw_trigger)); - bufp->chgBit(oldp+528,(vlSelf->main__DOT__emmcscopei__DOT__dr_stopped)); - bufp->chgCData(oldp+529,(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe),5); - bufp->chgBit(oldp+530,((1U & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - >> 4U)))); - bufp->chgIData(oldp+531,(vlSelf->main__DOT__emmcscopei__DOT__ck_addr),31); - bufp->chgIData(oldp+532,(vlSelf->main__DOT__emmcscopei__DOT__qd_data),31); - bufp->chgBit(oldp+533,(vlSelf->main__DOT__emmcscopei__DOT__dr_force_write)); - bufp->chgBit(oldp+534,(vlSelf->main__DOT__emmcscopei__DOT__dr_run_timeout)); - bufp->chgBit(oldp+535,(vlSelf->main__DOT__emmcscopei__DOT__new_data)); - bufp->chgBit(oldp+536,(vlSelf->main__DOT__emmcscopei__DOT__dr_force_inhibit)); - bufp->chgBit(oldp+537,(vlSelf->main__DOT__emmcscopei__DOT__imm_adr)); - bufp->chgBit(oldp+538,(vlSelf->main__DOT__emmcscopei__DOT__lst_adr)); - bufp->chgIData(oldp+539,(vlSelf->main__DOT__emmcscopei__DOT__lst_val),31); - bufp->chgIData(oldp+540,(vlSelf->main__DOT__emmcscopei__DOT__imm_val),31); - bufp->chgBit(oldp+541,(vlSelf->main__DOT__emmcscopei__DOT__record_ce)); - bufp->chgIData(oldp+542,(vlSelf->main__DOT__emmcscopei__DOT__r_data),32); - bufp->chgBit(oldp+543,(vlSelf->main__DOT__emmcscopei__DOT__br_pre_wb_ack)); - bufp->chgSData(oldp+544,(vlSelf->main__DOT__emmcscopei__DOT__this_addr),12); - bufp->chgIData(oldp+545,(vlSelf->main__DOT__emmcscopei__DOT__nxt_mem),32); - bufp->chgBit(oldp+546,(vlSelf->main__DOT__emmcscopei__DOT__br_level_interrupt)); - bufp->chgBit(oldp+547,(vlSelf->main__DOT__genbus__DOT__soft_reset)); - bufp->chgBit(oldp+548,(vlSelf->main__DOT__genbus__DOT__rx_valid)); - bufp->chgCData(oldp+549,((0x7fU & (IData)(vlSelf->main__DOT__wbu_rx_data))),8); - bufp->chgBit(oldp+550,(vlSelf->main__DOT__genbus__DOT__in_stb)); - bufp->chgBit(oldp+551,(((IData)(vlSelf->main__DOT__genbus__DOT__rx_valid) - | ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT__in_stb)) - | (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))) - | (0U < (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len)))))); - bufp->chgQData(oldp+552,(vlSelf->main__DOT__genbus__DOT__in_word),36); - bufp->chgBit(oldp+554,(vlSelf->main__DOT__genbus__DOT__wbu_tx_stb)); - bufp->chgCData(oldp+555,(vlSelf->main__DOT__genbus__DOT__wbu_tx_data),8); - bufp->chgBit(oldp+556,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)); - bufp->chgQData(oldp+557,(vlSelf->main__DOT__genbus__DOT__ififo_codword),36); - bufp->chgBit(oldp+559,(vlSelf->main__DOT__genbus__DOT__exec_stb)); - bufp->chgQData(oldp+560,(vlSelf->main__DOT__genbus__DOT__exec_word),36); - bufp->chgBit(oldp+562,(vlSelf->main__DOT__genbus__DOT__ofifo_rd)); - bufp->chgQData(oldp+563,(vlSelf->main__DOT__genbus__DOT__ofifo_codword),36); - bufp->chgBit(oldp+565,((((IData)(vlSelf->main__DOT__genbus__DOT__exec_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd)) - & (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow))) - | ((~ (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)) - & (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd))))); - bufp->chgBit(oldp+566,(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)); - bufp->chgBit(oldp+567,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy)); - bufp->chgIData(oldp+568,(vlSelf->main__DOT__genbus__DOT__r_wdt_timer),19); - bufp->chgBit(oldp+569,(((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy) - & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb)))); - bufp->chgBit(oldp+570,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb)); - bufp->chgBit(oldp+571,(((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__r_active)))); - bufp->chgSData(oldp+572,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr),11); - bufp->chgSData(oldp+573,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr),11); - bufp->chgSData(oldp+574,((0x7ffU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr)))),11); - bufp->chgSData(oldp+575,((0x7ffU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr)))),11); - bufp->chgBit(oldp+576,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow)); - bufp->chgBit(oldp+577,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow)); - bufp->chgBit(oldp+578,((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow))))); - bufp->chgBit(oldp+579,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write)); - bufp->chgBit(oldp+580,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read)); - bufp->chgBit(oldp+581,((((IData)(vlSelf->main__DOT__genbus__DOT__in_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd)) - & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow))) - | ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)) - & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd))))); - bufp->chgBit(oldp+582,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd)); - bufp->chgCData(oldp+583,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr),7); - bufp->chgCData(oldp+584,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr),7); - bufp->chgCData(oldp+585,((0x7fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr)))),7); - bufp->chgCData(oldp+586,((0x7fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr)))),7); - bufp->chgBit(oldp+587,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow)); - bufp->chgBit(oldp+588,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow)); - bufp->chgBit(oldp+589,((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow))))); - bufp->chgBit(oldp+590,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write)); - bufp->chgBit(oldp+591,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read)); - bufp->chgBit(oldp+592,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb)); - bufp->chgBit(oldp+593,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid)); - bufp->chgCData(oldp+594,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits),6); - bufp->chgBit(oldp+595,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb)); - bufp->chgBit(oldp+596,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy)); - bufp->chgBit(oldp+597,(((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - | (0U < (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len))))); - bufp->chgQData(oldp+598,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word),36); - bufp->chgBit(oldp+600,((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)))); - bufp->chgBit(oldp+601,(((IData)(vlSelf->main__DOT__genbus__DOT__in_stb) - | (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))))); - bufp->chgCData(oldp+602,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr),8); - bufp->chgQData(oldp+603,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word),36); - bufp->chgCData(oldp+605,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cmd_addr),8); - bufp->chgIData(oldp+606,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr),25); - bufp->chgIData(oldp+607,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr),32); - bufp->chgSData(oldp+608,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__rd_len),10); - bufp->chgIData(oldp+609,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cword),32); - bufp->chgCData(oldp+610,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb),3); - bufp->chgBit(oldp+611,((3U == (7U & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x21U)))))); - bufp->chgCData(oldp+612,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len),3); - bufp->chgCData(oldp+613,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len),3); - bufp->chgCData(oldp+614,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw),2); - bufp->chgBit(oldp+615,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb)); - bufp->chgQData(oldp+616,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg),36); - bufp->chgIData(oldp+618,((((IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x1fU)) - << 0x1eU) | (0x3fffffffU - & (IData)(vlSelf->main__DOT__genbus__DOT__ififo_codword)))),32); - bufp->chgCData(oldp+619,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state),2); - bufp->chgSData(oldp+620,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed),10); - bufp->chgSData(oldp+621,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len),10); - bufp->chgBit(oldp+622,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_inc)); - bufp->chgBit(oldp+623,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_new_addr)); - bufp->chgBit(oldp+624,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_read_request)); - bufp->chgBit(oldp+625,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_ack)); - bufp->chgBit(oldp+626,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__zero_acks)); - bufp->chgIData(oldp+627,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr),32); - bufp->chgBit(oldp+628,(vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy)); - bufp->chgBit(oldp+629,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)); - bufp->chgBit(oldp+630,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)); - bufp->chgBit(oldp+631,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb)); - bufp->chgBit(oldp+632,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy)); - bufp->chgBit(oldp+633,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy)); - bufp->chgBit(oldp+634,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy)); - bufp->chgBit(oldp+635,(((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb))))); - bufp->chgBit(oldp+636,(((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))); - bufp->chgBit(oldp+637,(((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl)))))); - bufp->chgQData(oldp+638,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword),36); - bufp->chgQData(oldp+640,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword),36); - bufp->chgCData(oldp+642,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits),7); - bufp->chgCData(oldp+643,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_bits),7); - bufp->chgBit(oldp+644,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__r_active)); - bufp->chgBit(oldp+645,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid)); - bufp->chgQData(oldp+646,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__a_addrword),36); - bufp->chgIData(oldp+648,((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword)),32); - bufp->chgCData(oldp+649,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck),4); - bufp->chgBit(oldp+650,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)); - bufp->chgBit(oldp+651,(((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)))); - bufp->chgQData(oldp+652,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word),36); - bufp->chgSData(oldp+654,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr),10); - bufp->chgBit(oldp+655,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled)); - bufp->chgSData(oldp+656,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr),10); - bufp->chgBit(oldp+657,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch)); - bufp->chgBit(oldp+658,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch)); - bufp->chgBit(oldp+659,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__vaddr)); - bufp->chgIData(oldp+660,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__cword),32); - bufp->chgSData(oldp+661,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__maddr),10); - bufp->chgBit(oldp+662,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched)); - bufp->chgBit(oldp+663,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__zmatch)); - bufp->chgBit(oldp+664,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__hmatch)); - bufp->chgSData(oldp+665,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld),10); - bufp->chgCData(oldp+666,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_hlfd),3); - bufp->chgSData(oldp+667,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr),10); - bufp->chgBit(oldp+668,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table)); - bufp->chgBit(oldp+669,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table)); - bufp->chgBit(oldp+670,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match)); - bufp->chgBit(oldp+671,((1U & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld) - >> 9U)))); - bufp->chgBit(oldp+672,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy)); - bufp->chgBit(oldp+673,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request)); - bufp->chgBit(oldp+674,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent)); - bufp->chgBit(oldp+675,(((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state)) - & (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter - >> 0x15U)))); - bufp->chgBit(oldp+676,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state)); - bufp->chgIData(oldp+677,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter),22); - bufp->chgCData(oldp+678,(((0U == (7U & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x21U)))) - ? 1U : ((2U == (0xfU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x20U)))) - ? 6U : - (7U & ((3U - == - (0xfU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x20U)))) - ? - ((IData)(2U) - + - (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x1eU)))) - : - ((1U - == - (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x22U)))) - ? 2U - : - ((2U - == - (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x22U)))) - ? 1U - : 6U))))))),3); - bufp->chgCData(oldp+679,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len),3); - bufp->chgIData(oldp+680,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word),30); - bufp->chgBit(oldp+681,(((IData)(vlSelf->main__DOT__wbu_cyc) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy))))); - bufp->chgBit(oldp+682,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl)); - bufp->chgBit(oldp+683,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl)); - bufp->chgBit(oldp+684,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__full_line)); - bufp->chgBit(oldp+685,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy)); - bufp->chgCData(oldp+686,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen),7); - bufp->chgSData(oldp+687,(vlSelf->main__DOT__gpioi__DOT__r_gpio),16); - bufp->chgSData(oldp+688,(vlSelf->main__DOT__gpioi__DOT__x_gpio),16); - bufp->chgSData(oldp+689,(vlSelf->main__DOT__gpioi__DOT__q_gpio),16); - bufp->chgBit(oldp+690,(vlSelf->main__DOT__i2ci__DOT__r_halted)); - bufp->chgBit(oldp+691,(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc)); - bufp->chgIData(oldp+692,(vlSelf->main__DOT__i2ci__DOT__pf_jump_addr),28); - bufp->chgBit(oldp+693,(vlSelf->main__DOT__i2ci__DOT__pf_valid)); - bufp->chgBit(oldp+694,(vlSelf->main__DOT__i2ci__DOT__pf_ready)); - bufp->chgCData(oldp+695,(vlSelf->main__DOT__i2ci__DOT__pf_insn),8); - bufp->chgIData(oldp+696,(vlSelf->main__DOT__i2ci__DOT__pf_insn_addr),28); - bufp->chgBit(oldp+697,(vlSelf->main__DOT__i2ci__DOT__pf_illegal)); - bufp->chgBit(oldp+698,(vlSelf->main__DOT__i2ci__DOT__half_valid)); - bufp->chgBit(oldp+699,(vlSelf->main__DOT__i2ci__DOT__imm_cycle)); - bufp->chgBit(oldp+700,(vlSelf->main__DOT__i2ci__DOT__insn_ready)); - bufp->chgBit(oldp+701,(vlSelf->main__DOT__i2ci__DOT__half_ready)); - bufp->chgBit(oldp+702,(vlSelf->main__DOT__i2ci__DOT__i2c_abort)); - bufp->chgBit(oldp+703,(vlSelf->main__DOT__i2ci__DOT__insn_valid)); - bufp->chgSData(oldp+704,(vlSelf->main__DOT__i2ci__DOT__insn),12); - bufp->chgCData(oldp+705,(vlSelf->main__DOT__i2ci__DOT__half_insn),4); - bufp->chgBit(oldp+706,(vlSelf->main__DOT__i2ci__DOT__i2c_ckedge)); - bufp->chgBit(oldp+707,(vlSelf->main__DOT__i2ci__DOT__i2c_stretch)); - bufp->chgSData(oldp+708,(vlSelf->main__DOT__i2ci__DOT__i2c_ckcount),12); - bufp->chgSData(oldp+709,(vlSelf->main__DOT__i2ci__DOT__ckcount),12); - bufp->chgIData(oldp+710,(vlSelf->main__DOT__i2ci__DOT__abort_address),28); - bufp->chgIData(oldp+711,(vlSelf->main__DOT__i2ci__DOT__jump_target),28); - bufp->chgBit(oldp+712,(vlSelf->main__DOT__i2ci__DOT__r_wait)); - bufp->chgBit(oldp+713,(vlSelf->main__DOT__i2ci__DOT__soft_halt_request)); - bufp->chgBit(oldp+714,(vlSelf->main__DOT__i2ci__DOT__r_err)); - bufp->chgBit(oldp+715,(vlSelf->main__DOT__i2ci__DOT__r_aborted)); - bufp->chgBit(oldp+716,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual)); - bufp->chgBit(oldp+717,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda)); - bufp->chgBit(oldp+718,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl)); - bufp->chgBit(oldp+719,(((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - | (IData)(vlSelf->main__DOT__i2ci__DOT__r_wait)))); - bufp->chgBit(oldp+720,(vlSelf->main__DOT__i2ci__DOT__w_sda)); - bufp->chgBit(oldp+721,(vlSelf->main__DOT__i2ci__DOT__w_scl)); - bufp->chgBit(oldp+722,(vlSelf->main__DOT__i2ci__DOT__ovw_ready)); - bufp->chgBit(oldp+723,(vlSelf->main__DOT__i2ci__DOT__s_tvalid)); - bufp->chgSData(oldp+724,(vlSelf->main__DOT__i2ci__DOT__ovw_data),10); - bufp->chgBit(oldp+725,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl)); - bufp->chgBit(oldp+726,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda)); - bufp->chgBit(oldp+727,(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__mid_axis_pkt)); - bufp->chgCData(oldp+728,(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__r_channel),2); - bufp->chgSData(oldp+729,((0x7ffU & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))),11); - bufp->chgBit(oldp+730,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte)); - bufp->chgBit(oldp+731,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir)); - bufp->chgBit(oldp+732,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack)); - bufp->chgCData(oldp+733,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state),4); - bufp->chgCData(oldp+734,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits),3); - bufp->chgCData(oldp+735,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg),8); - bufp->chgBit(oldp+736,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_scl)); - bufp->chgBit(oldp+737,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_sda)); - bufp->chgBit(oldp+738,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)); - bufp->chgBit(oldp+739,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda)); - bufp->chgBit(oldp+740,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_scl)); - bufp->chgBit(oldp+741,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_sda)); - bufp->chgBit(oldp+742,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__stop_bit)); - bufp->chgBit(oldp+743,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy)); - bufp->chgBit(oldp+744,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__last_stb)); - bufp->chgBit(oldp+745,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle)); - bufp->chgWData(oldp+746,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word),512); - bufp->chgBit(oldp+762,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid)); - bufp->chgCData(oldp+763,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight),2); - bufp->chgBit(oldp+764,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal)); - bufp->chgBit(oldp+765,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid)); - bufp->chgWData(oldp+766,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn),512); - bufp->chgWData(oldp+782,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted),512); - bufp->chgCData(oldp+798,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count),7); - bufp->chgCData(oldp+799,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift),6); - bufp->chgBit(oldp+800,(vlSelf->main__DOT__i2cscopei__DOT__read_address)); - bufp->chgSData(oldp+801,(vlSelf->main__DOT__i2cscopei__DOT__raddr),10); - bufp->chgSData(oldp+802,(vlSelf->main__DOT__i2cscopei__DOT__waddr),10); - bufp->chgBit(oldp+803,((1U & (~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U))))); - bufp->chgBit(oldp+804,((1U & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 1U)))); - bufp->chgBit(oldp+805,((1U & (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config)))); - bufp->chgCData(oldp+806,(vlSelf->main__DOT__i2cscopei__DOT__br_config),3); - bufp->chgIData(oldp+807,(vlSelf->main__DOT__i2cscopei__DOT__br_holdoff),20); - bufp->chgIData(oldp+808,(vlSelf->main__DOT__i2cscopei__DOT__holdoff_counter),20); - bufp->chgBit(oldp+809,(vlSelf->main__DOT__i2cscopei__DOT__dr_triggered)); - bufp->chgBit(oldp+810,(vlSelf->main__DOT__i2cscopei__DOT__dr_primed)); - bufp->chgBit(oldp+811,(vlSelf->main__DOT__i2cscopei__DOT__dw_trigger)); - bufp->chgBit(oldp+812,(vlSelf->main__DOT__i2cscopei__DOT__dr_stopped)); - bufp->chgCData(oldp+813,(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe),5); - bufp->chgBit(oldp+814,((1U & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - >> 4U)))); - bufp->chgIData(oldp+815,(vlSelf->main__DOT__i2cscopei__DOT__ck_addr),31); - bufp->chgIData(oldp+816,(vlSelf->main__DOT__i2cscopei__DOT__qd_data),31); - bufp->chgBit(oldp+817,(vlSelf->main__DOT__i2cscopei__DOT__dr_force_write)); - bufp->chgBit(oldp+818,(vlSelf->main__DOT__i2cscopei__DOT__dr_run_timeout)); - bufp->chgBit(oldp+819,(vlSelf->main__DOT__i2cscopei__DOT__new_data)); - bufp->chgBit(oldp+820,(vlSelf->main__DOT__i2cscopei__DOT__dr_force_inhibit)); - bufp->chgBit(oldp+821,(vlSelf->main__DOT__i2cscopei__DOT__imm_adr)); - bufp->chgBit(oldp+822,(vlSelf->main__DOT__i2cscopei__DOT__lst_adr)); - bufp->chgIData(oldp+823,(vlSelf->main__DOT__i2cscopei__DOT__lst_val),31); - bufp->chgIData(oldp+824,(vlSelf->main__DOT__i2cscopei__DOT__imm_val),31); - bufp->chgBit(oldp+825,(vlSelf->main__DOT__i2cscopei__DOT__record_ce)); - bufp->chgIData(oldp+826,(vlSelf->main__DOT__i2cscopei__DOT__r_data),32); - bufp->chgBit(oldp+827,(vlSelf->main__DOT__i2cscopei__DOT__br_pre_wb_ack)); - bufp->chgSData(oldp+828,(vlSelf->main__DOT__i2cscopei__DOT__this_addr),10); - bufp->chgIData(oldp+829,(vlSelf->main__DOT__i2cscopei__DOT__nxt_mem),32); - bufp->chgBit(oldp+830,(vlSelf->main__DOT__i2cscopei__DOT__br_level_interrupt)); - bufp->chgCData(oldp+831,(vlSelf->main__DOT__rcv__DOT__state),4); - bufp->chgCData(oldp+832,(vlSelf->main__DOT__rcv__DOT__baud_counter),7); - bufp->chgBit(oldp+833,(vlSelf->main__DOT__rcv__DOT__zero_baud_counter)); - bufp->chgBit(oldp+834,(vlSelf->main__DOT__rcv__DOT__q_uart)); - bufp->chgBit(oldp+835,(vlSelf->main__DOT__rcv__DOT__qq_uart)); - bufp->chgBit(oldp+836,(vlSelf->main__DOT__rcv__DOT__ck_uart)); - bufp->chgCData(oldp+837,(vlSelf->main__DOT__rcv__DOT__chg_counter),7); - bufp->chgBit(oldp+838,(vlSelf->main__DOT__rcv__DOT__half_baud_time)); - bufp->chgCData(oldp+839,(vlSelf->main__DOT__rcv__DOT__data_reg),8); - bufp->chgBit(oldp+840,(vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3)); - bufp->chgIData(oldp+841,(vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4),31); - bufp->chgBit(oldp+842,(vlSelf->main__DOT__sdioscopei__DOT__read_address)); - bufp->chgSData(oldp+843,(vlSelf->main__DOT__sdioscopei__DOT__raddr),12); - bufp->chgSData(oldp+844,(vlSelf->main__DOT__sdioscopei__DOT__waddr),12); - bufp->chgBit(oldp+845,((1U & (~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U))))); - bufp->chgBit(oldp+846,((1U & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 1U)))); - bufp->chgBit(oldp+847,((1U & (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config)))); - bufp->chgCData(oldp+848,(vlSelf->main__DOT__sdioscopei__DOT__br_config),3); - bufp->chgIData(oldp+849,(vlSelf->main__DOT__sdioscopei__DOT__br_holdoff),20); - bufp->chgIData(oldp+850,(vlSelf->main__DOT__sdioscopei__DOT__holdoff_counter),20); - bufp->chgBit(oldp+851,(vlSelf->main__DOT__sdioscopei__DOT__dr_triggered)); - bufp->chgBit(oldp+852,(vlSelf->main__DOT__sdioscopei__DOT__dr_primed)); - bufp->chgBit(oldp+853,(vlSelf->main__DOT__sdioscopei__DOT__dw_trigger)); - bufp->chgBit(oldp+854,(vlSelf->main__DOT__sdioscopei__DOT__dr_stopped)); - bufp->chgCData(oldp+855,(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe),5); - bufp->chgBit(oldp+856,((1U & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - >> 4U)))); - bufp->chgIData(oldp+857,(vlSelf->main__DOT__sdioscopei__DOT__ck_addr),31); - bufp->chgIData(oldp+858,(vlSelf->main__DOT__sdioscopei__DOT__qd_data),31); - bufp->chgBit(oldp+859,(vlSelf->main__DOT__sdioscopei__DOT__dr_force_write)); - bufp->chgBit(oldp+860,(vlSelf->main__DOT__sdioscopei__DOT__dr_run_timeout)); - bufp->chgBit(oldp+861,(vlSelf->main__DOT__sdioscopei__DOT__new_data)); - bufp->chgBit(oldp+862,(vlSelf->main__DOT__sdioscopei__DOT__dr_force_inhibit)); - bufp->chgBit(oldp+863,(vlSelf->main__DOT__sdioscopei__DOT__imm_adr)); - bufp->chgBit(oldp+864,(vlSelf->main__DOT__sdioscopei__DOT__lst_adr)); - bufp->chgIData(oldp+865,(vlSelf->main__DOT__sdioscopei__DOT__lst_val),31); - bufp->chgIData(oldp+866,(vlSelf->main__DOT__sdioscopei__DOT__imm_val),31); - bufp->chgBit(oldp+867,(vlSelf->main__DOT__sdioscopei__DOT__record_ce)); - bufp->chgIData(oldp+868,(vlSelf->main__DOT__sdioscopei__DOT__r_data),32); - bufp->chgBit(oldp+869,(vlSelf->main__DOT__sdioscopei__DOT__br_pre_wb_ack)); - bufp->chgSData(oldp+870,(vlSelf->main__DOT__sdioscopei__DOT__this_addr),12); - bufp->chgIData(oldp+871,(vlSelf->main__DOT__sdioscopei__DOT__nxt_mem),32); - bufp->chgBit(oldp+872,(vlSelf->main__DOT__sdioscopei__DOT__br_level_interrupt)); - bufp->chgBit(oldp+873,(vlSelf->main__DOT__spioi__DOT__led_demo)); - bufp->chgCData(oldp+874,(vlSelf->main__DOT__spioi__DOT__r_led),8); - bufp->chgCData(oldp+875,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn),8); - bufp->chgCData(oldp+876,(vlSelf->main__DOT__spioi__DOT__bounced),8); - bufp->chgCData(oldp+877,(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw),8); - bufp->chgBit(oldp+878,(vlSelf->main__DOT__spioi__DOT__sw_int)); - bufp->chgBit(oldp+879,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn_int)); - bufp->chgCData(oldp+880,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__s_btn),5); - bufp->chgCData(oldp+881,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn),5); - bufp->chgSData(oldp+882,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe),10); - bufp->chgSData(oldp+883,(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe),16); - bufp->chgCData(oldp+884,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner),8); - bufp->chgBit(oldp+885,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_dir)); - bufp->chgIData(oldp+886,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr),25); - bufp->chgBit(oldp+887,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_clk)); - bufp->chgCData(oldp+888,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr),5); - bufp->chgCData(oldp+889,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness),5); - bufp->chgCData(oldp+890,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness),5); - bufp->chgCData(oldp+891,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness),5); - bufp->chgCData(oldp+892,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness),5); - bufp->chgCData(oldp+893,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness),5); - bufp->chgCData(oldp+894,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness),5); - bufp->chgCData(oldp+895,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness),5); - bufp->chgCData(oldp+896,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness),5); - bufp->chgSData(oldp+897,(vlSelf->main__DOT__swic__DOT__main_int_vector),15); - bufp->chgSData(oldp+898,(vlSelf->main__DOT__swic__DOT__alt_int_vector),15); - bufp->chgBit(oldp+899,(vlSelf->main__DOT__swic__DOT__ctri_int)); - bufp->chgBit(oldp+900,(vlSelf->main__DOT__swic__DOT__tma_int)); - bufp->chgBit(oldp+901,(vlSelf->main__DOT__swic__DOT__tmb_int)); - bufp->chgBit(oldp+902,(vlSelf->main__DOT__swic__DOT__tmc_int)); - bufp->chgBit(oldp+903,(vlSelf->main__DOT__swic__DOT__jif_int)); - bufp->chgBit(oldp+904,(vlSelf->main__DOT__swic__DOT__dmac_int)); - bufp->chgBit(oldp+905,(vlSelf->main__DOT__swic__DOT__mtc_int)); - bufp->chgBit(oldp+906,(vlSelf->main__DOT__swic__DOT__moc_int)); - bufp->chgBit(oldp+907,(vlSelf->main__DOT__swic__DOT__mpc_int)); - bufp->chgBit(oldp+908,(vlSelf->main__DOT__swic__DOT__mic_int)); - bufp->chgBit(oldp+909,(vlSelf->main__DOT__swic__DOT__utc_int)); - bufp->chgBit(oldp+910,(vlSelf->main__DOT__swic__DOT__uoc_int)); - bufp->chgBit(oldp+911,(vlSelf->main__DOT__swic__DOT__upc_int)); - bufp->chgBit(oldp+912,(vlSelf->main__DOT__swic__DOT__uic_int)); - bufp->chgIData(oldp+913,(((4U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? ((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data)) - : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data)))),32); - bufp->chgBit(oldp+914,(vlSelf->main__DOT__swic__DOT__actr_ack)); - bufp->chgBit(oldp+915,(((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - | ((IData)(vlSelf->main__DOT__swic__DOT__cmd_read) - | ((~ ((IData)(vlSelf->main__DOT__swic__DOT__dbg_addr) - >> 6U)) & (IData)(vlSelf->main__DOT__swic__DOT__dbg_stb)))))); - bufp->chgBit(oldp+916,(vlSelf->main__DOT__swic__DOT__sys_cyc)); - bufp->chgBit(oldp+917,(vlSelf->main__DOT__swic__DOT__sys_stb)); - bufp->chgBit(oldp+918,(vlSelf->main__DOT__swic__DOT__sys_we)); - bufp->chgCData(oldp+919,(vlSelf->main__DOT__swic__DOT__sys_addr),8); - bufp->chgIData(oldp+920,(vlSelf->main__DOT__swic__DOT__sys_data),32); - bufp->chgIData(oldp+921,(vlSelf->main__DOT__swic__DOT__cpu_addr),22); - bufp->chgIData(oldp+922,(vlSelf->main__DOT__swic__DOT__sys_idata),32); - bufp->chgBit(oldp+923,(vlSelf->main__DOT__swic__DOT__sys_ack)); - bufp->chgBit(oldp+924,(vlSelf->main__DOT__swic__DOT__sel_timer)); - bufp->chgBit(oldp+925,(vlSelf->main__DOT__swic__DOT__sel_pic)); - bufp->chgBit(oldp+926,(vlSelf->main__DOT__swic__DOT__sel_apic)); - bufp->chgBit(oldp+927,(vlSelf->main__DOT__swic__DOT__sel_watchdog)); - bufp->chgBit(oldp+928,(vlSelf->main__DOT__swic__DOT__sel_bus_watchdog)); - bufp->chgBit(oldp+929,(vlSelf->main__DOT__swic__DOT__sel_dmac)); - bufp->chgBit(oldp+930,(((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_addr) - >> 7U)))); - bufp->chgBit(oldp+931,(vlSelf->main__DOT__swic__DOT__dbg_cyc)); - bufp->chgBit(oldp+932,(vlSelf->main__DOT__swic__DOT__dbg_stb)); - bufp->chgBit(oldp+933,(vlSelf->main__DOT__swic__DOT__dbg_we)); - bufp->chgCData(oldp+934,(vlSelf->main__DOT__swic__DOT__dbg_addr),7); - bufp->chgIData(oldp+935,(vlSelf->main__DOT__swic__DOT__dbg_idata),32); - bufp->chgBit(oldp+936,(vlSelf->main__DOT__swic__DOT__dbg_ack)); - bufp->chgBit(oldp+937,(vlSelf->main__DOT__swic__DOT__dbg_stall)); - bufp->chgIData(oldp+938,(vlSelf->main__DOT__swic__DOT__dbg_odata),32); - bufp->chgCData(oldp+939,(vlSelf->main__DOT__swic__DOT__dbg_sel),4); - bufp->chgBit(oldp+940,(vlSelf->main__DOT__swic__DOT__no_dbg_err)); - bufp->chgBit(oldp+941,(vlSelf->main__DOT__swic__DOT__cpu_break)); - bufp->chgBit(oldp+942,(vlSelf->main__DOT__swic__DOT__dbg_cmd_write)); - bufp->chgBit(oldp+943,(vlSelf->main__DOT__swic__DOT__dbg_cpu_write)); - bufp->chgBit(oldp+944,(vlSelf->main__DOT__swic__DOT__dbg_cpu_read)); - bufp->chgBit(oldp+945,(vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__r_reset_hold)); - bufp->chgBit(oldp+946,(vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch)); - bufp->chgBit(oldp+947,(vlSelf->main__DOT__swic__DOT__reset_request)); - bufp->chgBit(oldp+948,(((~ vlSelf->main__DOT__swic__DOT__dbg_idata) - & (IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0)))); - bufp->chgBit(oldp+949,(vlSelf->main__DOT__swic__DOT__halt_request)); - bufp->chgBit(oldp+950,(vlSelf->main__DOT__swic__DOT__step_request)); - bufp->chgBit(oldp+951,(vlSelf->main__DOT__swic__DOT__clear_cache_request)); - bufp->chgBit(oldp+952,(vlSelf->main__DOT__swic__DOT__cmd_reset)); - bufp->chgBit(oldp+953,(vlSelf->main__DOT__swic__DOT__cmd_halt)); - bufp->chgBit(oldp+954,(vlSelf->main__DOT__swic__DOT__cmd_step)); - bufp->chgBit(oldp+955,(vlSelf->main__DOT__swic__DOT__cmd_clear_cache)); - bufp->chgBit(oldp+956,(vlSelf->main__DOT__swic__DOT__cmd_write)); - bufp->chgBit(oldp+957,(vlSelf->main__DOT__swic__DOT__cmd_read)); - bufp->chgCData(oldp+958,(vlSelf->main__DOT__swic__DOT__cmd_waddr),5); - bufp->chgIData(oldp+959,(vlSelf->main__DOT__swic__DOT__cmd_wdata),32); - bufp->chgCData(oldp+960,(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc),3); - bufp->chgBit(oldp+961,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall))))); - bufp->chgBit(oldp+962,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)); - bufp->chgIData(oldp+963,(((((IData)(vlSelf->main__DOT__gpio_int) - << 0x1bU) | (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0x1aU) - | ((0x2000000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0x19U)) - | ((0x1000000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0x18U)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0x17U) - | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 0x16U) - | (((IData)(vlSelf->main__DOT__emmcscope_int) - << 0x15U) - | ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0) - << 0xcU)))))))) - | (((IData)(vlSelf->main__DOT__swic__DOT__cpu_break) - << 0xbU) | (((IData)(vlSelf->main__DOT__swic__DOT__pic_interrupt) - << 0xaU) - | ((0x300U - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - << 8U)) - | (((IData)(vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch) - << 5U) - | (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - << 3U) - | ((2U - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)) - << 1U)) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))))))))),32); - bufp->chgBit(oldp+964,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))); - bufp->chgBit(oldp+965,(vlSelf->main__DOT__swic__DOT__wdt_ack)); - bufp->chgBit(oldp+966,(vlSelf->main__DOT__swic__DOT__wdt_reset)); - bufp->chgIData(oldp+967,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value),32); - bufp->chgBit(oldp+968,(vlSelf->main__DOT__swic__DOT__wdbus_ack)); - bufp->chgIData(oldp+969,(vlSelf->main__DOT__swic__DOT__r_wdbus_data),22); - bufp->chgIData(oldp+970,(vlSelf->main__DOT__swic__DOT__pic_data),32); - bufp->chgIData(oldp+971,(vlSelf->main__DOT__swic__DOT__r_wdbus_data),32); - bufp->chgBit(oldp+972,((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_zip_cyc)) - | ((IData)(vlSelf->main__DOT__wbwide_zip_stb) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U)))))); - bufp->chgBit(oldp+973,(vlSelf->main__DOT__swic__DOT__wdbus_int)); - bufp->chgBit(oldp+974,(vlSelf->main__DOT__swic__DOT__cpu_pf_stall)); - bufp->chgBit(oldp+975,(vlSelf->main__DOT__swic__DOT__cpu_i_count)); - bufp->chgBit(oldp+976,(vlSelf->main__DOT__swic__DOT__dmac_stb)); - bufp->chgBit(oldp+977,(vlSelf->main__DOT__swic__DOT__dc_err)); - bufp->chgIData(oldp+978,(vlSelf->main__DOT__swic__DOT__dmac_data),32); - bufp->chgBit(oldp+979,(vlSelf->main__DOT__swic__DOT__dmac_ack)); - bufp->chgBit(oldp+980,(vlSelf->main__DOT__swic__DOT__dc_cyc)); - bufp->chgBit(oldp+981,(vlSelf->main__DOT__swic__DOT__dc_stb)); - bufp->chgBit(oldp+982,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner))))); - bufp->chgBit(oldp+983,(vlSelf->main__DOT__swic__DOT__dc_stall)); - bufp->chgBit(oldp+984,(vlSelf->main__DOT__swic__DOT__dc_ack)); - bufp->chgIData(oldp+985,(((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr)),22); - bufp->chgWData(oldp+986,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data),512); - bufp->chgQData(oldp+1002,(((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel)),64); - bufp->chgBit(oldp+1004,(vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc)); - bufp->chgIData(oldp+1005,((((IData)(vlSelf->main__DOT__swic__DOT__alt_int_vector) - << 0x10U) | (((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0) - << 6U) - | (((IData)(vlSelf->main__DOT__swic__DOT__ctri_int) - << 5U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tma_int) - << 4U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tmb_int) - << 3U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tmc_int) - << 2U) - | ((IData)(vlSelf->main__DOT__swic__DOT__jif_int) - << 1U)))))))),32); - bufp->chgBit(oldp+1006,(((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_apic)))); - bufp->chgIData(oldp+1007,(vlSelf->main__DOT__swic__DOT__ctri_data),32); - bufp->chgBit(oldp+1008,(vlSelf->main__DOT__swic__DOT__tma_ack)); - bufp->chgBit(oldp+1009,(vlSelf->main__DOT__swic__DOT__tmb_ack)); - bufp->chgBit(oldp+1010,(vlSelf->main__DOT__swic__DOT__tmc_ack)); - bufp->chgBit(oldp+1011,(vlSelf->main__DOT__swic__DOT__jif_ack)); - bufp->chgIData(oldp+1012,((((IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) | vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value)),32); - bufp->chgIData(oldp+1013,((((IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) | vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value)),32); - bufp->chgIData(oldp+1014,((((IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) | vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value)),32); - bufp->chgIData(oldp+1015,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter),32); - bufp->chgBit(oldp+1016,(((IData)(vlSelf->main__DOT__swic__DOT__sys_cyc) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_pic))))); - bufp->chgBit(oldp+1017,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb)))); - bufp->chgBit(oldp+1018,(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc)); - bufp->chgBit(oldp+1019,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl)))); - bufp->chgBit(oldp+1020,(vlSelf->main__DOT__swic__DOT__cpu_we)); - bufp->chgWData(oldp+1021,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data),512); - bufp->chgQData(oldp+1037,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL)),64); - bufp->chgWData(oldp+1039,(vlSelf->main__DOT__swic__DOT__cpu_idata),512); - bufp->chgBit(oldp+1055,(vlSelf->main__DOT__swic__DOT__cpu_stall)); - bufp->chgBit(oldp+1056,(vlSelf->main__DOT__swic__DOT__pic_interrupt)); - bufp->chgBit(oldp+1057,(vlSelf->main__DOT__swic__DOT__cpu_ack)); - bufp->chgBit(oldp+1058,(vlSelf->main__DOT__swic__DOT__cpu_err)); - bufp->chgIData(oldp+1059,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg),32); - bufp->chgBit(oldp+1060,((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)) - | ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 2U))))); - bufp->chgBit(oldp+1061,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U) & (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)))); - bufp->chgBit(oldp+1062,(((IData)(vlSelf->main__DOT__swic__DOT__ext_err) - & (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)))); - bufp->chgBit(oldp+1063,(vlSelf->main__DOT__swic__DOT__r_mmus_ack)); - bufp->chgBit(oldp+1064,(vlSelf->main__DOT__swic__DOT__ext_err)); - bufp->chgIData(oldp+1065,(((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter - : (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value)) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value) - : (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value)))),32); - bufp->chgCData(oldp+1066,(vlSelf->main__DOT__swic__DOT__w_ack_idx),3); - bufp->chgCData(oldp+1067,(vlSelf->main__DOT__swic__DOT__ack_idx),3); - bufp->chgBit(oldp+1068,(vlSelf->main__DOT__swic__DOT__last_sys_stb)); - bufp->chgBit(oldp+1069,(vlSelf->main__DOT__swic__DOT__cmd_read_ack)); - bufp->chgBit(oldp+1070,(vlSelf->main__DOT__swic__DOT__dbg_pre_ack)); - bufp->chgCData(oldp+1071,(vlSelf->main__DOT__swic__DOT__dbg_pre_addr),2); - bufp->chgIData(oldp+1072,(vlSelf->main__DOT__swic__DOT__dbg_cpu_status),32); - bufp->chgBit(oldp+1073,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_ack)); - bufp->chgBit(oldp+1074,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_ack)); - bufp->chgBit(oldp+1075,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_ack)); - bufp->chgBit(oldp+1076,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_ack)); - bufp->chgBit(oldp+1077,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_ack)); - bufp->chgBit(oldp+1078,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_ack)); - bufp->chgBit(oldp+1079,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_ack)); - bufp->chgBit(oldp+1080,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_ack)); - bufp->chgIData(oldp+1081,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data),32); - bufp->chgIData(oldp+1082,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data),32); - bufp->chgIData(oldp+1083,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data),32); - bufp->chgIData(oldp+1084,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data),32); - bufp->chgIData(oldp+1085,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data),32); - bufp->chgIData(oldp+1086,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data),32); - bufp->chgIData(oldp+1087,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data),32); - bufp->chgIData(oldp+1088,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data),32); - bufp->chgBit(oldp+1089,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mins_ctr____pinNumber5)); - bufp->chgBit(oldp+1090,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mmstall_ctr____pinNumber5)); - bufp->chgBit(oldp+1091,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mpstall_ctr____pinNumber5)); - bufp->chgBit(oldp+1092,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))))); - bufp->chgBit(oldp+1093,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mtask_ctr____pinNumber5)); - bufp->chgBit(oldp+1094,(((IData)(vlSelf->main__DOT__swic__DOT__cpu_i_count) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))); - bufp->chgBit(oldp+1095,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__uins_ctr____pinNumber5)); - bufp->chgBit(oldp+1096,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__umstall_ctr____pinNumber5)); - bufp->chgBit(oldp+1097,(((IData)(vlSelf->main__DOT__swic__DOT__cpu_pf_stall) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))); - bufp->chgBit(oldp+1098,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__upstall_ctr____pinNumber5)); - bufp->chgBit(oldp+1099,((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U))))); - bufp->chgBit(oldp+1100,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__utask_ctr____pinNumber5)); - bufp->chgBit(oldp+1101,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_we)); - bufp->chgCData(oldp+1102,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_addr),7); - bufp->chgIData(oldp+1103,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_data),32); - bufp->chgCData(oldp+1104,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_sel),4); - bufp->chgCData(oldp+1105,((3U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))),2); - bufp->chgBit(oldp+1106,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request)); - bufp->chgBit(oldp+1107,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort)); - bufp->chgBit(oldp+1108,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)); - bufp->chgBit(oldp+1109,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err)); - bufp->chgIData(oldp+1110,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src),28); - bufp->chgIData(oldp+1111,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst),28); - bufp->chgIData(oldp+1112,((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - << 6U)),28); - bufp->chgIData(oldp+1113,((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr - << 6U)),28); - bufp->chgIData(oldp+1114,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length),28); - bufp->chgIData(oldp+1115,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length),28); - bufp->chgSData(oldp+1116,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen),11); - bufp->chgBit(oldp+1117,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger)); - bufp->chgBit(oldp+1118,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request)); - bufp->chgBit(oldp+1119,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request)); - bufp->chgBit(oldp+1120,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy)); - bufp->chgBit(oldp+1121,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy)); - bufp->chgBit(oldp+1122,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err)); - bufp->chgBit(oldp+1123,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err)); - bufp->chgBit(oldp+1124,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc)); - bufp->chgBit(oldp+1125,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc)); - bufp->chgCData(oldp+1126,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size),2); - bufp->chgCData(oldp+1127,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size),2); - bufp->chgIData(oldp+1128,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr),28); - bufp->chgIData(oldp+1129,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr),28); - bufp->chgSData(oldp+1130,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen),11); - bufp->chgBit(oldp+1131,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc)); - bufp->chgBit(oldp+1132,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb)); - bufp->chgBit(oldp+1133,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall)); - bufp->chgBit(oldp+1134,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack)); - bufp->chgBit(oldp+1135,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err)); - bufp->chgIData(oldp+1136,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr),22); - bufp->chgQData(oldp+1137,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel),64); - bufp->chgBit(oldp+1139,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid)); - bufp->chgBit(oldp+1140,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready)); - bufp->chgBit(oldp+1141,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last)); - bufp->chgWData(oldp+1142,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg),512); - bufp->chgCData(oldp+1158,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes),7); - bufp->chgBit(oldp+1159,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid)); - bufp->chgBit(oldp+1160,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full))))); - bufp->chgBit(oldp+1161,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last)); - __Vtemp_hd1e4c677__0[0U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U]; - __Vtemp_hd1e4c677__0[1U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U]; - __Vtemp_hd1e4c677__0[2U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U]; - __Vtemp_hd1e4c677__0[3U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U]; - __Vtemp_hd1e4c677__0[4U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U]; - __Vtemp_hd1e4c677__0[5U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U]; - __Vtemp_hd1e4c677__0[6U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U]; - __Vtemp_hd1e4c677__0[7U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U]; - __Vtemp_hd1e4c677__0[8U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U]; - __Vtemp_hd1e4c677__0[9U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U]; - __Vtemp_hd1e4c677__0[0xaU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU]; - __Vtemp_hd1e4c677__0[0xbU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU]; - __Vtemp_hd1e4c677__0[0xcU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU]; - __Vtemp_hd1e4c677__0[0xdU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU]; - __Vtemp_hd1e4c677__0[0xeU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU]; - __Vtemp_hd1e4c677__0[0xfU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU]; - bufp->chgWData(oldp+1162,(__Vtemp_hd1e4c677__0),512); - bufp->chgCData(oldp+1178,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes),7); - bufp->chgBit(oldp+1179,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty))))); - bufp->chgBit(oldp+1180,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready)); - bufp->chgBit(oldp+1181,((1U & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U] - >> 7U)))); - __Vtemp_h6ddae8d1__0[0U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0U]; - __Vtemp_h6ddae8d1__0[1U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[1U]; - __Vtemp_h6ddae8d1__0[2U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[2U]; - __Vtemp_h6ddae8d1__0[3U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[3U]; - __Vtemp_h6ddae8d1__0[4U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[4U]; - __Vtemp_h6ddae8d1__0[5U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[5U]; - __Vtemp_h6ddae8d1__0[6U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[6U]; - __Vtemp_h6ddae8d1__0[7U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[7U]; - __Vtemp_h6ddae8d1__0[8U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[8U]; - __Vtemp_h6ddae8d1__0[9U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[9U]; - __Vtemp_h6ddae8d1__0[0xaU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xaU]; - __Vtemp_h6ddae8d1__0[0xbU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xbU]; - __Vtemp_h6ddae8d1__0[0xcU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xcU]; - __Vtemp_h6ddae8d1__0[0xdU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xdU]; - __Vtemp_h6ddae8d1__0[0xeU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xeU]; - __Vtemp_h6ddae8d1__0[0xfU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xfU]; - bufp->chgWData(oldp+1182,(__Vtemp_h6ddae8d1__0),512); - bufp->chgCData(oldp+1198,((0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])),7); - bufp->chgBit(oldp+1199,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)); - bufp->chgBit(oldp+1200,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty)); - bufp->chgCData(oldp+1201,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill),5); - bufp->chgBit(oldp+1202,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid)); - bufp->chgBit(oldp+1203,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready)); - bufp->chgBit(oldp+1204,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last)); - bufp->chgWData(oldp+1205,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg),512); - bufp->chgCData(oldp+1221,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes),7); - bufp->chgBit(oldp+1222,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc)); - bufp->chgBit(oldp+1223,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb)); - bufp->chgBit(oldp+1224,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall)); - bufp->chgBit(oldp+1225,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack)); - bufp->chgBit(oldp+1226,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err)); - bufp->chgIData(oldp+1227,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr),22); - bufp->chgQData(oldp+1228,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel),64); - bufp->chgBit(oldp+1230,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)); - bufp->chgBit(oldp+1231,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner)); - bufp->chgBit(oldp+1232,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger)); - bufp->chgBit(oldp+1233,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err)); - bufp->chgBit(oldp+1234,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_zero_len)); - bufp->chgBit(oldp+1235,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_busy)); - bufp->chgCData(oldp+1236,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel),5); - bufp->chgIData(oldp+1237,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src),32); - bufp->chgIData(oldp+1238,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst),32); - bufp->chgIData(oldp+1239,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len),32); - bufp->chgIData(oldp+1240,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen),32); - bufp->chgIData(oldp+1241,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg),32); - bufp->chgCData(oldp+1242,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state),2); - bufp->chgBit(oldp+1243,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset)); - bufp->chgCData(oldp+1244,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size),7); - bufp->chgCData(oldp+1245,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size),7); - bufp->chgCData(oldp+1246,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size),7); - bufp->chgCData(oldp+1247,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size),7); - bufp->chgIData(oldp+1248,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr),28); - bufp->chgIData(oldp+1249,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr),28); - bufp->chgCData(oldp+1250,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr),6); - bufp->chgCData(oldp+1251,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr),6); - bufp->chgQData(oldp+1252,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel),64); - bufp->chgQData(oldp+1254,(((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? (0x8000000000000000ULL - >> (0x3fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : ((0x4000000000000000ULL - | ((QData)((IData)( - (1U - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - << 0x3fU)) - >> (0x3eU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((2U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? ((1U - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? (0x1000000000000000ULL - >> - (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : (0x3000000000000000ULL - >> - (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - : ((1U - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? (0x7000000000000000ULL - >> - (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : (0xf000000000000000ULL - >> - (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)))) - : (0xffffffffffffffffULL - >> (0x3fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))))),64); - bufp->chgQData(oldp+1256,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel),64); - bufp->chgQData(oldp+1258,(((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? (0x8000000000000000ULL - >> (0x3fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : (0xc000000000000000ULL - >> (0x3eU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? (0xf000000000000000ULL - >> (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : 0xffffffffffffffffULL))),64); - bufp->chgSData(oldp+1260,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding),11); - bufp->chgCData(oldp+1261,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__fill),8); - bufp->chgCData(oldp+1262,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill),8); - bufp->chgSData(oldp+1263,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len),11); - bufp->chgSData(oldp+1264,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len),11); - bufp->chgCData(oldp+1265,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift),6); - __Vtemp_hc1d82fb0__1[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U]; - __Vtemp_hc1d82fb0__1[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U]; - __Vtemp_hc1d82fb0__1[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U]; - __Vtemp_hc1d82fb0__1[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U]; - __Vtemp_hc1d82fb0__1[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U]; - __Vtemp_hc1d82fb0__1[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U]; - __Vtemp_hc1d82fb0__1[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U]; - __Vtemp_hc1d82fb0__1[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U]; - __Vtemp_hc1d82fb0__1[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U]; - __Vtemp_hc1d82fb0__1[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U]; - __Vtemp_hc1d82fb0__1[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU]; - __Vtemp_hc1d82fb0__1[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU]; - __Vtemp_hc1d82fb0__1[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU]; - __Vtemp_hc1d82fb0__1[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU]; - __Vtemp_hc1d82fb0__1[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU]; - __Vtemp_hc1d82fb0__1[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU]; - VL_SHIFTL_WWI(512,512,32, __Vtemp_h6d0d1506__0, __Vtemp_hc1d82fb0__1, - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift) - << 3U)); - bufp->chgWData(oldp+1266,(__Vtemp_h6d0d1506__0),512); - bufp->chgBit(oldp+1282,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc)); - bufp->chgCData(oldp+1283,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size),2); - bufp->chgWData(oldp+1284,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg),1024); - bufp->chgCData(oldp+1316,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill),8); - bufp->chgCData(oldp+1317,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill),8); - bufp->chgBit(oldp+1318,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last)); - bufp->chgBit(oldp+1319,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last)); - bufp->chgBit(oldp+1320,((0x40U <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill)))); - bufp->chgCData(oldp+1321,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift),6); - bufp->chgWData(oldp+1322,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data),512); - bufp->chgBit(oldp+1338,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc)); - bufp->chgCData(oldp+1339,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size),2); - bufp->chgIData(oldp+1340,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr),29); - bufp->chgCData(oldp+1341,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr),6); - bufp->chgWData(oldp+1342,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data),1024); - bufp->chgWData(oldp+1374,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data),512); - bufp->chgWData(oldp+1390,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel),128); - bufp->chgWData(oldp+1394,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel),128); - bufp->chgQData(oldp+1398,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel),64); - bufp->chgBit(oldp+1400,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last)); - bufp->chgSData(oldp+1401,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding),10); - bufp->chgBit(oldp+1402,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full)); - bufp->chgBit(oldp+1403,((1U & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - >> 0x1cU)))); - __Vtemp_h6b3f223d__0[0U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U]; - __Vtemp_h6b3f223d__0[1U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U]; - __Vtemp_h6b3f223d__0[2U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U]; - __Vtemp_h6b3f223d__0[3U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U]; - __Vtemp_h6b3f223d__0[4U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U]; - __Vtemp_h6b3f223d__0[5U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U]; - __Vtemp_h6b3f223d__0[6U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U]; - __Vtemp_h6b3f223d__0[7U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U]; - __Vtemp_h6b3f223d__0[8U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U]; - __Vtemp_h6b3f223d__0[9U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U]; - __Vtemp_h6b3f223d__0[0xaU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU]; - __Vtemp_h6b3f223d__0[0xbU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU]; - __Vtemp_h6b3f223d__0[0xcU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU]; - __Vtemp_h6b3f223d__0[0xdU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU]; - __Vtemp_h6b3f223d__0[0xeU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU]; - __Vtemp_h6b3f223d__0[0xfU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU]; - __Vtemp_h6b3f223d__0[0x10U] = (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last) - << 7U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes)); - bufp->chgWData(oldp+1404,(__Vtemp_h6b3f223d__0),520); - bufp->chgWData(oldp+1421,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data),520); - bufp->chgWData(oldp+1438,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[0]),520); - bufp->chgWData(oldp+1455,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[1]),520); - bufp->chgWData(oldp+1472,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[2]),520); - bufp->chgWData(oldp+1489,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[3]),520); - bufp->chgWData(oldp+1506,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[4]),520); - bufp->chgWData(oldp+1523,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[5]),520); - bufp->chgWData(oldp+1540,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[6]),520); - bufp->chgWData(oldp+1557,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[7]),520); - bufp->chgWData(oldp+1574,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[8]),520); - bufp->chgWData(oldp+1591,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[9]),520); - bufp->chgWData(oldp+1608,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[10]),520); - bufp->chgWData(oldp+1625,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[11]),520); - bufp->chgWData(oldp+1642,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[12]),520); - bufp->chgWData(oldp+1659,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[13]),520); - bufp->chgWData(oldp+1676,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[14]),520); - bufp->chgWData(oldp+1693,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[15]),520); - bufp->chgCData(oldp+1710,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr),5); - bufp->chgCData(oldp+1711,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr),5); - bufp->chgBit(oldp+1712,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr)); - bufp->chgBit(oldp+1713,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd)); - bufp->chgBit(oldp+1714,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last)); - bufp->chgBit(oldp+1715,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next)); - bufp->chgCData(oldp+1716,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill),7); - bufp->chgCData(oldp+1717,(vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter),5); - bufp->chgSData(oldp+1718,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state),15); - bufp->chgSData(oldp+1719,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable),15); - bufp->chgBit(oldp+1720,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie)); - bufp->chgBit(oldp+1721,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any)); - bufp->chgBit(oldp+1722,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write)); - bufp->chgBit(oldp+1723,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__enable_ints)); - bufp->chgBit(oldp+1724,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__disable_ints)); - bufp->chgSData(oldp+1725,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state),15); - bufp->chgSData(oldp+1726,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable),15); - bufp->chgBit(oldp+1727,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie)); - bufp->chgBit(oldp+1728,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any)); - bufp->chgBit(oldp+1729,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write)); - bufp->chgBit(oldp+1730,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__enable_ints)); - bufp->chgBit(oldp+1731,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__disable_ints)); - bufp->chgBit(oldp+1732,(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)); - bufp->chgCData(oldp+1733,((0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))),5); - bufp->chgBit(oldp+1734,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc)); - bufp->chgBit(oldp+1735,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache)); - bufp->chgIData(oldp+1736,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address),28); - bufp->chgIData(oldp+1737,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU]),32); - bufp->chgIData(oldp+1738,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc),28); - bufp->chgBit(oldp+1739,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)); - bufp->chgBit(oldp+1740,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal)); - bufp->chgBit(oldp+1741,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc)); - bufp->chgBit(oldp+1742,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb)); - bufp->chgBit(oldp+1743,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stall)); - bufp->chgBit(oldp+1744,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack)); - bufp->chgBit(oldp+1745,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err)); - bufp->chgIData(oldp+1746,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr),22); - bufp->chgBit(oldp+1747,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__CLEAR_DCACHE__DOT__r_clear_dcache)); - bufp->chgBit(oldp+1748,((0U != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))); - bufp->chgCData(oldp+1749,((7U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))),3); - bufp->chgIData(oldp+1750,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr),32); - bufp->chgIData(oldp+1751,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_lock_pc),28); - bufp->chgIData(oldp+1752,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata),32); - bufp->chgCData(oldp+1753,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R),5); - bufp->chgBit(oldp+1754,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)); - bufp->chgBit(oldp+1755,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)); - bufp->chgBit(oldp+1756,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled)); - bufp->chgBit(oldp+1757,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid)); - bufp->chgBit(oldp+1758,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err)); - bufp->chgCData(oldp+1759,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wreg),5); - bufp->chgIData(oldp+1760,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result),32); - bufp->chgBit(oldp+1761,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl)); - bufp->chgBit(oldp+1762,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl)); - bufp->chgBit(oldp+1763,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl)); - bufp->chgBit(oldp+1764,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl)); - bufp->chgIData(oldp+1765,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr),22); - bufp->chgBit(oldp+1766,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we)); - bufp->chgBit(oldp+1767,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)); - bufp->chgBit(oldp+1768,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack)); - bufp->chgBit(oldp+1769,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err)); - bufp->chgQData(oldp+1770,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel),64); - bufp->chgIData(oldp+1772,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__ik),32); - bufp->chgBit(oldp+1773,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)); - bufp->chgBit(oldp+1774,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb)); - bufp->chgBit(oldp+1775,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack)); - bufp->chgBit(oldp+1776,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line)); - bufp->chgBit(oldp+1777,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb)); - bufp->chgBit(oldp+1778,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl)); - bufp->chgBit(oldp+1779,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl)); - bufp->chgCData(oldp+1780,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending),5); - bufp->chgCData(oldp+1781,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v),8); - bufp->chgIData(oldp+1782,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[0]),19); - bufp->chgIData(oldp+1783,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[1]),19); - bufp->chgIData(oldp+1784,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[2]),19); - bufp->chgIData(oldp+1785,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[3]),19); - bufp->chgIData(oldp+1786,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[4]),19); - bufp->chgIData(oldp+1787,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[5]),19); - bufp->chgIData(oldp+1788,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[6]),19); - bufp->chgIData(oldp+1789,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[7]),19); - bufp->chgBit(oldp+1790,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag)); - bufp->chgCData(oldp+1791,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state),2); - bufp->chgCData(oldp+1792,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr),6); - bufp->chgWData(oldp+1793,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword),512); - bufp->chgWData(oldp+1809,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword),512); - bufp->chgBit(oldp+1825,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl)); - bufp->chgBit(oldp+1826,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl)); - bufp->chgBit(oldp+1827,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr)); - bufp->chgWData(oldp+1828,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata),512); - bufp->chgQData(oldp+1844,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel),64); - bufp->chgCData(oldp+1846,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr),6); - bufp->chgIData(oldp+1847,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag),19); - bufp->chgBit(oldp+1848,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid)); - bufp->chgCData(oldp+1849,((7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U))),3); - bufp->chgCData(oldp+1850,((0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))),6); - bufp->chgBit(oldp+1851,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow)); - bufp->chgBit(oldp+1852,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable)); - bufp->chgBit(oldp+1853,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address)); - bufp->chgBit(oldp+1854,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable)); - bufp->chgBit(oldp+1855,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid)); - bufp->chgBit(oldp+1856,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid)); - bufp->chgBit(oldp+1857,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd)); - bufp->chgBit(oldp+1858,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss)); - bufp->chgBit(oldp+1859,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending)); - bufp->chgIData(oldp+1860,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr),22); - bufp->chgCData(oldp+1861,((7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U))),3); - bufp->chgCData(oldp+1862,((0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)),6); - bufp->chgIData(oldp+1863,((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U))),19); - bufp->chgBit(oldp+1864,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb)); - bufp->chgBit(oldp+1865,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv)); - bufp->chgBit(oldp+1866,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__in_cache)); - bufp->chgIData(oldp+1867,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag),19); - bufp->chgSData(oldp+1868,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__req_data),13); - bufp->chgBit(oldp+1869,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__gie)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid) { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xfU]; - } else if ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__cpu_idata[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__cpu_idata[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__cpu_idata[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__cpu_idata[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__cpu_idata[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__cpu_idata[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__cpu_idata[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__cpu_idata[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__cpu_idata[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__cpu_idata[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU]; - } else { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xfU]; - } - bufp->chgWData(oldp+1870,(__Vtemp_h01ff8f7b__0),512); - bufp->chgWData(oldp+1886,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted),512); - bufp->chgCData(oldp+1902,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel),4); - bufp->chgQData(oldp+1903,(((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) - ? ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel)) - >> (3U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)) - : (((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel)) - << 0x3cU) >> - (0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)))),64); - bufp->chgIData(oldp+1905,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift),32); - bufp->chgWData(oldp+1906,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift),512); - bufp->chgWData(oldp+1922,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data),512); - bufp->chgSData(oldp+1938,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[0]),12); - bufp->chgSData(oldp+1939,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[1]),12); - bufp->chgSData(oldp+1940,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[2]),12); - bufp->chgSData(oldp+1941,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[3]),12); - bufp->chgSData(oldp+1942,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[4]),12); - bufp->chgSData(oldp+1943,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[5]),12); - bufp->chgSData(oldp+1944,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[6]),12); - bufp->chgSData(oldp+1945,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[7]),12); - bufp->chgSData(oldp+1946,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[8]),12); - bufp->chgSData(oldp+1947,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[9]),12); - bufp->chgSData(oldp+1948,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[10]),12); - bufp->chgSData(oldp+1949,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[11]),12); - bufp->chgSData(oldp+1950,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[12]),12); - bufp->chgSData(oldp+1951,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[13]),12); - bufp->chgSData(oldp+1952,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[14]),12); - bufp->chgSData(oldp+1953,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[15]),12); - bufp->chgCData(oldp+1954,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr),5); - bufp->chgCData(oldp+1955,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr),5); - bufp->chgIData(oldp+1956,((0xfffffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)),28); - bufp->chgBit(oldp+1957,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc) { - __Vtemp_he3c3974d__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0U]; - __Vtemp_he3c3974d__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[1U]; - __Vtemp_he3c3974d__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[2U]; - __Vtemp_he3c3974d__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[3U]; - __Vtemp_he3c3974d__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[4U]; - __Vtemp_he3c3974d__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[5U]; - __Vtemp_he3c3974d__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[6U]; - __Vtemp_he3c3974d__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[7U]; - __Vtemp_he3c3974d__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[8U]; - __Vtemp_he3c3974d__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[9U]; - __Vtemp_he3c3974d__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xaU]; - __Vtemp_he3c3974d__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xbU]; - __Vtemp_he3c3974d__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xcU]; - __Vtemp_he3c3974d__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xdU]; - __Vtemp_he3c3974d__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xeU]; - __Vtemp_he3c3974d__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xfU]; - } else { - __Vtemp_he3c3974d__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0U]; - __Vtemp_he3c3974d__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[1U]; - __Vtemp_he3c3974d__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[2U]; - __Vtemp_he3c3974d__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[3U]; - __Vtemp_he3c3974d__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[4U]; - __Vtemp_he3c3974d__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[5U]; - __Vtemp_he3c3974d__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[6U]; - __Vtemp_he3c3974d__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[7U]; - __Vtemp_he3c3974d__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[8U]; - __Vtemp_he3c3974d__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[9U]; - __Vtemp_he3c3974d__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xaU]; - __Vtemp_he3c3974d__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xbU]; - __Vtemp_he3c3974d__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xcU]; - __Vtemp_he3c3974d__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xdU]; - __Vtemp_he3c3974d__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xeU]; - __Vtemp_he3c3974d__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xfU]; - } - bufp->chgWData(oldp+1958,(__Vtemp_he3c3974d__0),512); - bufp->chgSData(oldp+1974,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[0]),16); - bufp->chgSData(oldp+1975,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[1]),16); - bufp->chgSData(oldp+1976,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[2]),16); - bufp->chgSData(oldp+1977,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[3]),16); - bufp->chgSData(oldp+1978,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[4]),16); - bufp->chgSData(oldp+1979,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[5]),16); - bufp->chgSData(oldp+1980,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[6]),16); - bufp->chgSData(oldp+1981,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[7]),16); - bufp->chgCData(oldp+1982,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask),8); - bufp->chgBit(oldp+1983,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_pc)); - bufp->chgBit(oldp+1984,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_last)); - bufp->chgBit(oldp+1985,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__rvsrc)); - bufp->chgBit(oldp+1986,((((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U)) - == (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup - == (0x7ffffU & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask) - >> (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))))))); - bufp->chgBit(oldp+1987,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_v_from_last)); - bufp->chgIData(oldp+1988,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc),28); - bufp->chgCData(oldp+1989,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr),6); - bufp->chgIData(oldp+1990,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__pc_tag_lookup),19); - bufp->chgIData(oldp+1991,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_tag_lookup),19); - bufp->chgIData(oldp+1992,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup),19); - bufp->chgIData(oldp+1993,((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))),19); - bufp->chgIData(oldp+1994,((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))),19); - bufp->chgBit(oldp+1995,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid)); - bufp->chgIData(oldp+1996,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache),19); - bufp->chgWData(oldp+1997,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache),512); - bufp->chgWData(oldp+2013,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache),512); - bufp->chgBit(oldp+2029,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc)); - bufp->chgCData(oldp+2030,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay),2); - bufp->chgBit(oldp+2031,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__svmask)); - bufp->chgBit(oldp+2032,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack)); - bufp->chgBit(oldp+2033,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__needload)); - bufp->chgBit(oldp+2034,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr)); - bufp->chgBit(oldp+2035,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort)); - bufp->chgCData(oldp+2036,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__saddr),3); - bufp->chgBit(oldp+2037,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_invalidate_result)); - bufp->chgCData(oldp+2038,((7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))),3); - bufp->chgCData(oldp+2039,((7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))),3); - bufp->chgWData(oldp+2040,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted),512); - bufp->chgCData(oldp+2056,((0xfU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc - >> 2U))),4); - bufp->chgBit(oldp+2057,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)); - bufp->chgIData(oldp+2058,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[0]),32); - bufp->chgIData(oldp+2059,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[1]),32); - bufp->chgIData(oldp+2060,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[2]),32); - bufp->chgIData(oldp+2061,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[3]),32); - bufp->chgIData(oldp+2062,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[4]),32); - bufp->chgIData(oldp+2063,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[5]),32); - bufp->chgIData(oldp+2064,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[6]),32); - bufp->chgIData(oldp+2065,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[7]),32); - bufp->chgIData(oldp+2066,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[8]),32); - bufp->chgIData(oldp+2067,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[9]),32); - bufp->chgIData(oldp+2068,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[10]),32); - bufp->chgIData(oldp+2069,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[11]),32); - bufp->chgIData(oldp+2070,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[12]),32); - bufp->chgIData(oldp+2071,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[13]),32); - bufp->chgIData(oldp+2072,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[14]),32); - bufp->chgIData(oldp+2073,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[15]),32); - bufp->chgIData(oldp+2074,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[16]),32); - bufp->chgIData(oldp+2075,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[17]),32); - bufp->chgIData(oldp+2076,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[18]),32); - bufp->chgIData(oldp+2077,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[19]),32); - bufp->chgIData(oldp+2078,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[20]),32); - bufp->chgIData(oldp+2079,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[21]),32); - bufp->chgIData(oldp+2080,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[22]),32); - bufp->chgIData(oldp+2081,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[23]),32); - bufp->chgIData(oldp+2082,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[24]),32); - bufp->chgIData(oldp+2083,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[25]),32); - bufp->chgIData(oldp+2084,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[26]),32); - bufp->chgIData(oldp+2085,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[27]),32); - bufp->chgIData(oldp+2086,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[28]),32); - bufp->chgIData(oldp+2087,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[29]),32); - bufp->chgIData(oldp+2088,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[30]),32); - bufp->chgIData(oldp+2089,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[31]),32); - bufp->chgCData(oldp+2090,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__flags),4); - bufp->chgCData(oldp+2091,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__iflags),4); - bufp->chgSData(oldp+2092,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags),16); - bufp->chgSData(oldp+2093,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags),16); - bufp->chgBit(oldp+2094,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en)); - bufp->chgBit(oldp+2095,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step)); - bufp->chgBit(oldp+2096,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep)); - bufp->chgBit(oldp+2097,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted)); - bufp->chgBit(oldp+2098,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending)); - bufp->chgBit(oldp+2099,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap)); - bufp->chgBit(oldp+2100,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)); - bufp->chgBit(oldp+2101,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak)); - bufp->chgBit(oldp+2102,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt)); - bufp->chgBit(oldp+2103,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped)); - bufp->chgBit(oldp+2104,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step)); - bufp->chgBit(oldp+2105,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u)); - bufp->chgBit(oldp+2106,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i)); - bufp->chgBit(oldp+2107,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag)); - bufp->chgBit(oldp+2108,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag)); - bufp->chgBit(oldp+2109,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag)); - bufp->chgBit(oldp+2110,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag)); - bufp->chgBit(oldp+2111,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase)); - bufp->chgBit(oldp+2112,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase)); - bufp->chgBit(oldp+2113,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce)); - bufp->chgIData(oldp+2114,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc),28); - bufp->chgBit(oldp+2115,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)); - bufp->chgCData(oldp+2116,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_opn),4); - bufp->chgBit(oldp+2117,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)); - bufp->chgCData(oldp+2118,((0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))),5); - bufp->chgCData(oldp+2119,((0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))),5); - bufp->chgCData(oldp+2120,((0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R))),5); - bufp->chgCData(oldp+2121,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA),5); - bufp->chgCData(oldp+2122,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB),5); - bufp->chgBit(oldp+2123,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U)))); - bufp->chgBit(oldp+2124,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U)))); - bufp->chgBit(oldp+2125,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 5U)))); - bufp->chgBit(oldp+2126,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 5U)))); - bufp->chgBit(oldp+2127,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R) - >> 6U)))); - bufp->chgBit(oldp+2128,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R) - >> 5U)))); - bufp->chgCData(oldp+2129,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F),4); - bufp->chgBit(oldp+2130,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wR)); - bufp->chgBit(oldp+2131,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA)); - bufp->chgBit(oldp+2132,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB)); - bufp->chgBit(oldp+2133,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ALU)); - bufp->chgBit(oldp+2134,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_M)); - bufp->chgBit(oldp+2135,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_DIV)); - bufp->chgBit(oldp+2136,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_FP)); - bufp->chgBit(oldp+2137,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wF)); - bufp->chgBit(oldp+2138,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_break)); - bufp->chgBit(oldp+2139,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_lock)); - bufp->chgBit(oldp+2140,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe)); - bufp->chgBit(oldp+2141,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp)); - bufp->chgBit(oldp+2142,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid)); - bufp->chgIData(oldp+2143,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I),32); - bufp->chgBit(oldp+2144,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI)); - bufp->chgBit(oldp+2145,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal)); - bufp->chgBit(oldp+2146,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)); - bufp->chgBit(oldp+2147,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb)); - bufp->chgIData(oldp+2148,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc),28); - bufp->chgBit(oldp+2149,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall)); - bufp->chgBit(oldp+2150,((1U >= (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))); - bufp->chgBit(oldp+2151,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)); - bufp->chgBit(oldp+2152,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write)); - bufp->chgBit(oldp+2153,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem)); - bufp->chgBit(oldp+2154,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu)); - bufp->chgBit(oldp+2155,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div)); - bufp->chgBit(oldp+2156,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_fpu)); - bufp->chgCData(oldp+2157,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn),4); - bufp->chgBit(oldp+2158,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_Rcc)); - bufp->chgCData(oldp+2159,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Aid),5); - bufp->chgCData(oldp+2160,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid),5); - bufp->chgBit(oldp+2161,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rA)); - bufp->chgBit(oldp+2162,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB)); - bufp->chgIData(oldp+2163,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av),32); - bufp->chgIData(oldp+2164,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv),32); - bufp->chgIData(oldp+2165,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc),28); - bufp->chgIData(oldp+2166,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av),32); - bufp->chgIData(oldp+2167,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv),32); - bufp->chgIData(oldp+2168,(((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv - : (0xeb800000U - | ((0x7f0000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv) - | ((0x10U - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags))))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - : 0U))),32); - bufp->chgBit(oldp+2169,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR)); - bufp->chgBit(oldp+2170,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_wF)); - bufp->chgCData(oldp+2171,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0))),4); - bufp->chgCData(oldp+2172,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F),7); - bufp->chgCData(oldp+2173,(((0x80U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F) - << 4U)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F))),8); - bufp->chgBit(oldp+2174,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase)); - bufp->chgBit(oldp+2175,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe)); - bufp->chgBit(oldp+2176,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break)); - bufp->chgBit(oldp+2177,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_valid)); - bufp->chgBit(oldp+2178,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal)); - bufp->chgBit(oldp+2179,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock)); - bufp->chgIData(oldp+2180,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc),28); - bufp->chgCData(oldp+2181,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg),5); - bufp->chgBit(oldp+2182,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid)); - bufp->chgBit(oldp+2183,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid)); - bufp->chgBit(oldp+2184,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid)); - bufp->chgBit(oldp+2185,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)); - bufp->chgIData(oldp+2186,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result),32); - bufp->chgCData(oldp+2187,(((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)) - << 3U) | ((4U & - ((4U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - >> 0x1dU)) - ^ ( - ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)) - << 2U))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c) - << 1U) - | (0U - == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result))))),4); - bufp->chgBit(oldp+2188,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid)); - bufp->chgBit(oldp+2189,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)); - bufp->chgBit(oldp+2190,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond)); - bufp->chgBit(oldp+2191,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR)); - bufp->chgBit(oldp+2192,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF)); - bufp->chgBit(oldp+2193,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal)); - bufp->chgBit(oldp+2194,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error)); - bufp->chgBit(oldp+2195,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy)); - bufp->chgBit(oldp+2196,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid)); - bufp->chgIData(oldp+2197,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result),32); - bufp->chgCData(oldp+2198,(((4U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - >> 0x1dU)) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z)))),4); - bufp->chgBit(oldp+2199,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv)); - bufp->chgBit(oldp+2200,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe)); - bufp->chgIData(oldp+2201,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_val),32); - bufp->chgIData(oldp+2202,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc),32); - bufp->chgBit(oldp+2203,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_dbg_stall)); - bufp->chgBit(oldp+2204,((0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))))); - bufp->chgBit(oldp+2205,((0xeU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))))); - bufp->chgBit(oldp+2206,((0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))); - bufp->chgBit(oldp+2207,((0x1eU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))); - bufp->chgBit(oldp+2208,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)); - bufp->chgBit(oldp+2209,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce)); - bufp->chgCData(oldp+2210,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags),4); - bufp->chgCData(oldp+2211,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index),3); - bufp->chgCData(oldp+2212,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id),5); - bufp->chgIData(oldp+2213,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl),32); - bufp->chgIData(oldp+2214,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl),32); - bufp->chgBit(oldp+2215,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt)); - bufp->chgBit(oldp+2216,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt)); - bufp->chgIData(oldp+2217,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc),28); - bufp->chgIData(oldp+2218,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc),28); - bufp->chgBit(oldp+2219,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__last_write_to_cc)); - bufp->chgBit(oldp+2220,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__last_write_to_cc)))); - bufp->chgCData(oldp+2221,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R),7); - bufp->chgCData(oldp+2222,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A),7); - bufp->chgCData(oldp+2223,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B),7); - bufp->chgCData(oldp+2224,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc),2); - bufp->chgBit(oldp+2225,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim)); - bufp->chgIData(oldp+2226,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim_immv),23); - bufp->chgCData(oldp+2227,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__regid),5); - bufp->chgCData(oldp+2228,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock),2); - bufp->chgBit(oldp+2229,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset)); - bufp->chgBit(oldp+2230,((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)))); - bufp->chgBit(oldp+2231,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy)); - bufp->chgIData(oldp+2232,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor),32); - bufp->chgQData(oldp+2233,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend),63); - bufp->chgQData(oldp+2235,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff),33); - bufp->chgBit(oldp+2237,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign)); - bufp->chgBit(oldp+2238,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign)); - bufp->chgBit(oldp+2239,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z)); - bufp->chgBit(oldp+2240,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c)); - bufp->chgBit(oldp+2241,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit)); - bufp->chgCData(oldp+2242,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_bit),5); - bufp->chgBit(oldp+2243,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor)); - bufp->chgBit(oldp+2244,((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - >> 0x1fU))); - bufp->chgBit(oldp+2245,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt)); - bufp->chgBit(oldp+2246,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_stb)); - bufp->chgIData(oldp+2247,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_addr),28); - bufp->chgIData(oldp+2248,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks),32); - bufp->chgBit(oldp+2249,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim)); - bufp->chgIData(oldp+2250,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim_immv),23); - bufp->chgIData(oldp+2251,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset - [(0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))]),32); - bufp->chgIData(oldp+2252,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_brev_result),32); - bufp->chgBit(oldp+2253,((0U == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result))); - bufp->chgBit(oldp+2254,((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - >> 0x1fU))); - bufp->chgBit(oldp+2255,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)))); - bufp->chgBit(oldp+2256,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)))); - bufp->chgBit(oldp+2257,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c)); - bufp->chgBit(oldp+2258,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__pre_sign)); - bufp->chgBit(oldp+2259,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl)); - bufp->chgBit(oldp+2260,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl)); - bufp->chgQData(oldp+2261,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result),33); - bufp->chgQData(oldp+2263,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_asr_result),33); - bufp->chgQData(oldp+2265,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result),33); - bufp->chgQData(oldp+2267,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result),64); - bufp->chgBit(oldp+2269,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_hi)); - bufp->chgBit(oldp+2270,((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe)))); - bufp->chgBit(oldp+2271,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe) - >> 1U)))); - bufp->chgQData(oldp+2272,(((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - << 1U)),33); - bufp->chgQData(oldp+2274,((0x1ffffffffULL & - VL_SHIFTRS_QQI(33,33,5, - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - << 1U), - (0x1fU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)))),33); - bufp->chgCData(oldp+2276,((3U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))),2); - bufp->chgQData(oldp+2277,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_smpy_result),64); - bufp->chgQData(oldp+2279,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_umpy_result),64); - bufp->chgIData(oldp+2281,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input),32); - bufp->chgIData(oldp+2282,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input),32); - bufp->chgCData(oldp+2283,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe),2); - bufp->chgCData(oldp+2284,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_sgn),2); - bufp->chgQData(oldp+2285,((((QData)((IData)( - (- (IData)( - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input - >> 0x1fU))))) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input)))),64); - bufp->chgQData(oldp+2287,((((QData)((IData)( - (- (IData)( - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input - >> 0x1fU))))) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input)))),64); - bufp->chgQData(oldp+2289,((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input))),64); - bufp->chgQData(oldp+2291,((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input))),64); - bufp->chgBit(oldp+2293,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset)); - bufp->chgCData(oldp+2294,((0x1fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x16U))),5); - bufp->chgBit(oldp+2295,((0xcU == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))); - bufp->chgBit(oldp+2296,((0xdU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))); - bufp->chgBit(oldp+2297,((8U == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))); - bufp->chgBit(oldp+2298,((9U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))); - bufp->chgBit(oldp+2299,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU)); - bufp->chgBit(oldp+2300,((8U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))); - bufp->chgBit(oldp+2301,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_noop)); - bufp->chgBit(oldp+2302,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_lock)); - bufp->chgBit(oldp+2303,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - & (0x7800000U == (0x7c00000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))))); - bufp->chgBit(oldp+2304,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - & (0x7000000U == (0x7c00000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))))); - bufp->chgBit(oldp+2305,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special)); - bufp->chgBit(oldp+2306,((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))); - bufp->chgBit(oldp+2307,(((5U == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))) - | (0xcU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op))))); - bufp->chgBit(oldp+2308,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_pc)); - bufp->chgBit(oldp+2309,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_cc)); - bufp->chgBit(oldp+2310,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB) - & (0xfU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0))))); - bufp->chgBit(oldp+2311,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB) - & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0))))); - bufp->chgCData(oldp+2312,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h9ed30f6d__0) - ? 8U : (((0U == - (7U & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x13U))) - << 3U) - | (7U & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x13U))))),4); - bufp->chgBit(oldp+2313,(((8U == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h9ed30f6d__0) - | (0U == (7U & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x13U)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_he52a0fcf__0) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU) - & ((0xdU - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - & ((9U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - & ((8U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - & (7U - != - (7U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1cU)))))))))))); - bufp->chgBit(oldp+2314,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem)); - bufp->chgBit(oldp+2315,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto)); - bufp->chgBit(oldp+2316,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div)); - bufp->chgBit(oldp+2317,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_fpu)); - bufp->chgBit(oldp+2318,((1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - | (8U - == - (0xfU - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))))))); - bufp->chgBit(oldp+2319,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_he52a0fcf__0) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU) - & ((8U != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - & (0xdU != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto) - | (8U == (0xfU - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U)))))))); - bufp->chgBit(oldp+2320,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB)); - bufp->chgBit(oldp+2321,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - | (8U == (0xfU - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))))); - bufp->chgBit(oldp+2322,((0x7c87c000U == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - bufp->chgBit(oldp+2323,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_ljmp)); - bufp->chgIData(oldp+2324,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword),32); - bufp->chgBit(oldp+2325,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid)); - bufp->chgSData(oldp+2326,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_nxt_half),15); - bufp->chgCData(oldp+2327,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op),5); - bufp->chgIData(oldp+2328,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I),23); - bufp->chgIData(oldp+2329,((0x7fffffU & ((2U - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? - ((0x7fc000U - & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xdU)))) - << 0xeU)) - | (0x3fffU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - : - ((0x7c0000U - & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x11U)))) - << 0x12U)) - | (0x3ffffU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))) - : - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? - ((0x7fe000U - & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xcU)))) - << 0xdU)) - | (0x1fffU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)))),23); - bufp->chgIData(oldp+2330,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I),23); - bufp->chgBit(oldp+2331,((0U == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I))); - bufp->chgCData(oldp+2332,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc),2); - bufp->chgBit(oldp+2333,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable)); - bufp->chgCData(oldp+2334,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI),8); - bufp->chgCData(oldp+2335,((0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x10U))),8); - bufp->chgBit(oldp+2336,(((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)) - & (IData)((0x78800000U - == (0xfffc0000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU])))))); - bufp->chgBit(oldp+2337,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_jiffies__i_wb_stb)); - bufp->chgBit(oldp+2338,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_set)); - bufp->chgBit(oldp+2339,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_set)); - bufp->chgBit(oldp+2340,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_now)); - bufp->chgIData(oldp+2341,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_when),32); - bufp->chgIData(oldp+2342,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_when),32); - bufp->chgIData(oldp+2343,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_wb),32); - bufp->chgIData(oldp+2344,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_when),32); - bufp->chgBit(oldp+2345,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_a__i_wb_stb)); - bufp->chgBit(oldp+2346,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_running)); - bufp->chgBit(oldp+2347,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_zero)); - bufp->chgIData(oldp+2348,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value),31); - bufp->chgBit(oldp+2349,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write)); - bufp->chgBit(oldp+2350,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload)); - bufp->chgIData(oldp+2351,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_interval_count),31); - bufp->chgBit(oldp+2352,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_b__i_wb_stb)); - bufp->chgBit(oldp+2353,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running)); - bufp->chgBit(oldp+2354,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero)); - bufp->chgIData(oldp+2355,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value),31); - bufp->chgBit(oldp+2356,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write)); - bufp->chgBit(oldp+2357,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload)); - bufp->chgIData(oldp+2358,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_interval_count),31); - bufp->chgBit(oldp+2359,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_c__i_wb_stb)); - bufp->chgBit(oldp+2360,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running)); - bufp->chgBit(oldp+2361,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero)); - bufp->chgIData(oldp+2362,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value),31); - bufp->chgBit(oldp+2363,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write)); - bufp->chgBit(oldp+2364,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload)); - bufp->chgIData(oldp+2365,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_interval_count),31); - bufp->chgBit(oldp+2366,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchbus____pinNumber2)); - bufp->chgSData(oldp+2367,(vlSelf->main__DOT__swic__DOT__u_watchbus__DOT__r_value),14); - bufp->chgBit(oldp+2368,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchdog__i_wb_stb)); - bufp->chgBit(oldp+2369,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running)); - bufp->chgBit(oldp+2370,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_zero)); - bufp->chgIData(oldp+2371,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value),31); - bufp->chgBit(oldp+2372,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__wb_write)); - bufp->chgCData(oldp+2373,(vlSelf->main__DOT__txv__DOT__baud_counter),7); - bufp->chgCData(oldp+2374,(vlSelf->main__DOT__txv__DOT__state),4); - bufp->chgCData(oldp+2375,(vlSelf->main__DOT__txv__DOT__lcl_data),8); - bufp->chgBit(oldp+2376,(vlSelf->main__DOT__txv__DOT__zero_baud_counter)); - bufp->chgBit(oldp+2377,(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)); - bufp->chgCData(oldp+2378,(vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift),5); - bufp->chgCData(oldp+2379,(vlSelf->main__DOT__u_emmc__DOT__sdclk),8); - bufp->chgBit(oldp+2380,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)); - bufp->chgBit(oldp+2381,(vlSelf->main__DOT__u_emmc__DOT__pp_cmd)); - bufp->chgCData(oldp+2382,((3U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2eU)))),2); - bufp->chgBit(oldp+2383,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)); - bufp->chgBit(oldp+2384,(vlSelf->main__DOT__u_emmc__DOT__pp_data)); - bufp->chgBit(oldp+2385,(vlSelf->main__DOT__u_emmc__DOT__rx_en)); - bufp->chgIData(oldp+2386,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data),32); - bufp->chgBit(oldp+2387,(((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds)))); - bufp->chgCData(oldp+2388,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) - << 1U)),2); - bufp->chgCData(oldp+2389,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data) - << 1U)),2); - bufp->chgBit(oldp+2390,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy)); - bufp->chgCData(oldp+2391,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U)),2); - bufp->chgSData(oldp+2392,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - << 8U)),16); - bufp->chgBit(oldp+2393,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy)); - bufp->chgBit(oldp+2394,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge)); - bufp->chgBit(oldp+2395,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge)); - bufp->chgBit(oldp+2396,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__resp_started)); - bufp->chgBit(oldp+2397,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__io_started)); - bufp->chgBit(oldp+2398,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck)); - bufp->chgBit(oldp+2399,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data)); - bufp->chgBit(oldp+2400,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb)); - bufp->chgBit(oldp+2401,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb)); - bufp->chgCData(oldp+2402,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data),8); - bufp->chgCData(oldp+2403,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg),2); - bufp->chgCData(oldp+2404,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg),2); - bufp->chgBit(oldp+2405,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck)); - bufp->chgBit(oldp+2406,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck)); - bufp->chgBit(oldp+2407,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset)); - bufp->chgBit(oldp+2408,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90)); - bufp->chgBit(oldp+2409,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown)); - bufp->chgBit(oldp+2410,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds)); - bufp->chgCData(oldp+2411,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed),8); - bufp->chgCData(oldp+2412,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width),2); - bufp->chgBit(oldp+2413,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb)); - bufp->chgBit(oldp+2414,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_half)); - bufp->chgCData(oldp+2415,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__w_sdclk),8); - bufp->chgCData(oldp+2416,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_ckspd),8); - bufp->chgBit(oldp+2417,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request)); - bufp->chgBit(oldp+2418,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err)); - bufp->chgBit(oldp+2419,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)); - bufp->chgBit(oldp+2420,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done)); - bufp->chgCData(oldp+2421,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type),2); - bufp->chgCData(oldp+2422,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode),2); - bufp->chgBit(oldp+2423,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb)); - bufp->chgCData(oldp+2424,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd),7); - bufp->chgCData(oldp+2425,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_id),6); - bufp->chgIData(oldp+2426,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg),32); - bufp->chgIData(oldp+2427,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_arg),32); - bufp->chgBit(oldp+2428,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid)); - bufp->chgSData(oldp+2429,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr),10); - bufp->chgIData(oldp+2430,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_data),32); - bufp->chgBit(oldp+2431,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)); - bufp->chgBit(oldp+2432,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)); - bufp->chgBit(oldp+2433,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready)); - bufp->chgBit(oldp+2434,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last)); - bufp->chgIData(oldp+2435,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data),32); - bufp->chgSData(oldp+2436,((0x1fffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk)))),13); - bufp->chgBit(oldp+2437,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid)); - bufp->chgSData(oldp+2438,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr),10); - bufp->chgCData(oldp+2439,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb),4); - bufp->chgIData(oldp+2440,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data),32); - bufp->chgBit(oldp+2441,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done)); - bufp->chgBit(oldp+2442,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_err)); - bufp->chgBit(oldp+2443,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb)); - bufp->chgBit(oldp+2444,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk)); - bufp->chgSData(oldp+2445,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter),10); - bufp->chgSData(oldp+2446,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter),10); - bufp->chgBit(oldp+2447,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__clk90)); - bufp->chgCData(oldp+2448,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd),8); - bufp->chgBit(oldp+2449,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90)); - bufp->chgCData(oldp+2450,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd),8); - bufp->chgBit(oldp+2451,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)); - bufp->chgBit(oldp+2452,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)); - bufp->chgBit(oldp+2453,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)); - bufp->chgBit(oldp+2454,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent)); - bufp->chgBit(oldp+2455,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)); - bufp->chgBit(oldp+2456,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err)); - bufp->chgCData(oldp+2457,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode),2); - bufp->chgCData(oldp+2458,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk),4); - bufp->chgIData(oldp+2459,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word),32); - bufp->chgIData(oldp+2460,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl),32); - bufp->chgSData(oldp+2461,((0xffffU & (((0xfU - >= - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? ((IData)(1U) - << - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - - (IData)(1U)))),16); - bufp->chgIData(oldp+2462,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ika),32); - bufp->chgIData(oldp+2463,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ikb),32); - bufp->chgIData(oldp+2464,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a),32); - bufp->chgIData(oldp+2465,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b),32); - bufp->chgSData(oldp+2466,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr),10); - bufp->chgSData(oldp+2467,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr),10); - bufp->chgSData(oldp+2468,((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)) - ? (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))),10); - bufp->chgSData(oldp+2469,((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - ? (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))),10); - bufp->chgSData(oldp+2470,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr),10); - bufp->chgIData(oldp+2471,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - ? vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b - : vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a)),32); - bufp->chgBit(oldp+2472,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last)); - bufp->chgBit(oldp+2473,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - >= (0xffffU & ( - ((0xfU - >= - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? - ((IData)(1U) - << - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - - (IData)(1U))))))); - bufp->chgBit(oldp+2474,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid)); - bufp->chgBit(oldp+2475,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_ack)); - bufp->chgCData(oldp+2476,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel),2); - bufp->chgIData(oldp+2477,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data),32); - bufp->chgSData(oldp+2478,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a),10); - bufp->chgSData(oldp+2479,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b),10); - bufp->chgCData(oldp+2480,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a),4); - bufp->chgCData(oldp+2481,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b),4); - bufp->chgIData(oldp+2482,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a),32); - bufp->chgIData(oldp+2483,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b),32); - bufp->chgBit(oldp+2484,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)); - bufp->chgCData(oldp+2485,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill),5); - bufp->chgIData(oldp+2486,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg),20); - bufp->chgBit(oldp+2487,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid)); - bufp->chgCData(oldp+2488,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill),2); - bufp->chgSData(oldp+2489,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data),16); - bufp->chgBit(oldp+2490,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)); - bufp->chgBit(oldp+2491,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb)); - bufp->chgCData(oldp+2492,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr),2); - bufp->chgCData(oldp+2493,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr),2); - bufp->chgCData(oldp+2494,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data),8); - bufp->chgBit(oldp+2495,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy)); - bufp->chgBit(oldp+2496,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)); - bufp->chgBit(oldp+2497,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)); - bufp->chgBit(oldp+2498,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc)); - bufp->chgSData(oldp+2499,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count),16); - bufp->chgCData(oldp+2500,(((0x80U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err) - << 6U)) - | ((0x40U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err) - << 5U)) - | ((0x20U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err) - << 4U)) - | ((0x10U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err) - << 3U)) - | ((8U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err) - << 3U)) - | ((4U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err) - << 2U)) - | ((2U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err)))))))))),8); - bufp->chgIData(oldp+2501,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout),23); - bufp->chgBit(oldp+2502,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog)); - bufp->chgBit(oldp+2503,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb)); - bufp->chgBit(oldp+2504,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done)); - bufp->chgSData(oldp+2505,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc),16); - bufp->chgSData(oldp+2506,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc),16); - bufp->chgCData(oldp+2507,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err),2); - bufp->chgSData(oldp+2508,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc),16); - bufp->chgSData(oldp+2509,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc),16); - bufp->chgCData(oldp+2510,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err),2); - bufp->chgSData(oldp+2511,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc),16); - bufp->chgSData(oldp+2512,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc),16); - bufp->chgCData(oldp+2513,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err),2); - bufp->chgSData(oldp+2514,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc),16); - bufp->chgSData(oldp+2515,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc),16); - bufp->chgCData(oldp+2516,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err),2); - bufp->chgBit(oldp+2517,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl)); - bufp->chgCData(oldp+2518,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount),6); - bufp->chgQData(oldp+2519,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg),48); - bufp->chgBit(oldp+2521,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response)); - bufp->chgBit(oldp+2522,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds)); - bufp->chgBit(oldp+2523,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl)); - bufp->chgBit(oldp+2524,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err)); - bufp->chgCData(oldp+2525,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type),2); - bufp->chgCData(oldp+2526,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count),8); - bufp->chgBit(oldp+2527,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - >> 1U) & ( - (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x30U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)))) - | ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x88U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))))))); - bufp->chgBit(oldp+2528,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done)); - bufp->chgBit(oldp+2529,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) - & (9U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill))))); - bufp->chgBit(oldp+2530,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)); - bufp->chgQData(oldp+2531,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg),40); - bufp->chgBit(oldp+2533,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout)); - bufp->chgIData(oldp+2534,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter),26); - bufp->chgCData(oldp+2535,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill),7); - bufp->chgBit(oldp+2536,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy)); - bufp->chgBit(oldp+2537,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data)); - bufp->chgBit(oldp+2538,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)); - bufp->chgBit(oldp+2539,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID)); - bufp->chgBit(oldp+2540,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)); - bufp->chgCData(oldp+2541,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width),2); - bufp->chgCData(oldp+2542,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period),2); - bufp->chgBit(oldp+2543,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet)); - bufp->chgBit(oldp+2544,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid)); - bufp->chgCData(oldp+2545,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate),2); - bufp->chgBit(oldp+2546,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready)); - bufp->chgIData(oldp+2547,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data),32); - bufp->chgCData(oldp+2548,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count),4); - bufp->chgSData(oldp+2549,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg),16); - bufp->chgIData(oldp+2550,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w),32); - bufp->chgIData(oldp+2551,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w),32); - bufp->chgIData(oldp+2552,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w),32); - bufp->chgIData(oldp+2553,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg),32); - bufp->chgQData(oldp+2554,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w),64); - bufp->chgQData(oldp+2556,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w),64); - bufp->chgQData(oldp+2558,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w),64); - bufp->chgQData(oldp+2560,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg),64); - bufp->chgWData(oldp+2562,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w),128); - bufp->chgWData(oldp+2566,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w),128); - bufp->chgWData(oldp+2570,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w),128); - bufp->chgWData(oldp+2574,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg),128); - bufp->chgWData(oldp+2578,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d),256); - bufp->chgWData(oldp+2586,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d),256); - bufp->chgWData(oldp+2594,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d),256); - bufp->chgWData(oldp+2602,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg),256); - bufp->chgCData(oldp+2610,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts),5); - bufp->chgIData(oldp+2611,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg),32); - bufp->chgBit(oldp+2612,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit)); - bufp->chgSData(oldp+2613,(vlSelf->main__DOT__u_fan__DOT__pwm_counter),13); - bufp->chgSData(oldp+2614,(vlSelf->main__DOT__u_fan__DOT__ctl_fpga),13); - bufp->chgSData(oldp+2615,(vlSelf->main__DOT__u_fan__DOT__ctl_sys),13); - bufp->chgBit(oldp+2616,(vlSelf->main__DOT__u_fan__DOT__ck_tach)); - bufp->chgBit(oldp+2617,(vlSelf->main__DOT__u_fan__DOT__last_tach)); - bufp->chgCData(oldp+2618,(vlSelf->main__DOT__u_fan__DOT__pipe_tach),2); - bufp->chgBit(oldp+2619,(vlSelf->main__DOT__u_fan__DOT__tach_reset)); - bufp->chgIData(oldp+2620,(vlSelf->main__DOT__u_fan__DOT__tach_count),27); - bufp->chgIData(oldp+2621,(vlSelf->main__DOT__u_fan__DOT__tach_counter),27); - bufp->chgIData(oldp+2622,(vlSelf->main__DOT__u_fan__DOT__tach_timer),27); - bufp->chgBit(oldp+2623,(vlSelf->main__DOT__u_fan__DOT__i2c_wb_ack)); - bufp->chgIData(oldp+2624,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data),32); - bufp->chgBit(oldp+2625,(vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc)); - bufp->chgBit(oldp+2626,(vlSelf->main__DOT__u_fan__DOT__mem_stb)); - bufp->chgCData(oldp+2627,(vlSelf->main__DOT__u_fan__DOT__mem_addr),5); - bufp->chgCData(oldp+2628,(vlSelf->main__DOT__u_fan__DOT__mem_data),8); - bufp->chgBit(oldp+2629,(vlSelf->main__DOT__u_fan__DOT__mem_ack)); - bufp->chgBit(oldp+2630,(vlSelf->main__DOT__u_fan__DOT__i2cd_valid)); - bufp->chgBit(oldp+2631,(vlSelf->main__DOT__u_fan__DOT__i2cd_last)); - bufp->chgCData(oldp+2632,(vlSelf->main__DOT__u_fan__DOT__i2cd_data),8); - bufp->chgBit(oldp+2633,(vlSelf->main__DOT__u_fan__DOT__pp_ms)); - bufp->chgIData(oldp+2634,(vlSelf->main__DOT__u_fan__DOT__trigger_counter),17); - bufp->chgIData(oldp+2635,(vlSelf->main__DOT__u_fan__DOT__temp_tmp),24); - bufp->chgIData(oldp+2636,(vlSelf->main__DOT__u_fan__DOT__temp_data),32); - bufp->chgBit(oldp+2637,(vlSelf->main__DOT__u_fan__DOT__pre_ack)); - bufp->chgIData(oldp+2638,(vlSelf->main__DOT__u_fan__DOT__pre_data),32); - bufp->chgBit(oldp+2639,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted)); - bufp->chgBit(oldp+2640,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc)); - bufp->chgCData(oldp+2641,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr),5); - bufp->chgBit(oldp+2642,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid)); - bufp->chgBit(oldp+2643,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)); - bufp->chgCData(oldp+2644,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn),8); - bufp->chgCData(oldp+2645,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr),5); - bufp->chgBit(oldp+2646,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal)); - bufp->chgBit(oldp+2647,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid)); - bufp->chgBit(oldp+2648,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle)); - bufp->chgBit(oldp+2649,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready)); - bufp->chgBit(oldp+2650,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready)); - bufp->chgBit(oldp+2651,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort)); - bufp->chgBit(oldp+2652,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid)); - bufp->chgSData(oldp+2653,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn),12); - bufp->chgCData(oldp+2654,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn),4); - bufp->chgBit(oldp+2655,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge)); - bufp->chgBit(oldp+2656,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch)); - bufp->chgSData(oldp+2657,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount),12); - bufp->chgSData(oldp+2658,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount),12); - bufp->chgCData(oldp+2659,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__abort_address),5); - bufp->chgCData(oldp+2660,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__jump_target),5); - bufp->chgBit(oldp+2661,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait)); - bufp->chgBit(oldp+2662,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request)); - bufp->chgBit(oldp+2663,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err)); - bufp->chgBit(oldp+2664,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted)); - bufp->chgBit(oldp+2665,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual)); - bufp->chgBit(oldp+2666,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda)); - bufp->chgBit(oldp+2667,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl)); - bufp->chgBit(oldp+2668,(((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait)))); - bufp->chgBit(oldp+2669,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda)); - bufp->chgBit(oldp+2670,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl)); - bufp->chgBit(oldp+2671,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_ready)); - bufp->chgBit(oldp+2672,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid)); - bufp->chgSData(oldp+2673,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data),10); - bufp->chgBit(oldp+2674,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl)); - bufp->chgBit(oldp+2675,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda)); - bufp->chgSData(oldp+2676,((0x7ffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))),11); - bufp->chgBit(oldp+2677,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte)); - bufp->chgBit(oldp+2678,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir)); - bufp->chgBit(oldp+2679,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack)); - bufp->chgCData(oldp+2680,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state),4); - bufp->chgCData(oldp+2681,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits),3); - bufp->chgCData(oldp+2682,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg),8); - bufp->chgBit(oldp+2683,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_scl)); - bufp->chgBit(oldp+2684,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_sda)); - bufp->chgBit(oldp+2685,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)); - bufp->chgBit(oldp+2686,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda)); - bufp->chgBit(oldp+2687,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_scl)); - bufp->chgBit(oldp+2688,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_sda)); - bufp->chgBit(oldp+2689,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__stop_bit)); - bufp->chgBit(oldp+2690,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy)); - bufp->chgBit(oldp+2691,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__last_stb)); - bufp->chgBit(oldp+2692,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle)); - bufp->chgCData(oldp+2693,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_word),8); - bufp->chgBit(oldp+2694,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid)); - bufp->chgCData(oldp+2695,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight),2); - bufp->chgBit(oldp+2696,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_illegal)); - bufp->chgBit(oldp+2697,(vlSelf->main__DOT____Vcellinp__u_i2cdma__S_VALID)); - bufp->chgIData(oldp+2698,(vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr),28); - bufp->chgIData(oldp+2699,(vlSelf->main__DOT__u_i2cdma__DOT__r_memlen),28); - bufp->chgCData(oldp+2700,(vlSelf->main__DOT__u_i2cdma__DOT__subaddr),6); - bufp->chgIData(oldp+2701,(vlSelf->main__DOT__u_i2cdma__DOT__current_addr),28); - bufp->chgBit(oldp+2702,(vlSelf->main__DOT__u_i2cdma__DOT__wb_last)); - bufp->chgBit(oldp+2703,(vlSelf->main__DOT__u_i2cdma__DOT__bus_err)); - bufp->chgBit(oldp+2704,(vlSelf->main__DOT__u_i2cdma__DOT__r_reset)); - bufp->chgBit(oldp+2705,(vlSelf->main__DOT__u_i2cdma__DOT__r_overflow)); - bufp->chgBit(oldp+2706,(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid)); - bufp->chgBit(oldp+2707,(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready)); - bufp->chgBit(oldp+2708,((1U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - >> 8U)))); - bufp->chgCData(oldp+2709,((0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))),8); - bufp->chgSData(oldp+2710,(vlSelf->main__DOT__u_i2cdma__DOT____Vcellinp__sskd__i_data),9); - bufp->chgSData(oldp+2711,(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data),9); - bufp->chgSData(oldp+2712,(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_data),9); - bufp->chgBit(oldp+2713,(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid)); - bufp->chgBit(oldp+2714,(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)); - bufp->chgCData(oldp+2715,(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift),5); - bufp->chgCData(oldp+2716,(vlSelf->main__DOT__u_sdcard__DOT__sdclk),8); - bufp->chgBit(oldp+2717,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active)); - bufp->chgBit(oldp+2718,(vlSelf->main__DOT__u_sdcard__DOT__pp_cmd)); - bufp->chgCData(oldp+2719,((3U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2eU)))),2); - bufp->chgBit(oldp+2720,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)); - bufp->chgBit(oldp+2721,(vlSelf->main__DOT__u_sdcard__DOT__pp_data)); - bufp->chgBit(oldp+2722,(vlSelf->main__DOT__u_sdcard__DOT__rx_en)); - bufp->chgIData(oldp+2723,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data),32); - bufp->chgBit(oldp+2724,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds)))); - bufp->chgCData(oldp+2725,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) - << 1U)),2); - bufp->chgCData(oldp+2726,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data) - << 1U)),2); - bufp->chgBit(oldp+2727,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy)); - bufp->chgCData(oldp+2728,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U)),2); - bufp->chgSData(oldp+2729,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - << 8U)),16); - bufp->chgBit(oldp+2730,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy)); - bufp->chgCData(oldp+2731,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->chgBit(oldp+2732,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0])); - bufp->chgBit(oldp+2733,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[1])); - bufp->chgBit(oldp+2734,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[2])); - bufp->chgBit(oldp+2735,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[3])); - bufp->chgBit(oldp+2736,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[4])); - bufp->chgBit(oldp+2737,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[5])); - bufp->chgBit(oldp+2738,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[6])); - bufp->chgBit(oldp+2739,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[7])); - bufp->chgBit(oldp+2740,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[8])); - bufp->chgBit(oldp+2741,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[9])); - bufp->chgBit(oldp+2742,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[10])); - bufp->chgBit(oldp+2743,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[11])); - bufp->chgBit(oldp+2744,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[12])); - bufp->chgBit(oldp+2745,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[13])); - bufp->chgBit(oldp+2746,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[14])); - bufp->chgBit(oldp+2747,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[15])); - bufp->chgSData(oldp+2748,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat),16); - bufp->chgCData(oldp+2749,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge),2); - bufp->chgCData(oldp+2750,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge),2); - bufp->chgCData(oldp+2751,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg),6); - bufp->chgCData(oldp+2752,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pck_sreg),6); - bufp->chgCData(oldp+2753,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck),2); - bufp->chgCData(oldp+2754,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck),2); - bufp->chgBit(oldp+2755,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__resp_started)); - bufp->chgBit(oldp+2756,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__io_started)); - bufp->chgBit(oldp+2757,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck)); - bufp->chgBit(oldp+2758,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb)); - bufp->chgBit(oldp+2759,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data)); - bufp->chgBit(oldp+2760,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb)); - bufp->chgCData(oldp+2761,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data),8); - bufp->chgBit(oldp+2762,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__high_z)); - bufp->chgCData(oldp+2763,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out),8); - bufp->chgBit(oldp+2764,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z)); - bufp->chgCData(oldp+2765,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->chgCData(oldp+2766,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out),2); - bufp->chgBit(oldp+2767,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->chgBit(oldp+2768,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z)); - bufp->chgCData(oldp+2769,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->chgCData(oldp+2770,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out),2); - bufp->chgBit(oldp+2771,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->chgBit(oldp+2772,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z)); - bufp->chgCData(oldp+2773,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->chgCData(oldp+2774,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out),2); - bufp->chgBit(oldp+2775,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->chgBit(oldp+2776,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z)); - bufp->chgCData(oldp+2777,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->chgCData(oldp+2778,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out),2); - bufp->chgBit(oldp+2779,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->chgCData(oldp+2780,(((2U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 6U)) | - (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 3U)))),2); - bufp->chgCData(oldp+2781,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out),2); - bufp->chgBit(oldp+2782,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z)); - bufp->chgCData(oldp+2783,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out),2); - bufp->chgBit(oldp+2784,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->chgBit(oldp+2785,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset)); - bufp->chgBit(oldp+2786,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90)); - bufp->chgBit(oldp+2787,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown)); - bufp->chgBit(oldp+2788,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds)); - bufp->chgCData(oldp+2789,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed),8); - bufp->chgCData(oldp+2790,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width),2); - bufp->chgBit(oldp+2791,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb)); - bufp->chgBit(oldp+2792,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half)); - bufp->chgCData(oldp+2793,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk),8); - bufp->chgCData(oldp+2794,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_ckspd),8); - bufp->chgBit(oldp+2795,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request)); - bufp->chgBit(oldp+2796,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err)); - bufp->chgBit(oldp+2797,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)); - bufp->chgBit(oldp+2798,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done)); - bufp->chgCData(oldp+2799,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type),2); - bufp->chgCData(oldp+2800,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode),2); - bufp->chgBit(oldp+2801,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb)); - bufp->chgCData(oldp+2802,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd),7); - bufp->chgCData(oldp+2803,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id),6); - bufp->chgIData(oldp+2804,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg),32); - bufp->chgIData(oldp+2805,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg),32); - bufp->chgBit(oldp+2806,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid)); - bufp->chgSData(oldp+2807,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr),10); - bufp->chgIData(oldp+2808,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_data),32); - bufp->chgBit(oldp+2809,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)); - bufp->chgBit(oldp+2810,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)); - bufp->chgBit(oldp+2811,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready)); - bufp->chgBit(oldp+2812,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last)); - bufp->chgIData(oldp+2813,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data),32); - bufp->chgSData(oldp+2814,((0x1fffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk)))),13); - bufp->chgBit(oldp+2815,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid)); - bufp->chgSData(oldp+2816,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr),10); - bufp->chgCData(oldp+2817,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb),4); - bufp->chgIData(oldp+2818,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data),32); - bufp->chgBit(oldp+2819,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done)); - bufp->chgBit(oldp+2820,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err)); - bufp->chgBit(oldp+2821,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb)); - bufp->chgBit(oldp+2822,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk)); - bufp->chgSData(oldp+2823,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter),10); - bufp->chgSData(oldp+2824,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter),10); - bufp->chgBit(oldp+2825,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__clk90)); - bufp->chgCData(oldp+2826,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd),8); - bufp->chgBit(oldp+2827,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90)); - bufp->chgCData(oldp+2828,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd),8); - bufp->chgBit(oldp+2829,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)); - bufp->chgBit(oldp+2830,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)); - bufp->chgBit(oldp+2831,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)); - bufp->chgBit(oldp+2832,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent)); - bufp->chgBit(oldp+2833,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)); - bufp->chgBit(oldp+2834,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err)); - bufp->chgCData(oldp+2835,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode),2); - bufp->chgCData(oldp+2836,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk),4); - bufp->chgIData(oldp+2837,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word),32); - bufp->chgIData(oldp+2838,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl),32); - bufp->chgSData(oldp+2839,((0xffffU & (((0xfU - >= - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? ((IData)(1U) - << - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - - (IData)(1U)))),16); - bufp->chgIData(oldp+2840,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ika),32); - bufp->chgIData(oldp+2841,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ikb),32); - bufp->chgIData(oldp+2842,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a),32); - bufp->chgIData(oldp+2843,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b),32); - bufp->chgSData(oldp+2844,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr),10); - bufp->chgSData(oldp+2845,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr),10); - bufp->chgSData(oldp+2846,((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)) - ? (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))),10); - bufp->chgSData(oldp+2847,((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - ? (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))),10); - bufp->chgSData(oldp+2848,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr),10); - bufp->chgIData(oldp+2849,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - ? vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b - : vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a)),32); - bufp->chgBit(oldp+2850,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last)); - bufp->chgBit(oldp+2851,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - >= (0xffffU & ( - ((0xfU - >= - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? - ((IData)(1U) - << - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - - (IData)(1U))))))); - bufp->chgBit(oldp+2852,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid)); - bufp->chgBit(oldp+2853,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present)); - bufp->chgBit(oldp+2854,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_removed)); - bufp->chgBit(oldp+2855,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_ack)); - bufp->chgCData(oldp+2856,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel),2); - bufp->chgIData(oldp+2857,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data),32); - bufp->chgSData(oldp+2858,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a),10); - bufp->chgSData(oldp+2859,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b),10); - bufp->chgCData(oldp+2860,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a),4); - bufp->chgCData(oldp+2861,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b),4); - bufp->chgIData(oldp+2862,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a),32); - bufp->chgIData(oldp+2863,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b),32); - bufp->chgBit(oldp+2864,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)); - bufp->chgCData(oldp+2865,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present),3); - bufp->chgSData(oldp+2866,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter),10); - bufp->chgCData(oldp+2867,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill),5); - bufp->chgIData(oldp+2868,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg),20); - bufp->chgBit(oldp+2869,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid)); - bufp->chgCData(oldp+2870,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill),2); - bufp->chgSData(oldp+2871,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data),16); - bufp->chgBit(oldp+2872,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)); - bufp->chgBit(oldp+2873,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb)); - bufp->chgCData(oldp+2874,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr),2); - bufp->chgCData(oldp+2875,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr),2); - bufp->chgCData(oldp+2876,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data),8); - bufp->chgBit(oldp+2877,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy)); - bufp->chgBit(oldp+2878,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)); - bufp->chgBit(oldp+2879,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)); - bufp->chgBit(oldp+2880,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc)); - bufp->chgSData(oldp+2881,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count),16); - bufp->chgCData(oldp+2882,(((0x80U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err) - << 6U)) - | ((0x40U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err) - << 5U)) - | ((0x20U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err) - << 4U)) - | ((0x10U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err) - << 3U)) - | ((8U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err) - << 3U)) - | ((4U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err) - << 2U)) - | ((2U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err)))))))))),8); - bufp->chgIData(oldp+2883,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout),23); - bufp->chgBit(oldp+2884,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog)); - bufp->chgBit(oldp+2885,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb)); - bufp->chgBit(oldp+2886,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done)); - bufp->chgSData(oldp+2887,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc),16); - bufp->chgSData(oldp+2888,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc),16); - bufp->chgCData(oldp+2889,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err),2); - bufp->chgSData(oldp+2890,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc),16); - bufp->chgSData(oldp+2891,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc),16); - bufp->chgCData(oldp+2892,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err),2); - bufp->chgSData(oldp+2893,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc),16); - bufp->chgSData(oldp+2894,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc),16); - bufp->chgCData(oldp+2895,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err),2); - bufp->chgSData(oldp+2896,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc),16); - bufp->chgSData(oldp+2897,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc),16); - bufp->chgCData(oldp+2898,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err),2); - bufp->chgBit(oldp+2899,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl)); - bufp->chgCData(oldp+2900,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount),6); - bufp->chgQData(oldp+2901,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg),48); - bufp->chgBit(oldp+2903,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response)); - bufp->chgBit(oldp+2904,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds)); - bufp->chgBit(oldp+2905,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl)); - bufp->chgBit(oldp+2906,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err)); - bufp->chgCData(oldp+2907,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type),2); - bufp->chgCData(oldp+2908,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count),8); - bufp->chgBit(oldp+2909,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - >> 1U) & ( - (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x30U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)))) - | ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x88U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))))))); - bufp->chgBit(oldp+2910,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done)); - bufp->chgBit(oldp+2911,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) - & (9U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill))))); - bufp->chgBit(oldp+2912,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)); - bufp->chgQData(oldp+2913,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg),40); - bufp->chgBit(oldp+2915,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout)); - bufp->chgIData(oldp+2916,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter),26); - bufp->chgCData(oldp+2917,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill),7); - bufp->chgBit(oldp+2918,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy)); - bufp->chgBit(oldp+2919,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data)); - bufp->chgBit(oldp+2920,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)); - bufp->chgBit(oldp+2921,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID)); - bufp->chgBit(oldp+2922,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)); - bufp->chgCData(oldp+2923,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width),2); - bufp->chgCData(oldp+2924,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period),2); - bufp->chgBit(oldp+2925,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet)); - bufp->chgBit(oldp+2926,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid)); - bufp->chgCData(oldp+2927,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate),2); - bufp->chgBit(oldp+2928,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready)); - bufp->chgIData(oldp+2929,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data),32); - bufp->chgCData(oldp+2930,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count),4); - bufp->chgSData(oldp+2931,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg),16); - bufp->chgIData(oldp+2932,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w),32); - bufp->chgIData(oldp+2933,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w),32); - bufp->chgIData(oldp+2934,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w),32); - bufp->chgIData(oldp+2935,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg),32); - bufp->chgQData(oldp+2936,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w),64); - bufp->chgQData(oldp+2938,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w),64); - bufp->chgQData(oldp+2940,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w),64); - bufp->chgQData(oldp+2942,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg),64); - bufp->chgWData(oldp+2944,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w),128); - bufp->chgWData(oldp+2948,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w),128); - bufp->chgWData(oldp+2952,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w),128); - bufp->chgWData(oldp+2956,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg),128); - bufp->chgWData(oldp+2960,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d),256); - bufp->chgWData(oldp+2968,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d),256); - bufp->chgWData(oldp+2976,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d),256); - bufp->chgWData(oldp+2984,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg),256); - bufp->chgCData(oldp+2992,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts),5); - bufp->chgIData(oldp+2993,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg),32); - bufp->chgBit(oldp+2994,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit)); - bufp->chgBit(oldp+2995,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb)); - bufp->chgBit(oldp+2996,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first)); - bufp->chgBit(oldp+2997,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null)); - bufp->chgBit(oldp+2998,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last)); - bufp->chgWData(oldp+2999,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data),512); - bufp->chgWData(oldp+3015,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data),512); - bufp->chgQData(oldp+3031,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel),64); - bufp->chgQData(oldp+3033,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel),64); - bufp->chgCData(oldp+3035,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift),4); - bufp->chgCData(oldp+3036,((0xfU & (IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data))),4); - bufp->chgBit(oldp+3037,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full)); - bufp->chgBit(oldp+3038,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty)); - bufp->chgBit(oldp+3039,((1U & ((IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data) - >> 4U)))); - bufp->chgCData(oldp+3040,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill),6); - bufp->chgBit(oldp+3041,(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr)); - bufp->chgCData(oldp+3042,(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data),5); - bufp->chgCData(oldp+3043,(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data),5); - bufp->chgBit(oldp+3044,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_full)); - bufp->chgBit(oldp+3045,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty)); - bufp->chgCData(oldp+3046,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[0]),5); - bufp->chgCData(oldp+3047,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[1]),5); - bufp->chgCData(oldp+3048,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[2]),5); - bufp->chgCData(oldp+3049,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[3]),5); - bufp->chgCData(oldp+3050,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[4]),5); - bufp->chgCData(oldp+3051,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[5]),5); - bufp->chgCData(oldp+3052,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[6]),5); - bufp->chgCData(oldp+3053,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[7]),5); - bufp->chgCData(oldp+3054,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[8]),5); - bufp->chgCData(oldp+3055,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[9]),5); - bufp->chgCData(oldp+3056,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[10]),5); - bufp->chgCData(oldp+3057,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[11]),5); - bufp->chgCData(oldp+3058,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[12]),5); - bufp->chgCData(oldp+3059,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[13]),5); - bufp->chgCData(oldp+3060,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[14]),5); - bufp->chgCData(oldp+3061,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[15]),5); - bufp->chgCData(oldp+3062,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[16]),5); - bufp->chgCData(oldp+3063,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[17]),5); - bufp->chgCData(oldp+3064,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[18]),5); - bufp->chgCData(oldp+3065,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[19]),5); - bufp->chgCData(oldp+3066,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[20]),5); - bufp->chgCData(oldp+3067,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[21]),5); - bufp->chgCData(oldp+3068,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[22]),5); - bufp->chgCData(oldp+3069,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[23]),5); - bufp->chgCData(oldp+3070,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[24]),5); - bufp->chgCData(oldp+3071,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[25]),5); - bufp->chgCData(oldp+3072,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[26]),5); - bufp->chgCData(oldp+3073,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[27]),5); - bufp->chgCData(oldp+3074,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[28]),5); - bufp->chgCData(oldp+3075,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[29]),5); - bufp->chgCData(oldp+3076,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[30]),5); - bufp->chgCData(oldp+3077,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[31]),5); - bufp->chgCData(oldp+3078,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr),6); - bufp->chgCData(oldp+3079,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr),6); - bufp->chgBit(oldp+3080,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr)); - bufp->chgBit(oldp+3081,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd)); - bufp->chgSData(oldp+3082,(vlSelf->main__DOT__wb32_xbar__DOT__grant[0]),13); - bufp->chgBit(oldp+3083,(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)); - bufp->chgCData(oldp+3084,(vlSelf->main__DOT__wb32_xbar__DOT__w_mpending[0]),6); - bufp->chgBit(oldp+3085,(vlSelf->main__DOT__wb32_xbar__DOT__mfull)); - bufp->chgBit(oldp+3086,(vlSelf->main__DOT__wb32_xbar__DOT__mnearfull)); - bufp->chgBit(oldp+3087,(vlSelf->main__DOT__wb32_xbar__DOT__mempty)); - bufp->chgIData(oldp+3088,(vlSelf->main__DOT__wb32_xbar__DOT__iN),32); - bufp->chgCData(oldp+3089,(vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending),6); - bufp->chgSData(oldp+3090,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded),13); - bufp->chgBit(oldp+3091,((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))); - bufp->chgCData(oldp+3092,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr),8); - bufp->chgQData(oldp+3093,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data),45); - bufp->chgQData(oldp+3095,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data),45); - bufp->chgIData(oldp+3097,((0x3ffffffU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr))),26); - bufp->chgBit(oldp+3098,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb)); - bufp->chgWData(oldp+3099,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data),512); - bufp->chgCData(oldp+3115,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_shift),4); - bufp->chgBit(oldp+3116,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full)); - bufp->chgBit(oldp+3117,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty)); - bufp->chgCData(oldp+3118,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill),6); - bufp->chgCData(oldp+3119,((0xfU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr))),4); - bufp->chgCData(oldp+3120,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem - [(0x1fU & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr))]),4); - __Vtemp_hcfafa750__0[0U] = Vmain__ConstPool__CONST_hbd99daea_0[0U]; - __Vtemp_hcfafa750__0[1U] = Vmain__ConstPool__CONST_hbd99daea_0[1U]; - __Vtemp_hcfafa750__0[2U] = Vmain__ConstPool__CONST_hbd99daea_0[2U]; - __Vtemp_hcfafa750__0[3U] = Vmain__ConstPool__CONST_hbd99daea_0[3U]; - __Vtemp_hcfafa750__0[4U] = Vmain__ConstPool__CONST_hbd99daea_0[4U]; - __Vtemp_hcfafa750__0[5U] = Vmain__ConstPool__CONST_hbd99daea_0[5U]; - __Vtemp_hcfafa750__0[6U] = Vmain__ConstPool__CONST_hbd99daea_0[6U]; - __Vtemp_hcfafa750__0[7U] = Vmain__ConstPool__CONST_hbd99daea_0[7U]; - __Vtemp_hcfafa750__0[8U] = Vmain__ConstPool__CONST_hbd99daea_0[8U]; - __Vtemp_hcfafa750__0[9U] = Vmain__ConstPool__CONST_hbd99daea_0[9U]; - __Vtemp_hcfafa750__0[0xaU] = Vmain__ConstPool__CONST_hbd99daea_0[0xaU]; - __Vtemp_hcfafa750__0[0xbU] = Vmain__ConstPool__CONST_hbd99daea_0[0xbU]; - __Vtemp_hcfafa750__0[0xcU] = Vmain__ConstPool__CONST_hbd99daea_0[0xcU]; - __Vtemp_hcfafa750__0[0xdU] = Vmain__ConstPool__CONST_hbd99daea_0[0xdU]; - __Vtemp_hcfafa750__0[0xeU] = Vmain__ConstPool__CONST_hbd99daea_0[0xeU]; - __Vtemp_hcfafa750__0[0xfU] = (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata); - bufp->chgWData(oldp+3121,(__Vtemp_hcfafa750__0),512); - bufp->chgQData(oldp+3137,(((QData)((IData)( - (0xfU - & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel)))) - << 0x3cU)),64); - bufp->chgBit(oldp+3139,(((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - & (IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb)))); - bufp->chgCData(oldp+3140,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[0]),4); - bufp->chgCData(oldp+3141,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[1]),4); - bufp->chgCData(oldp+3142,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[2]),4); - bufp->chgCData(oldp+3143,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[3]),4); - bufp->chgCData(oldp+3144,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[4]),4); - bufp->chgCData(oldp+3145,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[5]),4); - bufp->chgCData(oldp+3146,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[6]),4); - bufp->chgCData(oldp+3147,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[7]),4); - bufp->chgCData(oldp+3148,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[8]),4); - bufp->chgCData(oldp+3149,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[9]),4); - bufp->chgCData(oldp+3150,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[10]),4); - bufp->chgCData(oldp+3151,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[11]),4); - bufp->chgCData(oldp+3152,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[12]),4); - bufp->chgCData(oldp+3153,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[13]),4); - bufp->chgCData(oldp+3154,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[14]),4); - bufp->chgCData(oldp+3155,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[15]),4); - bufp->chgCData(oldp+3156,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[16]),4); - bufp->chgCData(oldp+3157,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[17]),4); - bufp->chgCData(oldp+3158,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[18]),4); - bufp->chgCData(oldp+3159,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[19]),4); - bufp->chgCData(oldp+3160,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[20]),4); - bufp->chgCData(oldp+3161,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[21]),4); - bufp->chgCData(oldp+3162,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[22]),4); - bufp->chgCData(oldp+3163,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[23]),4); - bufp->chgCData(oldp+3164,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[24]),4); - bufp->chgCData(oldp+3165,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[25]),4); - bufp->chgCData(oldp+3166,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[26]),4); - bufp->chgCData(oldp+3167,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[27]),4); - bufp->chgCData(oldp+3168,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[28]),4); - bufp->chgCData(oldp+3169,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[29]),4); - bufp->chgCData(oldp+3170,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[30]),4); - bufp->chgCData(oldp+3171,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[31]),4); - bufp->chgCData(oldp+3172,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr),6); - bufp->chgCData(oldp+3173,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr),6); - bufp->chgBit(oldp+3174,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr)); - bufp->chgBit(oldp+3175,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd)); - bufp->chgCData(oldp+3176,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc),2); - bufp->chgCData(oldp+3177,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb),2); - bufp->chgCData(oldp+3178,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe),2); - bufp->chgQData(oldp+3179,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr),54); - bufp->chgQData(oldp+3181,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata),64); - bufp->chgCData(oldp+3183,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel),8); - bufp->chgQData(oldp+3184,((((QData)((IData)(vlSelf->main__DOT__wbu_zip_idata)) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xfU])))),64); - bufp->chgCData(oldp+3186,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err),2); - bufp->chgCData(oldp+3187,(vlSelf->main__DOT__wbu_xbar__DOT__request[0]),3); - bufp->chgCData(oldp+3188,(vlSelf->main__DOT__wbu_xbar__DOT__grant[0]),3); - bufp->chgBit(oldp+3189,(vlSelf->main__DOT__wbu_xbar__DOT__mgrant)); - bufp->chgCData(oldp+3190,(vlSelf->main__DOT__wbu_xbar__DOT__sgrant),2); - bufp->chgCData(oldp+3191,(vlSelf->main__DOT__wbu_xbar__DOT__w_mpending[0]),6); - bufp->chgBit(oldp+3192,(vlSelf->main__DOT__wbu_xbar__DOT__mfull)); - bufp->chgBit(oldp+3193,(vlSelf->main__DOT__wbu_xbar__DOT__mnearfull)); - bufp->chgBit(oldp+3194,(vlSelf->main__DOT__wbu_xbar__DOT__mempty)); - bufp->chgBit(oldp+3195,(vlSelf->main__DOT__wbu_xbar__DOT__m_stb)); - bufp->chgBit(oldp+3196,((1U & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> 0x24U))))); - bufp->chgIData(oldp+3197,(vlSelf->main__DOT__wbu_xbar__DOT__m_addr[0]),27); - bufp->chgIData(oldp+3198,(vlSelf->main__DOT__wbu_xbar__DOT__m_data[0]),32); - bufp->chgCData(oldp+3199,(vlSelf->main__DOT__wbu_xbar__DOT__m_sel[0]),4); - bufp->chgIData(oldp+3200,(vlSelf->main__DOT__wbu_xbar__DOT__s_data[0]),32); - bufp->chgIData(oldp+3201,(vlSelf->main__DOT__wbu_xbar__DOT__s_data[1]),32); - bufp->chgIData(oldp+3202,(vlSelf->main__DOT__wbu_xbar__DOT__s_data[2]),32); - bufp->chgIData(oldp+3203,(vlSelf->main__DOT__wbu_xbar__DOT__s_data[3]),32); - bufp->chgCData(oldp+3204,(vlSelf->main__DOT__wbu_xbar__DOT__s_err),4); - bufp->chgBit(oldp+3205,(vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb)); - bufp->chgIData(oldp+3206,(vlSelf->main__DOT__wbu_xbar__DOT__iN),32); - bufp->chgBit(oldp+3207,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)); - bufp->chgBit(oldp+3208,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available)); - bufp->chgCData(oldp+3209,(vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending),6); - bufp->chgBit(oldp+3210,((1U & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x3fU))))); - bufp->chgIData(oldp+3211,((0x7ffffffU & (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))),27); - bufp->chgIData(oldp+3212,((IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 4U))),32); - bufp->chgCData(oldp+3213,((0xfU & (IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data))),4); - bufp->chgCData(oldp+3214,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded),3); - bufp->chgBit(oldp+3215,((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))); - bufp->chgQData(oldp+3216,((((QData)((IData)( - (1U - & (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x3fU))))) - << 0x24U) | (0xfffffffffULL - & vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data))),37); - bufp->chgIData(oldp+3218,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr),27); - bufp->chgQData(oldp+3219,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data),37); - bufp->chgCData(oldp+3221,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest),2); - bufp->chgQData(oldp+3222,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data),64); - bufp->chgQData(oldp+3224,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data),64); - bufp->chgQData(oldp+3226,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data),64); - bufp->chgCData(oldp+3228,((((IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb) - << 3U) | (((IData)(vlSelf->main__DOT__wbwide_zip_stb) - << 2U) - | (((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - << 1U) - | (IData)(vlSelf->main__DOT__wbwide_i2cdma_stb))))),4); - bufp->chgCData(oldp+3229,((1U | (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we) - << 3U) | - (4U & (((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__cpu_we) - : - (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner))) - << 2U))))),4); - __Vtemp_h708d16f1__0[0U] = (IData)((((QData)((IData)(vlSelf->main__DOT__wbwide_i2cm_addr)) - << 0x16U) - | (QData)((IData)(vlSelf->main__DOT__wbwide_i2cdma_addr)))); - __Vtemp_h708d16f1__0[1U] = ((vlSelf->main__DOT__wbwide_zip_addr - << 0xcU) | (IData)( - ((((QData)((IData)(vlSelf->main__DOT__wbwide_i2cm_addr)) - << 0x16U) - | (QData)((IData)(vlSelf->main__DOT__wbwide_i2cdma_addr))) - >> 0x20U))); - __Vtemp_h708d16f1__0[2U] = ((vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr - << 2U) | (vlSelf->main__DOT__wbwide_zip_addr - >> 0x14U)); - bufp->chgWData(oldp+3230,(__Vtemp_h708d16f1__0),88); - __Vtemp_h95b27ed2__0[0U] = vlSelf->main__DOT__wbwide_i2cdma_data[0U]; - __Vtemp_h95b27ed2__0[1U] = vlSelf->main__DOT__wbwide_i2cdma_data[1U]; - __Vtemp_h95b27ed2__0[2U] = vlSelf->main__DOT__wbwide_i2cdma_data[2U]; - __Vtemp_h95b27ed2__0[3U] = vlSelf->main__DOT__wbwide_i2cdma_data[3U]; - __Vtemp_h95b27ed2__0[4U] = vlSelf->main__DOT__wbwide_i2cdma_data[4U]; - __Vtemp_h95b27ed2__0[5U] = vlSelf->main__DOT__wbwide_i2cdma_data[5U]; - __Vtemp_h95b27ed2__0[6U] = vlSelf->main__DOT__wbwide_i2cdma_data[6U]; - __Vtemp_h95b27ed2__0[7U] = vlSelf->main__DOT__wbwide_i2cdma_data[7U]; - __Vtemp_h95b27ed2__0[8U] = vlSelf->main__DOT__wbwide_i2cdma_data[8U]; - __Vtemp_h95b27ed2__0[9U] = vlSelf->main__DOT__wbwide_i2cdma_data[9U]; - __Vtemp_h95b27ed2__0[0xaU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xaU]; - __Vtemp_h95b27ed2__0[0xbU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xbU]; - __Vtemp_h95b27ed2__0[0xcU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xcU]; - __Vtemp_h95b27ed2__0[0xdU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xdU]; - __Vtemp_h95b27ed2__0[0xeU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xeU]; - __Vtemp_h95b27ed2__0[0xfU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xfU]; - __Vtemp_h95b27ed2__0[0x10U] = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - __Vtemp_h95b27ed2__0[0x11U] = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - __Vtemp_h95b27ed2__0[0x12U] = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - __Vtemp_h95b27ed2__0[0x13U] = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - __Vtemp_h95b27ed2__0[0x14U] = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - __Vtemp_h95b27ed2__0[0x15U] = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - __Vtemp_h95b27ed2__0[0x16U] = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - __Vtemp_h95b27ed2__0[0x17U] = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - __Vtemp_h95b27ed2__0[0x18U] = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - __Vtemp_h95b27ed2__0[0x19U] = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - __Vtemp_h95b27ed2__0[0x1aU] = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - __Vtemp_h95b27ed2__0[0x1bU] = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - __Vtemp_h95b27ed2__0[0x1cU] = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - __Vtemp_h95b27ed2__0[0x1dU] = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - __Vtemp_h95b27ed2__0[0x1eU] = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - __Vtemp_h95b27ed2__0[0x1fU] = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - if (vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) { - __Vtemp_h95b27ed2__0[0x20U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - __Vtemp_h95b27ed2__0[0x21U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U]; - __Vtemp_h95b27ed2__0[0x22U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U]; - __Vtemp_h95b27ed2__0[0x23U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U]; - __Vtemp_h95b27ed2__0[0x24U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U]; - __Vtemp_h95b27ed2__0[0x25U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U]; - __Vtemp_h95b27ed2__0[0x26U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U]; - __Vtemp_h95b27ed2__0[0x27U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U]; - __Vtemp_h95b27ed2__0[0x28U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U]; - __Vtemp_h95b27ed2__0[0x29U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U]; - __Vtemp_h95b27ed2__0[0x2aU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU]; - __Vtemp_h95b27ed2__0[0x2bU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU]; - __Vtemp_h95b27ed2__0[0x2cU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU]; - __Vtemp_h95b27ed2__0[0x2dU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU]; - __Vtemp_h95b27ed2__0[0x2eU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU]; - __Vtemp_h95b27ed2__0[0x2fU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU]; - } else { - __Vtemp_h95b27ed2__0[0x20U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0U]; - __Vtemp_h95b27ed2__0[0x21U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[1U]; - __Vtemp_h95b27ed2__0[0x22U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[2U]; - __Vtemp_h95b27ed2__0[0x23U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[3U]; - __Vtemp_h95b27ed2__0[0x24U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[4U]; - __Vtemp_h95b27ed2__0[0x25U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[5U]; - __Vtemp_h95b27ed2__0[0x26U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[6U]; - __Vtemp_h95b27ed2__0[0x27U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[7U]; - __Vtemp_h95b27ed2__0[0x28U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[8U]; - __Vtemp_h95b27ed2__0[0x29U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[9U]; - __Vtemp_h95b27ed2__0[0x2aU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xaU]; - __Vtemp_h95b27ed2__0[0x2bU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xbU]; - __Vtemp_h95b27ed2__0[0x2cU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xcU]; - __Vtemp_h95b27ed2__0[0x2dU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xdU]; - __Vtemp_h95b27ed2__0[0x2eU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xeU]; - __Vtemp_h95b27ed2__0[0x2fU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xfU]; - } - __Vtemp_h95b27ed2__0[0x30U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0U]; - __Vtemp_h95b27ed2__0[0x31U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[1U]; - __Vtemp_h95b27ed2__0[0x32U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[2U]; - __Vtemp_h95b27ed2__0[0x33U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[3U]; - __Vtemp_h95b27ed2__0[0x34U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[4U]; - __Vtemp_h95b27ed2__0[0x35U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[5U]; - __Vtemp_h95b27ed2__0[0x36U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[6U]; - __Vtemp_h95b27ed2__0[0x37U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[7U]; - __Vtemp_h95b27ed2__0[0x38U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[8U]; - __Vtemp_h95b27ed2__0[0x39U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[9U]; - __Vtemp_h95b27ed2__0[0x3aU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xaU]; - __Vtemp_h95b27ed2__0[0x3bU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xbU]; - __Vtemp_h95b27ed2__0[0x3cU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xcU]; - __Vtemp_h95b27ed2__0[0x3dU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xdU]; - __Vtemp_h95b27ed2__0[0x3eU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xeU]; - __Vtemp_h95b27ed2__0[0x3fU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xfU]; - bufp->chgWData(oldp+3233,(__Vtemp_h95b27ed2__0),2048); - __Vtemp_h7cab7483__0[0U] = (IData)(vlSelf->main__DOT__wbwide_i2cdma_sel); - __Vtemp_h7cab7483__0[1U] = (IData)((vlSelf->main__DOT__wbwide_i2cdma_sel - >> 0x20U)); - __Vtemp_h7cab7483__0[2U] = 0xffffffffU; - __Vtemp_h7cab7483__0[3U] = 0xffffffffU; - __Vtemp_h7cab7483__0[4U] = (IData)(((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel))); - __Vtemp_h7cab7483__0[5U] = (IData)((((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel)) - >> 0x20U)); - __Vtemp_h7cab7483__0[6U] = (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel); - __Vtemp_h7cab7483__0[7U] = (IData)((vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel - >> 0x20U)); - bufp->chgWData(oldp+3297,(__Vtemp_h7cab7483__0),256); - bufp->chgCData(oldp+3305,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - << 3U) | (IData)(vlSelf->__VdfgTmp_h503d14d1__0))),4); - bufp->chgCData(oldp+3306,(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack),4); - bufp->chgWData(oldp+3307,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata),2048); - bufp->chgCData(oldp+3371,(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr),4); - bufp->chgCData(oldp+3372,(vlSelf->main__DOT__wbwide_xbar__DOT__request[0]),4); - bufp->chgCData(oldp+3373,(vlSelf->main__DOT__wbwide_xbar__DOT__request[1]),4); - bufp->chgCData(oldp+3374,(vlSelf->main__DOT__wbwide_xbar__DOT__request[2]),4); - bufp->chgCData(oldp+3375,(vlSelf->main__DOT__wbwide_xbar__DOT__request[3]),4); - bufp->chgCData(oldp+3376,(vlSelf->main__DOT__wbwide_xbar__DOT__requested[0]),3); - bufp->chgCData(oldp+3377,(vlSelf->main__DOT__wbwide_xbar__DOT__requested[1]),3); - bufp->chgCData(oldp+3378,(vlSelf->main__DOT__wbwide_xbar__DOT__requested[2]),3); - bufp->chgCData(oldp+3379,(vlSelf->main__DOT__wbwide_xbar__DOT__requested[3]),3); - bufp->chgCData(oldp+3380,(vlSelf->main__DOT__wbwide_xbar__DOT__grant[0]),4); - bufp->chgCData(oldp+3381,(vlSelf->main__DOT__wbwide_xbar__DOT__grant[1]),4); - bufp->chgCData(oldp+3382,(vlSelf->main__DOT__wbwide_xbar__DOT__grant[2]),4); - bufp->chgCData(oldp+3383,(vlSelf->main__DOT__wbwide_xbar__DOT__grant[3]),4); - bufp->chgCData(oldp+3384,(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant),4); - bufp->chgCData(oldp+3385,(vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[0]),6); - bufp->chgCData(oldp+3386,(vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[1]),6); - bufp->chgCData(oldp+3387,(vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[2]),6); - bufp->chgCData(oldp+3388,(vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[3]),6); - bufp->chgCData(oldp+3389,(vlSelf->main__DOT__wbwide_xbar__DOT__mfull),4); - bufp->chgCData(oldp+3390,(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull),4); - bufp->chgCData(oldp+3391,(vlSelf->main__DOT__wbwide_xbar__DOT__mempty),4); - bufp->chgCData(oldp+3392,(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb),4); - bufp->chgCData(oldp+3393,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid) - << 3U) | (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid) - << 2U) - | (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid) - << 1U) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid))))),4); - bufp->chgBit(oldp+3394,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)); - bufp->chgBit(oldp+3395,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel)); - bufp->chgBit(oldp+3396,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel)); - bufp->chgBit(oldp+3397,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel)); - bufp->chgCData(oldp+3398,(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending),6); - bufp->chgCData(oldp+3399,(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending),6); - bufp->chgCData(oldp+3400,(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending),6); - bufp->chgCData(oldp+3401,(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending),6); - bufp->chgBit(oldp+3402,((1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)))); - bufp->chgIData(oldp+3403,((0x3fffffU & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U])),22); - __Vtemp_h53a5df10__0[0U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U]; - __Vtemp_h53a5df10__0[1U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U]; - __Vtemp_h53a5df10__0[2U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U]; - __Vtemp_h53a5df10__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U]; - __Vtemp_h53a5df10__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U]; - __Vtemp_h53a5df10__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U]; - __Vtemp_h53a5df10__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U]; - __Vtemp_h53a5df10__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U]; - __Vtemp_h53a5df10__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_h53a5df10__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_h53a5df10__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU]; - __Vtemp_h53a5df10__0[0xbU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU]; - __Vtemp_h53a5df10__0[0xcU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU]; - __Vtemp_h53a5df10__0[0xdU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU]; - __Vtemp_h53a5df10__0[0xeU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U]; - __Vtemp_h53a5df10__0[0xfU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U]; - bufp->chgWData(oldp+3404,(__Vtemp_h53a5df10__0),512); - bufp->chgQData(oldp+3420,((((QData)((IData)( - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U])))),64); - bufp->chgCData(oldp+3422,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded),4); - bufp->chgBit(oldp+3423,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))); - __Vtemp_hb52cb2db__0[0U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U]; - __Vtemp_hb52cb2db__0[1U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U]; - __Vtemp_hb52cb2db__0[2U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U]; - __Vtemp_hb52cb2db__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U]; - __Vtemp_hb52cb2db__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U]; - __Vtemp_hb52cb2db__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U]; - __Vtemp_hb52cb2db__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U]; - __Vtemp_hb52cb2db__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U]; - __Vtemp_hb52cb2db__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U]; - __Vtemp_hb52cb2db__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U]; - __Vtemp_hb52cb2db__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_hb52cb2db__0[0xbU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_hb52cb2db__0[0xcU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU]; - __Vtemp_hb52cb2db__0[0xdU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU]; - __Vtemp_hb52cb2db__0[0xeU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU]; - __Vtemp_hb52cb2db__0[0xfU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU]; - __Vtemp_hb52cb2db__0[0x10U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U]; - __Vtemp_hb52cb2db__0[0x11U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U]; - __Vtemp_hb52cb2db__0[0x12U] = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)); - bufp->chgWData(oldp+3424,(__Vtemp_hb52cb2db__0),577); - bufp->chgBit(oldp+3443,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)); - bufp->chgIData(oldp+3444,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr),22); - bufp->chgWData(oldp+3445,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data),577); - bufp->chgCData(oldp+3464,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest),3); - bufp->chgWData(oldp+3465,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data),599); - bufp->chgWData(oldp+3484,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data),599); - bufp->chgWData(oldp+3503,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data),599); - bufp->chgBit(oldp+3522,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)); - bufp->chgBit(oldp+3523,((1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)))); - bufp->chgIData(oldp+3524,((0x3fffffU & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U])),22); - __Vtemp_hebded4b4__0[0U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[2U]; - __Vtemp_hebded4b4__0[1U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[3U]; - __Vtemp_hebded4b4__0[2U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[4U]; - __Vtemp_hebded4b4__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[5U]; - __Vtemp_hebded4b4__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[6U]; - __Vtemp_hebded4b4__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[7U]; - __Vtemp_hebded4b4__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[8U]; - __Vtemp_hebded4b4__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[9U]; - __Vtemp_hebded4b4__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_hebded4b4__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_hebded4b4__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xcU]; 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- bufp->chgCData(oldp+3785,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__decoded),4); - bufp->chgBit(oldp+3786,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))); - __Vtemp_hfe9179b2__0[0U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0U]; - __Vtemp_hfe9179b2__0[1U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[1U]; - __Vtemp_hfe9179b2__0[2U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[2U]; - __Vtemp_hfe9179b2__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[3U]; - __Vtemp_hfe9179b2__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[4U]; - __Vtemp_hfe9179b2__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[5U]; - __Vtemp_hfe9179b2__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[6U]; - __Vtemp_hfe9179b2__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[7U]; - __Vtemp_hfe9179b2__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[8U]; - __Vtemp_hfe9179b2__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[9U]; - __Vtemp_hfe9179b2__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_hfe9179b2__0[0xbU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_hfe9179b2__0[0xcU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xcU]; - __Vtemp_hfe9179b2__0[0xdU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xdU]; - __Vtemp_hfe9179b2__0[0xeU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xeU]; - __Vtemp_hfe9179b2__0[0xfU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xfU]; - __Vtemp_hfe9179b2__0[0x10U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x10U]; - __Vtemp_hfe9179b2__0[0x11U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x11U]; - __Vtemp_hfe9179b2__0[0x12U] = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)); - bufp->chgWData(oldp+3787,(__Vtemp_hfe9179b2__0),577); - bufp->chgBit(oldp+3806,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid)); - bufp->chgIData(oldp+3807,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_addr),22); - bufp->chgWData(oldp+3808,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data),577); - bufp->chgCData(oldp+3827,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest),3); - bufp->chgWData(oldp+3828,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data),599); - bufp->chgWData(oldp+3847,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data),599); - bufp->chgWData(oldp+3866,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data),599); - bufp->chgCData(oldp+3885,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex),2); - bufp->chgCData(oldp+3886,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex),2); - bufp->chgCData(oldp+3887,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex),2); - } - if (VL_UNLIKELY((vlSelf->__Vm_traceActivity[2U] - | vlSelf->__Vm_traceActivity[3U]))) { - bufp->chgSData(oldp+3888,((((IData)(vlSelf->main__DOT__wb32_ddr3_phy_ack) - << 0xbU) | (((IData)(vlSelf->main__DOT__r_cfg_ack) - << 0xaU) - | (((IData)(vlSelf->main__DOT__r_wb32_sio_ack) - << 9U) - | (((IData)(vlSelf->main__DOT__wb32_sdcard_ack) - << 8U) - | (((IData)(vlSelf->main__DOT__wb32_fan_ack) - << 7U) - | (((IData)(vlSelf->main__DOT__wb32_emmc_ack) - << 6U) - | (((IData)(vlSelf->main__DOT__wb32_uart_ack) - << 5U) - | (((IData)(vlSelf->main__DOT__wb32_i2cdma_ack) - << 4U) - | (((IData)(vlSelf->main__DOT__wb32_i2cs_ack) - << 3U) - | (((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack) - << 2U) - | (((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack) - << 1U) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack))))))))))))),12); - __Vtemp_ha40692d2__0[0U] = vlSelf->main__DOT__emmcscopei__DOT__o_bus_data; - __Vtemp_ha40692d2__0[1U] = vlSelf->main__DOT__i2cscopei__DOT__o_bus_data; - __Vtemp_ha40692d2__0[2U] = vlSelf->main__DOT__sdioscopei__DOT__o_bus_data; - __Vtemp_ha40692d2__0[3U] = vlSelf->main__DOT__i2ci__DOT__bus_read_data; - __Vtemp_ha40692d2__0[4U] = vlSelf->main__DOT__wb32_i2cdma_idata; - __Vtemp_ha40692d2__0[5U] = vlSelf->main__DOT__wb32_uart_idata; - __Vtemp_ha40692d2__0[6U] = vlSelf->main__DOT__wb32_emmc_idata; - __Vtemp_ha40692d2__0[7U] = vlSelf->main__DOT__wb32_fan_idata; - __Vtemp_ha40692d2__0[8U] = vlSelf->main__DOT__wb32_sdcard_idata; - __Vtemp_ha40692d2__0[9U] = vlSelf->main__DOT__r_wb32_sio_data; - __Vtemp_ha40692d2__0[0xaU] = (IData)(((QData)((IData)(vlSelf->main__DOT__wb32_ddr3_phy_idata)) - << 0x20U)); - __Vtemp_ha40692d2__0[0xbU] = (IData)((((QData)((IData)(vlSelf->main__DOT__wb32_ddr3_phy_idata)) - << 0x20U) - >> 0x20U)); - bufp->chgWData(oldp+3889,(__Vtemp_ha40692d2__0),384); - bufp->chgIData(oldp+3901,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[0]),32); - bufp->chgIData(oldp+3902,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[1]),32); - bufp->chgIData(oldp+3903,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[2]),32); - bufp->chgIData(oldp+3904,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[3]),32); - bufp->chgIData(oldp+3905,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[4]),32); - bufp->chgIData(oldp+3906,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[5]),32); - bufp->chgIData(oldp+3907,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[6]),32); - bufp->chgIData(oldp+3908,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[7]),32); - bufp->chgIData(oldp+3909,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[8]),32); - bufp->chgIData(oldp+3910,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[9]),32); - bufp->chgIData(oldp+3911,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[10]),32); - bufp->chgIData(oldp+3912,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[11]),32); - bufp->chgIData(oldp+3913,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[12]),32); - bufp->chgIData(oldp+3914,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[13]),32); - bufp->chgIData(oldp+3915,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[14]),32); - bufp->chgIData(oldp+3916,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[15]),32); - bufp->chgCData(oldp+3917,((((IData)(vlSelf->main__DOT__wbwide_ddr3_controller_stall) - << 2U) | (IData)(vlSelf->main__DOT__wbwide_wbdown_stall))),3); - bufp->chgCData(oldp+3918,((((vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U] & (0xeU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - << 2U) | (((IData)(vlSelf->main__DOT__wbwide_bkram_ack) - << 1U) - | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack)))),3); - __Vtemp_h8a06d21b__0[0U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U]; - __Vtemp_h8a06d21b__0[1U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U]; - __Vtemp_h8a06d21b__0[2U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U]; - __Vtemp_h8a06d21b__0[3U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U]; - __Vtemp_h8a06d21b__0[4U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U]; - __Vtemp_h8a06d21b__0[5U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U]; - __Vtemp_h8a06d21b__0[6U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U]; - __Vtemp_h8a06d21b__0[7U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U]; - __Vtemp_h8a06d21b__0[8U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U]; - __Vtemp_h8a06d21b__0[9U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U]; - __Vtemp_h8a06d21b__0[0xaU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU]; - __Vtemp_h8a06d21b__0[0xbU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU]; - __Vtemp_h8a06d21b__0[0xcU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU]; - __Vtemp_h8a06d21b__0[0xdU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU]; - __Vtemp_h8a06d21b__0[0xeU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU]; - __Vtemp_h8a06d21b__0[0xfU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU]; - __Vtemp_h8a06d21b__0[0x10U] = vlSelf->main__DOT__wbwide_bkram_idata[0U]; - __Vtemp_h8a06d21b__0[0x11U] = vlSelf->main__DOT__wbwide_bkram_idata[1U]; - __Vtemp_h8a06d21b__0[0x12U] = vlSelf->main__DOT__wbwide_bkram_idata[2U]; - __Vtemp_h8a06d21b__0[0x13U] = vlSelf->main__DOT__wbwide_bkram_idata[3U]; - __Vtemp_h8a06d21b__0[0x14U] = vlSelf->main__DOT__wbwide_bkram_idata[4U]; - __Vtemp_h8a06d21b__0[0x15U] = vlSelf->main__DOT__wbwide_bkram_idata[5U]; - __Vtemp_h8a06d21b__0[0x16U] = vlSelf->main__DOT__wbwide_bkram_idata[6U]; - __Vtemp_h8a06d21b__0[0x17U] = vlSelf->main__DOT__wbwide_bkram_idata[7U]; - __Vtemp_h8a06d21b__0[0x18U] = vlSelf->main__DOT__wbwide_bkram_idata[8U]; - __Vtemp_h8a06d21b__0[0x19U] = vlSelf->main__DOT__wbwide_bkram_idata[9U]; - __Vtemp_h8a06d21b__0[0x1aU] = vlSelf->main__DOT__wbwide_bkram_idata[0xaU]; - __Vtemp_h8a06d21b__0[0x1bU] = vlSelf->main__DOT__wbwide_bkram_idata[0xbU]; - __Vtemp_h8a06d21b__0[0x1cU] = vlSelf->main__DOT__wbwide_bkram_idata[0xcU]; - __Vtemp_h8a06d21b__0[0x1dU] = vlSelf->main__DOT__wbwide_bkram_idata[0xdU]; - __Vtemp_h8a06d21b__0[0x1eU] = vlSelf->main__DOT__wbwide_bkram_idata[0xeU]; - __Vtemp_h8a06d21b__0[0x1fU] = vlSelf->main__DOT__wbwide_bkram_idata[0xfU]; - __Vtemp_h8a06d21b__0[0x20U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0U]; - __Vtemp_h8a06d21b__0[0x21U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][1U]; - __Vtemp_h8a06d21b__0[0x22U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][2U]; - __Vtemp_h8a06d21b__0[0x23U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][3U]; - __Vtemp_h8a06d21b__0[0x24U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][4U]; - __Vtemp_h8a06d21b__0[0x25U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][5U]; - __Vtemp_h8a06d21b__0[0x26U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][6U]; - __Vtemp_h8a06d21b__0[0x27U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][7U]; - __Vtemp_h8a06d21b__0[0x28U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][8U]; - __Vtemp_h8a06d21b__0[0x29U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][9U]; - __Vtemp_h8a06d21b__0[0x2aU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xaU]; - __Vtemp_h8a06d21b__0[0x2bU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xbU]; - __Vtemp_h8a06d21b__0[0x2cU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xcU]; - __Vtemp_h8a06d21b__0[0x2dU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xdU]; - __Vtemp_h8a06d21b__0[0x2eU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xeU]; - __Vtemp_h8a06d21b__0[0x2fU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xfU]; - bufp->chgWData(oldp+3919,(__Vtemp_h8a06d21b__0),1536); - bufp->chgWData(oldp+3967,(vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0]),512); - bufp->chgWData(oldp+3983,(vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1]),512); - bufp->chgWData(oldp+3999,(vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2]),512); - bufp->chgWData(oldp+4015,(vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3]),512); - } - if (VL_UNLIKELY(vlSelf->__Vm_traceActivity[3U])) { - bufp->chgBit(oldp+4031,((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U] >> 1U)))); - bufp->chgBit(oldp+4032,(vlSelf->main__DOT__wbwide_ddr3_controller_stall)); - bufp->chgBit(oldp+4033,((vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U] & (0xeU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))))); - __Vtemp_hc035b709__1[0U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0U]; - __Vtemp_hc035b709__1[1U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][1U]; - __Vtemp_hc035b709__1[2U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][2U]; - __Vtemp_hc035b709__1[3U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][3U]; - __Vtemp_hc035b709__1[4U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][4U]; - __Vtemp_hc035b709__1[5U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][5U]; - __Vtemp_hc035b709__1[6U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][6U]; - __Vtemp_hc035b709__1[7U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][7U]; - __Vtemp_hc035b709__1[8U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][8U]; - __Vtemp_hc035b709__1[9U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][9U]; - __Vtemp_hc035b709__1[0xaU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xaU]; - __Vtemp_hc035b709__1[0xbU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xbU]; - __Vtemp_hc035b709__1[0xcU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xcU]; - __Vtemp_hc035b709__1[0xdU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xdU]; - __Vtemp_hc035b709__1[0xeU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xeU]; - __Vtemp_hc035b709__1[0xfU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xfU]; - bufp->chgWData(oldp+4034,(__Vtemp_hc035b709__1),512); - bufp->chgBit(oldp+4050,(vlSelf->main__DOT__wb32_ddr3_phy_stall)); - bufp->chgBit(oldp+4051,(vlSelf->main__DOT__wb32_ddr3_phy_ack)); - bufp->chgIData(oldp+4052,(vlSelf->main__DOT__wb32_ddr3_phy_idata),32); - bufp->chgIData(oldp+4053,(vlSelf->main__DOT__ddr3_controller_inst__DOT__index),32); - bufp->chgCData(oldp+4054,(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address),5); - bufp->chgIData(oldp+4055,(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction),28); - bufp->chgSData(oldp+4056,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter),16); - bufp->chgBit(oldp+4057,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero)); - bufp->chgBit(oldp+4058,(vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done)); - bufp->chgBit(oldp+4059,(vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter)); - bufp->chgBit(oldp+4060,((2U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate)))); - bufp->chgBit(oldp+4061,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update)); - bufp->chgCData(oldp+4062,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q),8); - bufp->chgSData(oldp+4063,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[0]),14); - bufp->chgSData(oldp+4064,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[1]),14); - bufp->chgSData(oldp+4065,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[2]),14); - bufp->chgSData(oldp+4066,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[3]),14); - bufp->chgSData(oldp+4067,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[4]),14); - bufp->chgSData(oldp+4068,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[5]),14); - bufp->chgSData(oldp+4069,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[6]),14); - bufp->chgSData(oldp+4070,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[7]),14); - bufp->chgBit(oldp+4071,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending)); - bufp->chgBit(oldp+4072,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_aux)); - bufp->chgBit(oldp+4073,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we)); - bufp->chgWData(oldp+4074,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data),512); - bufp->chgQData(oldp+4090,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_dm),64); - bufp->chgSData(oldp+4092,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_col),10); - bufp->chgCData(oldp+4093,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank),3); - bufp->chgSData(oldp+4094,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row),14); - bufp->chgCData(oldp+4095,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank),3); - bufp->chgSData(oldp+4096,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row),14); - bufp->chgBit(oldp+4097,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending)); - bufp->chgBit(oldp+4098,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux)); - bufp->chgBit(oldp+4099,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we)); - bufp->chgQData(oldp+4100,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned),64); - bufp->chgQData(oldp+4102,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0]),64); - bufp->chgQData(oldp+4104,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[1]),64); - bufp->chgWData(oldp+4106,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned),512); - bufp->chgWData(oldp+4122,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0]),512); - bufp->chgWData(oldp+4138,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1]),512); - bufp->chgQData(oldp+4154,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[0]),64); - bufp->chgQData(oldp+4156,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[1]),64); - bufp->chgQData(oldp+4158,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[2]),64); - bufp->chgQData(oldp+4160,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[3]),64); - bufp->chgQData(oldp+4162,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[4]),64); - bufp->chgQData(oldp+4164,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[5]),64); - bufp->chgQData(oldp+4166,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[6]),64); - bufp->chgQData(oldp+4168,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[7]),64); - bufp->chgCData(oldp+4170,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[0]),8); - bufp->chgCData(oldp+4171,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[1]),8); - bufp->chgCData(oldp+4172,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[2]),8); - bufp->chgCData(oldp+4173,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[3]),8); - bufp->chgCData(oldp+4174,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[4]),8); - bufp->chgCData(oldp+4175,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[5]),8); - bufp->chgCData(oldp+4176,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[6]),8); - bufp->chgCData(oldp+4177,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[7]),8); - bufp->chgSData(oldp+4178,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col),10); - bufp->chgCData(oldp+4179,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank),3); - bufp->chgSData(oldp+4180,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row),14); - bufp->chgCData(oldp+4181,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[0]),4); - bufp->chgCData(oldp+4182,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[1]),4); - bufp->chgCData(oldp+4183,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[2]),4); - bufp->chgCData(oldp+4184,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[3]),4); - bufp->chgCData(oldp+4185,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[4]),4); - bufp->chgCData(oldp+4186,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[5]),4); - bufp->chgCData(oldp+4187,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[6]),4); - bufp->chgCData(oldp+4188,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[7]),4); - bufp->chgCData(oldp+4189,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[0]),4); - bufp->chgCData(oldp+4190,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[1]),4); - bufp->chgCData(oldp+4191,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[2]),4); - bufp->chgCData(oldp+4192,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[3]),4); - bufp->chgCData(oldp+4193,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[4]),4); - bufp->chgCData(oldp+4194,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[5]),4); - bufp->chgCData(oldp+4195,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[6]),4); - bufp->chgCData(oldp+4196,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[7]),4); - bufp->chgCData(oldp+4197,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[0]),4); - bufp->chgCData(oldp+4198,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[1]),4); - bufp->chgCData(oldp+4199,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[2]),4); - bufp->chgCData(oldp+4200,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[3]),4); - bufp->chgCData(oldp+4201,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[4]),4); - bufp->chgCData(oldp+4202,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[5]),4); - bufp->chgCData(oldp+4203,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[6]),4); - bufp->chgCData(oldp+4204,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[7]),4); - bufp->chgCData(oldp+4205,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[0]),4); - bufp->chgCData(oldp+4206,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[1]),4); - bufp->chgCData(oldp+4207,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[2]),4); - bufp->chgCData(oldp+4208,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[3]),4); - bufp->chgCData(oldp+4209,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[4]),4); - bufp->chgCData(oldp+4210,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[5]),4); - bufp->chgCData(oldp+4211,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[6]),4); - bufp->chgCData(oldp+4212,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[7]),4); - bufp->chgBit(oldp+4213,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt_q)); - bufp->chgBit(oldp+4214,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q)); - bufp->chgCData(oldp+4215,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_q),2); - bufp->chgBit(oldp+4216,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d)); - bufp->chgCData(oldp+4217,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs),3); - bufp->chgCData(oldp+4218,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_val),3); - bufp->chgBit(oldp+4219,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_q)); - bufp->chgBit(oldp+4220,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d)); - bufp->chgCData(oldp+4221,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq),4); - bufp->chgCData(oldp+4222,(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate),5); - bufp->chgQData(oldp+4223,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store),40); - bufp->chgCData(oldp+4225,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat),4); - bufp->chgCData(oldp+4226,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index),6); - bufp->chgCData(oldp+4227,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored),6); - bufp->chgCData(oldp+4228,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index),6); - bufp->chgCData(oldp+4229,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig),6); - bufp->chgCData(oldp+4230,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index),6); - bufp->chgCData(oldp+4231,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value),6); - bufp->chgBit(oldp+4232,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat)); - bufp->chgCData(oldp+4233,(vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay),2); - bufp->chgCData(oldp+4234,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data),4); - bufp->chgCData(oldp+4235,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback),5); - bufp->chgBit(oldp+4236,(vlSelf->main__DOT__ddr3_controller_inst__DOT__initial_dqs)); - bufp->chgCData(oldp+4237,(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane),3); - bufp->chgCData(oldp+4238,(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8),6); - bufp->chgSData(oldp+4239,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement),16); - bufp->chgCData(oldp+4240,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max),4); - bufp->chgCData(oldp+4241,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[0]),4); - bufp->chgCData(oldp+4242,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[1]),4); - bufp->chgCData(oldp+4243,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[2]),4); - bufp->chgCData(oldp+4244,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[3]),4); - bufp->chgCData(oldp+4245,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[4]),4); - bufp->chgCData(oldp+4246,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[5]),4); - bufp->chgCData(oldp+4247,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[6]),4); - bufp->chgCData(oldp+4248,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[7]),4); - bufp->chgCData(oldp+4249,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[0]),2); - bufp->chgCData(oldp+4250,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[1]),2); - bufp->chgCData(oldp+4251,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[2]),2); - bufp->chgCData(oldp+4252,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[3]),2); - bufp->chgCData(oldp+4253,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[4]),2); - bufp->chgCData(oldp+4254,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[0]),2); - bufp->chgCData(oldp+4255,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[1]),2); - bufp->chgCData(oldp+4256,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[2]),2); - bufp->chgCData(oldp+4257,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[3]),2); - bufp->chgCData(oldp+4258,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4]),2); - bufp->chgBit(oldp+4259,(vlSelf->main__DOT__ddr3_controller_inst__DOT__index_read_pipe)); - bufp->chgBit(oldp+4260,(vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data)); - bufp->chgSData(oldp+4261,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[0]),16); - bufp->chgSData(oldp+4262,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[1]),16); - bufp->chgWData(oldp+4263,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0]),512); - bufp->chgWData(oldp+4279,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1]),512); - bufp->chgCData(oldp+4295,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0]),2); - bufp->chgCData(oldp+4296,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[1]),2); - bufp->chgCData(oldp+4297,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[2]),2); - bufp->chgCData(oldp+4298,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[3]),2); - bufp->chgCData(oldp+4299,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[4]),2); - bufp->chgCData(oldp+4300,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[5]),2); - bufp->chgCData(oldp+4301,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[6]),2); - bufp->chgCData(oldp+4302,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[7]),2); - bufp->chgCData(oldp+4303,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[8]),2); - bufp->chgCData(oldp+4304,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[9]),2); - bufp->chgCData(oldp+4305,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[10]),2); - bufp->chgCData(oldp+4306,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[11]),2); - bufp->chgCData(oldp+4307,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[12]),2); - bufp->chgCData(oldp+4308,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[13]),2); - bufp->chgCData(oldp+4309,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[14]),2); - bufp->chgCData(oldp+4310,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[15]),2); - bufp->chgBit(oldp+4311,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_stb)); - bufp->chgBit(oldp+4312,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux)); - bufp->chgBit(oldp+4313,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we)); - bufp->chgSData(oldp+4314,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col),10); - bufp->chgWData(oldp+4315,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data),512); - bufp->chgBit(oldp+4331,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt)); - bufp->chgBit(oldp+4332,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs)); - bufp->chgBit(oldp+4333,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dq)); - bufp->chgBit(oldp+4334,(vlSelf->main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback)); - bufp->chgWData(oldp+4335,(vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store),512); - bufp->chgWData(oldp+4351,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern),128); - bufp->chgCData(oldp+4355,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[0]),7); - bufp->chgCData(oldp+4356,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[1]),7); - bufp->chgCData(oldp+4357,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[2]),7); - bufp->chgCData(oldp+4358,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[3]),7); - bufp->chgCData(oldp+4359,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[4]),7); - bufp->chgCData(oldp+4360,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[5]),7); - bufp->chgCData(oldp+4361,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[6]),7); - bufp->chgCData(oldp+4362,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[7]),7); - bufp->chgCData(oldp+4363,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[0]),5); - bufp->chgCData(oldp+4364,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[1]),5); - bufp->chgCData(oldp+4365,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[2]),5); - bufp->chgCData(oldp+4366,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[3]),5); - bufp->chgCData(oldp+4367,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[4]),5); - bufp->chgCData(oldp+4368,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[5]),5); - bufp->chgCData(oldp+4369,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[6]),5); - bufp->chgCData(oldp+4370,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[7]),5); - bufp->chgCData(oldp+4371,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[0]),5); - bufp->chgCData(oldp+4372,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[1]),5); - bufp->chgCData(oldp+4373,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[2]),5); - bufp->chgCData(oldp+4374,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[3]),5); - bufp->chgCData(oldp+4375,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[4]),5); - bufp->chgCData(oldp+4376,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[5]),5); - bufp->chgCData(oldp+4377,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[6]),5); - bufp->chgCData(oldp+4378,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[7]),5); - bufp->chgCData(oldp+4379,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[0]),5); - bufp->chgCData(oldp+4380,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[1]),5); - bufp->chgCData(oldp+4381,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[2]),5); - bufp->chgCData(oldp+4382,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[3]),5); - bufp->chgCData(oldp+4383,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[4]),5); - bufp->chgCData(oldp+4384,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[5]),5); - bufp->chgCData(oldp+4385,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[6]),5); - bufp->chgCData(oldp+4386,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[7]),5); - bufp->chgCData(oldp+4387,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev),5); - bufp->chgCData(oldp+4388,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[0]),5); - bufp->chgCData(oldp+4389,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[1]),5); - bufp->chgCData(oldp+4390,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[2]),5); - bufp->chgCData(oldp+4391,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[3]),5); - bufp->chgCData(oldp+4392,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[4]),5); - bufp->chgCData(oldp+4393,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[5]),5); - bufp->chgCData(oldp+4394,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[6]),5); - bufp->chgCData(oldp+4395,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[7]),5); - bufp->chgBit(oldp+4396,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_stb)); - bufp->chgBit(oldp+4397,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_update)); - bufp->chgBit(oldp+4398,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)); - bufp->chgIData(oldp+4399,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr),32); - bufp->chgIData(oldp+4400,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_data),32); - bufp->chgCData(oldp+4401,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_sel),4); - bufp->chgCData(oldp+4402,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_cntvaluein),5); - bufp->chgCData(oldp+4403,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_cntvaluein),5); - bufp->chgCData(oldp+4404,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_cntvaluein),5); - bufp->chgCData(oldp+4405,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_cntvaluein),5); - bufp->chgCData(oldp+4406,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_ld),8); - bufp->chgCData(oldp+4407,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_ld),8); - bufp->chgCData(oldp+4408,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_ld),8); - bufp->chgCData(oldp+4409,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_ld),8); - bufp->chgCData(oldp+4410,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane),3); - bufp->chgIData(oldp+4411,(vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result),32); - bufp->chgSData(oldp+4412,(((IData)(vlSelf->main__DOT__wb32_ddr3_phy_stall) - << 0xbU)),12); - } - if (VL_UNLIKELY(vlSelf->__Vm_traceActivity[4U])) { - bufp->chgBit(oldp+4413,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->chgBit(oldp+4414,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->chgBit(oldp+4415,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->chgBit(oldp+4416,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->chgBit(oldp+4417,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - } - if (VL_UNLIKELY(vlSelf->__Vm_traceActivity[5U])) { - bufp->chgBit(oldp+4418,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc)))); - bufp->chgBit(oldp+4419,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)))); - bufp->chgBit(oldp+4420,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)))); - bufp->chgIData(oldp+4421,((0x3fffffU & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U])),22); - __Vtemp_hf82de6ac__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0U]; - __Vtemp_hf82de6ac__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[1U]; - __Vtemp_hf82de6ac__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[2U]; - __Vtemp_hf82de6ac__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[3U]; - __Vtemp_hf82de6ac__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[4U]; - __Vtemp_hf82de6ac__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[5U]; - __Vtemp_hf82de6ac__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[6U]; - __Vtemp_hf82de6ac__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[7U]; - __Vtemp_hf82de6ac__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[8U]; - __Vtemp_hf82de6ac__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[9U]; - __Vtemp_hf82de6ac__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xaU]; - __Vtemp_hf82de6ac__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xbU]; - __Vtemp_hf82de6ac__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xcU]; - __Vtemp_hf82de6ac__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xdU]; - __Vtemp_hf82de6ac__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xeU]; - __Vtemp_hf82de6ac__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xfU]; - bufp->chgWData(oldp+4422,(__Vtemp_hf82de6ac__0),512); - bufp->chgQData(oldp+4438,((((QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[0U])))),64); - bufp->chgBit(oldp+4440,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err)); - bufp->chgBit(oldp+4441,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 1U)))); - bufp->chgBit(oldp+4442,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 1U)))); - bufp->chgBit(oldp+4443,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe) - >> 1U)))); - bufp->chgIData(oldp+4444,((0x3fffffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - << 0xaU) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - >> 0x16U)))),22); - __Vtemp_hf74e670c__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x10U]; - __Vtemp_hf74e670c__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x11U]; - __Vtemp_hf74e670c__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x12U]; - __Vtemp_hf74e670c__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x13U]; - __Vtemp_hf74e670c__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x14U]; - __Vtemp_hf74e670c__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x15U]; - __Vtemp_hf74e670c__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x16U]; - __Vtemp_hf74e670c__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x17U]; - __Vtemp_hf74e670c__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x18U]; - __Vtemp_hf74e670c__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x19U]; - __Vtemp_hf74e670c__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1aU]; - __Vtemp_hf74e670c__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1bU]; - __Vtemp_hf74e670c__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1cU]; - __Vtemp_hf74e670c__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1dU]; - __Vtemp_hf74e670c__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1eU]; - __Vtemp_hf74e670c__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1fU]; - bufp->chgWData(oldp+4445,(__Vtemp_hf74e670c__0),512); - bufp->chgQData(oldp+4461,((((QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[3U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[2U])))),64); - bufp->chgBit(oldp+4463,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 2U)))); - bufp->chgBit(oldp+4464,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 2U)))); - bufp->chgBit(oldp+4465,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe) - >> 2U)))); - bufp->chgIData(oldp+4466,((0x3fffffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0x14U) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0xcU)))),22); - __Vtemp_h21e563ec__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x20U]; - __Vtemp_h21e563ec__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x21U]; - __Vtemp_h21e563ec__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x22U]; - __Vtemp_h21e563ec__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x23U]; - __Vtemp_h21e563ec__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x24U]; - __Vtemp_h21e563ec__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x25U]; - __Vtemp_h21e563ec__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x26U]; - __Vtemp_h21e563ec__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x27U]; - __Vtemp_h21e563ec__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x28U]; - __Vtemp_h21e563ec__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x29U]; - __Vtemp_h21e563ec__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2aU]; - __Vtemp_h21e563ec__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2bU]; - __Vtemp_h21e563ec__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2cU]; - __Vtemp_h21e563ec__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2dU]; - __Vtemp_h21e563ec__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2eU]; - __Vtemp_h21e563ec__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2fU]; - bufp->chgWData(oldp+4467,(__Vtemp_h21e563ec__0),512); - bufp->chgQData(oldp+4483,((((QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[5U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[4U])))),64); - bufp->chgBit(oldp+4485,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)); - bufp->chgBit(oldp+4486,(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - bufp->chgBit(oldp+4487,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 9U)))); - bufp->chgBit(oldp+4488,((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) & - (0U == (0x700U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))))); - bufp->chgBit(oldp+4489,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 9U)))); - bufp->chgIData(oldp+4490,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U]),32); - bufp->chgCData(oldp+4491,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x24U)))),4); - bufp->chgBit(oldp+4492,((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) & - (0x100U == - (0x700U & - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))))); - bufp->chgBit(oldp+4493,(vlSelf->main__DOT__wb32_sirefclk_stb)); - bufp->chgBit(oldp+4494,(vlSelf->main__DOT__wb32_spio_stb)); - bufp->chgBit(oldp+4495,((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) & - (0x400U == - (0x700U & - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))))); - bufp->chgBit(oldp+4496,((1U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)))); - bufp->chgBit(oldp+4497,((1U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb)))); - bufp->chgBit(oldp+4498,((1U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)))); - bufp->chgCData(oldp+4499,((0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])),8); - bufp->chgIData(oldp+4500,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0U]),32); - bufp->chgCData(oldp+4501,((0xfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))),4); - bufp->chgBit(oldp+4502,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 1U)))); - bufp->chgBit(oldp+4503,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 1U)))); - bufp->chgBit(oldp+4504,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 1U)))); - bufp->chgCData(oldp+4505,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U))),8); - bufp->chgIData(oldp+4506,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[1U]),32); - bufp->chgCData(oldp+4507,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 4U)))),4); - bufp->chgBit(oldp+4508,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 2U)))); - bufp->chgBit(oldp+4509,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 2U)))); - bufp->chgBit(oldp+4510,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 2U)))); - bufp->chgCData(oldp+4511,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U))),8); - bufp->chgIData(oldp+4512,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[2U]),32); - bufp->chgCData(oldp+4513,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 8U)))),4); - bufp->chgBit(oldp+4514,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 3U)))); - bufp->chgBit(oldp+4515,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 3U)))); - bufp->chgBit(oldp+4516,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 3U)))); - bufp->chgCData(oldp+4517,((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x18U)),8); - bufp->chgIData(oldp+4518,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U]),32); - bufp->chgCData(oldp+4519,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xcU)))),4); - bufp->chgBit(oldp+4520,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 4U)))); - bufp->chgBit(oldp+4521,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 4U)))); - bufp->chgBit(oldp+4522,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 4U)))); - bufp->chgCData(oldp+4523,((0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])),8); - bufp->chgIData(oldp+4524,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[4U]),32); - bufp->chgCData(oldp+4525,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x10U)))),4); - bufp->chgBit(oldp+4526,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 5U)))); - bufp->chgBit(oldp+4527,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 5U)))); - bufp->chgBit(oldp+4528,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 5U)))); - bufp->chgCData(oldp+4529,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 8U))),8); - bufp->chgIData(oldp+4530,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[5U]),32); - bufp->chgCData(oldp+4531,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x14U)))),4); - bufp->chgBit(oldp+4532,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 6U)))); - bufp->chgBit(oldp+4533,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U)))); - bufp->chgBit(oldp+4534,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U)))); - bufp->chgCData(oldp+4535,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U))),8); - bufp->chgIData(oldp+4536,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]),32); - bufp->chgCData(oldp+4537,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U)))),4); - bufp->chgBit(oldp+4538,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 7U)))); - bufp->chgBit(oldp+4539,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 7U)))); - bufp->chgBit(oldp+4540,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 7U)))); - bufp->chgCData(oldp+4541,((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U)),8); - bufp->chgIData(oldp+4542,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U]),32); - bufp->chgCData(oldp+4543,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1cU)))),4); - bufp->chgBit(oldp+4544,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 8U)))); - bufp->chgBit(oldp+4545,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U)))); - bufp->chgBit(oldp+4546,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U)))); - bufp->chgCData(oldp+4547,((0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])),8); - bufp->chgIData(oldp+4548,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]),32); - bufp->chgCData(oldp+4549,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U)))),4); - bufp->chgBit(oldp+4550,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U)))); - bufp->chgCData(oldp+4551,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - >> 8U))),8); - bufp->chgBit(oldp+4552,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 0xaU)))); - bufp->chgBit(oldp+4553,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 0xaU)))); - bufp->chgBit(oldp+4554,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 0xaU)))); - bufp->chgCData(oldp+4555,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - >> 0x10U))),8); - bufp->chgIData(oldp+4556,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0xaU]),32); - bufp->chgCData(oldp+4557,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x28U)))),4); - bufp->chgBit(oldp+4558,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 0xbU)))); - bufp->chgBit(oldp+4559,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 0xbU)))); - bufp->chgBit(oldp+4560,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 0xbU)))); - bufp->chgCData(oldp+4561,((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - >> 0x18U)),8); - bufp->chgIData(oldp+4562,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0xbU]),32); - bufp->chgCData(oldp+4563,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x2cU)))),4); - bufp->chgSData(oldp+4564,((0x3fffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - << 0xaU) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - >> 0x16U)))),14); - bufp->chgCData(oldp+4565,((3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 8U))),2); - bufp->chgIData(oldp+4566,((0x1fffffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0x14U) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0xcU)))),21); - bufp->chgIData(oldp+4567,((0x7fU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - >> 0x18U))),32); - bufp->chgIData(oldp+4568,((0x1fffffU & ((IData)(5U) - + ( - (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0x14U) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0xcU))))),21); - bufp->chgBit(oldp+4569,((1U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]))); - bufp->chgBit(oldp+4570,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe))))); - bufp->chgBit(oldp+4571,(vlSelf->main__DOT__emmcscopei__DOT__read_from_data)); - bufp->chgBit(oldp+4572,(vlSelf->main__DOT__emmcscopei__DOT__write_to_control)); - bufp->chgCData(oldp+4573,((3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x18U))),2); - bufp->chgBit(oldp+4574,(vlSelf->main__DOT__i2ci__DOT__next_valid)); - bufp->chgCData(oldp+4575,(vlSelf->main__DOT__i2ci__DOT__next_insn),8); - bufp->chgBit(oldp+4576,((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 3U) & (~ - ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 3U)))))); - bufp->chgBit(oldp+4577,(vlSelf->main__DOT__i2ci__DOT__bus_write)); - bufp->chgBit(oldp+4578,(vlSelf->main__DOT__i2ci__DOT__bus_override)); - bufp->chgBit(oldp+4579,(vlSelf->main__DOT__i2ci__DOT__bus_manual)); - bufp->chgBit(oldp+4580,(vlSelf->main__DOT__i2ci__DOT__bus_jump)); - bufp->chgBit(oldp+4581,((1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U)))); - bufp->chgBit(oldp+4582,((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 1U)))); - bufp->chgBit(oldp+4583,(vlSelf->main__DOT__i2cscopei__DOT__read_from_data)); - bufp->chgBit(oldp+4584,(vlSelf->main__DOT__i2cscopei__DOT__write_to_control)); - bufp->chgBit(oldp+4585,((1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U)))); - bufp->chgBit(oldp+4586,((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 2U)))); - bufp->chgBit(oldp+4587,(vlSelf->main__DOT__sdioscopei__DOT__read_from_data)); - bufp->chgBit(oldp+4588,(vlSelf->main__DOT__sdioscopei__DOT__write_to_control)); - bufp->chgCData(oldp+4589,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn),5); - bufp->chgBit(oldp+4590,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_int)); - bufp->chgCData(oldp+4591,((7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U))),3); - bufp->chgBit(oldp+4592,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)); - bufp->chgBit(oldp+4593,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb)); - bufp->chgCData(oldp+4594,((7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U))),3); - bufp->chgBit(oldp+4595,(vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb)); - bufp->chgCData(oldp+4596,((3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U))),2); - bufp->chgBit(oldp+4597,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid)); - bufp->chgCData(oldp+4598,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn),8); - bufp->chgBit(oldp+4599,(((IData)(vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb) - & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 7U))))); - bufp->chgBit(oldp+4600,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write)); - bufp->chgBit(oldp+4601,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override)); - bufp->chgBit(oldp+4602,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual)); - bufp->chgBit(oldp+4603,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump)); - bufp->chgCData(oldp+4604,((3U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])),2); - bufp->chgIData(oldp+4605,(vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr),32); - bufp->chgIData(oldp+4606,(vlSelf->main__DOT__u_i2cdma__DOT__next_memlen),32); - bufp->chgCData(oldp+4607,((7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])),3); - bufp->chgBit(oldp+4608,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)); - bufp->chgBit(oldp+4609,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb)); - bufp->chgCData(oldp+4610,((0xfU & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U])),4); - bufp->chgCData(oldp+4611,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__i_subaddr),4); - bufp->chgIData(oldp+4612,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm),32); - bufp->chgSData(oldp+4613,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc),12); - bufp->chgSData(oldp+4614,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb),12); - bufp->chgSData(oldp+4615,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe),12); - bufp->chgWData(oldp+4616,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr),96); - bufp->chgWData(oldp+4619,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata),384); - bufp->chgQData(oldp+4631,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel),48); - bufp->chgSData(oldp+4633,(vlSelf->main__DOT__wb32_xbar__DOT__request[0]),13); - bufp->chgSData(oldp+4634,(vlSelf->main__DOT__wb32_xbar__DOT__sgrant),12); - bufp->chgCData(oldp+4635,(vlSelf->main__DOT__wb32_xbar__DOT__mindex[0]),4); - bufp->chgBit(oldp+4636,(vlSelf->main__DOT__wb32_xbar__DOT__m_stb)); - bufp->chgBit(oldp+4637,((1U & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> 0x24U))))); - bufp->chgCData(oldp+4638,(vlSelf->main__DOT__wb32_xbar__DOT__m_addr[0]),8); - bufp->chgIData(oldp+4639,(vlSelf->main__DOT__wb32_xbar__DOT__m_data[0]),32); - bufp->chgCData(oldp+4640,(vlSelf->main__DOT__wb32_xbar__DOT__m_sel[0]),4); - bufp->chgBit(oldp+4641,(vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb)); - bufp->chgSData(oldp+4642,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),13); - bufp->chgBit(oldp+4643,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)); - bufp->chgBit(oldp+4644,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available)); - bufp->chgCData(oldp+4645,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),4); - bufp->chgBit(oldp+4646,((1U & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x2cU))))); - bufp->chgCData(oldp+4647,((0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))),8); - bufp->chgIData(oldp+4648,((IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 4U))),32); - bufp->chgCData(oldp+4649,((0xfU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data))),4); - bufp->chgQData(oldp+4650,((((QData)((IData)( - (1U - & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x2cU))))) - << 0x24U) | (0xfffffffffULL - & vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data))),37); - bufp->chgQData(oldp+4652,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data),37); - bufp->chgSData(oldp+4654,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest),12); - bufp->chgQData(oldp+4655,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data),45); - bufp->chgCData(oldp+4657,(vlSelf->main__DOT__wbu_xbar__DOT__mindex[0]),2); - bufp->chgCData(oldp+4658,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),3); - bufp->chgCData(oldp+4659,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->chgCData(oldp+4660,(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc),4); - bufp->chgCData(oldp+4661,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc),3); - bufp->chgCData(oldp+4662,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb),3); - bufp->chgCData(oldp+4663,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe),3); - bufp->chgWData(oldp+4664,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr),66); - bufp->chgWData(oldp+4667,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata),1536); - bufp->chgWData(oldp+4715,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel),192); - bufp->chgCData(oldp+4721,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err),3); - bufp->chgCData(oldp+4722,(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant),3); - bufp->chgCData(oldp+4723,(vlSelf->main__DOT__wbwide_xbar__DOT__mindex[0]),2); - bufp->chgCData(oldp+4724,(vlSelf->main__DOT__wbwide_xbar__DOT__mindex[1]),2); - bufp->chgCData(oldp+4725,(vlSelf->main__DOT__wbwide_xbar__DOT__mindex[2]),2); - bufp->chgCData(oldp+4726,(vlSelf->main__DOT__wbwide_xbar__DOT__mindex[3]),2); - bufp->chgCData(oldp+4727,(vlSelf->main__DOT__wbwide_xbar__DOT__sindex[0]),2); - bufp->chgCData(oldp+4728,(vlSelf->main__DOT__wbwide_xbar__DOT__sindex[1]),2); - bufp->chgCData(oldp+4729,(vlSelf->main__DOT__wbwide_xbar__DOT__sindex[2]),2); - bufp->chgCData(oldp+4730,(vlSelf->main__DOT__wbwide_xbar__DOT__sindex[3]),2); - bufp->chgCData(oldp+4731,(vlSelf->main__DOT__wbwide_xbar__DOT__m_we),4); - bufp->chgIData(oldp+4732,(vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[0]),22); - bufp->chgIData(oldp+4733,(vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[1]),22); - bufp->chgIData(oldp+4734,(vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[2]),22); - bufp->chgIData(oldp+4735,(vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[3]),22); - bufp->chgWData(oldp+4736,(vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0]),512); - bufp->chgWData(oldp+4752,(vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1]),512); - bufp->chgWData(oldp+4768,(vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2]),512); - bufp->chgWData(oldp+4784,(vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3]),512); - bufp->chgQData(oldp+4800,(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[0]),64); - bufp->chgQData(oldp+4802,(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[1]),64); - bufp->chgQData(oldp+4804,(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[2]),64); - bufp->chgQData(oldp+4806,(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[3]),64); - bufp->chgCData(oldp+4808,(vlSelf->main__DOT__wbwide_xbar__DOT__s_err),4); - bufp->chgCData(oldp+4809,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),4); - bufp->chgBit(oldp+4810,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available)); - bufp->chgCData(oldp+4811,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->chgCData(oldp+4812,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),4); - bufp->chgBit(oldp+4813,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available)); - bufp->chgCData(oldp+4814,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->chgCData(oldp+4815,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),4); - bufp->chgBit(oldp+4816,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available)); - bufp->chgCData(oldp+4817,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->chgCData(oldp+4818,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),4); - bufp->chgBit(oldp+4819,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__requested_channel_is_available)); - bufp->chgCData(oldp+4820,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->chgCData(oldp+4821,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant),4); - bufp->chgCData(oldp+4822,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex),2); - bufp->chgCData(oldp+4823,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant),4); - bufp->chgCData(oldp+4824,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex),2); - bufp->chgCData(oldp+4825,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant),4); - bufp->chgCData(oldp+4826,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex),2); - } - if (VL_UNLIKELY(vlSelf->__Vm_traceActivity[6U])) { - bufp->chgBit(oldp+4827,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall)); - bufp->chgBit(oldp+4828,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall)); - bufp->chgCData(oldp+4829,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d),8); - bufp->chgSData(oldp+4830,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[0]),14); - bufp->chgSData(oldp+4831,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[1]),14); - bufp->chgSData(oldp+4832,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[2]),14); - bufp->chgSData(oldp+4833,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[3]),14); - bufp->chgSData(oldp+4834,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[4]),14); - bufp->chgSData(oldp+4835,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[5]),14); - bufp->chgSData(oldp+4836,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[6]),14); - bufp->chgSData(oldp+4837,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[7]),14); - bufp->chgCData(oldp+4838,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[0]),4); - bufp->chgCData(oldp+4839,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[1]),4); - bufp->chgCData(oldp+4840,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[2]),4); - bufp->chgCData(oldp+4841,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[3]),4); - bufp->chgCData(oldp+4842,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[4]),4); - bufp->chgCData(oldp+4843,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[5]),4); - bufp->chgCData(oldp+4844,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[6]),4); - bufp->chgCData(oldp+4845,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[7]),4); - bufp->chgCData(oldp+4846,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[0]),4); - bufp->chgCData(oldp+4847,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[1]),4); - bufp->chgCData(oldp+4848,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[2]),4); - bufp->chgCData(oldp+4849,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[3]),4); - bufp->chgCData(oldp+4850,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[4]),4); - bufp->chgCData(oldp+4851,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[5]),4); - bufp->chgCData(oldp+4852,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[6]),4); - bufp->chgCData(oldp+4853,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[7]),4); - bufp->chgCData(oldp+4854,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[0]),4); - bufp->chgCData(oldp+4855,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[1]),4); - bufp->chgCData(oldp+4856,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[2]),4); - bufp->chgCData(oldp+4857,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[3]),4); - bufp->chgCData(oldp+4858,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[4]),4); - bufp->chgCData(oldp+4859,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[5]),4); - bufp->chgCData(oldp+4860,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[6]),4); - bufp->chgCData(oldp+4861,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[7]),4); - bufp->chgCData(oldp+4862,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[0]),4); - bufp->chgCData(oldp+4863,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[1]),4); - bufp->chgCData(oldp+4864,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[2]),4); - bufp->chgCData(oldp+4865,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[3]),4); - bufp->chgCData(oldp+4866,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[4]),4); - bufp->chgCData(oldp+4867,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[5]),4); - bufp->chgCData(oldp+4868,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[6]),4); - bufp->chgCData(oldp+4869,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[7]),4); - bufp->chgIData(oldp+4870,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0]),24); - bufp->chgIData(oldp+4871,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1]),24); - bufp->chgIData(oldp+4872,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2]),24); - bufp->chgIData(oldp+4873,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3]),24); - bufp->chgBit(oldp+4874,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt)); - bufp->chgBit(oldp+4875,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en)); - bufp->chgBit(oldp+4876,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n)); - bufp->chgBit(oldp+4877,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_d)); - bufp->chgBit(oldp+4878,(vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy)); - bufp->chgBit(oldp+4879,(vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy)); - bufp->chgBit(oldp+4880,(vlSelf->main__DOT__wb32_xbar__DOT__m_stall)); - bufp->chgSData(oldp+4881,(vlSelf->main__DOT__wb32_xbar__DOT__s_stall),16); - bufp->chgBit(oldp+4882,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)); - bufp->chgBit(oldp+4883,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall)); - bufp->chgBit(oldp+4884,((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall))))); - bufp->chgCData(oldp+4885,(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall),4); - bufp->chgCData(oldp+4886,(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall),4); - bufp->chgCData(oldp+4887,(vlSelf->main__DOT__wbwide_xbar__DOT__s_ack),4); - bufp->chgBit(oldp+4888,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)); - bufp->chgBit(oldp+4889,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall)); - bufp->chgBit(oldp+4890,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall))))); - bufp->chgBit(oldp+4891,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall)); - bufp->chgBit(oldp+4892,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall)); - bufp->chgBit(oldp+4893,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall))))); - bufp->chgBit(oldp+4894,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall)); - bufp->chgBit(oldp+4895,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall)); - bufp->chgBit(oldp+4896,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall))))); - bufp->chgBit(oldp+4897,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall)); - bufp->chgBit(oldp+4898,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall)); - bufp->chgBit(oldp+4899,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall))))); - } - bufp->chgBit(oldp+4900,(vlSelf->i_clk)); - bufp->chgBit(oldp+4901,(vlSelf->i_reset)); - bufp->chgWData(oldp+4902,(vlSelf->i_ddr3_controller_iserdes_data),512); - bufp->chgQData(oldp+4918,(vlSelf->i_ddr3_controller_iserdes_dqs),64); - bufp->chgQData(oldp+4920,(vlSelf->i_ddr3_controller_iserdes_bitslip_reference),64); - bufp->chgBit(oldp+4922,(vlSelf->i_ddr3_controller_idelayctrl_rdy)); - bufp->chgWData(oldp+4923,(vlSelf->o_ddr3_controller_cmd),96); - bufp->chgBit(oldp+4926,(vlSelf->o_ddr3_controller_dqs_tri_control)); - bufp->chgBit(oldp+4927,(vlSelf->o_ddr3_controller_dq_tri_control)); - bufp->chgBit(oldp+4928,(vlSelf->o_ddr3_controller_toggle_dqs)); - bufp->chgWData(oldp+4929,(vlSelf->o_ddr3_controller_data),512); - bufp->chgQData(oldp+4945,(vlSelf->o_ddr3_controller_dm),64); - bufp->chgCData(oldp+4947,(vlSelf->o_ddr3_controller_odelay_data_cntvaluein),5); - bufp->chgCData(oldp+4948,(vlSelf->o_ddr3_controller_odelay_dqs_cntvaluein),5); - bufp->chgCData(oldp+4949,(vlSelf->o_ddr3_controller_idelay_data_cntvaluein),5); - bufp->chgCData(oldp+4950,(vlSelf->o_ddr3_controller_idelay_dqs_cntvaluein),5); - bufp->chgCData(oldp+4951,(vlSelf->o_ddr3_controller_odelay_data_ld),8); - bufp->chgCData(oldp+4952,(vlSelf->o_ddr3_controller_odelay_dqs_ld),8); - bufp->chgCData(oldp+4953,(vlSelf->o_ddr3_controller_idelay_data_ld),8); - bufp->chgCData(oldp+4954,(vlSelf->o_ddr3_controller_idelay_dqs_ld),8); - bufp->chgCData(oldp+4955,(vlSelf->o_ddr3_controller_bitslip),8); - bufp->chgCData(oldp+4956,(vlSelf->o_sirefclk_word),8); - bufp->chgBit(oldp+4957,(vlSelf->o_sirefclk_ce)); - bufp->chgBit(oldp+4958,(vlSelf->i_fan_sda)); - bufp->chgBit(oldp+4959,(vlSelf->i_fan_scl)); - bufp->chgBit(oldp+4960,(vlSelf->o_fan_sda)); - bufp->chgBit(oldp+4961,(vlSelf->o_fan_scl)); - bufp->chgBit(oldp+4962,(vlSelf->o_fpga_pwm)); - bufp->chgBit(oldp+4963,(vlSelf->o_sys_pwm)); - bufp->chgBit(oldp+4964,(vlSelf->i_fan_tach)); - bufp->chgBit(oldp+4965,(vlSelf->o_emmc_clk)); - bufp->chgBit(oldp+4966,(vlSelf->i_emmc_ds)); - bufp->chgBit(oldp+4967,(vlSelf->io_emmc_cmd_tristate)); - bufp->chgBit(oldp+4968,(vlSelf->o_emmc_cmd)); - bufp->chgBit(oldp+4969,(vlSelf->i_emmc_cmd)); - bufp->chgCData(oldp+4970,(vlSelf->io_emmc_dat_tristate),8); - bufp->chgCData(oldp+4971,(vlSelf->o_emmc_dat),8); - bufp->chgCData(oldp+4972,(vlSelf->i_emmc_dat),8); - bufp->chgBit(oldp+4973,(vlSelf->i_emmc_detect)); - bufp->chgBit(oldp+4974,(vlSelf->i_i2c_sda)); - bufp->chgBit(oldp+4975,(vlSelf->i_i2c_scl)); - bufp->chgBit(oldp+4976,(vlSelf->o_i2c_sda)); - bufp->chgBit(oldp+4977,(vlSelf->o_i2c_scl)); - bufp->chgBit(oldp+4978,(vlSelf->o_sdcard_clk)); - bufp->chgBit(oldp+4979,(vlSelf->i_sdcard_ds)); - bufp->chgBit(oldp+4980,(vlSelf->io_sdcard_cmd_tristate)); - bufp->chgBit(oldp+4981,(vlSelf->o_sdcard_cmd)); - bufp->chgBit(oldp+4982,(vlSelf->i_sdcard_cmd)); - bufp->chgCData(oldp+4983,(vlSelf->io_sdcard_dat_tristate),4); - bufp->chgCData(oldp+4984,(vlSelf->o_sdcard_dat),4); - bufp->chgCData(oldp+4985,(vlSelf->i_sdcard_dat),4); - bufp->chgBit(oldp+4986,(vlSelf->i_sdcard_detect)); - bufp->chgBit(oldp+4987,(vlSelf->cpu_sim_cyc)); - bufp->chgBit(oldp+4988,(vlSelf->cpu_sim_stb)); - bufp->chgBit(oldp+4989,(vlSelf->cpu_sim_we)); - bufp->chgCData(oldp+4990,(vlSelf->cpu_sim_addr),7); - bufp->chgIData(oldp+4991,(vlSelf->cpu_sim_data),32); - bufp->chgBit(oldp+4992,(vlSelf->cpu_sim_stall)); - bufp->chgBit(oldp+4993,(vlSelf->cpu_sim_ack)); - bufp->chgIData(oldp+4994,(vlSelf->cpu_sim_idata),32); - bufp->chgBit(oldp+4995,(vlSelf->cpu_prof_stb)); - bufp->chgIData(oldp+4996,(vlSelf->cpu_prof_addr),28); - bufp->chgIData(oldp+4997,(vlSelf->cpu_prof_ticks),32); - bufp->chgBit(oldp+4998,(vlSelf->i_cpu_reset)); - bufp->chgBit(oldp+4999,(vlSelf->i_wbu_uart_rx)); - bufp->chgBit(oldp+5000,(vlSelf->o_wbu_uart_tx)); - bufp->chgBit(oldp+5001,(vlSelf->o_wbu_uart_cts_n)); - bufp->chgSData(oldp+5002,(vlSelf->i_gpio),16); - bufp->chgCData(oldp+5003,(vlSelf->o_gpio),8); - bufp->chgCData(oldp+5004,(vlSelf->i_sw),8); - bufp->chgCData(oldp+5005,(vlSelf->i_btn),5); - bufp->chgCData(oldp+5006,(vlSelf->o_led),8); - bufp->chgBit(oldp+5007,(vlSelf->i_clk200)); - bufp->chgIData(oldp+5008,((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted) - << 0x1fU) | ((0x40000000U - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data) - << 0x15U)) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort) - << 0x1dU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch) - << 0x1cU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn) - << 0x18U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait) - << 0x17U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request) - << 0x16U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted) - << 0x15U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl) - << 0xfU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda) - << 0xeU) - | (((IData)(vlSelf->i_fan_scl) - << 0xdU) - | (((IData)(vlSelf->i_fan_sda) - << 0xcU) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))))))))))))))))))),32); - bufp->chgIData(oldp+5009,((((IData)(vlSelf->main__DOT__gpioi__DOT__r_gpio) - << 0x10U) | (IData)(vlSelf->o_gpio))),32); - bufp->chgBit(oldp+5010,(((IData)(vlSelf->cpu_sim_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)))); - bufp->chgBit(oldp+5011,(((~ (IData)(vlSelf->cpu_sim_cyc)) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)))); - bufp->chgBit(oldp+5012,(vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n)); - bufp->chgSData(oldp+5013,(vlSelf->o_gpio),16); - bufp->chgBit(oldp+5014,(vlSelf->main__DOT____Vcellinp__swic__i_reset)); - bufp->chgCData(oldp+5015,(((IData)(vlSelf->cpu_sim_cyc) - ? 0xfU : (0xfU & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel) - >> 4U)))),4); - bufp->chgIData(oldp+5016,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc),28); - bufp->chgBit(oldp+5017,((((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F) - >> 3U)) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA) - & (IData)( - ((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))) - & ((0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - & (IData)( - ((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))) - & ((0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))))) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR) - & (IData)(((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U))))))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write))))); - bufp->chgBit(oldp+5018,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim)); - bufp->chgIData(oldp+5019,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim_immv),23); - bufp->chgBit(oldp+5020,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid)); - bufp->chgBit(oldp+5021,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim)); - bufp->chgIData(oldp+5022,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv),23); - bufp->chgBit(oldp+5023,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim)); - bufp->chgIData(oldp+5024,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv),23); - bufp->chgBit(oldp+5025,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce)); - bufp->chgIData(oldp+5026,((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn) - << 0x1cU) | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual) - << 0x18U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait) - << 0x17U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request) - << 0x16U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted) - << 0x15U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl) - << 0xfU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda) - << 0xeU) - | (((IData)(vlSelf->i_fan_scl) - << 0xdU) - | (((IData)(vlSelf->i_fan_sda) - << 0xcU) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)))))))))))))))),32); - bufp->chgBit(oldp+5027,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U)) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - bufp->chgCData(oldp+5028,((3U & (- (IData)((1U - & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U))))))),2); - bufp->chgBit(oldp+5029,((1U & (IData)(vlSelf->i_sdcard_dat)))); - bufp->chgBit(oldp+5030,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x19U)) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - bufp->chgCData(oldp+5031,((3U & (- (IData)((1U - & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x19U))))))),2); - bufp->chgBit(oldp+5032,((1U & ((IData)(vlSelf->i_sdcard_dat) - >> 1U)))); - bufp->chgBit(oldp+5033,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1aU)) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - bufp->chgCData(oldp+5034,((3U & (- (IData)((1U - & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1aU))))))),2); - bufp->chgBit(oldp+5035,((1U & ((IData)(vlSelf->i_sdcard_dat) - >> 2U)))); - bufp->chgBit(oldp+5036,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1bU)) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - bufp->chgCData(oldp+5037,((3U & (- (IData)((1U - & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1bU))))))),2); - bufp->chgBit(oldp+5038,((1U & ((IData)(vlSelf->i_sdcard_dat) - >> 3U)))); - bufp->chgBit(oldp+5039,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((~ (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2fU))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_cmd)))))); - bufp->chgCData(oldp+5040,((3U & (- (IData)(((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2fU)))))),2); - bufp->chgSData(oldp+5041,(((0xfffff800U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_ddr3_phy_ack) - << 0xbU))) - | ((0xfffffc00U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__r_cfg_ack) - << 0xaU))) - | ((0xfffffe00U & - ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__r_wb32_sio_ack) - << 9U))) - | ((0xffffff00U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_sdcard_ack) - << 8U))) - | ((0xffffff80U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_fan_ack) - << 7U))) - | ((0xffffffc0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_emmc_ack) - << 6U))) - | ((0xffffffe0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_uart_ack) - << 5U))) - | ((0xfffffff0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_i2cdma_ack) - << 4U))) - | ((0xfffffff8U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_i2cs_ack) - << 3U))) - | ((0xfffffffcU - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack) - << 2U))) - | ((0xfffffffeU - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack)))))))))))))),16); - bufp->chgIData(oldp+5042,(vlSelf->main__DOT__wb32_xbar__DOT__iM),32); - bufp->chgCData(oldp+5043,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),4); - bufp->chgCData(oldp+5044,(((((IData)(vlSelf->cpu_sim_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)) - << 1U) | (IData)(vlSelf->main__DOT__wbu_wbu_arbiter_stall))),2); - bufp->chgCData(oldp+5045,(((((~ (IData)(vlSelf->cpu_sim_cyc)) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)) - << 1U) | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack))),2); - bufp->chgCData(oldp+5046,(((0xfffffffeU & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (((~ (IData)(vlSelf->cpu_sim_cyc)) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack)))),4); - bufp->chgIData(oldp+5047,(vlSelf->main__DOT__wbu_xbar__DOT__iM),32); - bufp->chgCData(oldp+5048,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->chgIData(oldp+5049,(vlSelf->main__DOT__wbwide_xbar__DOT__iN),32); - bufp->chgIData(oldp+5050,(vlSelf->main__DOT__wbwide_xbar__DOT__iM),32); - bufp->chgCData(oldp+5051,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->chgCData(oldp+5052,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->chgCData(oldp+5053,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->chgCData(oldp+5054,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); -} - -void Vmain___024root__trace_cleanup(void* voidSelf, VerilatedVcd* /*unused*/) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root__trace_cleanup\n"); ); - // Init - Vmain___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast(voidSelf); - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - // Body - vlSymsp->__Vm_activity = false; - vlSymsp->TOP.__Vm_traceActivity[0U] = 0U; - vlSymsp->TOP.__Vm_traceActivity[1U] = 0U; - vlSymsp->TOP.__Vm_traceActivity[2U] = 0U; - vlSymsp->TOP.__Vm_traceActivity[3U] = 0U; - vlSymsp->TOP.__Vm_traceActivity[4U] = 0U; - vlSymsp->TOP.__Vm_traceActivity[5U] = 0U; - vlSymsp->TOP.__Vm_traceActivity[6U] = 0U; -} diff --git a/delete_later/rtl/obj_dir/Vmain__Trace__0__Slow.cpp b/delete_later/rtl/obj_dir/Vmain__Trace__0__Slow.cpp deleted file mode 100644 index 5d45889..0000000 --- a/delete_later/rtl/obj_dir/Vmain__Trace__0__Slow.cpp +++ /dev/null @@ -1,11607 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Tracing implementation internals -#include "verilated_vcd_c.h" -#include "Vmain__Syms.h" - - -VL_ATTR_COLD void Vmain___024root__trace_init_sub__TOP__0(Vmain___024root* vlSelf, VerilatedVcd* tracep) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root__trace_init_sub__TOP__0\n"); ); - // Init - const int c = vlSymsp->__Vm_baseCode; - // Body - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declArray(c+4903,"i_ddr3_controller_iserdes_data", false,-1, 511,0); - tracep->declQuad(c+4919,"i_ddr3_controller_iserdes_dqs", false,-1, 63,0); - tracep->declQuad(c+4921,"i_ddr3_controller_iserdes_bitslip_reference", false,-1, 63,0); - tracep->declBit(c+4923,"i_ddr3_controller_idelayctrl_rdy", false,-1); - tracep->declArray(c+4924,"o_ddr3_controller_cmd", false,-1, 95,0); - tracep->declBit(c+4927,"o_ddr3_controller_dqs_tri_control", false,-1); - tracep->declBit(c+4928,"o_ddr3_controller_dq_tri_control", false,-1); - tracep->declBit(c+4929,"o_ddr3_controller_toggle_dqs", false,-1); - tracep->declArray(c+4930,"o_ddr3_controller_data", false,-1, 511,0); - tracep->declQuad(c+4946,"o_ddr3_controller_dm", false,-1, 63,0); - tracep->declBus(c+4948,"o_ddr3_controller_odelay_data_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4949,"o_ddr3_controller_odelay_dqs_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4950,"o_ddr3_controller_idelay_data_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4951,"o_ddr3_controller_idelay_dqs_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4952,"o_ddr3_controller_odelay_data_ld", false,-1, 7,0); - tracep->declBus(c+4953,"o_ddr3_controller_odelay_dqs_ld", false,-1, 7,0); - tracep->declBus(c+4954,"o_ddr3_controller_idelay_data_ld", false,-1, 7,0); - tracep->declBus(c+4955,"o_ddr3_controller_idelay_dqs_ld", false,-1, 7,0); - tracep->declBus(c+4956,"o_ddr3_controller_bitslip", false,-1, 7,0); - tracep->declBus(c+4957,"o_sirefclk_word", false,-1, 7,0); - tracep->declBit(c+4958,"o_sirefclk_ce", false,-1); - tracep->declBit(c+4959,"i_fan_sda", false,-1); - tracep->declBit(c+4960,"i_fan_scl", false,-1); - tracep->declBit(c+4961,"o_fan_sda", false,-1); - tracep->declBit(c+4962,"o_fan_scl", false,-1); - tracep->declBit(c+4963,"o_fpga_pwm", false,-1); - tracep->declBit(c+4964,"o_sys_pwm", false,-1); - tracep->declBit(c+4965,"i_fan_tach", false,-1); - tracep->declBit(c+4966,"o_emmc_clk", false,-1); - tracep->declBit(c+4967,"i_emmc_ds", false,-1); - tracep->declBit(c+4968,"io_emmc_cmd_tristate", false,-1); - tracep->declBit(c+4969,"o_emmc_cmd", false,-1); - tracep->declBit(c+4970,"i_emmc_cmd", false,-1); - tracep->declBus(c+4971,"io_emmc_dat_tristate", false,-1, 7,0); - tracep->declBus(c+4972,"o_emmc_dat", false,-1, 7,0); - tracep->declBus(c+4973,"i_emmc_dat", false,-1, 7,0); - tracep->declBit(c+4974,"i_emmc_detect", false,-1); - tracep->declBit(c+4975,"i_i2c_sda", false,-1); - tracep->declBit(c+4976,"i_i2c_scl", false,-1); - tracep->declBit(c+4977,"o_i2c_sda", false,-1); - tracep->declBit(c+4978,"o_i2c_scl", false,-1); - tracep->declBit(c+4979,"o_sdcard_clk", false,-1); - tracep->declBit(c+4980,"i_sdcard_ds", false,-1); - tracep->declBit(c+4981,"io_sdcard_cmd_tristate", false,-1); - tracep->declBit(c+4982,"o_sdcard_cmd", false,-1); - tracep->declBit(c+4983,"i_sdcard_cmd", false,-1); - tracep->declBus(c+4984,"io_sdcard_dat_tristate", false,-1, 3,0); - tracep->declBus(c+4985,"o_sdcard_dat", false,-1, 3,0); - tracep->declBus(c+4986,"i_sdcard_dat", false,-1, 3,0); - tracep->declBit(c+4987,"i_sdcard_detect", false,-1); - tracep->declBit(c+4988,"cpu_sim_cyc", false,-1); - tracep->declBit(c+4989,"cpu_sim_stb", false,-1); - tracep->declBit(c+4990,"cpu_sim_we", false,-1); - tracep->declBus(c+4991,"cpu_sim_addr", false,-1, 6,0); - tracep->declBus(c+4992,"cpu_sim_data", false,-1, 31,0); - tracep->declBit(c+4993,"cpu_sim_stall", false,-1); - tracep->declBit(c+4994,"cpu_sim_ack", false,-1); - tracep->declBus(c+4995,"cpu_sim_idata", false,-1, 31,0); - tracep->declBit(c+4996,"cpu_prof_stb", false,-1); - tracep->declBus(c+4997,"cpu_prof_addr", false,-1, 27,0); - tracep->declBus(c+4998,"cpu_prof_ticks", false,-1, 31,0); - tracep->declBit(c+4999,"i_cpu_reset", false,-1); - tracep->declBit(c+5000,"i_wbu_uart_rx", false,-1); - tracep->declBit(c+5001,"o_wbu_uart_tx", false,-1); - tracep->declBit(c+5002,"o_wbu_uart_cts_n", false,-1); - tracep->declBus(c+5003,"i_gpio", false,-1, 15,0); - tracep->declBus(c+5004,"o_gpio", false,-1, 7,0); - tracep->declBus(c+5005,"i_sw", false,-1, 7,0); - tracep->declBus(c+5006,"i_btn", false,-1, 4,0); - tracep->declBus(c+5007,"o_led", false,-1, 7,0); - tracep->declBit(c+5008,"i_clk200", false,-1); - tracep->pushNamePrefix("main "); - tracep->declDouble(c+5056,"DDR3_CONTROLLERCONTROLLER_CLK_PERIOD", false,-1); - tracep->declDouble(c+5058,"DDR3_CLK_PERIOD", false,-1); - tracep->declBus(c+5060,"DDR3_CONTROLLERROW_BITS", false,-1, 31,0); - tracep->declBus(c+5061,"DDR3_CONTROLLERCOL_BITS", false,-1, 31,0); - tracep->declBus(c+5062,"DDR3_CONTROLLERBA_BITS", false,-1, 31,0); - tracep->declBus(c+5063,"DDR3_CONTROLLERDQ_BITS", false,-1, 31,0); - tracep->declBus(c+5063,"DDR3_CONTROLLERLANES", false,-1, 31,0); - tracep->declBus(c+5064,"DDR3_CONTROLLERAUX_WIDTH", false,-1, 31,0); - tracep->declBus(c+5065,"DDR3_CONTROLLERSERDES_RATIO", false,-1, 31,0); - tracep->declBus(c+5066,"DDR3_CONTROLLERCMD_LEN", false,-1, 31,0); - tracep->declBus(c+5067,"RESET_ADDRESS", false,-1, 31,0); - tracep->declBus(c+5068,"ZIP_ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5069,"ZIP_INTS", false,-1, 31,0); - tracep->declBus(c+5070,"ZIP_START_HALTED", false,-1, 0,0); - tracep->declBus(c+5071,"BUSUART", false,-1, 23,0); - tracep->declBus(c+5072,"DBGBUSBITS", false,-1, 31,0); - tracep->declBus(c+5069,"DBGBUSWATCHDOG_RAW", false,-1, 31,0); - tracep->declBus(c+5073,"DBGBUSWATCHDOG", false,-1, 31,0); - tracep->declBus(c+5062,"ICAPE_LGDIV", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declArray(c+4903,"i_ddr3_controller_iserdes_data", false,-1, 511,0); - tracep->declQuad(c+4919,"i_ddr3_controller_iserdes_dqs", false,-1, 63,0); - tracep->declQuad(c+4921,"i_ddr3_controller_iserdes_bitslip_reference", false,-1, 63,0); - tracep->declBit(c+4923,"i_ddr3_controller_idelayctrl_rdy", false,-1); - tracep->declArray(c+4924,"o_ddr3_controller_cmd", false,-1, 95,0); - tracep->declBit(c+4927,"o_ddr3_controller_dqs_tri_control", false,-1); - tracep->declBit(c+4928,"o_ddr3_controller_dq_tri_control", false,-1); - tracep->declBit(c+4929,"o_ddr3_controller_toggle_dqs", false,-1); - tracep->declArray(c+4930,"o_ddr3_controller_data", false,-1, 511,0); - tracep->declQuad(c+4946,"o_ddr3_controller_dm", false,-1, 63,0); - tracep->declBus(c+4948,"o_ddr3_controller_odelay_data_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4949,"o_ddr3_controller_odelay_dqs_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4950,"o_ddr3_controller_idelay_data_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4951,"o_ddr3_controller_idelay_dqs_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4952,"o_ddr3_controller_odelay_data_ld", false,-1, 7,0); - tracep->declBus(c+4953,"o_ddr3_controller_odelay_dqs_ld", false,-1, 7,0); - tracep->declBus(c+4954,"o_ddr3_controller_idelay_data_ld", false,-1, 7,0); - tracep->declBus(c+4955,"o_ddr3_controller_idelay_dqs_ld", false,-1, 7,0); - tracep->declBus(c+4956,"o_ddr3_controller_bitslip", false,-1, 7,0); - tracep->declBus(c+4957,"o_sirefclk_word", false,-1, 7,0); - tracep->declBit(c+4958,"o_sirefclk_ce", false,-1); - tracep->declBit(c+4959,"i_fan_sda", false,-1); - tracep->declBit(c+4960,"i_fan_scl", false,-1); - tracep->declBit(c+4961,"o_fan_sda", false,-1); - tracep->declBit(c+4962,"o_fan_scl", false,-1); - tracep->declBit(c+4963,"o_fpga_pwm", false,-1); - tracep->declBit(c+4964,"o_sys_pwm", false,-1); - tracep->declBit(c+4965,"i_fan_tach", false,-1); - tracep->declBit(c+4966,"o_emmc_clk", false,-1); - tracep->declBit(c+4967,"i_emmc_ds", false,-1); - tracep->declBit(c+4968,"io_emmc_cmd_tristate", false,-1); - tracep->declBit(c+4969,"o_emmc_cmd", false,-1); - tracep->declBit(c+4970,"i_emmc_cmd", false,-1); - tracep->declBus(c+4971,"io_emmc_dat_tristate", false,-1, 7,0); - tracep->declBus(c+4972,"o_emmc_dat", false,-1, 7,0); - tracep->declBus(c+4973,"i_emmc_dat", false,-1, 7,0); - tracep->declBit(c+4974,"i_emmc_detect", false,-1); - tracep->declBit(c+4975,"i_i2c_sda", false,-1); - tracep->declBit(c+4976,"i_i2c_scl", false,-1); - tracep->declBit(c+4977,"o_i2c_sda", false,-1); - tracep->declBit(c+4978,"o_i2c_scl", false,-1); - tracep->declBit(c+4979,"o_sdcard_clk", false,-1); - tracep->declBit(c+4980,"i_sdcard_ds", false,-1); - tracep->declBit(c+4981,"io_sdcard_cmd_tristate", false,-1); - tracep->declBit(c+4982,"o_sdcard_cmd", false,-1); - tracep->declBit(c+4983,"i_sdcard_cmd", false,-1); - tracep->declBus(c+4984,"io_sdcard_dat_tristate", false,-1, 3,0); - tracep->declBus(c+4985,"o_sdcard_dat", false,-1, 3,0); - tracep->declBus(c+4986,"i_sdcard_dat", false,-1, 3,0); - tracep->declBit(c+4987,"i_sdcard_detect", false,-1); - tracep->declBit(c+4988,"cpu_sim_cyc", false,-1); - tracep->declBit(c+4989,"cpu_sim_stb", false,-1); - tracep->declBit(c+4990,"cpu_sim_we", false,-1); - tracep->declBus(c+4991,"cpu_sim_addr", false,-1, 6,0); - tracep->declBus(c+4992,"cpu_sim_data", false,-1, 31,0); - tracep->declBit(c+4993,"cpu_sim_stall", false,-1); - tracep->declBit(c+4994,"cpu_sim_ack", false,-1); - tracep->declBus(c+4995,"cpu_sim_idata", false,-1, 31,0); - tracep->declBit(c+4996,"cpu_prof_stb", false,-1); - tracep->declBus(c+4997,"cpu_prof_addr", false,-1, 27,0); - tracep->declBus(c+4998,"cpu_prof_ticks", false,-1, 31,0); - tracep->declBit(c+4999,"i_cpu_reset", false,-1); - tracep->declBit(c+5000,"i_wbu_uart_rx", false,-1); - tracep->declBit(c+5001,"o_wbu_uart_tx", false,-1); - tracep->declBit(c+5002,"o_wbu_uart_cts_n", false,-1); - tracep->declBus(c+5069,"NGPI", false,-1, 31,0); - tracep->declBus(c+5063,"NGPO", false,-1, 31,0); - tracep->declBus(c+5003,"i_gpio", false,-1, 15,0); - tracep->declBus(c+5004,"o_gpio", false,-1, 7,0); - tracep->declBus(c+5005,"i_sw", false,-1, 7,0); - tracep->declBus(c+5006,"i_btn", false,-1, 4,0); - tracep->declBus(c+5007,"o_led", false,-1, 7,0); - tracep->declBit(c+158,"emmcscope_int", false,-1); - tracep->declBit(c+159,"sdioscope_int", false,-1); - tracep->declBit(c+160,"emmc_int", false,-1); - tracep->declBit(c+161,"sdcard_int", false,-1); - tracep->declBit(c+162,"uartrxf_int", false,-1); - tracep->declBit(c+163,"uarttx_int", false,-1); - tracep->declBit(c+164,"uarttxf_int", false,-1); - tracep->declBit(c+165,"uartrx_int", false,-1); - tracep->declBit(c+166,"i2cscope_int", false,-1); - tracep->declBit(c+167,"gpio_int", false,-1); - tracep->declBit(c+168,"spio_int", false,-1); - tracep->declBus(c+4032,"ddr3_controller_aux_out", false,-1, 0,0); - tracep->declBit(c+169,"r_sirefclk_en", false,-1); - tracep->declBus(c+170,"r_sirefclk_data", false,-1, 29,0); - tracep->declBit(c+171,"w_sirefclk_unused_stb", false,-1); - tracep->declBit(c+172,"r_sirefclk_ack", false,-1); - tracep->declBit(c+173,"i2cdma_ready", false,-1); - tracep->declBus(c+5009,"fan_debug", false,-1, 31,0); - tracep->declBit(c+5074,"w_emmc_1p8v", false,-1); - tracep->declBus(c+36,"emmc_debug", false,-1, 31,0); - tracep->declBus(c+5075,"I2C_ID_WIDTH", false,-1, 31,0); - tracep->declBit(c+174,"i2c_valid", false,-1); - tracep->declBit(c+175,"i2c_ready", false,-1); - tracep->declBit(c+176,"i2c_last", false,-1); - tracep->declBus(c+177,"i2c_data", false,-1, 7,0); - tracep->declBus(c+178,"i2c_id", false,-1, 1,0); - tracep->declBus(c+37,"i2c_debug", false,-1, 31,0); - tracep->declBit(c+5074,"w_sdcard_1p8v", false,-1); - tracep->declBus(c+179,"sdcard_debug", false,-1, 31,0); - tracep->declBit(c+180,"w_console_rx_stb", false,-1); - tracep->declBit(c+181,"w_console_tx_stb", false,-1); - tracep->declBit(c+182,"w_console_busy", false,-1); - tracep->declBus(c+183,"w_console_rx_data", false,-1, 6,0); - tracep->declBus(c+184,"w_console_tx_data", false,-1, 6,0); - tracep->declBus(c+185,"uart_debug", false,-1, 31,0); - tracep->declBit(c+186,"raw_cpu_dbg_stall", false,-1); - tracep->declBit(c+187,"raw_cpu_dbg_ack", false,-1); - tracep->declBus(c+5076,"zip_debug", false,-1, 31,0); - tracep->declBit(c+5074,"zip_trigger", false,-1); - tracep->declBus(c+188,"zip_int_vector", false,-1, 15,0); - tracep->declBit(c+189,"zip_cpu_int", false,-1); - tracep->declBit(c+5008,"i_clk200", false,-1); - tracep->declBus(c+190,"wbu_rx_data", false,-1, 7,0); - tracep->declBus(c+191,"wbu_tx_data", false,-1, 7,0); - tracep->declBit(c+192,"wbu_rx_stb", false,-1); - tracep->declBit(c+193,"wbu_tx_stb", false,-1); - tracep->declBit(c+194,"wbu_tx_busy", false,-1); - tracep->declBus(c+195,"wbubus_dbg", false,-1, 0,0); - tracep->declBus(c+5076,"cfg_debug", false,-1, 31,0); - tracep->declBus(c+196,"w_led", false,-1, 7,0); - tracep->declBus(c+197,"sys_int_vector", false,-1, 14,0); - tracep->declBus(c+198,"alt_int_vector", false,-1, 14,0); - tracep->declBit(c+199,"wbwide_i2cdma_cyc", false,-1); - tracep->declBit(c+200,"wbwide_i2cdma_stb", false,-1); - tracep->declBit(c+5077,"wbwide_i2cdma_we", false,-1); - tracep->declBus(c+201,"wbwide_i2cdma_addr", false,-1, 21,0); - tracep->declArray(c+202,"wbwide_i2cdma_data", false,-1, 511,0); - tracep->declQuad(c+218,"wbwide_i2cdma_sel", false,-1, 63,0); - tracep->declBit(c+220,"wbwide_i2cdma_stall", false,-1); - tracep->declBit(c+221,"wbwide_i2cdma_ack", false,-1); - tracep->declBit(c+222,"wbwide_i2cdma_err", false,-1); - tracep->declArray(c+223,"wbwide_i2cdma_idata", false,-1, 511,0); - tracep->declBit(c+239,"wbwide_i2cm_cyc", false,-1); - tracep->declBit(c+240,"wbwide_i2cm_stb", false,-1); - tracep->declBit(c+5074,"wbwide_i2cm_we", false,-1); - tracep->declBus(c+241,"wbwide_i2cm_addr", false,-1, 21,0); - tracep->declArray(c+5078,"wbwide_i2cm_data", false,-1, 511,0); - tracep->declQuad(c+5094,"wbwide_i2cm_sel", false,-1, 63,0); - tracep->declBit(c+242,"wbwide_i2cm_stall", false,-1); - tracep->declBit(c+243,"wbwide_i2cm_ack", false,-1); - tracep->declBit(c+244,"wbwide_i2cm_err", false,-1); - tracep->declArray(c+245,"wbwide_i2cm_idata", false,-1, 511,0); - tracep->declBit(c+261,"wbwide_zip_cyc", false,-1); - tracep->declBit(c+262,"wbwide_zip_stb", false,-1); - tracep->declBit(c+263,"wbwide_zip_we", false,-1); - tracep->declBus(c+264,"wbwide_zip_addr", false,-1, 21,0); - tracep->declArray(c+265,"wbwide_zip_data", false,-1, 511,0); - tracep->declQuad(c+281,"wbwide_zip_sel", false,-1, 63,0); - tracep->declBit(c+283,"wbwide_zip_stall", false,-1); - tracep->declBit(c+284,"wbwide_zip_ack", false,-1); - tracep->declBit(c+285,"wbwide_zip_err", false,-1); - tracep->declArray(c+286,"wbwide_zip_idata", false,-1, 511,0); - tracep->declBit(c+302,"wbwide_wbu_arbiter_cyc", false,-1); - tracep->declBit(c+303,"wbwide_wbu_arbiter_stb", false,-1); - tracep->declBit(c+304,"wbwide_wbu_arbiter_we", false,-1); - tracep->declBus(c+305,"wbwide_wbu_arbiter_addr", false,-1, 21,0); - tracep->declArray(c+306,"wbwide_wbu_arbiter_data", false,-1, 511,0); - tracep->declQuad(c+322,"wbwide_wbu_arbiter_sel", false,-1, 63,0); - tracep->declBit(c+324,"wbwide_wbu_arbiter_stall", false,-1); - tracep->declBit(c+325,"wbwide_wbu_arbiter_ack", false,-1); - tracep->declBit(c+326,"wbwide_wbu_arbiter_err", false,-1); - tracep->declArray(c+327,"wbwide_wbu_arbiter_idata", false,-1, 511,0); - tracep->declBit(c+4419,"wbwide_wbdown_cyc", false,-1); - tracep->declBit(c+4420,"wbwide_wbdown_stb", false,-1); - tracep->declBit(c+4421,"wbwide_wbdown_we", false,-1); - tracep->declBus(c+4422,"wbwide_wbdown_addr", false,-1, 21,0); - tracep->declArray(c+4423,"wbwide_wbdown_data", false,-1, 511,0); - tracep->declQuad(c+4439,"wbwide_wbdown_sel", false,-1, 63,0); - tracep->declBit(c+343,"wbwide_wbdown_stall", false,-1); - tracep->declBit(c+344,"wbwide_wbdown_ack", false,-1); - tracep->declBit(c+4441,"wbwide_wbdown_err", false,-1); - tracep->declArray(c+345,"wbwide_wbdown_idata", false,-1, 511,0); - tracep->declBit(c+4442,"wbwide_bkram_cyc", false,-1); - tracep->declBit(c+4443,"wbwide_bkram_stb", false,-1); - tracep->declBit(c+4444,"wbwide_bkram_we", false,-1); - tracep->declBus(c+4445,"wbwide_bkram_addr", false,-1, 21,0); - tracep->declArray(c+4446,"wbwide_bkram_data", false,-1, 511,0); - tracep->declQuad(c+4462,"wbwide_bkram_sel", false,-1, 63,0); - tracep->declBit(c+5074,"wbwide_bkram_stall", false,-1); - tracep->declBit(c+361,"wbwide_bkram_ack", false,-1); - tracep->declBit(c+5074,"wbwide_bkram_err", false,-1); - tracep->declArray(c+362,"wbwide_bkram_idata", false,-1, 511,0); - tracep->declBit(c+4464,"wbwide_ddr3_controller_cyc", false,-1); - tracep->declBit(c+4465,"wbwide_ddr3_controller_stb", false,-1); - tracep->declBit(c+4466,"wbwide_ddr3_controller_we", false,-1); - tracep->declBus(c+4467,"wbwide_ddr3_controller_addr", false,-1, 21,0); - tracep->declArray(c+4468,"wbwide_ddr3_controller_data", false,-1, 511,0); - tracep->declQuad(c+4484,"wbwide_ddr3_controller_sel", false,-1, 63,0); - tracep->declBit(c+4033,"wbwide_ddr3_controller_stall", false,-1); - tracep->declBit(c+4034,"wbwide_ddr3_controller_ack", false,-1); - tracep->declBit(c+5074,"wbwide_ddr3_controller_err", false,-1); - tracep->declArray(c+4035,"wbwide_ddr3_controller_idata", false,-1, 511,0); - tracep->declBit(c+4486,"wb32_wbdown_cyc", false,-1); - tracep->declBit(c+378,"wb32_wbdown_stb", false,-1); - tracep->declBit(c+379,"wb32_wbdown_we", false,-1); - tracep->declBus(c+380,"wb32_wbdown_addr", false,-1, 7,0); - tracep->declBus(c+381,"wb32_wbdown_data", false,-1, 31,0); - tracep->declBus(c+382,"wb32_wbdown_sel", false,-1, 3,0); - tracep->declBit(c+383,"wb32_wbdown_stall", false,-1); - tracep->declBit(c+384,"wb32_wbdown_ack", false,-1); - tracep->declBit(c+4487,"wb32_wbdown_err", false,-1); - tracep->declBus(c+385,"wb32_wbdown_idata", false,-1, 31,0); - tracep->declBit(c+4488,"wb32_buildtime_cyc", false,-1); - tracep->declBit(c+4489,"wb32_buildtime_stb", false,-1); - tracep->declBit(c+4490,"wb32_buildtime_we", false,-1); - tracep->declBus(c+5096,"wb32_buildtime_addr", false,-1, 7,0); - tracep->declBus(c+4491,"wb32_buildtime_data", false,-1, 31,0); - tracep->declBus(c+4492,"wb32_buildtime_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_buildtime_stall", false,-1); - tracep->declBit(c+4489,"wb32_buildtime_ack", false,-1); - tracep->declBit(c+5097,"wb32_buildtime_err", false,-1); - tracep->declBus(c+5098,"wb32_buildtime_idata", false,-1, 31,0); - tracep->declBit(c+4488,"wb32_gpio_cyc", false,-1); - tracep->declBit(c+4493,"wb32_gpio_stb", false,-1); - tracep->declBit(c+4490,"wb32_gpio_we", false,-1); - tracep->declBus(c+5099,"wb32_gpio_addr", false,-1, 7,0); - tracep->declBus(c+4491,"wb32_gpio_data", false,-1, 31,0); - tracep->declBus(c+4492,"wb32_gpio_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_gpio_stall", false,-1); - tracep->declBit(c+4493,"wb32_gpio_ack", false,-1); - tracep->declBit(c+5100,"wb32_gpio_err", false,-1); - tracep->declBus(c+5010,"wb32_gpio_idata", false,-1, 31,0); - tracep->declBit(c+4488,"wb32_sirefclk_cyc", false,-1); - tracep->declBit(c+4494,"wb32_sirefclk_stb", false,-1); - tracep->declBit(c+4490,"wb32_sirefclk_we", false,-1); - tracep->declBus(c+5101,"wb32_sirefclk_addr", false,-1, 7,0); - tracep->declBus(c+4491,"wb32_sirefclk_data", false,-1, 31,0); - tracep->declBus(c+4492,"wb32_sirefclk_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_sirefclk_stall", false,-1); - tracep->declBit(c+172,"wb32_sirefclk_ack", false,-1); - tracep->declBit(c+5102,"wb32_sirefclk_err", false,-1); - tracep->declBus(c+386,"wb32_sirefclk_idata", false,-1, 31,0); - tracep->declBit(c+4488,"wb32_spio_cyc", false,-1); - tracep->declBit(c+4495,"wb32_spio_stb", false,-1); - tracep->declBit(c+4490,"wb32_spio_we", false,-1); - tracep->declBus(c+5103,"wb32_spio_addr", false,-1, 7,0); - tracep->declBus(c+4491,"wb32_spio_data", false,-1, 31,0); - tracep->declBus(c+4492,"wb32_spio_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_spio_stall", false,-1); - tracep->declBit(c+387,"wb32_spio_ack", false,-1); - tracep->declBit(c+5104,"wb32_spio_err", false,-1); - tracep->declBus(c+388,"wb32_spio_idata", false,-1, 31,0); - tracep->declBit(c+4488,"wb32_version_cyc", false,-1); - tracep->declBit(c+4496,"wb32_version_stb", false,-1); - tracep->declBit(c+4490,"wb32_version_we", false,-1); - tracep->declBus(c+5105,"wb32_version_addr", false,-1, 7,0); - tracep->declBus(c+4491,"wb32_version_data", false,-1, 31,0); - tracep->declBus(c+4492,"wb32_version_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_version_stall", false,-1); - tracep->declBit(c+4496,"wb32_version_ack", false,-1); - tracep->declBit(c+5106,"wb32_version_err", false,-1); - tracep->declBus(c+5107,"wb32_version_idata", false,-1, 31,0); - tracep->declBit(c+4497,"wb32_emmcscope_cyc", false,-1); - tracep->declBit(c+4498,"wb32_emmcscope_stb", false,-1); - tracep->declBit(c+4499,"wb32_emmcscope_we", false,-1); - tracep->declBus(c+4500,"wb32_emmcscope_addr", false,-1, 7,0); - tracep->declBus(c+4501,"wb32_emmcscope_data", false,-1, 31,0); - tracep->declBus(c+4502,"wb32_emmcscope_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_emmcscope_stall", false,-1); - tracep->declBit(c+389,"wb32_emmcscope_ack", false,-1); - tracep->declBit(c+5074,"wb32_emmcscope_err", false,-1); - tracep->declBus(c+390,"wb32_emmcscope_idata", false,-1, 31,0); - tracep->declBit(c+4503,"wb32_i2cscope_cyc", false,-1); - tracep->declBit(c+4504,"wb32_i2cscope_stb", false,-1); - tracep->declBit(c+4505,"wb32_i2cscope_we", false,-1); - tracep->declBus(c+4506,"wb32_i2cscope_addr", false,-1, 7,0); - tracep->declBus(c+4507,"wb32_i2cscope_data", false,-1, 31,0); - tracep->declBus(c+4508,"wb32_i2cscope_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_i2cscope_stall", false,-1); - tracep->declBit(c+391,"wb32_i2cscope_ack", false,-1); - tracep->declBit(c+5074,"wb32_i2cscope_err", false,-1); - tracep->declBus(c+392,"wb32_i2cscope_idata", false,-1, 31,0); - tracep->declBit(c+4509,"wb32_sdioscope_cyc", false,-1); - tracep->declBit(c+4510,"wb32_sdioscope_stb", false,-1); - tracep->declBit(c+4511,"wb32_sdioscope_we", false,-1); - tracep->declBus(c+4512,"wb32_sdioscope_addr", false,-1, 7,0); - tracep->declBus(c+4513,"wb32_sdioscope_data", false,-1, 31,0); - tracep->declBus(c+4514,"wb32_sdioscope_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_sdioscope_stall", false,-1); - tracep->declBit(c+393,"wb32_sdioscope_ack", false,-1); - tracep->declBit(c+5074,"wb32_sdioscope_err", false,-1); - tracep->declBus(c+394,"wb32_sdioscope_idata", false,-1, 31,0); - tracep->declBit(c+4515,"wb32_i2cs_cyc", false,-1); - tracep->declBit(c+4516,"wb32_i2cs_stb", false,-1); - tracep->declBit(c+4517,"wb32_i2cs_we", false,-1); - tracep->declBus(c+4518,"wb32_i2cs_addr", false,-1, 7,0); - tracep->declBus(c+4519,"wb32_i2cs_data", false,-1, 31,0); - tracep->declBus(c+4520,"wb32_i2cs_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_i2cs_stall", false,-1); - tracep->declBit(c+395,"wb32_i2cs_ack", false,-1); - tracep->declBit(c+5074,"wb32_i2cs_err", false,-1); - tracep->declBus(c+396,"wb32_i2cs_idata", false,-1, 31,0); - tracep->declBit(c+4521,"wb32_i2cdma_cyc", false,-1); - tracep->declBit(c+4522,"wb32_i2cdma_stb", false,-1); - tracep->declBit(c+4523,"wb32_i2cdma_we", false,-1); - tracep->declBus(c+4524,"wb32_i2cdma_addr", false,-1, 7,0); - tracep->declBus(c+4525,"wb32_i2cdma_data", false,-1, 31,0); - tracep->declBus(c+4526,"wb32_i2cdma_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_i2cdma_stall", false,-1); - tracep->declBit(c+397,"wb32_i2cdma_ack", false,-1); - tracep->declBit(c+5074,"wb32_i2cdma_err", false,-1); - tracep->declBus(c+398,"wb32_i2cdma_idata", false,-1, 31,0); - tracep->declBit(c+4527,"wb32_uart_cyc", false,-1); - tracep->declBit(c+4528,"wb32_uart_stb", false,-1); - tracep->declBit(c+4529,"wb32_uart_we", false,-1); - tracep->declBus(c+4530,"wb32_uart_addr", false,-1, 7,0); - tracep->declBus(c+4531,"wb32_uart_data", false,-1, 31,0); - tracep->declBus(c+4532,"wb32_uart_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_uart_stall", false,-1); - tracep->declBit(c+399,"wb32_uart_ack", false,-1); - tracep->declBit(c+5074,"wb32_uart_err", false,-1); - tracep->declBus(c+400,"wb32_uart_idata", false,-1, 31,0); - tracep->declBit(c+4533,"wb32_emmc_cyc", false,-1); - tracep->declBit(c+4534,"wb32_emmc_stb", false,-1); - tracep->declBit(c+4535,"wb32_emmc_we", false,-1); - tracep->declBus(c+4536,"wb32_emmc_addr", false,-1, 7,0); - tracep->declBus(c+4537,"wb32_emmc_data", false,-1, 31,0); - tracep->declBus(c+4538,"wb32_emmc_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_emmc_stall", false,-1); - tracep->declBit(c+401,"wb32_emmc_ack", false,-1); - tracep->declBit(c+5074,"wb32_emmc_err", false,-1); - tracep->declBus(c+402,"wb32_emmc_idata", false,-1, 31,0); - tracep->declBit(c+4539,"wb32_fan_cyc", false,-1); - tracep->declBit(c+4540,"wb32_fan_stb", false,-1); - tracep->declBit(c+4541,"wb32_fan_we", false,-1); - tracep->declBus(c+4542,"wb32_fan_addr", false,-1, 7,0); - tracep->declBus(c+4543,"wb32_fan_data", false,-1, 31,0); - tracep->declBus(c+4544,"wb32_fan_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_fan_stall", false,-1); - tracep->declBit(c+403,"wb32_fan_ack", false,-1); - tracep->declBit(c+5074,"wb32_fan_err", false,-1); - tracep->declBus(c+404,"wb32_fan_idata", false,-1, 31,0); - tracep->declBit(c+4545,"wb32_sdcard_cyc", false,-1); - tracep->declBit(c+4546,"wb32_sdcard_stb", false,-1); - tracep->declBit(c+4547,"wb32_sdcard_we", false,-1); - tracep->declBus(c+4548,"wb32_sdcard_addr", false,-1, 7,0); - tracep->declBus(c+4549,"wb32_sdcard_data", false,-1, 31,0); - tracep->declBus(c+4550,"wb32_sdcard_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_sdcard_stall", false,-1); - tracep->declBit(c+405,"wb32_sdcard_ack", false,-1); - tracep->declBit(c+5074,"wb32_sdcard_err", false,-1); - tracep->declBus(c+406,"wb32_sdcard_idata", false,-1, 31,0); - tracep->declBit(c+4488,"wb32_sio_cyc", false,-1); - tracep->declBit(c+4551,"wb32_sio_stb", false,-1); - tracep->declBit(c+4490,"wb32_sio_we", false,-1); - tracep->declBus(c+4552,"wb32_sio_addr", false,-1, 7,0); - tracep->declBus(c+4491,"wb32_sio_data", false,-1, 31,0); - tracep->declBus(c+4492,"wb32_sio_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_sio_stall", false,-1); - tracep->declBit(c+407,"wb32_sio_ack", false,-1); - tracep->declBit(c+5074,"wb32_sio_err", false,-1); - tracep->declBus(c+408,"wb32_sio_idata", false,-1, 31,0); - tracep->declBit(c+4553,"wb32_cfg_cyc", false,-1); - tracep->declBit(c+4554,"wb32_cfg_stb", false,-1); - tracep->declBit(c+4555,"wb32_cfg_we", false,-1); - tracep->declBus(c+4556,"wb32_cfg_addr", false,-1, 7,0); - tracep->declBus(c+4557,"wb32_cfg_data", false,-1, 31,0); - tracep->declBus(c+4558,"wb32_cfg_sel", false,-1, 3,0); - tracep->declBit(c+5074,"wb32_cfg_stall", false,-1); - tracep->declBit(c+409,"wb32_cfg_ack", false,-1); - tracep->declBit(c+5074,"wb32_cfg_err", false,-1); - tracep->declBus(c+5076,"wb32_cfg_idata", false,-1, 31,0); - tracep->declBit(c+4559,"wb32_ddr3_phy_cyc", false,-1); - tracep->declBit(c+4560,"wb32_ddr3_phy_stb", false,-1); - tracep->declBit(c+4561,"wb32_ddr3_phy_we", false,-1); - tracep->declBus(c+4562,"wb32_ddr3_phy_addr", false,-1, 7,0); - tracep->declBus(c+4563,"wb32_ddr3_phy_data", false,-1, 31,0); - tracep->declBus(c+4564,"wb32_ddr3_phy_sel", false,-1, 3,0); - tracep->declBit(c+4051,"wb32_ddr3_phy_stall", false,-1); - tracep->declBit(c+4052,"wb32_ddr3_phy_ack", false,-1); - tracep->declBit(c+5074,"wb32_ddr3_phy_err", false,-1); - tracep->declBus(c+4053,"wb32_ddr3_phy_idata", false,-1, 31,0); - tracep->declBit(c+410,"wbu_cyc", false,-1); - tracep->declBit(c+411,"wbu_stb", false,-1); - tracep->declBit(c+412,"wbu_we", false,-1); - tracep->declBus(c+413,"wbu_addr", false,-1, 26,0); - tracep->declBus(c+414,"wbu_data", false,-1, 31,0); - tracep->declBus(c+5108,"wbu_sel", false,-1, 3,0); - tracep->declBit(c+415,"wbu_stall", false,-1); - tracep->declBit(c+416,"wbu_ack", false,-1); - tracep->declBit(c+417,"wbu_err", false,-1); - tracep->declBus(c+418,"wbu_idata", false,-1, 31,0); - tracep->declBit(c+419,"wbu_wbu_arbiter_cyc", false,-1); - tracep->declBit(c+420,"wbu_wbu_arbiter_stb", false,-1); - tracep->declBit(c+421,"wbu_wbu_arbiter_we", false,-1); - tracep->declBus(c+422,"wbu_wbu_arbiter_addr", false,-1, 26,0); - tracep->declBus(c+423,"wbu_wbu_arbiter_data", false,-1, 31,0); - tracep->declBus(c+424,"wbu_wbu_arbiter_sel", false,-1, 3,0); - tracep->declBit(c+425,"wbu_wbu_arbiter_stall", false,-1); - tracep->declBit(c+426,"wbu_wbu_arbiter_ack", false,-1); - tracep->declBit(c+427,"wbu_wbu_arbiter_err", false,-1); - tracep->declBus(c+428,"wbu_wbu_arbiter_idata", false,-1, 31,0); - tracep->declBit(c+429,"wbu_zip_cyc", false,-1); - tracep->declBit(c+430,"wbu_zip_stb", false,-1); - tracep->declBit(c+431,"wbu_zip_we", false,-1); - tracep->declBus(c+432,"wbu_zip_addr", false,-1, 26,0); - tracep->declBus(c+433,"wbu_zip_data", false,-1, 31,0); - tracep->declBus(c+434,"wbu_zip_sel", false,-1, 3,0); - tracep->declBit(c+5011,"wbu_zip_stall", false,-1); - tracep->declBit(c+5012,"wbu_zip_ack", false,-1); - tracep->declBit(c+5074,"wbu_zip_err", false,-1); - tracep->declBus(c+435,"wbu_zip_idata", false,-1, 31,0); - tracep->declBit(c+407,"r_wb32_sio_ack", false,-1); - tracep->declBus(c+408,"r_wb32_sio_data", false,-1, 31,0); - tracep->declBit(c+5074,"zip_unused", false,-1); - tracep->declBit(c+189,"w_bus_int", false,-1); - tracep->declBus(c+436,"wbu_tmp_addr", false,-1, 29,0); - tracep->declBit(c+409,"r_cfg_ack", false,-1); - tracep->declBit(c+5074,"cfg_unused", false,-1); - tracep->declBus(c+5109,"INITIAL_GPIO", false,-1, 7,0); - tracep->pushNamePrefix("bkrami "); - tracep->declBus(c+5110,"LGMEMSZ", false,-1, 31,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5064,"EXTRACLOCK", false,-1, 31,0); - tracep->declBus(c+5112,"HEXFILE", false,-1, 7,0); - tracep->declBus(c+5113,"OPT_ROM", false,-1, 0,0); - tracep->declBus(c+5060,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4442,"i_wb_cyc", false,-1); - tracep->declBit(c+4443,"i_wb_stb", false,-1); - tracep->declBit(c+4444,"i_wb_we", false,-1); - tracep->declBus(c+4565,"i_wb_addr", false,-1, 13,0); - tracep->declArray(c+4446,"i_wb_data", false,-1, 511,0); - tracep->declQuad(c+4462,"i_wb_sel", false,-1, 63,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+361,"o_wb_ack", false,-1); - tracep->declArray(c+362,"o_wb_data", false,-1, 511,0); - tracep->declBit(c+437,"w_wstb", false,-1); - tracep->declBit(c+438,"w_stb", false,-1); - tracep->declArray(c+439,"w_data", false,-1, 511,0); - tracep->declBus(c+455,"w_addr", false,-1, 13,0); - tracep->declQuad(c+456,"w_sel", false,-1, 63,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("EXTRA_MEM_CLOCK_CYCLE "); - tracep->declBit(c+437,"last_wstb", false,-1); - tracep->declBit(c+438,"last_stb", false,-1); - tracep->declBus(c+455,"last_addr", false,-1, 13,0); - tracep->declArray(c+439,"last_data", false,-1, 511,0); - tracep->declQuad(c+456,"last_sel", false,-1, 63,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("WRITE_TO_MEMORY "); - tracep->declBus(c+458,"ik", false,-1, 31,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("clock_generator "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBus(c+5063,"UPSAMPLE", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBus(c+459,"i_delay", false,-1, 31,0); - tracep->declBus(c+4957,"o_word", false,-1, 7,0); - tracep->declBit(c+171,"o_stb", false,-1); - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+460+i*1,"counter", true,(i+0), 31,0); - } - tracep->declBus(c+468,"r_delay", false,-1, 31,0); - tracep->declBus(c+469,"times_three", false,-1, 31,0); - tracep->declBus(c+470,"times_five", false,-1, 31,0); - tracep->declBus(c+471,"times_seven", false,-1, 31,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("console "); - tracep->declBus(c+5115,"LGFLEN", false,-1, 3,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+4527,"i_wb_cyc", false,-1); - tracep->declBit(c+4528,"i_wb_stb", false,-1); - tracep->declBit(c+4529,"i_wb_we", false,-1); - tracep->declBus(c+4566,"i_wb_addr", false,-1, 1,0); - tracep->declBus(c+4531,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4532,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+399,"o_wb_ack", false,-1); - tracep->declBus(c+400,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+181,"o_uart_stb", false,-1); - tracep->declBus(c+184,"o_uart_data", false,-1, 6,0); - tracep->declBit(c+182,"i_uart_busy", false,-1); - tracep->declBit(c+180,"i_uart_stb", false,-1); - tracep->declBus(c+183,"i_uart_data", false,-1, 6,0); - tracep->declBit(c+165,"o_uart_rx_int", false,-1); - tracep->declBit(c+163,"o_uart_tx_int", false,-1); - tracep->declBit(c+162,"o_uart_rxfifo_int", false,-1); - tracep->declBit(c+164,"o_uart_txfifo_int", false,-1); - tracep->declBus(c+185,"o_debug", false,-1, 31,0); - tracep->declBus(c+5115,"LCLLGFLEN", false,-1, 3,0); - tracep->declBus(c+5116,"UART_SETUP", false,-1, 1,0); - tracep->declBus(c+5117,"UART_FIFO", false,-1, 1,0); - tracep->declBus(c+5118,"UART_RXREG", false,-1, 1,0); - tracep->declBus(c+5119,"UART_TXREG", false,-1, 1,0); - tracep->declBit(c+472,"rx_uart_reset", false,-1); - tracep->declBit(c+165,"rx_empty_n", false,-1); - tracep->declBit(c+473,"rx_fifo_err", false,-1); - tracep->declBus(c+474,"rxf_wb_data", false,-1, 6,0); - tracep->declBus(c+475,"rxf_status", false,-1, 15,0); - tracep->declBit(c+476,"rxf_wb_read", false,-1); - tracep->declBus(c+477,"wb_rx_data", false,-1, 31,0); - tracep->declBit(c+181,"tx_empty_n", false,-1); - tracep->declBit(c+478,"txf_err", false,-1); - tracep->declBus(c+479,"txf_status", false,-1, 15,0); - tracep->declBit(c+480,"txf_wb_write", false,-1); - tracep->declBit(c+481,"tx_uart_reset", false,-1); - tracep->declBus(c+482,"txf_wb_data", false,-1, 6,0); - tracep->declBus(c+483,"wb_tx_data", false,-1, 31,0); - tracep->declBus(c+484,"wb_fifo_data", false,-1, 31,0); - tracep->declBus(c+485,"r_wb_addr", false,-1, 1,0); - tracep->declBit(c+486,"r_wb_ack", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("rxfifo "); - tracep->declBus(c+5072,"BW", false,-1, 31,0); - tracep->declBus(c+5115,"LGFLEN", false,-1, 3,0); - tracep->declBus(c+5070,"RXFIFO", false,-1, 0,0); - tracep->declBus(c+5120,"FLEN", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+472,"i_reset", false,-1); - tracep->declBit(c+180,"i_wr", false,-1); - tracep->declBus(c+183,"i_data", false,-1, 6,0); - tracep->declBit(c+165,"o_empty_n", false,-1); - tracep->declBit(c+476,"i_rd", false,-1); - tracep->declBus(c+474,"o_data", false,-1, 6,0); - tracep->declBus(c+475,"o_status", false,-1, 15,0); - tracep->declBit(c+473,"o_err", false,-1); - tracep->declBus(c+487,"r_data", false,-1, 6,0); - tracep->declBus(c+488,"last_write", false,-1, 6,0); - tracep->declBus(c+489,"wr_addr", false,-1, 5,0); - tracep->declBus(c+490,"rd_addr", false,-1, 5,0); - tracep->declBus(c+491,"r_next", false,-1, 5,0); - tracep->declBit(c+492,"will_overflow", false,-1); - tracep->declBit(c+493,"will_underflow", false,-1); - tracep->declBit(c+494,"osrc", false,-1); - tracep->declBus(c+495,"w_waddr_plus_one", false,-1, 5,0); - tracep->declBus(c+496,"w_waddr_plus_two", false,-1, 5,0); - tracep->declBit(c+497,"w_write", false,-1); - tracep->declBit(c+498,"w_read", false,-1); - tracep->declBus(c+499,"r_fill", false,-1, 5,0); - tracep->declBus(c+5115,"lglen", false,-1, 3,0); - tracep->declBit(c+162,"w_half_full", false,-1); - tracep->declBus(c+500,"w_fill", false,-1, 9,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("txfifo "); - tracep->declBus(c+5072,"BW", false,-1, 31,0); - tracep->declBus(c+5115,"LGFLEN", false,-1, 3,0); - tracep->declBus(c+5113,"RXFIFO", false,-1, 0,0); - tracep->declBus(c+5120,"FLEN", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+481,"i_reset", false,-1); - tracep->declBit(c+480,"i_wr", false,-1); - tracep->declBus(c+482,"i_data", false,-1, 6,0); - tracep->declBit(c+181,"o_empty_n", false,-1); - tracep->declBit(c+501,"i_rd", false,-1); - tracep->declBus(c+184,"o_data", false,-1, 6,0); - tracep->declBus(c+479,"o_status", false,-1, 15,0); - tracep->declBit(c+478,"o_err", false,-1); - tracep->declBus(c+502,"r_data", false,-1, 6,0); - tracep->declBus(c+503,"last_write", false,-1, 6,0); - tracep->declBus(c+504,"wr_addr", false,-1, 5,0); - tracep->declBus(c+505,"rd_addr", false,-1, 5,0); - tracep->declBus(c+506,"r_next", false,-1, 5,0); - tracep->declBit(c+507,"will_overflow", false,-1); - tracep->declBit(c+508,"will_underflow", false,-1); - tracep->declBit(c+509,"osrc", false,-1); - tracep->declBus(c+510,"w_waddr_plus_one", false,-1, 5,0); - tracep->declBus(c+511,"w_waddr_plus_two", false,-1, 5,0); - tracep->declBit(c+512,"w_write", false,-1); - tracep->declBit(c+513,"w_read", false,-1); - tracep->declBus(c+514,"r_fill", false,-1, 5,0); - tracep->declBus(c+5115,"lglen", false,-1, 3,0); - tracep->declBit(c+164,"w_half_full", false,-1); - tracep->declBus(c+515,"w_fill", false,-1, 9,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("ddr3_controller_inst "); - tracep->declDouble(c+5056,"CONTROLLER_CLK_PERIOD", false,-1); - tracep->declDouble(c+5058,"DDR3_CLK_PERIOD", false,-1); - tracep->declBus(c+5060,"ROW_BITS", false,-1, 31,0); - tracep->declBus(c+5061,"COL_BITS", false,-1, 31,0); - tracep->declBus(c+5062,"BA_BITS", false,-1, 31,0); - tracep->declBus(c+5063,"DQ_BITS", false,-1, 31,0); - tracep->declBus(c+5063,"LANES", false,-1, 31,0); - tracep->declBus(c+5064,"AUX_WIDTH", false,-1, 31,0); - tracep->declBus(c+5114,"WB2_ADDR_BITS", false,-1, 31,0); - tracep->declBus(c+5114,"WB2_DATA_BITS", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_BUS_ABORT", false,-1, 0,0); - tracep->declBus(c+5065,"serdes_ratio", false,-1, 31,0); - tracep->declBus(c+5111,"wb_data_bits", false,-1, 31,0); - tracep->declBus(c+5121,"wb_addr_bits", false,-1, 31,0); - tracep->declBus(c+5120,"wb_sel_bits", false,-1, 31,0); - tracep->declBus(c+5065,"wb2_sel_bits", false,-1, 31,0); - tracep->declBus(c+5066,"cmd_len", false,-1, 31,0); - tracep->declBit(c+4901,"i_controller_clk", false,-1); - tracep->declBit(c+5013,"i_rst_n", false,-1); - tracep->declBit(c+4464,"i_wb_cyc", false,-1); - tracep->declBit(c+4465,"i_wb_stb", false,-1); - tracep->declBit(c+4466,"i_wb_we", false,-1); - tracep->declBus(c+4567,"i_wb_addr", false,-1, 20,0); - tracep->declArray(c+4468,"i_wb_data", false,-1, 511,0); - tracep->declQuad(c+4484,"i_wb_sel", false,-1, 63,0); - tracep->declBus(c+5074,"i_aux", false,-1, 0,0); - tracep->declBit(c+4033,"o_wb_stall", false,-1); - tracep->declBit(c+4034,"o_wb_ack", false,-1); - tracep->declArray(c+4035,"o_wb_data", false,-1, 511,0); - tracep->declBus(c+4032,"o_aux", false,-1, 0,0); - tracep->declBit(c+4559,"i_wb2_cyc", false,-1); - tracep->declBit(c+4560,"i_wb2_stb", false,-1); - tracep->declBit(c+4561,"i_wb2_we", false,-1); - tracep->declBus(c+4568,"i_wb2_addr", false,-1, 31,0); - tracep->declBus(c+4564,"i_wb2_sel", false,-1, 3,0); - tracep->declBus(c+4563,"i_wb2_data", false,-1, 31,0); - tracep->declBit(c+4051,"o_wb2_stall", false,-1); - tracep->declBit(c+4052,"o_wb2_ack", false,-1); - tracep->declBus(c+4053,"o_wb2_data", false,-1, 31,0); - tracep->declArray(c+4903,"i_phy_iserdes_data", false,-1, 511,0); - tracep->declQuad(c+4919,"i_phy_iserdes_dqs", false,-1, 63,0); - tracep->declQuad(c+4921,"i_phy_iserdes_bitslip_reference", false,-1, 63,0); - tracep->declBit(c+4923,"i_phy_idelayctrl_rdy", false,-1); - tracep->declArray(c+4924,"o_phy_cmd", false,-1, 95,0); - tracep->declBit(c+4927,"o_phy_dqs_tri_control", false,-1); - tracep->declBit(c+4928,"o_phy_dq_tri_control", false,-1); - tracep->declBit(c+4929,"o_phy_toggle_dqs", false,-1); - tracep->declArray(c+4930,"o_phy_data", false,-1, 511,0); - tracep->declQuad(c+4946,"o_phy_dm", false,-1, 63,0); - tracep->declBus(c+4948,"o_phy_odelay_data_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4949,"o_phy_odelay_dqs_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4950,"o_phy_idelay_data_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4951,"o_phy_idelay_dqs_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4952,"o_phy_odelay_data_ld", false,-1, 7,0); - tracep->declBus(c+4953,"o_phy_odelay_dqs_ld", false,-1, 7,0); - tracep->declBus(c+4954,"o_phy_idelay_data_ld", false,-1, 7,0); - tracep->declBus(c+4955,"o_phy_idelay_dqs_ld", false,-1, 7,0); - tracep->declBus(c+4956,"o_phy_bitslip", false,-1, 7,0); - tracep->declBus(c+5122,"CMD_MRS", false,-1, 3,0); - tracep->declBus(c+5123,"CMD_REF", false,-1, 3,0); - tracep->declBus(c+5124,"CMD_PRE", false,-1, 3,0); - tracep->declBus(c+5125,"CMD_ACT", false,-1, 3,0); - tracep->declBus(c+5126,"CMD_WR", false,-1, 3,0); - tracep->declBus(c+5127,"CMD_RD", false,-1, 3,0); - tracep->declBus(c+5128,"CMD_NOP", false,-1, 3,0); - tracep->declBus(c+5129,"CMD_DES", false,-1, 3,0); - tracep->declBus(c+5115,"CMD_ZQC", false,-1, 3,0); - tracep->declBus(c+5130,"RST_DONE", false,-1, 31,0); - tracep->declBus(c+5130,"REF_IDLE", false,-1, 31,0); - tracep->declBus(c+5131,"USE_TIMER", false,-1, 31,0); - tracep->declBus(c+5132,"A10_CONTROL", false,-1, 31,0); - tracep->declBus(c+5066,"CLOCK_EN", false,-1, 31,0); - tracep->declBus(c+5133,"RESET_N", false,-1, 31,0); - tracep->declBus(c+5068,"DDR3_CMD_START", false,-1, 31,0); - tracep->declBus(c+5073,"DDR3_CMD_END", false,-1, 31,0); - tracep->declBus(c+5134,"MRS_BANK_START", false,-1, 31,0); - tracep->declBus(c+5133,"CMD_CS_N", false,-1, 31,0); - tracep->declBus(c+5068,"CMD_RAS_N", false,-1, 31,0); - tracep->declBus(c+5121,"CMD_CAS_N", false,-1, 31,0); - tracep->declBus(c+5110,"CMD_WE_N", false,-1, 31,0); - tracep->declBus(c+5073,"CMD_ODT", false,-1, 31,0); - tracep->declBus(c+5134,"CMD_CKE", false,-1, 31,0); - tracep->declBus(c+5135,"CMD_RESET_N", false,-1, 31,0); - tracep->declBus(c+5069,"CMD_BANK_START", false,-1, 31,0); - tracep->declBus(c+5136,"CMD_ADDRESS_START", false,-1, 31,0); - tracep->declBus(c+5118,"READ_SLOT", false,-1, 1,0); - tracep->declBus(c+5119,"WRITE_SLOT", false,-1, 1,0); - tracep->declBus(c+5116,"ACTIVATE_SLOT", false,-1, 1,0); - tracep->declBus(c+5117,"PRECHARGE_SLOT", false,-1, 1,0); - tracep->declBus(c+5076,"DATA_INITIAL_ODELAY_TAP", false,-1, 31,0); - tracep->declBus(c+5063,"DQS_INITIAL_ODELAY_TAP", false,-1, 31,0); - tracep->declBus(c+5076,"DATA_INITIAL_IDELAY_TAP", false,-1, 31,0); - tracep->declBus(c+5063,"DQS_INITIAL_IDELAY_TAP", false,-1, 31,0); - tracep->declBus(c+5073,"DELAY_SLOT_WIDTH", false,-1, 31,0); - tracep->declBus(c+5137,"POWER_ON_RESET_HIGH", false,-1, 31,0); - tracep->declBus(c+5138,"INITIAL_CKE_LOW", false,-1, 31,0); - tracep->declDouble(c+5139,"tRCD", false,-1); - tracep->declDouble(c+5139,"tRP", false,-1); - tracep->declBus(c+5141,"tRAS", false,-1, 31,0); - tracep->declDouble(c+5142,"tRFC", false,-1); - tracep->declBus(c+5144,"tREFI", false,-1, 31,0); - tracep->declDouble(c+5145,"tXPR", false,-1); - tracep->declBus(c+5065,"tMRD", false,-1, 31,0); - tracep->declDouble(c+5147,"tWR", false,-1); - tracep->declDouble(c+5056,"tWTR", false,-1); - tracep->declBus(c+5149,"tWLMRD", false,-1, 18,0); - tracep->declDouble(c+5150,"tWLO", false,-1); - tracep->declBus(c+5075,"tWLOE", false,-1, 31,0); - tracep->declDouble(c+5056,"tRTP", false,-1); - tracep->declBus(c+5065,"tCCD", false,-1, 31,0); - tracep->declBus(c+5062,"tMOD", false,-1, 31,0); - tracep->declBus(c+5152,"tZQinit", false,-1, 31,0); - tracep->declBus(c+5153,"CL_nCK", false,-1, 31,0); - tracep->declBus(c+5154,"CWL_nCK", false,-1, 31,0); - tracep->declBus(c+5155,"DELAY_MAX_VALUE", false,-1, 18,0); - tracep->declBus(c+5069,"DELAY_COUNTER_WIDTH", false,-1, 31,0); - tracep->declBus(c+5075,"CALIBRATION_DELAY", false,-1, 31,0); - tracep->declBus(c+5123,"PRECHARGE_TO_ACTIVATE_DELAY", false,-1, 3,0); - tracep->declBus(c+5125,"ACTIVATE_TO_PRECHARGE_DELAY", false,-1, 3,0); - tracep->declBus(c+5122,"ACTIVATE_TO_WRITE_DELAY", false,-1, 3,0); - tracep->declBus(c+5122,"ACTIVATE_TO_READ_DELAY", false,-1, 3,0); - tracep->declBus(c+5123,"READ_TO_WRITE_DELAY", false,-1, 3,0); - tracep->declBus(c+5122,"READ_TO_READ_DELAY", false,-1, 3,0); - tracep->declBus(c+5123,"READ_TO_PRECHARGE_DELAY", false,-1, 3,0); - tracep->declBus(c+5122,"WRITE_TO_WRITE_DELAY", false,-1, 3,0); - tracep->declBus(c+5125,"WRITE_TO_READ_DELAY", false,-1, 3,0); - tracep->declBus(c+5126,"WRITE_TO_PRECHARGE_DELAY", false,-1, 3,0); - tracep->declBus(c+5154,"PRE_REFRESH_DELAY", false,-1, 31,0); - tracep->declBus(c+5127,"MARGIN_BEFORE_ANTICIPATE", false,-1, 3,0); - tracep->declBus(c+5075,"STAGE2_DATA_DEPTH", false,-1, 31,0); - tracep->declBus(c+5076,"READ_DELAY", false,-1, 31,0); - tracep->declBus(c+5154,"READ_ACK_PIPE_WIDTH", false,-1, 31,0); - tracep->declBus(c+5069,"MAX_ADDED_READ_ACK_DELAY", false,-1, 31,0); - tracep->declBus(c+5136,"DELAY_BEFORE_WRITE_LEVEL_FEEDBACK", false,-1, 31,0); - tracep->declBus(c+5076,"IDLE", false,-1, 31,0); - tracep->declBus(c+5064,"BITSLIP_DQS_TRAIN_1", false,-1, 31,0); - tracep->declBus(c+5075,"MPR_READ", false,-1, 31,0); - tracep->declBus(c+5062,"COLLECT_DQS", false,-1, 31,0); - tracep->declBus(c+5065,"ANALYZE_DQS", false,-1, 31,0); - tracep->declBus(c+5154,"CALIBRATE_DQS", false,-1, 31,0); - tracep->declBus(c+5153,"BITSLIP_DQS_TRAIN_2", false,-1, 31,0); - tracep->declBus(c+5072,"START_WRITE_LEVEL", false,-1, 31,0); - tracep->declBus(c+5063,"WAIT_FOR_FEEDBACK", false,-1, 31,0); - tracep->declBus(c+5156,"ISSUE_WRITE_1", false,-1, 31,0); - tracep->declBus(c+5061,"ISSUE_WRITE_2", false,-1, 31,0); - tracep->declBus(c+5157,"ISSUE_READ", false,-1, 31,0); - tracep->declBus(c+5158,"READ_DATA", false,-1, 31,0); - tracep->declBus(c+5136,"ANALYZE_DATA", false,-1, 31,0); - tracep->declBus(c+5060,"DONE_CALIBRATE", false,-1, 31,0); - tracep->declBus(c+5154,"STORED_DQS_SIZE", false,-1, 31,0); - tracep->declBus(c+5064,"REPEAT_DQS_ANALYZE", false,-1, 31,0); - tracep->declBus(c+5159,"PASR", false,-1, 2,0); - tracep->declBus(c+5159,"CWL", false,-1, 2,0); - tracep->declBus(c+5070,"ASR", false,-1, 0,0); - tracep->declBus(c+5113,"SRT", false,-1, 0,0); - tracep->declBus(c+5116,"RTT_WR", false,-1, 1,0); - tracep->declBus(c+5160,"MR2_SEL", false,-1, 2,0); - tracep->declBus(c+5161,"MR2", false,-1, 18,0); - tracep->declBus(c+5116,"MPR_LOC", false,-1, 1,0); - tracep->declBus(c+5070,"MPR_EN", false,-1, 0,0); - tracep->declBus(c+5113,"MPR_DIS", false,-1, 0,0); - tracep->declBus(c+5162,"MR3_SEL", false,-1, 2,0); - tracep->declBus(c+5163,"MR3_MPR_EN", false,-1, 18,0); - tracep->declBus(c+5164,"MR3_MPR_DIS", false,-1, 18,0); - tracep->declBus(c+5165,"MR3_RD_ADDR", false,-1, 16,0); - tracep->declBus(c+5113,"DLL_EN", false,-1, 0,0); - tracep->declBus(c+5116,"DIC", false,-1, 1,0); - tracep->declBus(c+5162,"RTT_NOM", false,-1, 2,0); - tracep->declBus(c+5070,"WL_EN", false,-1, 0,0); - tracep->declBus(c+5113,"WL_DIS", false,-1, 0,0); - tracep->declBus(c+5116,"AL", false,-1, 1,0); - tracep->declBus(c+5070,"TDQS", false,-1, 0,0); - tracep->declBus(c+5113,"QOFF", false,-1, 0,0); - tracep->declBus(c+5166,"MR1_SEL", false,-1, 2,0); - tracep->declBus(c+5167,"MR1_WL_EN", false,-1, 18,0); - tracep->declBus(c+5168,"MR1_WL_DIS", false,-1, 18,0); - tracep->declBus(c+5116,"BL", false,-1, 1,0); - tracep->declBus(c+5126,"CL", false,-1, 3,0); - tracep->declBus(c+5113,"RBT", false,-1, 0,0); - tracep->declBus(c+5070,"DLL_RST", false,-1, 0,0); - tracep->declBus(c+5162,"WR", false,-1, 2,0); - tracep->declBus(c+5113,"PPD", false,-1, 0,0); - tracep->declBus(c+5159,"MR0_SEL", false,-1, 2,0); - tracep->declBus(c+5169,"MR0", false,-1, 18,0); - tracep->declBus(c+5170,"INITIAL_RESET_INSTRUCTION", false,-1, 27,0); - tracep->declBus(c+4054,"index", false,-1, 31,0); - tracep->declBus(c+4055,"instruction_address", false,-1, 4,0); - tracep->declBus(c+4056,"instruction", false,-1, 27,0); - tracep->declBus(c+4057,"delay_counter", false,-1, 15,0); - tracep->declBit(c+4058,"delay_counter_is_zero", false,-1); - tracep->declBit(c+4059,"reset_done", false,-1); - tracep->declBit(c+4060,"pause_counter", false,-1); - tracep->declBit(c+4061,"issue_read_command", false,-1); - tracep->declBit(c+5074,"issue_write_command", false,-1); - tracep->declBit(c+4062,"stage2_update", false,-1); - tracep->declBit(c+4828,"stage2_stall", false,-1); - tracep->declBit(c+4829,"stage1_stall", false,-1); - tracep->declBus(c+4063,"bank_status_q", false,-1, 7,0); - tracep->declBus(c+4830,"bank_status_d", false,-1, 7,0); - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4064+i*1,"bank_active_row_q", true,(i+0), 13,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4831+i*1,"bank_active_row_d", true,(i+0), 13,0); - } - tracep->declBit(c+4072,"stage1_pending", false,-1); - tracep->declBus(c+4073,"stage1_aux", false,-1, 0,0); - tracep->declBit(c+4074,"stage1_we", false,-1); - tracep->declArray(c+4075,"stage1_data", false,-1, 511,0); - tracep->declQuad(c+4091,"stage1_dm", false,-1, 63,0); - tracep->declBus(c+4093,"stage1_col", false,-1, 9,0); - tracep->declBus(c+4094,"stage1_bank", false,-1, 2,0); - tracep->declBus(c+4095,"stage1_row", false,-1, 13,0); - tracep->declBus(c+4096,"stage1_next_bank", false,-1, 2,0); - tracep->declBus(c+4097,"stage1_next_row", false,-1, 13,0); - tracep->declBus(c+4569,"wb_addr_plus_anticipate", false,-1, 20,0); - tracep->declBit(c+4098,"stage2_pending", false,-1); - tracep->declBus(c+4099,"stage2_aux", false,-1, 0,0); - tracep->declBit(c+4100,"stage2_we", false,-1); - tracep->declQuad(c+4101,"stage2_dm_unaligned", false,-1, 63,0); - for (int i = 0; i < 2; ++i) { - tracep->declQuad(c+4103+i*2,"stage2_dm", true,(i+0), 63,0); - } - tracep->declArray(c+4107,"stage2_data_unaligned", false,-1, 511,0); - for (int i = 0; i < 2; ++i) { - tracep->declArray(c+4123+i*16,"stage2_data", true,(i+0), 511,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declQuad(c+4155+i*2,"unaligned_data", true,(i+0), 63,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4171+i*1,"unaligned_dm", true,(i+0), 7,0); - } - tracep->declBus(c+4179,"stage2_col", false,-1, 9,0); - tracep->declBus(c+4180,"stage2_bank", false,-1, 2,0); - tracep->declBus(c+4181,"stage2_row", false,-1, 13,0); - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4182+i*1,"delay_before_precharge_counter_q", true,(i+0), 3,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4839+i*1,"delay_before_precharge_counter_d", true,(i+0), 3,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4190+i*1,"delay_before_activate_counter_q", true,(i+0), 3,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4847+i*1,"delay_before_activate_counter_d", true,(i+0), 3,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4198+i*1,"delay_before_write_counter_q", true,(i+0), 3,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4855+i*1,"delay_before_write_counter_d", true,(i+0), 3,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4206+i*1,"delay_before_read_counter_q", true,(i+0), 3,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4863+i*1,"delay_before_read_counter_d", true,(i+0), 3,0); - } - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+4871+i*1,"cmd_d", true,(i+0), 23,0); - } - tracep->declBit(c+4214,"cmd_odt_q", false,-1); - tracep->declBit(c+4875,"cmd_odt", false,-1); - tracep->declBit(c+4876,"cmd_ck_en", false,-1); - tracep->declBit(c+4877,"cmd_reset_n", false,-1); - tracep->declBit(c+4215,"o_wb_stall_q", false,-1); - tracep->declBit(c+4878,"o_wb_stall_d", false,-1); - tracep->declBit(c+4879,"precharge_slot_busy", false,-1); - tracep->declBit(c+4880,"activate_slot_busy", false,-1); - tracep->declBus(c+4216,"write_dqs_q", false,-1, 1,0); - tracep->declBit(c+4217,"write_dqs_d", false,-1); - tracep->declBus(c+4218,"write_dqs", false,-1, 2,0); - tracep->declBus(c+4219,"write_dqs_val", false,-1, 2,0); - tracep->declBit(c+4220,"write_dq_q", false,-1); - tracep->declBit(c+4221,"write_dq_d", false,-1); - tracep->declBus(c+4222,"write_dq", false,-1, 3,0); - tracep->declBus(c+5171,"aligned_cmd", false,-1, 23,0); - tracep->declBus(c+5172,"serial_index", false,-1, 1,0); - tracep->declBus(c+5173,"serial_index_q", false,-1, 1,0); - tracep->declBus(c+5174,"test_OFB", false,-1, 7,0); - tracep->declBus(c+4223,"state_calibrate", false,-1, 4,0); - tracep->declQuad(c+4224,"dqs_store", false,-1, 39,0); - tracep->declBus(c+4226,"dqs_count_repeat", false,-1, 3,0); - tracep->declBus(c+4227,"dqs_start_index", false,-1, 5,0); - tracep->declBus(c+4228,"dqs_start_index_stored", false,-1, 5,0); - tracep->declBus(c+4229,"dqs_target_index", false,-1, 5,0); - tracep->declBus(c+4230,"dqs_target_index_orig", false,-1, 5,0); - tracep->declBus(c+4231,"dq_target_index", false,-1, 5,0); - tracep->declBus(c+4232,"dqs_target_index_value", false,-1, 5,0); - tracep->declBus(c+4233,"dqs_start_index_repeat", false,-1, 0,0); - tracep->declBus(c+4234,"train_delay", false,-1, 1,0); - tracep->declBus(c+4235,"delay_before_read_data", false,-1, 3,0); - tracep->declBus(c+4236,"delay_before_write_level_feedback", false,-1, 4,0); - tracep->declBit(c+4237,"initial_dqs", false,-1); - tracep->declBus(c+4238,"lane", false,-1, 2,0); - tracep->declBus(c+4239,"lane_times_8", false,-1, 5,0); - tracep->declBus(c+4240,"dqs_bitslip_arrangement", false,-1, 15,0); - tracep->declBus(c+4241,"added_read_pipe_max", false,-1, 3,0); - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4242+i*1,"added_read_pipe", true,(i+0), 3,0); - } - for (int i = 0; i < 5; ++i) { - tracep->declBus(c+4250+i*1,"shift_reg_read_pipe_q", true,(i+0), 1,0); - } - for (int i = 0; i < 5; ++i) { - tracep->declBus(c+4255+i*1,"shift_reg_read_pipe_d", true,(i+0), 1,0); - } - tracep->declBit(c+4260,"index_read_pipe", false,-1); - tracep->declBit(c+4261,"index_wb_data", false,-1); - for (int i = 0; i < 2; ++i) { - tracep->declBus(c+4262+i*1,"delay_read_pipe", true,(i+0), 15,0); - } - for (int i = 0; i < 2; ++i) { - tracep->declArray(c+4264+i*16,"o_wb_data_q", true,(i+0), 511,0); - } - for (int i = 0; i < 16; ++i) { - tracep->declBus(c+4296+i*1,"o_wb_ack_read_q", true,(i+0), 1,0); - } - tracep->declBit(c+4312,"write_calib_stb", false,-1); - tracep->declBus(c+4313,"write_calib_aux", false,-1, 0,0); - tracep->declBit(c+4314,"write_calib_we", false,-1); - tracep->declBus(c+4315,"write_calib_col", false,-1, 9,0); - tracep->declArray(c+4316,"write_calib_data", false,-1, 511,0); - tracep->declBit(c+4332,"write_calib_odt", false,-1); - tracep->declBit(c+4333,"write_calib_dqs", false,-1); - tracep->declBit(c+4334,"write_calib_dq", false,-1); - tracep->declBit(c+4335,"prev_write_level_feedback", false,-1); - tracep->declArray(c+4336,"read_data_store", false,-1, 511,0); - tracep->declArray(c+4352,"write_pattern", false,-1, 127,0); - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4356+i*1,"data_start_index", true,(i+0), 6,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4364+i*1,"odelay_data_cntvaluein", true,(i+0), 4,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4372+i*1,"odelay_dqs_cntvaluein", true,(i+0), 4,0); - } - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4380+i*1,"idelay_data_cntvaluein", true,(i+0), 4,0); - } - tracep->declBus(c+4388,"idelay_data_cntvaluein_prev", false,-1, 4,0); - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+4389+i*1,"idelay_dqs_cntvaluein", true,(i+0), 4,0); - } - tracep->declBit(c+4397,"wb2_stb", false,-1); - tracep->declBit(c+4398,"wb2_update", false,-1); - tracep->declBit(c+4399,"wb2_we", false,-1); - tracep->declBus(c+4400,"wb2_addr", false,-1, 31,0); - tracep->declBus(c+4401,"wb2_data", false,-1, 31,0); - tracep->declBus(c+4402,"wb2_sel", false,-1, 3,0); - tracep->declBus(c+5175,"wb2_read_lane", false,-1, 2,0); - tracep->declBus(c+4403,"wb2_phy_odelay_data_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4404,"wb2_phy_odelay_dqs_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4405,"wb2_phy_idelay_data_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4406,"wb2_phy_idelay_dqs_cntvaluein", false,-1, 4,0); - tracep->declBus(c+4407,"wb2_phy_odelay_data_ld", false,-1, 7,0); - tracep->declBus(c+4408,"wb2_phy_odelay_dqs_ld", false,-1, 7,0); - tracep->declBus(c+4409,"wb2_phy_idelay_data_ld", false,-1, 7,0); - tracep->declBus(c+4410,"wb2_phy_idelay_dqs_ld", false,-1, 7,0); - tracep->declBus(c+4411,"wb2_write_lane", false,-1, 2,0); - tracep->declBus(c+4412,"ns_to_cycles__Vstatic__result", false,-1, 31,0); - tracep->declBus(c+1,"nCK_to_cycles__Vstatic__result", false,-1, 31,0); - tracep->declBus(c+5176,"get_slot__Vstatic__delay", false,-1, 31,0); - tracep->declBus(c+5177,"get_slot__Vstatic__slot_number", false,-1, 1,0); - tracep->declBus(c+5178,"get_slot__Vstatic__read_slot", false,-1, 1,0); - tracep->declBus(c+5179,"get_slot__Vstatic__write_slot", false,-1, 1,0); - tracep->declBus(c+5180,"get_slot__Vstatic__anticipate_activate_slot", false,-1, 1,0); - tracep->declBus(c+5181,"get_slot__Vstatic__anticipate_precharge_slot", false,-1, 1,0); - tracep->declBus(c+5182,"find_delay__Vstatic__k", false,-1, 31,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("emmcscopei "); - tracep->declBus(c+5183,"LGMEM", false,-1, 4,0); - tracep->declBus(c+5114,"BUSW", false,-1, 31,0); - tracep->declBus(c+5184,"NELM", false,-1, 31,0); - tracep->declBus(c+5070,"SYNCHRONOUS", false,-1, 0,0); - tracep->declBus(c+5110,"HOLDOFFBITS", false,-1, 31,0); - tracep->declBus(c+5185,"DEFAULT_HOLDOFF", false,-1, 19,0); - tracep->declBus(c+5184,"STEP_BITS", false,-1, 31,0); - tracep->declBus(c+5186,"MAX_STEP", false,-1, 30,0); - tracep->declBit(c+4901,"i_data_clk", false,-1); - tracep->declBit(c+5077,"i_ce", false,-1); - tracep->declBit(c+516,"i_trigger", false,-1); - tracep->declBus(c+38,"i_data", false,-1, 30,0); - tracep->declBit(c+4901,"i_wb_clk", false,-1); - tracep->declBit(c+4497,"i_wb_cyc", false,-1); - tracep->declBit(c+4498,"i_wb_stb", false,-1); - tracep->declBit(c+4499,"i_wb_we", false,-1); - tracep->declBit(c+4570,"i_wb_addr", false,-1); - tracep->declBus(c+4501,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4502,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+389,"o_wb_ack", false,-1); - tracep->declBus(c+390,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+158,"o_interrupt", false,-1); - tracep->declBit(c+4571,"write_stb", false,-1); - tracep->declBit(c+4572,"read_from_data", false,-1); - tracep->declBit(c+4573,"write_to_control", false,-1); - tracep->declBus(c+390,"o_bus_data", false,-1, 31,0); - tracep->declBit(c+4901,"bus_clock", false,-1); - tracep->declBit(c+517,"read_address", false,-1); - tracep->declBus(c+4501,"i_bus_data", false,-1, 31,0); - tracep->declBus(c+518,"raddr", false,-1, 11,0); - tracep->declBus(c+519,"waddr", false,-1, 11,0); - tracep->declBit(c+520,"bw_reset_request", false,-1); - tracep->declBit(c+521,"bw_manual_trigger", false,-1); - tracep->declBit(c+522,"bw_disable_trigger", false,-1); - tracep->declBit(c+520,"bw_reset_complete", false,-1); - tracep->declBus(c+523,"br_config", false,-1, 2,0); - tracep->declBus(c+524,"br_holdoff", false,-1, 19,0); - tracep->declBus(c+525,"holdoff_counter", false,-1, 19,0); - tracep->declBit(c+520,"dw_reset", false,-1); - tracep->declBit(c+521,"dw_manual_trigger", false,-1); - tracep->declBit(c+522,"dw_disable_trigger", false,-1); - tracep->declBit(c+526,"dr_triggered", false,-1); - tracep->declBit(c+527,"dr_primed", false,-1); - tracep->declBit(c+528,"dw_trigger", false,-1); - tracep->declBit(c+529,"dr_stopped", false,-1); - tracep->declBus(c+5154,"DLYSTOP", false,-1, 31,0); - tracep->declBus(c+530,"dr_stop_pipe", false,-1, 4,0); - tracep->declBit(c+531,"dw_final_stop", false,-1); - tracep->declBus(c+532,"ck_addr", false,-1, 30,0); - tracep->declBus(c+533,"qd_data", false,-1, 30,0); - tracep->declBit(c+534,"dr_force_write", false,-1); - tracep->declBit(c+535,"dr_run_timeout", false,-1); - tracep->declBit(c+536,"new_data", false,-1); - tracep->declBit(c+537,"dr_force_inhibit", false,-1); - tracep->declBus(c+533,"w_data", false,-1, 30,0); - tracep->declBit(c+538,"imm_adr", false,-1); - tracep->declBit(c+539,"lst_adr", false,-1); - tracep->declBus(c+540,"lst_val", false,-1, 30,0); - tracep->declBus(c+541,"imm_val", false,-1, 30,0); - tracep->declBit(c+542,"record_ce", false,-1); - tracep->declBus(c+543,"r_data", false,-1, 31,0); - tracep->declBit(c+531,"bw_stopped", false,-1); - tracep->declBit(c+526,"bw_triggered", false,-1); - tracep->declBit(c+527,"bw_primed", false,-1); - tracep->declBit(c+389,"br_wb_ack", false,-1); - tracep->declBit(c+544,"br_pre_wb_ack", false,-1); - tracep->declBit(c+4498,"bw_cyc_stb", false,-1); - tracep->declBus(c+545,"this_addr", false,-1, 11,0); - tracep->declBus(c+546,"nxt_mem", false,-1, 31,0); - tracep->declBus(c+524,"full_holdoff", false,-1, 19,0); - tracep->declBus(c+5183,"bw_lgmem", false,-1, 4,0); - tracep->declBit(c+547,"br_level_interrupt", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("genbus "); - tracep->declBus(c+5073,"LGWATCHDOG", false,-1, 31,0); - tracep->declBus(c+5153,"LGINPUT_FIFO", false,-1, 31,0); - tracep->declBus(c+5061,"LGOUTPUT_FIFO", false,-1, 31,0); - tracep->declBus(c+5113,"CMD_PORT_OFF_UNTIL_ACCESSED", false,-1, 0,0); - tracep->declBus(c+5187,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+192,"i_rx_stb", false,-1); - tracep->declBus(c+190,"i_rx_data", false,-1, 7,0); - tracep->declBit(c+410,"o_wb_cyc", false,-1); - tracep->declBit(c+411,"o_wb_stb", false,-1); - tracep->declBit(c+412,"o_wb_we", false,-1); - tracep->declBus(c+436,"o_wb_addr", false,-1, 29,0); - tracep->declBus(c+414,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+415,"i_wb_stall", false,-1); - tracep->declBit(c+416,"i_wb_ack", false,-1); - tracep->declBus(c+418,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+417,"i_wb_err", false,-1); - tracep->declBit(c+189,"i_interrupt", false,-1); - tracep->declBit(c+193,"o_tx_stb", false,-1); - tracep->declBus(c+191,"o_tx_data", false,-1, 7,0); - tracep->declBit(c+194,"i_tx_busy", false,-1); - tracep->declBit(c+181,"i_console_stb", false,-1); - tracep->declBus(c+184,"i_console_data", false,-1, 6,0); - tracep->declBit(c+182,"o_console_busy", false,-1); - tracep->declBit(c+180,"o_console_stb", false,-1); - tracep->declBus(c+183,"o_console_data", false,-1, 6,0); - tracep->declBit(c+195,"o_dbg", false,-1); - tracep->declBit(c+548,"soft_reset", false,-1); - tracep->declBit(c+195,"r_wdt_reset", false,-1); - tracep->declBit(c+5077,"cmd_port_active", false,-1); - tracep->declBit(c+549,"rx_valid", false,-1); - tracep->declBus(c+550,"rx_data", false,-1, 7,0); - tracep->declBit(c+551,"in_stb", false,-1); - tracep->declBit(c+552,"in_active", false,-1); - tracep->declQuad(c+553,"in_word", false,-1, 35,0); - tracep->declBit(c+193,"ps_full", false,-1); - tracep->declBus(c+191,"ps_data", false,-1, 7,0); - tracep->declBit(c+555,"wbu_tx_stb", false,-1); - tracep->declBus(c+556,"wbu_tx_data", false,-1, 7,0); - tracep->declBit(c+557,"ififo_valid", false,-1); - tracep->declQuad(c+558,"ififo_codword", false,-1, 35,0); - tracep->declBit(c+560,"exec_stb", false,-1); - tracep->declQuad(c+561,"exec_word", false,-1, 35,0); - tracep->declBit(c+563,"ofifo_rd", false,-1); - tracep->declQuad(c+564,"ofifo_codword", false,-1, 35,0); - tracep->declBit(c+566,"ofifo_err", false,-1); - tracep->declBit(c+567,"ofifo_empty_n", false,-1); - tracep->declBit(c+568,"w_bus_busy", false,-1); - tracep->declBit(c+195,"w_bus_reset", false,-1); - tracep->declBus(c+569,"r_wdt_timer", false,-1, 18,0); - tracep->declBit(c+570,"ign_input_busy", false,-1); - tracep->declBit(c+571,"output_busy", false,-1); - tracep->declBit(c+572,"out_active", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_OUTBOUND_FIFO "); - tracep->pushNamePrefix("busoutfifo "); - tracep->declBus(c+5188,"BW", false,-1, 31,0); - tracep->declBus(c+5061,"LGFLEN", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+195,"i_reset", false,-1); - tracep->declBit(c+560,"i_wr", false,-1); - tracep->declQuad(c+561,"i_data", false,-1, 35,0); - tracep->declBit(c+563,"i_rd", false,-1); - tracep->declQuad(c+564,"o_data", false,-1, 35,0); - tracep->declBit(c+567,"o_empty_n", false,-1); - tracep->declBit(c+566,"o_err", false,-1); - tracep->declBus(c+5189,"FLEN", false,-1, 31,0); - tracep->declBus(c+573,"r_wrptr", false,-1, 10,0); - tracep->declBus(c+574,"r_rdptr", false,-1, 10,0); - tracep->declBus(c+575,"nxt_wrptr", false,-1, 10,0); - tracep->declBus(c+576,"nxt_rdptr", false,-1, 10,0); - tracep->declBit(c+577,"will_overflow", false,-1); - tracep->declBit(c+578,"will_underflow", false,-1); - tracep->declBit(c+579,"r_empty_n", false,-1); - tracep->declBit(c+580,"w_write", false,-1); - tracep->declBit(c+581,"w_read", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("INPUT_FIFO "); - tracep->declBit(c+557,"ififo_empty_n", false,-1); - tracep->declBit(c+582,"ififo_err", false,-1); - tracep->declBit(c+583,"ififo_rd", false,-1); - tracep->declBit(c+5074,"gen_unused", false,-1); - tracep->pushNamePrefix("padififo "); - tracep->declBus(c+5188,"BW", false,-1, 31,0); - tracep->declBus(c+5153,"LGFLEN", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+195,"i_reset", false,-1); - tracep->declBit(c+551,"i_wr", false,-1); - tracep->declQuad(c+553,"i_data", false,-1, 35,0); - tracep->declBit(c+583,"i_rd", false,-1); - tracep->declQuad(c+558,"o_data", false,-1, 35,0); - tracep->declBit(c+557,"o_empty_n", false,-1); - tracep->declBit(c+582,"o_err", false,-1); - tracep->declBus(c+5120,"FLEN", false,-1, 31,0); - tracep->declBus(c+584,"r_wrptr", false,-1, 6,0); - tracep->declBus(c+585,"r_rdptr", false,-1, 6,0); - tracep->declBus(c+586,"nxt_wrptr", false,-1, 6,0); - tracep->declBus(c+587,"nxt_rdptr", false,-1, 6,0); - tracep->declBit(c+588,"will_overflow", false,-1); - tracep->declBit(c+589,"will_underflow", false,-1); - tracep->declBit(c+590,"r_empty_n", false,-1); - tracep->declBit(c+591,"w_write", false,-1); - tracep->declBit(c+592,"w_read", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("getinput "); - tracep->declBus(c+5070,"OPT_COMPRESSION", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+549,"i_stb", false,-1); - tracep->declBit(c+570,"o_busy", false,-1); - tracep->declBus(c+550,"i_byte", false,-1, 7,0); - tracep->declBit(c+548,"o_soft_reset", false,-1); - tracep->declBit(c+551,"o_stb", false,-1); - tracep->declBit(c+5074,"i_busy", false,-1); - tracep->declQuad(c+553,"o_codword", false,-1, 35,0); - tracep->declBit(c+552,"o_active", false,-1); - tracep->declBit(c+593,"hx_stb", false,-1); - tracep->declBit(c+594,"hx_valid", false,-1); - tracep->declBus(c+595,"hx_hexbits", false,-1, 5,0); - tracep->declBit(c+596,"cw_stb", false,-1); - tracep->declBit(c+597,"cw_busy", false,-1); - tracep->declBit(c+598,"cw_active", false,-1); - tracep->declQuad(c+599,"cw_word", false,-1, 35,0); - tracep->declBit(c+601,"cod_busy", false,-1); - tracep->declBit(c+602,"cod_active", false,-1); - tracep->pushNamePrefix("GEN_COMPRESSION "); - tracep->pushNamePrefix("unpack "); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+596,"i_stb", false,-1); - tracep->declBit(c+601,"o_busy", false,-1); - tracep->declQuad(c+599,"i_word", false,-1, 35,0); - tracep->declBit(c+551,"o_stb", false,-1); - tracep->declBit(c+5074,"i_busy", false,-1); - tracep->declQuad(c+553,"o_word", false,-1, 35,0); - tracep->declBit(c+602,"o_active", false,-1); - tracep->declBus(c+603,"wr_addr", false,-1, 7,0); - tracep->declQuad(c+604,"r_word", false,-1, 35,0); - tracep->declBus(c+606,"cmd_addr", false,-1, 7,0); - tracep->declBus(c+607,"r_addr", false,-1, 24,0); - tracep->declBus(c+608,"w_addr", false,-1, 31,0); - tracep->declBus(c+609,"rd_len", false,-1, 9,0); - tracep->declBus(c+610,"cword", false,-1, 31,0); - tracep->declBus(c+611,"r_stb", false,-1, 2,0); - tracep->declBit(c+612,"cmd_write_not_compressed", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("formcw "); - tracep->declBus(c+5113,"OPT_SKIDBUFFER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+593,"i_stb", false,-1); - tracep->declBit(c+597,"o_busy", false,-1); - tracep->declBit(c+594,"i_valid", false,-1); - tracep->declBus(c+595,"i_hexbits", false,-1, 5,0); - tracep->declBit(c+596,"o_stb", false,-1); - tracep->declBit(c+601,"i_busy", false,-1); - tracep->declQuad(c+599,"o_codword", false,-1, 35,0); - tracep->declBit(c+598,"o_active", false,-1); - tracep->declBus(c+613,"r_len", false,-1, 2,0); - tracep->declBus(c+614,"cw_len", false,-1, 2,0); - tracep->declBus(c+615,"lastcw", false,-1, 1,0); - tracep->declBit(c+616,"w_stb", false,-1); - tracep->declQuad(c+617,"shiftreg", false,-1, 35,0); - tracep->declBit(c+593,"skd_stb", false,-1); - tracep->declBit(c+594,"skd_valid", false,-1); - tracep->declBus(c+595,"skd_hexbits", false,-1, 5,0); - tracep->declBit(c+597,"skd_busy", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("tobits "); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+549,"i_stb", false,-1); - tracep->declBit(c+570,"o_busy", false,-1); - tracep->declBus(c+550,"i_byte", false,-1, 7,0); - tracep->declBit(c+548,"o_soft_reset", false,-1); - tracep->declBit(c+593,"o_stb", false,-1); - tracep->declBit(c+594,"o_valid", false,-1); - tracep->declBit(c+597,"i_busy", false,-1); - tracep->declBus(c+595,"o_hexbits", false,-1, 5,0); - tracep->declBus(c+2,"k", false,-1, 31,0); - tracep->declBus(c+3,"newv", false,-1, 6,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("runwb "); - tracep->declBus(c+5113,"OPT_COUNT_FIFO", false,-1, 0,0); - tracep->declBus(c+5065,"LGFIFO", false,-1, 31,0); - tracep->declBus(c+5187,"AW", false,-1, 31,0); - tracep->declBus(c+5114,"DW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+195,"i_reset", false,-1); - tracep->declBit(c+557,"i_valid", false,-1); - tracep->declQuad(c+558,"i_codword", false,-1, 35,0); - tracep->declBit(c+568,"o_busy", false,-1); - tracep->declBit(c+410,"o_wb_cyc", false,-1); - tracep->declBit(c+411,"o_wb_stb", false,-1); - tracep->declBit(c+412,"o_wb_we", false,-1); - tracep->declBus(c+436,"o_wb_addr", false,-1, 29,0); - tracep->declBus(c+414,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+415,"i_wb_stall", false,-1); - tracep->declBit(c+416,"i_wb_ack", false,-1); - tracep->declBus(c+418,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+417,"i_wb_err", false,-1); - tracep->declBit(c+560,"o_stb", false,-1); - tracep->declQuad(c+561,"o_codword", false,-1, 35,0); - tracep->declBit(c+563,"i_fifo_rd", false,-1); - tracep->declBus(c+5116,"WB_IDLE", false,-1, 1,0); - tracep->declBus(c+5117,"WB_READ_REQUEST", false,-1, 1,0); - tracep->declBus(c+5118,"WB_WRITE_REQUEST", false,-1, 1,0); - tracep->declBus(c+5119,"WB_FLUSH_WRITE_REQUESTS", false,-1, 1,0); - tracep->declBus(c+5117,"WRITE_PREFIX", false,-1, 1,0); - tracep->declBus(c+619,"w_cod_data", false,-1, 31,0); - tracep->declBus(c+620,"wb_state", false,-1, 1,0); - tracep->declBus(c+621,"r_acks_needed", false,-1, 9,0); - tracep->declBus(c+622,"r_len", false,-1, 9,0); - tracep->declBit(c+623,"r_inc", false,-1); - tracep->declBit(c+624,"r_new_addr", false,-1); - tracep->declBit(c+625,"last_read_request", false,-1); - tracep->declBit(c+626,"last_ack", false,-1); - tracep->declBit(c+627,"zero_acks", false,-1); - tracep->declBit(c+568,"r_busy", false,-1); - tracep->declBus(c+628,"wide_addr", false,-1, 31,0); - tracep->declBus(c+5190,"fifo_space_available", false,-1, 4,0); - tracep->declBit(c+5077,"space_available", false,-1); - tracep->pushNamePrefix("NO_FIFO "); - tracep->declBit(c+5074,"unused_count", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("wroutput "); - tracep->declBus(c+5070,"OPT_COMPRESSION", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_IDLES", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+195,"i_soft_reset", false,-1); - tracep->declBit(c+563,"i_stb", false,-1); - tracep->declBit(c+571,"o_busy", false,-1); - tracep->declQuad(c+564,"i_codword", false,-1, 35,0); - tracep->declBit(c+410,"i_wb_cyc", false,-1); - tracep->declBit(c+189,"i_int", false,-1); - tracep->declBit(c+629,"i_bus_busy", false,-1); - tracep->declBit(c+555,"o_stb", false,-1); - tracep->declBit(c+572,"o_active", false,-1); - tracep->declBus(c+556,"o_char", false,-1, 7,0); - tracep->declBit(c+193,"i_tx_busy", false,-1); - tracep->declBit(c+630,"dw_busy", false,-1); - tracep->declBit(c+571,"cw_stb", false,-1); - tracep->declBit(c+571,"cw_busy", false,-1); - tracep->declBit(c+631,"cp_stb", false,-1); - tracep->declBit(c+630,"dw_stb", false,-1); - tracep->declBit(c+632,"ln_stb", false,-1); - tracep->declBit(c+633,"ln_busy", false,-1); - tracep->declBit(c+634,"cp_busy", false,-1); - tracep->declBit(c+635,"byte_busy", false,-1); - tracep->declBit(c+636,"cp_active", false,-1); - tracep->declBit(c+637,"dw_active", false,-1); - tracep->declBit(c+638,"ln_active", false,-1); - tracep->declQuad(c+639,"cw_codword", false,-1, 35,0); - tracep->declQuad(c+641,"cp_word", false,-1, 35,0); - tracep->declBus(c+643,"dw_bits", false,-1, 6,0); - tracep->declBus(c+644,"ln_bits", false,-1, 6,0); - tracep->declBit(c+645,"r_active", false,-1); - tracep->pushNamePrefix("GEN_COMPRESSION "); - tracep->pushNamePrefix("packit "); - tracep->declBus(c+5114,"DW", false,-1, 31,0); - tracep->declBus(c+5188,"CW", false,-1, 31,0); - tracep->declBus(c+5061,"TBITS", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+195,"i_reset", false,-1); - tracep->declBit(c+571,"i_stb", false,-1); - tracep->declQuad(c+639,"i_codword", false,-1, 35,0); - tracep->declBit(c+630,"i_busy", false,-1); - tracep->declBit(c+631,"o_stb", false,-1); - tracep->declQuad(c+641,"o_cword", false,-1, 35,0); - tracep->declBit(c+634,"o_busy", false,-1); - tracep->declBit(c+636,"o_active", false,-1); - tracep->declBit(c+646,"aword_valid", false,-1); - tracep->declQuad(c+647,"a_addrword", false,-1, 35,0); - tracep->declBus(c+649,"w_addr", false,-1, 31,0); - tracep->declBus(c+650,"addr_zcheck", false,-1, 3,0); - tracep->declBit(c+651,"tbl_busy", false,-1); - tracep->declBit(c+652,"w_accepted", false,-1); - tracep->declQuad(c+653,"r_word", false,-1, 35,0); - tracep->declBus(c+655,"tbl_addr", false,-1, 9,0); - tracep->declBit(c+656,"tbl_filled", false,-1); - tracep->declBus(c+657,"rd_addr", false,-1, 9,0); - tracep->declBit(c+658,"pmatch", false,-1); - tracep->declBit(c+659,"dmatch", false,-1); - tracep->declBit(c+660,"vaddr", false,-1); - tracep->declBus(c+661,"cword", false,-1, 31,0); - tracep->declBus(c+662,"maddr", false,-1, 9,0); - tracep->declBit(c+663,"matched", false,-1); - tracep->declBit(c+664,"zmatch", false,-1); - tracep->declBit(c+665,"hmatch", false,-1); - tracep->declBus(c+666,"adr_dbld", false,-1, 9,0); - tracep->declBus(c+667,"adr_hlfd", false,-1, 2,0); - tracep->declQuad(c+641,"r_cword", false,-1, 35,0); - tracep->declBus(c+668,"dffaddr", false,-1, 9,0); - tracep->declBit(c+669,"clear_table", false,-1); - tracep->declBit(c+670,"addr_within_table", false,-1); - tracep->declBit(c+671,"w_match", false,-1); - tracep->declBus(c+4,"k", false,-1, 31,0); - tracep->declBit(c+672,"unused", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("GEN_IDLES "); - tracep->pushNamePrefix("buildcw "); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+195,"i_reset", false,-1); - tracep->declBit(c+563,"i_stb", false,-1); - tracep->declQuad(c+564,"i_codword", false,-1, 35,0); - tracep->declBit(c+410,"i_cyc", false,-1); - tracep->declBit(c+629,"i_busy", false,-1); - tracep->declBit(c+189,"i_int", false,-1); - tracep->declBit(c+571,"o_stb", false,-1); - tracep->declQuad(c+639,"o_codword", false,-1, 35,0); - tracep->declBit(c+571,"o_busy", false,-1); - tracep->declBit(c+673,"i_tx_busy", false,-1); - tracep->declQuad(c+5191,"CW_INTERRUPT", false,-1, 35,0); - tracep->declQuad(c+5193,"CW_BUSBUSY", false,-1, 35,0); - tracep->declQuad(c+5195,"CW_IDLE", false,-1, 35,0); - tracep->declBus(c+5068,"IDLEBITS", false,-1, 31,0); - tracep->declBit(c+674,"int_request", false,-1); - tracep->declBit(c+675,"int_sent", false,-1); - tracep->declBit(c+676,"idle_expired", false,-1); - tracep->declBit(c+677,"idle_state", false,-1); - tracep->declBus(c+678,"idle_counter", false,-1, 21,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("deword "); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+631,"i_stb", false,-1); - tracep->declQuad(c+641,"i_word", false,-1, 35,0); - tracep->declBit(c+633,"i_tx_busy", false,-1); - tracep->declBit(c+630,"o_stb", false,-1); - tracep->declBus(c+643,"o_nl_hexbits", false,-1, 6,0); - tracep->declBit(c+630,"o_busy", false,-1); - tracep->declBit(c+637,"o_active", false,-1); - tracep->declBus(c+679,"w_len", false,-1, 2,0); - tracep->declBus(c+680,"r_len", false,-1, 2,0); - tracep->declBus(c+681,"r_word", false,-1, 29,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("linepacker "); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+630,"i_stb", false,-1); - tracep->declBus(c+643,"i_nl_hexbits", false,-1, 6,0); - tracep->declBit(c+632,"o_stb", false,-1); - tracep->declBus(c+644,"o_nl_hexbits", false,-1, 6,0); - tracep->declBit(c+682,"i_bus_busy", false,-1); - tracep->declBit(c+635,"i_tx_busy", false,-1); - tracep->declBit(c+633,"o_busy", false,-1); - tracep->declBit(c+638,"o_active", false,-1); - tracep->declBus(c+5197,"MAX_LINE_LENGTH", false,-1, 6,0); - tracep->declBus(c+5198,"TRIGGER_LENGTH", false,-1, 6,0); - tracep->declBit(c+683,"last_out_nl", false,-1); - tracep->declBit(c+684,"last_in_nl", false,-1); - tracep->declBit(c+685,"full_line", false,-1); - tracep->declBit(c+686,"r_busy", false,-1); - tracep->declBus(c+687,"linelen", false,-1, 6,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("mkbytes "); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+632,"i_stb", false,-1); - tracep->declBus(c+644,"i_bits", false,-1, 6,0); - tracep->declBit(c+555,"o_stb", false,-1); - tracep->declBus(c+556,"o_char", false,-1, 7,0); - tracep->declBit(c+635,"o_busy", false,-1); - tracep->declBit(c+193,"i_busy", false,-1); - tracep->declBus(c+5,"newv", false,-1, 6,0); - tracep->declBus(c+6,"k", false,-1, 31,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("gpioi "); - tracep->declBus(c+5069,"NIN", false,-1, 31,0); - tracep->declBus(c+5063,"NOUT", false,-1, 31,0); - tracep->declBus(c+5109,"DEFAULT", false,-1, 7,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4488,"i_wb_cyc", false,-1); - tracep->declBit(c+4493,"i_wb_stb", false,-1); - tracep->declBit(c+4490,"i_wb_we", false,-1); - tracep->declBus(c+4491,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4492,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+4493,"o_wb_ack", false,-1); - tracep->declBus(c+5010,"o_wb_data", false,-1, 31,0); - tracep->declBus(c+5003,"i_gpio", false,-1, 15,0); - tracep->declBus(c+5004,"o_gpio", false,-1, 7,0); - tracep->declBit(c+167,"o_int", false,-1); - tracep->declBus(c+688,"r_gpio", false,-1, 15,0); - tracep->declBus(c+689,"x_gpio", false,-1, 15,0); - tracep->declBus(c+690,"q_gpio", false,-1, 15,0); - tracep->declBus(c+688,"hi_bits", false,-1, 15,0); - tracep->declBus(c+5014,"low_bits", false,-1, 15,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("i2ci "); - tracep->declBus(c+5068,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"DATA_WIDTH", false,-1, 31,0); - tracep->declBus(c+5063,"I2C_WIDTH", false,-1, 31,0); - tracep->declBus(c+5075,"AXIS_ID_WIDTH", false,-1, 31,0); - tracep->declBus(c+5116,"DEF_CHANNEL", false,-1, 1,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5063,"RW", false,-1, 31,0); - tracep->declBus(c+5199,"BAW", false,-1, 31,0); - tracep->declBus(c+5200,"RESET_ADDRESS", false,-1, 27,0); - tracep->declBus(c+5070,"OPT_START_HALTED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_MANUAL", false,-1, 0,0); - tracep->declBus(c+5076,"OPT_WATCHDOG", false,-1, 31,0); - tracep->declBus(c+5201,"DEF_CKCOUNT", false,-1, 11,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4515,"i_wb_cyc", false,-1); - tracep->declBit(c+4516,"i_wb_stb", false,-1); - tracep->declBit(c+4517,"i_wb_we", false,-1); - tracep->declBus(c+4574,"i_wb_addr", false,-1, 1,0); - tracep->declBus(c+4519,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4520,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+395,"o_wb_ack", false,-1); - tracep->declBus(c+396,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+239,"o_pf_cyc", false,-1); - tracep->declBit(c+240,"o_pf_stb", false,-1); - tracep->declBit(c+5074,"o_pf_we", false,-1); - tracep->declBus(c+241,"o_pf_addr", false,-1, 21,0); - tracep->declArray(c+5078,"o_pf_data", false,-1, 511,0); - tracep->declQuad(c+5094,"o_pf_sel", false,-1, 63,0); - tracep->declBit(c+242,"i_pf_stall", false,-1); - tracep->declBit(c+243,"i_pf_ack", false,-1); - tracep->declBit(c+244,"i_pf_err", false,-1); - tracep->declArray(c+245,"i_pf_data", false,-1, 511,0); - tracep->declBit(c+4975,"i_i2c_sda", false,-1); - tracep->declBit(c+4976,"i_i2c_scl", false,-1); - tracep->declBit(c+4977,"o_i2c_sda", false,-1); - tracep->declBit(c+4978,"o_i2c_scl", false,-1); - tracep->declBit(c+174,"M_AXIS_TVALID", false,-1); - tracep->declBit(c+175,"M_AXIS_TREADY", false,-1); - tracep->declBus(c+177,"M_AXIS_TDATA", false,-1, 7,0); - tracep->declBit(c+176,"M_AXIS_TLAST", false,-1); - tracep->declBus(c+178,"M_AXIS_TID", false,-1, 1,0); - tracep->declBit(c+5074,"i_sync_signal", false,-1); - tracep->declBus(c+37,"o_debug", false,-1, 31,0); - tracep->declBus(c+5116,"ADR_CONTROL", false,-1, 1,0); - tracep->declBus(c+5117,"ADR_OVERRIDE", false,-1, 1,0); - tracep->declBus(c+5118,"ADR_ADDRESS", false,-1, 1,0); - tracep->declBus(c+5119,"ADR_CKCOUNT", false,-1, 1,0); - tracep->declBus(c+5073,"HALT_BIT", false,-1, 31,0); - tracep->declBus(c+5110,"ERR_BIT", false,-1, 31,0); - tracep->declBus(c+5121,"ABORT_BIT", false,-1, 31,0); - tracep->declBus(c+5068,"SOFTHALT_BIT", false,-1, 31,0); - tracep->declBus(c+5156,"OVW_VALID", false,-1, 31,0); - tracep->declBus(c+5157,"MANUAL_BIT", false,-1, 31,0); - tracep->declBus(c+5122,"CMD_NOOP", false,-1, 3,0); - tracep->declBus(c+5124,"CMD_STOP", false,-1, 3,0); - tracep->declBus(c+5125,"CMD_SEND", false,-1, 3,0); - tracep->declBus(c+5126,"CMD_RXK", false,-1, 3,0); - tracep->declBus(c+5127,"CMD_RXN", false,-1, 3,0); - tracep->declBus(c+5115,"CMD_RXLK", false,-1, 3,0); - tracep->declBus(c+5128,"CMD_RXLN", false,-1, 3,0); - tracep->declBus(c+5129,"CMD_WAIT", false,-1, 3,0); - tracep->declBus(c+5202,"CMD_HALT", false,-1, 3,0); - tracep->declBus(c+5203,"CMD_ABORT", false,-1, 3,0); - tracep->declBus(c+5204,"CMD_TARGET", false,-1, 3,0); - tracep->declBus(c+5205,"CMD_JUMP", false,-1, 3,0); - tracep->declBus(c+5206,"CMD_CHANNEL", false,-1, 3,0); - tracep->declBit(c+691,"cpu_reset", false,-1); - tracep->declBit(c+5074,"cpu_clear_cache", false,-1); - tracep->declBit(c+692,"cpu_new_pc", false,-1); - tracep->declBus(c+693,"pf_jump_addr", false,-1, 27,0); - tracep->declBit(c+694,"pf_valid", false,-1); - tracep->declBit(c+695,"pf_ready", false,-1); - tracep->declBus(c+696,"pf_insn", false,-1, 7,0); - tracep->declBus(c+697,"pf_insn_addr", false,-1, 27,0); - tracep->declBit(c+698,"pf_illegal", false,-1); - tracep->declBit(c+699,"half_valid", false,-1); - tracep->declBit(c+700,"imm_cycle", false,-1); - tracep->declBit(c+4575,"next_valid", false,-1); - tracep->declBus(c+4576,"next_insn", false,-1, 7,0); - tracep->declBit(c+701,"insn_ready", false,-1); - tracep->declBit(c+702,"half_ready", false,-1); - tracep->declBit(c+703,"i2c_abort", false,-1); - tracep->declBit(c+704,"insn_valid", false,-1); - tracep->declBus(c+705,"insn", false,-1, 11,0); - tracep->declBus(c+706,"half_insn", false,-1, 3,0); - tracep->declBit(c+707,"i2c_ckedge", false,-1); - tracep->declBit(c+708,"i2c_stretch", false,-1); - tracep->declBus(c+709,"i2c_ckcount", false,-1, 11,0); - tracep->declBus(c+710,"ckcount", false,-1, 11,0); - tracep->declBus(c+711,"abort_address", false,-1, 27,0); - tracep->declBus(c+712,"jump_target", false,-1, 27,0); - tracep->declBit(c+713,"r_wait", false,-1); - tracep->declBit(c+714,"soft_halt_request", false,-1); - tracep->declBit(c+691,"r_halted", false,-1); - tracep->declBit(c+715,"r_err", false,-1); - tracep->declBit(c+716,"r_aborted", false,-1); - tracep->declBit(c+717,"r_manual", false,-1); - tracep->declBit(c+718,"r_sda", false,-1); - tracep->declBit(c+719,"r_scl", false,-1); - tracep->declBit(c+720,"w_stopped", false,-1); - tracep->declBit(c+721,"w_sda", false,-1); - tracep->declBit(c+722,"w_scl", false,-1); - tracep->declBit(c+4577,"bus_read", false,-1); - tracep->declBit(c+4578,"bus_write", false,-1); - tracep->declBit(c+4579,"bus_override", false,-1); - tracep->declBit(c+4580,"bus_manual", false,-1); - tracep->declBit(c+723,"ovw_ready", false,-1); - tracep->declBit(c+4581,"bus_jump", false,-1); - tracep->declBus(c+4574,"bus_write_addr", false,-1, 1,0); - tracep->declBus(c+4574,"bus_read_addr", false,-1, 1,0); - tracep->declBus(c+4519,"bus_write_data", false,-1, 31,0); - tracep->declBus(c+4520,"bus_write_strb", false,-1, 3,0); - tracep->declBus(c+396,"bus_read_data", false,-1, 31,0); - tracep->declBit(c+724,"s_tvalid", false,-1); - tracep->declBit(c+702,"s_tready", false,-1); - tracep->declBus(c+725,"ovw_data", false,-1, 9,0); - tracep->declBus(c+39,"w_control", false,-1, 31,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_MANUAL "); - tracep->declBit(c+717,"manual", false,-1); - tracep->declBit(c+719,"scl", false,-1); - tracep->declBit(c+718,"sda", false,-1); - tracep->declBit(c+726,"o_scl", false,-1); - tracep->declBit(c+727,"o_sda", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_TID "); - tracep->declBit(c+728,"mid_axis_pkt", false,-1); - tracep->declBus(c+729,"r_channel", false,-1, 1,0); - tracep->declBus(c+178,"axis_tid", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_axisi2c "); - tracep->declBus(c+5076,"OPT_WATCHDOG", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"S_AXI_ACLK", false,-1); - tracep->declBit(c+40,"S_AXI_ARESETN", false,-1); - tracep->declBit(c+724,"S_AXIS_TVALID", false,-1); - tracep->declBit(c+701,"S_AXIS_TREADY", false,-1); - tracep->declBus(c+730,"S_AXIS_TDATA", false,-1, 10,0); - tracep->declBit(c+174,"M_AXIS_TVALID", false,-1); - tracep->declBit(c+175,"M_AXIS_TREADY", false,-1); - tracep->declBus(c+177,"M_AXIS_TDATA", false,-1, 7,0); - tracep->declBit(c+176,"M_AXIS_TLAST", false,-1); - tracep->declBit(c+707,"i_ckedge", false,-1); - tracep->declBit(c+708,"o_stretch", false,-1); - tracep->declBit(c+4976,"i_scl", false,-1); - tracep->declBit(c+4975,"i_sda", false,-1); - tracep->declBit(c+722,"o_scl", false,-1); - tracep->declBit(c+721,"o_sda", false,-1); - tracep->declBit(c+703,"o_abort", false,-1); - tracep->declBus(c+5122,"IDLE_STOPPED", false,-1, 3,0); - tracep->declBus(c+5123,"START", false,-1, 3,0); - tracep->declBus(c+5124,"IDLE_ACTIVE", false,-1, 3,0); - tracep->declBus(c+5125,"STOP", false,-1, 3,0); - tracep->declBus(c+5126,"DATA", false,-1, 3,0); - tracep->declBus(c+5127,"CLOCK", false,-1, 3,0); - tracep->declBus(c+5115,"ACK", false,-1, 3,0); - tracep->declBus(c+5128,"CKACKLO", false,-1, 3,0); - tracep->declBus(c+5129,"CKACKHI", false,-1, 3,0); - tracep->declBus(c+5202,"RXNAK", false,-1, 3,0); - tracep->declBus(c+5203,"ABORT", false,-1, 3,0); - tracep->declBus(c+5204,"REPEAT_START", false,-1, 3,0); - tracep->declBus(c+5205,"REPEAT_START2", false,-1, 3,0); - tracep->declBus(c+5113,"D_RD", false,-1, 0,0); - tracep->declBus(c+5070,"D_WR", false,-1, 0,0); - tracep->declBus(c+5159,"CMD_NOOP", false,-1, 2,0); - tracep->declBus(c+5166,"CMD_START", false,-1, 2,0); - tracep->declBus(c+5160,"CMD_STOP", false,-1, 2,0); - tracep->declBus(c+5162,"CMD_SEND", false,-1, 2,0); - tracep->declBus(c+5207,"CMD_RXK", false,-1, 2,0); - tracep->declBus(c+5208,"CMD_RXN", false,-1, 2,0); - tracep->declBus(c+5209,"CMD_RXLK", false,-1, 2,0); - tracep->declBus(c+5210,"CMD_RXLN", false,-1, 2,0); - tracep->declBus(c+5113,"OPT_ABORT_REQUEST", false,-1, 0,0); - tracep->declBit(c+731,"last_byte", false,-1); - tracep->declBit(c+732,"dir", false,-1); - tracep->declBit(c+733,"will_ack", false,-1); - tracep->declBus(c+734,"state", false,-1, 3,0); - tracep->declBus(c+735,"nbits", false,-1, 2,0); - tracep->declBus(c+736,"sreg", false,-1, 7,0); - tracep->declBit(c+737,"q_scl", false,-1); - tracep->declBit(c+738,"q_sda", false,-1); - tracep->declBit(c+739,"ck_scl", false,-1); - tracep->declBit(c+740,"ck_sda", false,-1); - tracep->declBit(c+741,"lst_scl", false,-1); - tracep->declBit(c+742,"lst_sda", false,-1); - tracep->declBit(c+743,"stop_bit", false,-1); - tracep->declBit(c+744,"channel_busy", false,-1); - tracep->declBit(c+5074,"watchdog_timeout", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_fetch "); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5063,"INSN_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"DATA_WIDTH", false,-1, 31,0); - tracep->declBus(c+5199,"AW", false,-1, 31,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+41,"i_reset", false,-1); - tracep->declBit(c+692,"i_new_pc", false,-1); - tracep->declBit(c+5074,"i_clear_cache", false,-1); - tracep->declBit(c+695,"i_ready", false,-1); - tracep->declBus(c+693,"i_pc", false,-1, 27,0); - tracep->declBit(c+694,"o_valid", false,-1); - tracep->declBit(c+698,"o_illegal", false,-1); - tracep->declBus(c+696,"o_insn", false,-1, 7,0); - tracep->declBus(c+697,"o_pc", false,-1, 27,0); - tracep->declBit(c+239,"o_wb_cyc", false,-1); - tracep->declBit(c+240,"o_wb_stb", false,-1); - tracep->declBit(c+5074,"o_wb_we", false,-1); - tracep->declBus(c+241,"o_wb_addr", false,-1, 21,0); - tracep->declArray(c+5078,"o_wb_data", false,-1, 511,0); - tracep->declBit(c+242,"i_wb_stall", false,-1); - tracep->declBit(c+243,"i_wb_ack", false,-1); - tracep->declBit(c+244,"i_wb_err", false,-1); - tracep->declArray(c+245,"i_wb_data", false,-1, 511,0); - tracep->declBit(c+745,"last_stb", false,-1); - tracep->declBit(c+746,"invalid_bus_cycle", false,-1); - tracep->declArray(c+747,"cache_word", false,-1, 511,0); - tracep->declBit(c+763,"cache_valid", false,-1); - tracep->declBus(c+764,"inflight", false,-1, 1,0); - tracep->declBit(c+765,"cache_illegal", false,-1); - tracep->declBit(c+766,"r_valid", false,-1); - tracep->declArray(c+767,"r_insn", false,-1, 511,0); - tracep->declArray(c+783,"i_wb_shifted", false,-1, 511,0); - tracep->pushNamePrefix("GEN_SUBSHIFT "); - tracep->declBus(c+5153,"NSHIFT", false,-1, 31,0); - tracep->declBit(c+766,"rg_valid", false,-1); - tracep->declArray(c+767,"rg_insn", false,-1, 511,0); - tracep->declBus(c+799,"r_count", false,-1, 6,0); - tracep->declBus(c+800,"r_shift", false,-1, 5,0); - tracep->declBit(c+5074,"unused_shift", false,-1); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("i2cscopei "); - tracep->declBus(c+5211,"LGMEM", false,-1, 4,0); - tracep->declBus(c+5114,"BUSW", false,-1, 31,0); - tracep->declBus(c+5184,"NELM", false,-1, 31,0); - tracep->declBus(c+5070,"SYNCHRONOUS", false,-1, 0,0); - tracep->declBus(c+5110,"HOLDOFFBITS", false,-1, 31,0); - tracep->declBus(c+5212,"DEFAULT_HOLDOFF", false,-1, 19,0); - tracep->declBus(c+5184,"STEP_BITS", false,-1, 31,0); - tracep->declBus(c+5186,"MAX_STEP", false,-1, 30,0); - tracep->declBit(c+4901,"i_data_clk", false,-1); - tracep->declBit(c+5077,"i_ce", false,-1); - tracep->declBit(c+716,"i_trigger", false,-1); - tracep->declBus(c+42,"i_data", false,-1, 30,0); - tracep->declBit(c+4901,"i_wb_clk", false,-1); - tracep->declBit(c+4503,"i_wb_cyc", false,-1); - tracep->declBit(c+4504,"i_wb_stb", false,-1); - tracep->declBit(c+4505,"i_wb_we", false,-1); - tracep->declBit(c+4582,"i_wb_addr", false,-1); - tracep->declBus(c+4507,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4508,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+391,"o_wb_ack", false,-1); - tracep->declBus(c+392,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+166,"o_interrupt", false,-1); - tracep->declBit(c+4583,"write_stb", false,-1); - tracep->declBit(c+4584,"read_from_data", false,-1); - tracep->declBit(c+4585,"write_to_control", false,-1); - tracep->declBus(c+392,"o_bus_data", false,-1, 31,0); - tracep->declBit(c+4901,"bus_clock", false,-1); - tracep->declBit(c+801,"read_address", false,-1); - tracep->declBus(c+4507,"i_bus_data", false,-1, 31,0); - tracep->declBus(c+802,"raddr", false,-1, 9,0); - tracep->declBus(c+803,"waddr", false,-1, 9,0); - tracep->declBit(c+804,"bw_reset_request", false,-1); - tracep->declBit(c+805,"bw_manual_trigger", false,-1); - tracep->declBit(c+806,"bw_disable_trigger", false,-1); - tracep->declBit(c+804,"bw_reset_complete", false,-1); - tracep->declBus(c+807,"br_config", false,-1, 2,0); - tracep->declBus(c+808,"br_holdoff", false,-1, 19,0); - tracep->declBus(c+809,"holdoff_counter", false,-1, 19,0); - tracep->declBit(c+804,"dw_reset", false,-1); - tracep->declBit(c+805,"dw_manual_trigger", false,-1); - tracep->declBit(c+806,"dw_disable_trigger", false,-1); - tracep->declBit(c+810,"dr_triggered", false,-1); - tracep->declBit(c+811,"dr_primed", false,-1); - tracep->declBit(c+812,"dw_trigger", false,-1); - tracep->declBit(c+813,"dr_stopped", false,-1); - tracep->declBus(c+5154,"DLYSTOP", false,-1, 31,0); - tracep->declBus(c+814,"dr_stop_pipe", false,-1, 4,0); - tracep->declBit(c+815,"dw_final_stop", false,-1); - tracep->declBus(c+816,"ck_addr", false,-1, 30,0); - tracep->declBus(c+817,"qd_data", false,-1, 30,0); - tracep->declBit(c+818,"dr_force_write", false,-1); - tracep->declBit(c+819,"dr_run_timeout", false,-1); - tracep->declBit(c+820,"new_data", false,-1); - tracep->declBit(c+821,"dr_force_inhibit", false,-1); - tracep->declBus(c+817,"w_data", false,-1, 30,0); - tracep->declBit(c+822,"imm_adr", false,-1); - tracep->declBit(c+823,"lst_adr", false,-1); - tracep->declBus(c+824,"lst_val", false,-1, 30,0); - tracep->declBus(c+825,"imm_val", false,-1, 30,0); - tracep->declBit(c+826,"record_ce", false,-1); - tracep->declBus(c+827,"r_data", false,-1, 31,0); - tracep->declBit(c+815,"bw_stopped", false,-1); - tracep->declBit(c+810,"bw_triggered", false,-1); - tracep->declBit(c+811,"bw_primed", false,-1); - tracep->declBit(c+391,"br_wb_ack", false,-1); - tracep->declBit(c+828,"br_pre_wb_ack", false,-1); - tracep->declBit(c+4504,"bw_cyc_stb", false,-1); - tracep->declBus(c+829,"this_addr", false,-1, 9,0); - tracep->declBus(c+830,"nxt_mem", false,-1, 31,0); - tracep->declBus(c+808,"full_holdoff", false,-1, 19,0); - tracep->declBus(c+5211,"bw_lgmem", false,-1, 4,0); - tracep->declBit(c+831,"br_level_interrupt", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("rcv "); - tracep->declBus(c+5072,"TIMER_BITS", false,-1, 31,0); - tracep->declBus(c+5213,"CLOCKS_PER_BAUD", false,-1, 6,0); - tracep->declBus(c+5072,"TB", false,-1, 31,0); - tracep->declBus(c+5122,"RXUL_BIT_ZERO", false,-1, 3,0); - tracep->declBus(c+5123,"RXUL_BIT_ONE", false,-1, 3,0); - tracep->declBus(c+5124,"RXUL_BIT_TWO", false,-1, 3,0); - tracep->declBus(c+5125,"RXUL_BIT_THREE", false,-1, 3,0); - tracep->declBus(c+5126,"RXUL_BIT_FOUR", false,-1, 3,0); - tracep->declBus(c+5127,"RXUL_BIT_FIVE", false,-1, 3,0); - tracep->declBus(c+5115,"RXUL_BIT_SIX", false,-1, 3,0); - tracep->declBus(c+5128,"RXUL_BIT_SEVEN", false,-1, 3,0); - tracep->declBus(c+5129,"RXUL_STOP", false,-1, 3,0); - tracep->declBus(c+5202,"RXUL_WAIT", false,-1, 3,0); - tracep->declBus(c+5108,"RXUL_IDLE", false,-1, 3,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5000,"i_uart_rx", false,-1); - tracep->declBit(c+192,"o_wr", false,-1); - tracep->declBus(c+190,"o_data", false,-1, 7,0); - tracep->declBus(c+5214,"half_baud", false,-1, 6,0); - tracep->declBus(c+832,"state", false,-1, 3,0); - tracep->declBus(c+833,"baud_counter", false,-1, 6,0); - tracep->declBit(c+834,"zero_baud_counter", false,-1); - tracep->declBit(c+835,"q_uart", false,-1); - tracep->declBit(c+836,"qq_uart", false,-1); - tracep->declBit(c+837,"ck_uart", false,-1); - tracep->declBus(c+838,"chg_counter", false,-1, 6,0); - tracep->declBit(c+839,"half_baud_time", false,-1); - tracep->declBus(c+840,"data_reg", false,-1, 7,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("sdioscopei "); - tracep->declBus(c+5183,"LGMEM", false,-1, 4,0); - tracep->declBus(c+5114,"BUSW", false,-1, 31,0); - tracep->declBus(c+5184,"NELM", false,-1, 31,0); - tracep->declBus(c+5070,"SYNCHRONOUS", false,-1, 0,0); - tracep->declBus(c+5110,"HOLDOFFBITS", false,-1, 31,0); - tracep->declBus(c+5185,"DEFAULT_HOLDOFF", false,-1, 19,0); - tracep->declBus(c+5184,"STEP_BITS", false,-1, 31,0); - tracep->declBus(c+5186,"MAX_STEP", false,-1, 30,0); - tracep->declBit(c+4901,"i_data_clk", false,-1); - tracep->declBit(c+5077,"i_ce", false,-1); - tracep->declBit(c+841,"i_trigger", false,-1); - tracep->declBus(c+842,"i_data", false,-1, 30,0); - tracep->declBit(c+4901,"i_wb_clk", false,-1); - tracep->declBit(c+4509,"i_wb_cyc", false,-1); - tracep->declBit(c+4510,"i_wb_stb", false,-1); - tracep->declBit(c+4511,"i_wb_we", false,-1); - tracep->declBit(c+4586,"i_wb_addr", false,-1); - tracep->declBus(c+4513,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4514,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+393,"o_wb_ack", false,-1); - tracep->declBus(c+394,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+159,"o_interrupt", false,-1); - tracep->declBit(c+4587,"write_stb", false,-1); - tracep->declBit(c+4588,"read_from_data", false,-1); - tracep->declBit(c+4589,"write_to_control", false,-1); - tracep->declBus(c+394,"o_bus_data", false,-1, 31,0); - tracep->declBit(c+4901,"bus_clock", false,-1); - tracep->declBit(c+843,"read_address", false,-1); - tracep->declBus(c+4513,"i_bus_data", false,-1, 31,0); - tracep->declBus(c+844,"raddr", false,-1, 11,0); - tracep->declBus(c+845,"waddr", false,-1, 11,0); - tracep->declBit(c+846,"bw_reset_request", false,-1); - tracep->declBit(c+847,"bw_manual_trigger", false,-1); - tracep->declBit(c+848,"bw_disable_trigger", false,-1); - tracep->declBit(c+846,"bw_reset_complete", false,-1); - tracep->declBus(c+849,"br_config", false,-1, 2,0); - tracep->declBus(c+850,"br_holdoff", false,-1, 19,0); - tracep->declBus(c+851,"holdoff_counter", false,-1, 19,0); - tracep->declBit(c+846,"dw_reset", false,-1); - tracep->declBit(c+847,"dw_manual_trigger", false,-1); - tracep->declBit(c+848,"dw_disable_trigger", false,-1); - tracep->declBit(c+852,"dr_triggered", false,-1); - tracep->declBit(c+853,"dr_primed", false,-1); - tracep->declBit(c+854,"dw_trigger", false,-1); - tracep->declBit(c+855,"dr_stopped", false,-1); - tracep->declBus(c+5154,"DLYSTOP", false,-1, 31,0); - tracep->declBus(c+856,"dr_stop_pipe", false,-1, 4,0); - tracep->declBit(c+857,"dw_final_stop", false,-1); - tracep->declBus(c+858,"ck_addr", false,-1, 30,0); - tracep->declBus(c+859,"qd_data", false,-1, 30,0); - tracep->declBit(c+860,"dr_force_write", false,-1); - tracep->declBit(c+861,"dr_run_timeout", false,-1); - tracep->declBit(c+862,"new_data", false,-1); - tracep->declBit(c+863,"dr_force_inhibit", false,-1); - tracep->declBus(c+859,"w_data", false,-1, 30,0); - tracep->declBit(c+864,"imm_adr", false,-1); - tracep->declBit(c+865,"lst_adr", false,-1); - tracep->declBus(c+866,"lst_val", false,-1, 30,0); - tracep->declBus(c+867,"imm_val", false,-1, 30,0); - tracep->declBit(c+868,"record_ce", false,-1); - tracep->declBus(c+869,"r_data", false,-1, 31,0); - tracep->declBit(c+857,"bw_stopped", false,-1); - tracep->declBit(c+852,"bw_triggered", false,-1); - tracep->declBit(c+853,"bw_primed", false,-1); - tracep->declBit(c+393,"br_wb_ack", false,-1); - tracep->declBit(c+870,"br_pre_wb_ack", false,-1); - tracep->declBit(c+4510,"bw_cyc_stb", false,-1); - tracep->declBus(c+871,"this_addr", false,-1, 11,0); - tracep->declBus(c+872,"nxt_mem", false,-1, 31,0); - tracep->declBus(c+850,"full_holdoff", false,-1, 19,0); - tracep->declBus(c+5183,"bw_lgmem", false,-1, 4,0); - tracep->declBit(c+873,"br_level_interrupt", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("spioi "); - tracep->declBus(c+5063,"NLEDS", false,-1, 31,0); - tracep->declBus(c+5154,"NBTN", false,-1, 31,0); - tracep->declBus(c+5063,"NSW", false,-1, 31,0); - tracep->declBus(c+5075,"NFF", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4488,"i_wb_cyc", false,-1); - tracep->declBit(c+4495,"i_wb_stb", false,-1); - tracep->declBit(c+4490,"i_wb_we", false,-1); - tracep->declBus(c+4491,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4492,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+387,"o_wb_ack", false,-1); - tracep->declBus(c+388,"o_wb_data", false,-1, 31,0); - tracep->declBus(c+5005,"i_sw", false,-1, 7,0); - tracep->declBus(c+5006,"i_btn", false,-1, 4,0); - tracep->declBus(c+196,"o_led", false,-1, 7,0); - tracep->declBit(c+168,"o_int", false,-1); - tracep->declBit(c+874,"led_demo", false,-1); - tracep->declBus(c+875,"r_led", false,-1, 7,0); - tracep->declBus(c+876,"w_btn", false,-1, 7,0); - tracep->declBus(c+877,"bounced", false,-1, 7,0); - tracep->declBus(c+878,"r_sw", false,-1, 7,0); - tracep->declBit(c+879,"sw_int", false,-1); - tracep->declBit(c+880,"btn_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_BUTTON "); - tracep->declBus(c+4590,"next_btn", false,-1, 4,0); - tracep->declBus(c+881,"s_btn", false,-1, 4,0); - tracep->declBus(c+882,"r_btn", false,-1, 4,0); - tracep->declBus(c+883,"btn_pipe", false,-1, 9,0); - tracep->declBit(c+880,"r_btn_int", false,-1); - tracep->declBit(c+4591,"next_int", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_SWITCHES "); - tracep->declBus(c+884,"sw_pipe", false,-1, 15,0); - tracep->declBus(c+878,"rr_sw", false,-1, 7,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("knightrider "); - tracep->declBus(c+5063,"NLEDS", false,-1, 31,0); - tracep->declBus(c+5132,"CTRBITS", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBus(c+877,"o_leds", false,-1, 7,0); - tracep->declBus(c+885,"led_owner", false,-1, 7,0); - tracep->declBit(c+886,"led_dir", false,-1); - tracep->declBus(c+887,"led_ctr", false,-1, 24,0); - tracep->declBit(c+888,"led_clk", false,-1); - tracep->declBus(c+889,"br_ctr", false,-1, 4,0); - tracep->pushNamePrefix("GEN_BRIGHTNESS[0] "); - tracep->declBus(c+890,"brightness", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_BRIGHTNESS[1] "); - tracep->declBus(c+891,"brightness", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_BRIGHTNESS[2] "); - tracep->declBus(c+892,"brightness", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_BRIGHTNESS[3] "); - tracep->declBus(c+893,"brightness", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_BRIGHTNESS[4] "); - tracep->declBus(c+894,"brightness", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_BRIGHTNESS[5] "); - tracep->declBus(c+895,"brightness", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_BRIGHTNESS[6] "); - tracep->declBus(c+896,"brightness", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_BRIGHTNESS[7] "); - tracep->declBus(c+897,"brightness", false,-1, 4,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("swic "); - tracep->declBus(c+5067,"RESET_ADDRESS", false,-1, 31,0); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5114,"DBG_WIDTH", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_PIPELINED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_EARLY_BRANCHING", false,-1, 0,0); - tracep->declBus(c+5158,"OPT_LGICACHE", false,-1, 31,0); - tracep->declBus(c+5158,"OPT_LGDCACHE", false,-1, 31,0); - tracep->declBus(c+5070,"START_HALTED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DISTRIBUTED_REGS", false,-1, 0,0); - tracep->declBus(c+5069,"EXTERNAL_INTERRUPTS", false,-1, 31,0); - tracep->declBus(c+5062,"OPT_MPY", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_DIV", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_SHIFTS", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_FPU", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_CIS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_LOCK", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_USERMODE", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DBGPORT", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_TRACE_PORT", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PROFILER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DMA", false,-1, 0,0); - tracep->declBus(c+5061,"DMA_LGMEM", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_ACCOUNTING", false,-1, 0,0); - tracep->declBus(c+5070,"DELAY_DBG_BUS", false,-1, 0,0); - tracep->declBus(c+5113,"DELAY_EXT_BUS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_SIM", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_CLKGATE", false,-1, 0,0); - tracep->declBus(c+5110,"RESET_DURATION", false,-1, 31,0); - tracep->declBus(c+5068,"PAW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5015,"i_reset", false,-1); - tracep->declBit(c+261,"o_wb_cyc", false,-1); - tracep->declBit(c+262,"o_wb_stb", false,-1); - tracep->declBit(c+263,"o_wb_we", false,-1); - tracep->declBus(c+264,"o_wb_addr", false,-1, 21,0); - tracep->declArray(c+265,"o_wb_data", false,-1, 511,0); - tracep->declQuad(c+281,"o_wb_sel", false,-1, 63,0); - tracep->declBit(c+283,"i_wb_stall", false,-1); - tracep->declBit(c+284,"i_wb_ack", false,-1); - tracep->declArray(c+286,"i_wb_data", false,-1, 511,0); - tracep->declBit(c+285,"i_wb_err", false,-1); - tracep->declBus(c+188,"i_ext_int", false,-1, 15,0); - tracep->declBit(c+189,"o_ext_int", false,-1); - tracep->declBit(c+43,"i_dbg_cyc", false,-1); - tracep->declBit(c+44,"i_dbg_stb", false,-1); - tracep->declBit(c+45,"i_dbg_we", false,-1); - tracep->declBus(c+46,"i_dbg_addr", false,-1, 6,0); - tracep->declBus(c+47,"i_dbg_data", false,-1, 31,0); - tracep->declBus(c+5016,"i_dbg_sel", false,-1, 3,0); - tracep->declBit(c+186,"o_dbg_stall", false,-1); - tracep->declBit(c+187,"o_dbg_ack", false,-1); - tracep->declBus(c+435,"o_dbg_data", false,-1, 31,0); - tracep->declBus(c+5076,"o_cpu_debug", false,-1, 31,0); - tracep->declBit(c+4996,"o_prof_stb", false,-1); - tracep->declBus(c+4997,"o_prof_addr", false,-1, 27,0); - tracep->declBus(c+4998,"o_prof_ticks", false,-1, 31,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5215,"PERIPHBASE", false,-1, 31,0); - tracep->declBus(c+5112,"INTCTRL", false,-1, 7,0); - tracep->declBus(c+5216,"WATCHDOG", false,-1, 7,0); - tracep->declBus(c+5217,"BUSWATCHDOG", false,-1, 7,0); - tracep->declBus(c+5218,"CTRINT", false,-1, 7,0); - tracep->declBus(c+5219,"TIMER_A", false,-1, 7,0); - tracep->declBus(c+5220,"TIMER_B", false,-1, 7,0); - tracep->declBus(c+5221,"TIMER_C", false,-1, 7,0); - tracep->declBus(c+5222,"JIFFIES", false,-1, 7,0); - tracep->declBus(c+5223,"MSTR_TASK_CTR", false,-1, 7,0); - tracep->declBus(c+5224,"MSTR_MSTL_CTR", false,-1, 7,0); - tracep->declBus(c+5225,"MSTR_PSTL_CTR", false,-1, 7,0); - tracep->declBus(c+5226,"MSTR_INST_CTR", false,-1, 7,0); - tracep->declBus(c+5227,"USER_TASK_CTR", false,-1, 7,0); - tracep->declBus(c+5228,"USER_MSTL_CTR", false,-1, 7,0); - tracep->declBus(c+5229,"USER_PSTL_CTR", false,-1, 7,0); - tracep->declBus(c+5230,"USER_INST_CTR", false,-1, 7,0); - tracep->declBus(c+5231,"MMU_ADDR", false,-1, 7,0); - tracep->declBus(c+5232,"DMAC_ADDR", false,-1, 7,0); - tracep->declBus(c+5076,"HALT_BIT", false,-1, 31,0); - tracep->declBus(c+5075,"STEP_BIT", false,-1, 31,0); - tracep->declBus(c+5062,"RESET_BIT", false,-1, 31,0); - tracep->declBus(c+5065,"CLEAR_CACHE_BIT", false,-1, 31,0); - tracep->declBus(c+5154,"CATCH_BIT", false,-1, 31,0); - tracep->declBus(c+5068,"VIRTUAL_ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5116,"DBG_ADDR_CTRL", false,-1, 1,0); - tracep->declBus(c+5117,"DBG_ADDR_CPU", false,-1, 1,0); - tracep->declBus(c+5118,"DBG_ADDR_SYS", false,-1, 1,0); - tracep->declBus(c+898,"main_int_vector", false,-1, 14,0); - tracep->declBus(c+899,"alt_int_vector", false,-1, 14,0); - tracep->declBit(c+900,"ctri_int", false,-1); - tracep->declBit(c+901,"tma_int", false,-1); - tracep->declBit(c+902,"tmb_int", false,-1); - tracep->declBit(c+903,"tmc_int", false,-1); - tracep->declBit(c+904,"jif_int", false,-1); - tracep->declBit(c+905,"dmac_int", false,-1); - tracep->declBit(c+906,"mtc_int", false,-1); - tracep->declBit(c+907,"moc_int", false,-1); - tracep->declBit(c+908,"mpc_int", false,-1); - tracep->declBit(c+909,"mic_int", false,-1); - tracep->declBit(c+910,"utc_int", false,-1); - tracep->declBit(c+911,"uoc_int", false,-1); - tracep->declBit(c+912,"upc_int", false,-1); - tracep->declBit(c+913,"uic_int", false,-1); - tracep->declBus(c+914,"actr_data", false,-1, 31,0); - tracep->declBit(c+915,"actr_ack", false,-1); - tracep->declBit(c+5074,"actr_stall", false,-1); - tracep->declBit(c+916,"cpu_clken", false,-1); - tracep->declBit(c+917,"sys_cyc", false,-1); - tracep->declBit(c+918,"sys_stb", false,-1); - tracep->declBit(c+919,"sys_we", false,-1); - tracep->declBus(c+920,"sys_addr", false,-1, 7,0); - tracep->declBus(c+921,"sys_data", false,-1, 31,0); - tracep->declBus(c+922,"cpu_addr", false,-1, 21,0); - tracep->declBus(c+923,"sys_idata", false,-1, 31,0); - tracep->declBit(c+924,"sys_ack", false,-1); - tracep->declBit(c+5074,"sys_stall", false,-1); - tracep->declBit(c+915,"sel_counter", false,-1); - tracep->declBit(c+925,"sel_timer", false,-1); - tracep->declBit(c+926,"sel_pic", false,-1); - tracep->declBit(c+927,"sel_apic", false,-1); - tracep->declBit(c+928,"sel_watchdog", false,-1); - tracep->declBit(c+929,"sel_bus_watchdog", false,-1); - tracep->declBit(c+930,"sel_dmac", false,-1); - tracep->declBit(c+931,"sel_mmus", false,-1); - tracep->declBit(c+932,"dbg_cyc", false,-1); - tracep->declBit(c+933,"dbg_stb", false,-1); - tracep->declBit(c+934,"dbg_we", false,-1); - tracep->declBus(c+935,"dbg_addr", false,-1, 6,0); - tracep->declBus(c+936,"dbg_idata", false,-1, 31,0); - tracep->declBit(c+937,"dbg_ack", false,-1); - tracep->declBit(c+938,"dbg_stall", false,-1); - tracep->declBus(c+939,"dbg_odata", false,-1, 31,0); - tracep->declBus(c+940,"dbg_sel", false,-1, 3,0); - tracep->declBit(c+941,"no_dbg_err", false,-1); - tracep->declBit(c+942,"cpu_break", false,-1); - tracep->declBit(c+943,"dbg_cmd_write", false,-1); - tracep->declBit(c+944,"dbg_cpu_write", false,-1); - tracep->declBit(c+945,"dbg_cpu_read", false,-1); - tracep->declBus(c+936,"dbg_cmd_data", false,-1, 31,0); - tracep->declBus(c+940,"dbg_cmd_strb", false,-1, 3,0); - tracep->declBit(c+946,"reset_hold", false,-1); - tracep->declBit(c+947,"halt_on_fault", false,-1); - tracep->declBit(c+947,"dbg_catch", false,-1); - tracep->declBit(c+948,"reset_request", false,-1); - tracep->declBit(c+949,"release_request", false,-1); - tracep->declBit(c+950,"halt_request", false,-1); - tracep->declBit(c+951,"step_request", false,-1); - tracep->declBit(c+952,"clear_cache_request", false,-1); - tracep->declBit(c+953,"cmd_reset", false,-1); - tracep->declBit(c+954,"cmd_halt", false,-1); - tracep->declBit(c+955,"cmd_step", false,-1); - tracep->declBit(c+956,"cmd_clear_cache", false,-1); - tracep->declBit(c+957,"cmd_write", false,-1); - tracep->declBit(c+958,"cmd_read", false,-1); - tracep->declBus(c+959,"cmd_waddr", false,-1, 4,0); - tracep->declBus(c+960,"cmd_wdata", false,-1, 31,0); - tracep->declBus(c+961,"cpu_dbg_cc", false,-1, 2,0); - tracep->declBit(c+953,"cpu_reset", false,-1); - tracep->declBit(c+954,"cpu_halt", false,-1); - tracep->declBit(c+962,"cpu_has_halted", false,-1); - tracep->declBit(c+963,"cpu_dbg_stall", false,-1); - tracep->declBus(c+964,"cpu_status", false,-1, 31,0); - tracep->declBit(c+965,"cpu_gie", false,-1); - tracep->declBit(c+5074,"wdt_stall", false,-1); - tracep->declBit(c+966,"wdt_ack", false,-1); - tracep->declBit(c+967,"wdt_reset", false,-1); - tracep->declBus(c+968,"wdt_data", false,-1, 31,0); - tracep->declBit(c+969,"wdbus_ack", false,-1); - tracep->declBus(c+970,"r_wdbus_data", false,-1, 21,0); - tracep->declBus(c+971,"pic_data", false,-1, 31,0); - tracep->declBus(c+972,"wdbus_data", false,-1, 31,0); - tracep->declBit(c+973,"reset_wdbus_timer", false,-1); - tracep->declBit(c+974,"wdbus_int", false,-1); - tracep->declBit(c+48,"cpu_op_stall", false,-1); - tracep->declBit(c+975,"cpu_pf_stall", false,-1); - tracep->declBit(c+976,"cpu_i_count", false,-1); - tracep->declBit(c+977,"dmac_stb", false,-1); - tracep->declBit(c+978,"dc_err", false,-1); - tracep->declBus(c+979,"dmac_data", false,-1, 31,0); - tracep->declBit(c+5074,"dmac_stall", false,-1); - tracep->declBit(c+980,"dmac_ack", false,-1); - tracep->declBit(c+981,"dc_cyc", false,-1); - tracep->declBit(c+982,"dc_stb", false,-1); - tracep->declBit(c+983,"dc_we", false,-1); - tracep->declBit(c+984,"dc_stall", false,-1); - tracep->declBit(c+985,"dc_ack", false,-1); - tracep->declBus(c+986,"dc_addr", false,-1, 21,0); - tracep->declArray(c+987,"dc_data", false,-1, 511,0); - tracep->declQuad(c+1003,"dc_sel", false,-1, 63,0); - tracep->declBit(c+1005,"cpu_gbl_cyc", false,-1); - tracep->declBus(c+1006,"dmac_int_vec", false,-1, 31,0); - tracep->declBit(c+1007,"ctri_sel", false,-1); - tracep->declBit(c+5074,"ctri_stall", false,-1); - tracep->declBit(c+1007,"ctri_ack", false,-1); - tracep->declBus(c+1008,"ctri_data", false,-1, 31,0); - tracep->declBit(c+5074,"tma_stall", false,-1); - tracep->declBit(c+1009,"tma_ack", false,-1); - tracep->declBit(c+5074,"tmb_stall", false,-1); - tracep->declBit(c+1010,"tmb_ack", false,-1); - tracep->declBit(c+5074,"tmc_stall", false,-1); - tracep->declBit(c+1011,"tmc_ack", false,-1); - tracep->declBit(c+5074,"jif_stall", false,-1); - tracep->declBit(c+1012,"jif_ack", false,-1); - tracep->declBus(c+1013,"tma_data", false,-1, 31,0); - tracep->declBus(c+1014,"tmb_data", false,-1, 31,0); - tracep->declBus(c+1015,"tmc_data", false,-1, 31,0); - tracep->declBus(c+1016,"jif_data", false,-1, 31,0); - tracep->declBit(c+5074,"pic_stall", false,-1); - tracep->declBit(c+1017,"pic_ack", false,-1); - tracep->declBit(c+1018,"cpu_gbl_stb", false,-1); - tracep->declBit(c+1019,"cpu_lcl_cyc", false,-1); - tracep->declBit(c+1020,"cpu_lcl_stb", false,-1); - tracep->declBit(c+1021,"cpu_we", false,-1); - tracep->declArray(c+1022,"cpu_data", false,-1, 511,0); - tracep->declQuad(c+1038,"cpu_sel", false,-1, 63,0); - tracep->declQuad(c+1038,"mmu_sel", false,-1, 63,0); - tracep->declArray(c+1040,"cpu_idata", false,-1, 511,0); - tracep->declBit(c+1056,"cpu_stall", false,-1); - tracep->declBit(c+1057,"pic_interrupt", false,-1); - tracep->declBit(c+1058,"cpu_ack", false,-1); - tracep->declBit(c+1059,"cpu_err", false,-1); - tracep->declBus(c+1060,"cpu_dbg_data", false,-1, 31,0); - tracep->declBit(c+283,"ext_stall", false,-1); - tracep->declBit(c+284,"ext_ack", false,-1); - tracep->declBit(c+1005,"mmu_cyc", false,-1); - tracep->declBit(c+1018,"mmu_stb", false,-1); - tracep->declBit(c+1021,"mmu_we", false,-1); - tracep->declBit(c+1061,"mmu_stall", false,-1); - tracep->declBit(c+1062,"mmu_ack", false,-1); - tracep->declBit(c+1063,"mmu_err", false,-1); - tracep->declBit(c+5074,"mmus_stall", false,-1); - tracep->declBit(c+1064,"mmus_ack", false,-1); - tracep->declBus(c+922,"mmu_addr", false,-1, 21,0); - tracep->declArray(c+1022,"mmu_data", false,-1, 511,0); - tracep->declArray(c+286,"mmu_idata", false,-1, 511,0); - tracep->declBus(c+5076,"mmus_data", false,-1, 31,0); - tracep->declBit(c+5074,"cpu_miss", false,-1); - tracep->declBit(c+1061,"mmu_cpu_stall", false,-1); - tracep->declBit(c+1062,"mmu_cpu_ack", false,-1); - tracep->declArray(c+286,"mmu_cpu_idata", false,-1, 511,0); - tracep->declBit(c+5074,"pf_return_stb", false,-1); - tracep->declBit(c+5074,"pf_return_we", false,-1); - tracep->declBit(c+5074,"pf_return_cachable", false,-1); - tracep->declBus(c+5233,"pf_return_v", false,-1, 19,0); - tracep->declBus(c+5233,"pf_return_p", false,-1, 19,0); - tracep->declBit(c+261,"ext_cyc", false,-1); - tracep->declBit(c+262,"ext_stb", false,-1); - tracep->declBit(c+263,"ext_we", false,-1); - tracep->declBit(c+1065,"ext_err", false,-1); - tracep->declBus(c+264,"ext_addr", false,-1, 21,0); - tracep->declArray(c+265,"ext_odata", false,-1, 511,0); - tracep->declQuad(c+281,"ext_sel", false,-1, 63,0); - tracep->declArray(c+286,"ext_idata", false,-1, 511,0); - tracep->declBus(c+1066,"tmr_data", false,-1, 31,0); - tracep->declBus(c+1067,"w_ack_idx", false,-1, 2,0); - tracep->declBus(c+1068,"ack_idx", false,-1, 2,0); - tracep->declBit(c+1069,"last_sys_stb", false,-1); - tracep->declBit(c+1070,"cmd_read_ack", false,-1); - tracep->declBit(c+1064,"r_mmus_ack", false,-1); - tracep->declBit(c+1071,"dbg_pre_ack", false,-1); - tracep->declBus(c+1072,"dbg_pre_addr", false,-1, 1,0); - tracep->declBus(c+1073,"dbg_cpu_status", false,-1, 31,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("ACCOUNTING_COUNTERS "); - tracep->declBit(c+5074,"mtc_stall", false,-1); - tracep->declBit(c+1074,"mtc_ack", false,-1); - tracep->declBit(c+5074,"moc_stall", false,-1); - tracep->declBit(c+1075,"moc_ack", false,-1); - tracep->declBit(c+5074,"mpc_stall", false,-1); - tracep->declBit(c+1076,"mpc_ack", false,-1); - tracep->declBit(c+5074,"mic_stall", false,-1); - tracep->declBit(c+1077,"mic_ack", false,-1); - tracep->declBit(c+5074,"utc_stall", false,-1); - tracep->declBit(c+1078,"utc_ack", false,-1); - tracep->declBit(c+5074,"uoc_stall", false,-1); - tracep->declBit(c+1079,"uoc_ack", false,-1); - tracep->declBit(c+5074,"upc_stall", false,-1); - tracep->declBit(c+1080,"upc_ack", false,-1); - tracep->declBit(c+5074,"uic_stall", false,-1); - tracep->declBit(c+1081,"uic_ack", false,-1); - tracep->declBus(c+1082,"mtc_data", false,-1, 31,0); - tracep->declBus(c+1083,"moc_data", false,-1, 31,0); - tracep->declBus(c+1084,"mpc_data", false,-1, 31,0); - tracep->declBus(c+1085,"mic_data", false,-1, 31,0); - tracep->declBus(c+1086,"utc_data", false,-1, 31,0); - tracep->declBus(c+1087,"uoc_data", false,-1, 31,0); - tracep->declBus(c+1088,"upc_data", false,-1, 31,0); - tracep->declBus(c+1089,"uic_data", false,-1, 31,0); - tracep->declBus(c+914,"r_actr_data", false,-1, 31,0); - tracep->pushNamePrefix("mins_ctr "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+976,"i_event", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1090,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1077,"o_wb_ack", false,-1); - tracep->declBus(c+1085,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+909,"o_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("mmstall_ctr "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+48,"i_event", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1091,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1075,"o_wb_ack", false,-1); - tracep->declBus(c+1083,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+907,"o_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("mpstall_ctr "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+975,"i_event", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1092,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1076,"o_wb_ack", false,-1); - tracep->declBus(c+1084,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+908,"o_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("mtask_ctr "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+1093,"i_event", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1094,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1074,"o_wb_ack", false,-1); - tracep->declBus(c+1082,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+906,"o_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("uins_ctr "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+1095,"i_event", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1096,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1081,"o_wb_ack", false,-1); - tracep->declBus(c+1089,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+913,"o_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("umstall_ctr "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+49,"i_event", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1097,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1079,"o_wb_ack", false,-1); - tracep->declBus(c+1087,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+911,"o_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("upstall_ctr "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+1098,"i_event", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1099,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1080,"o_wb_ack", false,-1); - tracep->declBus(c+1088,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+912,"o_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("utask_ctr "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_reset", false,-1); - tracep->declBit(c+1100,"i_event", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1101,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1078,"o_wb_ack", false,-1); - tracep->declBus(c+1086,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+910,"o_int", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("DELAY_THE_DEBUG_BUS "); - tracep->declBit(c+5074,"dbg_err", false,-1); - tracep->pushNamePrefix("wbdelay "); - tracep->declBus(c+5072,"AW", false,-1, 31,0); - tracep->declBus(c+5114,"DW", false,-1, 31,0); - tracep->declBus(c+5070,"DELAY_STALL", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5015,"i_reset", false,-1); - tracep->declBit(c+43,"i_wb_cyc", false,-1); - tracep->declBit(c+44,"i_wb_stb", false,-1); - tracep->declBit(c+45,"i_wb_we", false,-1); - tracep->declBus(c+46,"i_wb_addr", false,-1, 6,0); - tracep->declBus(c+47,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+186,"o_wb_stall", false,-1); - tracep->declBit(c+187,"o_wb_ack", false,-1); - tracep->declBus(c+435,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+941,"o_wb_err", false,-1); - tracep->declBit(c+932,"o_dly_cyc", false,-1); - tracep->declBit(c+933,"o_dly_stb", false,-1); - tracep->declBit(c+934,"o_dly_we", false,-1); - tracep->declBus(c+935,"o_dly_addr", false,-1, 6,0); - tracep->declBus(c+936,"o_dly_data", false,-1, 31,0); - tracep->declBus(c+940,"o_dly_sel", false,-1, 3,0); - tracep->declBit(c+938,"i_dly_stall", false,-1); - tracep->declBit(c+937,"i_dly_ack", false,-1); - tracep->declBus(c+939,"i_dly_data", false,-1, 31,0); - tracep->declBit(c+5074,"i_dly_err", false,-1); - tracep->pushNamePrefix("SKIDBUFFER "); - tracep->declBit(c+186,"r_stb", false,-1); - tracep->declBit(c+1102,"r_we", false,-1); - tracep->declBus(c+1103,"r_addr", false,-1, 6,0); - tracep->declBus(c+1104,"r_data", false,-1, 31,0); - tracep->declBus(c+1105,"r_sel", false,-1, 3,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DMA "); - tracep->pushNamePrefix("dma_controller "); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5061,"LGMEMLEN", false,-1, 31,0); - tracep->declBus(c+5199,"LGDMALENGTH", false,-1, 31,0); - tracep->declBus(c+5114,"SLV_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_REGISTER_RAM", false,-1, 0,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+917,"i_swb_cyc", false,-1); - tracep->declBit(c+977,"i_swb_stb", false,-1); - tracep->declBit(c+919,"i_swb_we", false,-1); - tracep->declBus(c+1106,"i_swb_addr", false,-1, 1,0); - tracep->declBus(c+921,"i_swb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_swb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_swb_stall", false,-1); - tracep->declBit(c+980,"o_swb_ack", false,-1); - tracep->declBus(c+979,"o_swb_data", false,-1, 31,0); - tracep->declBit(c+981,"o_mwb_cyc", false,-1); - tracep->declBit(c+982,"o_mwb_stb", false,-1); - tracep->declBit(c+983,"o_mwb_we", false,-1); - tracep->declBus(c+986,"o_mwb_addr", false,-1, 21,0); - tracep->declArray(c+987,"o_mwb_data", false,-1, 511,0); - tracep->declQuad(c+1003,"o_mwb_sel", false,-1, 63,0); - tracep->declBit(c+984,"i_mwb_stall", false,-1); - tracep->declBit(c+985,"i_mwb_ack", false,-1); - tracep->declArray(c+286,"i_mwb_data", false,-1, 511,0); - tracep->declBit(c+978,"i_mwb_err", false,-1); - tracep->declBus(c+1006,"i_dev_ints", false,-1, 31,0); - tracep->declBit(c+905,"o_interrupt", false,-1); - tracep->declBus(c+5234,"FIFO_WIDTH", false,-1, 31,0); - tracep->declBus(c+5065,"LGFIFO", false,-1, 31,0); - tracep->declBit(c+1107,"dma_request", false,-1); - tracep->declBit(c+1108,"dma_abort", false,-1); - tracep->declBit(c+1109,"dma_busy", false,-1); - tracep->declBit(c+1110,"dma_err", false,-1); - tracep->declBus(c+1111,"dma_src", false,-1, 27,0); - tracep->declBus(c+1112,"dma_dst", false,-1, 27,0); - tracep->declBus(c+1113,"read_addr", false,-1, 27,0); - tracep->declBus(c+1114,"write_addr", false,-1, 27,0); - tracep->declBus(c+1115,"dma_length", false,-1, 27,0); - tracep->declBus(c+1116,"remaining_len", false,-1, 27,0); - tracep->declBus(c+1117,"dma_transferlen", false,-1, 10,0); - tracep->declBit(c+1118,"dma_trigger", false,-1); - tracep->declBit(c+1119,"mm2s_request", false,-1); - tracep->declBit(c+1120,"s2mm_request", false,-1); - tracep->declBit(c+1121,"mm2s_busy", false,-1); - tracep->declBit(c+1122,"s2mm_busy", false,-1); - tracep->declBit(c+1123,"mm2s_err", false,-1); - tracep->declBit(c+1124,"s2mm_err", false,-1); - tracep->declBit(c+1125,"mm2s_inc", false,-1); - tracep->declBit(c+1126,"s2mm_inc", false,-1); - tracep->declBus(c+1127,"mm2s_size", false,-1, 1,0); - tracep->declBus(c+1128,"s2mm_size", false,-1, 1,0); - tracep->declBus(c+1129,"mm2s_addr", false,-1, 27,0); - tracep->declBus(c+1130,"s2mm_addr", false,-1, 27,0); - tracep->declBus(c+1131,"mm2s_transferlen", false,-1, 10,0); - tracep->declBus(c+1131,"s2mm_transferlen", false,-1, 10,0); - tracep->declBit(c+1132,"mm2s_rd_cyc", false,-1); - tracep->declBit(c+1133,"mm2s_rd_stb", false,-1); - tracep->declBit(c+5074,"mm2s_rd_we", false,-1); - tracep->declBit(c+1134,"mm2s_rd_stall", false,-1); - tracep->declBit(c+1135,"mm2s_rd_ack", false,-1); - tracep->declBit(c+1136,"mm2s_rd_err", false,-1); - tracep->declBus(c+1137,"mm2s_rd_addr", false,-1, 21,0); - tracep->declArray(c+5078,"mm2s_rd_data", false,-1, 511,0); - tracep->declQuad(c+1138,"mm2s_rd_sel", false,-1, 63,0); - tracep->declBit(c+1140,"mm2s_valid", false,-1); - tracep->declBit(c+1141,"mm2s_ready", false,-1); - tracep->declBit(c+1142,"mm2s_last", false,-1); - tracep->declArray(c+1143,"mm2s_data", false,-1, 511,0); - tracep->declBus(c+1159,"mm2s_bytes", false,-1, 6,0); - tracep->declBit(c+1160,"rx_valid", false,-1); - tracep->declBit(c+1161,"rx_ready", false,-1); - tracep->declBit(c+1162,"rx_last", false,-1); - tracep->declArray(c+1163,"rx_data", false,-1, 511,0); - tracep->declBus(c+1179,"rx_bytes", false,-1, 6,0); - tracep->declBit(c+1180,"tx_valid", false,-1); - tracep->declBit(c+1181,"tx_ready", false,-1); - tracep->declBit(c+1182,"tx_last", false,-1); - tracep->declArray(c+1183,"tx_data", false,-1, 511,0); - tracep->declBus(c+1199,"tx_bytes", false,-1, 6,0); - tracep->declBit(c+1200,"sfifo_full", false,-1); - tracep->declBit(c+1201,"sfifo_empty", false,-1); - tracep->declBus(c+1202,"ign_sfifo_fill", false,-1, 4,0); - tracep->declBit(c+1203,"s2mm_valid", false,-1); - tracep->declBit(c+1204,"s2mm_ready", false,-1); - tracep->declBit(c+1205,"s2mm_last", false,-1); - tracep->declArray(c+1206,"s2mm_data", false,-1, 511,0); - tracep->declBus(c+1222,"s2mm_bytes", false,-1, 6,0); - tracep->declBit(c+1223,"s2mm_wr_cyc", false,-1); - tracep->declBit(c+1224,"s2mm_wr_stb", false,-1); - tracep->declBit(c+5077,"s2mm_wr_we", false,-1); - tracep->declBit(c+1225,"s2mm_wr_stall", false,-1); - tracep->declBit(c+1226,"s2mm_wr_ack", false,-1); - tracep->declBit(c+1227,"s2mm_wr_err", false,-1); - tracep->declBus(c+1228,"s2mm_wr_addr", false,-1, 21,0); - tracep->declArray(c+987,"s2mm_wr_data", false,-1, 511,0); - tracep->declQuad(c+1229,"s2mm_wr_sel", false,-1, 63,0); - tracep->declBit(c+981,"wb_cyc", false,-1); - tracep->declBit(c+982,"wb_stb", false,-1); - tracep->declBit(c+983,"wb_we", false,-1); - tracep->declBit(c+984,"wb_stall", false,-1); - tracep->declBit(c+985,"wb_ack", false,-1); - tracep->declBit(c+978,"wb_err", false,-1); - tracep->declBus(c+986,"wb_addr", false,-1, 21,0); - tracep->declArray(c+987,"wb_data", false,-1, 511,0); - tracep->declArray(c+286,"wb_idata", false,-1, 511,0); - tracep->declQuad(c+1003,"wb_sel", false,-1, 63,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("u_arbiter "); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declArray(c+5235,"SCHEME", false,-1, 87,0); - tracep->declBus(c+5113,"OPT_ZERO_ON_IDLE", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1132,"i_a_cyc", false,-1); - tracep->declBit(c+1133,"i_a_stb", false,-1); - tracep->declBit(c+5074,"i_a_we", false,-1); - tracep->declBus(c+1137,"i_a_adr", false,-1, 21,0); - tracep->declArray(c+987,"i_a_dat", false,-1, 511,0); - tracep->declQuad(c+1138,"i_a_sel", false,-1, 63,0); - tracep->declBit(c+1134,"o_a_stall", false,-1); - tracep->declBit(c+1135,"o_a_ack", false,-1); - tracep->declBit(c+1136,"o_a_err", false,-1); - tracep->declBit(c+1223,"i_b_cyc", false,-1); - tracep->declBit(c+1224,"i_b_stb", false,-1); - tracep->declBit(c+5077,"i_b_we", false,-1); - tracep->declBus(c+1228,"i_b_adr", false,-1, 21,0); - tracep->declArray(c+987,"i_b_dat", false,-1, 511,0); - tracep->declQuad(c+1229,"i_b_sel", false,-1, 63,0); - tracep->declBit(c+1225,"o_b_stall", false,-1); - tracep->declBit(c+1226,"o_b_ack", false,-1); - tracep->declBit(c+1227,"o_b_err", false,-1); - tracep->declBit(c+981,"o_cyc", false,-1); - tracep->declBit(c+982,"o_stb", false,-1); - tracep->declBit(c+983,"o_we", false,-1); - tracep->declBus(c+986,"o_adr", false,-1, 21,0); - tracep->declArray(c+987,"o_dat", false,-1, 511,0); - tracep->declQuad(c+1003,"o_sel", false,-1, 63,0); - tracep->declBit(c+984,"i_stall", false,-1); - tracep->declBit(c+985,"i_ack", false,-1); - tracep->declBit(c+978,"i_err", false,-1); - tracep->declBit(c+1231,"r_a_owner", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("ALT "); - tracep->declBit(c+1232,"last_owner", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_controller "); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5061,"LGMEMLEN", false,-1, 31,0); - tracep->declBus(c+5114,"SLV_WIDTH", false,-1, 31,0); - tracep->declBus(c+5199,"LGDMALENGTH", false,-1, 31,0); - tracep->declBus(c+5238,"ABORT_KEY", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5199,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+917,"i_cyc", false,-1); - tracep->declBit(c+977,"i_stb", false,-1); - tracep->declBit(c+919,"i_we", false,-1); - tracep->declBus(c+1106,"i_addr", false,-1, 1,0); - tracep->declBus(c+921,"i_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_stall", false,-1); - tracep->declBit(c+980,"o_ack", false,-1); - tracep->declBus(c+979,"o_data", false,-1, 31,0); - tracep->declBit(c+1107,"o_dma_request", false,-1); - tracep->declBit(c+1108,"o_dma_abort", false,-1); - tracep->declBit(c+1109,"i_dma_busy", false,-1); - tracep->declBit(c+1110,"i_dma_err", false,-1); - tracep->declBus(c+1111,"o_src_addr", false,-1, 27,0); - tracep->declBus(c+1112,"o_dst_addr", false,-1, 27,0); - tracep->declBus(c+1115,"o_length", false,-1, 27,0); - tracep->declBus(c+1117,"o_transferlen", false,-1, 10,0); - tracep->declBit(c+1125,"o_mm2s_inc", false,-1); - tracep->declBit(c+1126,"o_s2mm_inc", false,-1); - tracep->declBus(c+1127,"o_mm2s_size", false,-1, 1,0); - tracep->declBus(c+1128,"o_s2mm_size", false,-1, 1,0); - tracep->declBit(c+1118,"o_trigger", false,-1); - tracep->declBus(c+1113,"i_current_src", false,-1, 27,0); - tracep->declBus(c+1114,"i_current_dst", false,-1, 27,0); - tracep->declBus(c+1116,"i_remaining_len", false,-1, 27,0); - tracep->declBus(c+1006,"i_dma_int", false,-1, 31,0); - tracep->declBit(c+905,"o_interrupt", false,-1); - tracep->declBit(c+1233,"int_trigger", false,-1); - tracep->declBit(c+1234,"r_err", false,-1); - tracep->declBit(c+1235,"r_zero_len", false,-1); - tracep->declBit(c+1236,"r_busy", false,-1); - tracep->declBus(c+1237,"int_sel", false,-1, 4,0); - tracep->declBus(c+1238,"next_src", false,-1, 31,0); - tracep->declBus(c+1239,"next_dst", false,-1, 31,0); - tracep->declBus(c+1240,"next_len", false,-1, 31,0); - tracep->declBus(c+1241,"next_tlen", false,-1, 31,0); - tracep->declBus(c+1242,"w_control_reg", false,-1, 31,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("UNUSED_LEN "); - tracep->declBit(c+5074,"unused_len", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("UNUSED_WIDE_ADDR "); - tracep->declBit(c+5074,"unused_addr", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_dma_fsm "); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5199,"LGDMALENGTH", false,-1, 31,0); - tracep->declBus(c+5061,"LGSUBLENGTH", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1108,"i_soft_reset", false,-1); - tracep->declBit(c+1107,"i_dma_request", false,-1); - tracep->declBit(c+1109,"o_dma_busy", false,-1); - tracep->declBit(c+1110,"o_dma_err", false,-1); - tracep->declBus(c+1111,"i_src_addr", false,-1, 27,0); - tracep->declBus(c+1112,"i_dst_addr", false,-1, 27,0); - tracep->declBus(c+1115,"i_length", false,-1, 27,0); - tracep->declBus(c+1117,"i_transferlen", false,-1, 10,0); - tracep->declBus(c+1116,"o_remaining_len", false,-1, 27,0); - tracep->declBit(c+1118,"i_trigger", false,-1); - tracep->declBit(c+1119,"o_mm2s_request", false,-1); - tracep->declBit(c+1121,"i_mm2s_busy", false,-1); - tracep->declBit(c+1123,"i_mm2s_err", false,-1); - tracep->declBit(c+1125,"i_mm2s_inc", false,-1); - tracep->declBus(c+1129,"o_mm2s_addr", false,-1, 27,0); - tracep->declBus(c+1131,"o_mm2s_transferlen", false,-1, 10,0); - tracep->declBit(c+1120,"o_s2mm_request", false,-1); - tracep->declBit(c+1122,"i_s2mm_busy", false,-1); - tracep->declBit(c+1124,"i_s2mm_err", false,-1); - tracep->declBit(c+1126,"i_s2mm_inc", false,-1); - tracep->declBus(c+1130,"o_s2mm_addr", false,-1, 27,0); - tracep->declBus(c+1131,"o_s2mm_transferlen", false,-1, 10,0); - tracep->declBus(c+5116,"S_IDLE", false,-1, 1,0); - tracep->declBus(c+5117,"S_WAIT", false,-1, 1,0); - tracep->declBus(c+5118,"S_READ", false,-1, 1,0); - tracep->declBus(c+5119,"S_WRITE", false,-1, 1,0); - tracep->declBus(c+1116,"r_length", false,-1, 27,0); - tracep->declBus(c+1131,"r_transferlen", false,-1, 10,0); - tracep->declBus(c+1243,"fsm_state", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_mm2s "); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5061,"LGLENGTH", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+1244,"i_reset", false,-1); - tracep->declBit(c+1119,"i_request", false,-1); - tracep->declBit(c+1121,"o_busy", false,-1); - tracep->declBit(c+1123,"o_err", false,-1); - tracep->declBit(c+1125,"i_inc", false,-1); - tracep->declBus(c+1127,"i_size", false,-1, 1,0); - tracep->declBus(c+1131,"i_transferlen", false,-1, 10,0); - tracep->declBus(c+1129,"i_addr", false,-1, 27,0); - tracep->declBit(c+1132,"o_rd_cyc", false,-1); - tracep->declBit(c+1133,"o_rd_stb", false,-1); - tracep->declBit(c+5074,"o_rd_we", false,-1); - tracep->declBus(c+1137,"o_rd_addr", false,-1, 21,0); - tracep->declArray(c+5078,"o_rd_data", false,-1, 511,0); - tracep->declQuad(c+1138,"o_rd_sel", false,-1, 63,0); - tracep->declBit(c+1134,"i_rd_stall", false,-1); - tracep->declBit(c+1135,"i_rd_ack", false,-1); - tracep->declArray(c+286,"i_rd_data", false,-1, 511,0); - tracep->declBit(c+1136,"i_rd_err", false,-1); - tracep->declBit(c+1140,"M_VALID", false,-1); - tracep->declBit(c+1141,"M_READY", false,-1); - tracep->declArray(c+1143,"M_DATA", false,-1, 511,0); - tracep->declBus(c+1159,"M_BYTES", false,-1, 6,0); - tracep->declBit(c+1142,"M_LAST", false,-1); - tracep->declBus(c+5119,"SZ_BYTE", false,-1, 1,0); - tracep->declBus(c+5118,"SZ_16B", false,-1, 1,0); - tracep->declBus(c+5117,"SZ_32B", false,-1, 1,0); - tracep->declBus(c+5116,"SZ_BUS", false,-1, 1,0); - tracep->declBus(c+5153,"WBLSB", false,-1, 31,0); - tracep->declBus(c+1245,"nxtstb_size", false,-1, 6,0); - tracep->declBus(c+1246,"rdstb_size", false,-1, 6,0); - tracep->declBus(c+1247,"rdack_size", false,-1, 6,0); - tracep->declBus(c+1248,"first_size", false,-1, 6,0); - tracep->declBus(c+1249,"next_addr", false,-1, 27,0); - tracep->declBus(c+1250,"last_request_addr", false,-1, 27,0); - tracep->declBus(c+1251,"subaddr", false,-1, 5,0); - tracep->declBus(c+1252,"rdack_subaddr", false,-1, 5,0); - tracep->declQuad(c+1253,"nxtstb_sel", false,-1, 63,0); - tracep->declQuad(c+1255,"first_sel", false,-1, 63,0); - tracep->declQuad(c+1257,"base_sel", false,-1, 63,0); - tracep->declQuad(c+1259,"ibase_sel", false,-1, 63,0); - tracep->declBus(c+1261,"wb_outstanding", false,-1, 10,0); - tracep->declBus(c+1262,"fill", false,-1, 7,0); - tracep->declBus(c+1263,"next_fill", false,-1, 7,0); - tracep->declBit(c+1140,"m_valid", false,-1); - tracep->declBit(c+1142,"m_last", false,-1); - tracep->declArray(c+1143,"sreg", false,-1, 511,0); - tracep->declBus(c+1159,"m_bytes", false,-1, 6,0); - tracep->declBus(c+1264,"rdstb_len", false,-1, 10,0); - tracep->declBus(c+1265,"rdack_len", false,-1, 10,0); - tracep->declBus(c+1266,"pre_shift", false,-1, 5,0); - tracep->declArray(c+1267,"pre_shifted_data", false,-1, 511,0); - tracep->declBit(c+1283,"r_inc", false,-1); - tracep->declBus(c+1284,"r_size", false,-1, 1,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_rxgears "); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1108,"i_soft_reset", false,-1); - tracep->declBit(c+1140,"S_VALID", false,-1); - tracep->declBit(c+1141,"S_READY", false,-1); - tracep->declArray(c+1143,"S_DATA", false,-1, 511,0); - tracep->declBus(c+1159,"S_BYTES", false,-1, 6,0); - tracep->declBit(c+1142,"S_LAST", false,-1); - tracep->declBit(c+1160,"M_VALID", false,-1); - tracep->declBit(c+1161,"M_READY", false,-1); - tracep->declArray(c+1163,"M_DATA", false,-1, 511,0); - tracep->declBus(c+1179,"M_BYTES", false,-1, 6,0); - tracep->declBit(c+1162,"M_LAST", false,-1); - tracep->declBus(c+5153,"WBLSB", false,-1, 31,0); - tracep->declArray(c+1285,"sreg", false,-1, 1023,0); - tracep->declBus(c+1317,"next_fill", false,-1, 7,0); - tracep->declBus(c+1318,"fill", false,-1, 7,0); - tracep->declBit(c+1160,"m_valid", false,-1); - tracep->declBit(c+1162,"m_last", false,-1); - tracep->declBit(c+1319,"next_last", false,-1); - tracep->declBit(c+1320,"r_last", false,-1); - tracep->declBit(c+1321,"r_full", false,-1); - tracep->declBus(c+1179,"m_bytes", false,-1, 6,0); - tracep->declBus(c+1322,"shift", false,-1, 5,0); - tracep->declArray(c+1323,"s_data", false,-1, 511,0); - tracep->declBus(c+5239,"ik", false,-1, 31,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_s2mm "); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5061,"LGPIPE", false,-1, 31,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+1244,"i_reset", false,-1); - tracep->declBit(c+1120,"i_request", false,-1); - tracep->declBit(c+1122,"o_busy", false,-1); - tracep->declBit(c+1124,"o_err", false,-1); - tracep->declBit(c+1126,"i_inc", false,-1); - tracep->declBus(c+1128,"i_size", false,-1, 1,0); - tracep->declBus(c+1130,"i_addr", false,-1, 27,0); - tracep->declBit(c+1203,"S_VALID", false,-1); - tracep->declBit(c+1204,"S_READY", false,-1); - tracep->declArray(c+1206,"S_DATA", false,-1, 511,0); - tracep->declBus(c+1222,"S_BYTES", false,-1, 6,0); - tracep->declBit(c+1205,"S_LAST", false,-1); - tracep->declBit(c+1223,"o_wr_cyc", false,-1); - tracep->declBit(c+1224,"o_wr_stb", false,-1); - tracep->declBit(c+5077,"o_wr_we", false,-1); - tracep->declBus(c+1228,"o_wr_addr", false,-1, 21,0); - tracep->declArray(c+987,"o_wr_data", false,-1, 511,0); - tracep->declQuad(c+1229,"o_wr_sel", false,-1, 63,0); - tracep->declBit(c+1225,"i_wr_stall", false,-1); - tracep->declBit(c+1226,"i_wr_ack", false,-1); - tracep->declArray(c+286,"i_wr_data", false,-1, 511,0); - tracep->declBit(c+1227,"i_wr_err", false,-1); - tracep->declBus(c+5119,"SZ_BYTE", false,-1, 1,0); - tracep->declBus(c+5118,"SZ_16B", false,-1, 1,0); - tracep->declBus(c+5117,"SZ_32B", false,-1, 1,0); - tracep->declBus(c+5116,"SZ_BUS", false,-1, 1,0); - tracep->declBus(c+5153,"WBLSB", false,-1, 31,0); - tracep->declBus(c+7,"ik", false,-1, 31,0); - tracep->declBit(c+1339,"r_inc", false,-1); - tracep->declBus(c+1340,"r_size", false,-1, 1,0); - tracep->declBus(c+1341,"next_addr", false,-1, 28,0); - tracep->declBus(c+1342,"subaddr", false,-1, 5,0); - tracep->declArray(c+1343,"next_data", false,-1, 1023,0); - tracep->declArray(c+1375,"r_data", false,-1, 511,0); - tracep->declArray(c+1391,"next_sel", false,-1, 127,0); - tracep->declArray(c+1395,"pre_sel", false,-1, 127,0); - tracep->declQuad(c+1399,"r_sel", false,-1, 63,0); - tracep->declBit(c+1401,"r_last", false,-1); - tracep->declBus(c+1402,"wb_outstanding", false,-1, 9,0); - tracep->declBit(c+1403,"wb_pipeline_full", false,-1); - tracep->declBit(c+1404,"addr_overflow", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_sfifo "); - tracep->declBus(c+5234,"BW", false,-1, 31,0); - tracep->declBus(c+5065,"LGFLEN", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_ASYNC_READ", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_WRITE_ON_FULL", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_READ_ON_EMPTY", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+1244,"i_reset", false,-1); - tracep->declBit(c+1160,"i_wr", false,-1); - tracep->declArray(c+1405,"i_data", false,-1, 519,0); - tracep->declBit(c+1200,"o_full", false,-1); - tracep->declBus(c+1202,"o_fill", false,-1, 4,0); - tracep->declBit(c+1181,"i_rd", false,-1); - tracep->declArray(c+1422,"o_data", false,-1, 519,0); - tracep->declBit(c+1201,"o_empty", false,-1); - tracep->declBus(c+5069,"FLEN", false,-1, 31,0); - tracep->declBit(c+1200,"r_full", false,-1); - tracep->declBit(c+1201,"r_empty", false,-1); - for (int i = 0; i < 16; ++i) { - tracep->declArray(c+1439+i*17,"mem", true,(i+0), 519,0); - } - tracep->declBus(c+1711,"wr_addr", false,-1, 4,0); - tracep->declBus(c+1712,"rd_addr", false,-1, 4,0); - tracep->declBit(c+1713,"w_wr", false,-1); - tracep->declBit(c+1714,"w_rd", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_txgears "); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1108,"i_soft_reset", false,-1); - tracep->declBus(c+1128,"i_size", false,-1, 1,0); - tracep->declBit(c+1180,"S_VALID", false,-1); - tracep->declBit(c+1181,"S_READY", false,-1); - tracep->declArray(c+1183,"S_DATA", false,-1, 511,0); - tracep->declBus(c+1199,"S_BYTES", false,-1, 6,0); - tracep->declBit(c+1182,"S_LAST", false,-1); - tracep->declBit(c+1203,"M_VALID", false,-1); - tracep->declBit(c+1204,"M_READY", false,-1); - tracep->declArray(c+1206,"M_DATA", false,-1, 511,0); - tracep->declBus(c+1222,"M_BYTES", false,-1, 6,0); - tracep->declBit(c+1205,"M_LAST", false,-1); - tracep->declBus(c+5153,"WBLSB", false,-1, 31,0); - tracep->declBus(c+5119,"SZ_BYTE", false,-1, 1,0); - tracep->declBus(c+5118,"SZ_16B", false,-1, 1,0); - tracep->declBus(c+5117,"SZ_32B", false,-1, 1,0); - tracep->declBus(c+5116,"SZ_BUS", false,-1, 1,0); - tracep->declBit(c+1203,"m_valid", false,-1); - tracep->declBit(c+1205,"m_last", false,-1); - tracep->declBit(c+1715,"r_last", false,-1); - tracep->declBit(c+1716,"r_next", false,-1); - tracep->declArray(c+1206,"sreg", false,-1, 511,0); - tracep->declBus(c+1222,"m_bytes", false,-1, 6,0); - tracep->declBus(c+1717,"fill", false,-1, 6,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("GEN_DBG_CATCH "); - tracep->declBit(c+947,"r_dbg_catch", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("INITIAL_RESET_HOLD "); - tracep->declBus(c+1718,"reset_counter", false,-1, 4,0); - tracep->declBit(c+946,"r_reset_hold", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("MAIN_PIC "); - tracep->pushNamePrefix("pic "); - tracep->declBus(c+5240,"IUSED", false,-1, 31,0); - tracep->declBus(c+5114,"DW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1017,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1017,"o_wb_ack", false,-1); - tracep->declBus(c+971,"o_wb_data", false,-1, 31,0); - tracep->declBus(c+898,"i_brd_ints", false,-1, 14,0); - tracep->declBit(c+1057,"o_interrupt", false,-1); - tracep->declBus(c+1719,"r_int_state", false,-1, 14,0); - tracep->declBus(c+1720,"r_int_enable", false,-1, 14,0); - tracep->declBit(c+1721,"r_mie", false,-1); - tracep->declBit(c+1722,"w_any", false,-1); - tracep->declBit(c+1723,"wb_write", false,-1); - tracep->declBit(c+1724,"enable_ints", false,-1); - tracep->declBit(c+1725,"disable_ints", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("PIC_WITH_ACCOUNTING "); - tracep->pushNamePrefix("ALT_PIC "); - tracep->pushNamePrefix("ctri "); - tracep->declBus(c+5240,"IUSED", false,-1, 31,0); - tracep->declBus(c+5114,"DW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+1007,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1007,"o_wb_ack", false,-1); - tracep->declBus(c+1008,"o_wb_data", false,-1, 31,0); - tracep->declBus(c+899,"i_brd_ints", false,-1, 14,0); - tracep->declBit(c+900,"o_interrupt", false,-1); - tracep->declBus(c+1726,"r_int_state", false,-1, 14,0); - tracep->declBus(c+1727,"r_int_enable", false,-1, 14,0); - tracep->declBit(c+1728,"r_mie", false,-1); - tracep->declBit(c+1729,"w_any", false,-1); - tracep->declBit(c+1730,"wb_write", false,-1); - tracep->declBit(c+1731,"enable_ints", false,-1); - tracep->declBit(c+1732,"disable_ints", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("dmacvcpu "); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_ZERO_ON_IDLE", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+1005,"i_a_cyc", false,-1); - tracep->declBit(c+1018,"i_a_stb", false,-1); - tracep->declBit(c+1021,"i_a_we", false,-1); - tracep->declBus(c+922,"i_a_adr", false,-1, 21,0); - tracep->declArray(c+1022,"i_a_dat", false,-1, 511,0); - tracep->declQuad(c+1038,"i_a_sel", false,-1, 63,0); - tracep->declBit(c+1061,"o_a_stall", false,-1); - tracep->declBit(c+1062,"o_a_ack", false,-1); - tracep->declBit(c+1063,"o_a_err", false,-1); - tracep->declBit(c+981,"i_b_cyc", false,-1); - tracep->declBit(c+982,"i_b_stb", false,-1); - tracep->declBit(c+983,"i_b_we", false,-1); - tracep->declBus(c+986,"i_b_adr", false,-1, 21,0); - tracep->declArray(c+987,"i_b_dat", false,-1, 511,0); - tracep->declQuad(c+1003,"i_b_sel", false,-1, 63,0); - tracep->declBit(c+984,"o_b_stall", false,-1); - tracep->declBit(c+985,"o_b_ack", false,-1); - tracep->declBit(c+978,"o_b_err", false,-1); - tracep->declBit(c+261,"o_cyc", false,-1); - tracep->declBit(c+262,"o_stb", false,-1); - tracep->declBit(c+263,"o_we", false,-1); - tracep->declBus(c+264,"o_adr", false,-1, 21,0); - tracep->declArray(c+265,"o_dat", false,-1, 511,0); - tracep->declQuad(c+281,"o_sel", false,-1, 63,0); - tracep->declBit(c+283,"i_stall", false,-1); - tracep->declBit(c+284,"i_ack", false,-1); - tracep->declBit(c+1065,"i_err", false,-1); - tracep->declBit(c+1733,"r_a_owner", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("thecpu "); - tracep->declBus(c+5067,"RESET_ADDRESS", false,-1, 31,0); - tracep->declBus(c+5068,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5158,"OPT_LGICACHE", false,-1, 31,0); - tracep->declBus(c+5114,"DATA_WIDTH", false,-1, 31,0); - tracep->declBus(c+5062,"OPT_MPY", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_DIV", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_SHIFTS", false,-1, 0,0); - tracep->declBus(c+5113,"IMPLEMENT_FPU", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_EARLY_BRANCHING", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_CIS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DISTRIBUTED_REGS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PIPELINED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_START_HALTED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_LOCK", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5158,"OPT_LGDCACHE", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_SIM", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_CLKGATE", false,-1, 0,0); - tracep->declBus(c+5070,"WITH_LOCAL_BUS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DBGPORT", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_TRACE_PORT", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PROFILER", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_USERMODE", false,-1, 0,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5153,"WBLSB", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1057,"i_interrupt", false,-1); - tracep->declBit(c+916,"i_cpu_clken", false,-1); - tracep->declBit(c+954,"i_halt", false,-1); - tracep->declBit(c+956,"i_clear_cache", false,-1); - tracep->declBus(c+959,"i_dbg_wreg", false,-1, 4,0); - tracep->declBit(c+957,"i_dbg_we", false,-1); - tracep->declBus(c+960,"i_dbg_data", false,-1, 31,0); - tracep->declBus(c+1734,"i_dbg_rreg", false,-1, 4,0); - tracep->declBit(c+963,"o_dbg_stall", false,-1); - tracep->declBit(c+962,"o_halted", false,-1); - tracep->declBus(c+1060,"o_dbg_reg", false,-1, 31,0); - tracep->declBus(c+961,"o_dbg_cc", false,-1, 2,0); - tracep->declBit(c+942,"o_break", false,-1); - tracep->declBit(c+1005,"o_wb_gbl_cyc", false,-1); - tracep->declBit(c+1018,"o_wb_gbl_stb", false,-1); - tracep->declBit(c+1019,"o_wb_lcl_cyc", false,-1); - tracep->declBit(c+1020,"o_wb_lcl_stb", false,-1); - tracep->declBit(c+1021,"o_wb_we", false,-1); - tracep->declBus(c+922,"o_wb_addr", false,-1, 21,0); - tracep->declArray(c+1022,"o_wb_data", false,-1, 511,0); - tracep->declQuad(c+1038,"o_wb_sel", false,-1, 63,0); - tracep->declBit(c+1056,"i_wb_stall", false,-1); - tracep->declBit(c+1058,"i_wb_ack", false,-1); - tracep->declArray(c+1040,"i_wb_data", false,-1, 511,0); - tracep->declBit(c+1059,"i_wb_err", false,-1); - tracep->declBit(c+48,"o_op_stall", false,-1); - tracep->declBit(c+975,"o_pf_stall", false,-1); - tracep->declBit(c+976,"o_i_count", false,-1); - tracep->declBus(c+5076,"o_debug", false,-1, 31,0); - tracep->declBit(c+4996,"o_prof_stb", false,-1); - tracep->declBus(c+4997,"o_prof_addr", false,-1, 27,0); - tracep->declBus(c+4998,"o_prof_ticks", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_DCACHE", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PIPELINED_BUS_ACCESS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_MEMPIPE", false,-1, 0,0); - tracep->declBus(c+5114,"INSN_WIDTH", false,-1, 31,0); - tracep->declBit(c+5077,"cpu_clken", false,-1); - tracep->declBit(c+4901,"cpu_clock", false,-1); - tracep->declBit(c+5077,"clk_gate", false,-1); - tracep->declBus(c+5076,"cpu_debug", false,-1, 31,0); - tracep->declBit(c+1735,"pf_new_pc", false,-1); - tracep->declBit(c+1736,"clear_icache", false,-1); - tracep->declBit(c+50,"pf_ready", false,-1); - tracep->declBus(c+1737,"pf_request_address", false,-1, 27,0); - tracep->declBus(c+1738,"pf_instruction", false,-1, 31,0); - tracep->declBus(c+1739,"pf_instruction_pc", false,-1, 27,0); - tracep->declBit(c+1740,"pf_valid", false,-1); - tracep->declBit(c+1741,"pf_illegal", false,-1); - tracep->declBit(c+1742,"pf_cyc", false,-1); - tracep->declBit(c+1743,"pf_stb", false,-1); - tracep->declBit(c+1744,"pf_stall", false,-1); - tracep->declBit(c+1745,"pf_ack", false,-1); - tracep->declBit(c+1746,"pf_err", false,-1); - tracep->declBus(c+1747,"pf_addr", false,-1, 21,0); - tracep->declBit(c+5074,"pf_we", false,-1); - tracep->declArray(c+5078,"pf_data", false,-1, 511,0); - tracep->declBit(c+1748,"clear_dcache", false,-1); - tracep->declBit(c+51,"mem_ce", false,-1); - tracep->declBit(c+1749,"bus_lock", false,-1); - tracep->declBus(c+1750,"mem_op", false,-1, 2,0); - tracep->declBus(c+1751,"mem_cpu_addr", false,-1, 31,0); - tracep->declBus(c+1752,"mem_lock_pc", false,-1, 27,0); - tracep->declBus(c+1753,"mem_wdata", false,-1, 31,0); - tracep->declArray(c+1022,"mem_data", false,-1, 511,0); - tracep->declBus(c+1754,"mem_reg", false,-1, 4,0); - tracep->declBit(c+1755,"mem_busy", false,-1); - tracep->declBit(c+1756,"mem_rdbusy", false,-1); - tracep->declBit(c+1757,"mem_pipe_stalled", false,-1); - tracep->declBit(c+1758,"mem_valid", false,-1); - tracep->declBit(c+1759,"mem_bus_err", false,-1); - tracep->declBus(c+1760,"mem_wreg", false,-1, 4,0); - tracep->declBus(c+1761,"mem_result", false,-1, 31,0); - tracep->declBit(c+1762,"mem_stb_lcl", false,-1); - tracep->declBit(c+1763,"mem_stb_gbl", false,-1); - tracep->declBit(c+1764,"mem_cyc_lcl", false,-1); - tracep->declBit(c+1765,"mem_cyc_gbl", false,-1); - tracep->declBus(c+1766,"mem_bus_addr", false,-1, 21,0); - tracep->declBit(c+1767,"mem_we", false,-1); - tracep->declBit(c+1768,"mem_stall", false,-1); - tracep->declBit(c+1769,"mem_ack", false,-1); - tracep->declBit(c+1770,"mem_err", false,-1); - tracep->declQuad(c+1771,"mem_sel", false,-1, 63,0); - tracep->declBit(c+963,"w_dbg_stall", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("DATA_CACHE "); - tracep->pushNamePrefix("mem "); - tracep->declBus(c+5153,"LGCACHELEN", false,-1, 31,0); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5068,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5062,"LGNLINES", false,-1, 31,0); - tracep->declBus(c+5154,"NAUX", false,-1, 31,0); - tracep->declBus(c+5114,"DATA_WIDTH", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_LOCAL_BUS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PIPE", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_LOCK", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DUAL_READ_PORT", false,-1, 0,0); - tracep->declBus(c+5065,"OPT_FIFO_DEPTH", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5153,"CS", false,-1, 31,0); - tracep->declBus(c+5062,"LS", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5065,"DP", false,-1, 31,0); - tracep->declBus(c+5153,"WBLSB", false,-1, 31,0); - tracep->declBus(c+5116,"DC_IDLE", false,-1, 1,0); - tracep->declBus(c+5117,"DC_WRITE", false,-1, 1,0); - tracep->declBus(c+5118,"DC_READS", false,-1, 1,0); - tracep->declBus(c+5119,"DC_READC", false,-1, 1,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1748,"i_clear", false,-1); - tracep->declBit(c+51,"i_pipe_stb", false,-1); - tracep->declBit(c+1749,"i_lock", false,-1); - tracep->declBus(c+1750,"i_op", false,-1, 2,0); - tracep->declBus(c+1751,"i_addr", false,-1, 31,0); - tracep->declBus(c+1753,"i_data", false,-1, 31,0); - tracep->declBus(c+1754,"i_oreg", false,-1, 4,0); - tracep->declBit(c+1755,"o_busy", false,-1); - tracep->declBit(c+1756,"o_rdbusy", false,-1); - tracep->declBit(c+1757,"o_pipe_stalled", false,-1); - tracep->declBit(c+1758,"o_valid", false,-1); - tracep->declBit(c+1759,"o_err", false,-1); - tracep->declBus(c+1760,"o_wreg", false,-1, 4,0); - tracep->declBus(c+1761,"o_data", false,-1, 31,0); - tracep->declBit(c+1765,"o_wb_cyc_gbl", false,-1); - tracep->declBit(c+1764,"o_wb_cyc_lcl", false,-1); - tracep->declBit(c+1763,"o_wb_stb_gbl", false,-1); - tracep->declBit(c+1762,"o_wb_stb_lcl", false,-1); - tracep->declBit(c+1767,"o_wb_we", false,-1); - tracep->declBus(c+1766,"o_wb_addr", false,-1, 21,0); - tracep->declArray(c+1022,"o_wb_data", false,-1, 511,0); - tracep->declQuad(c+1771,"o_wb_sel", false,-1, 63,0); - tracep->declBit(c+1768,"i_wb_stall", false,-1); - tracep->declBit(c+1769,"i_wb_ack", false,-1); - tracep->declBit(c+1770,"i_wb_err", false,-1); - tracep->declArray(c+1040,"i_wb_data", false,-1, 511,0); - tracep->declBus(c+5158,"FIF_WIDTH", false,-1, 31,0); - tracep->declBus(c+1773,"ik", false,-1, 31,0); - tracep->declBit(c+1774,"cyc", false,-1); - tracep->declBit(c+1775,"stb", false,-1); - tracep->declBit(c+1776,"last_ack", false,-1); - tracep->declBit(c+1777,"end_of_line", false,-1); - tracep->declBit(c+1778,"last_line_stb", false,-1); - tracep->declBit(c+1779,"r_wb_cyc_gbl", false,-1); - tracep->declBit(c+1780,"r_wb_cyc_lcl", false,-1); - tracep->declBus(c+1781,"npending", false,-1, 4,0); - tracep->declBus(c+1782,"c_v", false,-1, 7,0); - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+1783+i*1,"c_vtags", true,(i+0), 18,0); - } - tracep->declBit(c+1791,"set_vflag", false,-1); - tracep->declBus(c+1792,"state", false,-1, 1,0); - tracep->declBus(c+1793,"wr_addr", false,-1, 5,0); - tracep->declArray(c+1794,"cached_iword", false,-1, 511,0); - tracep->declArray(c+1810,"cached_rword", false,-1, 511,0); - tracep->declBit(c+1826,"lock_gbl", false,-1); - tracep->declBit(c+1827,"lock_lcl", false,-1); - tracep->declBit(c+1828,"c_wr", false,-1); - tracep->declArray(c+1829,"c_wdata", false,-1, 511,0); - tracep->declQuad(c+1845,"c_wsel", false,-1, 63,0); - tracep->declBus(c+1847,"c_waddr", false,-1, 5,0); - tracep->declBus(c+1848,"last_tag", false,-1, 18,0); - tracep->declBit(c+1849,"last_tag_valid", false,-1); - tracep->declBus(c+1850,"i_cline", false,-1, 2,0); - tracep->declBus(c+1851,"i_caddr", false,-1, 5,0); - tracep->declBit(c+1852,"cache_miss_inow", false,-1); - tracep->declBit(c+1853,"w_cachable", false,-1); - tracep->declBit(c+1854,"raw_cachable_address", false,-1); - tracep->declBit(c+1855,"r_cachable", false,-1); - tracep->declBit(c+1856,"r_svalid", false,-1); - tracep->declBit(c+1857,"r_dvalid", false,-1); - tracep->declBit(c+1858,"r_rd", false,-1); - tracep->declBit(c+1859,"r_cache_miss", false,-1); - tracep->declBit(c+1860,"r_rd_pending", false,-1); - tracep->declBus(c+1861,"r_addr", false,-1, 21,0); - tracep->declBus(c+1862,"r_cline", false,-1, 2,0); - tracep->declBus(c+1863,"r_caddr", false,-1, 5,0); - tracep->declBus(c+1864,"r_ctag", false,-1, 18,0); - tracep->declBit(c+1865,"wr_cstb", false,-1); - tracep->declBit(c+1866,"r_iv", false,-1); - tracep->declBit(c+1867,"in_cache", false,-1); - tracep->declBus(c+1868,"r_itag", false,-1, 18,0); - tracep->declBus(c+1869,"req_data", false,-1, 12,0); - tracep->declBit(c+1870,"gie", false,-1); - tracep->declArray(c+1871,"pre_data", false,-1, 511,0); - tracep->declArray(c+1887,"pre_shifted", false,-1, 511,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_SEL "); - tracep->declBus(c+1903,"pre_sel", false,-1, 3,0); - tracep->declQuad(c+1904,"full_sel", false,-1, 63,0); - tracep->declQuad(c+1771,"r_wb_sel", false,-1, 63,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_WIDE_BUS "); - tracep->declBus(c+1906,"pre_shift", false,-1, 31,0); - tracep->declArray(c+1907,"wide_preshift", false,-1, 511,0); - tracep->declArray(c+1923,"shifted_data", false,-1, 511,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OPT_PIPE_FIFO "); - for (int i = 0; i < 16; ++i) { - tracep->declBus(c+1939+i*1,"fifo_data", true,(i+0), 11,0); - } - tracep->declBus(c+1955,"wraddr", false,-1, 4,0); - tracep->declBus(c+1956,"rdaddr", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("UNUSED_BITS "); - tracep->declBit(c+5241,"unused_aw", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("chkaddress "); - tracep->declBus(c+1957,"i_addr", false,-1, 27,0); - tracep->declBit(c+1854,"o_cachable", false,-1); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("NO_CLOCK_GATE "); - tracep->declBit(c+5074,"unused_clk", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("PFCACHE "); - tracep->pushNamePrefix("pf "); - tracep->declBus(c+5153,"LGCACHELEN", false,-1, 31,0); - tracep->declBus(c+5068,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5062,"LGLINES", false,-1, 31,0); - tracep->declBus(c+5111,"BUS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5120,"CACHELEN", false,-1, 31,0); - tracep->declBus(c+5153,"CW", false,-1, 31,0); - tracep->declBus(c+5062,"LS", false,-1, 31,0); - tracep->declBus(c+5111,"BUSW", false,-1, 31,0); - tracep->declBus(c+5114,"INSN_WIDTH", false,-1, 31,0); - tracep->declBus(c+5153,"WBLSB", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1735,"i_new_pc", false,-1); - tracep->declBit(c+1736,"i_clear_cache", false,-1); - tracep->declBit(c+50,"i_ready", false,-1); - tracep->declBus(c+1737,"i_pc", false,-1, 27,0); - tracep->declBit(c+1740,"o_valid", false,-1); - tracep->declBit(c+1741,"o_illegal", false,-1); - tracep->declBus(c+1738,"o_insn", false,-1, 31,0); - tracep->declBus(c+1739,"o_pc", false,-1, 27,0); - tracep->declBit(c+1742,"o_wb_cyc", false,-1); - tracep->declBit(c+1743,"o_wb_stb", false,-1); - tracep->declBit(c+5074,"o_wb_we", false,-1); - tracep->declBus(c+1747,"o_wb_addr", false,-1, 21,0); - tracep->declArray(c+5078,"o_wb_data", false,-1, 511,0); - tracep->declBit(c+1744,"i_wb_stall", false,-1); - tracep->declBit(c+1745,"i_wb_ack", false,-1); - tracep->declBit(c+1746,"i_wb_err", false,-1); - tracep->declArray(c+1040,"i_wb_data", false,-1, 511,0); - tracep->declBus(c+5075,"INLSB", false,-1, 31,0); - tracep->declBit(c+1958,"r_v", false,-1); - tracep->declArray(c+1959,"cache_word", false,-1, 511,0); - for (int i = 0; i < 8; ++i) { - tracep->declBus(c+1975+i*1,"cache_tags", true,(i+0), 15,0); - } - tracep->declBus(c+1983,"valid_mask", false,-1, 7,0); - tracep->declBit(c+1984,"r_v_from_pc", false,-1); - tracep->declBit(c+1985,"r_v_from_last", false,-1); - tracep->declBit(c+1986,"rvsrc", false,-1); - tracep->declBit(c+1987,"w_v_from_pc", false,-1); - tracep->declBit(c+1988,"w_v_from_last", false,-1); - tracep->declBus(c+1989,"lastpc", false,-1, 27,0); - tracep->declBus(c+1990,"wraddr", false,-1, 5,0); - tracep->declBus(c+1991,"pc_tag_lookup", false,-1, 21,3); - tracep->declBus(c+1992,"last_tag_lookup", false,-1, 21,3); - tracep->declBus(c+1993,"tag_lookup", false,-1, 21,3); - tracep->declBus(c+1994,"pc_tag", false,-1, 21,3); - tracep->declBus(c+1995,"lasttag", false,-1, 21,3); - tracep->declBit(c+1996,"illegal_valid", false,-1); - tracep->declBus(c+1997,"illegal_cache", false,-1, 21,3); - tracep->declArray(c+1998,"r_pc_cache", false,-1, 511,0); - tracep->declArray(c+2014,"r_last_cache", false,-1, 511,0); - tracep->declBus(c+1739,"r_pc", false,-1, 27,0); - tracep->declBit(c+2030,"isrc", false,-1); - tracep->declBus(c+2031,"delay", false,-1, 1,0); - tracep->declBit(c+2032,"svmask", false,-1); - tracep->declBit(c+2033,"last_ack", false,-1); - tracep->declBit(c+2034,"needload", false,-1); - tracep->declBit(c+2035,"last_addr", false,-1); - tracep->declBit(c+2036,"bus_abort", false,-1); - tracep->declBus(c+2037,"saddr", false,-1, 2,0); - tracep->declBit(c+52,"w_advance", false,-1); - tracep->declBit(c+2038,"w_invalidate_result", false,-1); - tracep->declBus(c+2039,"pc_line", false,-1, 2,0); - tracep->declBus(c+2040,"last_line", false,-1, 2,0); - tracep->pushNamePrefix("SHIFT_INSN "); - tracep->declArray(c+2041,"shifted", false,-1, 511,0); - tracep->declBus(c+2057,"shift", false,-1, 3,0); - tracep->declBit(c+5074,"unused_shift", false,-1); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("PRIORITY_DATA "); - tracep->pushNamePrefix("pformem "); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_ZERO_ON_IDLE", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1765,"i_a_cyc_a", false,-1); - tracep->declBit(c+1764,"i_a_cyc_b", false,-1); - tracep->declBit(c+1763,"i_a_stb_a", false,-1); - tracep->declBit(c+1762,"i_a_stb_b", false,-1); - tracep->declBit(c+1767,"i_a_we", false,-1); - tracep->declBus(c+1766,"i_a_adr", false,-1, 21,0); - tracep->declArray(c+1022,"i_a_dat", false,-1, 511,0); - tracep->declQuad(c+1771,"i_a_sel", false,-1, 63,0); - tracep->declBit(c+1768,"o_a_stall", false,-1); - tracep->declBit(c+1769,"o_a_ack", false,-1); - tracep->declBit(c+1770,"o_a_err", false,-1); - tracep->declBit(c+1742,"i_b_cyc_a", false,-1); - tracep->declBit(c+5074,"i_b_cyc_b", false,-1); - tracep->declBit(c+1743,"i_b_stb_a", false,-1); - tracep->declBit(c+5074,"i_b_stb_b", false,-1); - tracep->declBit(c+5074,"i_b_we", false,-1); - tracep->declBus(c+1747,"i_b_adr", false,-1, 21,0); - tracep->declArray(c+1022,"i_b_dat", false,-1, 511,0); - tracep->declQuad(c+5094,"i_b_sel", false,-1, 63,0); - tracep->declBit(c+1744,"o_b_stall", false,-1); - tracep->declBit(c+1745,"o_b_ack", false,-1); - tracep->declBit(c+1746,"o_b_err", false,-1); - tracep->declBit(c+1005,"o_cyc_a", false,-1); - tracep->declBit(c+1019,"o_cyc_b", false,-1); - tracep->declBit(c+1018,"o_stb_a", false,-1); - tracep->declBit(c+1020,"o_stb_b", false,-1); - tracep->declBit(c+1021,"o_we", false,-1); - tracep->declBus(c+922,"o_adr", false,-1, 21,0); - tracep->declArray(c+1022,"o_dat", false,-1, 511,0); - tracep->declQuad(c+1038,"o_sel", false,-1, 63,0); - tracep->declBit(c+1056,"i_stall", false,-1); - tracep->declBit(c+1058,"i_ack", false,-1); - tracep->declBit(c+1059,"i_err", false,-1); - tracep->declBit(c+2058,"r_a_owner", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("core "); - tracep->declBus(c+5131,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5067,"RESET_ADDRESS", false,-1, 31,0); - tracep->declBus(c+5062,"OPT_MPY", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_SHIFTS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DIV", false,-1, 0,0); - tracep->declBus(c+5113,"IMPLEMENT_FPU", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_EARLY_BRANCHING", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_CIS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_SIM", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DISTRIBUTED_REGS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PIPELINED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PIPELINED_BUS_ACCESS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_LOCK", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DCACHE", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_USERMODE", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_CLKGATE", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_START_HALTED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DBGPORT", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_TRACE_PORT", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PROFILER", false,-1, 0,0); - tracep->declBus(c+5131,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1057,"i_interrupt", false,-1); - tracep->declBit(c+5077,"o_clken", false,-1); - tracep->declBit(c+954,"i_halt", false,-1); - tracep->declBit(c+956,"i_clear_cache", false,-1); - tracep->declBus(c+959,"i_dbg_wreg", false,-1, 4,0); - tracep->declBit(c+957,"i_dbg_we", false,-1); - tracep->declBus(c+960,"i_dbg_data", false,-1, 31,0); - tracep->declBus(c+1734,"i_dbg_rreg", false,-1, 4,0); - tracep->declBit(c+963,"o_dbg_stall", false,-1); - tracep->declBus(c+1060,"o_dbg_reg", false,-1, 31,0); - tracep->declBus(c+961,"o_dbg_cc", false,-1, 2,0); - tracep->declBit(c+942,"o_break", false,-1); - tracep->declBit(c+1735,"o_pf_new_pc", false,-1); - tracep->declBit(c+1736,"o_clear_icache", false,-1); - tracep->declBit(c+50,"o_pf_ready", false,-1); - tracep->declBus(c+1737,"o_pf_request_address", false,-1, 27,0); - tracep->declBit(c+1740,"i_pf_valid", false,-1); - tracep->declBit(c+1741,"i_pf_illegal", false,-1); - tracep->declBus(c+1738,"i_pf_instruction", false,-1, 31,0); - tracep->declBus(c+1739,"i_pf_instruction_pc", false,-1, 27,0); - tracep->declBit(c+1748,"o_clear_dcache", false,-1); - tracep->declBit(c+51,"o_mem_ce", false,-1); - tracep->declBit(c+1749,"o_bus_lock", false,-1); - tracep->declBus(c+1750,"o_mem_op", false,-1, 2,0); - tracep->declBus(c+1751,"o_mem_addr", false,-1, 31,0); - tracep->declBus(c+1753,"o_mem_data", false,-1, 31,0); - tracep->declBus(c+1752,"o_mem_lock_pc", false,-1, 27,0); - tracep->declBus(c+1754,"o_mem_reg", false,-1, 4,0); - tracep->declBit(c+1755,"i_mem_busy", false,-1); - tracep->declBit(c+1756,"i_mem_rdbusy", false,-1); - tracep->declBit(c+1757,"i_mem_pipe_stalled", false,-1); - tracep->declBit(c+1758,"i_mem_valid", false,-1); - tracep->declBit(c+1759,"i_bus_err", false,-1); - tracep->declBus(c+1760,"i_mem_wreg", false,-1, 4,0); - tracep->declBus(c+1761,"i_mem_result", false,-1, 31,0); - tracep->declBit(c+48,"o_op_stall", false,-1); - tracep->declBit(c+975,"o_pf_stall", false,-1); - tracep->declBit(c+976,"o_i_count", false,-1); - tracep->declBus(c+5076,"o_debug", false,-1, 31,0); - tracep->declBit(c+4996,"o_prof_stb", false,-1); - tracep->declBus(c+4997,"o_prof_addr", false,-1, 27,0); - tracep->declBus(c+4998,"o_prof_ticks", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_MEMPIPE", false,-1, 0,0); - tracep->declBus(c+5242,"RESET_BUS_ADDRESS", false,-1, 25,0); - tracep->declBus(c+5243,"CPU_CC_REG", false,-1, 3,0); - tracep->declBus(c+5108,"CPU_PC_REG", false,-1, 3,0); - tracep->declBus(c+5122,"CPU_SUB_OP", false,-1, 3,0); - tracep->declBus(c+5123,"CPU_AND_OP", false,-1, 3,0); - tracep->declBus(c+5129,"CPU_BREV_OP", false,-1, 3,0); - tracep->declBus(c+5206,"CPU_MOV_OP", false,-1, 3,0); - tracep->declBus(c+5240,"CPU_CLRDCACHE_BIT", false,-1, 31,0); - tracep->declBus(c+5060,"CPU_CLRICACHE_BIT", false,-1, 31,0); - tracep->declBus(c+5136,"CPU_PHASE_BIT", false,-1, 31,0); - tracep->declBus(c+5158,"CPU_FPUERR_BIT", false,-1, 31,0); - tracep->declBus(c+5157,"CPU_DIVERR_BIT", false,-1, 31,0); - tracep->declBus(c+5061,"CPU_BUSERR_BIT", false,-1, 31,0); - tracep->declBus(c+5156,"CPU_TRAP_BIT", false,-1, 31,0); - tracep->declBus(c+5063,"CPU_ILL_BIT", false,-1, 31,0); - tracep->declBus(c+5072,"CPU_BREAK_BIT", false,-1, 31,0); - tracep->declBus(c+5153,"CPU_STEP_BIT", false,-1, 31,0); - tracep->declBus(c+5154,"CPU_GIE_BIT", false,-1, 31,0); - tracep->declBus(c+5065,"CPU_SLEEP_BIT", false,-1, 31,0); - for (int i = 0; i < 32; ++i) { - tracep->declBus(c+2059+i*1,"regset", true,(i+0), 31,0); - } - tracep->declBus(c+2091,"flags", false,-1, 3,0); - tracep->declBus(c+2092,"iflags", false,-1, 3,0); - tracep->declBus(c+2093,"w_uflags", false,-1, 15,0); - tracep->declBus(c+2094,"w_iflags", false,-1, 15,0); - tracep->declBit(c+2095,"break_en", false,-1); - tracep->declBit(c+2096,"user_step", false,-1); - tracep->declBit(c+2097,"sleep", false,-1); - tracep->declBit(c+2098,"r_halted", false,-1); - tracep->declBit(c+2099,"break_pending", false,-1); - tracep->declBit(c+2100,"trap", false,-1); - tracep->declBit(c+2101,"gie", false,-1); - tracep->declBit(c+2102,"ubreak", false,-1); - tracep->declBit(c+2103,"pending_interrupt", false,-1); - tracep->declBit(c+2104,"stepped", false,-1); - tracep->declBit(c+2105,"step", false,-1); - tracep->declBit(c+2106,"ill_err_u", false,-1); - tracep->declBit(c+2107,"ill_err_i", false,-1); - tracep->declBit(c+2108,"ibus_err_flag", false,-1); - tracep->declBit(c+2109,"ubus_err_flag", false,-1); - tracep->declBit(c+2110,"idiv_err_flag", false,-1); - tracep->declBit(c+2111,"udiv_err_flag", false,-1); - tracep->declBit(c+5074,"ifpu_err_flag", false,-1); - tracep->declBit(c+5074,"ufpu_err_flag", false,-1); - tracep->declBit(c+2112,"ihalt_phase", false,-1); - tracep->declBit(c+2113,"uhalt_phase", false,-1); - tracep->declBit(c+2114,"master_ce", false,-1); - tracep->declBit(c+53,"master_stall", false,-1); - tracep->declBus(c+2115,"pf_pc", false,-1, 27,0); - tracep->declBit(c+2116,"new_pc", false,-1); - tracep->declBit(c+2116,"clear_pipeline", false,-1); - tracep->declBit(c+54,"dcd_stalled", false,-1); - tracep->declBit(c+2101,"pf_gie", false,-1); - tracep->declBus(c+2117,"dcd_opn", false,-1, 3,0); - tracep->declBit(c+55,"dcd_ce", false,-1); - tracep->declBit(c+2118,"dcd_phase", false,-1); - tracep->declBus(c+2119,"dcd_A", false,-1, 4,0); - tracep->declBus(c+2120,"dcd_B", false,-1, 4,0); - tracep->declBus(c+2121,"dcd_R", false,-1, 4,0); - tracep->declBus(c+2122,"dcd_preA", false,-1, 4,0); - tracep->declBus(c+2123,"dcd_preB", false,-1, 4,0); - tracep->declBit(c+2124,"dcd_Acc", false,-1); - tracep->declBit(c+2125,"dcd_Bcc", false,-1); - tracep->declBit(c+2126,"dcd_Apc", false,-1); - tracep->declBit(c+2127,"dcd_Bpc", false,-1); - tracep->declBit(c+2128,"dcd_Rcc", false,-1); - tracep->declBit(c+2129,"dcd_Rpc", false,-1); - tracep->declBus(c+2130,"dcd_F", false,-1, 3,0); - tracep->declBit(c+2131,"dcd_wR", false,-1); - tracep->declBit(c+2132,"dcd_rA", false,-1); - tracep->declBit(c+2133,"dcd_rB", false,-1); - tracep->declBit(c+2134,"dcd_ALU", false,-1); - tracep->declBit(c+2135,"dcd_M", false,-1); - tracep->declBit(c+2136,"dcd_DIV", false,-1); - tracep->declBit(c+2137,"dcd_FP", false,-1); - tracep->declBit(c+2138,"dcd_wF", false,-1); - tracep->declBit(c+2101,"dcd_gie", false,-1); - tracep->declBit(c+2139,"dcd_break", false,-1); - tracep->declBit(c+2140,"dcd_lock", false,-1); - tracep->declBit(c+2141,"dcd_pipe", false,-1); - tracep->declBit(c+2142,"dcd_ljmp", false,-1); - tracep->declBit(c+2143,"dcd_valid", false,-1); - tracep->declBus(c+5017,"dcd_pc", false,-1, 27,0); - tracep->declBus(c+2144,"dcd_I", false,-1, 31,0); - tracep->declBit(c+2145,"dcd_zI", false,-1); - tracep->declBit(c+56,"dcd_A_stall", false,-1); - tracep->declBit(c+57,"dcd_B_stall", false,-1); - tracep->declBit(c+5018,"dcd_F_stall", false,-1); - tracep->declBit(c+2146,"dcd_illegal", false,-1); - tracep->declBit(c+2147,"dcd_early_branch", false,-1); - tracep->declBit(c+2148,"dcd_early_branch_stb", false,-1); - tracep->declBus(c+2149,"dcd_branch_pc", false,-1, 27,0); - tracep->declBit(c+5019,"dcd_sim", false,-1); - tracep->declBus(c+5020,"dcd_sim_immv", false,-1, 22,0); - tracep->declBit(c+2150,"prelock_stall", false,-1); - tracep->declBit(c+2151,"last_lock_insn", false,-1); - tracep->declBit(c+2152,"cc_invalid_for_dcd", false,-1); - tracep->declBit(c+2153,"pending_sreg_write", false,-1); - tracep->declBit(c+5021,"op_valid", false,-1); - tracep->declBit(c+2154,"op_valid_mem", false,-1); - tracep->declBit(c+2155,"op_valid_alu", false,-1); - tracep->declBit(c+2156,"op_valid_div", false,-1); - tracep->declBit(c+2157,"op_valid_fpu", false,-1); - tracep->declBit(c+58,"op_stall", false,-1); - tracep->declBus(c+2158,"op_opn", false,-1, 3,0); - tracep->declBus(c+1754,"op_R", false,-1, 4,0); - tracep->declBit(c+2159,"op_Rcc", false,-1); - tracep->declBus(c+2160,"op_Aid", false,-1, 4,0); - tracep->declBus(c+2161,"op_Bid", false,-1, 4,0); - tracep->declBit(c+2162,"op_rA", false,-1); - tracep->declBit(c+2163,"op_rB", false,-1); - tracep->declBus(c+2164,"r_op_Av", false,-1, 31,0); - tracep->declBus(c+2165,"r_op_Bv", false,-1, 31,0); - tracep->declBus(c+2166,"op_pc", false,-1, 27,0); - tracep->declBus(c+2167,"w_op_Av", false,-1, 31,0); - tracep->declBus(c+2168,"w_op_Bv", false,-1, 31,0); - tracep->declBus(c+1753,"op_Av", false,-1, 31,0); - tracep->declBus(c+1751,"op_Bv", false,-1, 31,0); - tracep->declBus(c+59,"w_pcB_v", false,-1, 31,0); - tracep->declBus(c+60,"w_pcA_v", false,-1, 31,0); - tracep->declBus(c+2169,"w_op_BnI", false,-1, 31,0); - tracep->declBit(c+2170,"op_wR", false,-1); - tracep->declBit(c+2171,"op_wF", false,-1); - tracep->declBit(c+2101,"op_gie", false,-1); - tracep->declBus(c+2172,"op_Fl", false,-1, 3,0); - tracep->declBus(c+2173,"r_op_F", false,-1, 6,0); - tracep->declBus(c+2174,"op_F", false,-1, 7,0); - tracep->declBit(c+61,"op_ce", false,-1); - tracep->declBit(c+2175,"op_phase", false,-1); - tracep->declBit(c+2176,"op_pipe", false,-1); - tracep->declBit(c+2177,"r_op_break", false,-1); - tracep->declBit(c+2178,"w_op_valid", false,-1); - tracep->declBit(c+5074,"op_lowpower_clear", false,-1); - tracep->declBus(c+5244,"w_cpu_info", false,-1, 8,0); - tracep->declBit(c+2179,"op_illegal", false,-1); - tracep->declBit(c+2177,"op_break", false,-1); - tracep->declBit(c+2180,"op_lock", false,-1); - tracep->declBit(c+5022,"op_sim", false,-1); - tracep->declBus(c+5023,"op_sim_immv", false,-1, 22,0); - tracep->declBit(c+5024,"alu_sim", false,-1); - tracep->declBus(c+5025,"alu_sim_immv", false,-1, 22,0); - tracep->declBus(c+2181,"alu_pc", false,-1, 27,0); - tracep->declBus(c+2182,"alu_reg", false,-1, 4,0); - tracep->declBit(c+2183,"r_alu_pc_valid", false,-1); - tracep->declBit(c+2184,"mem_pc_valid", false,-1); - tracep->declBit(c+2185,"alu_pc_valid", false,-1); - tracep->declBit(c+2186,"alu_phase", false,-1); - tracep->declBit(c+5026,"alu_ce", false,-1); - tracep->declBit(c+62,"alu_stall", false,-1); - tracep->declBus(c+2187,"alu_result", false,-1, 31,0); - tracep->declBus(c+2188,"alu_flags", false,-1, 3,0); - tracep->declBit(c+2189,"alu_valid", false,-1); - tracep->declBit(c+2190,"alu_busy", false,-1); - tracep->declBit(c+2191,"set_cond", false,-1); - tracep->declBit(c+2192,"alu_wR", false,-1); - tracep->declBit(c+2193,"alu_wF", false,-1); - tracep->declBit(c+2101,"alu_gie", false,-1); - tracep->declBit(c+2194,"alu_illegal", false,-1); - tracep->declBit(c+63,"mem_ce", false,-1); - tracep->declBit(c+64,"mem_stalled", false,-1); - tracep->declBit(c+65,"div_ce", false,-1); - tracep->declBit(c+2195,"div_error", false,-1); - tracep->declBit(c+2196,"div_busy", false,-1); - tracep->declBit(c+2197,"div_valid", false,-1); - tracep->declBus(c+2198,"div_result", false,-1, 31,0); - tracep->declBus(c+2199,"div_flags", false,-1, 3,0); - tracep->declBit(c+5074,"fpu_ce", false,-1); - tracep->declBit(c+5074,"fpu_error", false,-1); - tracep->declBit(c+5074,"fpu_busy", false,-1); - tracep->declBit(c+5074,"fpu_valid", false,-1); - tracep->declBus(c+5076,"fpu_result", false,-1, 31,0); - tracep->declBus(c+5122,"fpu_flags", false,-1, 3,0); - tracep->declBit(c+66,"adf_ce_unconditional", false,-1); - tracep->declBit(c+2200,"dbgv", false,-1); - tracep->declBit(c+2201,"dbg_clear_pipe", false,-1); - tracep->declBus(c+2202,"dbg_val", false,-1, 31,0); - tracep->declBus(c+2203,"debug_pc", false,-1, 31,0); - tracep->declBit(c+2204,"r_dbg_stall", false,-1); - tracep->declBit(c+2205,"wr_write_pc", false,-1); - tracep->declBit(c+2206,"wr_write_cc", false,-1); - tracep->declBit(c+2207,"wr_write_scc", false,-1); - tracep->declBit(c+2208,"wr_write_ucc", false,-1); - tracep->declBit(c+2209,"wr_reg_ce", false,-1); - tracep->declBit(c+2210,"wr_flags_ce", false,-1); - tracep->declBus(c+2211,"wr_flags", false,-1, 3,0); - tracep->declBus(c+2212,"wr_index", false,-1, 2,0); - tracep->declBus(c+2213,"wr_reg_id", false,-1, 4,0); - tracep->declBus(c+2214,"wr_gpreg_vl", false,-1, 31,0); - tracep->declBus(c+2215,"wr_spreg_vl", false,-1, 31,0); - tracep->declBit(c+2216,"w_switch_to_interrupt", false,-1); - tracep->declBit(c+2217,"w_release_from_interrupt", false,-1); - tracep->declBus(c+2218,"ipc", false,-1, 27,0); - tracep->declBus(c+2219,"upc", false,-1, 27,0); - tracep->declBit(c+2220,"last_write_to_cc", false,-1); - tracep->declBit(c+2221,"cc_write_hold", false,-1); - tracep->declBit(c+1736,"r_clear_icache", false,-1); - tracep->declBit(c+67,"pfpcset", false,-1); - tracep->declBus(c+68,"pfpcsrc", false,-1, 2,0); - tracep->declBit(c+5077,"w_clken", false,-1); - tracep->declBus(c+2222,"dcd_full_R", false,-1, 6,0); - tracep->declBus(c+2223,"dcd_full_A", false,-1, 6,0); - tracep->declBus(c+2224,"dcd_full_B", false,-1, 6,0); - tracep->declBus(c+69,"avsrc", false,-1, 2,0); - tracep->declBus(c+70,"bvsrc", false,-1, 2,0); - tracep->declBus(c+2225,"bisrc", false,-1, 1,0); - tracep->declBit(c+71,"cpu_sim", false,-1); - tracep->declBus(c+5113,"OPT_SIM_DEBUG", false,-1, 0,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("ALU_SIM "); - tracep->declBit(c+2226,"r_alu_sim", false,-1); - tracep->declBus(c+2227,"r_alu_sim_immv", false,-1, 22,0); - tracep->declBus(c+2228,"regid", false,-1, 4,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("BUSLOCK "); - tracep->declBit(c+2150,"r_prelock_stall", false,-1); - tracep->declBus(c+2229,"r_bus_lock", false,-1, 1,0); - tracep->declBus(c+1752,"r_lock_pc", false,-1, 27,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("CLEAR_DCACHE "); - tracep->declBit(c+1748,"r_clear_dcache", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("DIVERR "); - tracep->declBit(c+2110,"r_idiv_err_flag", false,-1); - tracep->pushNamePrefix("USER_DIVERR "); - tracep->declBit(c+2111,"r_udiv_err_flag", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("DIVIDE "); - tracep->pushNamePrefix("thedivide "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBus(c+5154,"LGBW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+2230,"i_reset", false,-1); - tracep->declBit(c+65,"i_wr", false,-1); - tracep->declBit(c+2231,"i_signed", false,-1); - tracep->declBus(c+1753,"i_numerator", false,-1, 31,0); - tracep->declBus(c+1751,"i_denominator", false,-1, 31,0); - tracep->declBit(c+2196,"o_busy", false,-1); - tracep->declBit(c+2197,"o_valid", false,-1); - tracep->declBit(c+2195,"o_err", false,-1); - tracep->declBus(c+2198,"o_quotient", false,-1, 31,0); - tracep->declBus(c+2199,"o_flags", false,-1, 3,0); - tracep->declBit(c+2232,"r_busy", false,-1); - tracep->declBus(c+2233,"r_divisor", false,-1, 31,0); - tracep->declQuad(c+2234,"r_dividend", false,-1, 62,0); - tracep->declQuad(c+2236,"diff", false,-1, 32,0); - tracep->declBit(c+2238,"r_sign", false,-1); - tracep->declBit(c+2239,"pre_sign", false,-1); - tracep->declBit(c+2240,"r_z", false,-1); - tracep->declBit(c+2241,"r_c", false,-1); - tracep->declBit(c+2242,"last_bit", false,-1); - tracep->declBus(c+2243,"r_bit", false,-1, 4,0); - tracep->declBit(c+2244,"zero_divisor", false,-1); - tracep->declBit(c+2245,"w_n", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("FWD_OPERATION "); - tracep->declBus(c+2158,"r_op_opn", false,-1, 3,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_ALU_PC "); - tracep->declBus(c+2181,"r_alu_pc", false,-1, 27,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_ALU_PHASE "); - tracep->declBit(c+2186,"r_alu_phase", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_ALU_STALL "); - tracep->declBit(c+5074,"unused_alu_stall", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_DISTRIBUTED_REGS "); - tracep->declBit(c+5074,"unused_prereg_addrs", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_IHALT_PHASE "); - tracep->declBit(c+2112,"r_ihalt_phase", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_OPLOCK "); - tracep->declBit(c+2180,"r_op_lock", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_OP_PIPE "); - tracep->declBit(c+2176,"r_op_pipe", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_OP_STALL "); - tracep->declBit(c+2152,"r_cc_invalid_for_dcd", false,-1); - tracep->declBit(c+2153,"r_pending_sreg_write", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_OP_WR "); - tracep->declBit(c+2170,"r_op_wR", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_PENDING_BREAK "); - tracep->declBit(c+2099,"r_break_pending", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_PENDING_INTERRUPT "); - tracep->declBit(c+2246,"r_pending_interrupt", false,-1); - tracep->declBit(c+2104,"r_user_stepped", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_PROFILER "); - tracep->declBit(c+2247,"prof_stb", false,-1); - tracep->declBus(c+2248,"prof_addr", false,-1, 27,0); - tracep->declBus(c+2249,"prof_ticks", false,-1, 31,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_UHALT_PHASE "); - tracep->declBit(c+2113,"r_uhalt_phase", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OPT_CIS_OP_PHASE "); - tracep->declBit(c+2175,"r_op_phase", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OP_REG_ADVANEC "); - tracep->declBus(c+1754,"r_op_R", false,-1, 4,0); - tracep->declBus(c+2160,"r_op_Aid", false,-1, 4,0); - tracep->declBus(c+2161,"r_op_Bid", false,-1, 4,0); - tracep->declBit(c+2162,"r_op_rA", false,-1); - tracep->declBit(c+2163,"r_op_rB", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OP_SIM "); - tracep->declBit(c+2250,"r_op_sim", false,-1); - tracep->declBus(c+2251,"r_op_sim_immv", false,-1, 22,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SETDBG "); - tracep->declBus(c+2252,"pre_dbg_reg", false,-1, 31,0); - tracep->declBus(c+1060,"r_dbg_reg", false,-1, 31,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SET_ALU_ILLEGAL "); - tracep->declBit(c+2194,"r_alu_illegal", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SET_GIE "); - tracep->declBit(c+2101,"r_gie", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SET_OP_PC "); - tracep->declBus(c+2166,"r_op_pc", false,-1, 27,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SET_TRAP_N_UBREAK "); - tracep->declBit(c+2100,"r_trap", false,-1); - tracep->declBit(c+2102,"r_ubreak", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SET_USER_BUSERR "); - tracep->declBit(c+2109,"r_ubus_err_flag", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SET_USER_ILLEGAL_INSN "); - tracep->declBit(c+2106,"r_ill_err_u", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SET_USER_PC "); - tracep->declBus(c+2219,"r_upc", false,-1, 27,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("UNUSED_AW "); - tracep->declBit(c+5074,"generic_ignore", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("doalu "); - tracep->declBus(c+5062,"OPT_MPY", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_SHIFTS", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+2230,"i_reset", false,-1); - tracep->declBit(c+5026,"i_stb", false,-1); - tracep->declBus(c+2158,"i_op", false,-1, 3,0); - tracep->declBus(c+1753,"i_a", false,-1, 31,0); - tracep->declBus(c+1751,"i_b", false,-1, 31,0); - tracep->declBus(c+2187,"o_c", false,-1, 31,0); - tracep->declBus(c+2188,"o_f", false,-1, 3,0); - tracep->declBit(c+2189,"o_valid", false,-1); - tracep->declBit(c+2190,"o_busy", false,-1); - tracep->declBus(c+2253,"w_brev_result", false,-1, 31,0); - tracep->declBit(c+2254,"z", false,-1); - tracep->declBit(c+2255,"n", false,-1); - tracep->declBit(c+2256,"v", false,-1); - tracep->declBit(c+2257,"vx", false,-1); - tracep->declBit(c+2258,"c", false,-1); - tracep->declBit(c+2259,"pre_sign", false,-1); - tracep->declBit(c+2260,"set_ovfl", false,-1); - tracep->declBit(c+2261,"keep_sgn_on_ovfl", false,-1); - tracep->declQuad(c+2262,"w_lsr_result", false,-1, 32,0); - tracep->declQuad(c+2264,"w_asr_result", false,-1, 32,0); - tracep->declQuad(c+2266,"w_lsl_result", false,-1, 32,0); - tracep->declQuad(c+2268,"mpy_result", false,-1, 63,0); - tracep->declBit(c+2270,"mpyhi", false,-1); - tracep->declBit(c+2271,"mpybusy", false,-1); - tracep->declBit(c+2272,"mpydone", false,-1); - tracep->declBit(c+72,"this_is_a_multiply_op", false,-1); - tracep->declBit(c+2190,"r_busy", false,-1); - tracep->pushNamePrefix("IMPLEMENT_SHIFTS "); - tracep->declQuad(c+2273,"w_pre_asr_input", false,-1, 32,0); - tracep->declQuad(c+2275,"w_pre_asr_shifted", false,-1, 32,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("thempy "); - tracep->declBus(c+5062,"OPT_MPY", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+2230,"i_reset", false,-1); - tracep->declBit(c+72,"i_stb", false,-1); - tracep->declBus(c+2277,"i_op", false,-1, 1,0); - tracep->declBus(c+1753,"i_a", false,-1, 31,0); - tracep->declBus(c+1751,"i_b", false,-1, 31,0); - tracep->declBit(c+2272,"o_valid", false,-1); - tracep->declBit(c+2271,"o_busy", false,-1); - tracep->declQuad(c+2268,"o_result", false,-1, 63,0); - tracep->declBit(c+2270,"o_hi", false,-1); - tracep->pushNamePrefix("IMPY "); - tracep->pushNamePrefix("MPN1 "); - tracep->pushNamePrefix("MPN2 "); - tracep->pushNamePrefix("MPY3CK "); - tracep->declQuad(c+2278,"r_smpy_result", false,-1, 63,0); - tracep->declQuad(c+2280,"r_umpy_result", false,-1, 63,0); - tracep->declBus(c+2282,"r_mpy_a_input", false,-1, 31,0); - tracep->declBus(c+2283,"r_mpy_b_input", false,-1, 31,0); - tracep->declBus(c+2284,"mpypipe", false,-1, 1,0); - tracep->declBus(c+2285,"r_sgn", false,-1, 1,0); - tracep->declBit(c+2270,"r_hi", false,-1); - tracep->declQuad(c+2286,"s_mpy_a_input", false,-1, 63,0); - tracep->declQuad(c+2288,"s_mpy_b_input", false,-1, 63,0); - tracep->declQuad(c+2290,"u_mpy_a_input", false,-1, 63,0); - tracep->declQuad(c+2292,"u_mpy_b_input", false,-1, 63,0); - tracep->popNamePrefix(6); - tracep->pushNamePrefix("instruction_decoder "); - tracep->declBus(c+5131,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_MPY", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_SHIFTS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_EARLY_BRANCHING", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_PIPELINED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DIVIDE", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_FPU", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_CIS", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_LOCK", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_OPIPE", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_SIM", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_SUPPRESS_NULL_BRANCHES", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_USERMODE", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5131,"AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+2294,"i_reset", false,-1); - tracep->declBit(c+55,"i_ce", false,-1); - tracep->declBit(c+54,"i_stalled", false,-1); - tracep->declBus(c+1738,"i_instruction", false,-1, 31,0); - tracep->declBit(c+2101,"i_gie", false,-1); - tracep->declBus(c+1739,"i_pc", false,-1, 27,0); - tracep->declBit(c+1740,"i_pf_valid", false,-1); - tracep->declBit(c+1741,"i_illegal", false,-1); - tracep->declBit(c+2143,"o_valid", false,-1); - tracep->declBit(c+2118,"o_phase", false,-1); - tracep->declBit(c+2146,"o_illegal", false,-1); - tracep->declBus(c+5017,"o_pc", false,-1, 27,0); - tracep->declBus(c+2222,"o_dcdR", false,-1, 6,0); - tracep->declBus(c+2223,"o_dcdA", false,-1, 6,0); - tracep->declBus(c+2224,"o_dcdB", false,-1, 6,0); - tracep->declBus(c+2122,"o_preA", false,-1, 4,0); - tracep->declBus(c+2123,"o_preB", false,-1, 4,0); - tracep->declBus(c+2144,"o_I", false,-1, 31,0); - tracep->declBit(c+2145,"o_zI", false,-1); - tracep->declBus(c+2130,"o_cond", false,-1, 3,0); - tracep->declBit(c+2138,"o_wF", false,-1); - tracep->declBus(c+2117,"o_op", false,-1, 3,0); - tracep->declBit(c+2134,"o_ALU", false,-1); - tracep->declBit(c+2135,"o_M", false,-1); - tracep->declBit(c+2136,"o_DV", false,-1); - tracep->declBit(c+2137,"o_FP", false,-1); - tracep->declBit(c+2139,"o_break", false,-1); - tracep->declBit(c+2140,"o_lock", false,-1); - tracep->declBit(c+2131,"o_wR", false,-1); - tracep->declBit(c+2132,"o_rA", false,-1); - tracep->declBit(c+2133,"o_rB", false,-1); - tracep->declBit(c+2147,"o_early_branch", false,-1); - tracep->declBit(c+2148,"o_early_branch_stb", false,-1); - tracep->declBus(c+2149,"o_branch_pc", false,-1, 27,0); - tracep->declBit(c+2142,"o_ljmp", false,-1); - tracep->declBit(c+2141,"o_pipe", false,-1); - tracep->declBit(c+5019,"o_sim", false,-1); - tracep->declBus(c+5020,"o_sim_immv", false,-1, 22,0); - tracep->declBus(c+5206,"CPU_SP_REG", false,-1, 3,0); - tracep->declBus(c+5243,"CPU_CC_REG", false,-1, 3,0); - tracep->declBus(c+5108,"CPU_PC_REG", false,-1, 3,0); - tracep->declBus(c+5184,"CISBIT", false,-1, 31,0); - tracep->declBus(c+5133,"CISIMMSEL", false,-1, 31,0); - tracep->declBus(c+5134,"IMMSEL", false,-1, 31,0); - tracep->declBus(c+2295,"w_op", false,-1, 4,0); - tracep->declBit(c+2296,"w_ldi", false,-1); - tracep->declBit(c+2297,"w_mov", false,-1); - tracep->declBit(c+2298,"w_cmptst", false,-1); - tracep->declBit(c+2299,"w_ldilo", false,-1); - tracep->declBit(c+2300,"w_ALU", false,-1); - tracep->declBit(c+2301,"w_brev", false,-1); - tracep->declBit(c+2302,"w_noop", false,-1); - tracep->declBit(c+2303,"w_lock", false,-1); - tracep->declBit(c+2304,"w_sim", false,-1); - tracep->declBit(c+2305,"w_break", false,-1); - tracep->declBit(c+2306,"w_special", false,-1); - tracep->declBit(c+2307,"w_add", false,-1); - tracep->declBit(c+2308,"w_mpy", false,-1); - tracep->declBus(c+2122,"w_dcdR", false,-1, 4,0); - tracep->declBus(c+2123,"w_dcdB", false,-1, 4,0); - tracep->declBus(c+2122,"w_dcdA", false,-1, 4,0); - tracep->declBit(c+2309,"w_dcdR_pc", false,-1); - tracep->declBit(c+2310,"w_dcdR_cc", false,-1); - tracep->declBit(c+2309,"w_dcdA_pc", false,-1); - tracep->declBit(c+2310,"w_dcdA_cc", false,-1); - tracep->declBit(c+2311,"w_dcdB_pc", false,-1); - tracep->declBit(c+2312,"w_dcdB_cc", false,-1); - tracep->declBus(c+2313,"w_cond", false,-1, 3,0); - tracep->declBit(c+2314,"w_wF", false,-1); - tracep->declBit(c+2315,"w_mem", false,-1); - tracep->declBit(c+2316,"w_sto", false,-1); - tracep->declBit(c+2317,"w_div", false,-1); - tracep->declBit(c+2318,"w_fpu", false,-1); - tracep->declBit(c+2319,"w_wR", false,-1); - tracep->declBit(c+2320,"w_rA", false,-1); - tracep->declBit(c+2321,"w_rB", false,-1); - tracep->declBit(c+2322,"w_wR_n", false,-1); - tracep->declBit(c+2323,"w_ljmp", false,-1); - tracep->declBit(c+2142,"w_ljmp_dly", false,-1); - tracep->declBit(c+2324,"w_cis_ljmp", false,-1); - tracep->declBus(c+2325,"iword", false,-1, 31,0); - tracep->declBit(c+2326,"pf_valid", false,-1); - tracep->declBus(c+2327,"r_nxt_half", false,-1, 14,0); - tracep->declBus(c+2328,"w_cis_op", false,-1, 4,0); - tracep->declBus(c+2329,"r_I", false,-1, 22,0); - tracep->declBus(c+2330,"w_fullI", false,-1, 22,0); - tracep->declBus(c+2331,"w_I", false,-1, 22,0); - tracep->declBit(c+2332,"w_Iz", false,-1); - tracep->declBus(c+2333,"w_immsrc", false,-1, 1,0); - tracep->declBit(c+2143,"r_valid", false,-1); - tracep->declBit(c+2334,"insn_is_pipeable", false,-1); - tracep->declBit(c+5074,"illegal_shift", false,-1); - tracep->declBit(c+5074,"possibly_unused", false,-1); - tracep->pushNamePrefix("GEN_CIS_IMMEDIATE "); - tracep->declBus(c+2335,"w_halfI", false,-1, 7,0); - tracep->declBus(c+2336,"w_halfbits", false,-1, 7,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_CIS_PHASE "); - tracep->declBit(c+2118,"r_phase", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_EARLY_BRANCH_LOGIC "); - tracep->declBit(c+2147,"r_early_branch", false,-1); - tracep->declBit(c+2148,"r_early_branch_stb", false,-1); - tracep->declBit(c+2142,"r_ljmp", false,-1); - tracep->declBus(c+2149,"r_branch_pc", false,-1, 27,0); - tracep->declBit(c+2337,"w_add_to_pc", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_OPIPE "); - tracep->declBit(c+2141,"r_pipe", false,-1); - tracep->declBit(c+2334,"r_insn_is_pipeable", false,-1); - tracep->popNamePrefix(4); - tracep->pushNamePrefix("u_jiffies "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1093,"i_ce", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+2338,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1012,"o_wb_ack", false,-1); - tracep->declBus(c+1016,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+904,"o_int", false,-1); - tracep->declBus(c+1016,"r_counter", false,-1, 31,0); - tracep->declBit(c+2339,"int_set", false,-1); - tracep->declBit(c+2340,"new_set", false,-1); - tracep->declBit(c+2341,"int_now", false,-1); - tracep->declBus(c+2342,"int_when", false,-1, 31,0); - tracep->declBus(c+2343,"new_when", false,-1, 31,0); - tracep->declBus(c+2344,"till_wb", false,-1, 31,0); - tracep->declBus(c+2345,"till_when", false,-1, 31,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_timer_a "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBus(c+5184,"VW", false,-1, 31,0); - tracep->declBus(c+5070,"RELOADABLE", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1093,"i_ce", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+2346,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1009,"o_wb_ack", false,-1); - tracep->declBus(c+1013,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+901,"o_int", false,-1); - tracep->declBit(c+2347,"r_running", false,-1); - tracep->declBit(c+2348,"r_zero", false,-1); - tracep->declBus(c+2349,"r_value", false,-1, 30,0); - tracep->declBit(c+2350,"wb_write", false,-1); - tracep->declBit(c+2351,"auto_reload", false,-1); - tracep->declBus(c+2352,"interval_count", false,-1, 30,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_RELOAD "); - tracep->declBit(c+2351,"r_auto_reload", false,-1); - tracep->declBus(c+2352,"r_interval_count", false,-1, 30,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_timer_b "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBus(c+5184,"VW", false,-1, 31,0); - tracep->declBus(c+5070,"RELOADABLE", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1093,"i_ce", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+2353,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1010,"o_wb_ack", false,-1); - tracep->declBus(c+1014,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+902,"o_int", false,-1); - tracep->declBit(c+2354,"r_running", false,-1); - tracep->declBit(c+2355,"r_zero", false,-1); - tracep->declBus(c+2356,"r_value", false,-1, 30,0); - tracep->declBit(c+2357,"wb_write", false,-1); - tracep->declBit(c+2358,"auto_reload", false,-1); - tracep->declBus(c+2359,"interval_count", false,-1, 30,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_RELOAD "); - tracep->declBit(c+2358,"r_auto_reload", false,-1); - tracep->declBus(c+2359,"r_interval_count", false,-1, 30,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_timer_c "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBus(c+5184,"VW", false,-1, 31,0); - tracep->declBus(c+5070,"RELOADABLE", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1093,"i_ce", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+2360,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+1011,"o_wb_ack", false,-1); - tracep->declBus(c+1015,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+903,"o_int", false,-1); - tracep->declBit(c+2361,"r_running", false,-1); - tracep->declBit(c+2362,"r_zero", false,-1); - tracep->declBus(c+2363,"r_value", false,-1, 30,0); - tracep->declBit(c+2364,"wb_write", false,-1); - tracep->declBit(c+2365,"auto_reload", false,-1); - tracep->declBus(c+2366,"interval_count", false,-1, 30,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_RELOAD "); - tracep->declBit(c+2365,"r_auto_reload", false,-1); - tracep->declBus(c+2366,"r_interval_count", false,-1, 30,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_watchbus "); - tracep->declBus(c+5060,"BW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+2367,"i_reset", false,-1); - tracep->declBus(c+5245,"i_timeout", false,-1, 13,0); - tracep->declBit(c+974,"o_int", false,-1); - tracep->declBus(c+2368,"r_value", false,-1, 13,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_watchdog "); - tracep->declBus(c+5114,"BW", false,-1, 31,0); - tracep->declBus(c+5184,"VW", false,-1, 31,0); - tracep->declBus(c+5113,"RELOADABLE", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+953,"i_reset", false,-1); - tracep->declBit(c+1093,"i_ce", false,-1); - tracep->declBit(c+917,"i_wb_cyc", false,-1); - tracep->declBit(c+2369,"i_wb_stb", false,-1); - tracep->declBit(c+919,"i_wb_we", false,-1); - tracep->declBus(c+921,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+5108,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+966,"o_wb_ack", false,-1); - tracep->declBus(c+968,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+967,"o_int", false,-1); - tracep->declBit(c+2370,"r_running", false,-1); - tracep->declBit(c+2371,"r_zero", false,-1); - tracep->declBus(c+2372,"r_value", false,-1, 30,0); - tracep->declBit(c+2373,"wb_write", false,-1); - tracep->declBit(c+5074,"auto_reload", false,-1); - tracep->declBus(c+5246,"interval_count", false,-1, 30,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("txv "); - tracep->declBus(c+5247,"TIMING_BITS", false,-1, 4,0); - tracep->declBus(c+5247,"TB", false,-1, 4,0); - tracep->declBus(c+5213,"CLOCKS_PER_BAUD", false,-1, 6,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+193,"i_wr", false,-1); - tracep->declBus(c+191,"i_data", false,-1, 7,0); - tracep->declBit(c+5001,"o_uart_tx", false,-1); - tracep->declBit(c+194,"o_busy", false,-1); - tracep->declBus(c+5122,"TXUL_BIT_ZERO", false,-1, 3,0); - tracep->declBus(c+5129,"TXUL_STOP", false,-1, 3,0); - tracep->declBus(c+5108,"TXUL_IDLE", false,-1, 3,0); - tracep->declBus(c+2374,"baud_counter", false,-1, 6,0); - tracep->declBus(c+2375,"state", false,-1, 3,0); - tracep->declBus(c+2376,"lcl_data", false,-1, 7,0); - tracep->declBit(c+194,"r_busy", false,-1); - tracep->declBit(c+2377,"zero_baud_counter", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_emmc "); - tracep->declBus(c+5158,"LGFIFO", false,-1, 31,0); - tracep->declBus(c+5063,"NUMIO", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_DDR", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_CARD_DETECT", false,-1, 0,0); - tracep->declBus(c+5133,"LGTIMEOUT", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+5074,"i_hsclk", false,-1); - tracep->declBit(c+4533,"i_wb_cyc", false,-1); - tracep->declBit(c+4534,"i_wb_stb", false,-1); - tracep->declBit(c+4535,"i_wb_we", false,-1); - tracep->declBus(c+4592,"i_wb_addr", false,-1, 2,0); - tracep->declBus(c+4537,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4538,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+401,"o_wb_ack", false,-1); - tracep->declBus(c+402,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+4966,"o_ck", false,-1); - tracep->declBit(c+4967,"i_ds", false,-1); - tracep->declBit(c+4968,"io_cmd_tristate", false,-1); - tracep->declBit(c+4969,"o_cmd", false,-1); - tracep->declBit(c+4970,"i_cmd", false,-1); - tracep->declBus(c+4971,"io_dat_tristate", false,-1, 7,0); - tracep->declBus(c+4972,"o_dat", false,-1, 7,0); - tracep->declBus(c+4973,"i_dat", false,-1, 7,0); - tracep->declBit(c+4974,"i_card_detect", false,-1); - tracep->declBit(c+5074,"o_1p8v", false,-1); - tracep->declBit(c+160,"o_int", false,-1); - tracep->declBus(c+36,"o_debug", false,-1, 31,0); - tracep->declBit(c+2378,"cfg_ddr", false,-1); - tracep->declBus(c+2379,"cfg_sample_shift", false,-1, 4,0); - tracep->declBus(c+2380,"sdclk", false,-1, 7,0); - tracep->declBit(c+2381,"cmd_en", false,-1); - tracep->declBit(c+2382,"pp_cmd", false,-1); - tracep->declBus(c+2383,"cmd_data", false,-1, 1,0); - tracep->declBit(c+2384,"data_en", false,-1); - tracep->declBit(c+2385,"pp_data", false,-1); - tracep->declBit(c+2386,"rx_en", false,-1); - tracep->declBus(c+2387,"tx_data", false,-1, 31,0); - tracep->declBit(c+2388,"afifo_reset_n", false,-1); - tracep->declBus(c+2389,"rply_strb", false,-1, 1,0); - tracep->declBus(c+2390,"rply_data", false,-1, 1,0); - tracep->declBit(c+2391,"card_busy", false,-1); - tracep->declBus(c+2392,"rx_strb", false,-1, 1,0); - tracep->declBus(c+2393,"rx_data", false,-1, 15,0); - tracep->declBit(c+5074,"AC_VALID", false,-1); - tracep->declBus(c+5116,"AC_DATA", false,-1, 1,0); - tracep->declBit(c+5074,"AD_VALID", false,-1); - tracep->declBus(c+5076,"AD_DATA", false,-1, 31,0); - tracep->pushNamePrefix("u_sdfrontend "); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_DDR", false,-1, 0,0); - tracep->declBus(c+5063,"NUMIO", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_hsclk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+2378,"i_cfg_ddr", false,-1); - tracep->declBus(c+2379,"i_sample_shift", false,-1, 4,0); - tracep->declBus(c+2380,"i_sdclk", false,-1, 7,0); - tracep->declBit(c+2381,"i_cmd_en", false,-1); - tracep->declBit(c+2382,"i_pp_cmd", false,-1); - tracep->declBus(c+2383,"i_cmd_data", false,-1, 1,0); - tracep->declBit(c+2384,"i_data_en", false,-1); - tracep->declBit(c+2386,"i_rx_en", false,-1); - tracep->declBit(c+2385,"i_pp_data", false,-1); - tracep->declBus(c+2387,"i_tx_data", false,-1, 31,0); - tracep->declBit(c+2388,"i_afifo_reset_n", false,-1); - tracep->declBit(c+2391,"o_data_busy", false,-1); - tracep->declBus(c+2389,"o_cmd_strb", false,-1, 1,0); - tracep->declBus(c+2390,"o_cmd_data", false,-1, 1,0); - tracep->declBus(c+2392,"o_rx_strb", false,-1, 1,0); - tracep->declBus(c+2393,"o_rx_data", false,-1, 15,0); - tracep->declBit(c+5074,"MAC_VALID", false,-1); - tracep->declBus(c+5116,"MAC_DATA", false,-1, 1,0); - tracep->declBit(c+5074,"MAD_VALID", false,-1); - tracep->declBus(c+5076,"MAD_DATA", false,-1, 31,0); - tracep->declBit(c+4966,"o_ck", false,-1); - tracep->declBit(c+4967,"i_ds", false,-1); - tracep->declBit(c+4968,"io_cmd_tristate", false,-1); - tracep->declBit(c+4969,"o_cmd", false,-1); - tracep->declBit(c+4970,"i_cmd", false,-1); - tracep->declBus(c+4971,"io_dat_tristate", false,-1, 7,0); - tracep->declBus(c+4972,"o_dat", false,-1, 7,0); - tracep->declBus(c+4973,"i_dat", false,-1, 7,0); - tracep->declBus(c+36,"o_debug", false,-1, 31,0); - tracep->declBit(c+2391,"dat0_busy", false,-1); - tracep->declBit(c+2394,"wait_for_busy", false,-1); - tracep->pushNamePrefix("GEN_NO_SERDES "); - tracep->declBit(c+2395,"next_pedge", false,-1); - tracep->declBit(c+2396,"next_dedge", false,-1); - tracep->declBit(c+2397,"resp_started", false,-1); - tracep->declBit(c+2398,"io_started", false,-1); - tracep->declBit(c+2399,"last_ck", false,-1); - tracep->declBit(c+2400,"r_cmd_data", false,-1); - tracep->declBit(c+2401,"r_cmd_strb", false,-1); - tracep->declBit(c+2402,"r_rx_strb", false,-1); - tracep->declBus(c+2403,"r_rx_data", false,-1, 7,0); - tracep->declBus(c+2404,"ck_sreg", false,-1, 1,0); - tracep->declBus(c+2405,"pck_sreg", false,-1, 1,0); - tracep->declBit(c+2406,"sample_ck", false,-1); - tracep->declBit(c+2407,"cmd_sample_ck", false,-1); - tracep->declBus(c+4973,"w_out", false,-1, 7,0); - tracep->declBit(c+5074,"unused_no_serdes", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_sdio "); - tracep->declBus(c+5158,"LGFIFO", false,-1, 31,0); - tracep->declBus(c+5063,"NUMIO", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_DDR", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_CARD_DETECT", false,-1, 0,0); - tracep->declBus(c+5133,"LGTIMEOUT", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4533,"i_wb_cyc", false,-1); - tracep->declBit(c+4534,"i_wb_stb", false,-1); - tracep->declBit(c+4535,"i_wb_we", false,-1); - tracep->declBus(c+4592,"i_wb_addr", false,-1, 2,0); - tracep->declBus(c+4537,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4538,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+401,"o_wb_ack", false,-1); - tracep->declBus(c+402,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+4974,"i_card_detect", false,-1); - tracep->declBit(c+5074,"o_1p8v", false,-1); - tracep->declBit(c+160,"o_int", false,-1); - tracep->declBit(c+2378,"o_cfg_ddr", false,-1); - tracep->declBus(c+2379,"o_cfg_sample_shift", false,-1, 4,0); - tracep->declBus(c+2380,"o_sdclk", false,-1, 7,0); - tracep->declBit(c+2381,"o_cmd_en", false,-1); - tracep->declBit(c+2382,"o_pp_cmd", false,-1); - tracep->declBus(c+2383,"o_cmd_data", false,-1, 1,0); - tracep->declBit(c+2384,"o_data_en", false,-1); - tracep->declBit(c+2385,"o_pp_data", false,-1); - tracep->declBit(c+2386,"o_rx_en", false,-1); - tracep->declBus(c+2387,"o_tx_data", false,-1, 31,0); - tracep->declBit(c+2388,"o_afifo_reset_n", false,-1); - tracep->declBus(c+2389,"i_cmd_strb", false,-1, 1,0); - tracep->declBus(c+2390,"i_cmd_data", false,-1, 1,0); - tracep->declBit(c+2391,"i_card_busy", false,-1); - tracep->declBus(c+2392,"i_rx_strb", false,-1, 1,0); - tracep->declBus(c+2393,"i_rx_data", false,-1, 15,0); - tracep->declBit(c+5074,"S_AC_VALID", false,-1); - tracep->declBus(c+5116,"S_AC_DATA", false,-1, 1,0); - tracep->declBit(c+5074,"S_AD_VALID", false,-1); - tracep->declBus(c+5076,"S_AD_DATA", false,-1, 31,0); - tracep->declBit(c+2408,"soft_reset", false,-1); - tracep->declBit(c+2409,"cfg_clk90", false,-1); - tracep->declBit(c+2410,"cfg_clk_shutdown", false,-1); - tracep->declBit(c+2411,"cfg_ds", false,-1); - tracep->declBus(c+2412,"cfg_ckspeed", false,-1, 7,0); - tracep->declBus(c+2413,"cfg_width", false,-1, 1,0); - tracep->declBit(c+2414,"clk_stb", false,-1); - tracep->declBit(c+2415,"clk_half", false,-1); - tracep->declBus(c+2416,"w_sdclk", false,-1, 7,0); - tracep->declBus(c+2417,"clk_ckspd", false,-1, 7,0); - tracep->declBit(c+2418,"cmd_request", false,-1); - tracep->declBit(c+2419,"cmd_err", false,-1); - tracep->declBit(c+2420,"cmd_busy", false,-1); - tracep->declBit(c+2421,"cmd_done", false,-1); - tracep->declBus(c+2422,"cmd_type", false,-1, 1,0); - tracep->declBus(c+2423,"cmd_ercode", false,-1, 1,0); - tracep->declBit(c+2424,"rsp_stb", false,-1); - tracep->declBus(c+2425,"cmd_id", false,-1, 6,0); - tracep->declBus(c+2426,"rsp_id", false,-1, 5,0); - tracep->declBus(c+2427,"cmd_arg", false,-1, 31,0); - tracep->declBus(c+2428,"rsp_arg", false,-1, 31,0); - tracep->declBit(c+2429,"cmd_mem_valid", false,-1); - tracep->declBus(c+5108,"cmd_mem_strb", false,-1, 3,0); - tracep->declBus(c+2430,"cmd_mem_addr", false,-1, 9,0); - tracep->declBus(c+2431,"cmd_mem_data", false,-1, 31,0); - tracep->declBit(c+2432,"tx_en", false,-1); - tracep->declBit(c+2433,"tx_mem_valid", false,-1); - tracep->declBit(c+2434,"tx_mem_ready", false,-1); - tracep->declBit(c+2435,"tx_mem_last", false,-1); - tracep->declBus(c+2436,"tx_mem_data", false,-1, 31,0); - tracep->declBit(c+5077,"crc_en", false,-1); - tracep->declBus(c+2437,"rx_length", false,-1, 12,0); - tracep->declBit(c+2438,"rx_mem_valid", false,-1); - tracep->declBus(c+2439,"rx_mem_addr", false,-1, 9,0); - tracep->declBus(c+2440,"rx_mem_strb", false,-1, 3,0); - tracep->declBus(c+2441,"rx_mem_data", false,-1, 31,0); - tracep->declBit(c+2442,"rx_done", false,-1); - tracep->declBit(c+2443,"rx_err", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("u_clkgen "); - tracep->declBus(c+5063,"LGMAXDIV", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+2409,"i_cfg_clk90", false,-1); - tracep->declBus(c+2412,"i_cfg_ckspd", false,-1, 7,0); - tracep->declBit(c+2410,"i_cfg_shutdown", false,-1); - tracep->declBit(c+2414,"o_ckstb", false,-1); - tracep->declBit(c+2415,"o_hlfck", false,-1); - tracep->declBus(c+2416,"o_ckwide", false,-1, 7,0); - tracep->declBus(c+2417,"o_ckspd", false,-1, 7,0); - tracep->declBus(c+5061,"NCTR", false,-1, 31,0); - tracep->declBit(c+2444,"nxt_stb", false,-1); - tracep->declBit(c+2445,"nxt_clk", false,-1); - tracep->declBus(c+2446,"nxt_counter", false,-1, 9,0); - tracep->declBus(c+2447,"counter", false,-1, 9,0); - tracep->declBit(c+2448,"clk90", false,-1); - tracep->declBus(c+2449,"ckspd", false,-1, 7,0); - tracep->declBit(c+2450,"w_clk90", false,-1); - tracep->declBus(c+2451,"w_ckspd", false,-1, 7,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_control "); - tracep->declBus(c+5158,"LGFIFO", false,-1, 31,0); - tracep->declBus(c+5063,"NUMIO", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_DDR", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_CARD_DETECT", false,-1, 0,0); - tracep->declBus(c+5061,"LGFIFOW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_DMA", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_1P8V", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4533,"i_wb_cyc", false,-1); - tracep->declBit(c+4534,"i_wb_stb", false,-1); - tracep->declBit(c+4535,"i_wb_we", false,-1); - tracep->declBus(c+4592,"i_wb_addr", false,-1, 2,0); - tracep->declBus(c+4537,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4538,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+401,"o_wb_ack", false,-1); - tracep->declBus(c+402,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+2409,"o_cfg_clk90", false,-1); - tracep->declBus(c+2412,"o_cfg_ckspeed", false,-1, 7,0); - tracep->declBit(c+2410,"o_cfg_shutdown", false,-1); - tracep->declBus(c+2413,"o_cfg_width", false,-1, 1,0); - tracep->declBit(c+2411,"o_cfg_ds", false,-1); - tracep->declBit(c+2378,"o_cfg_ddr", false,-1); - tracep->declBit(c+2382,"o_pp_cmd", false,-1); - tracep->declBit(c+2385,"o_pp_data", false,-1); - tracep->declBus(c+2379,"o_cfg_sample_shift", false,-1, 4,0); - tracep->declBus(c+2417,"i_ckspd", false,-1, 7,0); - tracep->declBit(c+2408,"o_soft_reset", false,-1); - tracep->declBit(c+2418,"o_cmd_request", false,-1); - tracep->declBus(c+2422,"o_cmd_type", false,-1, 1,0); - tracep->declBus(c+2425,"o_cmd_id", false,-1, 6,0); - tracep->declBus(c+2427,"o_arg", false,-1, 31,0); - tracep->declBit(c+2420,"i_cmd_busy", false,-1); - tracep->declBit(c+2421,"i_cmd_done", false,-1); - tracep->declBit(c+2419,"i_cmd_err", false,-1); - tracep->declBus(c+2423,"i_cmd_ercode", false,-1, 1,0); - tracep->declBit(c+2424,"i_cmd_response", false,-1); - tracep->declBus(c+2426,"i_resp", false,-1, 5,0); - tracep->declBus(c+2428,"i_arg", false,-1, 31,0); - tracep->declBit(c+2429,"i_cmd_mem_valid", false,-1); - tracep->declBus(c+5108,"i_cmd_mem_strb", false,-1, 3,0); - tracep->declBus(c+2430,"i_cmd_mem_addr", false,-1, 9,0); - tracep->declBus(c+2431,"i_cmd_mem_data", false,-1, 31,0); - tracep->declBit(c+2432,"o_tx_en", false,-1); - tracep->declBit(c+2433,"o_tx_mem_valid", false,-1); - tracep->declBit(c+2452,"i_tx_mem_ready", false,-1); - tracep->declBus(c+2436,"o_tx_mem_data", false,-1, 31,0); - tracep->declBit(c+2435,"o_tx_mem_last", false,-1); - tracep->declBit(c+2384,"i_tx_busy", false,-1); - tracep->declBit(c+2386,"o_rx_en", false,-1); - tracep->declBit(c+5077,"o_crc_en", false,-1); - tracep->declBus(c+2437,"o_length", false,-1, 12,0); - tracep->declBit(c+2438,"i_rx_mem_valid", false,-1); - tracep->declBus(c+2440,"i_rx_mem_strb", false,-1, 3,0); - tracep->declBus(c+2439,"i_rx_mem_addr", false,-1, 9,0); - tracep->declBus(c+2441,"i_rx_mem_data", false,-1, 31,0); - tracep->declBit(c+2442,"i_rx_done", false,-1); - tracep->declBit(c+2443,"i_rx_err", false,-1); - tracep->declBit(c+4974,"i_card_detect", false,-1); - tracep->declBit(c+2391,"i_card_busy", false,-1); - tracep->declBit(c+5074,"o_1p8v", false,-1); - tracep->declBit(c+160,"o_int", false,-1); - tracep->declBus(c+5061,"LGFIFO32", false,-1, 31,0); - tracep->declBus(c+5159,"ADDR_CMD", false,-1, 2,0); - tracep->declBus(c+5166,"ADDR_ARG", false,-1, 2,0); - tracep->declBus(c+5160,"ADDR_FIFOA", false,-1, 2,0); - tracep->declBus(c+5162,"ADDR_FIFOB", false,-1, 2,0); - tracep->declBus(c+5207,"ADDR_PHY", false,-1, 2,0); - tracep->declBus(c+5117,"CMD_PREFIX", false,-1, 1,0); - tracep->declBus(c+5116,"NUL_PREFIX", false,-1, 1,0); - tracep->declBus(c+5116,"RNO_REPLY", false,-1, 1,0); - tracep->declBus(c+5118,"R2_REPLY", false,-1, 1,0); - tracep->declBus(c+5134,"CARD_REMOVED_BIT", false,-1, 31,0); - tracep->declBus(c+5136,"USE_DMA_BIT", false,-1, 31,0); - tracep->declBus(c+5158,"FIFO_ID_BIT", false,-1, 31,0); - tracep->declBus(c+5157,"USE_FIFO_BIT", false,-1, 31,0); - tracep->declBus(c+5061,"FIFO_WRITE_BIT", false,-1, 31,0); - tracep->declBus(c+5116,"WIDTH_1W", false,-1, 1,0); - tracep->declBus(c+5117,"WIDTH_4W", false,-1, 1,0); - tracep->declBus(c+5118,"WIDTH_8W", false,-1, 1,0); - tracep->declBit(c+4593,"wb_cmd_stb", false,-1); - tracep->declBit(c+4594,"wb_phy_stb", false,-1); - tracep->declBus(c+2425,"r_cmd", false,-1, 6,0); - tracep->declBit(c+2453,"r_tx_request", false,-1); - tracep->declBit(c+2454,"r_rx_request", false,-1); - tracep->declBit(c+2455,"r_tx_sent", false,-1); - tracep->declBit(c+2456,"r_fifo", false,-1); - tracep->declBit(c+2457,"r_cmd_err", false,-1); - tracep->declBus(c+2458,"r_cmd_ecode", false,-1, 1,0); - tracep->declBus(c+2427,"r_arg", false,-1, 31,0); - tracep->declBus(c+2459,"lgblk", false,-1, 3,0); - tracep->declBus(c+2413,"r_width", false,-1, 1,0); - tracep->declBus(c+2412,"r_ckspeed", false,-1, 7,0); - tracep->declBus(c+2460,"w_cmd_word", false,-1, 31,0); - tracep->declBus(c+2461,"w_phy_ctrl", false,-1, 31,0); - tracep->declBus(c+2462,"blk_words", false,-1, 15,0); - tracep->declBus(c+2463,"ika", false,-1, 31,0); - tracep->declBus(c+2464,"ikb", false,-1, 31,0); - tracep->declBus(c+5189,"NFIFOW", false,-1, 31,0); - tracep->declBus(c+2465,"tx_fifo_a", false,-1, 31,0); - tracep->declBus(c+2466,"tx_fifo_b", false,-1, 31,0); - tracep->declBus(c+5113,"tx_shift", false,-1, 0,0); - tracep->declBus(c+2467,"fif_wraddr", false,-1, 9,0); - tracep->declBus(c+2468,"fif_rdaddr", false,-1, 9,0); - tracep->declBus(c+2469,"fif_a_rdaddr", false,-1, 9,0); - tracep->declBus(c+2470,"fif_b_rdaddr", false,-1, 9,0); - tracep->declBus(c+2471,"tx_mem_addr", false,-1, 9,0); - tracep->declBus(c+2472,"next_tx_mem", false,-1, 31,0); - tracep->declBit(c+2473,"tx_fifo_last", false,-1); - tracep->declBit(c+2474,"pre_tx_last", false,-1); - tracep->declBit(c+2475,"tx_pipe_valid", false,-1); - tracep->declBit(c+5077,"card_present", false,-1); - tracep->declBit(c+5074,"card_removed", false,-1); - tracep->declBit(c+2476,"pre_ack", false,-1); - tracep->declBus(c+2477,"pre_sel", false,-1, 1,0); - tracep->declBus(c+2478,"pre_data", false,-1, 31,0); - tracep->declBus(c+2479,"mem_wr_addr_a", false,-1, 9,0); - tracep->declBus(c+2480,"mem_wr_addr_b", false,-1, 9,0); - tracep->declBus(c+2481,"mem_wr_strb_a", false,-1, 3,0); - tracep->declBus(c+2482,"mem_wr_strb_b", false,-1, 3,0); - tracep->declBus(c+2483,"mem_wr_data_a", false,-1, 31,0); - tracep->declBus(c+2484,"mem_wr_data_b", false,-1, 31,0); - tracep->declBit(c+2485,"cmd_busy", false,-1); - tracep->declBit(c+125,"new_cmd_request", false,-1); - tracep->declBit(c+126,"new_data_request", false,-1); - tracep->declBit(c+127,"new_tx_request", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("NO_CARD_DETECT_SIGNAL "); - tracep->declBit(c+5074,"unused_card_detect", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_rxframe "); - tracep->declBus(c+5158,"LGLEN", false,-1, 31,0); - tracep->declBus(c+5065,"NUMIO", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBus(c+5061,"LGLENW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_DS", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5133,"LGTIMEOUT", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+73,"i_reset", false,-1); - tracep->declBit(c+2411,"i_cfg_ds", false,-1); - tracep->declBit(c+2378,"i_cfg_ddr", false,-1); - tracep->declBus(c+2413,"i_cfg_width", false,-1, 1,0); - tracep->declBit(c+2386,"i_rx_en", false,-1); - tracep->declBit(c+5077,"i_crc_en", false,-1); - tracep->declBus(c+2437,"i_length", false,-1, 12,0); - tracep->declBus(c+2392,"i_rx_strb", false,-1, 1,0); - tracep->declBus(c+2393,"i_rx_data", false,-1, 15,0); - tracep->declBit(c+5074,"S_ASYNC_VALID", false,-1); - tracep->declBus(c+5076,"S_ASYNC_DATA", false,-1, 31,0); - tracep->declBit(c+2438,"o_mem_valid", false,-1); - tracep->declBus(c+2440,"o_mem_strb", false,-1, 3,0); - tracep->declBus(c+2439,"o_mem_addr", false,-1, 9,0); - tracep->declBus(c+2441,"o_mem_data", false,-1, 31,0); - tracep->declBit(c+2442,"o_done", false,-1); - tracep->declBit(c+2443,"o_err", false,-1); - tracep->declBus(c+5116,"WIDTH_1W", false,-1, 1,0); - tracep->declBus(c+5117,"WIDTH_4W", false,-1, 1,0); - tracep->declBus(c+5118,"WIDTH_8W", false,-1, 1,0); - tracep->declBus(c+5069,"NCRC", false,-1, 31,0); - tracep->declBus(c+5248,"CRC_POLYNOMIAL", false,-1, 15,0); - tracep->declBus(c+2486,"sync_fill", false,-1, 4,0); - tracep->declBus(c+2487,"sync_sreg", false,-1, 19,0); - tracep->declBit(c+2488,"s2_valid", false,-1); - tracep->declBus(c+2489,"s2_fill", false,-1, 1,0); - tracep->declBus(c+2490,"s2_data", false,-1, 15,0); - tracep->declBit(c+2438,"mem_valid", false,-1); - tracep->declBit(c+2491,"mem_full", false,-1); - tracep->declBit(c+2492,"rnxt_strb", false,-1); - tracep->declBus(c+2440,"mem_strb", false,-1, 3,0); - tracep->declBus(c+2441,"mem_data", false,-1, 31,0); - tracep->declBus(c+2439,"mem_addr", false,-1, 9,0); - tracep->declBus(c+2493,"subaddr", false,-1, 1,0); - tracep->declBus(c+2494,"next_subaddr", false,-1, 1,0); - tracep->declBus(c+2495,"rnxt_data", false,-1, 7,0); - tracep->declBit(c+2496,"busy", false,-1); - tracep->declBit(c+2497,"data_phase", false,-1); - tracep->declBit(c+2498,"load_crc", false,-1); - tracep->declBit(c+2499,"pending_crc", false,-1); - tracep->declBus(c+2500,"rail_count", false,-1, 15,0); - tracep->declBus(c+2501,"err", false,-1, 7,0); - tracep->declBus(c+2502,"r_timeout", false,-1, 22,0); - tracep->declBit(c+2503,"r_watchdog", false,-1); - tracep->declBit(c+2504,"last_strb", false,-1); - tracep->declBit(c+2505,"w_done", false,-1); - tracep->pushNamePrefix("GEN_RAIL_CRC[0] "); - tracep->declBus(c+2506,"pedge_crc", false,-1, 15,0); - tracep->declBus(c+2507,"nedge_crc", false,-1, 15,0); - tracep->declBus(c+2508,"lcl_err", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_RAIL_CRC[1] "); - tracep->declBus(c+2509,"pedge_crc", false,-1, 15,0); - tracep->declBus(c+2510,"nedge_crc", false,-1, 15,0); - tracep->declBus(c+2511,"lcl_err", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_RAIL_CRC[2] "); - tracep->declBus(c+2512,"pedge_crc", false,-1, 15,0); - tracep->declBus(c+2513,"nedge_crc", false,-1, 15,0); - tracep->declBus(c+2514,"lcl_err", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_RAIL_CRC[3] "); - tracep->declBus(c+2515,"pedge_crc", false,-1, 15,0); - tracep->declBus(c+2516,"nedge_crc", false,-1, 15,0); - tracep->declBus(c+2517,"lcl_err", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_sdcmd "); - tracep->declBus(c+5113,"OPT_DS", false,-1, 0,0); - tracep->declBus(c+5131,"LGTIMEOUT", false,-1, 31,0); - tracep->declBus(c+5061,"LGLEN", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+73,"i_reset", false,-1); - tracep->declBit(c+2411,"i_cfg_ds", false,-1); - tracep->declBit(c+2518,"i_cfg_dbl", false,-1); - tracep->declBit(c+2414,"i_ckstb", false,-1); - tracep->declBit(c+2418,"i_cmd_request", false,-1); - tracep->declBus(c+2422,"i_cmd_type", false,-1, 1,0); - tracep->declBus(c+2425,"i_cmd", false,-1, 6,0); - tracep->declBus(c+2427,"i_arg", false,-1, 31,0); - tracep->declBit(c+2420,"o_busy", false,-1); - tracep->declBit(c+2421,"o_done", false,-1); - tracep->declBit(c+2419,"o_err", false,-1); - tracep->declBus(c+2423,"o_ercode", false,-1, 1,0); - tracep->declBit(c+2381,"o_cmd_en", false,-1); - tracep->declBus(c+2383,"o_cmd_data", false,-1, 1,0); - tracep->declBus(c+2389,"i_cmd_strb", false,-1, 1,0); - tracep->declBus(c+2390,"i_cmd_data", false,-1, 1,0); - tracep->declBit(c+5074,"S_ASYNC_VALID", false,-1); - tracep->declBus(c+5116,"S_ASYNC_DATA", false,-1, 1,0); - tracep->declBit(c+2424,"o_cmd_response", false,-1); - tracep->declBus(c+2426,"o_resp", false,-1, 5,0); - tracep->declBus(c+2428,"o_arg", false,-1, 31,0); - tracep->declBit(c+2429,"o_mem_valid", false,-1); - tracep->declBus(c+5108,"o_mem_strb", false,-1, 3,0); - tracep->declBus(c+2430,"o_mem_addr", false,-1, 9,0); - tracep->declBus(c+2431,"o_mem_data", false,-1, 31,0); - tracep->declBus(c+5116,"R_NONE", false,-1, 1,0); - tracep->declBus(c+5117,"R_R1", false,-1, 1,0); - tracep->declBus(c+5118,"R_R2", false,-1, 1,0); - tracep->declBus(c+5116,"ECODE_TIMEOUT", false,-1, 1,0); - tracep->declBus(c+5117,"ECODE_OKAY", false,-1, 1,0); - tracep->declBus(c+5118,"ECODE_BADCRC", false,-1, 1,0); - tracep->declBus(c+5119,"ECODE_FRAMEERR", false,-1, 1,0); - tracep->declBus(c+5249,"CRC_POLYNOMIAL", false,-1, 6,0); - tracep->declBit(c+2381,"active", false,-1); - tracep->declBus(c+2519,"srcount", false,-1, 5,0); - tracep->declQuad(c+2520,"tx_sreg", false,-1, 47,0); - tracep->declBit(c+2522,"waiting_on_response", false,-1); - tracep->declBit(c+2523,"cfg_ds", false,-1); - tracep->declBit(c+2524,"cfg_dbl", false,-1); - tracep->declBit(c+2525,"r_frame_err", false,-1); - tracep->declBus(c+2526,"cmd_type", false,-1, 1,0); - tracep->declBus(c+2527,"resp_count", false,-1, 7,0); - tracep->declBit(c+2528,"frame_err", false,-1); - tracep->declBit(c+2529,"w_done", false,-1); - tracep->declBit(c+2530,"crc_err", false,-1); - tracep->declBit(c+2531,"w_no_response", false,-1); - tracep->declBus(c+2430,"mem_addr", false,-1, 9,0); - tracep->declQuad(c+2532,"rx_sreg", false,-1, 39,0); - tracep->declBit(c+2534,"rx_timeout", false,-1); - tracep->declBus(c+2535,"rx_timeout_counter", false,-1, 25,0); - tracep->declBus(c+2536,"crc_fill", false,-1, 6,0); - tracep->declBit(c+2537,"r_busy", false,-1); - tracep->declBit(c+2538,"new_data", false,-1); - tracep->declBit(c+2539,"r_done", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_txframe "); - tracep->declBus(c+5069,"NCRC", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5248,"CRC_POLYNOMIAL", false,-1, 15,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+73,"i_reset", false,-1); - tracep->declBus(c+2412,"i_cfg_spd", false,-1, 7,0); - tracep->declBus(c+2413,"i_cfg_width", false,-1, 1,0); - tracep->declBit(c+2378,"i_cfg_ddr", false,-1); - tracep->declBit(c+2432,"i_en", false,-1); - tracep->declBit(c+2414,"i_ckstb", false,-1); - tracep->declBit(c+2415,"i_hlfck", false,-1); - tracep->declBit(c+2540,"S_VALID", false,-1); - tracep->declBit(c+2434,"S_READY", false,-1); - tracep->declBus(c+2436,"S_DATA", false,-1, 31,0); - tracep->declBit(c+2435,"S_LAST", false,-1); - tracep->declBit(c+2384,"tx_valid", false,-1); - tracep->declBus(c+2387,"tx_data", false,-1, 31,0); - tracep->declBus(c+5116,"P_IDLE", false,-1, 1,0); - tracep->declBus(c+5117,"P_DATA", false,-1, 1,0); - tracep->declBus(c+5118,"P_CRC", false,-1, 1,0); - tracep->declBus(c+5119,"P_LAST", false,-1, 1,0); - tracep->declBus(c+5116,"WIDTH_1W", false,-1, 1,0); - tracep->declBus(c+5117,"WIDTH_4W", false,-1, 1,0); - tracep->declBus(c+5118,"WIDTH_8W", false,-1, 1,0); - tracep->declBus(c+5116,"P_1D", false,-1, 1,0); - tracep->declBus(c+5117,"P_2D", false,-1, 1,0); - tracep->declBus(c+5118,"P_4D", false,-1, 1,0); - tracep->declBit(c+2541,"cfg_ddr", false,-1); - tracep->declBus(c+2542,"cfg_width", false,-1, 1,0); - tracep->declBus(c+2543,"cfg_period", false,-1, 1,0); - tracep->declBit(c+2544,"start_packet", false,-1); - tracep->declBit(c+2545,"pre_valid", false,-1); - tracep->declBus(c+2546,"pstate", false,-1, 1,0); - tracep->declBit(c+2547,"pre_ready", false,-1); - tracep->declBus(c+2548,"pre_data", false,-1, 31,0); - tracep->declBus(c+2549,"pre_count", false,-1, 3,0); - tracep->declBus(c+5250,"ik", false,-1, 31,0); - tracep->declBus(c+5250,"jk", false,-1, 31,0); - tracep->declBus(c+2550,"crc_1w_reg", false,-1, 15,0); - tracep->declBus(c+2551,"di_crc_2w", false,-1, 31,0); - tracep->declBus(c+2552,"nxt_crc_2w", false,-1, 31,0); - tracep->declBus(c+2553,"new_crc_2w", false,-1, 31,0); - tracep->declBus(c+2554,"crc_2w_reg", false,-1, 31,0); - tracep->declQuad(c+2555,"di_crc_4w", false,-1, 63,0); - tracep->declQuad(c+2557,"nxt_crc_4w", false,-1, 63,0); - tracep->declQuad(c+2559,"new_crc_4w", false,-1, 63,0); - tracep->declQuad(c+2561,"crc_4w_reg", false,-1, 63,0); - tracep->declArray(c+2563,"di_crc_8w", false,-1, 127,0); - tracep->declArray(c+2567,"nxt_crc_8w", false,-1, 127,0); - tracep->declArray(c+2571,"new_crc_8w", false,-1, 127,0); - tracep->declArray(c+2575,"crc_8w_reg", false,-1, 127,0); - tracep->declArray(c+2579,"di_crc_8d", false,-1, 255,0); - tracep->declArray(c+2587,"nxt_crc_8d", false,-1, 255,0); - tracep->declArray(c+2595,"new_crc_8d", false,-1, 255,0); - tracep->declArray(c+2603,"crc_8d_reg", false,-1, 255,0); - tracep->declBit(c+2384,"ck_valid", false,-1); - tracep->declBus(c+2611,"ck_counts", false,-1, 4,0); - tracep->declBus(c+2387,"ck_data", false,-1, 31,0); - tracep->declBus(c+2612,"ck_sreg", false,-1, 31,0); - tracep->declBit(c+2613,"ck_stop_bit", false,-1); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("u_fan "); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4539,"i_wb_cyc", false,-1); - tracep->declBit(c+4540,"i_wb_stb", false,-1); - tracep->declBit(c+4541,"i_wb_we", false,-1); - tracep->declBus(c+4595,"i_wb_addr", false,-1, 2,0); - tracep->declBus(c+4543,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4544,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+403,"o_wb_ack", false,-1); - tracep->declBus(c+404,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+4959,"i_temp_sda", false,-1); - tracep->declBit(c+4960,"i_temp_scl", false,-1); - tracep->declBit(c+4961,"o_temp_sda", false,-1); - tracep->declBit(c+4962,"o_temp_scl", false,-1); - tracep->declBit(c+4963,"o_fpga_pwm", false,-1); - tracep->declBit(c+4964,"o_sys_pwm", false,-1); - tracep->declBit(c+4965,"i_fan_tach", false,-1); - tracep->declBus(c+5009,"temp_debug", false,-1, 31,0); - tracep->declBus(c+5251,"CK_PER_SECOND", false,-1, 31,0); - tracep->declBus(c+5252,"CK_PER_MS", false,-1, 31,0); - tracep->declBus(c+5253,"PWM_HZ", false,-1, 31,0); - tracep->declBus(c+5254,"MAX_PWM", false,-1, 31,0); - tracep->declBus(c+5136,"LGPWM", false,-1, 31,0); - tracep->declBus(c+2614,"pwm_counter", false,-1, 12,0); - tracep->declBus(c+2615,"ctl_fpga", false,-1, 12,0); - tracep->declBus(c+2616,"ctl_sys", false,-1, 12,0); - tracep->declBit(c+2617,"ck_tach", false,-1); - tracep->declBit(c+2618,"last_tach", false,-1); - tracep->declBus(c+2619,"pipe_tach", false,-1, 1,0); - tracep->declBit(c+2620,"tach_reset", false,-1); - tracep->declBus(c+2621,"tach_count", false,-1, 26,0); - tracep->declBus(c+2622,"tach_counter", false,-1, 26,0); - tracep->declBus(c+2623,"tach_timer", false,-1, 26,0); - tracep->declBit(c+5074,"i2c_wb_stall", false,-1); - tracep->declBit(c+2624,"i2c_wb_ack", false,-1); - tracep->declBus(c+2625,"i2c_wb_data", false,-1, 31,0); - tracep->declBit(c+2626,"ign_mem_cyc", false,-1); - tracep->declBit(c+2627,"mem_stb", false,-1); - tracep->declBit(c+5074,"ign_mem_we", false,-1); - tracep->declBit(c+5070,"ign_mem_sel", false,-1); - tracep->declBus(c+2628,"mem_addr", false,-1, 4,0); - tracep->declBus(c+5112,"ign_mem_data", false,-1, 7,0); - tracep->declBus(c+2629,"mem_data", false,-1, 7,0); - tracep->declBit(c+2630,"mem_ack", false,-1); - tracep->declBit(c+2631,"i2cd_valid", false,-1); - tracep->declBit(c+2632,"i2cd_last", false,-1); - tracep->declBit(c+5074,"ign_i2cd_id", false,-1); - tracep->declBus(c+2633,"i2cd_data", false,-1, 7,0); - tracep->declBit(c+2634,"pp_ms", false,-1); - tracep->declBus(c+2635,"trigger_counter", false,-1, 16,0); - tracep->declBus(c+2636,"temp_tmp", false,-1, 23,0); - tracep->declBus(c+2637,"temp_data", false,-1, 31,0); - tracep->declBit(c+2638,"pre_ack", false,-1); - tracep->declBus(c+2639,"pre_data", false,-1, 31,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("u_i2ccpu "); - tracep->declBus(c+5154,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5063,"DATA_WIDTH", false,-1, 31,0); - tracep->declBus(c+5063,"I2C_WIDTH", false,-1, 31,0); - tracep->declBus(c+5076,"AXIS_ID_WIDTH", false,-1, 31,0); - tracep->declBus(c+5113,"DEF_CHANNEL", false,-1, 0,0); - tracep->declBus(c+5154,"AW", false,-1, 31,0); - tracep->declBus(c+5063,"DW", false,-1, 31,0); - tracep->declBus(c+5063,"RW", false,-1, 31,0); - tracep->declBus(c+5154,"BAW", false,-1, 31,0); - tracep->declBus(c+5190,"RESET_ADDRESS", false,-1, 4,0); - tracep->declBus(c+5113,"OPT_START_HALTED", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_MANUAL", false,-1, 0,0); - tracep->declBus(c+5076,"OPT_WATCHDOG", false,-1, 31,0); - tracep->declBus(c+5255,"DEF_CKCOUNT", false,-1, 11,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4539,"i_wb_cyc", false,-1); - tracep->declBit(c+4596,"i_wb_stb", false,-1); - tracep->declBit(c+4541,"i_wb_we", false,-1); - tracep->declBus(c+4597,"i_wb_addr", false,-1, 1,0); - tracep->declBus(c+4543,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4544,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+2624,"o_wb_ack", false,-1); - tracep->declBus(c+2625,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+2626,"o_pf_cyc", false,-1); - tracep->declBit(c+2627,"o_pf_stb", false,-1); - tracep->declBit(c+5074,"o_pf_we", false,-1); - tracep->declBus(c+2628,"o_pf_addr", false,-1, 4,0); - tracep->declBus(c+5112,"o_pf_data", false,-1, 7,0); - tracep->declBus(c+5070,"o_pf_sel", false,-1, 0,0); - tracep->declBit(c+5074,"i_pf_stall", false,-1); - tracep->declBit(c+2630,"i_pf_ack", false,-1); - tracep->declBit(c+5074,"i_pf_err", false,-1); - tracep->declBus(c+2629,"i_pf_data", false,-1, 7,0); - tracep->declBit(c+4959,"i_i2c_sda", false,-1); - tracep->declBit(c+4960,"i_i2c_scl", false,-1); - tracep->declBit(c+4961,"o_i2c_sda", false,-1); - tracep->declBit(c+4962,"o_i2c_scl", false,-1); - tracep->declBit(c+2631,"M_AXIS_TVALID", false,-1); - tracep->declBit(c+5077,"M_AXIS_TREADY", false,-1); - tracep->declBus(c+2633,"M_AXIS_TDATA", false,-1, 7,0); - tracep->declBit(c+2632,"M_AXIS_TLAST", false,-1); - tracep->declBus(c+5074,"M_AXIS_TID", false,-1, 0,0); - tracep->declBit(c+2634,"i_sync_signal", false,-1); - tracep->declBus(c+5009,"o_debug", false,-1, 31,0); - tracep->declBus(c+5116,"ADR_CONTROL", false,-1, 1,0); - tracep->declBus(c+5117,"ADR_OVERRIDE", false,-1, 1,0); - tracep->declBus(c+5118,"ADR_ADDRESS", false,-1, 1,0); - tracep->declBus(c+5119,"ADR_CKCOUNT", false,-1, 1,0); - tracep->declBus(c+5073,"HALT_BIT", false,-1, 31,0); - tracep->declBus(c+5110,"ERR_BIT", false,-1, 31,0); - tracep->declBus(c+5121,"ABORT_BIT", false,-1, 31,0); - tracep->declBus(c+5068,"SOFTHALT_BIT", false,-1, 31,0); - tracep->declBus(c+5156,"OVW_VALID", false,-1, 31,0); - tracep->declBus(c+5157,"MANUAL_BIT", false,-1, 31,0); - tracep->declBus(c+5122,"CMD_NOOP", false,-1, 3,0); - tracep->declBus(c+5124,"CMD_STOP", false,-1, 3,0); - tracep->declBus(c+5125,"CMD_SEND", false,-1, 3,0); - tracep->declBus(c+5126,"CMD_RXK", false,-1, 3,0); - tracep->declBus(c+5127,"CMD_RXN", false,-1, 3,0); - tracep->declBus(c+5115,"CMD_RXLK", false,-1, 3,0); - tracep->declBus(c+5128,"CMD_RXLN", false,-1, 3,0); - tracep->declBus(c+5129,"CMD_WAIT", false,-1, 3,0); - tracep->declBus(c+5202,"CMD_HALT", false,-1, 3,0); - tracep->declBus(c+5203,"CMD_ABORT", false,-1, 3,0); - tracep->declBus(c+5204,"CMD_TARGET", false,-1, 3,0); - tracep->declBus(c+5205,"CMD_JUMP", false,-1, 3,0); - tracep->declBus(c+5206,"CMD_CHANNEL", false,-1, 3,0); - tracep->declBit(c+2640,"cpu_reset", false,-1); - tracep->declBit(c+5074,"cpu_clear_cache", false,-1); - tracep->declBit(c+2641,"cpu_new_pc", false,-1); - tracep->declBus(c+2642,"pf_jump_addr", false,-1, 4,0); - tracep->declBit(c+2643,"pf_valid", false,-1); - tracep->declBit(c+2644,"pf_ready", false,-1); - tracep->declBus(c+2645,"pf_insn", false,-1, 7,0); - tracep->declBus(c+2646,"pf_insn_addr", false,-1, 4,0); - tracep->declBit(c+2647,"pf_illegal", false,-1); - tracep->declBit(c+2648,"half_valid", false,-1); - tracep->declBit(c+2649,"imm_cycle", false,-1); - tracep->declBit(c+4598,"next_valid", false,-1); - tracep->declBus(c+4599,"next_insn", false,-1, 7,0); - tracep->declBit(c+2650,"insn_ready", false,-1); - tracep->declBit(c+2651,"half_ready", false,-1); - tracep->declBit(c+2652,"i2c_abort", false,-1); - tracep->declBit(c+2653,"insn_valid", false,-1); - tracep->declBus(c+2654,"insn", false,-1, 11,0); - tracep->declBus(c+2655,"half_insn", false,-1, 3,0); - tracep->declBit(c+2656,"i2c_ckedge", false,-1); - tracep->declBit(c+2657,"i2c_stretch", false,-1); - tracep->declBus(c+2658,"i2c_ckcount", false,-1, 11,0); - tracep->declBus(c+2659,"ckcount", false,-1, 11,0); - tracep->declBus(c+2660,"abort_address", false,-1, 4,0); - tracep->declBus(c+2661,"jump_target", false,-1, 4,0); - tracep->declBit(c+2662,"r_wait", false,-1); - tracep->declBit(c+2663,"soft_halt_request", false,-1); - tracep->declBit(c+2640,"r_halted", false,-1); - tracep->declBit(c+2664,"r_err", false,-1); - tracep->declBit(c+2665,"r_aborted", false,-1); - tracep->declBit(c+2666,"r_manual", false,-1); - tracep->declBit(c+2667,"r_sda", false,-1); - tracep->declBit(c+2668,"r_scl", false,-1); - tracep->declBit(c+2669,"w_stopped", false,-1); - tracep->declBit(c+2670,"w_sda", false,-1); - tracep->declBit(c+2671,"w_scl", false,-1); - tracep->declBit(c+4600,"bus_read", false,-1); - tracep->declBit(c+4601,"bus_write", false,-1); - tracep->declBit(c+4602,"bus_override", false,-1); - tracep->declBit(c+4603,"bus_manual", false,-1); - tracep->declBit(c+2672,"ovw_ready", false,-1); - tracep->declBit(c+4604,"bus_jump", false,-1); - tracep->declBus(c+4597,"bus_write_addr", false,-1, 1,0); - tracep->declBus(c+4597,"bus_read_addr", false,-1, 1,0); - tracep->declBus(c+4543,"bus_write_data", false,-1, 31,0); - tracep->declBus(c+4544,"bus_write_strb", false,-1, 3,0); - tracep->declBus(c+2625,"bus_read_data", false,-1, 31,0); - tracep->declBit(c+2673,"s_tvalid", false,-1); - tracep->declBit(c+2651,"s_tready", false,-1); - tracep->declBus(c+2674,"ovw_data", false,-1, 9,0); - tracep->declBus(c+5027,"w_control", false,-1, 31,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_MANUAL "); - tracep->declBit(c+2666,"manual", false,-1); - tracep->declBit(c+2668,"scl", false,-1); - tracep->declBit(c+2667,"sda", false,-1); - tracep->declBit(c+2675,"o_scl", false,-1); - tracep->declBit(c+2676,"o_sda", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_axisi2c "); - tracep->declBus(c+5076,"OPT_WATCHDOG", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"S_AXI_ACLK", false,-1); - tracep->declBit(c+74,"S_AXI_ARESETN", false,-1); - tracep->declBit(c+2673,"S_AXIS_TVALID", false,-1); - tracep->declBit(c+2650,"S_AXIS_TREADY", false,-1); - tracep->declBus(c+2677,"S_AXIS_TDATA", false,-1, 10,0); - tracep->declBit(c+2631,"M_AXIS_TVALID", false,-1); - tracep->declBit(c+5077,"M_AXIS_TREADY", false,-1); - tracep->declBus(c+2633,"M_AXIS_TDATA", false,-1, 7,0); - tracep->declBit(c+2632,"M_AXIS_TLAST", false,-1); - tracep->declBit(c+2656,"i_ckedge", false,-1); - tracep->declBit(c+2657,"o_stretch", false,-1); - tracep->declBit(c+4960,"i_scl", false,-1); - tracep->declBit(c+4959,"i_sda", false,-1); - tracep->declBit(c+2671,"o_scl", false,-1); - tracep->declBit(c+2670,"o_sda", false,-1); - tracep->declBit(c+2652,"o_abort", false,-1); - tracep->declBus(c+5122,"IDLE_STOPPED", false,-1, 3,0); - tracep->declBus(c+5123,"START", false,-1, 3,0); - tracep->declBus(c+5124,"IDLE_ACTIVE", false,-1, 3,0); - tracep->declBus(c+5125,"STOP", false,-1, 3,0); - tracep->declBus(c+5126,"DATA", false,-1, 3,0); - tracep->declBus(c+5127,"CLOCK", false,-1, 3,0); - tracep->declBus(c+5115,"ACK", false,-1, 3,0); - tracep->declBus(c+5128,"CKACKLO", false,-1, 3,0); - tracep->declBus(c+5129,"CKACKHI", false,-1, 3,0); - tracep->declBus(c+5202,"RXNAK", false,-1, 3,0); - tracep->declBus(c+5203,"ABORT", false,-1, 3,0); - tracep->declBus(c+5204,"REPEAT_START", false,-1, 3,0); - tracep->declBus(c+5205,"REPEAT_START2", false,-1, 3,0); - tracep->declBus(c+5113,"D_RD", false,-1, 0,0); - tracep->declBus(c+5070,"D_WR", false,-1, 0,0); - tracep->declBus(c+5159,"CMD_NOOP", false,-1, 2,0); - tracep->declBus(c+5166,"CMD_START", false,-1, 2,0); - tracep->declBus(c+5160,"CMD_STOP", false,-1, 2,0); - tracep->declBus(c+5162,"CMD_SEND", false,-1, 2,0); - tracep->declBus(c+5207,"CMD_RXK", false,-1, 2,0); - tracep->declBus(c+5208,"CMD_RXN", false,-1, 2,0); - tracep->declBus(c+5209,"CMD_RXLK", false,-1, 2,0); - tracep->declBus(c+5210,"CMD_RXLN", false,-1, 2,0); - tracep->declBus(c+5113,"OPT_ABORT_REQUEST", false,-1, 0,0); - tracep->declBit(c+2678,"last_byte", false,-1); - tracep->declBit(c+2679,"dir", false,-1); - tracep->declBit(c+2680,"will_ack", false,-1); - tracep->declBus(c+2681,"state", false,-1, 3,0); - tracep->declBus(c+2682,"nbits", false,-1, 2,0); - tracep->declBus(c+2683,"sreg", false,-1, 7,0); - tracep->declBit(c+2684,"q_scl", false,-1); - tracep->declBit(c+2685,"q_sda", false,-1); - tracep->declBit(c+2686,"ck_scl", false,-1); - tracep->declBit(c+2687,"ck_sda", false,-1); - tracep->declBit(c+2688,"lst_scl", false,-1); - tracep->declBit(c+2689,"lst_sda", false,-1); - tracep->declBit(c+2690,"stop_bit", false,-1); - tracep->declBit(c+2691,"channel_busy", false,-1); - tracep->declBit(c+5074,"watchdog_timeout", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_fetch "); - tracep->declBus(c+5154,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5063,"INSN_WIDTH", false,-1, 31,0); - tracep->declBus(c+5063,"DATA_WIDTH", false,-1, 31,0); - tracep->declBus(c+5154,"AW", false,-1, 31,0); - tracep->declBus(c+5063,"DW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+75,"i_reset", false,-1); - tracep->declBit(c+2641,"i_new_pc", false,-1); - tracep->declBit(c+5074,"i_clear_cache", false,-1); - tracep->declBit(c+2644,"i_ready", false,-1); - tracep->declBus(c+2642,"i_pc", false,-1, 4,0); - tracep->declBit(c+2643,"o_valid", false,-1); - tracep->declBit(c+2647,"o_illegal", false,-1); - tracep->declBus(c+2645,"o_insn", false,-1, 7,0); - tracep->declBus(c+2646,"o_pc", false,-1, 4,0); - tracep->declBit(c+2626,"o_wb_cyc", false,-1); - tracep->declBit(c+2627,"o_wb_stb", false,-1); - tracep->declBit(c+5074,"o_wb_we", false,-1); - tracep->declBus(c+2628,"o_wb_addr", false,-1, 4,0); - tracep->declBus(c+5112,"o_wb_data", false,-1, 7,0); - tracep->declBit(c+5074,"i_wb_stall", false,-1); - tracep->declBit(c+2630,"i_wb_ack", false,-1); - tracep->declBit(c+5074,"i_wb_err", false,-1); - tracep->declBus(c+2629,"i_wb_data", false,-1, 7,0); - tracep->declBit(c+2692,"last_stb", false,-1); - tracep->declBit(c+2693,"invalid_bus_cycle", false,-1); - tracep->declBus(c+2694,"cache_word", false,-1, 7,0); - tracep->declBit(c+2695,"cache_valid", false,-1); - tracep->declBus(c+2696,"inflight", false,-1, 1,0); - tracep->declBit(c+2697,"cache_illegal", false,-1); - tracep->declBit(c+5074,"r_valid", false,-1); - tracep->declBus(c+5112,"r_insn", false,-1, 7,0); - tracep->declBus(c+2629,"i_wb_shifted", false,-1, 7,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("u_i2cdma "); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declBus(c+5063,"SW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4521,"i_wb_cyc", false,-1); - tracep->declBit(c+4522,"i_wb_stb", false,-1); - tracep->declBit(c+4523,"i_wb_we", false,-1); - tracep->declBus(c+4605,"i_wb_addr", false,-1, 1,0); - tracep->declBus(c+4525,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4526,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+397,"o_wb_ack", false,-1); - tracep->declBus(c+398,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+2698,"S_VALID", false,-1); - tracep->declBit(c+173,"S_READY", false,-1); - tracep->declBus(c+177,"S_DATA", false,-1, 7,0); - tracep->declBit(c+176,"S_LAST", false,-1); - tracep->declBit(c+199,"o_dma_cyc", false,-1); - tracep->declBit(c+200,"o_dma_stb", false,-1); - tracep->declBit(c+5077,"o_dma_we", false,-1); - tracep->declBus(c+201,"o_dma_addr", false,-1, 21,0); - tracep->declArray(c+202,"o_dma_data", false,-1, 511,0); - tracep->declQuad(c+218,"o_dma_sel", false,-1, 63,0); - tracep->declBit(c+220,"i_dma_stall", false,-1); - tracep->declBit(c+221,"i_dma_ack", false,-1); - tracep->declArray(c+223,"i_dma_data", false,-1, 511,0); - tracep->declBit(c+222,"i_dma_err", false,-1); - tracep->declBus(c+5076,"SUBLSB", false,-1, 31,0); - tracep->declBus(c+5153,"WBLSB", false,-1, 31,0); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+2699,"r_baseaddr", false,-1, 27,0); - tracep->declBus(c+2700,"r_memlen", false,-1, 27,0); - tracep->declBus(c+2701,"subaddr", false,-1, 5,0); - tracep->declBus(c+2702,"current_addr", false,-1, 27,0); - tracep->declBus(c+4606,"next_baseaddr", false,-1, 31,0); - tracep->declBus(c+4607,"next_memlen", false,-1, 31,0); - tracep->declBit(c+2703,"wb_last", false,-1); - tracep->declBit(c+2704,"bus_err", false,-1); - tracep->declBit(c+2705,"r_reset", false,-1); - tracep->declBit(c+2706,"r_overflow", false,-1); - tracep->declBit(c+2707,"skd_valid", false,-1); - tracep->declBit(c+2708,"skd_ready", false,-1); - tracep->declBit(c+2709,"skd_last", false,-1); - tracep->declBus(c+2710,"skd_data", false,-1, 7,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("sskd "); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_OUTREG", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_PASSTHROUGH", false,-1, 0,0); - tracep->declBus(c+5156,"DW", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_INITIAL", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+2698,"i_valid", false,-1); - tracep->declBit(c+173,"o_ready", false,-1); - tracep->declBus(c+2711,"i_data", false,-1, 8,0); - tracep->declBit(c+2707,"o_valid", false,-1); - tracep->declBit(c+2708,"i_ready", false,-1); - tracep->declBus(c+2712,"o_data", false,-1, 8,0); - tracep->declBus(c+2713,"w_data", false,-1, 8,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("LOGIC "); - tracep->declBit(c+2714,"r_valid", false,-1); - tracep->declBus(c+2713,"r_data", false,-1, 8,0); - tracep->pushNamePrefix("REG_OUTPUT "); - tracep->declBit(c+2707,"ro_valid", false,-1); - tracep->popNamePrefix(4); - tracep->pushNamePrefix("u_sdcard "); - tracep->declBus(c+5158,"LGFIFO", false,-1, 31,0); - tracep->declBus(c+5065,"NUMIO", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DDR", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_CARD_DETECT", false,-1, 0,0); - tracep->declBus(c+5133,"LGTIMEOUT", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+5074,"i_hsclk", false,-1); - tracep->declBit(c+4545,"i_wb_cyc", false,-1); - tracep->declBit(c+4546,"i_wb_stb", false,-1); - tracep->declBit(c+4547,"i_wb_we", false,-1); - tracep->declBus(c+4608,"i_wb_addr", false,-1, 2,0); - tracep->declBus(c+4549,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4550,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+405,"o_wb_ack", false,-1); - tracep->declBus(c+406,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+4979,"o_ck", false,-1); - tracep->declBit(c+4980,"i_ds", false,-1); - tracep->declBit(c+4981,"io_cmd_tristate", false,-1); - tracep->declBit(c+4982,"o_cmd", false,-1); - tracep->declBit(c+4983,"i_cmd", false,-1); - tracep->declBus(c+4984,"io_dat_tristate", false,-1, 3,0); - tracep->declBus(c+4985,"o_dat", false,-1, 3,0); - tracep->declBus(c+4986,"i_dat", false,-1, 3,0); - tracep->declBit(c+4987,"i_card_detect", false,-1); - tracep->declBit(c+5074,"o_1p8v", false,-1); - tracep->declBit(c+161,"o_int", false,-1); - tracep->declBus(c+179,"o_debug", false,-1, 31,0); - tracep->declBit(c+2715,"cfg_ddr", false,-1); - tracep->declBus(c+2716,"cfg_sample_shift", false,-1, 4,0); - tracep->declBus(c+2717,"sdclk", false,-1, 7,0); - tracep->declBit(c+2718,"cmd_en", false,-1); - tracep->declBit(c+2719,"pp_cmd", false,-1); - tracep->declBus(c+2720,"cmd_data", false,-1, 1,0); - tracep->declBit(c+2721,"data_en", false,-1); - tracep->declBit(c+2722,"pp_data", false,-1); - tracep->declBit(c+2723,"rx_en", false,-1); - tracep->declBus(c+2724,"tx_data", false,-1, 31,0); - tracep->declBit(c+2725,"afifo_reset_n", false,-1); - tracep->declBus(c+2726,"rply_strb", false,-1, 1,0); - tracep->declBus(c+2727,"rply_data", false,-1, 1,0); - tracep->declBit(c+2728,"card_busy", false,-1); - tracep->declBus(c+2729,"rx_strb", false,-1, 1,0); - tracep->declBus(c+2730,"rx_data", false,-1, 15,0); - tracep->declBit(c+5074,"AC_VALID", false,-1); - tracep->declBus(c+5116,"AC_DATA", false,-1, 1,0); - tracep->declBit(c+5074,"AD_VALID", false,-1); - tracep->declBus(c+5076,"AD_DATA", false,-1, 31,0); - tracep->pushNamePrefix("u_sdfrontend "); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DDR", false,-1, 0,0); - tracep->declBus(c+5065,"NUMIO", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5074,"i_hsclk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+2715,"i_cfg_ddr", false,-1); - tracep->declBus(c+2716,"i_sample_shift", false,-1, 4,0); - tracep->declBus(c+2717,"i_sdclk", false,-1, 7,0); - tracep->declBit(c+2718,"i_cmd_en", false,-1); - tracep->declBit(c+2719,"i_pp_cmd", false,-1); - tracep->declBus(c+2720,"i_cmd_data", false,-1, 1,0); - tracep->declBit(c+2721,"i_data_en", false,-1); - tracep->declBit(c+2723,"i_rx_en", false,-1); - tracep->declBit(c+2722,"i_pp_data", false,-1); - tracep->declBus(c+2724,"i_tx_data", false,-1, 31,0); - tracep->declBit(c+2725,"i_afifo_reset_n", false,-1); - tracep->declBit(c+2728,"o_data_busy", false,-1); - tracep->declBus(c+2726,"o_cmd_strb", false,-1, 1,0); - tracep->declBus(c+2727,"o_cmd_data", false,-1, 1,0); - tracep->declBus(c+2729,"o_rx_strb", false,-1, 1,0); - tracep->declBus(c+2730,"o_rx_data", false,-1, 15,0); - tracep->declBit(c+5074,"MAC_VALID", false,-1); - tracep->declBus(c+5116,"MAC_DATA", false,-1, 1,0); - tracep->declBit(c+5074,"MAD_VALID", false,-1); - tracep->declBus(c+5076,"MAD_DATA", false,-1, 31,0); - tracep->declBit(c+4979,"o_ck", false,-1); - tracep->declBit(c+4980,"i_ds", false,-1); - tracep->declBit(c+4981,"io_cmd_tristate", false,-1); - tracep->declBit(c+4982,"o_cmd", false,-1); - tracep->declBit(c+4983,"i_cmd", false,-1); - tracep->declBus(c+4984,"io_dat_tristate", false,-1, 3,0); - tracep->declBus(c+4985,"o_dat", false,-1, 3,0); - tracep->declBus(c+4986,"i_dat", false,-1, 3,0); - tracep->declBus(c+179,"o_debug", false,-1, 31,0); - tracep->declBit(c+2728,"dat0_busy", false,-1); - tracep->declBit(c+2731,"wait_for_busy", false,-1); - tracep->pushNamePrefix("GEN_IODDR_IO "); - tracep->declBus(c+2732,"w_cmd", false,-1, 1,0); - for (int i = 0; i < 16; ++i) { - tracep->declBit(c+2733+i*1,"pre_dat", true,(i+0)); - } - tracep->declBus(c+2749,"w_dat", false,-1, 15,0); - tracep->declBus(c+2750,"next_pedge", false,-1, 1,0); - tracep->declBus(c+2751,"next_dedge", false,-1, 1,0); - tracep->declBus(c+2752,"ck_sreg", false,-1, 5,0); - tracep->declBus(c+2753,"pck_sreg", false,-1, 5,0); - tracep->declBus(c+2754,"sample_ck", false,-1, 1,0); - tracep->declBus(c+2755,"cmd_sample_ck", false,-1, 1,0); - tracep->declBit(c+2756,"resp_started", false,-1); - tracep->declBit(c+2757,"io_started", false,-1); - tracep->declBit(c+2758,"last_ck", false,-1); - tracep->declBit(c+2759,"r_cmd_strb", false,-1); - tracep->declBit(c+2760,"r_cmd_data", false,-1); - tracep->declBit(c+2761,"r_rx_strb", false,-1); - tracep->declBus(c+2762,"r_rx_data", false,-1, 7,0); - tracep->declBit(c+2763,"io_clk_tristate", false,-1); - tracep->declBit(c+4979,"ign_clk", false,-1); - tracep->declBus(c+5250,"ipre", false,-1, 31,0); - tracep->declBus(c+2764,"w_out", false,-1, 7,0); - tracep->declBit(c+5074,"unused_ddr", false,-1); - tracep->pushNamePrefix("DRIVE_DDR_IO[0] "); - tracep->declBit(c+5028,"enable", false,-1); - tracep->pushNamePrefix("u_dat_ddr "); - tracep->declBus(c+5070,"OPT_BIDIR", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5028,"i_en", false,-1); - tracep->declBus(c+5029,"i_data", false,-1, 1,0); - tracep->declBit(c+2765,"io_pin_tristate", false,-1); - tracep->declBit(c+5030,"i_pin", false,-1); - tracep->declBit(c+76,"o_pin", false,-1); - tracep->declBus(c+2766,"o_wide", false,-1, 1,0); - tracep->declBit(c+77,"w_in", false,-1); - tracep->declBit(c+76,"w_out", false,-1); - tracep->declBit(c+2765,"high_z", false,-1); - tracep->declBus(c+2767,"r_out", false,-1, 1,0); - tracep->pushNamePrefix("GEN_BIDIRECTIONAL "); - tracep->declBit(c+2768,"r_p", false,-1); - tracep->declBit(c+4414,"r_n", false,-1); - tracep->declBus(c+2766,"r_in", false,-1, 1,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DRIVE_DDR_IO[1] "); - tracep->declBit(c+5031,"enable", false,-1); - tracep->pushNamePrefix("u_dat_ddr "); - tracep->declBus(c+5070,"OPT_BIDIR", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5031,"i_en", false,-1); - tracep->declBus(c+5032,"i_data", false,-1, 1,0); - tracep->declBit(c+2769,"io_pin_tristate", false,-1); - tracep->declBit(c+5033,"i_pin", false,-1); - tracep->declBit(c+78,"o_pin", false,-1); - tracep->declBus(c+2770,"o_wide", false,-1, 1,0); - tracep->declBit(c+79,"w_in", false,-1); - tracep->declBit(c+78,"w_out", false,-1); - tracep->declBit(c+2769,"high_z", false,-1); - tracep->declBus(c+2771,"r_out", false,-1, 1,0); - tracep->pushNamePrefix("GEN_BIDIRECTIONAL "); - tracep->declBit(c+2772,"r_p", false,-1); - tracep->declBit(c+4415,"r_n", false,-1); - tracep->declBus(c+2770,"r_in", false,-1, 1,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DRIVE_DDR_IO[2] "); - tracep->declBit(c+5034,"enable", false,-1); - tracep->pushNamePrefix("u_dat_ddr "); - tracep->declBus(c+5070,"OPT_BIDIR", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5034,"i_en", false,-1); - tracep->declBus(c+5035,"i_data", false,-1, 1,0); - tracep->declBit(c+2773,"io_pin_tristate", false,-1); - tracep->declBit(c+5036,"i_pin", false,-1); - tracep->declBit(c+80,"o_pin", false,-1); - tracep->declBus(c+2774,"o_wide", false,-1, 1,0); - tracep->declBit(c+81,"w_in", false,-1); - tracep->declBit(c+80,"w_out", false,-1); - tracep->declBit(c+2773,"high_z", false,-1); - tracep->declBus(c+2775,"r_out", false,-1, 1,0); - tracep->pushNamePrefix("GEN_BIDIRECTIONAL "); - tracep->declBit(c+2776,"r_p", false,-1); - tracep->declBit(c+4416,"r_n", false,-1); - tracep->declBus(c+2774,"r_in", false,-1, 1,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DRIVE_DDR_IO[3] "); - tracep->declBit(c+5037,"enable", false,-1); - tracep->pushNamePrefix("u_dat_ddr "); - tracep->declBus(c+5070,"OPT_BIDIR", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5037,"i_en", false,-1); - tracep->declBus(c+5038,"i_data", false,-1, 1,0); - tracep->declBit(c+2777,"io_pin_tristate", false,-1); - tracep->declBit(c+5039,"i_pin", false,-1); - tracep->declBit(c+82,"o_pin", false,-1); - tracep->declBus(c+2778,"o_wide", false,-1, 1,0); - tracep->declBit(c+83,"w_in", false,-1); - tracep->declBit(c+82,"w_out", false,-1); - tracep->declBit(c+2777,"high_z", false,-1); - tracep->declBus(c+2779,"r_out", false,-1, 1,0); - tracep->pushNamePrefix("GEN_BIDIRECTIONAL "); - tracep->declBit(c+2780,"r_p", false,-1); - tracep->declBit(c+4417,"r_n", false,-1); - tracep->declBus(c+2778,"r_in", false,-1, 1,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("u_clk_oddr "); - tracep->declBus(c+5113,"OPT_BIDIR", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5077,"i_en", false,-1); - tracep->declBus(c+2781,"i_data", false,-1, 1,0); - tracep->declBit(c+2763,"io_pin_tristate", false,-1); - tracep->declBit(c+4979,"i_pin", false,-1); - tracep->declBit(c+4979,"o_pin", false,-1); - tracep->declBus(c+5119,"o_wide", false,-1, 1,0); - tracep->declBit(c+4979,"w_in", false,-1); - tracep->declBit(c+4979,"w_out", false,-1); - tracep->declBit(c+2763,"high_z", false,-1); - tracep->declBus(c+2782,"r_out", false,-1, 1,0); - tracep->pushNamePrefix("GEN_OUTPUT "); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_cmd_ddr "); - tracep->declBus(c+5070,"OPT_BIDIR", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+5040,"i_en", false,-1); - tracep->declBus(c+5041,"i_data", false,-1, 1,0); - tracep->declBit(c+4981,"io_pin_tristate", false,-1); - tracep->declBit(c+4983,"i_pin", false,-1); - tracep->declBit(c+4982,"o_pin", false,-1); - tracep->declBus(c+2732,"o_wide", false,-1, 1,0); - tracep->declBit(c+84,"w_in", false,-1); - tracep->declBit(c+4982,"w_out", false,-1); - tracep->declBit(c+2783,"high_z", false,-1); - tracep->declBus(c+2784,"r_out", false,-1, 1,0); - tracep->pushNamePrefix("GEN_BIDIRECTIONAL "); - tracep->declBit(c+2785,"r_p", false,-1); - tracep->declBit(c+4418,"r_n", false,-1); - tracep->declBus(c+2732,"r_in", false,-1, 1,0); - tracep->popNamePrefix(4); - tracep->pushNamePrefix("u_sdio "); - tracep->declBus(c+5158,"LGFIFO", false,-1, 31,0); - tracep->declBus(c+5065,"NUMIO", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DDR", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_CARD_DETECT", false,-1, 0,0); - tracep->declBus(c+5133,"LGTIMEOUT", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4545,"i_wb_cyc", false,-1); - tracep->declBit(c+4546,"i_wb_stb", false,-1); - tracep->declBit(c+4547,"i_wb_we", false,-1); - tracep->declBus(c+4608,"i_wb_addr", false,-1, 2,0); - tracep->declBus(c+4549,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4550,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+405,"o_wb_ack", false,-1); - tracep->declBus(c+406,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+4987,"i_card_detect", false,-1); - tracep->declBit(c+5074,"o_1p8v", false,-1); - tracep->declBit(c+161,"o_int", false,-1); - tracep->declBit(c+2715,"o_cfg_ddr", false,-1); - tracep->declBus(c+2716,"o_cfg_sample_shift", false,-1, 4,0); - tracep->declBus(c+2717,"o_sdclk", false,-1, 7,0); - tracep->declBit(c+2718,"o_cmd_en", false,-1); - tracep->declBit(c+2719,"o_pp_cmd", false,-1); - tracep->declBus(c+2720,"o_cmd_data", false,-1, 1,0); - tracep->declBit(c+2721,"o_data_en", false,-1); - tracep->declBit(c+2722,"o_pp_data", false,-1); - tracep->declBit(c+2723,"o_rx_en", false,-1); - tracep->declBus(c+2724,"o_tx_data", false,-1, 31,0); - tracep->declBit(c+2725,"o_afifo_reset_n", false,-1); - tracep->declBus(c+2726,"i_cmd_strb", false,-1, 1,0); - tracep->declBus(c+2727,"i_cmd_data", false,-1, 1,0); - tracep->declBit(c+2728,"i_card_busy", false,-1); - tracep->declBus(c+2729,"i_rx_strb", false,-1, 1,0); - tracep->declBus(c+2730,"i_rx_data", false,-1, 15,0); - tracep->declBit(c+5074,"S_AC_VALID", false,-1); - tracep->declBus(c+5116,"S_AC_DATA", false,-1, 1,0); - tracep->declBit(c+5074,"S_AD_VALID", false,-1); - tracep->declBus(c+5076,"S_AD_DATA", false,-1, 31,0); - tracep->declBit(c+2786,"soft_reset", false,-1); - tracep->declBit(c+2787,"cfg_clk90", false,-1); - tracep->declBit(c+2788,"cfg_clk_shutdown", false,-1); - tracep->declBit(c+2789,"cfg_ds", false,-1); - tracep->declBus(c+2790,"cfg_ckspeed", false,-1, 7,0); - tracep->declBus(c+2791,"cfg_width", false,-1, 1,0); - tracep->declBit(c+2792,"clk_stb", false,-1); - tracep->declBit(c+2793,"clk_half", false,-1); - tracep->declBus(c+2794,"w_sdclk", false,-1, 7,0); - tracep->declBus(c+2795,"clk_ckspd", false,-1, 7,0); - tracep->declBit(c+2796,"cmd_request", false,-1); - tracep->declBit(c+2797,"cmd_err", false,-1); - tracep->declBit(c+2798,"cmd_busy", false,-1); - tracep->declBit(c+2799,"cmd_done", false,-1); - tracep->declBus(c+2800,"cmd_type", false,-1, 1,0); - tracep->declBus(c+2801,"cmd_ercode", false,-1, 1,0); - tracep->declBit(c+2802,"rsp_stb", false,-1); - tracep->declBus(c+2803,"cmd_id", false,-1, 6,0); - tracep->declBus(c+2804,"rsp_id", false,-1, 5,0); - tracep->declBus(c+2805,"cmd_arg", false,-1, 31,0); - tracep->declBus(c+2806,"rsp_arg", false,-1, 31,0); - tracep->declBit(c+2807,"cmd_mem_valid", false,-1); - tracep->declBus(c+5108,"cmd_mem_strb", false,-1, 3,0); - tracep->declBus(c+2808,"cmd_mem_addr", false,-1, 9,0); - tracep->declBus(c+2809,"cmd_mem_data", false,-1, 31,0); - tracep->declBit(c+2810,"tx_en", false,-1); - tracep->declBit(c+2811,"tx_mem_valid", false,-1); - tracep->declBit(c+2812,"tx_mem_ready", false,-1); - tracep->declBit(c+2813,"tx_mem_last", false,-1); - tracep->declBus(c+2814,"tx_mem_data", false,-1, 31,0); - tracep->declBit(c+5077,"crc_en", false,-1); - tracep->declBus(c+2815,"rx_length", false,-1, 12,0); - tracep->declBit(c+2816,"rx_mem_valid", false,-1); - tracep->declBus(c+2817,"rx_mem_addr", false,-1, 9,0); - tracep->declBus(c+2818,"rx_mem_strb", false,-1, 3,0); - tracep->declBus(c+2819,"rx_mem_data", false,-1, 31,0); - tracep->declBit(c+2820,"rx_done", false,-1); - tracep->declBit(c+2821,"rx_err", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("u_clkgen "); - tracep->declBus(c+5063,"LGMAXDIV", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+2787,"i_cfg_clk90", false,-1); - tracep->declBus(c+2790,"i_cfg_ckspd", false,-1, 7,0); - tracep->declBit(c+2788,"i_cfg_shutdown", false,-1); - tracep->declBit(c+2792,"o_ckstb", false,-1); - tracep->declBit(c+2793,"o_hlfck", false,-1); - tracep->declBus(c+2794,"o_ckwide", false,-1, 7,0); - tracep->declBus(c+2795,"o_ckspd", false,-1, 7,0); - tracep->declBus(c+5061,"NCTR", false,-1, 31,0); - tracep->declBit(c+2822,"nxt_stb", false,-1); - tracep->declBit(c+2823,"nxt_clk", false,-1); - tracep->declBus(c+2824,"nxt_counter", false,-1, 9,0); - tracep->declBus(c+2825,"counter", false,-1, 9,0); - tracep->declBit(c+2826,"clk90", false,-1); - tracep->declBus(c+2827,"ckspd", false,-1, 7,0); - tracep->declBit(c+2828,"w_clk90", false,-1); - tracep->declBus(c+2829,"w_ckspd", false,-1, 7,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_control "); - tracep->declBus(c+5158,"LGFIFO", false,-1, 31,0); - tracep->declBus(c+5065,"NUMIO", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DDR", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_CARD_DETECT", false,-1, 0,0); - tracep->declBus(c+5061,"LGFIFOW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_DMA", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_1P8V", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4545,"i_wb_cyc", false,-1); - tracep->declBit(c+4546,"i_wb_stb", false,-1); - tracep->declBit(c+4547,"i_wb_we", false,-1); - tracep->declBus(c+4608,"i_wb_addr", false,-1, 2,0); - tracep->declBus(c+4549,"i_wb_data", false,-1, 31,0); - tracep->declBus(c+4550,"i_wb_sel", false,-1, 3,0); - tracep->declBit(c+5074,"o_wb_stall", false,-1); - tracep->declBit(c+405,"o_wb_ack", false,-1); - tracep->declBus(c+406,"o_wb_data", false,-1, 31,0); - tracep->declBit(c+2787,"o_cfg_clk90", false,-1); - tracep->declBus(c+2790,"o_cfg_ckspeed", false,-1, 7,0); - tracep->declBit(c+2788,"o_cfg_shutdown", false,-1); - tracep->declBus(c+2791,"o_cfg_width", false,-1, 1,0); - tracep->declBit(c+2789,"o_cfg_ds", false,-1); - tracep->declBit(c+2715,"o_cfg_ddr", false,-1); - tracep->declBit(c+2719,"o_pp_cmd", false,-1); - tracep->declBit(c+2722,"o_pp_data", false,-1); - tracep->declBus(c+2716,"o_cfg_sample_shift", false,-1, 4,0); - tracep->declBus(c+2795,"i_ckspd", false,-1, 7,0); - tracep->declBit(c+2786,"o_soft_reset", false,-1); - tracep->declBit(c+2796,"o_cmd_request", false,-1); - tracep->declBus(c+2800,"o_cmd_type", false,-1, 1,0); - tracep->declBus(c+2803,"o_cmd_id", false,-1, 6,0); - tracep->declBus(c+2805,"o_arg", false,-1, 31,0); - tracep->declBit(c+2798,"i_cmd_busy", false,-1); - tracep->declBit(c+2799,"i_cmd_done", false,-1); - tracep->declBit(c+2797,"i_cmd_err", false,-1); - tracep->declBus(c+2801,"i_cmd_ercode", false,-1, 1,0); - tracep->declBit(c+2802,"i_cmd_response", false,-1); - tracep->declBus(c+2804,"i_resp", false,-1, 5,0); - tracep->declBus(c+2806,"i_arg", false,-1, 31,0); - tracep->declBit(c+2807,"i_cmd_mem_valid", false,-1); - tracep->declBus(c+5108,"i_cmd_mem_strb", false,-1, 3,0); - tracep->declBus(c+2808,"i_cmd_mem_addr", false,-1, 9,0); - tracep->declBus(c+2809,"i_cmd_mem_data", false,-1, 31,0); - tracep->declBit(c+2810,"o_tx_en", false,-1); - tracep->declBit(c+2811,"o_tx_mem_valid", false,-1); - tracep->declBit(c+2830,"i_tx_mem_ready", false,-1); - tracep->declBus(c+2814,"o_tx_mem_data", false,-1, 31,0); - tracep->declBit(c+2813,"o_tx_mem_last", false,-1); - tracep->declBit(c+2721,"i_tx_busy", false,-1); - tracep->declBit(c+2723,"o_rx_en", false,-1); - tracep->declBit(c+5077,"o_crc_en", false,-1); - tracep->declBus(c+2815,"o_length", false,-1, 12,0); - tracep->declBit(c+2816,"i_rx_mem_valid", false,-1); - tracep->declBus(c+2818,"i_rx_mem_strb", false,-1, 3,0); - tracep->declBus(c+2817,"i_rx_mem_addr", false,-1, 9,0); - tracep->declBus(c+2819,"i_rx_mem_data", false,-1, 31,0); - tracep->declBit(c+2820,"i_rx_done", false,-1); - tracep->declBit(c+2821,"i_rx_err", false,-1); - tracep->declBit(c+4987,"i_card_detect", false,-1); - tracep->declBit(c+2728,"i_card_busy", false,-1); - tracep->declBit(c+5074,"o_1p8v", false,-1); - tracep->declBit(c+161,"o_int", false,-1); - tracep->declBus(c+5061,"LGFIFO32", false,-1, 31,0); - tracep->declBus(c+5159,"ADDR_CMD", false,-1, 2,0); - tracep->declBus(c+5166,"ADDR_ARG", false,-1, 2,0); - tracep->declBus(c+5160,"ADDR_FIFOA", false,-1, 2,0); - tracep->declBus(c+5162,"ADDR_FIFOB", false,-1, 2,0); - tracep->declBus(c+5207,"ADDR_PHY", false,-1, 2,0); - tracep->declBus(c+5117,"CMD_PREFIX", false,-1, 1,0); - tracep->declBus(c+5116,"NUL_PREFIX", false,-1, 1,0); - tracep->declBus(c+5116,"RNO_REPLY", false,-1, 1,0); - tracep->declBus(c+5118,"R2_REPLY", false,-1, 1,0); - tracep->declBus(c+5134,"CARD_REMOVED_BIT", false,-1, 31,0); - tracep->declBus(c+5136,"USE_DMA_BIT", false,-1, 31,0); - tracep->declBus(c+5158,"FIFO_ID_BIT", false,-1, 31,0); - tracep->declBus(c+5157,"USE_FIFO_BIT", false,-1, 31,0); - tracep->declBus(c+5061,"FIFO_WRITE_BIT", false,-1, 31,0); - tracep->declBus(c+5116,"WIDTH_1W", false,-1, 1,0); - tracep->declBus(c+5117,"WIDTH_4W", false,-1, 1,0); - tracep->declBus(c+5118,"WIDTH_8W", false,-1, 1,0); - tracep->declBit(c+4609,"wb_cmd_stb", false,-1); - tracep->declBit(c+4610,"wb_phy_stb", false,-1); - tracep->declBus(c+2803,"r_cmd", false,-1, 6,0); - tracep->declBit(c+2831,"r_tx_request", false,-1); - tracep->declBit(c+2832,"r_rx_request", false,-1); - tracep->declBit(c+2833,"r_tx_sent", false,-1); - tracep->declBit(c+2834,"r_fifo", false,-1); - tracep->declBit(c+2835,"r_cmd_err", false,-1); - tracep->declBus(c+2836,"r_cmd_ecode", false,-1, 1,0); - tracep->declBus(c+2805,"r_arg", false,-1, 31,0); - tracep->declBus(c+2837,"lgblk", false,-1, 3,0); - tracep->declBus(c+2791,"r_width", false,-1, 1,0); - tracep->declBus(c+2790,"r_ckspeed", false,-1, 7,0); - tracep->declBus(c+2838,"w_cmd_word", false,-1, 31,0); - tracep->declBus(c+2839,"w_phy_ctrl", false,-1, 31,0); - tracep->declBus(c+2840,"blk_words", false,-1, 15,0); - tracep->declBus(c+2841,"ika", false,-1, 31,0); - tracep->declBus(c+2842,"ikb", false,-1, 31,0); - tracep->declBus(c+5189,"NFIFOW", false,-1, 31,0); - tracep->declBus(c+2843,"tx_fifo_a", false,-1, 31,0); - tracep->declBus(c+2844,"tx_fifo_b", false,-1, 31,0); - tracep->declBus(c+5113,"tx_shift", false,-1, 0,0); - tracep->declBus(c+2845,"fif_wraddr", false,-1, 9,0); - tracep->declBus(c+2846,"fif_rdaddr", false,-1, 9,0); - tracep->declBus(c+2847,"fif_a_rdaddr", false,-1, 9,0); - tracep->declBus(c+2848,"fif_b_rdaddr", false,-1, 9,0); - tracep->declBus(c+2849,"tx_mem_addr", false,-1, 9,0); - tracep->declBus(c+2850,"next_tx_mem", false,-1, 31,0); - tracep->declBit(c+2851,"tx_fifo_last", false,-1); - tracep->declBit(c+2852,"pre_tx_last", false,-1); - tracep->declBit(c+2853,"tx_pipe_valid", false,-1); - tracep->declBit(c+2854,"card_present", false,-1); - tracep->declBit(c+2855,"card_removed", false,-1); - tracep->declBit(c+2856,"pre_ack", false,-1); - tracep->declBus(c+2857,"pre_sel", false,-1, 1,0); - tracep->declBus(c+2858,"pre_data", false,-1, 31,0); - tracep->declBus(c+2859,"mem_wr_addr_a", false,-1, 9,0); - tracep->declBus(c+2860,"mem_wr_addr_b", false,-1, 9,0); - tracep->declBus(c+2861,"mem_wr_strb_a", false,-1, 3,0); - tracep->declBus(c+2862,"mem_wr_strb_b", false,-1, 3,0); - tracep->declBus(c+2863,"mem_wr_data_a", false,-1, 31,0); - tracep->declBus(c+2864,"mem_wr_data_b", false,-1, 31,0); - tracep->declBit(c+2865,"cmd_busy", false,-1); - tracep->declBit(c+128,"new_cmd_request", false,-1); - tracep->declBit(c+129,"new_data_request", false,-1); - tracep->declBit(c+130,"new_tx_request", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("GEN_CARD_DETECT "); - tracep->declBus(c+2866,"raw_card_present", false,-1, 2,0); - tracep->declBus(c+2867,"card_detect_counter", false,-1, 9,0); - tracep->declBit(c+2855,"r_card_removed", false,-1); - tracep->declBit(c+2854,"r_card_present", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_rxframe "); - tracep->declBus(c+5158,"LGLEN", false,-1, 31,0); - tracep->declBus(c+5065,"NUMIO", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBus(c+5061,"LGLENW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_DS", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5133,"LGTIMEOUT", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+85,"i_reset", false,-1); - tracep->declBit(c+2789,"i_cfg_ds", false,-1); - tracep->declBit(c+2715,"i_cfg_ddr", false,-1); - tracep->declBus(c+2791,"i_cfg_width", false,-1, 1,0); - tracep->declBit(c+2723,"i_rx_en", false,-1); - tracep->declBit(c+5077,"i_crc_en", false,-1); - tracep->declBus(c+2815,"i_length", false,-1, 12,0); - tracep->declBus(c+2729,"i_rx_strb", false,-1, 1,0); - tracep->declBus(c+2730,"i_rx_data", false,-1, 15,0); - tracep->declBit(c+5074,"S_ASYNC_VALID", false,-1); - tracep->declBus(c+5076,"S_ASYNC_DATA", false,-1, 31,0); - tracep->declBit(c+2816,"o_mem_valid", false,-1); - tracep->declBus(c+2818,"o_mem_strb", false,-1, 3,0); - tracep->declBus(c+2817,"o_mem_addr", false,-1, 9,0); - tracep->declBus(c+2819,"o_mem_data", false,-1, 31,0); - tracep->declBit(c+2820,"o_done", false,-1); - tracep->declBit(c+2821,"o_err", false,-1); - tracep->declBus(c+5116,"WIDTH_1W", false,-1, 1,0); - tracep->declBus(c+5117,"WIDTH_4W", false,-1, 1,0); - tracep->declBus(c+5118,"WIDTH_8W", false,-1, 1,0); - tracep->declBus(c+5069,"NCRC", false,-1, 31,0); - tracep->declBus(c+5248,"CRC_POLYNOMIAL", false,-1, 15,0); - tracep->declBus(c+2868,"sync_fill", false,-1, 4,0); - tracep->declBus(c+2869,"sync_sreg", false,-1, 19,0); - tracep->declBit(c+2870,"s2_valid", false,-1); - tracep->declBus(c+2871,"s2_fill", false,-1, 1,0); - tracep->declBus(c+2872,"s2_data", false,-1, 15,0); - tracep->declBit(c+2816,"mem_valid", false,-1); - tracep->declBit(c+2873,"mem_full", false,-1); - tracep->declBit(c+2874,"rnxt_strb", false,-1); - tracep->declBus(c+2818,"mem_strb", false,-1, 3,0); - tracep->declBus(c+2819,"mem_data", false,-1, 31,0); - tracep->declBus(c+2817,"mem_addr", false,-1, 9,0); - tracep->declBus(c+2875,"subaddr", false,-1, 1,0); - tracep->declBus(c+2876,"next_subaddr", false,-1, 1,0); - tracep->declBus(c+2877,"rnxt_data", false,-1, 7,0); - tracep->declBit(c+2878,"busy", false,-1); - tracep->declBit(c+2879,"data_phase", false,-1); - tracep->declBit(c+2880,"load_crc", false,-1); - tracep->declBit(c+2881,"pending_crc", false,-1); - tracep->declBus(c+2882,"rail_count", false,-1, 15,0); - tracep->declBus(c+2883,"err", false,-1, 7,0); - tracep->declBus(c+2884,"r_timeout", false,-1, 22,0); - tracep->declBit(c+2885,"r_watchdog", false,-1); - tracep->declBit(c+2886,"last_strb", false,-1); - tracep->declBit(c+2887,"w_done", false,-1); - tracep->pushNamePrefix("GEN_RAIL_CRC[0] "); - tracep->declBus(c+2888,"pedge_crc", false,-1, 15,0); - tracep->declBus(c+2889,"nedge_crc", false,-1, 15,0); - tracep->declBus(c+2890,"lcl_err", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_RAIL_CRC[1] "); - tracep->declBus(c+2891,"pedge_crc", false,-1, 15,0); - tracep->declBus(c+2892,"nedge_crc", false,-1, 15,0); - tracep->declBus(c+2893,"lcl_err", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_RAIL_CRC[2] "); - tracep->declBus(c+2894,"pedge_crc", false,-1, 15,0); - tracep->declBus(c+2895,"nedge_crc", false,-1, 15,0); - tracep->declBus(c+2896,"lcl_err", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_RAIL_CRC[3] "); - tracep->declBus(c+2897,"pedge_crc", false,-1, 15,0); - tracep->declBus(c+2898,"nedge_crc", false,-1, 15,0); - tracep->declBus(c+2899,"lcl_err", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("u_sdcmd "); - tracep->declBus(c+5113,"OPT_DS", false,-1, 0,0); - tracep->declBus(c+5131,"LGTIMEOUT", false,-1, 31,0); - tracep->declBus(c+5061,"LGLEN", false,-1, 31,0); - tracep->declBus(c+5114,"MW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+85,"i_reset", false,-1); - tracep->declBit(c+2789,"i_cfg_ds", false,-1); - tracep->declBit(c+2900,"i_cfg_dbl", false,-1); - tracep->declBit(c+2792,"i_ckstb", false,-1); - tracep->declBit(c+2796,"i_cmd_request", false,-1); - tracep->declBus(c+2800,"i_cmd_type", false,-1, 1,0); - tracep->declBus(c+2803,"i_cmd", false,-1, 6,0); - tracep->declBus(c+2805,"i_arg", false,-1, 31,0); - tracep->declBit(c+2798,"o_busy", false,-1); - tracep->declBit(c+2799,"o_done", false,-1); - tracep->declBit(c+2797,"o_err", false,-1); - tracep->declBus(c+2801,"o_ercode", false,-1, 1,0); - tracep->declBit(c+2718,"o_cmd_en", false,-1); - tracep->declBus(c+2720,"o_cmd_data", false,-1, 1,0); - tracep->declBus(c+2726,"i_cmd_strb", false,-1, 1,0); - tracep->declBus(c+2727,"i_cmd_data", false,-1, 1,0); - tracep->declBit(c+5074,"S_ASYNC_VALID", false,-1); - tracep->declBus(c+5116,"S_ASYNC_DATA", false,-1, 1,0); - tracep->declBit(c+2802,"o_cmd_response", false,-1); - tracep->declBus(c+2804,"o_resp", false,-1, 5,0); - tracep->declBus(c+2806,"o_arg", false,-1, 31,0); - tracep->declBit(c+2807,"o_mem_valid", false,-1); - tracep->declBus(c+5108,"o_mem_strb", false,-1, 3,0); - tracep->declBus(c+2808,"o_mem_addr", false,-1, 9,0); - tracep->declBus(c+2809,"o_mem_data", false,-1, 31,0); - tracep->declBus(c+5116,"R_NONE", false,-1, 1,0); - tracep->declBus(c+5117,"R_R1", false,-1, 1,0); - tracep->declBus(c+5118,"R_R2", false,-1, 1,0); - tracep->declBus(c+5116,"ECODE_TIMEOUT", false,-1, 1,0); - tracep->declBus(c+5117,"ECODE_OKAY", false,-1, 1,0); - tracep->declBus(c+5118,"ECODE_BADCRC", false,-1, 1,0); - tracep->declBus(c+5119,"ECODE_FRAMEERR", false,-1, 1,0); - tracep->declBus(c+5249,"CRC_POLYNOMIAL", false,-1, 6,0); - tracep->declBit(c+2718,"active", false,-1); - tracep->declBus(c+2901,"srcount", false,-1, 5,0); - tracep->declQuad(c+2902,"tx_sreg", false,-1, 47,0); - tracep->declBit(c+2904,"waiting_on_response", false,-1); - tracep->declBit(c+2905,"cfg_ds", false,-1); - tracep->declBit(c+2906,"cfg_dbl", false,-1); - tracep->declBit(c+2907,"r_frame_err", false,-1); - tracep->declBus(c+2908,"cmd_type", false,-1, 1,0); - tracep->declBus(c+2909,"resp_count", false,-1, 7,0); - tracep->declBit(c+2910,"frame_err", false,-1); - tracep->declBit(c+2911,"w_done", false,-1); - tracep->declBit(c+2912,"crc_err", false,-1); - tracep->declBit(c+2913,"w_no_response", false,-1); - tracep->declBus(c+2808,"mem_addr", false,-1, 9,0); - tracep->declQuad(c+2914,"rx_sreg", false,-1, 39,0); - tracep->declBit(c+2916,"rx_timeout", false,-1); - tracep->declBus(c+2917,"rx_timeout_counter", false,-1, 25,0); - tracep->declBus(c+2918,"crc_fill", false,-1, 6,0); - tracep->declBit(c+2919,"r_busy", false,-1); - tracep->declBit(c+2920,"new_data", false,-1); - tracep->declBit(c+2921,"r_done", false,-1); - tracep->declBit(c+5074,"unused", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_txframe "); - tracep->declBus(c+5069,"NCRC", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_SERDES", false,-1, 0,0); - tracep->declBus(c+5248,"CRC_POLYNOMIAL", false,-1, 15,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+85,"i_reset", false,-1); - tracep->declBus(c+2790,"i_cfg_spd", false,-1, 7,0); - tracep->declBus(c+2791,"i_cfg_width", false,-1, 1,0); - tracep->declBit(c+2715,"i_cfg_ddr", false,-1); - tracep->declBit(c+2810,"i_en", false,-1); - tracep->declBit(c+2792,"i_ckstb", false,-1); - tracep->declBit(c+2793,"i_hlfck", false,-1); - tracep->declBit(c+2922,"S_VALID", false,-1); - tracep->declBit(c+2812,"S_READY", false,-1); - tracep->declBus(c+2814,"S_DATA", false,-1, 31,0); - tracep->declBit(c+2813,"S_LAST", false,-1); - tracep->declBit(c+2721,"tx_valid", false,-1); - tracep->declBus(c+2724,"tx_data", false,-1, 31,0); - tracep->declBus(c+5116,"P_IDLE", false,-1, 1,0); - tracep->declBus(c+5117,"P_DATA", false,-1, 1,0); - tracep->declBus(c+5118,"P_CRC", false,-1, 1,0); - tracep->declBus(c+5119,"P_LAST", false,-1, 1,0); - tracep->declBus(c+5116,"WIDTH_1W", false,-1, 1,0); - tracep->declBus(c+5117,"WIDTH_4W", false,-1, 1,0); - tracep->declBus(c+5118,"WIDTH_8W", false,-1, 1,0); - tracep->declBus(c+5116,"P_1D", false,-1, 1,0); - tracep->declBus(c+5117,"P_2D", false,-1, 1,0); - tracep->declBus(c+5118,"P_4D", false,-1, 1,0); - tracep->declBit(c+2923,"cfg_ddr", false,-1); - tracep->declBus(c+2924,"cfg_width", false,-1, 1,0); - tracep->declBus(c+2925,"cfg_period", false,-1, 1,0); - tracep->declBit(c+2926,"start_packet", false,-1); - tracep->declBit(c+2927,"pre_valid", false,-1); - tracep->declBus(c+2928,"pstate", false,-1, 1,0); - tracep->declBit(c+2929,"pre_ready", false,-1); - tracep->declBus(c+2930,"pre_data", false,-1, 31,0); - tracep->declBus(c+2931,"pre_count", false,-1, 3,0); - tracep->declBus(c+5250,"ik", false,-1, 31,0); - tracep->declBus(c+5250,"jk", false,-1, 31,0); - tracep->declBus(c+2932,"crc_1w_reg", false,-1, 15,0); - tracep->declBus(c+2933,"di_crc_2w", false,-1, 31,0); - tracep->declBus(c+2934,"nxt_crc_2w", false,-1, 31,0); - tracep->declBus(c+2935,"new_crc_2w", false,-1, 31,0); - tracep->declBus(c+2936,"crc_2w_reg", false,-1, 31,0); - tracep->declQuad(c+2937,"di_crc_4w", false,-1, 63,0); - tracep->declQuad(c+2939,"nxt_crc_4w", false,-1, 63,0); - tracep->declQuad(c+2941,"new_crc_4w", false,-1, 63,0); - tracep->declQuad(c+2943,"crc_4w_reg", false,-1, 63,0); - tracep->declArray(c+2945,"di_crc_8w", false,-1, 127,0); - tracep->declArray(c+2949,"nxt_crc_8w", false,-1, 127,0); - tracep->declArray(c+2953,"new_crc_8w", false,-1, 127,0); - tracep->declArray(c+2957,"crc_8w_reg", false,-1, 127,0); - tracep->declArray(c+2961,"di_crc_8d", false,-1, 255,0); - tracep->declArray(c+2969,"nxt_crc_8d", false,-1, 255,0); - tracep->declArray(c+2977,"new_crc_8d", false,-1, 255,0); - tracep->declArray(c+2985,"crc_8d_reg", false,-1, 255,0); - tracep->declBit(c+2721,"ck_valid", false,-1); - tracep->declBus(c+2993,"ck_counts", false,-1, 4,0); - tracep->declBus(c+2724,"ck_data", false,-1, 31,0); - tracep->declBus(c+2994,"ck_sreg", false,-1, 31,0); - tracep->declBit(c+2995,"ck_stop_bit", false,-1); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("u_wbdown "); - tracep->declBus(c+5061,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"WIDE_DW", false,-1, 31,0); - tracep->declBus(c+5114,"SMALL_DW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWLOGIC", false,-1, 0,0); - tracep->declBus(c+5065,"WIDE_AW", false,-1, 31,0); - tracep->declBus(c+5063,"SMALL_AW", false,-1, 31,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+4419,"i_wcyc", false,-1); - tracep->declBit(c+4420,"i_wstb", false,-1); - tracep->declBit(c+4421,"i_wwe", false,-1); - tracep->declBus(c+4611,"i_waddr", false,-1, 3,0); - tracep->declArray(c+4423,"i_wdata", false,-1, 511,0); - tracep->declQuad(c+4439,"i_wsel", false,-1, 63,0); - tracep->declBit(c+343,"o_wstall", false,-1); - tracep->declBit(c+344,"o_wack", false,-1); - tracep->declArray(c+345,"o_wdata", false,-1, 511,0); - tracep->declBit(c+4441,"o_werr", false,-1); - tracep->declBit(c+4486,"o_scyc", false,-1); - tracep->declBit(c+378,"o_sstb", false,-1); - tracep->declBit(c+379,"o_swe", false,-1); - tracep->declBus(c+380,"o_saddr", false,-1, 7,0); - tracep->declBus(c+381,"o_sdata", false,-1, 31,0); - tracep->declBus(c+382,"o_ssel", false,-1, 3,0); - tracep->declBit(c+383,"i_sstall", false,-1); - tracep->declBit(c+384,"i_sack", false,-1); - tracep->declBus(c+385,"i_sdata", false,-1, 31,0); - tracep->declBit(c+4487,"i_serr", false,-1); - tracep->declBus(c+5065,"WBLSB", false,-1, 31,0); - tracep->pushNamePrefix("DOWNSIZE "); - tracep->declBus(c+5154,"LGFIFO", false,-1, 31,0); - tracep->declBit(c+4486,"r_cyc", false,-1); - tracep->declBit(c+2996,"r_stb", false,-1); - tracep->declBit(c+379,"r_we", false,-1); - tracep->declBit(c+344,"r_ack", false,-1); - tracep->declBit(c+4441,"r_err", false,-1); - tracep->declBit(c+2997,"r_first", false,-1); - tracep->declBus(c+380,"r_addr", false,-1, 7,0); - tracep->declBit(c+2998,"s_null", false,-1); - tracep->declBit(c+2999,"s_last", false,-1); - tracep->declArray(c+3000,"s_data", false,-1, 511,0); - tracep->declArray(c+345,"r_data", false,-1, 511,0); - tracep->declArray(c+3016,"nxt_data", false,-1, 511,0); - tracep->declQuad(c+3032,"s_sel", false,-1, 63,0); - tracep->declQuad(c+3034,"nxt_sel", false,-1, 63,0); - tracep->declBus(c+3036,"r_shift", false,-1, 3,0); - tracep->declBus(c+3037,"fifo_addr", false,-1, 3,0); - tracep->declBus(c+4612,"i_subaddr", false,-1, 3,0); - tracep->declBit(c+3038,"fifo_full", false,-1); - tracep->declBit(c+3039,"fifo_empty", false,-1); - tracep->declBit(c+3040,"fifo_ack", false,-1); - tracep->declBus(c+3041,"ign_fifo_fill", false,-1, 5,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("DOWNSIZE "); - tracep->declBus(c+5250,"subaddr_fn__Vstatic__fnk", false,-1, 31,0); - tracep->declBus(c+4613,"subaddr_fn__Vstatic__fm", false,-1, 31,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("u_fifo "); - tracep->declBus(c+5154,"BW", false,-1, 31,0); - tracep->declBus(c+5154,"LGFLEN", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_ASYNC_READ", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_WRITE_ON_FULL", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_READ_ON_EMPTY", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+131,"i_reset", false,-1); - tracep->declBit(c+3042,"i_wr", false,-1); - tracep->declBus(c+3043,"i_data", false,-1, 4,0); - tracep->declBit(c+3038,"o_full", false,-1); - tracep->declBus(c+3041,"o_fill", false,-1, 5,0); - tracep->declBit(c+384,"i_rd", false,-1); - tracep->declBus(c+3044,"o_data", false,-1, 4,0); - tracep->declBit(c+3039,"o_empty", false,-1); - tracep->declBus(c+5114,"FLEN", false,-1, 31,0); - tracep->declBit(c+3045,"r_full", false,-1); - tracep->declBit(c+3046,"r_empty", false,-1); - for (int i = 0; i < 32; ++i) { - tracep->declBus(c+3047+i*1,"mem", true,(i+0), 4,0); - } - tracep->declBus(c+3079,"wr_addr", false,-1, 5,0); - tracep->declBus(c+3080,"rd_addr", false,-1, 5,0); - tracep->declBit(c+3081,"w_wr", false,-1); - tracep->declBit(c+3082,"w_rd", false,-1); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("wb32_xbar "); - tracep->declBus(c+5064,"NM", false,-1, 31,0); - tracep->declBus(c+5158,"NS", false,-1, 31,0); - tracep->declBus(c+5063,"AW", false,-1, 31,0); - tracep->declBus(c+5114,"DW", false,-1, 31,0); - tracep->declArray(c+5256,"SLAVE_ADDR", false,-1, 95,0); - tracep->declArray(c+5259,"SLAVE_MASK", false,-1, 95,0); - tracep->declBus(c+5153,"LGMAXBURST", false,-1, 31,0); - tracep->declBus(c+5076,"OPT_TIMEOUT", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_STARVATION_TIMEOUT", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DBLBUFFER", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBus(c+4486,"i_mcyc", false,-1, 0,0); - tracep->declBus(c+378,"i_mstb", false,-1, 0,0); - tracep->declBus(c+379,"i_mwe", false,-1, 0,0); - tracep->declBus(c+380,"i_maddr", false,-1, 7,0); - tracep->declBus(c+381,"i_mdata", false,-1, 31,0); - tracep->declBus(c+382,"i_msel", false,-1, 3,0); - tracep->declBus(c+383,"o_mstall", false,-1, 0,0); - tracep->declBus(c+384,"o_mack", false,-1, 0,0); - tracep->declBus(c+385,"o_mdata", false,-1, 31,0); - tracep->declBus(c+4487,"o_merr", false,-1, 0,0); - tracep->declBus(c+4614,"o_scyc", false,-1, 11,0); - tracep->declBus(c+4615,"o_sstb", false,-1, 11,0); - tracep->declBus(c+4616,"o_swe", false,-1, 11,0); - tracep->declArray(c+4617,"o_saddr", false,-1, 95,0); - tracep->declArray(c+4620,"o_sdata", false,-1, 383,0); - tracep->declQuad(c+4632,"o_ssel", false,-1, 47,0); - tracep->declBus(c+4413,"i_sstall", false,-1, 11,0); - tracep->declBus(c+3889,"i_sack", false,-1, 11,0); - tracep->declArray(c+3890,"i_sdata", false,-1, 383,0); - tracep->declBus(c+5262,"i_serr", false,-1, 11,0); - tracep->declBus(c+5076,"TIMEOUT_WIDTH", false,-1, 31,0); - tracep->declBus(c+5064,"LGNM", false,-1, 31,0); - tracep->declBus(c+5065,"LGNS", false,-1, 31,0); - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+4634+i*1,"request", true,(i+0), 12,0); - } - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+8+i*1,"requested", true,(i+0), 11,0); - } - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+3083+i*1,"grant", true,(i+0), 12,0); - } - tracep->declBus(c+3084,"mgrant", false,-1, 0,0); - tracep->declBus(c+4635,"sgrant", false,-1, 11,0); - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+3085+i*1,"w_mpending", true,(i+0), 5,0); - } - tracep->declBus(c+3086,"mfull", false,-1, 0,0); - tracep->declBus(c+3087,"mnearfull", false,-1, 0,0); - tracep->declBus(c+3088,"mempty", false,-1, 0,0); - tracep->declBus(c+5113,"timed_out", false,-1, 0,0); - tracep->declBus(c+5064,"NMFULL", false,-1, 31,0); - tracep->declBus(c+5069,"NSFULL", false,-1, 31,0); - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+4636+i*1,"mindex", true,(i+0), 3,0); - } - for (int i = 0; i < 16; ++i) { - tracep->declBus(c+9+i*1,"sindex", true,(i+0), 0,0); - } - tracep->declBus(c+4486,"m_cyc", false,-1, 0,0); - tracep->declBus(c+4637,"m_stb", false,-1, 0,0); - tracep->declBus(c+4638,"m_we", false,-1, 0,0); - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+4639+i*1,"m_addr", true,(i+0), 7,0); - } - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+4640+i*1,"m_data", true,(i+0), 31,0); - } - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+4641+i*1,"m_sel", true,(i+0), 3,0); - } - tracep->declBus(c+4881,"m_stall", false,-1, 0,0); - tracep->declBus(c+4882,"s_stall", false,-1, 15,0); - for (int i = 0; i < 16; ++i) { - tracep->declBus(c+3902+i*1,"s_data", true,(i+0), 31,0); - } - tracep->declBus(c+5042,"s_ack", false,-1, 15,0); - tracep->declBus(c+5263,"s_err", false,-1, 15,0); - tracep->declBus(c+4642,"dcd_stb", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_BUFFER_DECODER", false,-1, 0,0); - tracep->declBus(c+3089,"iN", false,-1, 31,0); - tracep->declBus(c+5043,"iM", false,-1, 31,0); - tracep->pushNamePrefix("ARBITRATE_REQUESTS[0] "); - tracep->declBus(c+4643,"regrant", false,-1, 12,0); - tracep->declBus(c+5044,"reindex", false,-1, 3,0); - tracep->declBit(c+4644,"stay_on_channel", false,-1); - tracep->declBit(c+4645,"requested_channel_is_available", false,-1); - tracep->pushNamePrefix("MINDEX_MULTIPLE_SLAVES "); - tracep->declBus(c+4646,"r_mindex", false,-1, 3,0); - tracep->declBus(c+4643,"r_regrant", false,-1, 12,0); - tracep->declBus(c+5044,"r_reindex", false,-1, 3,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("COUNT_PENDING_TRANSACTIONS[0] "); - tracep->declBus(c+3090,"lclpending", false,-1, 5,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("DECODE_REQUEST[0] "); - tracep->declBit(c+132,"skd_stb", false,-1); - tracep->declBit(c+4883,"skd_stall", false,-1); - tracep->declBit(c+4647,"skd_we", false,-1); - tracep->declBus(c+4648,"skd_addr", false,-1, 7,0); - tracep->declBus(c+4649,"skd_data", false,-1, 31,0); - tracep->declBus(c+4650,"skd_sel", false,-1, 3,0); - tracep->declBus(c+3091,"decoded", false,-1, 12,0); - tracep->declBit(c+3092,"iskd_ready", false,-1); - tracep->pushNamePrefix("adcd "); - tracep->declBus(c+5158,"NS", false,-1, 31,0); - tracep->declBus(c+5063,"AW", false,-1, 31,0); - tracep->declBus(c+5264,"DW", false,-1, 31,0); - tracep->declArray(c+5256,"SLAVE_ADDR", false,-1, 95,0); - tracep->declArray(c+5259,"SLAVE_MASK", false,-1, 95,0); - tracep->declBus(c+5201,"ACCESS_ALLOWED", false,-1, 11,0); - tracep->declBus(c+5070,"OPT_REGISTERED", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+133,"i_valid", false,-1); - tracep->declBit(c+4883,"o_stall", false,-1); - tracep->declBus(c+4648,"i_addr", false,-1, 7,0); - tracep->declQuad(c+4651,"i_data", false,-1, 36,0); - tracep->declBit(c+4642,"o_valid", false,-1); - tracep->declBit(c+4884,"i_stall", false,-1); - tracep->declBus(c+3091,"o_decode", false,-1, 12,0); - tracep->declBus(c+3093,"o_addr", false,-1, 7,0); - tracep->declQuad(c+4653,"o_data", false,-1, 36,0); - tracep->declBus(c+5070,"OPT_NONESEL", false,-1, 0,0); - tracep->declBus(c+134,"request", false,-1, 12,0); - tracep->declBus(c+4655,"prerequest", false,-1, 11,0); - tracep->declBus(c+25,"iM", false,-1, 31,0); - tracep->pushNamePrefix("NO_DEFAULT_REQUEST "); - tracep->declBus(c+135,"r_request", false,-1, 11,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OPT_NONESEL_REQUEST "); - tracep->declBit(c+136,"r_request_NS", false,-1); - tracep->declBit(c+137,"r_none_sel", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("iskid "); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_OUTREG", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_PASSTHROUGH", false,-1, 0,0); - tracep->declBus(c+5265,"DW", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_INITIAL", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+138,"i_reset", false,-1); - tracep->declBit(c+378,"i_valid", false,-1); - tracep->declBit(c+3092,"o_ready", false,-1); - tracep->declQuad(c+3094,"i_data", false,-1, 44,0); - tracep->declBit(c+132,"o_valid", false,-1); - tracep->declBit(c+4885,"i_ready", false,-1); - tracep->declQuad(c+4656,"o_data", false,-1, 44,0); - tracep->declQuad(c+3096,"w_data", false,-1, 44,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("LOGIC "); - tracep->declBit(c+383,"r_valid", false,-1); - tracep->declQuad(c+3096,"r_data", false,-1, 44,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DOUBLE_BUFFERRED_STALL "); - tracep->declBus(c+384,"r_mack", false,-1, 0,0); - tracep->declBus(c+4487,"r_merr", false,-1, 0,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[0] "); - tracep->declBit(c+139,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[10] "); - tracep->declBit(c+140,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[11] "); - tracep->declBit(c+141,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[1] "); - tracep->declBit(c+142,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[2] "); - tracep->declBit(c+143,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[3] "); - tracep->declBit(c+144,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[4] "); - tracep->declBit(c+145,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[5] "); - tracep->declBit(c+146,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[6] "); - tracep->declBit(c+147,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[7] "); - tracep->declBit(c+148,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[8] "); - tracep->declBit(c+149,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[9] "); - tracep->declBit(c+150,"drop_sgrant", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("wbu_arbiter_upsz "); - tracep->declBus(c+5199,"ADDRESS_WIDTH", false,-1, 31,0); - tracep->declBus(c+5111,"WIDE_DW", false,-1, 31,0); - tracep->declBus(c+5114,"SMALL_DW", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_LITTLE_ENDIAN", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+419,"i_scyc", false,-1); - tracep->declBit(c+420,"i_sstb", false,-1); - tracep->declBit(c+421,"i_swe", false,-1); - tracep->declBus(c+3098,"i_saddr", false,-1, 25,0); - tracep->declBus(c+423,"i_sdata", false,-1, 31,0); - tracep->declBus(c+424,"i_ssel", false,-1, 3,0); - tracep->declBit(c+425,"o_sstall", false,-1); - tracep->declBit(c+426,"o_sack", false,-1); - tracep->declBus(c+428,"o_sdata", false,-1, 31,0); - tracep->declBit(c+427,"o_serr", false,-1); - tracep->declBit(c+302,"o_wcyc", false,-1); - tracep->declBit(c+303,"o_wstb", false,-1); - tracep->declBit(c+304,"o_wwe", false,-1); - tracep->declBus(c+305,"o_waddr", false,-1, 21,0); - tracep->declArray(c+306,"o_wdata", false,-1, 511,0); - tracep->declQuad(c+322,"o_wsel", false,-1, 63,0); - tracep->declBit(c+324,"i_wstall", false,-1); - tracep->declBit(c+325,"i_wack", false,-1); - tracep->declArray(c+327,"i_wdata", false,-1, 511,0); - tracep->declBit(c+326,"i_werr", false,-1); - tracep->pushNamePrefix("UPSIZE "); - tracep->declBus(c+5154,"LGFIFO", false,-1, 31,0); - tracep->declBit(c+302,"r_cyc", false,-1); - tracep->declBit(c+3099,"r_stb", false,-1); - tracep->declBit(c+304,"r_we", false,-1); - tracep->declBit(c+426,"r_ack", false,-1); - tracep->declBit(c+427,"r_err", false,-1); - tracep->declBus(c+305,"r_addr", false,-1, 21,0); - tracep->declArray(c+306,"r_data", false,-1, 511,0); - tracep->declArray(c+3100,"rtn_data", false,-1, 511,0); - tracep->declQuad(c+322,"r_sel", false,-1, 63,0); - tracep->declBus(c+3116,"r_shift", false,-1, 3,0); - tracep->declBit(c+3117,"fifo_full", false,-1); - tracep->declBit(c+3118,"ign_fifo_empty", false,-1); - tracep->declBus(c+3119,"ign_fifo_fill", false,-1, 5,0); - tracep->declBus(c+3120,"w_shift", false,-1, 3,0); - tracep->declBus(c+3121,"fifo_shift", false,-1, 3,0); - tracep->declArray(c+3122,"w_data", false,-1, 511,0); - tracep->declQuad(c+3138,"w_sel", false,-1, 63,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("u_fifo "); - tracep->declBus(c+5065,"BW", false,-1, 31,0); - tracep->declBus(c+5154,"LGFLEN", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_ASYNC_READ", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_WRITE_ON_FULL", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_READ_ON_EMPTY", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+86,"i_reset", false,-1); - tracep->declBit(c+3140,"i_wr", false,-1); - tracep->declBus(c+3116,"i_data", false,-1, 3,0); - tracep->declBit(c+3117,"o_full", false,-1); - tracep->declBus(c+3119,"o_fill", false,-1, 5,0); - tracep->declBit(c+325,"i_rd", false,-1); - tracep->declBus(c+3121,"o_data", false,-1, 3,0); - tracep->declBit(c+3118,"o_empty", false,-1); - tracep->declBus(c+5114,"FLEN", false,-1, 31,0); - tracep->declBit(c+3117,"r_full", false,-1); - tracep->declBit(c+3118,"r_empty", false,-1); - for (int i = 0; i < 32; ++i) { - tracep->declBus(c+3141+i*1,"mem", true,(i+0), 3,0); - } - tracep->declBus(c+3173,"wr_addr", false,-1, 5,0); - tracep->declBus(c+3174,"rd_addr", false,-1, 5,0); - tracep->declBit(c+3175,"w_wr", false,-1); - tracep->declBit(c+3176,"w_rd", false,-1); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("wbu_xbar "); - tracep->declBus(c+5064,"NM", false,-1, 31,0); - tracep->declBus(c+5075,"NS", false,-1, 31,0); - tracep->declBus(c+5130,"AW", false,-1, 31,0); - tracep->declBus(c+5114,"DW", false,-1, 31,0); - tracep->declQuad(c+5266,"SLAVE_ADDR", false,-1, 53,0); - tracep->declQuad(c+5268,"SLAVE_MASK", false,-1, 53,0); - tracep->declBus(c+5153,"LGMAXBURST", false,-1, 31,0); - tracep->declBus(c+5076,"OPT_TIMEOUT", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_STARVATION_TIMEOUT", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DBLBUFFER", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBus(c+410,"i_mcyc", false,-1, 0,0); - tracep->declBus(c+411,"i_mstb", false,-1, 0,0); - tracep->declBus(c+412,"i_mwe", false,-1, 0,0); - tracep->declBus(c+413,"i_maddr", false,-1, 26,0); - tracep->declBus(c+414,"i_mdata", false,-1, 31,0); - tracep->declBus(c+5108,"i_msel", false,-1, 3,0); - tracep->declBus(c+415,"o_mstall", false,-1, 0,0); - tracep->declBus(c+416,"o_mack", false,-1, 0,0); - tracep->declBus(c+418,"o_mdata", false,-1, 31,0); - tracep->declBus(c+417,"o_merr", false,-1, 0,0); - tracep->declBus(c+3177,"o_scyc", false,-1, 1,0); - tracep->declBus(c+3178,"o_sstb", false,-1, 1,0); - tracep->declBus(c+3179,"o_swe", false,-1, 1,0); - tracep->declQuad(c+3180,"o_saddr", false,-1, 53,0); - tracep->declQuad(c+3182,"o_sdata", false,-1, 63,0); - tracep->declBus(c+3184,"o_ssel", false,-1, 7,0); - tracep->declBus(c+5045,"i_sstall", false,-1, 1,0); - tracep->declBus(c+5046,"i_sack", false,-1, 1,0); - tracep->declQuad(c+3185,"i_sdata", false,-1, 63,0); - tracep->declBus(c+3187,"i_serr", false,-1, 1,0); - tracep->declBus(c+5076,"TIMEOUT_WIDTH", false,-1, 31,0); - tracep->declBus(c+5064,"LGNM", false,-1, 31,0); - tracep->declBus(c+5075,"LGNS", false,-1, 31,0); - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+3188+i*1,"request", true,(i+0), 2,0); - } - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+26+i*1,"requested", true,(i+0), 1,0); - } - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+3189+i*1,"grant", true,(i+0), 2,0); - } - tracep->declBus(c+3190,"mgrant", false,-1, 0,0); - tracep->declBus(c+3191,"sgrant", false,-1, 1,0); - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+3192+i*1,"w_mpending", true,(i+0), 5,0); - } - tracep->declBus(c+3193,"mfull", false,-1, 0,0); - tracep->declBus(c+3194,"mnearfull", false,-1, 0,0); - tracep->declBus(c+3195,"mempty", false,-1, 0,0); - tracep->declBus(c+5113,"timed_out", false,-1, 0,0); - tracep->declBus(c+5064,"NMFULL", false,-1, 31,0); - tracep->declBus(c+5065,"NSFULL", false,-1, 31,0); - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+4658+i*1,"mindex", true,(i+0), 1,0); - } - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+27+i*1,"sindex", true,(i+0), 0,0); - } - tracep->declBus(c+410,"m_cyc", false,-1, 0,0); - tracep->declBus(c+3196,"m_stb", false,-1, 0,0); - tracep->declBus(c+3197,"m_we", false,-1, 0,0); - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+3198+i*1,"m_addr", true,(i+0), 26,0); - } - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+3199+i*1,"m_data", true,(i+0), 31,0); - } - for (int i = 0; i < 1; ++i) { - tracep->declBus(c+3200+i*1,"m_sel", true,(i+0), 3,0); - } - tracep->declBus(c+151,"m_stall", false,-1, 0,0); - tracep->declBus(c+87,"s_stall", false,-1, 3,0); - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+3201+i*1,"s_data", true,(i+0), 31,0); - } - tracep->declBus(c+5047,"s_ack", false,-1, 3,0); - tracep->declBus(c+3205,"s_err", false,-1, 3,0); - tracep->declBus(c+3206,"dcd_stb", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_BUFFER_DECODER", false,-1, 0,0); - tracep->declBus(c+3207,"iN", false,-1, 31,0); - tracep->declBus(c+5048,"iM", false,-1, 31,0); - tracep->pushNamePrefix("ARBITRATE_REQUESTS[0] "); - tracep->declBus(c+4659,"regrant", false,-1, 2,0); - tracep->declBus(c+5049,"reindex", false,-1, 1,0); - tracep->declBit(c+3208,"stay_on_channel", false,-1); - tracep->declBit(c+3209,"requested_channel_is_available", false,-1); - tracep->pushNamePrefix("MINDEX_MULTIPLE_SLAVES "); - tracep->declBus(c+4660,"r_mindex", false,-1, 1,0); - tracep->declBus(c+4659,"r_regrant", false,-1, 2,0); - tracep->declBus(c+5049,"r_reindex", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("COUNT_PENDING_TRANSACTIONS[0] "); - tracep->declBus(c+3210,"lclpending", false,-1, 5,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("DECODE_REQUEST[0] "); - tracep->declBit(c+88,"skd_stb", false,-1); - tracep->declBit(c+152,"skd_stall", false,-1); - tracep->declBit(c+3211,"skd_we", false,-1); - tracep->declBus(c+3212,"skd_addr", false,-1, 26,0); - tracep->declBus(c+3213,"skd_data", false,-1, 31,0); - tracep->declBus(c+3214,"skd_sel", false,-1, 3,0); - tracep->declBus(c+3215,"decoded", false,-1, 2,0); - tracep->declBit(c+3216,"iskd_ready", false,-1); - tracep->pushNamePrefix("adcd "); - tracep->declBus(c+5075,"NS", false,-1, 31,0); - tracep->declBus(c+5130,"AW", false,-1, 31,0); - tracep->declBus(c+5264,"DW", false,-1, 31,0); - tracep->declQuad(c+5266,"SLAVE_ADDR", false,-1, 53,0); - tracep->declQuad(c+5268,"SLAVE_MASK", false,-1, 53,0); - tracep->declBus(c+5119,"ACCESS_ALLOWED", false,-1, 1,0); - tracep->declBus(c+5070,"OPT_REGISTERED", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+89,"i_valid", false,-1); - tracep->declBit(c+152,"o_stall", false,-1); - tracep->declBus(c+3212,"i_addr", false,-1, 26,0); - tracep->declQuad(c+3217,"i_data", false,-1, 36,0); - tracep->declBit(c+3206,"o_valid", false,-1); - tracep->declBit(c+153,"i_stall", false,-1); - tracep->declBus(c+3215,"o_decode", false,-1, 2,0); - tracep->declBus(c+3219,"o_addr", false,-1, 26,0); - tracep->declQuad(c+3220,"o_data", false,-1, 36,0); - tracep->declBus(c+5070,"OPT_NONESEL", false,-1, 0,0); - tracep->declBus(c+90,"request", false,-1, 2,0); - tracep->declBus(c+3222,"prerequest", false,-1, 1,0); - tracep->declBus(c+31,"iM", false,-1, 31,0); - tracep->pushNamePrefix("NO_DEFAULT_REQUEST "); - tracep->declBus(c+91,"r_request", false,-1, 1,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OPT_NONESEL_REQUEST "); - tracep->declBit(c+92,"r_request_NS", false,-1); - tracep->declBit(c+93,"r_none_sel", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("iskid "); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_OUTREG", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_PASSTHROUGH", false,-1, 0,0); - tracep->declBus(c+5120,"DW", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_INITIAL", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+94,"i_reset", false,-1); - tracep->declBit(c+411,"i_valid", false,-1); - tracep->declBit(c+3216,"o_ready", false,-1); - tracep->declQuad(c+3223,"i_data", false,-1, 63,0); - tracep->declBit(c+88,"o_valid", false,-1); - tracep->declBit(c+154,"i_ready", false,-1); - tracep->declQuad(c+3225,"o_data", false,-1, 63,0); - tracep->declQuad(c+3227,"w_data", false,-1, 63,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("LOGIC "); - tracep->declBit(c+415,"r_valid", false,-1); - tracep->declQuad(c+3227,"r_data", false,-1, 63,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DOUBLE_BUFFERRED_STALL "); - tracep->declBus(c+416,"r_mack", false,-1, 0,0); - tracep->declBus(c+417,"r_merr", false,-1, 0,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[0] "); - tracep->declBit(c+95,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[1] "); - tracep->declBit(c+96,"drop_sgrant", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("wbwide_xbar "); - tracep->declBus(c+5065,"NM", false,-1, 31,0); - tracep->declBus(c+5062,"NS", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5111,"DW", false,-1, 31,0); - tracep->declArray(c+5270,"SLAVE_ADDR", false,-1, 65,0); - tracep->declArray(c+5273,"SLAVE_MASK", false,-1, 65,0); - tracep->declBus(c+5153,"LGMAXBURST", false,-1, 31,0); - tracep->declBus(c+5076,"OPT_TIMEOUT", false,-1, 31,0); - tracep->declBus(c+5113,"OPT_STARVATION_TIMEOUT", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_DBLBUFFER", false,-1, 0,0); - tracep->declBus(c+5070,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBus(c+4661,"i_mcyc", false,-1, 3,0); - tracep->declBus(c+3229,"i_mstb", false,-1, 3,0); - tracep->declBus(c+3230,"i_mwe", false,-1, 3,0); - tracep->declArray(c+3231,"i_maddr", false,-1, 87,0); - tracep->declArray(c+3234,"i_mdata", false,-1, 2047,0); - tracep->declArray(c+3298,"i_msel", false,-1, 255,0); - tracep->declBus(c+3306,"o_mstall", false,-1, 3,0); - tracep->declBus(c+3307,"o_mack", false,-1, 3,0); - tracep->declArray(c+3308,"o_mdata", false,-1, 2047,0); - tracep->declBus(c+3372,"o_merr", false,-1, 3,0); - tracep->declBus(c+4662,"o_scyc", false,-1, 2,0); - tracep->declBus(c+4663,"o_sstb", false,-1, 2,0); - tracep->declBus(c+4664,"o_swe", false,-1, 2,0); - tracep->declArray(c+4665,"o_saddr", false,-1, 65,0); - tracep->declArray(c+4668,"o_sdata", false,-1, 1535,0); - tracep->declArray(c+4716,"o_ssel", false,-1, 191,0); - tracep->declBus(c+3918,"i_sstall", false,-1, 2,0); - tracep->declBus(c+3919,"i_sack", false,-1, 2,0); - tracep->declArray(c+3920,"i_sdata", false,-1, 1535,0); - tracep->declBus(c+4722,"i_serr", false,-1, 2,0); - tracep->declBus(c+5076,"TIMEOUT_WIDTH", false,-1, 31,0); - tracep->declBus(c+5075,"LGNM", false,-1, 31,0); - tracep->declBus(c+5075,"LGNS", false,-1, 31,0); - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+3373+i*1,"request", true,(i+0), 3,0); - } - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+3377+i*1,"requested", true,(i+0), 2,0); - } - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+3381+i*1,"grant", true,(i+0), 3,0); - } - tracep->declBus(c+3385,"mgrant", false,-1, 3,0); - tracep->declBus(c+4723,"sgrant", false,-1, 2,0); - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+3386+i*1,"w_mpending", true,(i+0), 5,0); - } - tracep->declBus(c+3390,"mfull", false,-1, 3,0); - tracep->declBus(c+3391,"mnearfull", false,-1, 3,0); - tracep->declBus(c+3392,"mempty", false,-1, 3,0); - tracep->declBus(c+5122,"timed_out", false,-1, 3,0); - tracep->declBus(c+5065,"NMFULL", false,-1, 31,0); - tracep->declBus(c+5065,"NSFULL", false,-1, 31,0); - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+4724+i*1,"mindex", true,(i+0), 1,0); - } - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+4728+i*1,"sindex", true,(i+0), 1,0); - } - tracep->declBus(c+4661,"m_cyc", false,-1, 3,0); - tracep->declBus(c+3393,"m_stb", false,-1, 3,0); - tracep->declBus(c+4732,"m_we", false,-1, 3,0); - for (int i = 0; i < 4; ++i) { - tracep->declBus(c+4733+i*1,"m_addr", true,(i+0), 21,0); - } - for (int i = 0; i < 4; ++i) { - tracep->declArray(c+4737+i*16,"m_data", true,(i+0), 511,0); - } - for (int i = 0; i < 4; ++i) { - tracep->declQuad(c+4801+i*2,"m_sel", true,(i+0), 63,0); - } - tracep->declBus(c+4886,"m_stall", false,-1, 3,0); - tracep->declBus(c+4887,"s_stall", false,-1, 3,0); - for (int i = 0; i < 4; ++i) { - tracep->declArray(c+3968+i*16,"s_data", true,(i+0), 511,0); - } - tracep->declBus(c+4888,"s_ack", false,-1, 3,0); - tracep->declBus(c+4809,"s_err", false,-1, 3,0); - tracep->declBus(c+3394,"dcd_stb", false,-1, 3,0); - tracep->declBus(c+5070,"OPT_BUFFER_DECODER", false,-1, 0,0); - tracep->declBus(c+5050,"iN", false,-1, 31,0); - tracep->declBus(c+5051,"iM", false,-1, 31,0); - tracep->pushNamePrefix("ARBITRATE_REQUESTS[0] "); - tracep->declBus(c+4810,"regrant", false,-1, 3,0); - tracep->declBus(c+5052,"reindex", false,-1, 1,0); - tracep->declBit(c+3395,"stay_on_channel", false,-1); - tracep->declBit(c+4811,"requested_channel_is_available", false,-1); - tracep->pushNamePrefix("MINDEX_MULTIPLE_SLAVES "); - tracep->declBus(c+4812,"r_mindex", false,-1, 1,0); - tracep->declBus(c+4810,"r_regrant", false,-1, 3,0); - tracep->declBus(c+5052,"r_reindex", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("ARBITRATE_REQUESTS[1] "); - tracep->declBus(c+4813,"regrant", false,-1, 3,0); - tracep->declBus(c+5053,"reindex", false,-1, 1,0); - tracep->declBit(c+3396,"stay_on_channel", false,-1); - tracep->declBit(c+4814,"requested_channel_is_available", false,-1); - tracep->pushNamePrefix("MINDEX_MULTIPLE_SLAVES "); - tracep->declBus(c+4815,"r_mindex", false,-1, 1,0); - tracep->declBus(c+4813,"r_regrant", false,-1, 3,0); - tracep->declBus(c+5053,"r_reindex", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("ARBITRATE_REQUESTS[2] "); - tracep->declBus(c+4816,"regrant", false,-1, 3,0); - tracep->declBus(c+5054,"reindex", false,-1, 1,0); - tracep->declBit(c+3397,"stay_on_channel", false,-1); - tracep->declBit(c+4817,"requested_channel_is_available", false,-1); - tracep->pushNamePrefix("MINDEX_MULTIPLE_SLAVES "); - tracep->declBus(c+4818,"r_mindex", false,-1, 1,0); - tracep->declBus(c+4816,"r_regrant", false,-1, 3,0); - tracep->declBus(c+5054,"r_reindex", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("ARBITRATE_REQUESTS[3] "); - tracep->declBus(c+4819,"regrant", false,-1, 3,0); - tracep->declBus(c+5055,"reindex", false,-1, 1,0); - tracep->declBit(c+3398,"stay_on_channel", false,-1); - tracep->declBit(c+4820,"requested_channel_is_available", false,-1); - tracep->pushNamePrefix("MINDEX_MULTIPLE_SLAVES "); - tracep->declBus(c+4821,"r_mindex", false,-1, 1,0); - tracep->declBus(c+4819,"r_regrant", false,-1, 3,0); - tracep->declBus(c+5055,"r_reindex", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("COUNT_PENDING_TRANSACTIONS[0] "); - tracep->declBus(c+3399,"lclpending", false,-1, 5,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("COUNT_PENDING_TRANSACTIONS[1] "); - tracep->declBus(c+3400,"lclpending", false,-1, 5,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("COUNT_PENDING_TRANSACTIONS[2] "); - tracep->declBus(c+3401,"lclpending", false,-1, 5,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("COUNT_PENDING_TRANSACTIONS[3] "); - tracep->declBus(c+3402,"lclpending", false,-1, 5,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("DECODE_REQUEST[0] "); - tracep->declBit(c+97,"skd_stb", false,-1); - tracep->declBit(c+4889,"skd_stall", false,-1); - tracep->declBit(c+3403,"skd_we", false,-1); - tracep->declBus(c+3404,"skd_addr", false,-1, 21,0); - tracep->declArray(c+3405,"skd_data", false,-1, 511,0); - tracep->declQuad(c+3421,"skd_sel", false,-1, 63,0); - tracep->declBus(c+3423,"decoded", false,-1, 3,0); - tracep->declBit(c+3424,"iskd_ready", false,-1); - tracep->pushNamePrefix("adcd "); - tracep->declBus(c+5062,"NS", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5276,"DW", false,-1, 31,0); - tracep->declArray(c+5270,"SLAVE_ADDR", false,-1, 65,0); - tracep->declArray(c+5273,"SLAVE_MASK", false,-1, 65,0); - tracep->declBus(c+5210,"ACCESS_ALLOWED", false,-1, 2,0); - tracep->declBus(c+5070,"OPT_REGISTERED", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+98,"i_valid", false,-1); - tracep->declBit(c+4889,"o_stall", false,-1); - tracep->declBus(c+3404,"i_addr", false,-1, 21,0); - tracep->declArray(c+3425,"i_data", false,-1, 576,0); - tracep->declBit(c+3444,"o_valid", false,-1); - tracep->declBit(c+4890,"i_stall", false,-1); - tracep->declBus(c+3423,"o_decode", false,-1, 3,0); - tracep->declBus(c+3445,"o_addr", false,-1, 21,0); - tracep->declArray(c+3446,"o_data", false,-1, 576,0); - tracep->declBus(c+5070,"OPT_NONESEL", false,-1, 0,0); - tracep->declBus(c+99,"request", false,-1, 3,0); - tracep->declBus(c+3465,"prerequest", false,-1, 2,0); - tracep->declBus(c+32,"iM", false,-1, 31,0); - tracep->pushNamePrefix("NO_DEFAULT_REQUEST "); - tracep->declBus(c+100,"r_request", false,-1, 2,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OPT_NONESEL_REQUEST "); - tracep->declBit(c+101,"r_request_NS", false,-1); - tracep->declBit(c+102,"r_none_sel", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("iskid "); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_OUTREG", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_PASSTHROUGH", false,-1, 0,0); - tracep->declBus(c+5277,"DW", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_INITIAL", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+103,"i_reset", false,-1); - tracep->declBit(c+200,"i_valid", false,-1); - tracep->declBit(c+3424,"o_ready", false,-1); - tracep->declArray(c+3466,"i_data", false,-1, 598,0); - tracep->declBit(c+97,"o_valid", false,-1); - tracep->declBit(c+4891,"i_ready", false,-1); - tracep->declArray(c+3485,"o_data", false,-1, 598,0); - tracep->declArray(c+3504,"w_data", false,-1, 598,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("LOGIC "); - tracep->declBit(c+3523,"r_valid", false,-1); - tracep->declArray(c+3504,"r_data", false,-1, 598,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DECODE_REQUEST[1] "); - tracep->declBit(c+104,"skd_stb", false,-1); - tracep->declBit(c+4892,"skd_stall", false,-1); - tracep->declBit(c+3524,"skd_we", false,-1); - tracep->declBus(c+3525,"skd_addr", false,-1, 21,0); - tracep->declArray(c+3526,"skd_data", false,-1, 511,0); - tracep->declQuad(c+3542,"skd_sel", false,-1, 63,0); - tracep->declBus(c+3544,"decoded", false,-1, 3,0); - tracep->declBit(c+3545,"iskd_ready", false,-1); - tracep->pushNamePrefix("adcd "); - tracep->declBus(c+5062,"NS", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5276,"DW", false,-1, 31,0); - tracep->declArray(c+5270,"SLAVE_ADDR", false,-1, 65,0); - tracep->declArray(c+5273,"SLAVE_MASK", false,-1, 65,0); - tracep->declBus(c+5210,"ACCESS_ALLOWED", false,-1, 2,0); - tracep->declBus(c+5070,"OPT_REGISTERED", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+105,"i_valid", false,-1); - tracep->declBit(c+4892,"o_stall", false,-1); - tracep->declBus(c+3525,"i_addr", false,-1, 21,0); - tracep->declArray(c+3546,"i_data", false,-1, 576,0); - tracep->declBit(c+3565,"o_valid", false,-1); - tracep->declBit(c+4893,"i_stall", false,-1); - tracep->declBus(c+3544,"o_decode", false,-1, 3,0); - tracep->declBus(c+3566,"o_addr", false,-1, 21,0); - tracep->declArray(c+3567,"o_data", false,-1, 576,0); - tracep->declBus(c+5070,"OPT_NONESEL", false,-1, 0,0); - tracep->declBus(c+106,"request", false,-1, 3,0); - tracep->declBus(c+3586,"prerequest", false,-1, 2,0); - tracep->declBus(c+33,"iM", false,-1, 31,0); - tracep->pushNamePrefix("NO_DEFAULT_REQUEST "); - tracep->declBus(c+107,"r_request", false,-1, 2,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OPT_NONESEL_REQUEST "); - tracep->declBit(c+108,"r_request_NS", false,-1); - tracep->declBit(c+109,"r_none_sel", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("iskid "); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_OUTREG", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_PASSTHROUGH", false,-1, 0,0); - tracep->declBus(c+5277,"DW", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_INITIAL", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+110,"i_reset", false,-1); - tracep->declBit(c+240,"i_valid", false,-1); - tracep->declBit(c+3545,"o_ready", false,-1); - tracep->declArray(c+3587,"i_data", false,-1, 598,0); - tracep->declBit(c+104,"o_valid", false,-1); - tracep->declBit(c+4894,"i_ready", false,-1); - tracep->declArray(c+3606,"o_data", false,-1, 598,0); - tracep->declArray(c+3625,"w_data", false,-1, 598,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("LOGIC "); - tracep->declBit(c+3644,"r_valid", false,-1); - tracep->declArray(c+3625,"r_data", false,-1, 598,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DECODE_REQUEST[2] "); - tracep->declBit(c+111,"skd_stb", false,-1); - tracep->declBit(c+4895,"skd_stall", false,-1); - tracep->declBit(c+3645,"skd_we", false,-1); - tracep->declBus(c+3646,"skd_addr", false,-1, 21,0); - tracep->declArray(c+3647,"skd_data", false,-1, 511,0); - tracep->declQuad(c+3663,"skd_sel", false,-1, 63,0); - tracep->declBus(c+3665,"decoded", false,-1, 3,0); - tracep->declBit(c+3666,"iskd_ready", false,-1); - tracep->pushNamePrefix("adcd "); - tracep->declBus(c+5062,"NS", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5276,"DW", false,-1, 31,0); - tracep->declArray(c+5270,"SLAVE_ADDR", false,-1, 65,0); - tracep->declArray(c+5273,"SLAVE_MASK", false,-1, 65,0); - tracep->declBus(c+5210,"ACCESS_ALLOWED", false,-1, 2,0); - tracep->declBus(c+5070,"OPT_REGISTERED", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+112,"i_valid", false,-1); - tracep->declBit(c+4895,"o_stall", false,-1); - tracep->declBus(c+3646,"i_addr", false,-1, 21,0); - tracep->declArray(c+3667,"i_data", false,-1, 576,0); - tracep->declBit(c+3686,"o_valid", false,-1); - tracep->declBit(c+4896,"i_stall", false,-1); - tracep->declBus(c+3665,"o_decode", false,-1, 3,0); - tracep->declBus(c+3687,"o_addr", false,-1, 21,0); - tracep->declArray(c+3688,"o_data", false,-1, 576,0); - tracep->declBus(c+5070,"OPT_NONESEL", false,-1, 0,0); - tracep->declBus(c+113,"request", false,-1, 3,0); - tracep->declBus(c+3707,"prerequest", false,-1, 2,0); - tracep->declBus(c+34,"iM", false,-1, 31,0); - tracep->pushNamePrefix("NO_DEFAULT_REQUEST "); - tracep->declBus(c+114,"r_request", false,-1, 2,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OPT_NONESEL_REQUEST "); - tracep->declBit(c+115,"r_request_NS", false,-1); - tracep->declBit(c+116,"r_none_sel", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("iskid "); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_OUTREG", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_PASSTHROUGH", false,-1, 0,0); - tracep->declBus(c+5277,"DW", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_INITIAL", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+117,"i_reset", false,-1); - tracep->declBit(c+262,"i_valid", false,-1); - tracep->declBit(c+3666,"o_ready", false,-1); - tracep->declArray(c+3708,"i_data", false,-1, 598,0); - tracep->declBit(c+111,"o_valid", false,-1); - tracep->declBit(c+4897,"i_ready", false,-1); - tracep->declArray(c+3727,"o_data", false,-1, 598,0); - tracep->declArray(c+3746,"w_data", false,-1, 598,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("LOGIC "); - tracep->declBit(c+3765,"r_valid", false,-1); - tracep->declArray(c+3746,"r_data", false,-1, 598,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DECODE_REQUEST[3] "); - tracep->declBit(c+118,"skd_stb", false,-1); - tracep->declBit(c+4898,"skd_stall", false,-1); - tracep->declBit(c+3766,"skd_we", false,-1); - tracep->declBus(c+3767,"skd_addr", false,-1, 21,0); - tracep->declArray(c+3768,"skd_data", false,-1, 511,0); - tracep->declQuad(c+3784,"skd_sel", false,-1, 63,0); - tracep->declBus(c+3786,"decoded", false,-1, 3,0); - tracep->declBit(c+3787,"iskd_ready", false,-1); - tracep->pushNamePrefix("adcd "); - tracep->declBus(c+5062,"NS", false,-1, 31,0); - tracep->declBus(c+5068,"AW", false,-1, 31,0); - tracep->declBus(c+5276,"DW", false,-1, 31,0); - tracep->declArray(c+5270,"SLAVE_ADDR", false,-1, 65,0); - tracep->declArray(c+5273,"SLAVE_MASK", false,-1, 65,0); - tracep->declBus(c+5210,"ACCESS_ALLOWED", false,-1, 2,0); - tracep->declBus(c+5070,"OPT_REGISTERED", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+4902,"i_reset", false,-1); - tracep->declBit(c+119,"i_valid", false,-1); - tracep->declBit(c+4898,"o_stall", false,-1); - tracep->declBus(c+3767,"i_addr", false,-1, 21,0); - tracep->declArray(c+3788,"i_data", false,-1, 576,0); - tracep->declBit(c+3807,"o_valid", false,-1); - tracep->declBit(c+4899,"i_stall", false,-1); - tracep->declBus(c+3786,"o_decode", false,-1, 3,0); - tracep->declBus(c+3808,"o_addr", false,-1, 21,0); - tracep->declArray(c+3809,"o_data", false,-1, 576,0); - tracep->declBus(c+5070,"OPT_NONESEL", false,-1, 0,0); - tracep->declBus(c+120,"request", false,-1, 3,0); - tracep->declBus(c+3828,"prerequest", false,-1, 2,0); - tracep->declBus(c+35,"iM", false,-1, 31,0); - tracep->pushNamePrefix("NO_DEFAULT_REQUEST "); - tracep->declBus(c+121,"r_request", false,-1, 2,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("OPT_NONESEL_REQUEST "); - tracep->declBit(c+122,"r_request_NS", false,-1); - tracep->declBit(c+123,"r_none_sel", false,-1); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("iskid "); - tracep->declBus(c+5113,"OPT_LOWPOWER", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_OUTREG", false,-1, 0,0); - tracep->declBus(c+5113,"OPT_PASSTHROUGH", false,-1, 0,0); - tracep->declBus(c+5277,"DW", false,-1, 31,0); - tracep->declBus(c+5070,"OPT_INITIAL", false,-1, 0,0); - tracep->declBit(c+4901,"i_clk", false,-1); - tracep->declBit(c+124,"i_reset", false,-1); - tracep->declBit(c+303,"i_valid", false,-1); - tracep->declBit(c+3787,"o_ready", false,-1); - tracep->declArray(c+3829,"i_data", false,-1, 598,0); - tracep->declBit(c+118,"o_valid", false,-1); - tracep->declBit(c+4900,"i_ready", false,-1); - tracep->declArray(c+3848,"o_data", false,-1, 598,0); - tracep->declArray(c+3867,"w_data", false,-1, 598,0); - tracep->declBit(c+5074,"unused", false,-1); - tracep->pushNamePrefix("LOGIC "); - tracep->declBit(c+324,"r_valid", false,-1); - tracep->declArray(c+3867,"r_data", false,-1, 598,0); - tracep->popNamePrefix(3); - tracep->pushNamePrefix("DOUBLE_BUFFERRED_STALL "); - tracep->declBus(c+3307,"r_mack", false,-1, 3,0); - tracep->declBus(c+3372,"r_merr", false,-1, 3,0); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("GEN_SINDEX[0] "); - tracep->pushNamePrefix("SINDEX_MORE_THAN_ONE_MASTER "); - tracep->declBus(c+3886,"r_sindex", false,-1, 1,0); - tracep->declBus(c+4822,"regrant", false,-1, 3,0); - tracep->declBus(c+4823,"reindex", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("GEN_SINDEX[1] "); - tracep->pushNamePrefix("SINDEX_MORE_THAN_ONE_MASTER "); - tracep->declBus(c+3887,"r_sindex", false,-1, 1,0); - tracep->declBus(c+4824,"regrant", false,-1, 3,0); - tracep->declBus(c+4825,"reindex", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("GEN_SINDEX[2] "); - tracep->pushNamePrefix("SINDEX_MORE_THAN_ONE_MASTER "); - tracep->declBus(c+3888,"r_sindex", false,-1, 1,0); - tracep->declBus(c+4826,"regrant", false,-1, 3,0); - tracep->declBus(c+4827,"reindex", false,-1, 1,0); - tracep->popNamePrefix(2); - tracep->pushNamePrefix("SLAVE_GRANT[0] "); - tracep->declBit(c+155,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[1] "); - tracep->declBit(c+156,"drop_sgrant", false,-1); - tracep->popNamePrefix(1); - tracep->pushNamePrefix("SLAVE_GRANT[2] "); - tracep->declBit(c+157,"drop_sgrant", false,-1); - tracep->popNamePrefix(3); -} - -VL_ATTR_COLD void Vmain___024root__trace_init_top(Vmain___024root* vlSelf, VerilatedVcd* tracep) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root__trace_init_top\n"); ); - // Body - Vmain___024root__trace_init_sub__TOP__0(vlSelf, tracep); -} - -VL_ATTR_COLD void Vmain___024root__trace_full_top_0(void* voidSelf, VerilatedVcd::Buffer* bufp); -void Vmain___024root__trace_chg_top_0(void* voidSelf, VerilatedVcd::Buffer* bufp); -void Vmain___024root__trace_cleanup(void* voidSelf, VerilatedVcd* /*unused*/); - -VL_ATTR_COLD void Vmain___024root__trace_register(Vmain___024root* vlSelf, VerilatedVcd* tracep) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root__trace_register\n"); ); - // Body - tracep->addFullCb(&Vmain___024root__trace_full_top_0, vlSelf); - tracep->addChgCb(&Vmain___024root__trace_chg_top_0, vlSelf); - tracep->addCleanupCb(&Vmain___024root__trace_cleanup, vlSelf); -} - -VL_ATTR_COLD void Vmain___024root__trace_full_sub_0(Vmain___024root* vlSelf, VerilatedVcd::Buffer* bufp); - -VL_ATTR_COLD void Vmain___024root__trace_full_top_0(void* voidSelf, VerilatedVcd::Buffer* bufp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root__trace_full_top_0\n"); ); - // Init - Vmain___024root* const __restrict vlSelf VL_ATTR_UNUSED = static_cast(voidSelf); - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - // Body - Vmain___024root__trace_full_sub_0((&vlSymsp->TOP), bufp); -} - -extern const VlWide<15>/*479:0*/ Vmain__ConstPool__CONST_hbd99daea_0; -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0; -extern const VlWide<18>/*575:0*/ Vmain__ConstPool__CONST_hb679b2e5_0; - -VL_ATTR_COLD void Vmain___024root__trace_full_sub_0(Vmain___024root* vlSelf, VerilatedVcd::Buffer* bufp) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root__trace_full_sub_0\n"); ); - // Init - uint32_t* const oldp VL_ATTR_UNUSED = bufp->oldp(vlSymsp->__Vm_baseCode); - VlWide<16>/*511:0*/ __Vtemp_h053daff0__0; - VlWide<16>/*511:0*/ __Vtemp_h3711b190__0; - VlWide<16>/*511:0*/ __Vtemp_h58eb921b__0; - VlWide<16>/*511:0*/ __Vtemp_hc1d82fb0__0; - VlWide<16>/*511:0*/ __Vtemp_hc1851150__0; - VlWide<16>/*511:0*/ __Vtemp_hd1e4c677__0; - VlWide<16>/*511:0*/ __Vtemp_h6ddae8d1__0; - VlWide<16>/*511:0*/ __Vtemp_hc1d82fb0__1; - VlWide<16>/*511:0*/ __Vtemp_h6d0d1506__0; - VlWide<17>/*543:0*/ __Vtemp_h6b3f223d__0; - VlWide<16>/*511:0*/ __Vtemp_h01ff8f7b__0; - VlWide<16>/*511:0*/ __Vtemp_he3c3974d__0; - VlWide<16>/*511:0*/ __Vtemp_hcfafa750__0; - VlWide<3>/*95:0*/ __Vtemp_h708d16f1__0; - VlWide<64>/*2047:0*/ __Vtemp_h95b27ed2__0; - VlWide<8>/*255:0*/ __Vtemp_h7cab7483__0; - VlWide<16>/*511:0*/ __Vtemp_h53a5df10__0; - VlWide<19>/*607:0*/ __Vtemp_hb52cb2db__0; - VlWide<16>/*511:0*/ __Vtemp_hebded4b4__0; - VlWide<19>/*607:0*/ __Vtemp_h0a2cdfa5__0; - VlWide<19>/*607:0*/ __Vtemp_he57bd368__0; - VlWide<16>/*511:0*/ __Vtemp_h0964a254__0; - VlWide<19>/*607:0*/ __Vtemp_h925b4b87__0; - VlWide<16>/*511:0*/ __Vtemp_h5b5f8605__0; - VlWide<19>/*607:0*/ __Vtemp_hfe9179b2__0; - VlWide<12>/*383:0*/ __Vtemp_ha40692d2__0; - VlWide<48>/*1535:0*/ __Vtemp_h8a06d21b__0; - VlWide<16>/*511:0*/ __Vtemp_hc035b709__1; - VlWide<16>/*511:0*/ __Vtemp_hf82de6ac__0; - VlWide<16>/*511:0*/ __Vtemp_hf74e670c__0; - VlWide<16>/*511:0*/ __Vtemp_h21e563ec__0; - VlWide<3>/*95:0*/ __Vtemp_hf465e4c8__0; - VlWide<3>/*95:0*/ __Vtemp_hba125475__0; - VlWide<3>/*95:0*/ __Vtemp_hca679e21__0; - VlWide<3>/*95:0*/ __Vtemp_h0730ce07__0; - VlWide<3>/*95:0*/ __Vtemp_h754c1427__0; - // Body - bufp->fullIData(oldp+1,(vlSelf->main__DOT__ddr3_controller_inst__DOT__nCK_to_cycles__Vstatic__result),32); - bufp->fullIData(oldp+2,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k),32); - bufp->fullCData(oldp+3,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv),7); - bufp->fullIData(oldp+4,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k),32); - bufp->fullCData(oldp+5,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__newv),7); - bufp->fullIData(oldp+6,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k),32); - bufp->fullIData(oldp+7,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__ik),32); - bufp->fullSData(oldp+8,(vlSelf->main__DOT__wb32_xbar__DOT__requested[0]),12); - bufp->fullBit(oldp+9,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[0])); - bufp->fullBit(oldp+10,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[1])); - bufp->fullBit(oldp+11,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[2])); - bufp->fullBit(oldp+12,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[3])); - bufp->fullBit(oldp+13,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[4])); - bufp->fullBit(oldp+14,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[5])); - bufp->fullBit(oldp+15,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[6])); - bufp->fullBit(oldp+16,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[7])); - bufp->fullBit(oldp+17,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[8])); - bufp->fullBit(oldp+18,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[9])); - bufp->fullBit(oldp+19,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[10])); - bufp->fullBit(oldp+20,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[11])); - bufp->fullBit(oldp+21,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[12])); - bufp->fullBit(oldp+22,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[13])); - bufp->fullBit(oldp+23,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[14])); - bufp->fullBit(oldp+24,(vlSelf->main__DOT__wb32_xbar__DOT__sindex[15])); - bufp->fullIData(oldp+25,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM),32); - bufp->fullCData(oldp+26,(vlSelf->main__DOT__wbu_xbar__DOT__requested[0]),2); - bufp->fullBit(oldp+27,(vlSelf->main__DOT__wbu_xbar__DOT__sindex[0])); - bufp->fullBit(oldp+28,(vlSelf->main__DOT__wbu_xbar__DOT__sindex[1])); - bufp->fullBit(oldp+29,(vlSelf->main__DOT__wbu_xbar__DOT__sindex[2])); - bufp->fullBit(oldp+30,(vlSelf->main__DOT__wbu_xbar__DOT__sindex[3])); - bufp->fullIData(oldp+31,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM),32); - bufp->fullIData(oldp+32,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM),32); - bufp->fullIData(oldp+33,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__iM),32); - bufp->fullIData(oldp+34,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__iM),32); - bufp->fullIData(oldp+35,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__iM),32); - bufp->fullIData(oldp+36,((((IData)(vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3) - << 0x1fU) | vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4)),32); - bufp->fullIData(oldp+37,((((IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted) - << 0x1fU) | vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4)),32); - bufp->fullIData(oldp+38,(vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4),31); - bufp->fullIData(oldp+39,((((IData)(vlSelf->main__DOT__i2ci__DOT__half_insn) - << 0x1cU) | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual) - << 0x18U) - | vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0))),32); - bufp->fullBit(oldp+40,(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)); - bufp->fullBit(oldp+41,(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset)); - bufp->fullIData(oldp+42,(vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4),31); - bufp->fullBit(oldp+43,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc)); - bufp->fullBit(oldp+44,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb)); - bufp->fullBit(oldp+45,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_we)); - bufp->fullCData(oldp+46,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr),7); - bufp->fullIData(oldp+47,(vlSelf->main__DOT____Vcellinp__swic__i_dbg_data),32); - bufp->fullBit(oldp+48,(vlSelf->main__DOT__swic__DOT__cpu_op_stall)); - bufp->fullBit(oldp+49,(((IData)(vlSelf->main__DOT__swic__DOT__cpu_op_stall) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))); - bufp->fullBit(oldp+50,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready)); - bufp->fullBit(oldp+51,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce)); - bufp->fullBit(oldp+52,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance)); - bufp->fullBit(oldp+53,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall)); - bufp->fullBit(oldp+54,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)); - bufp->fullBit(oldp+55,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce)); - bufp->fullBit(oldp+56,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U))) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)))))); - bufp->fullBit(oldp+57,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)) - & (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI)) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - == (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR)) - | (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - | ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg) - == - (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U)))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U) & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)))))); - bufp->fullBit(oldp+58,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)); - bufp->fullIData(oldp+59,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v),32); - bufp->fullIData(oldp+60,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v),32); - bufp->fullBit(oldp+61,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce)); - bufp->fullBit(oldp+62,(((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0)))); - bufp->fullBit(oldp+63,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce)); - bufp->fullBit(oldp+64,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled)); - bufp->fullBit(oldp+65,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce)); - bufp->fullBit(oldp+66,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional)); - bufp->fullBit(oldp+67,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset)); - bufp->fullCData(oldp+68,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc),3); - bufp->fullCData(oldp+69,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc),3); - bufp->fullCData(oldp+70,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc),3); - bufp->fullBit(oldp+71,(((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim) - & ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((0xfU - == - (0xfU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))) - & ((1U - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie))))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu))))))))); - bufp->fullBit(oldp+72,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op)); - bufp->fullBit(oldp+73,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset)); - bufp->fullBit(oldp+74,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)); - bufp->fullBit(oldp+75,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset)); - bufp->fullBit(oldp+76,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin)); - bufp->fullBit(oldp+77,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in)); - bufp->fullBit(oldp+78,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin)); - bufp->fullBit(oldp+79,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in)); - bufp->fullBit(oldp+80,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin)); - bufp->fullBit(oldp+81,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in)); - bufp->fullBit(oldp+82,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin)); - bufp->fullBit(oldp+83,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in)); - bufp->fullBit(oldp+84,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in)); - bufp->fullBit(oldp+85,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset)); - bufp->fullBit(oldp+86,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset)); - bufp->fullCData(oldp+87,(vlSelf->main__DOT__wbu_xbar__DOT__s_stall),4); - bufp->fullBit(oldp+88,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb)); - bufp->fullBit(oldp+89,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid)); - bufp->fullCData(oldp+90,((((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 2U) | ((- (IData)((IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid))) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)))),3); - bufp->fullCData(oldp+91,(((- (IData)((IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid))) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest))),2); - bufp->fullBit(oldp+92,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->fullBit(oldp+93,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->fullBit(oldp+94,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)); - bufp->fullBit(oldp+95,(vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+96,(vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+97,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb)); - bufp->fullBit(oldp+98,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid)); - bufp->fullCData(oldp+99,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 3U) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),4); - bufp->fullCData(oldp+100,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),3); - bufp->fullBit(oldp+101,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->fullBit(oldp+102,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->fullBit(oldp+103,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)); - bufp->fullBit(oldp+104,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb)); - bufp->fullBit(oldp+105,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid)); - bufp->fullCData(oldp+106,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 3U) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),4); - bufp->fullCData(oldp+107,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),3); - bufp->fullBit(oldp+108,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->fullBit(oldp+109,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->fullBit(oldp+110,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset)); - bufp->fullBit(oldp+111,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb)); - bufp->fullBit(oldp+112,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid)); - bufp->fullCData(oldp+113,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 3U) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),4); - bufp->fullCData(oldp+114,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),3); - bufp->fullBit(oldp+115,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->fullBit(oldp+116,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->fullBit(oldp+117,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset)); - bufp->fullBit(oldp+118,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb)); - bufp->fullBit(oldp+119,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid)); - bufp->fullCData(oldp+120,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 3U) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),4); - bufp->fullCData(oldp+121,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),3); - bufp->fullBit(oldp+122,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->fullBit(oldp+123,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->fullBit(oldp+124,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset)); - bufp->fullBit(oldp+125,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request)); - bufp->fullBit(oldp+126,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request)); - bufp->fullBit(oldp+127,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request)); - bufp->fullBit(oldp+128,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request)); - bufp->fullBit(oldp+129,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request)); - bufp->fullBit(oldp+130,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request)); - bufp->fullBit(oldp+131,(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset)); - bufp->fullBit(oldp+132,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb)); - bufp->fullBit(oldp+133,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid)); - bufp->fullSData(oldp+134,((((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS) - << 0xcU) | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request))),13); - bufp->fullSData(oldp+135,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request),12); - bufp->fullBit(oldp+136,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS)); - bufp->fullBit(oldp+137,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel)); - bufp->fullBit(oldp+138,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)); - bufp->fullBit(oldp+139,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+140,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+141,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+142,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+143,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+144,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+145,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+146,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+147,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+148,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+149,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+150,(vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+151,(vlSelf->main__DOT__wbu_xbar__DOT__m_stall)); - bufp->fullBit(oldp+152,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)); - bufp->fullBit(oldp+153,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall)); - bufp->fullBit(oldp+154,((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall))))); - bufp->fullBit(oldp+155,(vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+156,(vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+157,(vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant)); - bufp->fullBit(oldp+158,(vlSelf->main__DOT__emmcscope_int)); - bufp->fullBit(oldp+159,(vlSelf->main__DOT__sdioscope_int)); - bufp->fullBit(oldp+160,(vlSelf->main__DOT__emmc_int)); - bufp->fullBit(oldp+161,(vlSelf->main__DOT__sdcard_int)); - bufp->fullBit(oldp+162,((1U & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - >> 5U)))); - bufp->fullBit(oldp+163,((1U & (~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow))))); - bufp->fullBit(oldp+164,((1U & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - >> 5U)))); - bufp->fullBit(oldp+165,((1U & (~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow))))); - bufp->fullBit(oldp+166,(vlSelf->main__DOT__i2cscope_int)); - bufp->fullBit(oldp+167,(vlSelf->main__DOT__gpio_int)); - bufp->fullBit(oldp+168,(vlSelf->main__DOT__spio_int)); - bufp->fullBit(oldp+169,(vlSelf->main__DOT__r_sirefclk_en)); - bufp->fullIData(oldp+170,(vlSelf->main__DOT__r_sirefclk_data),30); - bufp->fullBit(oldp+171,(vlSelf->main__DOT__w_sirefclk_unused_stb)); - bufp->fullBit(oldp+172,(vlSelf->main__DOT__r_sirefclk_ack)); - bufp->fullBit(oldp+173,((1U & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid))))); - bufp->fullBit(oldp+174,(vlSelf->main__DOT__i2c_valid)); - bufp->fullBit(oldp+175,(vlSelf->main__DOT__i2c_ready)); - bufp->fullBit(oldp+176,(vlSelf->main__DOT__i2c_last)); - bufp->fullCData(oldp+177,(vlSelf->main__DOT__i2c_data),8); - bufp->fullCData(oldp+178,(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid),2); - bufp->fullIData(oldp+179,((((IData)(vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3) - << 0x1fU) | vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4)),32); - bufp->fullBit(oldp+180,(vlSelf->main__DOT__w_console_rx_stb)); - bufp->fullBit(oldp+181,((1U & (~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow))))); - bufp->fullBit(oldp+182,(vlSelf->main__DOT__w_console_busy)); - bufp->fullCData(oldp+183,(vlSelf->main__DOT__w_console_rx_data),7); - bufp->fullCData(oldp+184,(vlSelf->main__DOT__w_console_tx_data),7); - bufp->fullIData(oldp+185,(vlSelf->main__DOT__uart_debug),32); - bufp->fullBit(oldp+186,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)); - bufp->fullBit(oldp+187,(vlSelf->main__DOT__raw_cpu_dbg_ack)); - bufp->fullSData(oldp+188,((((IData)(vlSelf->main__DOT__gpio_int) - << 0xfU) | (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0xeU) - | ((0x2000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0xdU)) - | ((0x1000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0xcU)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0xbU) - | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 0xaU) - | (((IData)(vlSelf->main__DOT__emmcscope_int) - << 9U) - | (IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0))))))))),16); - bufp->fullBit(oldp+189,(vlSelf->main__DOT__zip_cpu_int)); - bufp->fullCData(oldp+190,(vlSelf->main__DOT__wbu_rx_data),8); - bufp->fullCData(oldp+191,(vlSelf->main__DOT__genbus__DOT__ps_data),8); - bufp->fullBit(oldp+192,(vlSelf->main__DOT__wbu_rx_stb)); - bufp->fullBit(oldp+193,(vlSelf->main__DOT__genbus__DOT__ps_full)); - bufp->fullBit(oldp+194,(vlSelf->main__DOT__txv__DOT__r_busy)); - bufp->fullBit(oldp+195,(vlSelf->main__DOT__genbus__DOT__r_wdt_reset)); - bufp->fullCData(oldp+196,(vlSelf->main__DOT__w_led),8); - bufp->fullSData(oldp+197,((((IData)(vlSelf->main__DOT__spio_int) - << 9U) | ((0x100U & - ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - << 3U)) - | ((0x80U - & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - << 2U)) - | ((IData)(vlSelf->main__DOT__sdcard_int) - << 6U))))),15); - bufp->fullSData(oldp+198,((((IData)(vlSelf->main__DOT__gpio_int) - << 0xeU) | (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0xdU) - | ((0x1000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0xcU)) - | ((0x800U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0xbU)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0xaU) - | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 9U) - | ((IData)(vlSelf->main__DOT__emmcscope_int) - << 8U)))))))),15); - bufp->fullBit(oldp+199,(vlSelf->main__DOT__wbwide_i2cdma_cyc)); - bufp->fullBit(oldp+200,(vlSelf->main__DOT__wbwide_i2cdma_stb)); - bufp->fullIData(oldp+201,(vlSelf->main__DOT__wbwide_i2cdma_addr),22); - bufp->fullWData(oldp+202,(vlSelf->main__DOT__wbwide_i2cdma_data),512); - bufp->fullQData(oldp+218,(vlSelf->main__DOT__wbwide_i2cdma_sel),64); - bufp->fullBit(oldp+220,((1U & (IData)(vlSelf->__VdfgTmp_h503d14d1__0)))); - bufp->fullBit(oldp+221,((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))); - bufp->fullBit(oldp+222,((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))); - __Vtemp_h053daff0__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0U]; - __Vtemp_h053daff0__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[1U]; - __Vtemp_h053daff0__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[2U]; - __Vtemp_h053daff0__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[3U]; - __Vtemp_h053daff0__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[4U]; - __Vtemp_h053daff0__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[5U]; - __Vtemp_h053daff0__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[6U]; - __Vtemp_h053daff0__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[7U]; - __Vtemp_h053daff0__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[8U]; - __Vtemp_h053daff0__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[9U]; - __Vtemp_h053daff0__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xaU]; - __Vtemp_h053daff0__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xbU]; - __Vtemp_h053daff0__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xcU]; - __Vtemp_h053daff0__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xdU]; - __Vtemp_h053daff0__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xeU]; - __Vtemp_h053daff0__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xfU]; - bufp->fullWData(oldp+223,(__Vtemp_h053daff0__0),512); - bufp->fullBit(oldp+239,(vlSelf->main__DOT__wbwide_i2cm_cyc)); - bufp->fullBit(oldp+240,(vlSelf->main__DOT__wbwide_i2cm_stb)); - bufp->fullIData(oldp+241,(vlSelf->main__DOT__wbwide_i2cm_addr),22); - bufp->fullBit(oldp+242,((1U & ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 1U)))); - bufp->fullBit(oldp+243,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U)))); - bufp->fullBit(oldp+244,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 1U)))); - __Vtemp_h3711b190__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x10U]; - __Vtemp_h3711b190__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x11U]; - __Vtemp_h3711b190__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x12U]; - __Vtemp_h3711b190__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x13U]; - __Vtemp_h3711b190__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x14U]; - __Vtemp_h3711b190__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x15U]; - __Vtemp_h3711b190__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x16U]; - __Vtemp_h3711b190__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x17U]; - __Vtemp_h3711b190__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x18U]; - __Vtemp_h3711b190__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x19U]; - __Vtemp_h3711b190__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1aU]; - __Vtemp_h3711b190__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1bU]; - __Vtemp_h3711b190__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1cU]; - __Vtemp_h3711b190__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1dU]; - __Vtemp_h3711b190__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1eU]; - __Vtemp_h3711b190__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1fU]; - bufp->fullWData(oldp+245,(__Vtemp_h3711b190__0),512); - bufp->fullBit(oldp+261,(vlSelf->main__DOT__wbwide_zip_cyc)); - bufp->fullBit(oldp+262,(vlSelf->main__DOT__wbwide_zip_stb)); - bufp->fullBit(oldp+263,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__cpu_we) - : (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)))))); - bufp->fullIData(oldp+264,(vlSelf->main__DOT__wbwide_zip_addr),22); - if (vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) { - __Vtemp_h58eb921b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - __Vtemp_h58eb921b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U]; - __Vtemp_h58eb921b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U]; - __Vtemp_h58eb921b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U]; - __Vtemp_h58eb921b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U]; - __Vtemp_h58eb921b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U]; - __Vtemp_h58eb921b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U]; - __Vtemp_h58eb921b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U]; - __Vtemp_h58eb921b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U]; - __Vtemp_h58eb921b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U]; - __Vtemp_h58eb921b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU]; - __Vtemp_h58eb921b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU]; - __Vtemp_h58eb921b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU]; - __Vtemp_h58eb921b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU]; - __Vtemp_h58eb921b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU]; - __Vtemp_h58eb921b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU]; - } else { - __Vtemp_h58eb921b__0[0U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0U]; - __Vtemp_h58eb921b__0[1U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[1U]; - __Vtemp_h58eb921b__0[2U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[2U]; - __Vtemp_h58eb921b__0[3U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[3U]; - __Vtemp_h58eb921b__0[4U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[4U]; - __Vtemp_h58eb921b__0[5U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[5U]; - __Vtemp_h58eb921b__0[6U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[6U]; - __Vtemp_h58eb921b__0[7U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[7U]; - __Vtemp_h58eb921b__0[8U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[8U]; - __Vtemp_h58eb921b__0[9U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[9U]; - __Vtemp_h58eb921b__0[0xaU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xaU]; - __Vtemp_h58eb921b__0[0xbU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xbU]; - __Vtemp_h58eb921b__0[0xcU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xcU]; - __Vtemp_h58eb921b__0[0xdU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xdU]; - __Vtemp_h58eb921b__0[0xeU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xeU]; - __Vtemp_h58eb921b__0[0xfU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xfU]; - } - bufp->fullWData(oldp+265,(__Vtemp_h58eb921b__0),512); - bufp->fullQData(oldp+281,(((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel))),64); - bufp->fullBit(oldp+283,((1U & ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 2U)))); - bufp->fullBit(oldp+284,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U)))); - bufp->fullBit(oldp+285,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 2U)))); - __Vtemp_hc1d82fb0__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U]; - __Vtemp_hc1d82fb0__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U]; - __Vtemp_hc1d82fb0__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U]; - __Vtemp_hc1d82fb0__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U]; - __Vtemp_hc1d82fb0__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U]; - __Vtemp_hc1d82fb0__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U]; - __Vtemp_hc1d82fb0__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U]; - __Vtemp_hc1d82fb0__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U]; - __Vtemp_hc1d82fb0__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U]; - __Vtemp_hc1d82fb0__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U]; - __Vtemp_hc1d82fb0__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU]; - __Vtemp_hc1d82fb0__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU]; - __Vtemp_hc1d82fb0__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU]; - __Vtemp_hc1d82fb0__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU]; - __Vtemp_hc1d82fb0__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU]; - __Vtemp_hc1d82fb0__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU]; - bufp->fullWData(oldp+286,(__Vtemp_hc1d82fb0__0),512); - bufp->fullBit(oldp+302,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)); - bufp->fullBit(oldp+303,(vlSelf->main__DOT__wbwide_wbu_arbiter_stb)); - bufp->fullBit(oldp+304,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we)); - bufp->fullIData(oldp+305,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr),22); - bufp->fullWData(oldp+306,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data),512); - bufp->fullQData(oldp+322,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel),64); - bufp->fullBit(oldp+324,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)); - bufp->fullBit(oldp+325,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U)))); - bufp->fullBit(oldp+326,((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 3U)))); - __Vtemp_hc1851150__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x30U]; - __Vtemp_hc1851150__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x31U]; - __Vtemp_hc1851150__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x32U]; - __Vtemp_hc1851150__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x33U]; - __Vtemp_hc1851150__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x34U]; - __Vtemp_hc1851150__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x35U]; - __Vtemp_hc1851150__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x36U]; - __Vtemp_hc1851150__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x37U]; - __Vtemp_hc1851150__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x38U]; - __Vtemp_hc1851150__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x39U]; - __Vtemp_hc1851150__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3aU]; - __Vtemp_hc1851150__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3bU]; - __Vtemp_hc1851150__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3cU]; - __Vtemp_hc1851150__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3dU]; - __Vtemp_hc1851150__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3eU]; - __Vtemp_hc1851150__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3fU]; - bufp->fullWData(oldp+327,(__Vtemp_hc1851150__0),512); - bufp->fullBit(oldp+343,(vlSelf->main__DOT__wbwide_wbdown_stall)); - bufp->fullBit(oldp+344,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack)); - bufp->fullWData(oldp+345,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data),512); - bufp->fullBit(oldp+361,(vlSelf->main__DOT__wbwide_bkram_ack)); - bufp->fullWData(oldp+362,(vlSelf->main__DOT__wbwide_bkram_idata),512); - bufp->fullBit(oldp+378,(vlSelf->main__DOT__wb32_wbdown_stb)); - bufp->fullBit(oldp+379,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_we)); - bufp->fullCData(oldp+380,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr),8); - bufp->fullIData(oldp+381,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xfU]),32); - bufp->fullCData(oldp+382,((0xfU & (IData)((vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel - >> 0x3cU)))),4); - bufp->fullBit(oldp+383,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)); - bufp->fullBit(oldp+384,(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - bufp->fullIData(oldp+385,(vlSelf->main__DOT__wb32_wbdown_idata),32); - bufp->fullIData(oldp+386,((((~ (IData)(vlSelf->main__DOT__r_sirefclk_en)) - << 0x1fU) | vlSelf->main__DOT__r_sirefclk_data)),32); - bufp->fullBit(oldp+387,(vlSelf->main__DOT__wb32_spio_ack)); - bufp->fullIData(oldp+388,((((IData)(vlSelf->main__DOT__spioi__DOT__led_demo) - << 0x18U) | (((IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn) - << 0x10U) - | (((IData)(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw) - << 8U) - | (IData)(vlSelf->main__DOT__spioi__DOT__r_led))))),32); - bufp->fullBit(oldp+389,(vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack)); - bufp->fullIData(oldp+390,(vlSelf->main__DOT__emmcscopei__DOT__o_bus_data),32); - bufp->fullBit(oldp+391,(vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack)); - bufp->fullIData(oldp+392,(vlSelf->main__DOT__i2cscopei__DOT__o_bus_data),32); - bufp->fullBit(oldp+393,(vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack)); - bufp->fullIData(oldp+394,(vlSelf->main__DOT__sdioscopei__DOT__o_bus_data),32); - bufp->fullBit(oldp+395,(vlSelf->main__DOT__wb32_i2cs_ack)); - bufp->fullIData(oldp+396,(vlSelf->main__DOT__i2ci__DOT__bus_read_data),32); - bufp->fullBit(oldp+397,(vlSelf->main__DOT__wb32_i2cdma_ack)); - bufp->fullIData(oldp+398,(vlSelf->main__DOT__wb32_i2cdma_idata),32); - bufp->fullBit(oldp+399,(vlSelf->main__DOT__wb32_uart_ack)); - bufp->fullIData(oldp+400,(vlSelf->main__DOT__wb32_uart_idata),32); - bufp->fullBit(oldp+401,(vlSelf->main__DOT__wb32_emmc_ack)); - bufp->fullIData(oldp+402,(vlSelf->main__DOT__wb32_emmc_idata),32); - bufp->fullBit(oldp+403,(vlSelf->main__DOT__wb32_fan_ack)); - bufp->fullIData(oldp+404,(vlSelf->main__DOT__wb32_fan_idata),32); - bufp->fullBit(oldp+405,(vlSelf->main__DOT__wb32_sdcard_ack)); - bufp->fullIData(oldp+406,(vlSelf->main__DOT__wb32_sdcard_idata),32); - bufp->fullBit(oldp+407,(vlSelf->main__DOT__r_wb32_sio_ack)); - bufp->fullIData(oldp+408,(vlSelf->main__DOT__r_wb32_sio_data),32); - bufp->fullBit(oldp+409,(vlSelf->main__DOT__r_cfg_ack)); - bufp->fullBit(oldp+410,(vlSelf->main__DOT__wbu_cyc)); - bufp->fullBit(oldp+411,(vlSelf->main__DOT__wbu_stb)); - bufp->fullBit(oldp+412,(vlSelf->main__DOT__wbu_we)); - bufp->fullIData(oldp+413,((0x7ffffffU & vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr)),27); - bufp->fullIData(oldp+414,(vlSelf->main__DOT__wbu_data),32); - bufp->fullBit(oldp+415,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)); - bufp->fullBit(oldp+416,(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - bufp->fullBit(oldp+417,(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - bufp->fullIData(oldp+418,(vlSelf->main__DOT__wbu_idata),32); - bufp->fullBit(oldp+419,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)))); - bufp->fullBit(oldp+420,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb)))); - bufp->fullBit(oldp+421,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe)))); - bufp->fullIData(oldp+422,((0x7ffffffU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr))),27); - bufp->fullIData(oldp+423,((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata)),32); - bufp->fullCData(oldp+424,((0xfU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel))),4); - bufp->fullBit(oldp+425,(vlSelf->main__DOT__wbu_wbu_arbiter_stall)); - bufp->fullBit(oldp+426,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack)); - bufp->fullBit(oldp+427,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err)); - bufp->fullIData(oldp+428,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xfU]),32); - bufp->fullBit(oldp+429,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - >> 1U)))); - bufp->fullBit(oldp+430,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - >> 1U)))); - bufp->fullBit(oldp+431,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe) - >> 1U)))); - bufp->fullIData(oldp+432,((0x7ffffffU & (IData)( - (vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - >> 0x1bU)))),27); - bufp->fullIData(oldp+433,((IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - >> 0x20U))),32); - bufp->fullCData(oldp+434,((0xfU & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel) - >> 4U))),4); - bufp->fullIData(oldp+435,(vlSelf->main__DOT__wbu_zip_idata),32); - bufp->fullIData(oldp+436,((0x3fffffffU & vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr)),30); - bufp->fullBit(oldp+437,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_wstb)); - bufp->fullBit(oldp+438,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_stb)); - bufp->fullWData(oldp+439,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data),512); - bufp->fullSData(oldp+455,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr),14); - bufp->fullQData(oldp+456,(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel),64); - bufp->fullIData(oldp+458,(vlSelf->main__DOT__bkrami__DOT__WRITE_TO_MEMORY__DOT__ik),32); - bufp->fullIData(oldp+459,(vlSelf->main__DOT__r_sirefclk_data),32); - bufp->fullIData(oldp+460,(vlSelf->main__DOT__clock_generator__DOT__counter[0]),32); - bufp->fullIData(oldp+461,(vlSelf->main__DOT__clock_generator__DOT__counter[1]),32); - bufp->fullIData(oldp+462,(vlSelf->main__DOT__clock_generator__DOT__counter[2]),32); - bufp->fullIData(oldp+463,(vlSelf->main__DOT__clock_generator__DOT__counter[3]),32); - bufp->fullIData(oldp+464,(vlSelf->main__DOT__clock_generator__DOT__counter[4]),32); - bufp->fullIData(oldp+465,(vlSelf->main__DOT__clock_generator__DOT__counter[5]),32); - bufp->fullIData(oldp+466,(vlSelf->main__DOT__clock_generator__DOT__counter[6]),32); - bufp->fullIData(oldp+467,(vlSelf->main__DOT__clock_generator__DOT__counter[7]),32); - bufp->fullIData(oldp+468,(vlSelf->main__DOT__clock_generator__DOT__r_delay),32); - bufp->fullIData(oldp+469,(vlSelf->main__DOT__clock_generator__DOT__times_three),32); - bufp->fullIData(oldp+470,(vlSelf->main__DOT__clock_generator__DOT__times_five),32); - bufp->fullIData(oldp+471,(vlSelf->main__DOT__clock_generator__DOT__times_seven),32); - bufp->fullBit(oldp+472,(vlSelf->main__DOT__console__DOT__rx_uart_reset)); - bufp->fullBit(oldp+473,(((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__w_console_rx_stb)))); - bufp->fullCData(oldp+474,(vlSelf->main__DOT__console__DOT__rxf_wb_data),7); - bufp->fullSData(oldp+475,(vlSelf->main__DOT__console__DOT__rxf_status),16); - bufp->fullBit(oldp+476,(vlSelf->main__DOT__console__DOT__rxf_wb_read)); - bufp->fullIData(oldp+477,(((((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__w_console_rx_stb)) - << 0xcU) | (((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow) - << 8U) - | (IData)(vlSelf->main__DOT__console__DOT__rxf_wb_data)))),32); - bufp->fullBit(oldp+478,(((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__console__DOT__txf_wb_write)))); - bufp->fullSData(oldp+479,(vlSelf->main__DOT__console__DOT__txf_status),16); - bufp->fullBit(oldp+480,(vlSelf->main__DOT__console__DOT__txf_wb_write)); - bufp->fullBit(oldp+481,(vlSelf->main__DOT__console__DOT__tx_uart_reset)); - bufp->fullCData(oldp+482,(vlSelf->main__DOT__console__DOT__txf_wb_data),7); - bufp->fullIData(oldp+483,((((IData)(vlSelf->__VdfgTmp_ha46ae6a3__0) - << 0xdU) | ((((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__console__DOT__txf_wb_write)) - << 0xcU) - | ((0x400U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)) - << 0xaU)) - | (((IData)(vlSelf->main__DOT__console__DOT____VdfgTmp_h60af6732__0) - << 8U) - | ((IData)(vlSelf->main__DOT__console__DOT____VdfgTmp_h60af6732__0) - ? (IData)(vlSelf->main__DOT__console__DOT__txf_wb_data) - : 0U)))))),32); - bufp->fullIData(oldp+484,((((IData)(vlSelf->main__DOT__console__DOT__txf_status) - << 0x10U) | (IData)(vlSelf->main__DOT__console__DOT__rxf_status))),32); - bufp->fullCData(oldp+485,(vlSelf->main__DOT__console__DOT__r_wb_addr),2); - bufp->fullBit(oldp+486,(vlSelf->main__DOT__console__DOT__r_wb_ack)); - bufp->fullCData(oldp+487,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_data),7); - bufp->fullCData(oldp+488,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__last_write),7); - bufp->fullCData(oldp+489,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr),6); - bufp->fullCData(oldp+490,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr),6); - bufp->fullCData(oldp+491,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next),6); - bufp->fullBit(oldp+492,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow)); - bufp->fullBit(oldp+493,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)); - bufp->fullBit(oldp+494,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__osrc)); - bufp->fullCData(oldp+495,((0x3fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr)))),6); - bufp->fullCData(oldp+496,((0x3fU & ((IData)(2U) - + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr)))),6); - bufp->fullBit(oldp+497,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write)); - bufp->fullBit(oldp+498,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read)); - bufp->fullCData(oldp+499,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill),6); - bufp->fullSData(oldp+500,(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill),10); - bufp->fullBit(oldp+501,(vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6)); - bufp->fullCData(oldp+502,(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_data),7); - bufp->fullCData(oldp+503,(vlSelf->main__DOT__console__DOT__txfifo__DOT__last_write),7); - bufp->fullCData(oldp+504,(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr),6); - bufp->fullCData(oldp+505,(vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr),6); - bufp->fullCData(oldp+506,(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next),6); - bufp->fullBit(oldp+507,(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)); - bufp->fullBit(oldp+508,(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)); - bufp->fullBit(oldp+509,(vlSelf->main__DOT__console__DOT__txfifo__DOT__osrc)); - bufp->fullCData(oldp+510,((0x3fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr)))),6); - bufp->fullCData(oldp+511,((0x3fU & ((IData)(2U) - + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr)))),6); - bufp->fullBit(oldp+512,(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write)); - bufp->fullBit(oldp+513,(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read)); - bufp->fullCData(oldp+514,(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill),6); - bufp->fullSData(oldp+515,(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill),10); - bufp->fullBit(oldp+516,(vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3)); - bufp->fullBit(oldp+517,(vlSelf->main__DOT__emmcscopei__DOT__read_address)); - bufp->fullSData(oldp+518,(vlSelf->main__DOT__emmcscopei__DOT__raddr),12); - bufp->fullSData(oldp+519,(vlSelf->main__DOT__emmcscopei__DOT__waddr),12); - bufp->fullBit(oldp+520,((1U & (~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U))))); - bufp->fullBit(oldp+521,((1U & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 1U)))); - bufp->fullBit(oldp+522,((1U & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config)))); - bufp->fullCData(oldp+523,(vlSelf->main__DOT__emmcscopei__DOT__br_config),3); - bufp->fullIData(oldp+524,(vlSelf->main__DOT__emmcscopei__DOT__br_holdoff),20); - bufp->fullIData(oldp+525,(vlSelf->main__DOT__emmcscopei__DOT__holdoff_counter),20); - bufp->fullBit(oldp+526,(vlSelf->main__DOT__emmcscopei__DOT__dr_triggered)); - bufp->fullBit(oldp+527,(vlSelf->main__DOT__emmcscopei__DOT__dr_primed)); - bufp->fullBit(oldp+528,(vlSelf->main__DOT__emmcscopei__DOT__dw_trigger)); - bufp->fullBit(oldp+529,(vlSelf->main__DOT__emmcscopei__DOT__dr_stopped)); - bufp->fullCData(oldp+530,(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe),5); - bufp->fullBit(oldp+531,((1U & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - >> 4U)))); - bufp->fullIData(oldp+532,(vlSelf->main__DOT__emmcscopei__DOT__ck_addr),31); - bufp->fullIData(oldp+533,(vlSelf->main__DOT__emmcscopei__DOT__qd_data),31); - bufp->fullBit(oldp+534,(vlSelf->main__DOT__emmcscopei__DOT__dr_force_write)); - bufp->fullBit(oldp+535,(vlSelf->main__DOT__emmcscopei__DOT__dr_run_timeout)); - bufp->fullBit(oldp+536,(vlSelf->main__DOT__emmcscopei__DOT__new_data)); - bufp->fullBit(oldp+537,(vlSelf->main__DOT__emmcscopei__DOT__dr_force_inhibit)); - bufp->fullBit(oldp+538,(vlSelf->main__DOT__emmcscopei__DOT__imm_adr)); - bufp->fullBit(oldp+539,(vlSelf->main__DOT__emmcscopei__DOT__lst_adr)); - bufp->fullIData(oldp+540,(vlSelf->main__DOT__emmcscopei__DOT__lst_val),31); - bufp->fullIData(oldp+541,(vlSelf->main__DOT__emmcscopei__DOT__imm_val),31); - bufp->fullBit(oldp+542,(vlSelf->main__DOT__emmcscopei__DOT__record_ce)); - bufp->fullIData(oldp+543,(vlSelf->main__DOT__emmcscopei__DOT__r_data),32); - bufp->fullBit(oldp+544,(vlSelf->main__DOT__emmcscopei__DOT__br_pre_wb_ack)); - bufp->fullSData(oldp+545,(vlSelf->main__DOT__emmcscopei__DOT__this_addr),12); - bufp->fullIData(oldp+546,(vlSelf->main__DOT__emmcscopei__DOT__nxt_mem),32); - bufp->fullBit(oldp+547,(vlSelf->main__DOT__emmcscopei__DOT__br_level_interrupt)); - bufp->fullBit(oldp+548,(vlSelf->main__DOT__genbus__DOT__soft_reset)); - bufp->fullBit(oldp+549,(vlSelf->main__DOT__genbus__DOT__rx_valid)); - bufp->fullCData(oldp+550,((0x7fU & (IData)(vlSelf->main__DOT__wbu_rx_data))),8); - bufp->fullBit(oldp+551,(vlSelf->main__DOT__genbus__DOT__in_stb)); - bufp->fullBit(oldp+552,(((IData)(vlSelf->main__DOT__genbus__DOT__rx_valid) - | ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT__in_stb)) - | (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))) - | (0U < (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len)))))); - bufp->fullQData(oldp+553,(vlSelf->main__DOT__genbus__DOT__in_word),36); - bufp->fullBit(oldp+555,(vlSelf->main__DOT__genbus__DOT__wbu_tx_stb)); - bufp->fullCData(oldp+556,(vlSelf->main__DOT__genbus__DOT__wbu_tx_data),8); - bufp->fullBit(oldp+557,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)); - bufp->fullQData(oldp+558,(vlSelf->main__DOT__genbus__DOT__ififo_codword),36); - bufp->fullBit(oldp+560,(vlSelf->main__DOT__genbus__DOT__exec_stb)); - bufp->fullQData(oldp+561,(vlSelf->main__DOT__genbus__DOT__exec_word),36); - bufp->fullBit(oldp+563,(vlSelf->main__DOT__genbus__DOT__ofifo_rd)); - bufp->fullQData(oldp+564,(vlSelf->main__DOT__genbus__DOT__ofifo_codword),36); - bufp->fullBit(oldp+566,((((IData)(vlSelf->main__DOT__genbus__DOT__exec_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd)) - & (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow))) - | ((~ (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)) - & (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd))))); - bufp->fullBit(oldp+567,(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)); - bufp->fullBit(oldp+568,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy)); - bufp->fullIData(oldp+569,(vlSelf->main__DOT__genbus__DOT__r_wdt_timer),19); - bufp->fullBit(oldp+570,(((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy) - & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb)))); - bufp->fullBit(oldp+571,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb)); - bufp->fullBit(oldp+572,(((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__r_active)))); - bufp->fullSData(oldp+573,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr),11); - bufp->fullSData(oldp+574,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr),11); - bufp->fullSData(oldp+575,((0x7ffU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr)))),11); - bufp->fullSData(oldp+576,((0x7ffU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr)))),11); - bufp->fullBit(oldp+577,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow)); - bufp->fullBit(oldp+578,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow)); - bufp->fullBit(oldp+579,((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow))))); - bufp->fullBit(oldp+580,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write)); - bufp->fullBit(oldp+581,(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read)); - bufp->fullBit(oldp+582,((((IData)(vlSelf->main__DOT__genbus__DOT__in_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd)) - & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow))) - | ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)) - & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd))))); - bufp->fullBit(oldp+583,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd)); - bufp->fullCData(oldp+584,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr),7); - bufp->fullCData(oldp+585,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr),7); - bufp->fullCData(oldp+586,((0x7fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr)))),7); - bufp->fullCData(oldp+587,((0x7fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr)))),7); - bufp->fullBit(oldp+588,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow)); - bufp->fullBit(oldp+589,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow)); - bufp->fullBit(oldp+590,((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow))))); - bufp->fullBit(oldp+591,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write)); - bufp->fullBit(oldp+592,(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read)); - bufp->fullBit(oldp+593,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb)); - bufp->fullBit(oldp+594,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid)); - bufp->fullCData(oldp+595,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits),6); - bufp->fullBit(oldp+596,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb)); - bufp->fullBit(oldp+597,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy)); - bufp->fullBit(oldp+598,(((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - | (0U < (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len))))); - bufp->fullQData(oldp+599,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word),36); - bufp->fullBit(oldp+601,((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)))); - bufp->fullBit(oldp+602,(((IData)(vlSelf->main__DOT__genbus__DOT__in_stb) - | (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))))); - bufp->fullCData(oldp+603,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr),8); - bufp->fullQData(oldp+604,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word),36); - bufp->fullCData(oldp+606,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cmd_addr),8); - bufp->fullIData(oldp+607,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr),25); - bufp->fullIData(oldp+608,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr),32); - bufp->fullSData(oldp+609,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__rd_len),10); - bufp->fullIData(oldp+610,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cword),32); - bufp->fullCData(oldp+611,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb),3); - bufp->fullBit(oldp+612,((3U == (7U & (IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x21U)))))); - bufp->fullCData(oldp+613,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len),3); - bufp->fullCData(oldp+614,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len),3); - bufp->fullCData(oldp+615,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw),2); - bufp->fullBit(oldp+616,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb)); - bufp->fullQData(oldp+617,(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg),36); - bufp->fullIData(oldp+619,((((IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x1fU)) - << 0x1eU) | (0x3fffffffU - & (IData)(vlSelf->main__DOT__genbus__DOT__ififo_codword)))),32); - bufp->fullCData(oldp+620,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state),2); - bufp->fullSData(oldp+621,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed),10); - bufp->fullSData(oldp+622,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len),10); - bufp->fullBit(oldp+623,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_inc)); - bufp->fullBit(oldp+624,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_new_addr)); - bufp->fullBit(oldp+625,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_read_request)); - bufp->fullBit(oldp+626,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_ack)); - bufp->fullBit(oldp+627,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__zero_acks)); - bufp->fullIData(oldp+628,(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr),32); - bufp->fullBit(oldp+629,(vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy)); - bufp->fullBit(oldp+630,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)); - bufp->fullBit(oldp+631,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)); - bufp->fullBit(oldp+632,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb)); - bufp->fullBit(oldp+633,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy)); - bufp->fullBit(oldp+634,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy)); - bufp->fullBit(oldp+635,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy)); - bufp->fullBit(oldp+636,(((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb))))); - bufp->fullBit(oldp+637,(((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))); - bufp->fullBit(oldp+638,(((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl)))))); - bufp->fullQData(oldp+639,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword),36); - bufp->fullQData(oldp+641,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword),36); - bufp->fullCData(oldp+643,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits),7); - bufp->fullCData(oldp+644,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_bits),7); - bufp->fullBit(oldp+645,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__r_active)); - bufp->fullBit(oldp+646,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid)); - bufp->fullQData(oldp+647,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__a_addrword),36); - bufp->fullIData(oldp+649,((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword)),32); - bufp->fullCData(oldp+650,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck),4); - bufp->fullBit(oldp+651,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)); - bufp->fullBit(oldp+652,(((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)))); - bufp->fullQData(oldp+653,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word),36); - bufp->fullSData(oldp+655,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr),10); - bufp->fullBit(oldp+656,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled)); - bufp->fullSData(oldp+657,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr),10); - bufp->fullBit(oldp+658,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch)); - bufp->fullBit(oldp+659,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch)); - bufp->fullBit(oldp+660,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__vaddr)); - bufp->fullIData(oldp+661,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__cword),32); - bufp->fullSData(oldp+662,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__maddr),10); - bufp->fullBit(oldp+663,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched)); - bufp->fullBit(oldp+664,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__zmatch)); - bufp->fullBit(oldp+665,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__hmatch)); - bufp->fullSData(oldp+666,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld),10); - bufp->fullCData(oldp+667,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_hlfd),3); - bufp->fullSData(oldp+668,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr),10); - bufp->fullBit(oldp+669,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table)); - bufp->fullBit(oldp+670,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table)); - bufp->fullBit(oldp+671,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match)); - bufp->fullBit(oldp+672,((1U & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld) - >> 9U)))); - bufp->fullBit(oldp+673,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy)); - bufp->fullBit(oldp+674,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request)); - bufp->fullBit(oldp+675,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent)); - bufp->fullBit(oldp+676,(((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state)) - & (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter - >> 0x15U)))); - bufp->fullBit(oldp+677,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state)); - bufp->fullIData(oldp+678,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter),22); - bufp->fullCData(oldp+679,(((0U == (7U & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x21U)))) - ? 1U : ((2U == (0xfU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x20U)))) - ? 6U : (7U - & ((3U - == - (0xfU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x20U)))) - ? - ((IData)(2U) - + - (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x1eU)))) - : - ((1U - == - (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x22U)))) - ? 2U - : - ((2U - == - (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x22U)))) - ? 1U - : 6U))))))),3); - bufp->fullCData(oldp+680,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len),3); - bufp->fullIData(oldp+681,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word),30); - bufp->fullBit(oldp+682,(((IData)(vlSelf->main__DOT__wbu_cyc) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy))))); - bufp->fullBit(oldp+683,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl)); - bufp->fullBit(oldp+684,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl)); - bufp->fullBit(oldp+685,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__full_line)); - bufp->fullBit(oldp+686,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy)); - bufp->fullCData(oldp+687,(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen),7); - bufp->fullSData(oldp+688,(vlSelf->main__DOT__gpioi__DOT__r_gpio),16); - bufp->fullSData(oldp+689,(vlSelf->main__DOT__gpioi__DOT__x_gpio),16); - bufp->fullSData(oldp+690,(vlSelf->main__DOT__gpioi__DOT__q_gpio),16); - bufp->fullBit(oldp+691,(vlSelf->main__DOT__i2ci__DOT__r_halted)); - bufp->fullBit(oldp+692,(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc)); - bufp->fullIData(oldp+693,(vlSelf->main__DOT__i2ci__DOT__pf_jump_addr),28); - bufp->fullBit(oldp+694,(vlSelf->main__DOT__i2ci__DOT__pf_valid)); - bufp->fullBit(oldp+695,(vlSelf->main__DOT__i2ci__DOT__pf_ready)); - bufp->fullCData(oldp+696,(vlSelf->main__DOT__i2ci__DOT__pf_insn),8); - bufp->fullIData(oldp+697,(vlSelf->main__DOT__i2ci__DOT__pf_insn_addr),28); - bufp->fullBit(oldp+698,(vlSelf->main__DOT__i2ci__DOT__pf_illegal)); - bufp->fullBit(oldp+699,(vlSelf->main__DOT__i2ci__DOT__half_valid)); - bufp->fullBit(oldp+700,(vlSelf->main__DOT__i2ci__DOT__imm_cycle)); - bufp->fullBit(oldp+701,(vlSelf->main__DOT__i2ci__DOT__insn_ready)); - bufp->fullBit(oldp+702,(vlSelf->main__DOT__i2ci__DOT__half_ready)); - bufp->fullBit(oldp+703,(vlSelf->main__DOT__i2ci__DOT__i2c_abort)); - bufp->fullBit(oldp+704,(vlSelf->main__DOT__i2ci__DOT__insn_valid)); - bufp->fullSData(oldp+705,(vlSelf->main__DOT__i2ci__DOT__insn),12); - bufp->fullCData(oldp+706,(vlSelf->main__DOT__i2ci__DOT__half_insn),4); - bufp->fullBit(oldp+707,(vlSelf->main__DOT__i2ci__DOT__i2c_ckedge)); - bufp->fullBit(oldp+708,(vlSelf->main__DOT__i2ci__DOT__i2c_stretch)); - bufp->fullSData(oldp+709,(vlSelf->main__DOT__i2ci__DOT__i2c_ckcount),12); - bufp->fullSData(oldp+710,(vlSelf->main__DOT__i2ci__DOT__ckcount),12); - bufp->fullIData(oldp+711,(vlSelf->main__DOT__i2ci__DOT__abort_address),28); - bufp->fullIData(oldp+712,(vlSelf->main__DOT__i2ci__DOT__jump_target),28); - bufp->fullBit(oldp+713,(vlSelf->main__DOT__i2ci__DOT__r_wait)); - bufp->fullBit(oldp+714,(vlSelf->main__DOT__i2ci__DOT__soft_halt_request)); - bufp->fullBit(oldp+715,(vlSelf->main__DOT__i2ci__DOT__r_err)); - bufp->fullBit(oldp+716,(vlSelf->main__DOT__i2ci__DOT__r_aborted)); - bufp->fullBit(oldp+717,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual)); - bufp->fullBit(oldp+718,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda)); - bufp->fullBit(oldp+719,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl)); - bufp->fullBit(oldp+720,(((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - | (IData)(vlSelf->main__DOT__i2ci__DOT__r_wait)))); - bufp->fullBit(oldp+721,(vlSelf->main__DOT__i2ci__DOT__w_sda)); - bufp->fullBit(oldp+722,(vlSelf->main__DOT__i2ci__DOT__w_scl)); - bufp->fullBit(oldp+723,(vlSelf->main__DOT__i2ci__DOT__ovw_ready)); - bufp->fullBit(oldp+724,(vlSelf->main__DOT__i2ci__DOT__s_tvalid)); - bufp->fullSData(oldp+725,(vlSelf->main__DOT__i2ci__DOT__ovw_data),10); - bufp->fullBit(oldp+726,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl)); - bufp->fullBit(oldp+727,(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda)); - bufp->fullBit(oldp+728,(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__mid_axis_pkt)); - bufp->fullCData(oldp+729,(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__r_channel),2); - bufp->fullSData(oldp+730,((0x7ffU & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))),11); - bufp->fullBit(oldp+731,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte)); - bufp->fullBit(oldp+732,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir)); - bufp->fullBit(oldp+733,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack)); - bufp->fullCData(oldp+734,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state),4); - bufp->fullCData(oldp+735,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits),3); - bufp->fullCData(oldp+736,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg),8); - bufp->fullBit(oldp+737,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_scl)); - bufp->fullBit(oldp+738,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_sda)); - bufp->fullBit(oldp+739,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)); - bufp->fullBit(oldp+740,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda)); - bufp->fullBit(oldp+741,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_scl)); - bufp->fullBit(oldp+742,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_sda)); - bufp->fullBit(oldp+743,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__stop_bit)); - bufp->fullBit(oldp+744,(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy)); - bufp->fullBit(oldp+745,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__last_stb)); - bufp->fullBit(oldp+746,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle)); - bufp->fullWData(oldp+747,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word),512); - bufp->fullBit(oldp+763,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid)); - bufp->fullCData(oldp+764,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight),2); - bufp->fullBit(oldp+765,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal)); - bufp->fullBit(oldp+766,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid)); - bufp->fullWData(oldp+767,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn),512); - bufp->fullWData(oldp+783,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted),512); - bufp->fullCData(oldp+799,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count),7); - bufp->fullCData(oldp+800,(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift),6); - bufp->fullBit(oldp+801,(vlSelf->main__DOT__i2cscopei__DOT__read_address)); - bufp->fullSData(oldp+802,(vlSelf->main__DOT__i2cscopei__DOT__raddr),10); - bufp->fullSData(oldp+803,(vlSelf->main__DOT__i2cscopei__DOT__waddr),10); - bufp->fullBit(oldp+804,((1U & (~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U))))); - bufp->fullBit(oldp+805,((1U & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 1U)))); - bufp->fullBit(oldp+806,((1U & (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config)))); - bufp->fullCData(oldp+807,(vlSelf->main__DOT__i2cscopei__DOT__br_config),3); - bufp->fullIData(oldp+808,(vlSelf->main__DOT__i2cscopei__DOT__br_holdoff),20); - bufp->fullIData(oldp+809,(vlSelf->main__DOT__i2cscopei__DOT__holdoff_counter),20); - bufp->fullBit(oldp+810,(vlSelf->main__DOT__i2cscopei__DOT__dr_triggered)); - bufp->fullBit(oldp+811,(vlSelf->main__DOT__i2cscopei__DOT__dr_primed)); - bufp->fullBit(oldp+812,(vlSelf->main__DOT__i2cscopei__DOT__dw_trigger)); - bufp->fullBit(oldp+813,(vlSelf->main__DOT__i2cscopei__DOT__dr_stopped)); - bufp->fullCData(oldp+814,(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe),5); - bufp->fullBit(oldp+815,((1U & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - >> 4U)))); - bufp->fullIData(oldp+816,(vlSelf->main__DOT__i2cscopei__DOT__ck_addr),31); - bufp->fullIData(oldp+817,(vlSelf->main__DOT__i2cscopei__DOT__qd_data),31); - bufp->fullBit(oldp+818,(vlSelf->main__DOT__i2cscopei__DOT__dr_force_write)); - bufp->fullBit(oldp+819,(vlSelf->main__DOT__i2cscopei__DOT__dr_run_timeout)); - bufp->fullBit(oldp+820,(vlSelf->main__DOT__i2cscopei__DOT__new_data)); - bufp->fullBit(oldp+821,(vlSelf->main__DOT__i2cscopei__DOT__dr_force_inhibit)); - bufp->fullBit(oldp+822,(vlSelf->main__DOT__i2cscopei__DOT__imm_adr)); - bufp->fullBit(oldp+823,(vlSelf->main__DOT__i2cscopei__DOT__lst_adr)); - bufp->fullIData(oldp+824,(vlSelf->main__DOT__i2cscopei__DOT__lst_val),31); - bufp->fullIData(oldp+825,(vlSelf->main__DOT__i2cscopei__DOT__imm_val),31); - bufp->fullBit(oldp+826,(vlSelf->main__DOT__i2cscopei__DOT__record_ce)); - bufp->fullIData(oldp+827,(vlSelf->main__DOT__i2cscopei__DOT__r_data),32); - bufp->fullBit(oldp+828,(vlSelf->main__DOT__i2cscopei__DOT__br_pre_wb_ack)); - bufp->fullSData(oldp+829,(vlSelf->main__DOT__i2cscopei__DOT__this_addr),10); - bufp->fullIData(oldp+830,(vlSelf->main__DOT__i2cscopei__DOT__nxt_mem),32); - bufp->fullBit(oldp+831,(vlSelf->main__DOT__i2cscopei__DOT__br_level_interrupt)); - bufp->fullCData(oldp+832,(vlSelf->main__DOT__rcv__DOT__state),4); - bufp->fullCData(oldp+833,(vlSelf->main__DOT__rcv__DOT__baud_counter),7); - bufp->fullBit(oldp+834,(vlSelf->main__DOT__rcv__DOT__zero_baud_counter)); - bufp->fullBit(oldp+835,(vlSelf->main__DOT__rcv__DOT__q_uart)); - bufp->fullBit(oldp+836,(vlSelf->main__DOT__rcv__DOT__qq_uart)); - bufp->fullBit(oldp+837,(vlSelf->main__DOT__rcv__DOT__ck_uart)); - bufp->fullCData(oldp+838,(vlSelf->main__DOT__rcv__DOT__chg_counter),7); - bufp->fullBit(oldp+839,(vlSelf->main__DOT__rcv__DOT__half_baud_time)); - bufp->fullCData(oldp+840,(vlSelf->main__DOT__rcv__DOT__data_reg),8); - bufp->fullBit(oldp+841,(vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3)); - bufp->fullIData(oldp+842,(vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4),31); - bufp->fullBit(oldp+843,(vlSelf->main__DOT__sdioscopei__DOT__read_address)); - bufp->fullSData(oldp+844,(vlSelf->main__DOT__sdioscopei__DOT__raddr),12); - bufp->fullSData(oldp+845,(vlSelf->main__DOT__sdioscopei__DOT__waddr),12); - bufp->fullBit(oldp+846,((1U & (~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U))))); - bufp->fullBit(oldp+847,((1U & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 1U)))); - bufp->fullBit(oldp+848,((1U & (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config)))); - bufp->fullCData(oldp+849,(vlSelf->main__DOT__sdioscopei__DOT__br_config),3); - bufp->fullIData(oldp+850,(vlSelf->main__DOT__sdioscopei__DOT__br_holdoff),20); - bufp->fullIData(oldp+851,(vlSelf->main__DOT__sdioscopei__DOT__holdoff_counter),20); - bufp->fullBit(oldp+852,(vlSelf->main__DOT__sdioscopei__DOT__dr_triggered)); - bufp->fullBit(oldp+853,(vlSelf->main__DOT__sdioscopei__DOT__dr_primed)); - bufp->fullBit(oldp+854,(vlSelf->main__DOT__sdioscopei__DOT__dw_trigger)); - bufp->fullBit(oldp+855,(vlSelf->main__DOT__sdioscopei__DOT__dr_stopped)); - bufp->fullCData(oldp+856,(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe),5); - bufp->fullBit(oldp+857,((1U & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - >> 4U)))); - bufp->fullIData(oldp+858,(vlSelf->main__DOT__sdioscopei__DOT__ck_addr),31); - bufp->fullIData(oldp+859,(vlSelf->main__DOT__sdioscopei__DOT__qd_data),31); - bufp->fullBit(oldp+860,(vlSelf->main__DOT__sdioscopei__DOT__dr_force_write)); - bufp->fullBit(oldp+861,(vlSelf->main__DOT__sdioscopei__DOT__dr_run_timeout)); - bufp->fullBit(oldp+862,(vlSelf->main__DOT__sdioscopei__DOT__new_data)); - bufp->fullBit(oldp+863,(vlSelf->main__DOT__sdioscopei__DOT__dr_force_inhibit)); - bufp->fullBit(oldp+864,(vlSelf->main__DOT__sdioscopei__DOT__imm_adr)); - bufp->fullBit(oldp+865,(vlSelf->main__DOT__sdioscopei__DOT__lst_adr)); - bufp->fullIData(oldp+866,(vlSelf->main__DOT__sdioscopei__DOT__lst_val),31); - bufp->fullIData(oldp+867,(vlSelf->main__DOT__sdioscopei__DOT__imm_val),31); - bufp->fullBit(oldp+868,(vlSelf->main__DOT__sdioscopei__DOT__record_ce)); - bufp->fullIData(oldp+869,(vlSelf->main__DOT__sdioscopei__DOT__r_data),32); - bufp->fullBit(oldp+870,(vlSelf->main__DOT__sdioscopei__DOT__br_pre_wb_ack)); - bufp->fullSData(oldp+871,(vlSelf->main__DOT__sdioscopei__DOT__this_addr),12); - bufp->fullIData(oldp+872,(vlSelf->main__DOT__sdioscopei__DOT__nxt_mem),32); - bufp->fullBit(oldp+873,(vlSelf->main__DOT__sdioscopei__DOT__br_level_interrupt)); - bufp->fullBit(oldp+874,(vlSelf->main__DOT__spioi__DOT__led_demo)); - bufp->fullCData(oldp+875,(vlSelf->main__DOT__spioi__DOT__r_led),8); - bufp->fullCData(oldp+876,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn),8); - bufp->fullCData(oldp+877,(vlSelf->main__DOT__spioi__DOT__bounced),8); - bufp->fullCData(oldp+878,(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw),8); - bufp->fullBit(oldp+879,(vlSelf->main__DOT__spioi__DOT__sw_int)); - bufp->fullBit(oldp+880,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn_int)); - bufp->fullCData(oldp+881,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__s_btn),5); - bufp->fullCData(oldp+882,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn),5); - bufp->fullSData(oldp+883,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe),10); - bufp->fullSData(oldp+884,(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe),16); - bufp->fullCData(oldp+885,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner),8); - bufp->fullBit(oldp+886,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_dir)); - bufp->fullIData(oldp+887,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr),25); - bufp->fullBit(oldp+888,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_clk)); - bufp->fullCData(oldp+889,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr),5); - bufp->fullCData(oldp+890,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness),5); - bufp->fullCData(oldp+891,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness),5); - bufp->fullCData(oldp+892,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness),5); - bufp->fullCData(oldp+893,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness),5); - bufp->fullCData(oldp+894,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness),5); - bufp->fullCData(oldp+895,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness),5); - bufp->fullCData(oldp+896,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness),5); - bufp->fullCData(oldp+897,(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness),5); - bufp->fullSData(oldp+898,(vlSelf->main__DOT__swic__DOT__main_int_vector),15); - bufp->fullSData(oldp+899,(vlSelf->main__DOT__swic__DOT__alt_int_vector),15); - bufp->fullBit(oldp+900,(vlSelf->main__DOT__swic__DOT__ctri_int)); - bufp->fullBit(oldp+901,(vlSelf->main__DOT__swic__DOT__tma_int)); - bufp->fullBit(oldp+902,(vlSelf->main__DOT__swic__DOT__tmb_int)); - bufp->fullBit(oldp+903,(vlSelf->main__DOT__swic__DOT__tmc_int)); - bufp->fullBit(oldp+904,(vlSelf->main__DOT__swic__DOT__jif_int)); - bufp->fullBit(oldp+905,(vlSelf->main__DOT__swic__DOT__dmac_int)); - bufp->fullBit(oldp+906,(vlSelf->main__DOT__swic__DOT__mtc_int)); - bufp->fullBit(oldp+907,(vlSelf->main__DOT__swic__DOT__moc_int)); - bufp->fullBit(oldp+908,(vlSelf->main__DOT__swic__DOT__mpc_int)); - bufp->fullBit(oldp+909,(vlSelf->main__DOT__swic__DOT__mic_int)); - bufp->fullBit(oldp+910,(vlSelf->main__DOT__swic__DOT__utc_int)); - bufp->fullBit(oldp+911,(vlSelf->main__DOT__swic__DOT__uoc_int)); - bufp->fullBit(oldp+912,(vlSelf->main__DOT__swic__DOT__upc_int)); - bufp->fullBit(oldp+913,(vlSelf->main__DOT__swic__DOT__uic_int)); - bufp->fullIData(oldp+914,(((4U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? ((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data)) - : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data)))),32); - bufp->fullBit(oldp+915,(vlSelf->main__DOT__swic__DOT__actr_ack)); - bufp->fullBit(oldp+916,(((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - | ((IData)(vlSelf->main__DOT__swic__DOT__cmd_read) - | ((~ ((IData)(vlSelf->main__DOT__swic__DOT__dbg_addr) - >> 6U)) & (IData)(vlSelf->main__DOT__swic__DOT__dbg_stb)))))); - bufp->fullBit(oldp+917,(vlSelf->main__DOT__swic__DOT__sys_cyc)); - bufp->fullBit(oldp+918,(vlSelf->main__DOT__swic__DOT__sys_stb)); - bufp->fullBit(oldp+919,(vlSelf->main__DOT__swic__DOT__sys_we)); - bufp->fullCData(oldp+920,(vlSelf->main__DOT__swic__DOT__sys_addr),8); - bufp->fullIData(oldp+921,(vlSelf->main__DOT__swic__DOT__sys_data),32); - bufp->fullIData(oldp+922,(vlSelf->main__DOT__swic__DOT__cpu_addr),22); - bufp->fullIData(oldp+923,(vlSelf->main__DOT__swic__DOT__sys_idata),32); - bufp->fullBit(oldp+924,(vlSelf->main__DOT__swic__DOT__sys_ack)); - bufp->fullBit(oldp+925,(vlSelf->main__DOT__swic__DOT__sel_timer)); - bufp->fullBit(oldp+926,(vlSelf->main__DOT__swic__DOT__sel_pic)); - bufp->fullBit(oldp+927,(vlSelf->main__DOT__swic__DOT__sel_apic)); - bufp->fullBit(oldp+928,(vlSelf->main__DOT__swic__DOT__sel_watchdog)); - bufp->fullBit(oldp+929,(vlSelf->main__DOT__swic__DOT__sel_bus_watchdog)); - bufp->fullBit(oldp+930,(vlSelf->main__DOT__swic__DOT__sel_dmac)); - bufp->fullBit(oldp+931,(((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_addr) - >> 7U)))); - bufp->fullBit(oldp+932,(vlSelf->main__DOT__swic__DOT__dbg_cyc)); - bufp->fullBit(oldp+933,(vlSelf->main__DOT__swic__DOT__dbg_stb)); - bufp->fullBit(oldp+934,(vlSelf->main__DOT__swic__DOT__dbg_we)); - bufp->fullCData(oldp+935,(vlSelf->main__DOT__swic__DOT__dbg_addr),7); - bufp->fullIData(oldp+936,(vlSelf->main__DOT__swic__DOT__dbg_idata),32); - bufp->fullBit(oldp+937,(vlSelf->main__DOT__swic__DOT__dbg_ack)); - bufp->fullBit(oldp+938,(vlSelf->main__DOT__swic__DOT__dbg_stall)); - bufp->fullIData(oldp+939,(vlSelf->main__DOT__swic__DOT__dbg_odata),32); - bufp->fullCData(oldp+940,(vlSelf->main__DOT__swic__DOT__dbg_sel),4); - bufp->fullBit(oldp+941,(vlSelf->main__DOT__swic__DOT__no_dbg_err)); - bufp->fullBit(oldp+942,(vlSelf->main__DOT__swic__DOT__cpu_break)); - bufp->fullBit(oldp+943,(vlSelf->main__DOT__swic__DOT__dbg_cmd_write)); - bufp->fullBit(oldp+944,(vlSelf->main__DOT__swic__DOT__dbg_cpu_write)); - bufp->fullBit(oldp+945,(vlSelf->main__DOT__swic__DOT__dbg_cpu_read)); - bufp->fullBit(oldp+946,(vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__r_reset_hold)); - bufp->fullBit(oldp+947,(vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch)); - bufp->fullBit(oldp+948,(vlSelf->main__DOT__swic__DOT__reset_request)); - bufp->fullBit(oldp+949,(((~ vlSelf->main__DOT__swic__DOT__dbg_idata) - & (IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0)))); - bufp->fullBit(oldp+950,(vlSelf->main__DOT__swic__DOT__halt_request)); - bufp->fullBit(oldp+951,(vlSelf->main__DOT__swic__DOT__step_request)); - bufp->fullBit(oldp+952,(vlSelf->main__DOT__swic__DOT__clear_cache_request)); - bufp->fullBit(oldp+953,(vlSelf->main__DOT__swic__DOT__cmd_reset)); - bufp->fullBit(oldp+954,(vlSelf->main__DOT__swic__DOT__cmd_halt)); - bufp->fullBit(oldp+955,(vlSelf->main__DOT__swic__DOT__cmd_step)); - bufp->fullBit(oldp+956,(vlSelf->main__DOT__swic__DOT__cmd_clear_cache)); - bufp->fullBit(oldp+957,(vlSelf->main__DOT__swic__DOT__cmd_write)); - bufp->fullBit(oldp+958,(vlSelf->main__DOT__swic__DOT__cmd_read)); - bufp->fullCData(oldp+959,(vlSelf->main__DOT__swic__DOT__cmd_waddr),5); - bufp->fullIData(oldp+960,(vlSelf->main__DOT__swic__DOT__cmd_wdata),32); - bufp->fullCData(oldp+961,(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc),3); - bufp->fullBit(oldp+962,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall))))); - bufp->fullBit(oldp+963,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)); - bufp->fullIData(oldp+964,(((((IData)(vlSelf->main__DOT__gpio_int) - << 0x1bU) | (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0x1aU) - | ((0x2000000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0x19U)) - | ((0x1000000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0x18U)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0x17U) - | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 0x16U) - | (((IData)(vlSelf->main__DOT__emmcscope_int) - << 0x15U) - | ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0) - << 0xcU)))))))) - | (((IData)(vlSelf->main__DOT__swic__DOT__cpu_break) - << 0xbU) | (((IData)(vlSelf->main__DOT__swic__DOT__pic_interrupt) - << 0xaU) - | ((0x300U - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - << 8U)) - | (((IData)(vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch) - << 5U) - | (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - << 3U) - | ((2U - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)) - << 1U)) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))))))))),32); - bufp->fullBit(oldp+965,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))); - bufp->fullBit(oldp+966,(vlSelf->main__DOT__swic__DOT__wdt_ack)); - bufp->fullBit(oldp+967,(vlSelf->main__DOT__swic__DOT__wdt_reset)); - bufp->fullIData(oldp+968,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value),32); - bufp->fullBit(oldp+969,(vlSelf->main__DOT__swic__DOT__wdbus_ack)); - bufp->fullIData(oldp+970,(vlSelf->main__DOT__swic__DOT__r_wdbus_data),22); - bufp->fullIData(oldp+971,(vlSelf->main__DOT__swic__DOT__pic_data),32); - bufp->fullIData(oldp+972,(vlSelf->main__DOT__swic__DOT__r_wdbus_data),32); - bufp->fullBit(oldp+973,((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_zip_cyc)) - | ((IData)(vlSelf->main__DOT__wbwide_zip_stb) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U)))))); - bufp->fullBit(oldp+974,(vlSelf->main__DOT__swic__DOT__wdbus_int)); - bufp->fullBit(oldp+975,(vlSelf->main__DOT__swic__DOT__cpu_pf_stall)); - bufp->fullBit(oldp+976,(vlSelf->main__DOT__swic__DOT__cpu_i_count)); - bufp->fullBit(oldp+977,(vlSelf->main__DOT__swic__DOT__dmac_stb)); - bufp->fullBit(oldp+978,(vlSelf->main__DOT__swic__DOT__dc_err)); - bufp->fullIData(oldp+979,(vlSelf->main__DOT__swic__DOT__dmac_data),32); - bufp->fullBit(oldp+980,(vlSelf->main__DOT__swic__DOT__dmac_ack)); - bufp->fullBit(oldp+981,(vlSelf->main__DOT__swic__DOT__dc_cyc)); - bufp->fullBit(oldp+982,(vlSelf->main__DOT__swic__DOT__dc_stb)); - bufp->fullBit(oldp+983,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner))))); - bufp->fullBit(oldp+984,(vlSelf->main__DOT__swic__DOT__dc_stall)); - bufp->fullBit(oldp+985,(vlSelf->main__DOT__swic__DOT__dc_ack)); - bufp->fullIData(oldp+986,(((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr)),22); - bufp->fullWData(oldp+987,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data),512); - bufp->fullQData(oldp+1003,(((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel)),64); - bufp->fullBit(oldp+1005,(vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc)); - bufp->fullIData(oldp+1006,((((IData)(vlSelf->main__DOT__swic__DOT__alt_int_vector) - << 0x10U) | (((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0) - << 6U) - | (((IData)(vlSelf->main__DOT__swic__DOT__ctri_int) - << 5U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tma_int) - << 4U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tmb_int) - << 3U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tmc_int) - << 2U) - | ((IData)(vlSelf->main__DOT__swic__DOT__jif_int) - << 1U)))))))),32); - bufp->fullBit(oldp+1007,(((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_apic)))); - bufp->fullIData(oldp+1008,(vlSelf->main__DOT__swic__DOT__ctri_data),32); - bufp->fullBit(oldp+1009,(vlSelf->main__DOT__swic__DOT__tma_ack)); - bufp->fullBit(oldp+1010,(vlSelf->main__DOT__swic__DOT__tmb_ack)); - bufp->fullBit(oldp+1011,(vlSelf->main__DOT__swic__DOT__tmc_ack)); - bufp->fullBit(oldp+1012,(vlSelf->main__DOT__swic__DOT__jif_ack)); - bufp->fullIData(oldp+1013,((((IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) | vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value)),32); - bufp->fullIData(oldp+1014,((((IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) | vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value)),32); - bufp->fullIData(oldp+1015,((((IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) | vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value)),32); - bufp->fullIData(oldp+1016,(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter),32); - bufp->fullBit(oldp+1017,(((IData)(vlSelf->main__DOT__swic__DOT__sys_cyc) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_pic))))); - bufp->fullBit(oldp+1018,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb)))); - bufp->fullBit(oldp+1019,(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc)); - bufp->fullBit(oldp+1020,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl)))); - bufp->fullBit(oldp+1021,(vlSelf->main__DOT__swic__DOT__cpu_we)); - bufp->fullWData(oldp+1022,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data),512); - bufp->fullQData(oldp+1038,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL)),64); - bufp->fullWData(oldp+1040,(vlSelf->main__DOT__swic__DOT__cpu_idata),512); - bufp->fullBit(oldp+1056,(vlSelf->main__DOT__swic__DOT__cpu_stall)); - bufp->fullBit(oldp+1057,(vlSelf->main__DOT__swic__DOT__pic_interrupt)); - bufp->fullBit(oldp+1058,(vlSelf->main__DOT__swic__DOT__cpu_ack)); - bufp->fullBit(oldp+1059,(vlSelf->main__DOT__swic__DOT__cpu_err)); - bufp->fullIData(oldp+1060,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg),32); - bufp->fullBit(oldp+1061,((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)) - | ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 2U))))); - bufp->fullBit(oldp+1062,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U) & (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)))); - bufp->fullBit(oldp+1063,(((IData)(vlSelf->main__DOT__swic__DOT__ext_err) - & (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)))); - bufp->fullBit(oldp+1064,(vlSelf->main__DOT__swic__DOT__r_mmus_ack)); - bufp->fullBit(oldp+1065,(vlSelf->main__DOT__swic__DOT__ext_err)); - bufp->fullIData(oldp+1066,(((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter - : (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value)) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value) - : (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value)))),32); - bufp->fullCData(oldp+1067,(vlSelf->main__DOT__swic__DOT__w_ack_idx),3); - bufp->fullCData(oldp+1068,(vlSelf->main__DOT__swic__DOT__ack_idx),3); - bufp->fullBit(oldp+1069,(vlSelf->main__DOT__swic__DOT__last_sys_stb)); - bufp->fullBit(oldp+1070,(vlSelf->main__DOT__swic__DOT__cmd_read_ack)); - bufp->fullBit(oldp+1071,(vlSelf->main__DOT__swic__DOT__dbg_pre_ack)); - bufp->fullCData(oldp+1072,(vlSelf->main__DOT__swic__DOT__dbg_pre_addr),2); - bufp->fullIData(oldp+1073,(vlSelf->main__DOT__swic__DOT__dbg_cpu_status),32); - bufp->fullBit(oldp+1074,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_ack)); - bufp->fullBit(oldp+1075,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_ack)); - bufp->fullBit(oldp+1076,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_ack)); - bufp->fullBit(oldp+1077,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_ack)); - bufp->fullBit(oldp+1078,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_ack)); - bufp->fullBit(oldp+1079,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_ack)); - bufp->fullBit(oldp+1080,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_ack)); - bufp->fullBit(oldp+1081,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_ack)); - bufp->fullIData(oldp+1082,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data),32); - bufp->fullIData(oldp+1083,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data),32); - bufp->fullIData(oldp+1084,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data),32); - bufp->fullIData(oldp+1085,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data),32); - bufp->fullIData(oldp+1086,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data),32); - bufp->fullIData(oldp+1087,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data),32); - bufp->fullIData(oldp+1088,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data),32); - bufp->fullIData(oldp+1089,(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data),32); - bufp->fullBit(oldp+1090,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mins_ctr____pinNumber5)); - bufp->fullBit(oldp+1091,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mmstall_ctr____pinNumber5)); - bufp->fullBit(oldp+1092,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mpstall_ctr____pinNumber5)); - bufp->fullBit(oldp+1093,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))))); - bufp->fullBit(oldp+1094,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mtask_ctr____pinNumber5)); - bufp->fullBit(oldp+1095,(((IData)(vlSelf->main__DOT__swic__DOT__cpu_i_count) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))); - bufp->fullBit(oldp+1096,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__uins_ctr____pinNumber5)); - bufp->fullBit(oldp+1097,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__umstall_ctr____pinNumber5)); - bufp->fullBit(oldp+1098,(((IData)(vlSelf->main__DOT__swic__DOT__cpu_pf_stall) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))); - bufp->fullBit(oldp+1099,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__upstall_ctr____pinNumber5)); - bufp->fullBit(oldp+1100,((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U))))); - bufp->fullBit(oldp+1101,(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__utask_ctr____pinNumber5)); - bufp->fullBit(oldp+1102,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_we)); - bufp->fullCData(oldp+1103,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_addr),7); - bufp->fullIData(oldp+1104,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_data),32); - bufp->fullCData(oldp+1105,(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_sel),4); - bufp->fullCData(oldp+1106,((3U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))),2); - bufp->fullBit(oldp+1107,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request)); - bufp->fullBit(oldp+1108,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort)); - bufp->fullBit(oldp+1109,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)); - bufp->fullBit(oldp+1110,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err)); - bufp->fullIData(oldp+1111,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src),28); - bufp->fullIData(oldp+1112,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst),28); - bufp->fullIData(oldp+1113,((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - << 6U)),28); - bufp->fullIData(oldp+1114,((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr - << 6U)),28); - bufp->fullIData(oldp+1115,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length),28); - bufp->fullIData(oldp+1116,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length),28); - bufp->fullSData(oldp+1117,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen),11); - bufp->fullBit(oldp+1118,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger)); - bufp->fullBit(oldp+1119,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request)); - bufp->fullBit(oldp+1120,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request)); - bufp->fullBit(oldp+1121,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy)); - bufp->fullBit(oldp+1122,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy)); - bufp->fullBit(oldp+1123,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err)); - bufp->fullBit(oldp+1124,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err)); - bufp->fullBit(oldp+1125,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc)); - bufp->fullBit(oldp+1126,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc)); - bufp->fullCData(oldp+1127,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size),2); - bufp->fullCData(oldp+1128,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size),2); - bufp->fullIData(oldp+1129,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr),28); - bufp->fullIData(oldp+1130,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr),28); - bufp->fullSData(oldp+1131,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen),11); - bufp->fullBit(oldp+1132,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc)); - bufp->fullBit(oldp+1133,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb)); - bufp->fullBit(oldp+1134,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall)); - bufp->fullBit(oldp+1135,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack)); - bufp->fullBit(oldp+1136,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err)); - bufp->fullIData(oldp+1137,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr),22); - bufp->fullQData(oldp+1138,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel),64); - bufp->fullBit(oldp+1140,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid)); - bufp->fullBit(oldp+1141,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready)); - bufp->fullBit(oldp+1142,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last)); - bufp->fullWData(oldp+1143,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg),512); - bufp->fullCData(oldp+1159,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes),7); - bufp->fullBit(oldp+1160,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid)); - bufp->fullBit(oldp+1161,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full))))); - bufp->fullBit(oldp+1162,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last)); - __Vtemp_hd1e4c677__0[0U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U]; - __Vtemp_hd1e4c677__0[1U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U]; - __Vtemp_hd1e4c677__0[2U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U]; - __Vtemp_hd1e4c677__0[3U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U]; - __Vtemp_hd1e4c677__0[4U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U]; - __Vtemp_hd1e4c677__0[5U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U]; - __Vtemp_hd1e4c677__0[6U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U]; - __Vtemp_hd1e4c677__0[7U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U]; - __Vtemp_hd1e4c677__0[8U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U]; - __Vtemp_hd1e4c677__0[9U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U]; - __Vtemp_hd1e4c677__0[0xaU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU]; - __Vtemp_hd1e4c677__0[0xbU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU]; - __Vtemp_hd1e4c677__0[0xcU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU]; - __Vtemp_hd1e4c677__0[0xdU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU]; - __Vtemp_hd1e4c677__0[0xeU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU]; - __Vtemp_hd1e4c677__0[0xfU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU]; - bufp->fullWData(oldp+1163,(__Vtemp_hd1e4c677__0),512); - bufp->fullCData(oldp+1179,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes),7); - bufp->fullBit(oldp+1180,((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty))))); - bufp->fullBit(oldp+1181,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready)); - bufp->fullBit(oldp+1182,((1U & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U] - >> 7U)))); - __Vtemp_h6ddae8d1__0[0U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0U]; - __Vtemp_h6ddae8d1__0[1U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[1U]; - __Vtemp_h6ddae8d1__0[2U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[2U]; - __Vtemp_h6ddae8d1__0[3U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[3U]; - __Vtemp_h6ddae8d1__0[4U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[4U]; - __Vtemp_h6ddae8d1__0[5U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[5U]; - __Vtemp_h6ddae8d1__0[6U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[6U]; - __Vtemp_h6ddae8d1__0[7U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[7U]; - __Vtemp_h6ddae8d1__0[8U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[8U]; - __Vtemp_h6ddae8d1__0[9U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[9U]; - __Vtemp_h6ddae8d1__0[0xaU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xaU]; - __Vtemp_h6ddae8d1__0[0xbU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xbU]; - __Vtemp_h6ddae8d1__0[0xcU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xcU]; - __Vtemp_h6ddae8d1__0[0xdU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xdU]; - __Vtemp_h6ddae8d1__0[0xeU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xeU]; - __Vtemp_h6ddae8d1__0[0xfU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xfU]; - bufp->fullWData(oldp+1183,(__Vtemp_h6ddae8d1__0),512); - bufp->fullCData(oldp+1199,((0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])),7); - bufp->fullBit(oldp+1200,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)); - bufp->fullBit(oldp+1201,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty)); - bufp->fullCData(oldp+1202,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill),5); - bufp->fullBit(oldp+1203,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid)); - bufp->fullBit(oldp+1204,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready)); - bufp->fullBit(oldp+1205,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last)); - bufp->fullWData(oldp+1206,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg),512); - bufp->fullCData(oldp+1222,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes),7); - bufp->fullBit(oldp+1223,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc)); - bufp->fullBit(oldp+1224,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb)); - bufp->fullBit(oldp+1225,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall)); - bufp->fullBit(oldp+1226,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack)); - bufp->fullBit(oldp+1227,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err)); - bufp->fullIData(oldp+1228,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr),22); - bufp->fullQData(oldp+1229,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel),64); - bufp->fullBit(oldp+1231,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)); - bufp->fullBit(oldp+1232,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner)); - bufp->fullBit(oldp+1233,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger)); - bufp->fullBit(oldp+1234,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err)); - bufp->fullBit(oldp+1235,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_zero_len)); - bufp->fullBit(oldp+1236,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_busy)); - bufp->fullCData(oldp+1237,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel),5); - bufp->fullIData(oldp+1238,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src),32); - bufp->fullIData(oldp+1239,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst),32); - bufp->fullIData(oldp+1240,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len),32); - bufp->fullIData(oldp+1241,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen),32); - bufp->fullIData(oldp+1242,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg),32); - bufp->fullCData(oldp+1243,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state),2); - bufp->fullBit(oldp+1244,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset)); - bufp->fullCData(oldp+1245,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size),7); - bufp->fullCData(oldp+1246,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size),7); - bufp->fullCData(oldp+1247,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size),7); - bufp->fullCData(oldp+1248,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size),7); - bufp->fullIData(oldp+1249,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr),28); - bufp->fullIData(oldp+1250,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr),28); - bufp->fullCData(oldp+1251,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr),6); - bufp->fullCData(oldp+1252,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr),6); - bufp->fullQData(oldp+1253,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel),64); - bufp->fullQData(oldp+1255,(((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? (0x8000000000000000ULL - >> (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : ((0x4000000000000000ULL - | ((QData)((IData)( - (1U - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - << 0x3fU)) - >> (0x3eU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((2U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? ((1U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? (0x1000000000000000ULL - >> - (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : (0x3000000000000000ULL - >> - (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - : ((1U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? (0x7000000000000000ULL - >> - (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : (0xf000000000000000ULL - >> - (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)))) - : (0xffffffffffffffffULL - >> (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))))),64); - bufp->fullQData(oldp+1257,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel),64); - bufp->fullQData(oldp+1259,(((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? (0x8000000000000000ULL - >> (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : (0xc000000000000000ULL - >> (0x3eU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? (0xf000000000000000ULL - >> (0x3cU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : 0xffffffffffffffffULL))),64); - bufp->fullSData(oldp+1261,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding),11); - bufp->fullCData(oldp+1262,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__fill),8); - bufp->fullCData(oldp+1263,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill),8); - bufp->fullSData(oldp+1264,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len),11); - bufp->fullSData(oldp+1265,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len),11); - bufp->fullCData(oldp+1266,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift),6); - __Vtemp_hc1d82fb0__1[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U]; - __Vtemp_hc1d82fb0__1[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U]; - __Vtemp_hc1d82fb0__1[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U]; - __Vtemp_hc1d82fb0__1[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U]; - __Vtemp_hc1d82fb0__1[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U]; - __Vtemp_hc1d82fb0__1[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U]; - __Vtemp_hc1d82fb0__1[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U]; - __Vtemp_hc1d82fb0__1[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U]; - __Vtemp_hc1d82fb0__1[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U]; - __Vtemp_hc1d82fb0__1[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U]; - __Vtemp_hc1d82fb0__1[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU]; - __Vtemp_hc1d82fb0__1[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU]; - __Vtemp_hc1d82fb0__1[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU]; - __Vtemp_hc1d82fb0__1[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU]; - __Vtemp_hc1d82fb0__1[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU]; - __Vtemp_hc1d82fb0__1[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU]; - VL_SHIFTL_WWI(512,512,32, __Vtemp_h6d0d1506__0, __Vtemp_hc1d82fb0__1, - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift) - << 3U)); - bufp->fullWData(oldp+1267,(__Vtemp_h6d0d1506__0),512); - bufp->fullBit(oldp+1283,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc)); - bufp->fullCData(oldp+1284,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size),2); - bufp->fullWData(oldp+1285,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg),1024); - bufp->fullCData(oldp+1317,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill),8); - bufp->fullCData(oldp+1318,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill),8); - bufp->fullBit(oldp+1319,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last)); - bufp->fullBit(oldp+1320,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last)); - bufp->fullBit(oldp+1321,((0x40U <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill)))); - bufp->fullCData(oldp+1322,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift),6); - bufp->fullWData(oldp+1323,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data),512); - bufp->fullBit(oldp+1339,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc)); - bufp->fullCData(oldp+1340,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size),2); - bufp->fullIData(oldp+1341,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr),29); - bufp->fullCData(oldp+1342,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr),6); - bufp->fullWData(oldp+1343,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data),1024); - bufp->fullWData(oldp+1375,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data),512); - bufp->fullWData(oldp+1391,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel),128); - bufp->fullWData(oldp+1395,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel),128); - bufp->fullQData(oldp+1399,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel),64); - bufp->fullBit(oldp+1401,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last)); - bufp->fullSData(oldp+1402,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding),10); - bufp->fullBit(oldp+1403,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full)); - bufp->fullBit(oldp+1404,((1U & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - >> 0x1cU)))); - __Vtemp_h6b3f223d__0[0U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U]; - __Vtemp_h6b3f223d__0[1U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U]; - __Vtemp_h6b3f223d__0[2U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U]; - __Vtemp_h6b3f223d__0[3U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U]; - __Vtemp_h6b3f223d__0[4U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U]; - __Vtemp_h6b3f223d__0[5U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U]; - __Vtemp_h6b3f223d__0[6U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U]; - __Vtemp_h6b3f223d__0[7U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U]; - __Vtemp_h6b3f223d__0[8U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U]; - __Vtemp_h6b3f223d__0[9U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U]; - __Vtemp_h6b3f223d__0[0xaU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU]; - __Vtemp_h6b3f223d__0[0xbU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU]; - __Vtemp_h6b3f223d__0[0xcU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU]; - __Vtemp_h6b3f223d__0[0xdU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU]; - __Vtemp_h6b3f223d__0[0xeU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU]; - __Vtemp_h6b3f223d__0[0xfU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU]; - __Vtemp_h6b3f223d__0[0x10U] = (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last) - << 7U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes)); - bufp->fullWData(oldp+1405,(__Vtemp_h6b3f223d__0),520); - bufp->fullWData(oldp+1422,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data),520); - bufp->fullWData(oldp+1439,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[0]),520); - bufp->fullWData(oldp+1456,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[1]),520); - bufp->fullWData(oldp+1473,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[2]),520); - bufp->fullWData(oldp+1490,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[3]),520); - bufp->fullWData(oldp+1507,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[4]),520); - bufp->fullWData(oldp+1524,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[5]),520); - bufp->fullWData(oldp+1541,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[6]),520); - bufp->fullWData(oldp+1558,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[7]),520); - bufp->fullWData(oldp+1575,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[8]),520); - bufp->fullWData(oldp+1592,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[9]),520); - bufp->fullWData(oldp+1609,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[10]),520); - bufp->fullWData(oldp+1626,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[11]),520); - bufp->fullWData(oldp+1643,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[12]),520); - bufp->fullWData(oldp+1660,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[13]),520); - bufp->fullWData(oldp+1677,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[14]),520); - bufp->fullWData(oldp+1694,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[15]),520); - bufp->fullCData(oldp+1711,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr),5); - bufp->fullCData(oldp+1712,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr),5); - bufp->fullBit(oldp+1713,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr)); - bufp->fullBit(oldp+1714,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd)); - bufp->fullBit(oldp+1715,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last)); - bufp->fullBit(oldp+1716,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next)); - bufp->fullCData(oldp+1717,(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill),7); - bufp->fullCData(oldp+1718,(vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter),5); - bufp->fullSData(oldp+1719,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state),15); - bufp->fullSData(oldp+1720,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable),15); - bufp->fullBit(oldp+1721,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie)); - bufp->fullBit(oldp+1722,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any)); - bufp->fullBit(oldp+1723,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write)); - bufp->fullBit(oldp+1724,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__enable_ints)); - bufp->fullBit(oldp+1725,(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__disable_ints)); - bufp->fullSData(oldp+1726,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state),15); - bufp->fullSData(oldp+1727,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable),15); - bufp->fullBit(oldp+1728,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie)); - bufp->fullBit(oldp+1729,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any)); - bufp->fullBit(oldp+1730,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write)); - bufp->fullBit(oldp+1731,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__enable_ints)); - bufp->fullBit(oldp+1732,(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__disable_ints)); - bufp->fullBit(oldp+1733,(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)); - bufp->fullCData(oldp+1734,((0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))),5); - bufp->fullBit(oldp+1735,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc)); - bufp->fullBit(oldp+1736,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache)); - bufp->fullIData(oldp+1737,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address),28); - bufp->fullIData(oldp+1738,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU]),32); - bufp->fullIData(oldp+1739,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc),28); - bufp->fullBit(oldp+1740,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)); - bufp->fullBit(oldp+1741,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal)); - bufp->fullBit(oldp+1742,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc)); - bufp->fullBit(oldp+1743,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb)); - bufp->fullBit(oldp+1744,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stall)); - bufp->fullBit(oldp+1745,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack)); - bufp->fullBit(oldp+1746,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err)); - bufp->fullIData(oldp+1747,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr),22); - bufp->fullBit(oldp+1748,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__CLEAR_DCACHE__DOT__r_clear_dcache)); - bufp->fullBit(oldp+1749,((0U != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))); - bufp->fullCData(oldp+1750,((7U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))),3); - bufp->fullIData(oldp+1751,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr),32); - bufp->fullIData(oldp+1752,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_lock_pc),28); - bufp->fullIData(oldp+1753,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata),32); - bufp->fullCData(oldp+1754,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R),5); - bufp->fullBit(oldp+1755,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)); - bufp->fullBit(oldp+1756,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)); - bufp->fullBit(oldp+1757,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled)); - bufp->fullBit(oldp+1758,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid)); - bufp->fullBit(oldp+1759,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err)); - bufp->fullCData(oldp+1760,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wreg),5); - bufp->fullIData(oldp+1761,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result),32); - bufp->fullBit(oldp+1762,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl)); - bufp->fullBit(oldp+1763,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl)); - bufp->fullBit(oldp+1764,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl)); - bufp->fullBit(oldp+1765,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl)); - bufp->fullIData(oldp+1766,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr),22); - bufp->fullBit(oldp+1767,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we)); - bufp->fullBit(oldp+1768,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)); - bufp->fullBit(oldp+1769,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack)); - bufp->fullBit(oldp+1770,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err)); - bufp->fullQData(oldp+1771,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel),64); - bufp->fullIData(oldp+1773,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__ik),32); - bufp->fullBit(oldp+1774,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)); - bufp->fullBit(oldp+1775,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb)); - bufp->fullBit(oldp+1776,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack)); - bufp->fullBit(oldp+1777,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line)); - bufp->fullBit(oldp+1778,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb)); - bufp->fullBit(oldp+1779,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl)); - bufp->fullBit(oldp+1780,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl)); - bufp->fullCData(oldp+1781,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending),5); - bufp->fullCData(oldp+1782,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v),8); - bufp->fullIData(oldp+1783,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[0]),19); - bufp->fullIData(oldp+1784,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[1]),19); - bufp->fullIData(oldp+1785,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[2]),19); - bufp->fullIData(oldp+1786,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[3]),19); - bufp->fullIData(oldp+1787,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[4]),19); - bufp->fullIData(oldp+1788,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[5]),19); - bufp->fullIData(oldp+1789,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[6]),19); - bufp->fullIData(oldp+1790,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[7]),19); - bufp->fullBit(oldp+1791,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag)); - bufp->fullCData(oldp+1792,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state),2); - bufp->fullCData(oldp+1793,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr),6); - bufp->fullWData(oldp+1794,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword),512); - bufp->fullWData(oldp+1810,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword),512); - bufp->fullBit(oldp+1826,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl)); - bufp->fullBit(oldp+1827,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl)); - bufp->fullBit(oldp+1828,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr)); - bufp->fullWData(oldp+1829,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata),512); - bufp->fullQData(oldp+1845,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel),64); - bufp->fullCData(oldp+1847,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr),6); - bufp->fullIData(oldp+1848,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag),19); - bufp->fullBit(oldp+1849,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid)); - bufp->fullCData(oldp+1850,((7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U))),3); - bufp->fullCData(oldp+1851,((0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))),6); - bufp->fullBit(oldp+1852,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow)); - bufp->fullBit(oldp+1853,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable)); - bufp->fullBit(oldp+1854,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address)); - bufp->fullBit(oldp+1855,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable)); - bufp->fullBit(oldp+1856,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid)); - bufp->fullBit(oldp+1857,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid)); - bufp->fullBit(oldp+1858,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd)); - bufp->fullBit(oldp+1859,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss)); - bufp->fullBit(oldp+1860,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending)); - bufp->fullIData(oldp+1861,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr),22); - bufp->fullCData(oldp+1862,((7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U))),3); - bufp->fullCData(oldp+1863,((0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)),6); - bufp->fullIData(oldp+1864,((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U))),19); - bufp->fullBit(oldp+1865,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb)); - bufp->fullBit(oldp+1866,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv)); - bufp->fullBit(oldp+1867,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__in_cache)); - bufp->fullIData(oldp+1868,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag),19); - bufp->fullSData(oldp+1869,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__req_data),13); - bufp->fullBit(oldp+1870,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__gie)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid) { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xfU]; - } else if ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__cpu_idata[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__cpu_idata[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__cpu_idata[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__cpu_idata[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__cpu_idata[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__cpu_idata[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__cpu_idata[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__cpu_idata[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__cpu_idata[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__cpu_idata[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU]; - } else { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xfU]; - } - bufp->fullWData(oldp+1871,(__Vtemp_h01ff8f7b__0),512); - bufp->fullWData(oldp+1887,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted),512); - bufp->fullCData(oldp+1903,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel),4); - bufp->fullQData(oldp+1904,(((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) - ? ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel)) - >> (3U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)) - : (((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel)) - << 0x3cU) >> (0x3fU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)))),64); - bufp->fullIData(oldp+1906,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift),32); - bufp->fullWData(oldp+1907,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift),512); - bufp->fullWData(oldp+1923,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data),512); - bufp->fullSData(oldp+1939,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[0]),12); - bufp->fullSData(oldp+1940,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[1]),12); - bufp->fullSData(oldp+1941,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[2]),12); - bufp->fullSData(oldp+1942,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[3]),12); - bufp->fullSData(oldp+1943,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[4]),12); - bufp->fullSData(oldp+1944,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[5]),12); - bufp->fullSData(oldp+1945,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[6]),12); - bufp->fullSData(oldp+1946,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[7]),12); - bufp->fullSData(oldp+1947,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[8]),12); - bufp->fullSData(oldp+1948,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[9]),12); - bufp->fullSData(oldp+1949,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[10]),12); - bufp->fullSData(oldp+1950,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[11]),12); - bufp->fullSData(oldp+1951,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[12]),12); - bufp->fullSData(oldp+1952,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[13]),12); - bufp->fullSData(oldp+1953,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[14]),12); - bufp->fullSData(oldp+1954,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[15]),12); - bufp->fullCData(oldp+1955,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr),5); - bufp->fullCData(oldp+1956,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr),5); - bufp->fullIData(oldp+1957,((0xfffffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)),28); - bufp->fullBit(oldp+1958,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc) { - __Vtemp_he3c3974d__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0U]; - __Vtemp_he3c3974d__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[1U]; - __Vtemp_he3c3974d__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[2U]; - __Vtemp_he3c3974d__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[3U]; - __Vtemp_he3c3974d__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[4U]; - __Vtemp_he3c3974d__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[5U]; - __Vtemp_he3c3974d__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[6U]; - __Vtemp_he3c3974d__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[7U]; - __Vtemp_he3c3974d__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[8U]; - __Vtemp_he3c3974d__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[9U]; - __Vtemp_he3c3974d__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xaU]; - __Vtemp_he3c3974d__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xbU]; - __Vtemp_he3c3974d__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xcU]; - __Vtemp_he3c3974d__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xdU]; - __Vtemp_he3c3974d__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xeU]; - __Vtemp_he3c3974d__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xfU]; - } else { - __Vtemp_he3c3974d__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0U]; - __Vtemp_he3c3974d__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[1U]; - __Vtemp_he3c3974d__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[2U]; - __Vtemp_he3c3974d__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[3U]; - __Vtemp_he3c3974d__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[4U]; - __Vtemp_he3c3974d__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[5U]; - __Vtemp_he3c3974d__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[6U]; - __Vtemp_he3c3974d__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[7U]; - __Vtemp_he3c3974d__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[8U]; - __Vtemp_he3c3974d__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[9U]; - __Vtemp_he3c3974d__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xaU]; - __Vtemp_he3c3974d__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xbU]; - __Vtemp_he3c3974d__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xcU]; - __Vtemp_he3c3974d__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xdU]; - __Vtemp_he3c3974d__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xeU]; - __Vtemp_he3c3974d__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xfU]; - } - bufp->fullWData(oldp+1959,(__Vtemp_he3c3974d__0),512); - bufp->fullSData(oldp+1975,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[0]),16); - bufp->fullSData(oldp+1976,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[1]),16); - bufp->fullSData(oldp+1977,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[2]),16); - bufp->fullSData(oldp+1978,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[3]),16); - bufp->fullSData(oldp+1979,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[4]),16); - bufp->fullSData(oldp+1980,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[5]),16); - bufp->fullSData(oldp+1981,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[6]),16); - bufp->fullSData(oldp+1982,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[7]),16); - bufp->fullCData(oldp+1983,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask),8); - bufp->fullBit(oldp+1984,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_pc)); - bufp->fullBit(oldp+1985,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_last)); - bufp->fullBit(oldp+1986,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__rvsrc)); - bufp->fullBit(oldp+1987,((((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U)) - == (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup - == (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask) - >> (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))))))); - bufp->fullBit(oldp+1988,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_v_from_last)); - bufp->fullIData(oldp+1989,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc),28); - bufp->fullCData(oldp+1990,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr),6); - bufp->fullIData(oldp+1991,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__pc_tag_lookup),19); - bufp->fullIData(oldp+1992,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_tag_lookup),19); - bufp->fullIData(oldp+1993,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup),19); - bufp->fullIData(oldp+1994,((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))),19); - bufp->fullIData(oldp+1995,((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))),19); - bufp->fullBit(oldp+1996,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid)); - bufp->fullIData(oldp+1997,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache),19); - bufp->fullWData(oldp+1998,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache),512); - bufp->fullWData(oldp+2014,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache),512); - bufp->fullBit(oldp+2030,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc)); - bufp->fullCData(oldp+2031,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay),2); - bufp->fullBit(oldp+2032,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__svmask)); - bufp->fullBit(oldp+2033,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack)); - bufp->fullBit(oldp+2034,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__needload)); - bufp->fullBit(oldp+2035,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr)); - bufp->fullBit(oldp+2036,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort)); - bufp->fullCData(oldp+2037,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__saddr),3); - bufp->fullBit(oldp+2038,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_invalidate_result)); - bufp->fullCData(oldp+2039,((7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))),3); - bufp->fullCData(oldp+2040,((7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))),3); - bufp->fullWData(oldp+2041,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted),512); - bufp->fullCData(oldp+2057,((0xfU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc - >> 2U))),4); - bufp->fullBit(oldp+2058,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)); - bufp->fullIData(oldp+2059,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[0]),32); - bufp->fullIData(oldp+2060,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[1]),32); - bufp->fullIData(oldp+2061,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[2]),32); - bufp->fullIData(oldp+2062,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[3]),32); - bufp->fullIData(oldp+2063,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[4]),32); - bufp->fullIData(oldp+2064,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[5]),32); - bufp->fullIData(oldp+2065,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[6]),32); - bufp->fullIData(oldp+2066,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[7]),32); - bufp->fullIData(oldp+2067,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[8]),32); - bufp->fullIData(oldp+2068,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[9]),32); - bufp->fullIData(oldp+2069,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[10]),32); - bufp->fullIData(oldp+2070,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[11]),32); - bufp->fullIData(oldp+2071,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[12]),32); - bufp->fullIData(oldp+2072,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[13]),32); - bufp->fullIData(oldp+2073,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[14]),32); - bufp->fullIData(oldp+2074,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[15]),32); - bufp->fullIData(oldp+2075,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[16]),32); - bufp->fullIData(oldp+2076,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[17]),32); - bufp->fullIData(oldp+2077,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[18]),32); - bufp->fullIData(oldp+2078,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[19]),32); - bufp->fullIData(oldp+2079,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[20]),32); - bufp->fullIData(oldp+2080,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[21]),32); - bufp->fullIData(oldp+2081,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[22]),32); - bufp->fullIData(oldp+2082,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[23]),32); - bufp->fullIData(oldp+2083,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[24]),32); - bufp->fullIData(oldp+2084,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[25]),32); - bufp->fullIData(oldp+2085,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[26]),32); - bufp->fullIData(oldp+2086,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[27]),32); - bufp->fullIData(oldp+2087,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[28]),32); - bufp->fullIData(oldp+2088,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[29]),32); - bufp->fullIData(oldp+2089,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[30]),32); - bufp->fullIData(oldp+2090,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[31]),32); - bufp->fullCData(oldp+2091,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__flags),4); - bufp->fullCData(oldp+2092,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__iflags),4); - bufp->fullSData(oldp+2093,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags),16); - bufp->fullSData(oldp+2094,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags),16); - bufp->fullBit(oldp+2095,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en)); - bufp->fullBit(oldp+2096,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step)); - bufp->fullBit(oldp+2097,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep)); - bufp->fullBit(oldp+2098,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted)); - bufp->fullBit(oldp+2099,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending)); - bufp->fullBit(oldp+2100,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap)); - bufp->fullBit(oldp+2101,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)); - bufp->fullBit(oldp+2102,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak)); - bufp->fullBit(oldp+2103,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt)); - bufp->fullBit(oldp+2104,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped)); - bufp->fullBit(oldp+2105,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step)); - bufp->fullBit(oldp+2106,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u)); - bufp->fullBit(oldp+2107,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i)); - bufp->fullBit(oldp+2108,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag)); - bufp->fullBit(oldp+2109,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag)); - bufp->fullBit(oldp+2110,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag)); - bufp->fullBit(oldp+2111,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag)); - bufp->fullBit(oldp+2112,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase)); - bufp->fullBit(oldp+2113,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase)); - bufp->fullBit(oldp+2114,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce)); - bufp->fullIData(oldp+2115,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc),28); - bufp->fullBit(oldp+2116,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)); - bufp->fullCData(oldp+2117,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_opn),4); - bufp->fullBit(oldp+2118,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)); - bufp->fullCData(oldp+2119,((0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))),5); - bufp->fullCData(oldp+2120,((0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))),5); - bufp->fullCData(oldp+2121,((0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R))),5); - bufp->fullCData(oldp+2122,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA),5); - bufp->fullCData(oldp+2123,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB),5); - bufp->fullBit(oldp+2124,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U)))); - bufp->fullBit(oldp+2125,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U)))); - bufp->fullBit(oldp+2126,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 5U)))); - bufp->fullBit(oldp+2127,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 5U)))); - bufp->fullBit(oldp+2128,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R) - >> 6U)))); - bufp->fullBit(oldp+2129,((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R) - >> 5U)))); - bufp->fullCData(oldp+2130,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F),4); - bufp->fullBit(oldp+2131,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wR)); - bufp->fullBit(oldp+2132,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA)); - bufp->fullBit(oldp+2133,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB)); - bufp->fullBit(oldp+2134,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ALU)); - bufp->fullBit(oldp+2135,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_M)); - bufp->fullBit(oldp+2136,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_DIV)); - bufp->fullBit(oldp+2137,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_FP)); - bufp->fullBit(oldp+2138,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wF)); - bufp->fullBit(oldp+2139,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_break)); - bufp->fullBit(oldp+2140,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_lock)); - bufp->fullBit(oldp+2141,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe)); - bufp->fullBit(oldp+2142,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp)); - bufp->fullBit(oldp+2143,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid)); - bufp->fullIData(oldp+2144,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I),32); - bufp->fullBit(oldp+2145,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI)); - bufp->fullBit(oldp+2146,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal)); - bufp->fullBit(oldp+2147,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)); - bufp->fullBit(oldp+2148,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb)); - bufp->fullIData(oldp+2149,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc),28); - bufp->fullBit(oldp+2150,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall)); - bufp->fullBit(oldp+2151,((1U >= (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))); - bufp->fullBit(oldp+2152,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)); - bufp->fullBit(oldp+2153,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write)); - bufp->fullBit(oldp+2154,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem)); - bufp->fullBit(oldp+2155,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu)); - bufp->fullBit(oldp+2156,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div)); - bufp->fullBit(oldp+2157,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_fpu)); - bufp->fullCData(oldp+2158,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn),4); - bufp->fullBit(oldp+2159,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_Rcc)); - bufp->fullCData(oldp+2160,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Aid),5); - bufp->fullCData(oldp+2161,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid),5); - bufp->fullBit(oldp+2162,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rA)); - bufp->fullBit(oldp+2163,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB)); - bufp->fullIData(oldp+2164,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av),32); - bufp->fullIData(oldp+2165,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv),32); - bufp->fullIData(oldp+2166,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc),28); - bufp->fullIData(oldp+2167,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av),32); - bufp->fullIData(oldp+2168,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv),32); - bufp->fullIData(oldp+2169,(((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv - : (0xeb800000U - | ((0x7f0000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv) - | ((0x10U - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags))))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - : 0U))),32); - bufp->fullBit(oldp+2170,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR)); - bufp->fullBit(oldp+2171,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_wF)); - bufp->fullCData(oldp+2172,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0))),4); - bufp->fullCData(oldp+2173,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F),7); - bufp->fullCData(oldp+2174,(((0x80U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F) - << 4U)) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F))),8); - bufp->fullBit(oldp+2175,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase)); - bufp->fullBit(oldp+2176,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe)); - bufp->fullBit(oldp+2177,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break)); - bufp->fullBit(oldp+2178,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_valid)); - bufp->fullBit(oldp+2179,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal)); - bufp->fullBit(oldp+2180,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock)); - bufp->fullIData(oldp+2181,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc),28); - bufp->fullCData(oldp+2182,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg),5); - bufp->fullBit(oldp+2183,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid)); - bufp->fullBit(oldp+2184,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid)); - bufp->fullBit(oldp+2185,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid)); - bufp->fullBit(oldp+2186,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)); - bufp->fullIData(oldp+2187,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result),32); - bufp->fullCData(oldp+2188,(((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)) - << 3U) | ((4U & ((4U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - >> 0x1dU)) - ^ - (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)) - << 2U))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c) - << 1U) - | (0U - == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result))))),4); - bufp->fullBit(oldp+2189,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid)); - bufp->fullBit(oldp+2190,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)); - bufp->fullBit(oldp+2191,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond)); - bufp->fullBit(oldp+2192,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR)); - bufp->fullBit(oldp+2193,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF)); - bufp->fullBit(oldp+2194,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal)); - bufp->fullBit(oldp+2195,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error)); - bufp->fullBit(oldp+2196,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy)); - bufp->fullBit(oldp+2197,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid)); - bufp->fullIData(oldp+2198,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result),32); - bufp->fullCData(oldp+2199,(((4U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - >> 0x1dU)) | - (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z)))),4); 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- bufp->fullBit(oldp+2321,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB)); - bufp->fullBit(oldp+2322,(((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - | (8U == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))))); - bufp->fullBit(oldp+2323,((0x7c87c000U == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - bufp->fullBit(oldp+2324,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_ljmp)); - bufp->fullIData(oldp+2325,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword),32); - bufp->fullBit(oldp+2326,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid)); - bufp->fullSData(oldp+2327,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_nxt_half),15); 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((1U - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? - ((0x7fc000U - & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xdU)))) - << 0xeU)) - | (0x3fffU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - : - ((0x7c0000U - & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x11U)))) - << 0x12U)) - | (0x3ffffU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))) - : ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? - ((0x7fe000U - & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xcU)))) - << 0xdU)) - | (0x1fffU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)))),23); 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- bufp->fullBit(oldp+2350,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write)); - bufp->fullBit(oldp+2351,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload)); - bufp->fullIData(oldp+2352,(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_interval_count),31); - bufp->fullBit(oldp+2353,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_b__i_wb_stb)); - bufp->fullBit(oldp+2354,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running)); - bufp->fullBit(oldp+2355,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero)); - bufp->fullIData(oldp+2356,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value),31); - bufp->fullBit(oldp+2357,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write)); - bufp->fullBit(oldp+2358,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload)); - bufp->fullIData(oldp+2359,(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_interval_count),31); - bufp->fullBit(oldp+2360,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_c__i_wb_stb)); - bufp->fullBit(oldp+2361,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running)); - bufp->fullBit(oldp+2362,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero)); - bufp->fullIData(oldp+2363,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value),31); - bufp->fullBit(oldp+2364,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write)); - bufp->fullBit(oldp+2365,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload)); - bufp->fullIData(oldp+2366,(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_interval_count),31); - bufp->fullBit(oldp+2367,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchbus____pinNumber2)); - bufp->fullSData(oldp+2368,(vlSelf->main__DOT__swic__DOT__u_watchbus__DOT__r_value),14); - bufp->fullBit(oldp+2369,(vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchdog__i_wb_stb)); - bufp->fullBit(oldp+2370,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running)); - bufp->fullBit(oldp+2371,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_zero)); - bufp->fullIData(oldp+2372,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value),31); - bufp->fullBit(oldp+2373,(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__wb_write)); - bufp->fullCData(oldp+2374,(vlSelf->main__DOT__txv__DOT__baud_counter),7); - bufp->fullCData(oldp+2375,(vlSelf->main__DOT__txv__DOT__state),4); - bufp->fullCData(oldp+2376,(vlSelf->main__DOT__txv__DOT__lcl_data),8); - bufp->fullBit(oldp+2377,(vlSelf->main__DOT__txv__DOT__zero_baud_counter)); - bufp->fullBit(oldp+2378,(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)); - bufp->fullCData(oldp+2379,(vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift),5); - bufp->fullCData(oldp+2380,(vlSelf->main__DOT__u_emmc__DOT__sdclk),8); - bufp->fullBit(oldp+2381,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)); - bufp->fullBit(oldp+2382,(vlSelf->main__DOT__u_emmc__DOT__pp_cmd)); - bufp->fullCData(oldp+2383,((3U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2eU)))),2); - bufp->fullBit(oldp+2384,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)); - bufp->fullBit(oldp+2385,(vlSelf->main__DOT__u_emmc__DOT__pp_data)); - bufp->fullBit(oldp+2386,(vlSelf->main__DOT__u_emmc__DOT__rx_en)); - bufp->fullIData(oldp+2387,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data),32); - bufp->fullBit(oldp+2388,(((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds)))); - bufp->fullCData(oldp+2389,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) - << 1U)),2); - bufp->fullCData(oldp+2390,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data) - << 1U)),2); - bufp->fullBit(oldp+2391,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy)); - bufp->fullCData(oldp+2392,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U)),2); - bufp->fullSData(oldp+2393,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - << 8U)),16); - bufp->fullBit(oldp+2394,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy)); - bufp->fullBit(oldp+2395,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge)); - bufp->fullBit(oldp+2396,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge)); - bufp->fullBit(oldp+2397,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__resp_started)); - bufp->fullBit(oldp+2398,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__io_started)); - bufp->fullBit(oldp+2399,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck)); - bufp->fullBit(oldp+2400,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data)); - bufp->fullBit(oldp+2401,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb)); - bufp->fullBit(oldp+2402,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb)); - bufp->fullCData(oldp+2403,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data),8); - bufp->fullCData(oldp+2404,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg),2); - bufp->fullCData(oldp+2405,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg),2); - bufp->fullBit(oldp+2406,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck)); - bufp->fullBit(oldp+2407,(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck)); - bufp->fullBit(oldp+2408,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset)); - bufp->fullBit(oldp+2409,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90)); - bufp->fullBit(oldp+2410,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown)); - bufp->fullBit(oldp+2411,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds)); - bufp->fullCData(oldp+2412,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed),8); - bufp->fullCData(oldp+2413,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width),2); - bufp->fullBit(oldp+2414,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb)); - bufp->fullBit(oldp+2415,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_half)); - bufp->fullCData(oldp+2416,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__w_sdclk),8); - bufp->fullCData(oldp+2417,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_ckspd),8); - bufp->fullBit(oldp+2418,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request)); - bufp->fullBit(oldp+2419,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err)); - bufp->fullBit(oldp+2420,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)); - bufp->fullBit(oldp+2421,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done)); - bufp->fullCData(oldp+2422,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type),2); - bufp->fullCData(oldp+2423,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode),2); - bufp->fullBit(oldp+2424,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb)); - bufp->fullCData(oldp+2425,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd),7); - bufp->fullCData(oldp+2426,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_id),6); - bufp->fullIData(oldp+2427,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg),32); - bufp->fullIData(oldp+2428,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_arg),32); - bufp->fullBit(oldp+2429,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid)); - bufp->fullSData(oldp+2430,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr),10); - bufp->fullIData(oldp+2431,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_data),32); - bufp->fullBit(oldp+2432,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)); - bufp->fullBit(oldp+2433,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)); - bufp->fullBit(oldp+2434,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready)); - bufp->fullBit(oldp+2435,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last)); - bufp->fullIData(oldp+2436,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data),32); - bufp->fullSData(oldp+2437,((0x1fffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk)))),13); - bufp->fullBit(oldp+2438,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid)); - bufp->fullSData(oldp+2439,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr),10); - bufp->fullCData(oldp+2440,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb),4); - bufp->fullIData(oldp+2441,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data),32); - bufp->fullBit(oldp+2442,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done)); - bufp->fullBit(oldp+2443,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_err)); - bufp->fullBit(oldp+2444,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb)); - bufp->fullBit(oldp+2445,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk)); - bufp->fullSData(oldp+2446,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter),10); - bufp->fullSData(oldp+2447,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter),10); - bufp->fullBit(oldp+2448,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__clk90)); - bufp->fullCData(oldp+2449,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd),8); - bufp->fullBit(oldp+2450,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90)); - bufp->fullCData(oldp+2451,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd),8); - bufp->fullBit(oldp+2452,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)); - bufp->fullBit(oldp+2453,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)); - bufp->fullBit(oldp+2454,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)); - bufp->fullBit(oldp+2455,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent)); - bufp->fullBit(oldp+2456,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)); - bufp->fullBit(oldp+2457,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err)); - bufp->fullCData(oldp+2458,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode),2); - bufp->fullCData(oldp+2459,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk),4); - bufp->fullIData(oldp+2460,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word),32); - bufp->fullIData(oldp+2461,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl),32); - bufp->fullSData(oldp+2462,((0xffffU & (((0xfU >= - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? ((IData)(1U) - << - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - - (IData)(1U)))),16); - bufp->fullIData(oldp+2463,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ika),32); - bufp->fullIData(oldp+2464,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ikb),32); - bufp->fullIData(oldp+2465,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a),32); - bufp->fullIData(oldp+2466,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b),32); - bufp->fullSData(oldp+2467,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr),10); - bufp->fullSData(oldp+2468,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr),10); - bufp->fullSData(oldp+2469,((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)) - ? (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))),10); - bufp->fullSData(oldp+2470,((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - ? (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))),10); - bufp->fullSData(oldp+2471,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr),10); - bufp->fullIData(oldp+2472,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - ? vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b - : vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a)),32); - bufp->fullBit(oldp+2473,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last)); - bufp->fullBit(oldp+2474,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - >= (0xffffU & (((0xfU - >= - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? - ((IData)(1U) - << - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - - (IData)(1U))))))); - bufp->fullBit(oldp+2475,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid)); - bufp->fullBit(oldp+2476,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_ack)); - bufp->fullCData(oldp+2477,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel),2); - bufp->fullIData(oldp+2478,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data),32); - bufp->fullSData(oldp+2479,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a),10); - bufp->fullSData(oldp+2480,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b),10); - bufp->fullCData(oldp+2481,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a),4); - bufp->fullCData(oldp+2482,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b),4); - bufp->fullIData(oldp+2483,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a),32); - bufp->fullIData(oldp+2484,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b),32); - bufp->fullBit(oldp+2485,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)); - bufp->fullCData(oldp+2486,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill),5); - bufp->fullIData(oldp+2487,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg),20); - bufp->fullBit(oldp+2488,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid)); - bufp->fullCData(oldp+2489,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill),2); - bufp->fullSData(oldp+2490,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data),16); - bufp->fullBit(oldp+2491,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)); - bufp->fullBit(oldp+2492,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb)); - bufp->fullCData(oldp+2493,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr),2); - bufp->fullCData(oldp+2494,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr),2); - bufp->fullCData(oldp+2495,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data),8); - bufp->fullBit(oldp+2496,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy)); - bufp->fullBit(oldp+2497,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)); - bufp->fullBit(oldp+2498,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)); - bufp->fullBit(oldp+2499,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc)); - bufp->fullSData(oldp+2500,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count),16); - bufp->fullCData(oldp+2501,(((0x80U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err) - << 6U)) | - ((0x40U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err) - << 5U)) - | ((0x20U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err) - << 4U)) - | ((0x10U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err) - << 3U)) - | ((8U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err) - << 3U)) - | ((4U & - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err) - << 2U)) - | ((2U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err)))))))))),8); - bufp->fullIData(oldp+2502,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout),23); - bufp->fullBit(oldp+2503,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog)); - bufp->fullBit(oldp+2504,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb)); - bufp->fullBit(oldp+2505,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done)); - bufp->fullSData(oldp+2506,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc),16); - bufp->fullSData(oldp+2507,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc),16); - bufp->fullCData(oldp+2508,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err),2); - bufp->fullSData(oldp+2509,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc),16); - bufp->fullSData(oldp+2510,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc),16); - bufp->fullCData(oldp+2511,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err),2); - bufp->fullSData(oldp+2512,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc),16); - bufp->fullSData(oldp+2513,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc),16); - bufp->fullCData(oldp+2514,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err),2); - bufp->fullSData(oldp+2515,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc),16); - bufp->fullSData(oldp+2516,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc),16); - bufp->fullCData(oldp+2517,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err),2); - bufp->fullBit(oldp+2518,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl)); - bufp->fullCData(oldp+2519,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount),6); - bufp->fullQData(oldp+2520,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg),48); - bufp->fullBit(oldp+2522,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response)); - bufp->fullBit(oldp+2523,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds)); - bufp->fullBit(oldp+2524,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl)); - bufp->fullBit(oldp+2525,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err)); - bufp->fullCData(oldp+2526,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type),2); - bufp->fullCData(oldp+2527,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count),8); - bufp->fullBit(oldp+2528,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - >> 1U) & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x30U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)))) - | ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x88U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))))))); - bufp->fullBit(oldp+2529,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done)); - bufp->fullBit(oldp+2530,(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) - & (9U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill))))); - bufp->fullBit(oldp+2531,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)); - bufp->fullQData(oldp+2532,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg),40); - bufp->fullBit(oldp+2534,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout)); - bufp->fullIData(oldp+2535,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter),26); - bufp->fullCData(oldp+2536,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill),7); - bufp->fullBit(oldp+2537,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy)); - bufp->fullBit(oldp+2538,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data)); - bufp->fullBit(oldp+2539,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)); - bufp->fullBit(oldp+2540,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID)); - bufp->fullBit(oldp+2541,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)); - bufp->fullCData(oldp+2542,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width),2); - bufp->fullCData(oldp+2543,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period),2); - bufp->fullBit(oldp+2544,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet)); - bufp->fullBit(oldp+2545,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid)); - bufp->fullCData(oldp+2546,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate),2); - bufp->fullBit(oldp+2547,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready)); - bufp->fullIData(oldp+2548,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data),32); - bufp->fullCData(oldp+2549,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count),4); - bufp->fullSData(oldp+2550,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg),16); - bufp->fullIData(oldp+2551,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w),32); - bufp->fullIData(oldp+2552,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w),32); - bufp->fullIData(oldp+2553,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w),32); - bufp->fullIData(oldp+2554,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg),32); - bufp->fullQData(oldp+2555,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w),64); - bufp->fullQData(oldp+2557,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w),64); - bufp->fullQData(oldp+2559,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w),64); - bufp->fullQData(oldp+2561,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg),64); - bufp->fullWData(oldp+2563,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w),128); - bufp->fullWData(oldp+2567,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w),128); - bufp->fullWData(oldp+2571,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w),128); - bufp->fullWData(oldp+2575,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg),128); - bufp->fullWData(oldp+2579,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d),256); - bufp->fullWData(oldp+2587,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d),256); - bufp->fullWData(oldp+2595,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d),256); - bufp->fullWData(oldp+2603,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg),256); - bufp->fullCData(oldp+2611,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts),5); - bufp->fullIData(oldp+2612,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg),32); - bufp->fullBit(oldp+2613,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit)); - bufp->fullSData(oldp+2614,(vlSelf->main__DOT__u_fan__DOT__pwm_counter),13); - bufp->fullSData(oldp+2615,(vlSelf->main__DOT__u_fan__DOT__ctl_fpga),13); - bufp->fullSData(oldp+2616,(vlSelf->main__DOT__u_fan__DOT__ctl_sys),13); - bufp->fullBit(oldp+2617,(vlSelf->main__DOT__u_fan__DOT__ck_tach)); - bufp->fullBit(oldp+2618,(vlSelf->main__DOT__u_fan__DOT__last_tach)); - bufp->fullCData(oldp+2619,(vlSelf->main__DOT__u_fan__DOT__pipe_tach),2); - bufp->fullBit(oldp+2620,(vlSelf->main__DOT__u_fan__DOT__tach_reset)); - bufp->fullIData(oldp+2621,(vlSelf->main__DOT__u_fan__DOT__tach_count),27); - bufp->fullIData(oldp+2622,(vlSelf->main__DOT__u_fan__DOT__tach_counter),27); - bufp->fullIData(oldp+2623,(vlSelf->main__DOT__u_fan__DOT__tach_timer),27); - bufp->fullBit(oldp+2624,(vlSelf->main__DOT__u_fan__DOT__i2c_wb_ack)); - bufp->fullIData(oldp+2625,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data),32); - bufp->fullBit(oldp+2626,(vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc)); - bufp->fullBit(oldp+2627,(vlSelf->main__DOT__u_fan__DOT__mem_stb)); - bufp->fullCData(oldp+2628,(vlSelf->main__DOT__u_fan__DOT__mem_addr),5); - bufp->fullCData(oldp+2629,(vlSelf->main__DOT__u_fan__DOT__mem_data),8); - bufp->fullBit(oldp+2630,(vlSelf->main__DOT__u_fan__DOT__mem_ack)); - bufp->fullBit(oldp+2631,(vlSelf->main__DOT__u_fan__DOT__i2cd_valid)); - bufp->fullBit(oldp+2632,(vlSelf->main__DOT__u_fan__DOT__i2cd_last)); - bufp->fullCData(oldp+2633,(vlSelf->main__DOT__u_fan__DOT__i2cd_data),8); - bufp->fullBit(oldp+2634,(vlSelf->main__DOT__u_fan__DOT__pp_ms)); - bufp->fullIData(oldp+2635,(vlSelf->main__DOT__u_fan__DOT__trigger_counter),17); - bufp->fullIData(oldp+2636,(vlSelf->main__DOT__u_fan__DOT__temp_tmp),24); - bufp->fullIData(oldp+2637,(vlSelf->main__DOT__u_fan__DOT__temp_data),32); - bufp->fullBit(oldp+2638,(vlSelf->main__DOT__u_fan__DOT__pre_ack)); - bufp->fullIData(oldp+2639,(vlSelf->main__DOT__u_fan__DOT__pre_data),32); - bufp->fullBit(oldp+2640,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted)); - bufp->fullBit(oldp+2641,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc)); - bufp->fullCData(oldp+2642,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr),5); - bufp->fullBit(oldp+2643,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid)); - bufp->fullBit(oldp+2644,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)); - bufp->fullCData(oldp+2645,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn),8); - bufp->fullCData(oldp+2646,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr),5); - bufp->fullBit(oldp+2647,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal)); - bufp->fullBit(oldp+2648,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid)); - bufp->fullBit(oldp+2649,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle)); - bufp->fullBit(oldp+2650,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready)); - bufp->fullBit(oldp+2651,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready)); - bufp->fullBit(oldp+2652,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort)); - bufp->fullBit(oldp+2653,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid)); - bufp->fullSData(oldp+2654,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn),12); - bufp->fullCData(oldp+2655,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn),4); - bufp->fullBit(oldp+2656,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge)); - bufp->fullBit(oldp+2657,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch)); - bufp->fullSData(oldp+2658,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount),12); - bufp->fullSData(oldp+2659,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount),12); - bufp->fullCData(oldp+2660,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__abort_address),5); - bufp->fullCData(oldp+2661,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__jump_target),5); - bufp->fullBit(oldp+2662,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait)); - bufp->fullBit(oldp+2663,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request)); - bufp->fullBit(oldp+2664,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err)); - bufp->fullBit(oldp+2665,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted)); - bufp->fullBit(oldp+2666,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual)); - bufp->fullBit(oldp+2667,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda)); - bufp->fullBit(oldp+2668,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl)); - bufp->fullBit(oldp+2669,(((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait)))); - bufp->fullBit(oldp+2670,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda)); - bufp->fullBit(oldp+2671,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl)); - bufp->fullBit(oldp+2672,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_ready)); - bufp->fullBit(oldp+2673,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid)); - bufp->fullSData(oldp+2674,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data),10); - bufp->fullBit(oldp+2675,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl)); - bufp->fullBit(oldp+2676,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda)); - bufp->fullSData(oldp+2677,((0x7ffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))),11); - bufp->fullBit(oldp+2678,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte)); - bufp->fullBit(oldp+2679,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir)); - bufp->fullBit(oldp+2680,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack)); - bufp->fullCData(oldp+2681,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state),4); - bufp->fullCData(oldp+2682,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits),3); - bufp->fullCData(oldp+2683,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg),8); - bufp->fullBit(oldp+2684,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_scl)); - bufp->fullBit(oldp+2685,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_sda)); - bufp->fullBit(oldp+2686,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)); - bufp->fullBit(oldp+2687,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda)); - bufp->fullBit(oldp+2688,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_scl)); - bufp->fullBit(oldp+2689,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_sda)); - bufp->fullBit(oldp+2690,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__stop_bit)); - bufp->fullBit(oldp+2691,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy)); - bufp->fullBit(oldp+2692,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__last_stb)); - bufp->fullBit(oldp+2693,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle)); - bufp->fullCData(oldp+2694,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_word),8); - bufp->fullBit(oldp+2695,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid)); - bufp->fullCData(oldp+2696,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight),2); - bufp->fullBit(oldp+2697,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_illegal)); - bufp->fullBit(oldp+2698,(vlSelf->main__DOT____Vcellinp__u_i2cdma__S_VALID)); - bufp->fullIData(oldp+2699,(vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr),28); - bufp->fullIData(oldp+2700,(vlSelf->main__DOT__u_i2cdma__DOT__r_memlen),28); - bufp->fullCData(oldp+2701,(vlSelf->main__DOT__u_i2cdma__DOT__subaddr),6); - bufp->fullIData(oldp+2702,(vlSelf->main__DOT__u_i2cdma__DOT__current_addr),28); - bufp->fullBit(oldp+2703,(vlSelf->main__DOT__u_i2cdma__DOT__wb_last)); - bufp->fullBit(oldp+2704,(vlSelf->main__DOT__u_i2cdma__DOT__bus_err)); - bufp->fullBit(oldp+2705,(vlSelf->main__DOT__u_i2cdma__DOT__r_reset)); - bufp->fullBit(oldp+2706,(vlSelf->main__DOT__u_i2cdma__DOT__r_overflow)); - bufp->fullBit(oldp+2707,(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid)); - bufp->fullBit(oldp+2708,(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready)); - bufp->fullBit(oldp+2709,((1U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - >> 8U)))); - bufp->fullCData(oldp+2710,((0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))),8); - bufp->fullSData(oldp+2711,(vlSelf->main__DOT__u_i2cdma__DOT____Vcellinp__sskd__i_data),9); - bufp->fullSData(oldp+2712,(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data),9); - bufp->fullSData(oldp+2713,(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_data),9); - bufp->fullBit(oldp+2714,(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid)); - bufp->fullBit(oldp+2715,(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)); - bufp->fullCData(oldp+2716,(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift),5); - bufp->fullCData(oldp+2717,(vlSelf->main__DOT__u_sdcard__DOT__sdclk),8); - bufp->fullBit(oldp+2718,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active)); - bufp->fullBit(oldp+2719,(vlSelf->main__DOT__u_sdcard__DOT__pp_cmd)); - bufp->fullCData(oldp+2720,((3U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2eU)))),2); - bufp->fullBit(oldp+2721,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)); - bufp->fullBit(oldp+2722,(vlSelf->main__DOT__u_sdcard__DOT__pp_data)); - bufp->fullBit(oldp+2723,(vlSelf->main__DOT__u_sdcard__DOT__rx_en)); - bufp->fullIData(oldp+2724,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data),32); - bufp->fullBit(oldp+2725,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds)))); - bufp->fullCData(oldp+2726,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) - << 1U)),2); - bufp->fullCData(oldp+2727,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data) - << 1U)),2); - bufp->fullBit(oldp+2728,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy)); - bufp->fullCData(oldp+2729,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U)),2); - bufp->fullSData(oldp+2730,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - << 8U)),16); - bufp->fullBit(oldp+2731,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy)); - bufp->fullCData(oldp+2732,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->fullBit(oldp+2733,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0])); - bufp->fullBit(oldp+2734,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[1])); - bufp->fullBit(oldp+2735,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[2])); - bufp->fullBit(oldp+2736,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[3])); - bufp->fullBit(oldp+2737,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[4])); - bufp->fullBit(oldp+2738,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[5])); - bufp->fullBit(oldp+2739,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[6])); - bufp->fullBit(oldp+2740,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[7])); - bufp->fullBit(oldp+2741,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[8])); - bufp->fullBit(oldp+2742,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[9])); - bufp->fullBit(oldp+2743,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[10])); - bufp->fullBit(oldp+2744,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[11])); - bufp->fullBit(oldp+2745,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[12])); - bufp->fullBit(oldp+2746,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[13])); - bufp->fullBit(oldp+2747,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[14])); - bufp->fullBit(oldp+2748,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[15])); - bufp->fullSData(oldp+2749,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat),16); - bufp->fullCData(oldp+2750,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge),2); - bufp->fullCData(oldp+2751,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge),2); - bufp->fullCData(oldp+2752,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg),6); - bufp->fullCData(oldp+2753,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pck_sreg),6); - bufp->fullCData(oldp+2754,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck),2); - bufp->fullCData(oldp+2755,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck),2); - bufp->fullBit(oldp+2756,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__resp_started)); - bufp->fullBit(oldp+2757,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__io_started)); - bufp->fullBit(oldp+2758,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck)); - bufp->fullBit(oldp+2759,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb)); - bufp->fullBit(oldp+2760,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data)); - bufp->fullBit(oldp+2761,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb)); - bufp->fullCData(oldp+2762,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data),8); - bufp->fullBit(oldp+2763,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__high_z)); - bufp->fullCData(oldp+2764,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out),8); - bufp->fullBit(oldp+2765,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z)); - bufp->fullCData(oldp+2766,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->fullCData(oldp+2767,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out),2); - bufp->fullBit(oldp+2768,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->fullBit(oldp+2769,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z)); - bufp->fullCData(oldp+2770,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->fullCData(oldp+2771,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out),2); - bufp->fullBit(oldp+2772,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->fullBit(oldp+2773,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z)); - bufp->fullCData(oldp+2774,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->fullCData(oldp+2775,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out),2); - bufp->fullBit(oldp+2776,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->fullBit(oldp+2777,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z)); - bufp->fullCData(oldp+2778,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in),2); - bufp->fullCData(oldp+2779,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out),2); - bufp->fullBit(oldp+2780,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->fullCData(oldp+2781,(((2U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 6U)) | (1U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 3U)))),2); - bufp->fullCData(oldp+2782,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out),2); - bufp->fullBit(oldp+2783,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z)); - bufp->fullCData(oldp+2784,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out),2); - bufp->fullBit(oldp+2785,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p)); - bufp->fullBit(oldp+2786,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset)); - bufp->fullBit(oldp+2787,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90)); - bufp->fullBit(oldp+2788,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown)); - bufp->fullBit(oldp+2789,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds)); - bufp->fullCData(oldp+2790,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed),8); - bufp->fullCData(oldp+2791,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width),2); - bufp->fullBit(oldp+2792,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb)); - bufp->fullBit(oldp+2793,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half)); - bufp->fullCData(oldp+2794,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk),8); - bufp->fullCData(oldp+2795,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_ckspd),8); - bufp->fullBit(oldp+2796,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request)); - bufp->fullBit(oldp+2797,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err)); - bufp->fullBit(oldp+2798,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)); - bufp->fullBit(oldp+2799,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done)); - bufp->fullCData(oldp+2800,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type),2); - bufp->fullCData(oldp+2801,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode),2); - bufp->fullBit(oldp+2802,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb)); - bufp->fullCData(oldp+2803,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd),7); - bufp->fullCData(oldp+2804,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id),6); - bufp->fullIData(oldp+2805,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg),32); - bufp->fullIData(oldp+2806,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg),32); - bufp->fullBit(oldp+2807,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid)); - bufp->fullSData(oldp+2808,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr),10); - bufp->fullIData(oldp+2809,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_data),32); - bufp->fullBit(oldp+2810,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)); - bufp->fullBit(oldp+2811,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)); - bufp->fullBit(oldp+2812,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready)); - bufp->fullBit(oldp+2813,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last)); - bufp->fullIData(oldp+2814,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data),32); - bufp->fullSData(oldp+2815,((0x1fffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk)))),13); - bufp->fullBit(oldp+2816,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid)); - bufp->fullSData(oldp+2817,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr),10); - bufp->fullCData(oldp+2818,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb),4); - bufp->fullIData(oldp+2819,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data),32); - bufp->fullBit(oldp+2820,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done)); - bufp->fullBit(oldp+2821,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err)); - bufp->fullBit(oldp+2822,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb)); - bufp->fullBit(oldp+2823,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk)); - bufp->fullSData(oldp+2824,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter),10); - bufp->fullSData(oldp+2825,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter),10); - bufp->fullBit(oldp+2826,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__clk90)); - bufp->fullCData(oldp+2827,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd),8); - bufp->fullBit(oldp+2828,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90)); - bufp->fullCData(oldp+2829,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd),8); - bufp->fullBit(oldp+2830,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)); - bufp->fullBit(oldp+2831,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)); - bufp->fullBit(oldp+2832,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)); - bufp->fullBit(oldp+2833,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent)); - bufp->fullBit(oldp+2834,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)); - bufp->fullBit(oldp+2835,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err)); - bufp->fullCData(oldp+2836,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode),2); - bufp->fullCData(oldp+2837,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk),4); - bufp->fullIData(oldp+2838,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word),32); - bufp->fullIData(oldp+2839,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl),32); - bufp->fullSData(oldp+2840,((0xffffU & (((0xfU >= - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? ((IData)(1U) - << - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - - (IData)(1U)))),16); - bufp->fullIData(oldp+2841,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ika),32); - bufp->fullIData(oldp+2842,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ikb),32); - bufp->fullIData(oldp+2843,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a),32); - bufp->fullIData(oldp+2844,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b),32); - bufp->fullSData(oldp+2845,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr),10); - bufp->fullSData(oldp+2846,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr),10); - bufp->fullSData(oldp+2847,((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)) - ? (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))),10); - bufp->fullSData(oldp+2848,((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - ? (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))),10); - bufp->fullSData(oldp+2849,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr),10); - bufp->fullIData(oldp+2850,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - ? vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b - : vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a)),32); - bufp->fullBit(oldp+2851,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last)); - bufp->fullBit(oldp+2852,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - >= (0xffffU & (((0xfU - >= - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? - ((IData)(1U) - << - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - - (IData)(1U))))))); - bufp->fullBit(oldp+2853,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid)); - bufp->fullBit(oldp+2854,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present)); - bufp->fullBit(oldp+2855,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_removed)); - bufp->fullBit(oldp+2856,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_ack)); - bufp->fullCData(oldp+2857,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel),2); - bufp->fullIData(oldp+2858,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data),32); - bufp->fullSData(oldp+2859,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a),10); - bufp->fullSData(oldp+2860,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b),10); - bufp->fullCData(oldp+2861,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a),4); - bufp->fullCData(oldp+2862,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b),4); - bufp->fullIData(oldp+2863,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a),32); - bufp->fullIData(oldp+2864,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b),32); - bufp->fullBit(oldp+2865,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)); - bufp->fullCData(oldp+2866,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present),3); - bufp->fullSData(oldp+2867,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter),10); - bufp->fullCData(oldp+2868,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill),5); - bufp->fullIData(oldp+2869,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg),20); - bufp->fullBit(oldp+2870,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid)); - bufp->fullCData(oldp+2871,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill),2); - bufp->fullSData(oldp+2872,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data),16); - bufp->fullBit(oldp+2873,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)); - bufp->fullBit(oldp+2874,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb)); - bufp->fullCData(oldp+2875,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr),2); - bufp->fullCData(oldp+2876,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr),2); - bufp->fullCData(oldp+2877,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data),8); - bufp->fullBit(oldp+2878,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy)); - bufp->fullBit(oldp+2879,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)); - bufp->fullBit(oldp+2880,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)); - bufp->fullBit(oldp+2881,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc)); - bufp->fullSData(oldp+2882,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count),16); - bufp->fullCData(oldp+2883,(((0x80U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err) - << 6U)) | - ((0x40U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err) - << 5U)) - | ((0x20U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err) - << 4U)) - | ((0x10U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err) - << 3U)) - | ((8U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err) - << 3U)) - | ((4U & - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err) - << 2U)) - | ((2U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err)))))))))),8); - bufp->fullIData(oldp+2884,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout),23); - bufp->fullBit(oldp+2885,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog)); - bufp->fullBit(oldp+2886,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb)); - bufp->fullBit(oldp+2887,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done)); - bufp->fullSData(oldp+2888,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc),16); - bufp->fullSData(oldp+2889,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc),16); - bufp->fullCData(oldp+2890,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err),2); - bufp->fullSData(oldp+2891,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc),16); - bufp->fullSData(oldp+2892,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc),16); - bufp->fullCData(oldp+2893,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err),2); - bufp->fullSData(oldp+2894,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc),16); - bufp->fullSData(oldp+2895,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc),16); - bufp->fullCData(oldp+2896,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err),2); - bufp->fullSData(oldp+2897,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc),16); - bufp->fullSData(oldp+2898,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc),16); - bufp->fullCData(oldp+2899,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err),2); - bufp->fullBit(oldp+2900,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl)); - bufp->fullCData(oldp+2901,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount),6); - bufp->fullQData(oldp+2902,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg),48); - bufp->fullBit(oldp+2904,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response)); - bufp->fullBit(oldp+2905,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds)); - bufp->fullBit(oldp+2906,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl)); - bufp->fullBit(oldp+2907,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err)); - bufp->fullCData(oldp+2908,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type),2); - bufp->fullCData(oldp+2909,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count),8); - bufp->fullBit(oldp+2910,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - >> 1U) & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x30U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)))) - | ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x88U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))))))); - bufp->fullBit(oldp+2911,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done)); - bufp->fullBit(oldp+2912,(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) - & (9U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill))))); - bufp->fullBit(oldp+2913,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)); - bufp->fullQData(oldp+2914,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg),40); - bufp->fullBit(oldp+2916,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout)); - bufp->fullIData(oldp+2917,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter),26); - bufp->fullCData(oldp+2918,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill),7); - bufp->fullBit(oldp+2919,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy)); - bufp->fullBit(oldp+2920,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data)); - bufp->fullBit(oldp+2921,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)); - bufp->fullBit(oldp+2922,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID)); - bufp->fullBit(oldp+2923,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)); - bufp->fullCData(oldp+2924,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width),2); - bufp->fullCData(oldp+2925,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period),2); - bufp->fullBit(oldp+2926,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet)); - bufp->fullBit(oldp+2927,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid)); - bufp->fullCData(oldp+2928,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate),2); - bufp->fullBit(oldp+2929,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready)); - bufp->fullIData(oldp+2930,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data),32); - bufp->fullCData(oldp+2931,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count),4); - bufp->fullSData(oldp+2932,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg),16); - bufp->fullIData(oldp+2933,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w),32); - bufp->fullIData(oldp+2934,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w),32); - bufp->fullIData(oldp+2935,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w),32); - bufp->fullIData(oldp+2936,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg),32); - bufp->fullQData(oldp+2937,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w),64); - bufp->fullQData(oldp+2939,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w),64); - bufp->fullQData(oldp+2941,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w),64); - bufp->fullQData(oldp+2943,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg),64); - bufp->fullWData(oldp+2945,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w),128); - bufp->fullWData(oldp+2949,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w),128); - bufp->fullWData(oldp+2953,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w),128); - bufp->fullWData(oldp+2957,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg),128); - bufp->fullWData(oldp+2961,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d),256); - bufp->fullWData(oldp+2969,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d),256); - bufp->fullWData(oldp+2977,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d),256); - bufp->fullWData(oldp+2985,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg),256); - bufp->fullCData(oldp+2993,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts),5); - bufp->fullIData(oldp+2994,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg),32); - bufp->fullBit(oldp+2995,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit)); - bufp->fullBit(oldp+2996,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb)); - bufp->fullBit(oldp+2997,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first)); - bufp->fullBit(oldp+2998,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null)); - bufp->fullBit(oldp+2999,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last)); - bufp->fullWData(oldp+3000,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data),512); - bufp->fullWData(oldp+3016,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data),512); - bufp->fullQData(oldp+3032,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel),64); - bufp->fullQData(oldp+3034,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel),64); - bufp->fullCData(oldp+3036,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift),4); - bufp->fullCData(oldp+3037,((0xfU & (IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data))),4); - bufp->fullBit(oldp+3038,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full)); - bufp->fullBit(oldp+3039,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty)); - bufp->fullBit(oldp+3040,((1U & ((IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data) - >> 4U)))); - bufp->fullCData(oldp+3041,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill),6); - bufp->fullBit(oldp+3042,(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr)); - bufp->fullCData(oldp+3043,(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data),5); - bufp->fullCData(oldp+3044,(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data),5); - bufp->fullBit(oldp+3045,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_full)); - bufp->fullBit(oldp+3046,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty)); - bufp->fullCData(oldp+3047,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[0]),5); - bufp->fullCData(oldp+3048,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[1]),5); - bufp->fullCData(oldp+3049,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[2]),5); - bufp->fullCData(oldp+3050,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[3]),5); - bufp->fullCData(oldp+3051,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[4]),5); - bufp->fullCData(oldp+3052,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[5]),5); - bufp->fullCData(oldp+3053,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[6]),5); - bufp->fullCData(oldp+3054,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[7]),5); - bufp->fullCData(oldp+3055,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[8]),5); - bufp->fullCData(oldp+3056,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[9]),5); - bufp->fullCData(oldp+3057,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[10]),5); - bufp->fullCData(oldp+3058,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[11]),5); - bufp->fullCData(oldp+3059,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[12]),5); - bufp->fullCData(oldp+3060,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[13]),5); - bufp->fullCData(oldp+3061,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[14]),5); - bufp->fullCData(oldp+3062,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[15]),5); - bufp->fullCData(oldp+3063,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[16]),5); - bufp->fullCData(oldp+3064,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[17]),5); - bufp->fullCData(oldp+3065,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[18]),5); - bufp->fullCData(oldp+3066,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[19]),5); - bufp->fullCData(oldp+3067,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[20]),5); - bufp->fullCData(oldp+3068,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[21]),5); - bufp->fullCData(oldp+3069,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[22]),5); - bufp->fullCData(oldp+3070,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[23]),5); - bufp->fullCData(oldp+3071,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[24]),5); - bufp->fullCData(oldp+3072,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[25]),5); - bufp->fullCData(oldp+3073,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[26]),5); - bufp->fullCData(oldp+3074,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[27]),5); - bufp->fullCData(oldp+3075,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[28]),5); - bufp->fullCData(oldp+3076,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[29]),5); - bufp->fullCData(oldp+3077,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[30]),5); - bufp->fullCData(oldp+3078,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[31]),5); - bufp->fullCData(oldp+3079,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr),6); - bufp->fullCData(oldp+3080,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr),6); - bufp->fullBit(oldp+3081,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr)); - bufp->fullBit(oldp+3082,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd)); - bufp->fullSData(oldp+3083,(vlSelf->main__DOT__wb32_xbar__DOT__grant[0]),13); - bufp->fullBit(oldp+3084,(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)); - bufp->fullCData(oldp+3085,(vlSelf->main__DOT__wb32_xbar__DOT__w_mpending[0]),6); - bufp->fullBit(oldp+3086,(vlSelf->main__DOT__wb32_xbar__DOT__mfull)); - bufp->fullBit(oldp+3087,(vlSelf->main__DOT__wb32_xbar__DOT__mnearfull)); - bufp->fullBit(oldp+3088,(vlSelf->main__DOT__wb32_xbar__DOT__mempty)); - bufp->fullIData(oldp+3089,(vlSelf->main__DOT__wb32_xbar__DOT__iN),32); - bufp->fullCData(oldp+3090,(vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending),6); - bufp->fullSData(oldp+3091,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded),13); - bufp->fullBit(oldp+3092,((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))); - bufp->fullCData(oldp+3093,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr),8); - bufp->fullQData(oldp+3094,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data),45); - bufp->fullQData(oldp+3096,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data),45); - bufp->fullIData(oldp+3098,((0x3ffffffU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr))),26); - bufp->fullBit(oldp+3099,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb)); - bufp->fullWData(oldp+3100,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data),512); - bufp->fullCData(oldp+3116,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_shift),4); - bufp->fullBit(oldp+3117,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full)); - bufp->fullBit(oldp+3118,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty)); - bufp->fullCData(oldp+3119,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill),6); - bufp->fullCData(oldp+3120,((0xfU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr))),4); - bufp->fullCData(oldp+3121,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem - [(0x1fU & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr))]),4); - __Vtemp_hcfafa750__0[0U] = Vmain__ConstPool__CONST_hbd99daea_0[0U]; - __Vtemp_hcfafa750__0[1U] = Vmain__ConstPool__CONST_hbd99daea_0[1U]; - __Vtemp_hcfafa750__0[2U] = Vmain__ConstPool__CONST_hbd99daea_0[2U]; - __Vtemp_hcfafa750__0[3U] = Vmain__ConstPool__CONST_hbd99daea_0[3U]; - __Vtemp_hcfafa750__0[4U] = Vmain__ConstPool__CONST_hbd99daea_0[4U]; - __Vtemp_hcfafa750__0[5U] = Vmain__ConstPool__CONST_hbd99daea_0[5U]; - __Vtemp_hcfafa750__0[6U] = Vmain__ConstPool__CONST_hbd99daea_0[6U]; - __Vtemp_hcfafa750__0[7U] = Vmain__ConstPool__CONST_hbd99daea_0[7U]; - __Vtemp_hcfafa750__0[8U] = Vmain__ConstPool__CONST_hbd99daea_0[8U]; - __Vtemp_hcfafa750__0[9U] = Vmain__ConstPool__CONST_hbd99daea_0[9U]; - __Vtemp_hcfafa750__0[0xaU] = Vmain__ConstPool__CONST_hbd99daea_0[0xaU]; - __Vtemp_hcfafa750__0[0xbU] = Vmain__ConstPool__CONST_hbd99daea_0[0xbU]; - __Vtemp_hcfafa750__0[0xcU] = Vmain__ConstPool__CONST_hbd99daea_0[0xcU]; - __Vtemp_hcfafa750__0[0xdU] = Vmain__ConstPool__CONST_hbd99daea_0[0xdU]; - __Vtemp_hcfafa750__0[0xeU] = Vmain__ConstPool__CONST_hbd99daea_0[0xeU]; - __Vtemp_hcfafa750__0[0xfU] = (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata); - bufp->fullWData(oldp+3122,(__Vtemp_hcfafa750__0),512); - bufp->fullQData(oldp+3138,(((QData)((IData)((0xfU - & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel)))) - << 0x3cU)),64); - bufp->fullBit(oldp+3140,(((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - & (IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb)))); - bufp->fullCData(oldp+3141,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[0]),4); - bufp->fullCData(oldp+3142,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[1]),4); - bufp->fullCData(oldp+3143,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[2]),4); - bufp->fullCData(oldp+3144,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[3]),4); - bufp->fullCData(oldp+3145,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[4]),4); - bufp->fullCData(oldp+3146,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[5]),4); - bufp->fullCData(oldp+3147,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[6]),4); - bufp->fullCData(oldp+3148,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[7]),4); - bufp->fullCData(oldp+3149,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[8]),4); - bufp->fullCData(oldp+3150,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[9]),4); - bufp->fullCData(oldp+3151,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[10]),4); - bufp->fullCData(oldp+3152,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[11]),4); - bufp->fullCData(oldp+3153,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[12]),4); - bufp->fullCData(oldp+3154,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[13]),4); - bufp->fullCData(oldp+3155,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[14]),4); - bufp->fullCData(oldp+3156,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[15]),4); - bufp->fullCData(oldp+3157,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[16]),4); - bufp->fullCData(oldp+3158,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[17]),4); - bufp->fullCData(oldp+3159,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[18]),4); - bufp->fullCData(oldp+3160,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[19]),4); - bufp->fullCData(oldp+3161,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[20]),4); - bufp->fullCData(oldp+3162,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[21]),4); - bufp->fullCData(oldp+3163,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[22]),4); - bufp->fullCData(oldp+3164,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[23]),4); - bufp->fullCData(oldp+3165,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[24]),4); - bufp->fullCData(oldp+3166,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[25]),4); - bufp->fullCData(oldp+3167,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[26]),4); - bufp->fullCData(oldp+3168,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[27]),4); - bufp->fullCData(oldp+3169,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[28]),4); - bufp->fullCData(oldp+3170,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[29]),4); - bufp->fullCData(oldp+3171,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[30]),4); - bufp->fullCData(oldp+3172,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[31]),4); - bufp->fullCData(oldp+3173,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr),6); - bufp->fullCData(oldp+3174,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr),6); - bufp->fullBit(oldp+3175,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr)); - bufp->fullBit(oldp+3176,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd)); - bufp->fullCData(oldp+3177,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc),2); - bufp->fullCData(oldp+3178,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb),2); - bufp->fullCData(oldp+3179,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe),2); - bufp->fullQData(oldp+3180,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr),54); - bufp->fullQData(oldp+3182,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata),64); - bufp->fullCData(oldp+3184,(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel),8); - bufp->fullQData(oldp+3185,((((QData)((IData)(vlSelf->main__DOT__wbu_zip_idata)) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xfU])))),64); - bufp->fullCData(oldp+3187,(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err),2); - bufp->fullCData(oldp+3188,(vlSelf->main__DOT__wbu_xbar__DOT__request[0]),3); - bufp->fullCData(oldp+3189,(vlSelf->main__DOT__wbu_xbar__DOT__grant[0]),3); - bufp->fullBit(oldp+3190,(vlSelf->main__DOT__wbu_xbar__DOT__mgrant)); - bufp->fullCData(oldp+3191,(vlSelf->main__DOT__wbu_xbar__DOT__sgrant),2); - bufp->fullCData(oldp+3192,(vlSelf->main__DOT__wbu_xbar__DOT__w_mpending[0]),6); - bufp->fullBit(oldp+3193,(vlSelf->main__DOT__wbu_xbar__DOT__mfull)); - bufp->fullBit(oldp+3194,(vlSelf->main__DOT__wbu_xbar__DOT__mnearfull)); - bufp->fullBit(oldp+3195,(vlSelf->main__DOT__wbu_xbar__DOT__mempty)); - bufp->fullBit(oldp+3196,(vlSelf->main__DOT__wbu_xbar__DOT__m_stb)); - bufp->fullBit(oldp+3197,((1U & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> 0x24U))))); - bufp->fullIData(oldp+3198,(vlSelf->main__DOT__wbu_xbar__DOT__m_addr[0]),27); - bufp->fullIData(oldp+3199,(vlSelf->main__DOT__wbu_xbar__DOT__m_data[0]),32); - bufp->fullCData(oldp+3200,(vlSelf->main__DOT__wbu_xbar__DOT__m_sel[0]),4); - bufp->fullIData(oldp+3201,(vlSelf->main__DOT__wbu_xbar__DOT__s_data[0]),32); - bufp->fullIData(oldp+3202,(vlSelf->main__DOT__wbu_xbar__DOT__s_data[1]),32); - bufp->fullIData(oldp+3203,(vlSelf->main__DOT__wbu_xbar__DOT__s_data[2]),32); - bufp->fullIData(oldp+3204,(vlSelf->main__DOT__wbu_xbar__DOT__s_data[3]),32); - bufp->fullCData(oldp+3205,(vlSelf->main__DOT__wbu_xbar__DOT__s_err),4); - bufp->fullBit(oldp+3206,(vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb)); - bufp->fullIData(oldp+3207,(vlSelf->main__DOT__wbu_xbar__DOT__iN),32); - bufp->fullBit(oldp+3208,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)); - bufp->fullBit(oldp+3209,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available)); - bufp->fullCData(oldp+3210,(vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending),6); - bufp->fullBit(oldp+3211,((1U & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x3fU))))); - bufp->fullIData(oldp+3212,((0x7ffffffU & (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))),27); - bufp->fullIData(oldp+3213,((IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 4U))),32); - bufp->fullCData(oldp+3214,((0xfU & (IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data))),4); - bufp->fullCData(oldp+3215,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded),3); - bufp->fullBit(oldp+3216,((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))); - bufp->fullQData(oldp+3217,((((QData)((IData)((1U - & (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x3fU))))) - << 0x24U) | (0xfffffffffULL - & vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data))),37); - bufp->fullIData(oldp+3219,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr),27); - bufp->fullQData(oldp+3220,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data),37); - bufp->fullCData(oldp+3222,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest),2); - bufp->fullQData(oldp+3223,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data),64); - bufp->fullQData(oldp+3225,(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data),64); - bufp->fullQData(oldp+3227,(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data),64); - bufp->fullCData(oldp+3229,((((IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb) - << 3U) | (((IData)(vlSelf->main__DOT__wbwide_zip_stb) - << 2U) - | (((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - << 1U) - | (IData)(vlSelf->main__DOT__wbwide_i2cdma_stb))))),4); - bufp->fullCData(oldp+3230,((1U | (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we) - << 3U) | (4U - & (((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__cpu_we) - : - (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner))) - << 2U))))),4); - __Vtemp_h708d16f1__0[0U] = (IData)((((QData)((IData)(vlSelf->main__DOT__wbwide_i2cm_addr)) - << 0x16U) - | (QData)((IData)(vlSelf->main__DOT__wbwide_i2cdma_addr)))); - __Vtemp_h708d16f1__0[1U] = ((vlSelf->main__DOT__wbwide_zip_addr - << 0xcU) | (IData)( - ((((QData)((IData)(vlSelf->main__DOT__wbwide_i2cm_addr)) - << 0x16U) - | (QData)((IData)(vlSelf->main__DOT__wbwide_i2cdma_addr))) - >> 0x20U))); - __Vtemp_h708d16f1__0[2U] = ((vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr - << 2U) | (vlSelf->main__DOT__wbwide_zip_addr - >> 0x14U)); - bufp->fullWData(oldp+3231,(__Vtemp_h708d16f1__0),88); - __Vtemp_h95b27ed2__0[0U] = vlSelf->main__DOT__wbwide_i2cdma_data[0U]; - __Vtemp_h95b27ed2__0[1U] = vlSelf->main__DOT__wbwide_i2cdma_data[1U]; - __Vtemp_h95b27ed2__0[2U] = vlSelf->main__DOT__wbwide_i2cdma_data[2U]; - __Vtemp_h95b27ed2__0[3U] = vlSelf->main__DOT__wbwide_i2cdma_data[3U]; - __Vtemp_h95b27ed2__0[4U] = vlSelf->main__DOT__wbwide_i2cdma_data[4U]; - __Vtemp_h95b27ed2__0[5U] = vlSelf->main__DOT__wbwide_i2cdma_data[5U]; - __Vtemp_h95b27ed2__0[6U] = vlSelf->main__DOT__wbwide_i2cdma_data[6U]; - __Vtemp_h95b27ed2__0[7U] = vlSelf->main__DOT__wbwide_i2cdma_data[7U]; - __Vtemp_h95b27ed2__0[8U] = vlSelf->main__DOT__wbwide_i2cdma_data[8U]; - __Vtemp_h95b27ed2__0[9U] = vlSelf->main__DOT__wbwide_i2cdma_data[9U]; - __Vtemp_h95b27ed2__0[0xaU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xaU]; - __Vtemp_h95b27ed2__0[0xbU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xbU]; - __Vtemp_h95b27ed2__0[0xcU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xcU]; - __Vtemp_h95b27ed2__0[0xdU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xdU]; - __Vtemp_h95b27ed2__0[0xeU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xeU]; - __Vtemp_h95b27ed2__0[0xfU] = vlSelf->main__DOT__wbwide_i2cdma_data[0xfU]; - __Vtemp_h95b27ed2__0[0x10U] = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - __Vtemp_h95b27ed2__0[0x11U] = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - __Vtemp_h95b27ed2__0[0x12U] = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - __Vtemp_h95b27ed2__0[0x13U] = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - __Vtemp_h95b27ed2__0[0x14U] = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - __Vtemp_h95b27ed2__0[0x15U] = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - __Vtemp_h95b27ed2__0[0x16U] = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - __Vtemp_h95b27ed2__0[0x17U] = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - __Vtemp_h95b27ed2__0[0x18U] = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - __Vtemp_h95b27ed2__0[0x19U] = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - __Vtemp_h95b27ed2__0[0x1aU] = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - __Vtemp_h95b27ed2__0[0x1bU] = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - __Vtemp_h95b27ed2__0[0x1cU] = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - __Vtemp_h95b27ed2__0[0x1dU] = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - __Vtemp_h95b27ed2__0[0x1eU] = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - __Vtemp_h95b27ed2__0[0x1fU] = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - if (vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) { - __Vtemp_h95b27ed2__0[0x20U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - __Vtemp_h95b27ed2__0[0x21U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U]; - __Vtemp_h95b27ed2__0[0x22U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U]; - __Vtemp_h95b27ed2__0[0x23U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U]; - __Vtemp_h95b27ed2__0[0x24U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U]; - __Vtemp_h95b27ed2__0[0x25U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U]; - __Vtemp_h95b27ed2__0[0x26U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U]; - __Vtemp_h95b27ed2__0[0x27U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U]; - __Vtemp_h95b27ed2__0[0x28U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U]; - __Vtemp_h95b27ed2__0[0x29U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U]; - __Vtemp_h95b27ed2__0[0x2aU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU]; - __Vtemp_h95b27ed2__0[0x2bU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU]; - __Vtemp_h95b27ed2__0[0x2cU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU]; - __Vtemp_h95b27ed2__0[0x2dU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU]; - __Vtemp_h95b27ed2__0[0x2eU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU]; - __Vtemp_h95b27ed2__0[0x2fU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU]; - } else { - __Vtemp_h95b27ed2__0[0x20U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0U]; - __Vtemp_h95b27ed2__0[0x21U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[1U]; - __Vtemp_h95b27ed2__0[0x22U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[2U]; - __Vtemp_h95b27ed2__0[0x23U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[3U]; - __Vtemp_h95b27ed2__0[0x24U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[4U]; - __Vtemp_h95b27ed2__0[0x25U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[5U]; - __Vtemp_h95b27ed2__0[0x26U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[6U]; - __Vtemp_h95b27ed2__0[0x27U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[7U]; - __Vtemp_h95b27ed2__0[0x28U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[8U]; - __Vtemp_h95b27ed2__0[0x29U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[9U]; - __Vtemp_h95b27ed2__0[0x2aU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xaU]; - __Vtemp_h95b27ed2__0[0x2bU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xbU]; - __Vtemp_h95b27ed2__0[0x2cU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xcU]; - __Vtemp_h95b27ed2__0[0x2dU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xdU]; - __Vtemp_h95b27ed2__0[0x2eU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xeU]; - __Vtemp_h95b27ed2__0[0x2fU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xfU]; - } - __Vtemp_h95b27ed2__0[0x30U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0U]; - __Vtemp_h95b27ed2__0[0x31U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[1U]; - __Vtemp_h95b27ed2__0[0x32U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[2U]; - __Vtemp_h95b27ed2__0[0x33U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[3U]; - __Vtemp_h95b27ed2__0[0x34U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[4U]; - __Vtemp_h95b27ed2__0[0x35U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[5U]; - __Vtemp_h95b27ed2__0[0x36U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[6U]; - __Vtemp_h95b27ed2__0[0x37U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[7U]; - __Vtemp_h95b27ed2__0[0x38U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[8U]; - __Vtemp_h95b27ed2__0[0x39U] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[9U]; - __Vtemp_h95b27ed2__0[0x3aU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xaU]; - __Vtemp_h95b27ed2__0[0x3bU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xbU]; - __Vtemp_h95b27ed2__0[0x3cU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xcU]; - __Vtemp_h95b27ed2__0[0x3dU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xdU]; - __Vtemp_h95b27ed2__0[0x3eU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xeU]; - __Vtemp_h95b27ed2__0[0x3fU] = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xfU]; - bufp->fullWData(oldp+3234,(__Vtemp_h95b27ed2__0),2048); - __Vtemp_h7cab7483__0[0U] = (IData)(vlSelf->main__DOT__wbwide_i2cdma_sel); - __Vtemp_h7cab7483__0[1U] = (IData)((vlSelf->main__DOT__wbwide_i2cdma_sel - >> 0x20U)); - __Vtemp_h7cab7483__0[2U] = 0xffffffffU; - __Vtemp_h7cab7483__0[3U] = 0xffffffffU; - __Vtemp_h7cab7483__0[4U] = (IData)(((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel))); - __Vtemp_h7cab7483__0[5U] = (IData)((((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel)) - >> 0x20U)); - __Vtemp_h7cab7483__0[6U] = (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel); - __Vtemp_h7cab7483__0[7U] = (IData)((vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel - >> 0x20U)); - bufp->fullWData(oldp+3298,(__Vtemp_h7cab7483__0),256); - bufp->fullCData(oldp+3306,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - << 3U) | (IData)(vlSelf->__VdfgTmp_h503d14d1__0))),4); - bufp->fullCData(oldp+3307,(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack),4); - bufp->fullWData(oldp+3308,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata),2048); - bufp->fullCData(oldp+3372,(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr),4); - bufp->fullCData(oldp+3373,(vlSelf->main__DOT__wbwide_xbar__DOT__request[0]),4); - bufp->fullCData(oldp+3374,(vlSelf->main__DOT__wbwide_xbar__DOT__request[1]),4); - bufp->fullCData(oldp+3375,(vlSelf->main__DOT__wbwide_xbar__DOT__request[2]),4); - bufp->fullCData(oldp+3376,(vlSelf->main__DOT__wbwide_xbar__DOT__request[3]),4); - bufp->fullCData(oldp+3377,(vlSelf->main__DOT__wbwide_xbar__DOT__requested[0]),3); - bufp->fullCData(oldp+3378,(vlSelf->main__DOT__wbwide_xbar__DOT__requested[1]),3); - bufp->fullCData(oldp+3379,(vlSelf->main__DOT__wbwide_xbar__DOT__requested[2]),3); - bufp->fullCData(oldp+3380,(vlSelf->main__DOT__wbwide_xbar__DOT__requested[3]),3); - bufp->fullCData(oldp+3381,(vlSelf->main__DOT__wbwide_xbar__DOT__grant[0]),4); - bufp->fullCData(oldp+3382,(vlSelf->main__DOT__wbwide_xbar__DOT__grant[1]),4); - bufp->fullCData(oldp+3383,(vlSelf->main__DOT__wbwide_xbar__DOT__grant[2]),4); - bufp->fullCData(oldp+3384,(vlSelf->main__DOT__wbwide_xbar__DOT__grant[3]),4); - bufp->fullCData(oldp+3385,(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant),4); - bufp->fullCData(oldp+3386,(vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[0]),6); - bufp->fullCData(oldp+3387,(vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[1]),6); - bufp->fullCData(oldp+3388,(vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[2]),6); - bufp->fullCData(oldp+3389,(vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[3]),6); - bufp->fullCData(oldp+3390,(vlSelf->main__DOT__wbwide_xbar__DOT__mfull),4); - bufp->fullCData(oldp+3391,(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull),4); - bufp->fullCData(oldp+3392,(vlSelf->main__DOT__wbwide_xbar__DOT__mempty),4); - bufp->fullCData(oldp+3393,(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb),4); - bufp->fullCData(oldp+3394,((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid) - << 3U) | (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid) - << 2U) - | (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid) - << 1U) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid))))),4); - bufp->fullBit(oldp+3395,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)); - bufp->fullBit(oldp+3396,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel)); - bufp->fullBit(oldp+3397,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel)); - bufp->fullBit(oldp+3398,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel)); - bufp->fullCData(oldp+3399,(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending),6); - bufp->fullCData(oldp+3400,(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending),6); - bufp->fullCData(oldp+3401,(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending),6); - bufp->fullCData(oldp+3402,(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending),6); - bufp->fullBit(oldp+3403,((1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)))); - bufp->fullIData(oldp+3404,((0x3fffffU & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U])),22); - __Vtemp_h53a5df10__0[0U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U]; - __Vtemp_h53a5df10__0[1U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U]; - __Vtemp_h53a5df10__0[2U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U]; - __Vtemp_h53a5df10__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U]; - __Vtemp_h53a5df10__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U]; - __Vtemp_h53a5df10__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U]; - __Vtemp_h53a5df10__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U]; - __Vtemp_h53a5df10__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U]; - __Vtemp_h53a5df10__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_h53a5df10__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_h53a5df10__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU]; - __Vtemp_h53a5df10__0[0xbU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU]; - __Vtemp_h53a5df10__0[0xcU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU]; - __Vtemp_h53a5df10__0[0xdU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU]; - __Vtemp_h53a5df10__0[0xeU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U]; - __Vtemp_h53a5df10__0[0xfU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U]; - bufp->fullWData(oldp+3405,(__Vtemp_h53a5df10__0),512); - bufp->fullQData(oldp+3421,((((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U])))),64); - bufp->fullCData(oldp+3423,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded),4); - bufp->fullBit(oldp+3424,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))); - __Vtemp_hb52cb2db__0[0U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U]; - __Vtemp_hb52cb2db__0[1U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U]; - __Vtemp_hb52cb2db__0[2U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U]; - __Vtemp_hb52cb2db__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U]; - __Vtemp_hb52cb2db__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U]; - __Vtemp_hb52cb2db__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U]; - __Vtemp_hb52cb2db__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U]; - __Vtemp_hb52cb2db__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U]; - __Vtemp_hb52cb2db__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U]; - __Vtemp_hb52cb2db__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U]; - __Vtemp_hb52cb2db__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_hb52cb2db__0[0xbU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_hb52cb2db__0[0xcU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU]; - __Vtemp_hb52cb2db__0[0xdU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU]; - __Vtemp_hb52cb2db__0[0xeU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU]; - __Vtemp_hb52cb2db__0[0xfU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU]; - __Vtemp_hb52cb2db__0[0x10U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U]; - __Vtemp_hb52cb2db__0[0x11U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U]; - __Vtemp_hb52cb2db__0[0x12U] = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)); - bufp->fullWData(oldp+3425,(__Vtemp_hb52cb2db__0),577); - bufp->fullBit(oldp+3444,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)); - bufp->fullIData(oldp+3445,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr),22); - bufp->fullWData(oldp+3446,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data),577); - bufp->fullCData(oldp+3465,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest),3); - bufp->fullWData(oldp+3466,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data),599); - bufp->fullWData(oldp+3485,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data),599); - bufp->fullWData(oldp+3504,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data),599); - bufp->fullBit(oldp+3523,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)); - bufp->fullBit(oldp+3524,((1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)))); - bufp->fullIData(oldp+3525,((0x3fffffU & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U])),22); - __Vtemp_hebded4b4__0[0U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[2U]; - __Vtemp_hebded4b4__0[1U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[3U]; - __Vtemp_hebded4b4__0[2U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[4U]; - __Vtemp_hebded4b4__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[5U]; - __Vtemp_hebded4b4__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[6U]; - __Vtemp_hebded4b4__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[7U]; - __Vtemp_hebded4b4__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[8U]; - __Vtemp_hebded4b4__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[9U]; - __Vtemp_hebded4b4__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_hebded4b4__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_hebded4b4__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xcU]; 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- __Vtemp_h5b5f8605__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[5U]; - __Vtemp_h5b5f8605__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[6U]; - __Vtemp_h5b5f8605__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[7U]; - __Vtemp_h5b5f8605__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[8U]; - __Vtemp_h5b5f8605__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[9U]; - __Vtemp_h5b5f8605__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_h5b5f8605__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_h5b5f8605__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xcU]; - __Vtemp_h5b5f8605__0[0xbU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xdU]; - __Vtemp_h5b5f8605__0[0xcU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xeU]; - __Vtemp_h5b5f8605__0[0xdU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xfU]; - __Vtemp_h5b5f8605__0[0xeU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x10U]; - __Vtemp_h5b5f8605__0[0xfU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x11U]; - bufp->fullWData(oldp+3768,(__Vtemp_h5b5f8605__0),512); - bufp->fullQData(oldp+3784,((((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[1U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0U])))),64); - bufp->fullCData(oldp+3786,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__decoded),4); - bufp->fullBit(oldp+3787,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))); - __Vtemp_hfe9179b2__0[0U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0U]; - __Vtemp_hfe9179b2__0[1U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[1U]; - __Vtemp_hfe9179b2__0[2U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[2U]; - __Vtemp_hfe9179b2__0[3U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[3U]; - __Vtemp_hfe9179b2__0[4U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[4U]; - __Vtemp_hfe9179b2__0[5U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[5U]; - __Vtemp_hfe9179b2__0[6U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[6U]; - __Vtemp_hfe9179b2__0[7U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[7U]; - __Vtemp_hfe9179b2__0[8U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[8U]; - __Vtemp_hfe9179b2__0[9U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[9U]; - __Vtemp_hfe9179b2__0[0xaU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xaU]; - __Vtemp_hfe9179b2__0[0xbU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xbU]; - __Vtemp_hfe9179b2__0[0xcU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xcU]; - __Vtemp_hfe9179b2__0[0xdU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xdU]; - __Vtemp_hfe9179b2__0[0xeU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xeU]; - __Vtemp_hfe9179b2__0[0xfU] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xfU]; - __Vtemp_hfe9179b2__0[0x10U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x10U]; - __Vtemp_hfe9179b2__0[0x11U] = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x11U]; - __Vtemp_hfe9179b2__0[0x12U] = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)); - bufp->fullWData(oldp+3788,(__Vtemp_hfe9179b2__0),577); - bufp->fullBit(oldp+3807,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid)); - bufp->fullIData(oldp+3808,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_addr),22); - bufp->fullWData(oldp+3809,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data),577); - bufp->fullCData(oldp+3828,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest),3); - bufp->fullWData(oldp+3829,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data),599); - bufp->fullWData(oldp+3848,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data),599); - bufp->fullWData(oldp+3867,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data),599); - bufp->fullCData(oldp+3886,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex),2); - bufp->fullCData(oldp+3887,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex),2); - bufp->fullCData(oldp+3888,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex),2); - bufp->fullSData(oldp+3889,((((IData)(vlSelf->main__DOT__wb32_ddr3_phy_ack) - << 0xbU) | (((IData)(vlSelf->main__DOT__r_cfg_ack) - << 0xaU) - | (((IData)(vlSelf->main__DOT__r_wb32_sio_ack) - << 9U) - | (((IData)(vlSelf->main__DOT__wb32_sdcard_ack) - << 8U) - | (((IData)(vlSelf->main__DOT__wb32_fan_ack) - << 7U) - | (((IData)(vlSelf->main__DOT__wb32_emmc_ack) - << 6U) - | (((IData)(vlSelf->main__DOT__wb32_uart_ack) - << 5U) - | (((IData)(vlSelf->main__DOT__wb32_i2cdma_ack) - << 4U) - | (((IData)(vlSelf->main__DOT__wb32_i2cs_ack) - << 3U) - | (((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack) - << 2U) - | (((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack) - << 1U) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack))))))))))))),12); - __Vtemp_ha40692d2__0[0U] = vlSelf->main__DOT__emmcscopei__DOT__o_bus_data; - __Vtemp_ha40692d2__0[1U] = vlSelf->main__DOT__i2cscopei__DOT__o_bus_data; - __Vtemp_ha40692d2__0[2U] = vlSelf->main__DOT__sdioscopei__DOT__o_bus_data; - __Vtemp_ha40692d2__0[3U] = vlSelf->main__DOT__i2ci__DOT__bus_read_data; - __Vtemp_ha40692d2__0[4U] = vlSelf->main__DOT__wb32_i2cdma_idata; - __Vtemp_ha40692d2__0[5U] = vlSelf->main__DOT__wb32_uart_idata; - __Vtemp_ha40692d2__0[6U] = vlSelf->main__DOT__wb32_emmc_idata; - __Vtemp_ha40692d2__0[7U] = vlSelf->main__DOT__wb32_fan_idata; - __Vtemp_ha40692d2__0[8U] = vlSelf->main__DOT__wb32_sdcard_idata; - __Vtemp_ha40692d2__0[9U] = vlSelf->main__DOT__r_wb32_sio_data; - __Vtemp_ha40692d2__0[0xaU] = (IData)(((QData)((IData)(vlSelf->main__DOT__wb32_ddr3_phy_idata)) - << 0x20U)); - __Vtemp_ha40692d2__0[0xbU] = (IData)((((QData)((IData)(vlSelf->main__DOT__wb32_ddr3_phy_idata)) - << 0x20U) - >> 0x20U)); - bufp->fullWData(oldp+3890,(__Vtemp_ha40692d2__0),384); - bufp->fullIData(oldp+3902,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[0]),32); - bufp->fullIData(oldp+3903,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[1]),32); - bufp->fullIData(oldp+3904,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[2]),32); - bufp->fullIData(oldp+3905,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[3]),32); - bufp->fullIData(oldp+3906,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[4]),32); - bufp->fullIData(oldp+3907,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[5]),32); - bufp->fullIData(oldp+3908,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[6]),32); - bufp->fullIData(oldp+3909,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[7]),32); - bufp->fullIData(oldp+3910,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[8]),32); - bufp->fullIData(oldp+3911,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[9]),32); - bufp->fullIData(oldp+3912,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[10]),32); - bufp->fullIData(oldp+3913,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[11]),32); - bufp->fullIData(oldp+3914,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[12]),32); - bufp->fullIData(oldp+3915,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[13]),32); - bufp->fullIData(oldp+3916,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[14]),32); - bufp->fullIData(oldp+3917,(vlSelf->main__DOT__wb32_xbar__DOT__s_data[15]),32); - bufp->fullCData(oldp+3918,((((IData)(vlSelf->main__DOT__wbwide_ddr3_controller_stall) - << 2U) | (IData)(vlSelf->main__DOT__wbwide_wbdown_stall))),3); - bufp->fullCData(oldp+3919,((((vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U] & (0xeU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - << 2U) | (((IData)(vlSelf->main__DOT__wbwide_bkram_ack) - << 1U) - | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack)))),3); - __Vtemp_h8a06d21b__0[0U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U]; - __Vtemp_h8a06d21b__0[1U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U]; - __Vtemp_h8a06d21b__0[2U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U]; - __Vtemp_h8a06d21b__0[3U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U]; - __Vtemp_h8a06d21b__0[4U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U]; - __Vtemp_h8a06d21b__0[5U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U]; - __Vtemp_h8a06d21b__0[6U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U]; - __Vtemp_h8a06d21b__0[7U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U]; - __Vtemp_h8a06d21b__0[8U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U]; - __Vtemp_h8a06d21b__0[9U] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U]; - __Vtemp_h8a06d21b__0[0xaU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU]; - __Vtemp_h8a06d21b__0[0xbU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU]; - __Vtemp_h8a06d21b__0[0xcU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU]; - __Vtemp_h8a06d21b__0[0xdU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU]; - __Vtemp_h8a06d21b__0[0xeU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU]; - __Vtemp_h8a06d21b__0[0xfU] = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU]; - __Vtemp_h8a06d21b__0[0x10U] = vlSelf->main__DOT__wbwide_bkram_idata[0U]; - __Vtemp_h8a06d21b__0[0x11U] = vlSelf->main__DOT__wbwide_bkram_idata[1U]; - __Vtemp_h8a06d21b__0[0x12U] = vlSelf->main__DOT__wbwide_bkram_idata[2U]; - __Vtemp_h8a06d21b__0[0x13U] = vlSelf->main__DOT__wbwide_bkram_idata[3U]; - __Vtemp_h8a06d21b__0[0x14U] = vlSelf->main__DOT__wbwide_bkram_idata[4U]; - __Vtemp_h8a06d21b__0[0x15U] = vlSelf->main__DOT__wbwide_bkram_idata[5U]; - __Vtemp_h8a06d21b__0[0x16U] = vlSelf->main__DOT__wbwide_bkram_idata[6U]; - __Vtemp_h8a06d21b__0[0x17U] = vlSelf->main__DOT__wbwide_bkram_idata[7U]; - __Vtemp_h8a06d21b__0[0x18U] = vlSelf->main__DOT__wbwide_bkram_idata[8U]; - __Vtemp_h8a06d21b__0[0x19U] = vlSelf->main__DOT__wbwide_bkram_idata[9U]; - __Vtemp_h8a06d21b__0[0x1aU] = vlSelf->main__DOT__wbwide_bkram_idata[0xaU]; - __Vtemp_h8a06d21b__0[0x1bU] = vlSelf->main__DOT__wbwide_bkram_idata[0xbU]; - __Vtemp_h8a06d21b__0[0x1cU] = vlSelf->main__DOT__wbwide_bkram_idata[0xcU]; - __Vtemp_h8a06d21b__0[0x1dU] = vlSelf->main__DOT__wbwide_bkram_idata[0xdU]; - __Vtemp_h8a06d21b__0[0x1eU] = vlSelf->main__DOT__wbwide_bkram_idata[0xeU]; - __Vtemp_h8a06d21b__0[0x1fU] = vlSelf->main__DOT__wbwide_bkram_idata[0xfU]; - __Vtemp_h8a06d21b__0[0x20U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0U]; - __Vtemp_h8a06d21b__0[0x21U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][1U]; - __Vtemp_h8a06d21b__0[0x22U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][2U]; - __Vtemp_h8a06d21b__0[0x23U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][3U]; - __Vtemp_h8a06d21b__0[0x24U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][4U]; - __Vtemp_h8a06d21b__0[0x25U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][5U]; - __Vtemp_h8a06d21b__0[0x26U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][6U]; - __Vtemp_h8a06d21b__0[0x27U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][7U]; - __Vtemp_h8a06d21b__0[0x28U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][8U]; - __Vtemp_h8a06d21b__0[0x29U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][9U]; - __Vtemp_h8a06d21b__0[0x2aU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xaU]; - __Vtemp_h8a06d21b__0[0x2bU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xbU]; - __Vtemp_h8a06d21b__0[0x2cU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xcU]; - __Vtemp_h8a06d21b__0[0x2dU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xdU]; - __Vtemp_h8a06d21b__0[0x2eU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xeU]; - __Vtemp_h8a06d21b__0[0x2fU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xfU]; - bufp->fullWData(oldp+3920,(__Vtemp_h8a06d21b__0),1536); - bufp->fullWData(oldp+3968,(vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0]),512); - bufp->fullWData(oldp+3984,(vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1]),512); - bufp->fullWData(oldp+4000,(vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2]),512); - bufp->fullWData(oldp+4016,(vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3]),512); - bufp->fullBit(oldp+4032,((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U] >> 1U)))); - bufp->fullBit(oldp+4033,(vlSelf->main__DOT__wbwide_ddr3_controller_stall)); - bufp->fullBit(oldp+4034,((vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U] & (0xeU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))))); - __Vtemp_hc035b709__1[0U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0U]; - __Vtemp_hc035b709__1[1U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][1U]; - __Vtemp_hc035b709__1[2U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][2U]; - __Vtemp_hc035b709__1[3U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][3U]; - __Vtemp_hc035b709__1[4U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][4U]; - __Vtemp_hc035b709__1[5U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][5U]; - __Vtemp_hc035b709__1[6U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][6U]; - __Vtemp_hc035b709__1[7U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][7U]; - __Vtemp_hc035b709__1[8U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][8U]; - __Vtemp_hc035b709__1[9U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][9U]; - __Vtemp_hc035b709__1[0xaU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xaU]; - __Vtemp_hc035b709__1[0xbU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xbU]; - __Vtemp_hc035b709__1[0xcU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xcU]; - __Vtemp_hc035b709__1[0xdU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xdU]; - __Vtemp_hc035b709__1[0xeU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xeU]; - __Vtemp_hc035b709__1[0xfU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xfU]; - bufp->fullWData(oldp+4035,(__Vtemp_hc035b709__1),512); - bufp->fullBit(oldp+4051,(vlSelf->main__DOT__wb32_ddr3_phy_stall)); - bufp->fullBit(oldp+4052,(vlSelf->main__DOT__wb32_ddr3_phy_ack)); - bufp->fullIData(oldp+4053,(vlSelf->main__DOT__wb32_ddr3_phy_idata),32); - bufp->fullIData(oldp+4054,(vlSelf->main__DOT__ddr3_controller_inst__DOT__index),32); - bufp->fullCData(oldp+4055,(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address),5); - bufp->fullIData(oldp+4056,(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction),28); - bufp->fullSData(oldp+4057,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter),16); - bufp->fullBit(oldp+4058,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero)); - bufp->fullBit(oldp+4059,(vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done)); - bufp->fullBit(oldp+4060,(vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter)); - bufp->fullBit(oldp+4061,((2U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate)))); - bufp->fullBit(oldp+4062,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update)); - bufp->fullCData(oldp+4063,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q),8); - bufp->fullSData(oldp+4064,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[0]),14); - bufp->fullSData(oldp+4065,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[1]),14); - bufp->fullSData(oldp+4066,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[2]),14); - bufp->fullSData(oldp+4067,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[3]),14); - bufp->fullSData(oldp+4068,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[4]),14); - bufp->fullSData(oldp+4069,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[5]),14); - bufp->fullSData(oldp+4070,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[6]),14); - bufp->fullSData(oldp+4071,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[7]),14); - bufp->fullBit(oldp+4072,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending)); - bufp->fullBit(oldp+4073,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_aux)); - bufp->fullBit(oldp+4074,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we)); - bufp->fullWData(oldp+4075,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data),512); - bufp->fullQData(oldp+4091,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_dm),64); - bufp->fullSData(oldp+4093,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_col),10); - bufp->fullCData(oldp+4094,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank),3); - bufp->fullSData(oldp+4095,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row),14); - bufp->fullCData(oldp+4096,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank),3); - bufp->fullSData(oldp+4097,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row),14); - bufp->fullBit(oldp+4098,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending)); - bufp->fullBit(oldp+4099,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux)); - bufp->fullBit(oldp+4100,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we)); - bufp->fullQData(oldp+4101,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned),64); - bufp->fullQData(oldp+4103,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0]),64); - bufp->fullQData(oldp+4105,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[1]),64); - bufp->fullWData(oldp+4107,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned),512); - bufp->fullWData(oldp+4123,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0]),512); - bufp->fullWData(oldp+4139,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1]),512); - bufp->fullQData(oldp+4155,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[0]),64); - bufp->fullQData(oldp+4157,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[1]),64); - bufp->fullQData(oldp+4159,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[2]),64); - bufp->fullQData(oldp+4161,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[3]),64); - bufp->fullQData(oldp+4163,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[4]),64); - bufp->fullQData(oldp+4165,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[5]),64); - bufp->fullQData(oldp+4167,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[6]),64); - bufp->fullQData(oldp+4169,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[7]),64); - bufp->fullCData(oldp+4171,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[0]),8); - bufp->fullCData(oldp+4172,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[1]),8); - bufp->fullCData(oldp+4173,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[2]),8); - bufp->fullCData(oldp+4174,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[3]),8); - bufp->fullCData(oldp+4175,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[4]),8); - bufp->fullCData(oldp+4176,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[5]),8); - bufp->fullCData(oldp+4177,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[6]),8); - bufp->fullCData(oldp+4178,(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[7]),8); - bufp->fullSData(oldp+4179,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col),10); - bufp->fullCData(oldp+4180,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank),3); - bufp->fullSData(oldp+4181,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row),14); - bufp->fullCData(oldp+4182,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[0]),4); - bufp->fullCData(oldp+4183,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[1]),4); - bufp->fullCData(oldp+4184,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[2]),4); - bufp->fullCData(oldp+4185,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[3]),4); - bufp->fullCData(oldp+4186,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[4]),4); - bufp->fullCData(oldp+4187,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[5]),4); - bufp->fullCData(oldp+4188,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[6]),4); - bufp->fullCData(oldp+4189,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[7]),4); - bufp->fullCData(oldp+4190,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[0]),4); - bufp->fullCData(oldp+4191,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[1]),4); - bufp->fullCData(oldp+4192,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[2]),4); - bufp->fullCData(oldp+4193,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[3]),4); - bufp->fullCData(oldp+4194,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[4]),4); - bufp->fullCData(oldp+4195,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[5]),4); - bufp->fullCData(oldp+4196,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[6]),4); - bufp->fullCData(oldp+4197,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[7]),4); - bufp->fullCData(oldp+4198,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[0]),4); - bufp->fullCData(oldp+4199,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[1]),4); - bufp->fullCData(oldp+4200,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[2]),4); - bufp->fullCData(oldp+4201,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[3]),4); - bufp->fullCData(oldp+4202,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[4]),4); - bufp->fullCData(oldp+4203,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[5]),4); - bufp->fullCData(oldp+4204,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[6]),4); - bufp->fullCData(oldp+4205,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[7]),4); - bufp->fullCData(oldp+4206,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[0]),4); - bufp->fullCData(oldp+4207,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[1]),4); - bufp->fullCData(oldp+4208,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[2]),4); - bufp->fullCData(oldp+4209,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[3]),4); - bufp->fullCData(oldp+4210,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[4]),4); - bufp->fullCData(oldp+4211,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[5]),4); - bufp->fullCData(oldp+4212,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[6]),4); - bufp->fullCData(oldp+4213,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[7]),4); - bufp->fullBit(oldp+4214,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt_q)); - bufp->fullBit(oldp+4215,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q)); - bufp->fullCData(oldp+4216,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_q),2); - bufp->fullBit(oldp+4217,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d)); - bufp->fullCData(oldp+4218,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs),3); - bufp->fullCData(oldp+4219,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_val),3); - bufp->fullBit(oldp+4220,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_q)); - bufp->fullBit(oldp+4221,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d)); - bufp->fullCData(oldp+4222,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq),4); - bufp->fullCData(oldp+4223,(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate),5); - bufp->fullQData(oldp+4224,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store),40); - bufp->fullCData(oldp+4226,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat),4); - bufp->fullCData(oldp+4227,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index),6); - bufp->fullCData(oldp+4228,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored),6); - bufp->fullCData(oldp+4229,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index),6); - bufp->fullCData(oldp+4230,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig),6); - bufp->fullCData(oldp+4231,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index),6); - bufp->fullCData(oldp+4232,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value),6); - bufp->fullBit(oldp+4233,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat)); - bufp->fullCData(oldp+4234,(vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay),2); - bufp->fullCData(oldp+4235,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data),4); - bufp->fullCData(oldp+4236,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback),5); - bufp->fullBit(oldp+4237,(vlSelf->main__DOT__ddr3_controller_inst__DOT__initial_dqs)); - bufp->fullCData(oldp+4238,(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane),3); - bufp->fullCData(oldp+4239,(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8),6); - bufp->fullSData(oldp+4240,(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement),16); - bufp->fullCData(oldp+4241,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max),4); - bufp->fullCData(oldp+4242,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[0]),4); - bufp->fullCData(oldp+4243,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[1]),4); - bufp->fullCData(oldp+4244,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[2]),4); - bufp->fullCData(oldp+4245,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[3]),4); - bufp->fullCData(oldp+4246,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[4]),4); - bufp->fullCData(oldp+4247,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[5]),4); - bufp->fullCData(oldp+4248,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[6]),4); - bufp->fullCData(oldp+4249,(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[7]),4); - bufp->fullCData(oldp+4250,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[0]),2); - bufp->fullCData(oldp+4251,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[1]),2); - bufp->fullCData(oldp+4252,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[2]),2); - bufp->fullCData(oldp+4253,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[3]),2); - bufp->fullCData(oldp+4254,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[4]),2); - bufp->fullCData(oldp+4255,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[0]),2); - bufp->fullCData(oldp+4256,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[1]),2); - bufp->fullCData(oldp+4257,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[2]),2); - bufp->fullCData(oldp+4258,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[3]),2); - bufp->fullCData(oldp+4259,(vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4]),2); - bufp->fullBit(oldp+4260,(vlSelf->main__DOT__ddr3_controller_inst__DOT__index_read_pipe)); - bufp->fullBit(oldp+4261,(vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data)); - bufp->fullSData(oldp+4262,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[0]),16); - bufp->fullSData(oldp+4263,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[1]),16); - bufp->fullWData(oldp+4264,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0]),512); - bufp->fullWData(oldp+4280,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1]),512); - bufp->fullCData(oldp+4296,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0]),2); - bufp->fullCData(oldp+4297,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[1]),2); - bufp->fullCData(oldp+4298,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[2]),2); - bufp->fullCData(oldp+4299,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[3]),2); - bufp->fullCData(oldp+4300,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[4]),2); - bufp->fullCData(oldp+4301,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[5]),2); - bufp->fullCData(oldp+4302,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[6]),2); - bufp->fullCData(oldp+4303,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[7]),2); - bufp->fullCData(oldp+4304,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[8]),2); - bufp->fullCData(oldp+4305,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[9]),2); - bufp->fullCData(oldp+4306,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[10]),2); - bufp->fullCData(oldp+4307,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[11]),2); - bufp->fullCData(oldp+4308,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[12]),2); - bufp->fullCData(oldp+4309,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[13]),2); - bufp->fullCData(oldp+4310,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[14]),2); - bufp->fullCData(oldp+4311,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[15]),2); - bufp->fullBit(oldp+4312,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_stb)); - bufp->fullBit(oldp+4313,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux)); - bufp->fullBit(oldp+4314,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we)); - bufp->fullSData(oldp+4315,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col),10); - bufp->fullWData(oldp+4316,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data),512); - bufp->fullBit(oldp+4332,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt)); - bufp->fullBit(oldp+4333,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs)); - bufp->fullBit(oldp+4334,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dq)); - bufp->fullBit(oldp+4335,(vlSelf->main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback)); - bufp->fullWData(oldp+4336,(vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store),512); - bufp->fullWData(oldp+4352,(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern),128); - bufp->fullCData(oldp+4356,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[0]),7); - bufp->fullCData(oldp+4357,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[1]),7); - bufp->fullCData(oldp+4358,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[2]),7); - bufp->fullCData(oldp+4359,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[3]),7); - bufp->fullCData(oldp+4360,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[4]),7); - bufp->fullCData(oldp+4361,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[5]),7); - bufp->fullCData(oldp+4362,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[6]),7); - bufp->fullCData(oldp+4363,(vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[7]),7); - bufp->fullCData(oldp+4364,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[0]),5); - bufp->fullCData(oldp+4365,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[1]),5); - bufp->fullCData(oldp+4366,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[2]),5); - bufp->fullCData(oldp+4367,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[3]),5); - bufp->fullCData(oldp+4368,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[4]),5); - bufp->fullCData(oldp+4369,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[5]),5); - bufp->fullCData(oldp+4370,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[6]),5); - bufp->fullCData(oldp+4371,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[7]),5); - bufp->fullCData(oldp+4372,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[0]),5); - bufp->fullCData(oldp+4373,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[1]),5); - bufp->fullCData(oldp+4374,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[2]),5); - bufp->fullCData(oldp+4375,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[3]),5); - bufp->fullCData(oldp+4376,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[4]),5); - bufp->fullCData(oldp+4377,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[5]),5); - bufp->fullCData(oldp+4378,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[6]),5); - bufp->fullCData(oldp+4379,(vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[7]),5); - bufp->fullCData(oldp+4380,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[0]),5); - bufp->fullCData(oldp+4381,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[1]),5); - bufp->fullCData(oldp+4382,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[2]),5); - bufp->fullCData(oldp+4383,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[3]),5); - bufp->fullCData(oldp+4384,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[4]),5); - bufp->fullCData(oldp+4385,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[5]),5); - bufp->fullCData(oldp+4386,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[6]),5); - bufp->fullCData(oldp+4387,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[7]),5); - bufp->fullCData(oldp+4388,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev),5); - bufp->fullCData(oldp+4389,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[0]),5); - bufp->fullCData(oldp+4390,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[1]),5); - bufp->fullCData(oldp+4391,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[2]),5); - bufp->fullCData(oldp+4392,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[3]),5); - bufp->fullCData(oldp+4393,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[4]),5); - bufp->fullCData(oldp+4394,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[5]),5); - bufp->fullCData(oldp+4395,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[6]),5); - bufp->fullCData(oldp+4396,(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[7]),5); - bufp->fullBit(oldp+4397,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_stb)); - bufp->fullBit(oldp+4398,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_update)); - bufp->fullBit(oldp+4399,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)); - bufp->fullIData(oldp+4400,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr),32); - bufp->fullIData(oldp+4401,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_data),32); - bufp->fullCData(oldp+4402,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_sel),4); - bufp->fullCData(oldp+4403,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_cntvaluein),5); - bufp->fullCData(oldp+4404,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_cntvaluein),5); - bufp->fullCData(oldp+4405,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_cntvaluein),5); - bufp->fullCData(oldp+4406,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_cntvaluein),5); - bufp->fullCData(oldp+4407,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_ld),8); - bufp->fullCData(oldp+4408,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_ld),8); - bufp->fullCData(oldp+4409,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_ld),8); - bufp->fullCData(oldp+4410,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_ld),8); - bufp->fullCData(oldp+4411,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane),3); - bufp->fullIData(oldp+4412,(vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result),32); - bufp->fullSData(oldp+4413,(((IData)(vlSelf->main__DOT__wb32_ddr3_phy_stall) - << 0xbU)),12); - bufp->fullBit(oldp+4414,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->fullBit(oldp+4415,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->fullBit(oldp+4416,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->fullBit(oldp+4417,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->fullBit(oldp+4418,(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - bufp->fullBit(oldp+4419,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc)))); - bufp->fullBit(oldp+4420,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)))); - bufp->fullBit(oldp+4421,((1U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)))); - bufp->fullIData(oldp+4422,((0x3fffffU & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U])),22); - __Vtemp_hf82de6ac__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0U]; - __Vtemp_hf82de6ac__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[1U]; - __Vtemp_hf82de6ac__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[2U]; - __Vtemp_hf82de6ac__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[3U]; - __Vtemp_hf82de6ac__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[4U]; - __Vtemp_hf82de6ac__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[5U]; - __Vtemp_hf82de6ac__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[6U]; - __Vtemp_hf82de6ac__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[7U]; - __Vtemp_hf82de6ac__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[8U]; - __Vtemp_hf82de6ac__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[9U]; - __Vtemp_hf82de6ac__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xaU]; - __Vtemp_hf82de6ac__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xbU]; - __Vtemp_hf82de6ac__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xcU]; - __Vtemp_hf82de6ac__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xdU]; - __Vtemp_hf82de6ac__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xeU]; - __Vtemp_hf82de6ac__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xfU]; - bufp->fullWData(oldp+4423,(__Vtemp_hf82de6ac__0),512); - bufp->fullQData(oldp+4439,((((QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[0U])))),64); - bufp->fullBit(oldp+4441,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err)); - bufp->fullBit(oldp+4442,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 1U)))); - bufp->fullBit(oldp+4443,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 1U)))); - bufp->fullBit(oldp+4444,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe) - >> 1U)))); - bufp->fullIData(oldp+4445,((0x3fffffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - << 0xaU) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - >> 0x16U)))),22); - __Vtemp_hf74e670c__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x10U]; - __Vtemp_hf74e670c__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x11U]; - __Vtemp_hf74e670c__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x12U]; - __Vtemp_hf74e670c__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x13U]; - __Vtemp_hf74e670c__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x14U]; - __Vtemp_hf74e670c__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x15U]; - __Vtemp_hf74e670c__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x16U]; - __Vtemp_hf74e670c__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x17U]; - __Vtemp_hf74e670c__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x18U]; - __Vtemp_hf74e670c__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x19U]; - __Vtemp_hf74e670c__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1aU]; - __Vtemp_hf74e670c__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1bU]; - __Vtemp_hf74e670c__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1cU]; - __Vtemp_hf74e670c__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1dU]; - __Vtemp_hf74e670c__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1eU]; - __Vtemp_hf74e670c__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1fU]; - bufp->fullWData(oldp+4446,(__Vtemp_hf74e670c__0),512); - bufp->fullQData(oldp+4462,((((QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[3U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[2U])))),64); - bufp->fullBit(oldp+4464,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 2U)))); - bufp->fullBit(oldp+4465,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 2U)))); - bufp->fullBit(oldp+4466,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe) - >> 2U)))); - bufp->fullIData(oldp+4467,((0x3fffffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0x14U) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0xcU)))),22); - __Vtemp_h21e563ec__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x20U]; - __Vtemp_h21e563ec__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x21U]; - __Vtemp_h21e563ec__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x22U]; - __Vtemp_h21e563ec__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x23U]; - __Vtemp_h21e563ec__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x24U]; - __Vtemp_h21e563ec__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x25U]; - __Vtemp_h21e563ec__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x26U]; - __Vtemp_h21e563ec__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x27U]; - __Vtemp_h21e563ec__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x28U]; - __Vtemp_h21e563ec__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x29U]; - __Vtemp_h21e563ec__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2aU]; - __Vtemp_h21e563ec__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2bU]; - __Vtemp_h21e563ec__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2cU]; - __Vtemp_h21e563ec__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2dU]; - __Vtemp_h21e563ec__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2eU]; - __Vtemp_h21e563ec__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2fU]; - bufp->fullWData(oldp+4468,(__Vtemp_h21e563ec__0),512); - bufp->fullQData(oldp+4484,((((QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[5U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[4U])))),64); - bufp->fullBit(oldp+4486,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)); - bufp->fullBit(oldp+4487,(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - bufp->fullBit(oldp+4488,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 9U)))); - bufp->fullBit(oldp+4489,((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) & (0U - == - (0x700U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))))); - bufp->fullBit(oldp+4490,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 9U)))); - bufp->fullIData(oldp+4491,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U]),32); - bufp->fullCData(oldp+4492,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x24U)))),4); - bufp->fullBit(oldp+4493,((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) & (0x100U - == - (0x700U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))))); - bufp->fullBit(oldp+4494,(vlSelf->main__DOT__wb32_sirefclk_stb)); - bufp->fullBit(oldp+4495,(vlSelf->main__DOT__wb32_spio_stb)); - bufp->fullBit(oldp+4496,((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) & (0x400U - == - (0x700U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))))); - bufp->fullBit(oldp+4497,((1U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)))); - bufp->fullBit(oldp+4498,((1U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb)))); - bufp->fullBit(oldp+4499,((1U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)))); - bufp->fullCData(oldp+4500,((0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])),8); - bufp->fullIData(oldp+4501,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0U]),32); - bufp->fullCData(oldp+4502,((0xfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))),4); - bufp->fullBit(oldp+4503,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 1U)))); - bufp->fullBit(oldp+4504,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 1U)))); - bufp->fullBit(oldp+4505,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 1U)))); - bufp->fullCData(oldp+4506,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U))),8); - bufp->fullIData(oldp+4507,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[1U]),32); - bufp->fullCData(oldp+4508,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 4U)))),4); - bufp->fullBit(oldp+4509,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 2U)))); - bufp->fullBit(oldp+4510,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 2U)))); - bufp->fullBit(oldp+4511,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 2U)))); - bufp->fullCData(oldp+4512,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U))),8); - bufp->fullIData(oldp+4513,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[2U]),32); - bufp->fullCData(oldp+4514,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 8U)))),4); - bufp->fullBit(oldp+4515,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 3U)))); - bufp->fullBit(oldp+4516,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 3U)))); - bufp->fullBit(oldp+4517,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 3U)))); - bufp->fullCData(oldp+4518,((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x18U)),8); - bufp->fullIData(oldp+4519,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U]),32); - bufp->fullCData(oldp+4520,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xcU)))),4); - bufp->fullBit(oldp+4521,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 4U)))); - bufp->fullBit(oldp+4522,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 4U)))); - bufp->fullBit(oldp+4523,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 4U)))); - bufp->fullCData(oldp+4524,((0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])),8); - bufp->fullIData(oldp+4525,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[4U]),32); - bufp->fullCData(oldp+4526,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x10U)))),4); - bufp->fullBit(oldp+4527,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 5U)))); - bufp->fullBit(oldp+4528,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 5U)))); - bufp->fullBit(oldp+4529,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 5U)))); - bufp->fullCData(oldp+4530,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 8U))),8); - bufp->fullIData(oldp+4531,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[5U]),32); - bufp->fullCData(oldp+4532,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x14U)))),4); - bufp->fullBit(oldp+4533,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 6U)))); - bufp->fullBit(oldp+4534,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U)))); - bufp->fullBit(oldp+4535,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U)))); - bufp->fullCData(oldp+4536,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U))),8); - bufp->fullIData(oldp+4537,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]),32); - bufp->fullCData(oldp+4538,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U)))),4); - bufp->fullBit(oldp+4539,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 7U)))); - bufp->fullBit(oldp+4540,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 7U)))); - bufp->fullBit(oldp+4541,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 7U)))); - bufp->fullCData(oldp+4542,((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U)),8); - bufp->fullIData(oldp+4543,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U]),32); - bufp->fullCData(oldp+4544,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1cU)))),4); - bufp->fullBit(oldp+4545,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 8U)))); - bufp->fullBit(oldp+4546,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U)))); - bufp->fullBit(oldp+4547,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U)))); - bufp->fullCData(oldp+4548,((0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])),8); - bufp->fullIData(oldp+4549,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]),32); - bufp->fullCData(oldp+4550,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U)))),4); - bufp->fullBit(oldp+4551,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U)))); - bufp->fullCData(oldp+4552,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - >> 8U))),8); - bufp->fullBit(oldp+4553,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 0xaU)))); - bufp->fullBit(oldp+4554,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 0xaU)))); - bufp->fullBit(oldp+4555,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 0xaU)))); - bufp->fullCData(oldp+4556,((0xffU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - >> 0x10U))),8); - bufp->fullIData(oldp+4557,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0xaU]),32); - bufp->fullCData(oldp+4558,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x28U)))),4); - bufp->fullBit(oldp+4559,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 0xbU)))); - bufp->fullBit(oldp+4560,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 0xbU)))); - bufp->fullBit(oldp+4561,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 0xbU)))); - bufp->fullCData(oldp+4562,((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - >> 0x18U)),8); - bufp->fullIData(oldp+4563,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0xbU]),32); - bufp->fullCData(oldp+4564,((0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x2cU)))),4); - bufp->fullSData(oldp+4565,((0x3fffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - << 0xaU) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - >> 0x16U)))),14); - bufp->fullCData(oldp+4566,((3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 8U))),2); - bufp->fullIData(oldp+4567,((0x1fffffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0x14U) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0xcU)))),21); - bufp->fullIData(oldp+4568,((0x7fU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - >> 0x18U))),32); - bufp->fullIData(oldp+4569,((0x1fffffU & ((IData)(5U) - + ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0x14U) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0xcU))))),21); - bufp->fullBit(oldp+4570,((1U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]))); - bufp->fullBit(oldp+4571,((1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe))))); - bufp->fullBit(oldp+4572,(vlSelf->main__DOT__emmcscopei__DOT__read_from_data)); - bufp->fullBit(oldp+4573,(vlSelf->main__DOT__emmcscopei__DOT__write_to_control)); - bufp->fullCData(oldp+4574,((3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x18U))),2); - bufp->fullBit(oldp+4575,(vlSelf->main__DOT__i2ci__DOT__next_valid)); - bufp->fullCData(oldp+4576,(vlSelf->main__DOT__i2ci__DOT__next_insn),8); - bufp->fullBit(oldp+4577,((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 3U) & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 3U)))))); - bufp->fullBit(oldp+4578,(vlSelf->main__DOT__i2ci__DOT__bus_write)); - bufp->fullBit(oldp+4579,(vlSelf->main__DOT__i2ci__DOT__bus_override)); - bufp->fullBit(oldp+4580,(vlSelf->main__DOT__i2ci__DOT__bus_manual)); - bufp->fullBit(oldp+4581,(vlSelf->main__DOT__i2ci__DOT__bus_jump)); - bufp->fullBit(oldp+4582,((1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U)))); - bufp->fullBit(oldp+4583,((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 1U)))); - bufp->fullBit(oldp+4584,(vlSelf->main__DOT__i2cscopei__DOT__read_from_data)); - bufp->fullBit(oldp+4585,(vlSelf->main__DOT__i2cscopei__DOT__write_to_control)); - bufp->fullBit(oldp+4586,((1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U)))); - bufp->fullBit(oldp+4587,((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 2U)))); - bufp->fullBit(oldp+4588,(vlSelf->main__DOT__sdioscopei__DOT__read_from_data)); - bufp->fullBit(oldp+4589,(vlSelf->main__DOT__sdioscopei__DOT__write_to_control)); - bufp->fullCData(oldp+4590,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn),5); - bufp->fullBit(oldp+4591,(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_int)); - bufp->fullCData(oldp+4592,((7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U))),3); - bufp->fullBit(oldp+4593,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)); - bufp->fullBit(oldp+4594,(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb)); - bufp->fullCData(oldp+4595,((7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U))),3); - bufp->fullBit(oldp+4596,(vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb)); - bufp->fullCData(oldp+4597,((3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U))),2); - bufp->fullBit(oldp+4598,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid)); - bufp->fullCData(oldp+4599,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn),8); - bufp->fullBit(oldp+4600,(((IData)(vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb) - & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 7U))))); - bufp->fullBit(oldp+4601,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write)); - bufp->fullBit(oldp+4602,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override)); - bufp->fullBit(oldp+4603,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual)); - bufp->fullBit(oldp+4604,(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump)); - bufp->fullCData(oldp+4605,((3U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])),2); - bufp->fullIData(oldp+4606,(vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr),32); - bufp->fullIData(oldp+4607,(vlSelf->main__DOT__u_i2cdma__DOT__next_memlen),32); - bufp->fullCData(oldp+4608,((7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])),3); - bufp->fullBit(oldp+4609,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)); - bufp->fullBit(oldp+4610,(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb)); - bufp->fullCData(oldp+4611,((0xfU & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U])),4); - bufp->fullCData(oldp+4612,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__i_subaddr),4); - bufp->fullIData(oldp+4613,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm),32); - bufp->fullSData(oldp+4614,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc),12); - bufp->fullSData(oldp+4615,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb),12); - bufp->fullSData(oldp+4616,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe),12); - bufp->fullWData(oldp+4617,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr),96); - bufp->fullWData(oldp+4620,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata),384); - bufp->fullQData(oldp+4632,(vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel),48); - bufp->fullSData(oldp+4634,(vlSelf->main__DOT__wb32_xbar__DOT__request[0]),13); - bufp->fullSData(oldp+4635,(vlSelf->main__DOT__wb32_xbar__DOT__sgrant),12); - bufp->fullCData(oldp+4636,(vlSelf->main__DOT__wb32_xbar__DOT__mindex[0]),4); - bufp->fullBit(oldp+4637,(vlSelf->main__DOT__wb32_xbar__DOT__m_stb)); - bufp->fullBit(oldp+4638,((1U & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> 0x24U))))); - bufp->fullCData(oldp+4639,(vlSelf->main__DOT__wb32_xbar__DOT__m_addr[0]),8); - bufp->fullIData(oldp+4640,(vlSelf->main__DOT__wb32_xbar__DOT__m_data[0]),32); - bufp->fullCData(oldp+4641,(vlSelf->main__DOT__wb32_xbar__DOT__m_sel[0]),4); - bufp->fullBit(oldp+4642,(vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb)); - bufp->fullSData(oldp+4643,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),13); - bufp->fullBit(oldp+4644,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)); - bufp->fullBit(oldp+4645,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available)); - bufp->fullCData(oldp+4646,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),4); - bufp->fullBit(oldp+4647,((1U & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x2cU))))); - bufp->fullCData(oldp+4648,((0xffU & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))),8); - bufp->fullIData(oldp+4649,((IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 4U))),32); - bufp->fullCData(oldp+4650,((0xfU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data))),4); - bufp->fullQData(oldp+4651,((((QData)((IData)((1U - & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x2cU))))) - << 0x24U) | (0xfffffffffULL - & vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data))),37); - bufp->fullQData(oldp+4653,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data),37); - bufp->fullSData(oldp+4655,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest),12); - bufp->fullQData(oldp+4656,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data),45); - bufp->fullCData(oldp+4658,(vlSelf->main__DOT__wbu_xbar__DOT__mindex[0]),2); - bufp->fullCData(oldp+4659,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),3); - bufp->fullCData(oldp+4660,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->fullCData(oldp+4661,(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc),4); - bufp->fullCData(oldp+4662,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc),3); - bufp->fullCData(oldp+4663,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb),3); - bufp->fullCData(oldp+4664,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe),3); - bufp->fullWData(oldp+4665,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr),66); - bufp->fullWData(oldp+4668,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata),1536); - bufp->fullWData(oldp+4716,(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel),192); - bufp->fullCData(oldp+4722,(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err),3); - bufp->fullCData(oldp+4723,(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant),3); - bufp->fullCData(oldp+4724,(vlSelf->main__DOT__wbwide_xbar__DOT__mindex[0]),2); - bufp->fullCData(oldp+4725,(vlSelf->main__DOT__wbwide_xbar__DOT__mindex[1]),2); - bufp->fullCData(oldp+4726,(vlSelf->main__DOT__wbwide_xbar__DOT__mindex[2]),2); - bufp->fullCData(oldp+4727,(vlSelf->main__DOT__wbwide_xbar__DOT__mindex[3]),2); - bufp->fullCData(oldp+4728,(vlSelf->main__DOT__wbwide_xbar__DOT__sindex[0]),2); - bufp->fullCData(oldp+4729,(vlSelf->main__DOT__wbwide_xbar__DOT__sindex[1]),2); - bufp->fullCData(oldp+4730,(vlSelf->main__DOT__wbwide_xbar__DOT__sindex[2]),2); - bufp->fullCData(oldp+4731,(vlSelf->main__DOT__wbwide_xbar__DOT__sindex[3]),2); - bufp->fullCData(oldp+4732,(vlSelf->main__DOT__wbwide_xbar__DOT__m_we),4); - bufp->fullIData(oldp+4733,(vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[0]),22); - bufp->fullIData(oldp+4734,(vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[1]),22); - bufp->fullIData(oldp+4735,(vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[2]),22); - bufp->fullIData(oldp+4736,(vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[3]),22); - bufp->fullWData(oldp+4737,(vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0]),512); - bufp->fullWData(oldp+4753,(vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1]),512); - bufp->fullWData(oldp+4769,(vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2]),512); - bufp->fullWData(oldp+4785,(vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3]),512); - bufp->fullQData(oldp+4801,(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[0]),64); - bufp->fullQData(oldp+4803,(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[1]),64); - bufp->fullQData(oldp+4805,(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[2]),64); - bufp->fullQData(oldp+4807,(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[3]),64); - bufp->fullCData(oldp+4809,(vlSelf->main__DOT__wbwide_xbar__DOT__s_err),4); - bufp->fullCData(oldp+4810,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),4); - bufp->fullBit(oldp+4811,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available)); - bufp->fullCData(oldp+4812,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->fullCData(oldp+4813,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),4); - bufp->fullBit(oldp+4814,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available)); - bufp->fullCData(oldp+4815,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->fullCData(oldp+4816,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),4); - bufp->fullBit(oldp+4817,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available)); - bufp->fullCData(oldp+4818,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->fullCData(oldp+4819,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant),4); - bufp->fullBit(oldp+4820,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__requested_channel_is_available)); - bufp->fullCData(oldp+4821,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex),2); - bufp->fullCData(oldp+4822,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant),4); - bufp->fullCData(oldp+4823,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex),2); - bufp->fullCData(oldp+4824,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant),4); - bufp->fullCData(oldp+4825,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex),2); - bufp->fullCData(oldp+4826,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant),4); - bufp->fullCData(oldp+4827,(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex),2); - bufp->fullBit(oldp+4828,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall)); - bufp->fullBit(oldp+4829,(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall)); - bufp->fullCData(oldp+4830,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d),8); - bufp->fullSData(oldp+4831,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[0]),14); - bufp->fullSData(oldp+4832,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[1]),14); - bufp->fullSData(oldp+4833,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[2]),14); - bufp->fullSData(oldp+4834,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[3]),14); - bufp->fullSData(oldp+4835,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[4]),14); - bufp->fullSData(oldp+4836,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[5]),14); - bufp->fullSData(oldp+4837,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[6]),14); - bufp->fullSData(oldp+4838,(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[7]),14); - bufp->fullCData(oldp+4839,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[0]),4); - bufp->fullCData(oldp+4840,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[1]),4); - bufp->fullCData(oldp+4841,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[2]),4); - bufp->fullCData(oldp+4842,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[3]),4); - bufp->fullCData(oldp+4843,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[4]),4); - bufp->fullCData(oldp+4844,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[5]),4); - bufp->fullCData(oldp+4845,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[6]),4); - bufp->fullCData(oldp+4846,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[7]),4); - bufp->fullCData(oldp+4847,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[0]),4); - bufp->fullCData(oldp+4848,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[1]),4); - bufp->fullCData(oldp+4849,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[2]),4); - bufp->fullCData(oldp+4850,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[3]),4); - bufp->fullCData(oldp+4851,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[4]),4); - bufp->fullCData(oldp+4852,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[5]),4); - bufp->fullCData(oldp+4853,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[6]),4); - bufp->fullCData(oldp+4854,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[7]),4); - bufp->fullCData(oldp+4855,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[0]),4); - bufp->fullCData(oldp+4856,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[1]),4); - bufp->fullCData(oldp+4857,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[2]),4); - bufp->fullCData(oldp+4858,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[3]),4); - bufp->fullCData(oldp+4859,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[4]),4); - bufp->fullCData(oldp+4860,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[5]),4); - bufp->fullCData(oldp+4861,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[6]),4); - bufp->fullCData(oldp+4862,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[7]),4); - bufp->fullCData(oldp+4863,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[0]),4); - bufp->fullCData(oldp+4864,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[1]),4); - bufp->fullCData(oldp+4865,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[2]),4); - bufp->fullCData(oldp+4866,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[3]),4); - bufp->fullCData(oldp+4867,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[4]),4); - bufp->fullCData(oldp+4868,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[5]),4); - bufp->fullCData(oldp+4869,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[6]),4); - bufp->fullCData(oldp+4870,(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[7]),4); - bufp->fullIData(oldp+4871,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0]),24); - bufp->fullIData(oldp+4872,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1]),24); - bufp->fullIData(oldp+4873,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2]),24); - bufp->fullIData(oldp+4874,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3]),24); - bufp->fullBit(oldp+4875,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt)); - bufp->fullBit(oldp+4876,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en)); - bufp->fullBit(oldp+4877,(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n)); - bufp->fullBit(oldp+4878,(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_d)); - bufp->fullBit(oldp+4879,(vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy)); - bufp->fullBit(oldp+4880,(vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy)); - bufp->fullBit(oldp+4881,(vlSelf->main__DOT__wb32_xbar__DOT__m_stall)); - bufp->fullSData(oldp+4882,(vlSelf->main__DOT__wb32_xbar__DOT__s_stall),16); - bufp->fullBit(oldp+4883,(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)); - bufp->fullBit(oldp+4884,(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall)); - bufp->fullBit(oldp+4885,((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall))))); - bufp->fullCData(oldp+4886,(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall),4); - bufp->fullCData(oldp+4887,(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall),4); - bufp->fullCData(oldp+4888,(vlSelf->main__DOT__wbwide_xbar__DOT__s_ack),4); - bufp->fullBit(oldp+4889,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)); - bufp->fullBit(oldp+4890,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall)); - bufp->fullBit(oldp+4891,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall))))); - bufp->fullBit(oldp+4892,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall)); - bufp->fullBit(oldp+4893,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall)); - bufp->fullBit(oldp+4894,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall))))); - bufp->fullBit(oldp+4895,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall)); - bufp->fullBit(oldp+4896,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall)); - bufp->fullBit(oldp+4897,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall))))); - bufp->fullBit(oldp+4898,(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall)); - bufp->fullBit(oldp+4899,(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall)); - bufp->fullBit(oldp+4900,((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall))))); - bufp->fullBit(oldp+4901,(vlSelf->i_clk)); - bufp->fullBit(oldp+4902,(vlSelf->i_reset)); - bufp->fullWData(oldp+4903,(vlSelf->i_ddr3_controller_iserdes_data),512); - bufp->fullQData(oldp+4919,(vlSelf->i_ddr3_controller_iserdes_dqs),64); - bufp->fullQData(oldp+4921,(vlSelf->i_ddr3_controller_iserdes_bitslip_reference),64); - bufp->fullBit(oldp+4923,(vlSelf->i_ddr3_controller_idelayctrl_rdy)); - bufp->fullWData(oldp+4924,(vlSelf->o_ddr3_controller_cmd),96); - bufp->fullBit(oldp+4927,(vlSelf->o_ddr3_controller_dqs_tri_control)); - bufp->fullBit(oldp+4928,(vlSelf->o_ddr3_controller_dq_tri_control)); - bufp->fullBit(oldp+4929,(vlSelf->o_ddr3_controller_toggle_dqs)); - bufp->fullWData(oldp+4930,(vlSelf->o_ddr3_controller_data),512); - bufp->fullQData(oldp+4946,(vlSelf->o_ddr3_controller_dm),64); - bufp->fullCData(oldp+4948,(vlSelf->o_ddr3_controller_odelay_data_cntvaluein),5); - bufp->fullCData(oldp+4949,(vlSelf->o_ddr3_controller_odelay_dqs_cntvaluein),5); - bufp->fullCData(oldp+4950,(vlSelf->o_ddr3_controller_idelay_data_cntvaluein),5); - bufp->fullCData(oldp+4951,(vlSelf->o_ddr3_controller_idelay_dqs_cntvaluein),5); - bufp->fullCData(oldp+4952,(vlSelf->o_ddr3_controller_odelay_data_ld),8); - bufp->fullCData(oldp+4953,(vlSelf->o_ddr3_controller_odelay_dqs_ld),8); - bufp->fullCData(oldp+4954,(vlSelf->o_ddr3_controller_idelay_data_ld),8); - bufp->fullCData(oldp+4955,(vlSelf->o_ddr3_controller_idelay_dqs_ld),8); - bufp->fullCData(oldp+4956,(vlSelf->o_ddr3_controller_bitslip),8); - bufp->fullCData(oldp+4957,(vlSelf->o_sirefclk_word),8); - bufp->fullBit(oldp+4958,(vlSelf->o_sirefclk_ce)); - bufp->fullBit(oldp+4959,(vlSelf->i_fan_sda)); - bufp->fullBit(oldp+4960,(vlSelf->i_fan_scl)); - bufp->fullBit(oldp+4961,(vlSelf->o_fan_sda)); - bufp->fullBit(oldp+4962,(vlSelf->o_fan_scl)); - bufp->fullBit(oldp+4963,(vlSelf->o_fpga_pwm)); - bufp->fullBit(oldp+4964,(vlSelf->o_sys_pwm)); - bufp->fullBit(oldp+4965,(vlSelf->i_fan_tach)); - bufp->fullBit(oldp+4966,(vlSelf->o_emmc_clk)); - bufp->fullBit(oldp+4967,(vlSelf->i_emmc_ds)); - bufp->fullBit(oldp+4968,(vlSelf->io_emmc_cmd_tristate)); - bufp->fullBit(oldp+4969,(vlSelf->o_emmc_cmd)); - bufp->fullBit(oldp+4970,(vlSelf->i_emmc_cmd)); - bufp->fullCData(oldp+4971,(vlSelf->io_emmc_dat_tristate),8); - bufp->fullCData(oldp+4972,(vlSelf->o_emmc_dat),8); - bufp->fullCData(oldp+4973,(vlSelf->i_emmc_dat),8); - bufp->fullBit(oldp+4974,(vlSelf->i_emmc_detect)); - bufp->fullBit(oldp+4975,(vlSelf->i_i2c_sda)); - bufp->fullBit(oldp+4976,(vlSelf->i_i2c_scl)); - bufp->fullBit(oldp+4977,(vlSelf->o_i2c_sda)); - bufp->fullBit(oldp+4978,(vlSelf->o_i2c_scl)); - bufp->fullBit(oldp+4979,(vlSelf->o_sdcard_clk)); - bufp->fullBit(oldp+4980,(vlSelf->i_sdcard_ds)); - bufp->fullBit(oldp+4981,(vlSelf->io_sdcard_cmd_tristate)); - bufp->fullBit(oldp+4982,(vlSelf->o_sdcard_cmd)); - bufp->fullBit(oldp+4983,(vlSelf->i_sdcard_cmd)); - bufp->fullCData(oldp+4984,(vlSelf->io_sdcard_dat_tristate),4); - bufp->fullCData(oldp+4985,(vlSelf->o_sdcard_dat),4); - bufp->fullCData(oldp+4986,(vlSelf->i_sdcard_dat),4); - bufp->fullBit(oldp+4987,(vlSelf->i_sdcard_detect)); - bufp->fullBit(oldp+4988,(vlSelf->cpu_sim_cyc)); - bufp->fullBit(oldp+4989,(vlSelf->cpu_sim_stb)); - bufp->fullBit(oldp+4990,(vlSelf->cpu_sim_we)); - bufp->fullCData(oldp+4991,(vlSelf->cpu_sim_addr),7); - bufp->fullIData(oldp+4992,(vlSelf->cpu_sim_data),32); - bufp->fullBit(oldp+4993,(vlSelf->cpu_sim_stall)); - bufp->fullBit(oldp+4994,(vlSelf->cpu_sim_ack)); - bufp->fullIData(oldp+4995,(vlSelf->cpu_sim_idata),32); - bufp->fullBit(oldp+4996,(vlSelf->cpu_prof_stb)); - bufp->fullIData(oldp+4997,(vlSelf->cpu_prof_addr),28); - bufp->fullIData(oldp+4998,(vlSelf->cpu_prof_ticks),32); - bufp->fullBit(oldp+4999,(vlSelf->i_cpu_reset)); - bufp->fullBit(oldp+5000,(vlSelf->i_wbu_uart_rx)); - bufp->fullBit(oldp+5001,(vlSelf->o_wbu_uart_tx)); - bufp->fullBit(oldp+5002,(vlSelf->o_wbu_uart_cts_n)); - bufp->fullSData(oldp+5003,(vlSelf->i_gpio),16); - bufp->fullCData(oldp+5004,(vlSelf->o_gpio),8); - bufp->fullCData(oldp+5005,(vlSelf->i_sw),8); - bufp->fullCData(oldp+5006,(vlSelf->i_btn),5); - bufp->fullCData(oldp+5007,(vlSelf->o_led),8); - bufp->fullBit(oldp+5008,(vlSelf->i_clk200)); - bufp->fullIData(oldp+5009,((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted) - << 0x1fU) | ((0x40000000U - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data) - << 0x15U)) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort) - << 0x1dU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch) - << 0x1cU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn) - << 0x18U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait) - << 0x17U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request) - << 0x16U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted) - << 0x15U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl) - << 0xfU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda) - << 0xeU) - | (((IData)(vlSelf->i_fan_scl) - << 0xdU) - | (((IData)(vlSelf->i_fan_sda) - << 0xcU) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))))))))))))))))))),32); - bufp->fullIData(oldp+5010,((((IData)(vlSelf->main__DOT__gpioi__DOT__r_gpio) - << 0x10U) | (IData)(vlSelf->o_gpio))),32); - bufp->fullBit(oldp+5011,(((IData)(vlSelf->cpu_sim_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)))); - bufp->fullBit(oldp+5012,(((~ (IData)(vlSelf->cpu_sim_cyc)) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)))); - bufp->fullBit(oldp+5013,(vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n)); - bufp->fullSData(oldp+5014,(vlSelf->o_gpio),16); - bufp->fullBit(oldp+5015,(vlSelf->main__DOT____Vcellinp__swic__i_reset)); - bufp->fullCData(oldp+5016,(((IData)(vlSelf->cpu_sim_cyc) - ? 0xfU : (0xfU & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel) - >> 4U)))),4); - bufp->fullIData(oldp+5017,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc),28); - bufp->fullBit(oldp+5018,((((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F) - >> 3U)) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA) - & (IData)( - ((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))) - & ((0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - & (IData)( - ((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))) - & ((0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))))) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR) - & (IData)(((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U))))))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write))))); - bufp->fullBit(oldp+5019,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim)); - bufp->fullIData(oldp+5020,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim_immv),23); - bufp->fullBit(oldp+5021,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid)); - bufp->fullBit(oldp+5022,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim)); - bufp->fullIData(oldp+5023,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv),23); - bufp->fullBit(oldp+5024,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim)); - bufp->fullIData(oldp+5025,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv),23); - bufp->fullBit(oldp+5026,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce)); - bufp->fullIData(oldp+5027,((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn) - << 0x1cU) | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual) - << 0x18U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait) - << 0x17U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request) - << 0x16U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted) - << 0x15U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl) - << 0xfU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda) - << 0xeU) - | (((IData)(vlSelf->i_fan_scl) - << 0xdU) - | (((IData)(vlSelf->i_fan_sda) - << 0xcU) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)))))))))))))))),32); - bufp->fullBit(oldp+5028,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - bufp->fullCData(oldp+5029,((3U & (- (IData)((1U - & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U))))))),2); - bufp->fullBit(oldp+5030,((1U & (IData)(vlSelf->i_sdcard_dat)))); - bufp->fullBit(oldp+5031,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x19U)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - bufp->fullCData(oldp+5032,((3U & (- (IData)((1U - & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x19U))))))),2); - bufp->fullBit(oldp+5033,((1U & ((IData)(vlSelf->i_sdcard_dat) - >> 1U)))); - bufp->fullBit(oldp+5034,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1aU)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - bufp->fullCData(oldp+5035,((3U & (- (IData)((1U - & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1aU))))))),2); - bufp->fullBit(oldp+5036,((1U & ((IData)(vlSelf->i_sdcard_dat) - >> 2U)))); - bufp->fullBit(oldp+5037,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1bU)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - bufp->fullCData(oldp+5038,((3U & (- (IData)((1U - & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1bU))))))),2); - bufp->fullBit(oldp+5039,((1U & ((IData)(vlSelf->i_sdcard_dat) - >> 3U)))); - bufp->fullBit(oldp+5040,(((IData)(vlSelf->i_reset) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((~ (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2fU))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_cmd)))))); - bufp->fullCData(oldp+5041,((3U & (- (IData)(((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2fU)))))),2); - bufp->fullSData(oldp+5042,(((0xfffff800U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_ddr3_phy_ack) - << 0xbU))) - | ((0xfffffc00U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__r_cfg_ack) - << 0xaU))) - | ((0xfffffe00U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__r_wb32_sio_ack) - << 9U))) - | ((0xffffff00U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_sdcard_ack) - << 8U))) - | ((0xffffff80U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_fan_ack) - << 7U))) - | ((0xffffffc0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_emmc_ack) - << 6U))) - | ((0xffffffe0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_uart_ack) - << 5U))) - | ((0xfffffff0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_i2cdma_ack) - << 4U))) - | ((0xfffffff8U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_i2cs_ack) - << 3U))) - | ((0xfffffffcU - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack) - << 2U))) - | ((0xfffffffeU - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack)))))))))))))),16); - bufp->fullIData(oldp+5043,(vlSelf->main__DOT__wb32_xbar__DOT__iM),32); - bufp->fullCData(oldp+5044,(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),4); - bufp->fullCData(oldp+5045,(((((IData)(vlSelf->cpu_sim_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)) - << 1U) | (IData)(vlSelf->main__DOT__wbu_wbu_arbiter_stall))),2); - bufp->fullCData(oldp+5046,(((((~ (IData)(vlSelf->cpu_sim_cyc)) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)) - << 1U) | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack))),2); - bufp->fullCData(oldp+5047,(((0xfffffffeU & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (((~ (IData)(vlSelf->cpu_sim_cyc)) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack)))),4); - bufp->fullIData(oldp+5048,(vlSelf->main__DOT__wbu_xbar__DOT__iM),32); - bufp->fullCData(oldp+5049,(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->fullIData(oldp+5050,(vlSelf->main__DOT__wbwide_xbar__DOT__iN),32); - bufp->fullIData(oldp+5051,(vlSelf->main__DOT__wbwide_xbar__DOT__iM),32); - bufp->fullCData(oldp+5052,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->fullCData(oldp+5053,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->fullCData(oldp+5054,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->fullCData(oldp+5055,(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex),2); - bufp->fullDouble(oldp+5056,(10.0)); - bufp->fullDouble(oldp+5058,(2.50000000000000000e+00)); - bufp->fullIData(oldp+5060,(0xeU),32); - bufp->fullIData(oldp+5061,(0xaU),32); - bufp->fullIData(oldp+5062,(3U),32); - bufp->fullIData(oldp+5063,(8U),32); - bufp->fullIData(oldp+5064,(1U),32); - bufp->fullIData(oldp+5065,(4U),32); - bufp->fullIData(oldp+5066,(0x18U),32); - bufp->fullIData(oldp+5067,(0x4000000U),32); - bufp->fullIData(oldp+5068,(0x16U),32); - bufp->fullIData(oldp+5069,(0x10U),32); - bufp->fullBit(oldp+5070,(1U)); - bufp->fullIData(oldp+5071,(0x64U),24); - bufp->fullIData(oldp+5072,(7U),32); - bufp->fullIData(oldp+5073,(0x13U),32); - bufp->fullBit(oldp+5074,(0U)); - bufp->fullIData(oldp+5075,(2U),32); - bufp->fullIData(oldp+5076,(0U),32); - bufp->fullBit(oldp+5077,(1U)); - bufp->fullWData(oldp+5078,(Vmain__ConstPool__CONST_h93e1b771_0),512); - bufp->fullQData(oldp+5094,(0xffffffffffffffffULL),64); - bufp->fullCData(oldp+5096,(vlSelf->main__DOT__wb32_buildtime_addr),8); - bufp->fullBit(oldp+5097,(vlSelf->main__DOT__wb32_buildtime_err)); - bufp->fullIData(oldp+5098,(0x82055U),32); - bufp->fullCData(oldp+5099,(vlSelf->main__DOT__wb32_gpio_addr),8); - bufp->fullBit(oldp+5100,(vlSelf->main__DOT__wb32_gpio_err)); - bufp->fullCData(oldp+5101,(vlSelf->main__DOT__wb32_sirefclk_addr),8); - bufp->fullBit(oldp+5102,(vlSelf->main__DOT__wb32_sirefclk_err)); - bufp->fullCData(oldp+5103,(vlSelf->main__DOT__wb32_spio_addr),8); - bufp->fullBit(oldp+5104,(vlSelf->main__DOT__wb32_spio_err)); - bufp->fullCData(oldp+5105,(vlSelf->main__DOT__wb32_version_addr),8); - bufp->fullBit(oldp+5106,(vlSelf->main__DOT__wb32_version_err)); - bufp->fullIData(oldp+5107,(0x20230723U),32); - bufp->fullCData(oldp+5108,(0xfU),4); - bufp->fullCData(oldp+5109,(0x20U),8); - bufp->fullIData(oldp+5110,(0x14U),32); - bufp->fullIData(oldp+5111,(0x200U),32); - bufp->fullCData(oldp+5112,(0U),8); - bufp->fullBit(oldp+5113,(0U)); - bufp->fullIData(oldp+5114,(0x20U),32); - bufp->fullCData(oldp+5115,(6U),4); - bufp->fullCData(oldp+5116,(0U),2); - bufp->fullCData(oldp+5117,(1U),2); - bufp->fullCData(oldp+5118,(2U),2); - bufp->fullCData(oldp+5119,(3U),2); - bufp->fullIData(oldp+5120,(0x40U),32); - bufp->fullIData(oldp+5121,(0x15U),32); - bufp->fullCData(oldp+5122,(0U),4); - bufp->fullCData(oldp+5123,(1U),4); - bufp->fullCData(oldp+5124,(2U),4); - bufp->fullCData(oldp+5125,(3U),4); - bufp->fullCData(oldp+5126,(4U),4); - bufp->fullCData(oldp+5127,(5U),4); - bufp->fullCData(oldp+5128,(7U),4); - bufp->fullCData(oldp+5129,(8U),4); - bufp->fullIData(oldp+5130,(0x1bU),32); - bufp->fullIData(oldp+5131,(0x1aU),32); - bufp->fullIData(oldp+5132,(0x19U),32); - bufp->fullIData(oldp+5133,(0x17U),32); - bufp->fullIData(oldp+5134,(0x12U),32); - bufp->fullIData(oldp+5135,(0x11U),32); - bufp->fullIData(oldp+5136,(0xdU),32); - bufp->fullIData(oldp+5137,(0x30d40U),32); - bufp->fullIData(oldp+5138,(0x7a120U),32); - bufp->fullDouble(oldp+5139,(1.37500000000000000e+01)); - bufp->fullIData(oldp+5141,(0x23U),32); - bufp->fullDouble(oldp+5142,(350.0)); - bufp->fullIData(oldp+5144,(0x1e78U),32); - bufp->fullDouble(oldp+5145,(360.0)); - bufp->fullDouble(oldp+5147,(15.0)); - bufp->fullIData(oldp+5149,(0xaU),19); - bufp->fullDouble(oldp+5150,(7.50000000000000000e+00)); - bufp->fullIData(oldp+5152,(0x80U),32); - bufp->fullIData(oldp+5153,(6U),32); - bufp->fullIData(oldp+5154,(5U),32); - bufp->fullIData(oldp+5155,(0xc350U),19); - bufp->fullIData(oldp+5156,(9U),32); - bufp->fullIData(oldp+5157,(0xbU),32); - bufp->fullIData(oldp+5158,(0xcU),32); - bufp->fullCData(oldp+5159,(0U),3); - bufp->fullCData(oldp+5160,(2U),3); - bufp->fullIData(oldp+5161,(0x20040U),19); - bufp->fullCData(oldp+5162,(3U),3); - bufp->fullIData(oldp+5163,(0x30004U),19); - bufp->fullIData(oldp+5164,(0x30000U),19); - bufp->fullIData(oldp+5165,(0U),17); - bufp->fullCData(oldp+5166,(1U),3); - bufp->fullIData(oldp+5167,(0x108c4U),19); - bufp->fullIData(oldp+5168,(0x10844U),19); - bufp->fullIData(oldp+5169,(0x720U),19); - bufp->fullIData(oldp+5170,(0x4380005U),28); - bufp->fullIData(oldp+5171,(vlSelf->main__DOT__ddr3_controller_inst__DOT__aligned_cmd),24); - bufp->fullCData(oldp+5172,(vlSelf->main__DOT__ddr3_controller_inst__DOT__serial_index),2); - bufp->fullCData(oldp+5173,(vlSelf->main__DOT__ddr3_controller_inst__DOT__serial_index_q),2); - bufp->fullCData(oldp+5174,(vlSelf->main__DOT__ddr3_controller_inst__DOT__test_OFB),8); - bufp->fullCData(oldp+5175,(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_read_lane),3); - bufp->fullIData(oldp+5176,(vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__delay),32); - bufp->fullCData(oldp+5177,(vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__slot_number),2); - bufp->fullCData(oldp+5178,(vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__read_slot),2); - bufp->fullCData(oldp+5179,(vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__write_slot),2); - bufp->fullCData(oldp+5180,(vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__anticipate_activate_slot),2); - bufp->fullCData(oldp+5181,(vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__anticipate_precharge_slot),2); - bufp->fullIData(oldp+5182,(vlSelf->main__DOT__ddr3_controller_inst__DOT__find_delay__Vstatic__k),32); - bufp->fullCData(oldp+5183,(0xcU),5); - bufp->fullIData(oldp+5184,(0x1fU),32); - bufp->fullIData(oldp+5185,(0x7fcU),20); - bufp->fullIData(oldp+5186,(0x7fffffffU),31); - bufp->fullIData(oldp+5187,(0x1eU),32); - bufp->fullIData(oldp+5188,(0x24U),32); - bufp->fullIData(oldp+5189,(0x400U),32); - bufp->fullCData(oldp+5190,(0U),5); - bufp->fullQData(oldp+5191,(0x100000000ULL),36); - bufp->fullQData(oldp+5193,(0x40000000ULL),36); - bufp->fullQData(oldp+5195,(0ULL),36); - bufp->fullCData(oldp+5197,(0x4fU),7); - bufp->fullCData(oldp+5198,(0x49U),7); - bufp->fullIData(oldp+5199,(0x1cU),32); - bufp->fullIData(oldp+5200,(0U),28); - bufp->fullSData(oldp+5201,(0xfffU),12); - bufp->fullCData(oldp+5202,(9U),4); - bufp->fullCData(oldp+5203,(0xaU),4); - bufp->fullCData(oldp+5204,(0xbU),4); - bufp->fullCData(oldp+5205,(0xcU),4); - bufp->fullCData(oldp+5206,(0xdU),4); - bufp->fullCData(oldp+5207,(4U),3); - bufp->fullCData(oldp+5208,(5U),3); - bufp->fullCData(oldp+5209,(6U),3); - bufp->fullCData(oldp+5210,(7U),3); - bufp->fullCData(oldp+5211,(0xaU),5); - bufp->fullIData(oldp+5212,(0x1fcU),20); - bufp->fullCData(oldp+5213,(0x64U),7); - bufp->fullCData(oldp+5214,(0x32U),7); - bufp->fullIData(oldp+5215,(0xc0000000U),32); - bufp->fullCData(oldp+5216,(1U),8); - bufp->fullCData(oldp+5217,(2U),8); - bufp->fullCData(oldp+5218,(3U),8); - bufp->fullCData(oldp+5219,(4U),8); - bufp->fullCData(oldp+5220,(5U),8); - bufp->fullCData(oldp+5221,(6U),8); - bufp->fullCData(oldp+5222,(7U),8); - bufp->fullCData(oldp+5223,(8U),8); - bufp->fullCData(oldp+5224,(9U),8); - bufp->fullCData(oldp+5225,(0xaU),8); - bufp->fullCData(oldp+5226,(0xbU),8); - bufp->fullCData(oldp+5227,(0xcU),8); - bufp->fullCData(oldp+5228,(0xdU),8); - bufp->fullCData(oldp+5229,(0xeU),8); - bufp->fullCData(oldp+5230,(0xfU),8); - bufp->fullCData(oldp+5231,(0x80U),8); - bufp->fullCData(oldp+5232,(0x10U),8); - bufp->fullIData(oldp+5233,(0U),20); - bufp->fullIData(oldp+5234,(0x208U),32); - __Vtemp_hf465e4c8__0[0U] = 0x54494e47U; - __Vtemp_hf465e4c8__0[1U] = 0x45524e41U; - __Vtemp_hf465e4c8__0[2U] = 0x414c54U; - bufp->fullWData(oldp+5235,(__Vtemp_hf465e4c8__0),88); - bufp->fullIData(oldp+5238,(0x41425254U),32); - bufp->fullIData(oldp+5239,(0x40U),32); - bufp->fullIData(oldp+5240,(0xfU),32); - bufp->fullBit(oldp+5241,(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__UNUSED_BITS__DOT__unused_aw)); - bufp->fullIData(oldp+5242,(0x1000000U),26); - bufp->fullCData(oldp+5243,(0xeU),4); - bufp->fullSData(oldp+5244,(0x1d7U),9); - bufp->fullSData(oldp+5245,(0x2000U),14); - bufp->fullIData(oldp+5246,(0U),31); - bufp->fullCData(oldp+5247,(7U),5); - bufp->fullSData(oldp+5248,(0x1021U),16); - bufp->fullCData(oldp+5249,(9U),7); - bufp->fullIData(oldp+5250,(0x10U),32); - bufp->fullIData(oldp+5251,(0x5f5e100U),32); - bufp->fullIData(oldp+5252,(0x186a0U),32); - bufp->fullIData(oldp+5253,(0x4e20U),32); - bufp->fullIData(oldp+5254,(0x1387U),32); - bufp->fullSData(oldp+5255,(0xc8U),12); - __Vtemp_hba125475__0[0U] = 0x18100800U; - __Vtemp_hba125475__0[1U] = 0x38302820U; - __Vtemp_hba125475__0[2U] = 0x80604840U; - bufp->fullWData(oldp+5256,(__Vtemp_hba125475__0),96); - __Vtemp_hca679e21__0[0U] = 0xf8f8f8f8U; - __Vtemp_hca679e21__0[1U] = 0xf8f8f8f8U; - __Vtemp_hca679e21__0[2U] = 0x80e0f8f8U; - bufp->fullWData(oldp+5259,(__Vtemp_hca679e21__0),96); - bufp->fullSData(oldp+5262,(0U),12); - bufp->fullSData(oldp+5263,(0xf000U),16); - bufp->fullIData(oldp+5264,(0x25U),32); - bufp->fullIData(oldp+5265,(0x2dU),32); - bufp->fullQData(oldp+5266,(0x20000000000000ULL),54); - bufp->fullQData(oldp+5268,(0x20000004000000ULL),54); - __Vtemp_h0730ce07__0[0U] = 0x80000U; - __Vtemp_h0730ce07__0[1U] = 0x400U; - __Vtemp_h0730ce07__0[2U] = 2U; - bufp->fullWData(oldp+5270,(__Vtemp_h0730ce07__0),66); - __Vtemp_h754c1427__0[0U] = 0x380000U; - __Vtemp_h754c1427__0[1U] = 0xe00U; - __Vtemp_h754c1427__0[2U] = 2U; - bufp->fullWData(oldp+5273,(__Vtemp_h754c1427__0),66); - bufp->fullIData(oldp+5276,(0x241U),32); - bufp->fullIData(oldp+5277,(0x257U),32); -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root.h b/delete_later/rtl/obj_dir/Vmain___024root.h deleted file mode 100644 index 627eba2..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root.h +++ /dev/null @@ -1,3379 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design internal header -// See Vmain.h for the primary calling header - -#ifndef VERILATED_VMAIN___024ROOT_H_ -#define VERILATED_VMAIN___024ROOT_H_ // guard - -#include "verilated.h" - - -class Vmain__Syms; - -class alignas(VL_CACHE_LINE_BYTES) Vmain___024root final : public VerilatedModule { - public: - - // DESIGN SPECIFIC STATE - // Anonymous structures to workaround compiler member-count bugs - struct { - VL_IN8(i_clk,0,0); - CData/*0:0*/ main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n; - VL_IN8(i_reset,0,0); - VL_IN8(i_ddr3_controller_idelayctrl_rdy,0,0); - VL_OUT8(o_ddr3_controller_dqs_tri_control,0,0); - VL_OUT8(o_ddr3_controller_dq_tri_control,0,0); - VL_OUT8(o_ddr3_controller_toggle_dqs,0,0); - VL_OUT8(o_ddr3_controller_odelay_data_cntvaluein,4,0); - VL_OUT8(o_ddr3_controller_odelay_dqs_cntvaluein,4,0); - VL_OUT8(o_ddr3_controller_idelay_data_cntvaluein,4,0); - VL_OUT8(o_ddr3_controller_idelay_dqs_cntvaluein,4,0); - VL_OUT8(o_ddr3_controller_odelay_data_ld,7,0); - VL_OUT8(o_ddr3_controller_odelay_dqs_ld,7,0); - VL_OUT8(o_ddr3_controller_idelay_data_ld,7,0); - VL_OUT8(o_ddr3_controller_idelay_dqs_ld,7,0); - VL_OUT8(o_ddr3_controller_bitslip,7,0); - VL_OUT8(o_sirefclk_word,7,0); - VL_OUT8(o_sirefclk_ce,0,0); - VL_IN8(i_fan_sda,0,0); - VL_IN8(i_fan_scl,0,0); - VL_OUT8(o_fan_sda,0,0); - VL_OUT8(o_fan_scl,0,0); - VL_OUT8(o_fpga_pwm,0,0); - VL_OUT8(o_sys_pwm,0,0); - VL_IN8(i_fan_tach,0,0); - VL_OUT8(o_emmc_clk,0,0); - VL_IN8(i_emmc_ds,0,0); - VL_OUT8(io_emmc_cmd_tristate,0,0); - VL_OUT8(o_emmc_cmd,0,0); - VL_IN8(i_emmc_cmd,0,0); - VL_OUT8(io_emmc_dat_tristate,7,0); - VL_OUT8(o_emmc_dat,7,0); - VL_IN8(i_emmc_dat,7,0); - VL_IN8(i_emmc_detect,0,0); - VL_IN8(i_i2c_sda,0,0); - VL_IN8(i_i2c_scl,0,0); - VL_OUT8(o_i2c_sda,0,0); - VL_OUT8(o_i2c_scl,0,0); - VL_OUT8(o_sdcard_clk,0,0); - VL_IN8(i_sdcard_ds,0,0); - VL_OUT8(io_sdcard_cmd_tristate,0,0); - VL_OUT8(o_sdcard_cmd,0,0); - VL_IN8(i_sdcard_cmd,0,0); - VL_OUT8(io_sdcard_dat_tristate,3,0); - VL_OUT8(o_sdcard_dat,3,0); - VL_IN8(i_sdcard_dat,3,0); - VL_IN8(i_sdcard_detect,0,0); - VL_IN8(cpu_sim_cyc,0,0); - VL_IN8(cpu_sim_stb,0,0); - VL_IN8(cpu_sim_we,0,0); - VL_IN8(cpu_sim_addr,6,0); - VL_OUT8(cpu_sim_stall,0,0); - VL_OUT8(cpu_sim_ack,0,0); - VL_OUT8(cpu_prof_stb,0,0); - VL_IN8(i_cpu_reset,0,0); - VL_IN8(i_clk200,0,0); - VL_IN8(i_wbu_uart_rx,0,0); - VL_OUT8(o_wbu_uart_tx,0,0); - VL_OUT8(o_wbu_uart_cts_n,0,0); - VL_OUT8(o_gpio,7,0); - VL_IN8(i_sw,7,0); - VL_IN8(i_btn,4,0); - VL_OUT8(o_led,7,0); - CData/*0:0*/ main__DOT__emmcscope_int; - }; - struct { - CData/*0:0*/ main__DOT__sdioscope_int; - CData/*0:0*/ main__DOT__emmc_int; - CData/*0:0*/ main__DOT__sdcard_int; - CData/*0:0*/ main__DOT__i2cscope_int; - CData/*0:0*/ main__DOT__gpio_int; - CData/*0:0*/ main__DOT__spio_int; - CData/*0:0*/ main__DOT__r_sirefclk_en; - CData/*0:0*/ main__DOT__w_sirefclk_unused_stb; - CData/*0:0*/ main__DOT__r_sirefclk_ack; - CData/*0:0*/ main__DOT__i2cdma_ready; - CData/*0:0*/ main__DOT__i2c_valid; - CData/*0:0*/ main__DOT__i2c_ready; - CData/*0:0*/ main__DOT__i2c_last; - CData/*7:0*/ main__DOT__i2c_data; - CData/*0:0*/ main__DOT__w_console_rx_stb; - CData/*0:0*/ main__DOT__w_console_busy; - CData/*6:0*/ main__DOT__w_console_rx_data; - CData/*6:0*/ main__DOT__w_console_tx_data; - CData/*0:0*/ main__DOT__raw_cpu_dbg_stall; - CData/*0:0*/ main__DOT__raw_cpu_dbg_ack; - CData/*0:0*/ main__DOT__zip_cpu_int; - CData/*7:0*/ main__DOT__wbu_rx_data; - CData/*0:0*/ main__DOT__wbu_rx_stb; - CData/*7:0*/ main__DOT__w_led; - CData/*0:0*/ main__DOT__wbwide_i2cdma_cyc; - CData/*0:0*/ main__DOT__wbwide_i2cdma_stb; - CData/*0:0*/ main__DOT__wbwide_i2cm_cyc; - CData/*0:0*/ main__DOT__wbwide_i2cm_stb; - CData/*0:0*/ main__DOT__wbwide_zip_cyc; - CData/*0:0*/ main__DOT__wbwide_zip_stb; - CData/*0:0*/ main__DOT__wbwide_wbu_arbiter_cyc; - CData/*0:0*/ main__DOT__wbwide_wbu_arbiter_stb; - CData/*0:0*/ main__DOT__wbwide_wbdown_stall; - CData/*0:0*/ main__DOT__wbwide_bkram_ack; - CData/*0:0*/ main__DOT__wbwide_ddr3_controller_stall; - CData/*0:0*/ main__DOT__wb32_wbdown_cyc; - CData/*0:0*/ main__DOT__wb32_wbdown_stb; - CData/*0:0*/ main__DOT__wb32_wbdown_err; - CData/*7:0*/ main__DOT__wb32_buildtime_addr; - CData/*0:0*/ main__DOT__wb32_buildtime_err; - CData/*7:0*/ main__DOT__wb32_gpio_addr; - CData/*0:0*/ main__DOT__wb32_gpio_err; - CData/*0:0*/ main__DOT__wb32_sirefclk_stb; - CData/*7:0*/ main__DOT__wb32_sirefclk_addr; - CData/*0:0*/ main__DOT__wb32_sirefclk_err; - CData/*0:0*/ main__DOT__wb32_spio_stb; - CData/*7:0*/ main__DOT__wb32_spio_addr; - CData/*0:0*/ main__DOT__wb32_spio_ack; - CData/*0:0*/ main__DOT__wb32_spio_err; - CData/*7:0*/ main__DOT__wb32_version_addr; - CData/*0:0*/ main__DOT__wb32_version_err; - CData/*0:0*/ main__DOT__wb32_i2cs_ack; - CData/*0:0*/ main__DOT__wb32_i2cdma_ack; - CData/*0:0*/ main__DOT__wb32_uart_ack; - CData/*0:0*/ main__DOT__wb32_emmc_ack; - CData/*0:0*/ main__DOT__wb32_fan_ack; - CData/*0:0*/ main__DOT__wb32_sdcard_ack; - CData/*0:0*/ main__DOT__wb32_ddr3_phy_stall; - CData/*0:0*/ main__DOT__wb32_ddr3_phy_ack; - CData/*0:0*/ main__DOT__wbu_cyc; - CData/*0:0*/ main__DOT__wbu_stb; - CData/*0:0*/ main__DOT__wbu_we; - CData/*0:0*/ main__DOT__wbu_err; - CData/*0:0*/ main__DOT__wbu_wbu_arbiter_stall; - }; - struct { - CData/*2:0*/ main__DOT____Vcellout__wbwide_xbar__o_swe; - CData/*2:0*/ main__DOT____Vcellout__wbwide_xbar__o_sstb; - CData/*2:0*/ main__DOT____Vcellout__wbwide_xbar__o_scyc; - CData/*3:0*/ main__DOT____Vcellout__wbwide_xbar__o_merr; - CData/*3:0*/ main__DOT____Vcellinp__wbwide_xbar__i_mcyc; - CData/*0:0*/ main__DOT__r_wb32_sio_ack; - CData/*7:0*/ main__DOT____Vcellout__wbu_xbar__o_ssel; - CData/*1:0*/ main__DOT____Vcellout__wbu_xbar__o_swe; - CData/*1:0*/ main__DOT____Vcellout__wbu_xbar__o_sstb; - CData/*1:0*/ main__DOT____Vcellout__wbu_xbar__o_scyc; - CData/*0:0*/ main__DOT____Vcellinp__emmcscopei____pinNumber3; - CData/*0:0*/ main__DOT____Vcellinp__sdioscopei____pinNumber3; - CData/*0:0*/ main__DOT____Vcellinp__u_i2cdma__S_VALID; - CData/*6:0*/ main__DOT____Vcellinp__swic__i_dbg_addr; - CData/*0:0*/ main__DOT____Vcellinp__swic__i_dbg_we; - CData/*0:0*/ main__DOT____Vcellinp__swic__i_dbg_stb; - CData/*0:0*/ main__DOT____Vcellinp__swic__i_dbg_cyc; - CData/*0:0*/ main__DOT____Vcellinp__swic__i_reset; - CData/*0:0*/ main__DOT__r_cfg_ack; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__mgrant; - CData/*2:0*/ main__DOT__wbwide_xbar__DOT__sgrant; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__mfull; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__mnearfull; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__mempty; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__m_stb; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__m_we; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__m_stall; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__s_stall; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__s_ack; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__s_err; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__decoded; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskd_ready; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__decoded; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskd_ready; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__decoded; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskd_ready; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant; - }; - struct { - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available; - CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available; - CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available; - CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - CData/*3:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - CData/*1:0*/ main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex; 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- CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__clk90; - CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90; - CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active; - CData/*5:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type; - CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout; - CData/*6:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready; - CData/*3:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid; - CData/*4:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit; - CData/*4:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb; - CData/*3:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr; - CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge; - }; - struct { - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__resp_started; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__io_started; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb; - CData/*7:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg; - CData/*1:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck; - CData/*0:0*/ main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0; - CData/*0:0*/ main__DOT__i2ci__DOT__cpu_new_pc; - CData/*0:0*/ main__DOT__i2ci__DOT__pf_valid; - CData/*0:0*/ main__DOT__i2ci__DOT__pf_ready; - CData/*7:0*/ main__DOT__i2ci__DOT__pf_insn; - CData/*0:0*/ main__DOT__i2ci__DOT__pf_illegal; - CData/*0:0*/ main__DOT__i2ci__DOT__half_valid; - CData/*0:0*/ main__DOT__i2ci__DOT__imm_cycle; - CData/*0:0*/ main__DOT__i2ci__DOT__next_valid; - CData/*7:0*/ main__DOT__i2ci__DOT__next_insn; - CData/*0:0*/ main__DOT__i2ci__DOT__insn_ready; - CData/*0:0*/ main__DOT__i2ci__DOT__half_ready; - CData/*0:0*/ main__DOT__i2ci__DOT__i2c_abort; - CData/*0:0*/ main__DOT__i2ci__DOT__insn_valid; - CData/*3:0*/ main__DOT__i2ci__DOT__half_insn; - CData/*0:0*/ main__DOT__i2ci__DOT__i2c_ckedge; - CData/*0:0*/ main__DOT__i2ci__DOT__i2c_stretch; - CData/*0:0*/ main__DOT__i2ci__DOT__r_wait; - CData/*0:0*/ main__DOT__i2ci__DOT__soft_halt_request; - CData/*0:0*/ main__DOT__i2ci__DOT__r_halted; - CData/*0:0*/ main__DOT__i2ci__DOT__r_err; - CData/*0:0*/ main__DOT__i2ci__DOT__r_aborted; - CData/*0:0*/ main__DOT__i2ci__DOT__w_sda; - CData/*0:0*/ main__DOT__i2ci__DOT__w_scl; - CData/*0:0*/ main__DOT__i2ci__DOT__bus_write; - CData/*0:0*/ main__DOT__i2ci__DOT__bus_override; - CData/*0:0*/ main__DOT__i2ci__DOT__bus_manual; - CData/*0:0*/ main__DOT__i2ci__DOT__ovw_ready; - CData/*0:0*/ main__DOT__i2ci__DOT__bus_jump; - CData/*0:0*/ main__DOT__i2ci__DOT__s_tvalid; - CData/*0:0*/ main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset; - CData/*0:0*/ main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN; - CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual; - CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl; - CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda; - CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl; - CData/*0:0*/ main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda; - CData/*0:0*/ main__DOT__i2ci__DOT__GEN_TID__DOT__mid_axis_pkt; - CData/*1:0*/ main__DOT__i2ci__DOT__GEN_TID__DOT__r_channel; - CData/*1:0*/ main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid; - CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__last_stb; - CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle; - CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid; - CData/*1:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__inflight; - CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal; - CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__r_valid; - CData/*0:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid; - CData/*6:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count; - CData/*5:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__dir; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack; - CData/*3:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__state; - }; - struct { - CData/*2:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits; - CData/*7:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__q_scl; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__q_sda; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_scl; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_sda; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__stop_bit; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_we; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first; - CData/*7:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last; - CData/*3:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift; - CData/*3:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__i_subaddr; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty; - CData/*5:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill; - CData/*4:0*/ main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data; - CData/*4:0*/ main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data; - CData/*0:0*/ main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr; - CData/*0:0*/ main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_full; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty; - CData/*5:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr; - CData/*5:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr; - CData/*0:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd; - CData/*0:0*/ main__DOT__u_sdcard__DOT__cfg_ddr; - CData/*4:0*/ main__DOT__u_sdcard__DOT__cfg_sample_shift; - CData/*7:0*/ main__DOT__u_sdcard__DOT__sdclk; - CData/*0:0*/ main__DOT__u_sdcard__DOT__pp_cmd; - CData/*0:0*/ main__DOT__u_sdcard__DOT__pp_data; - CData/*0:0*/ main__DOT__u_sdcard__DOT__rx_en; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half; - CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk; - CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_ckspd; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done; - CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type; - CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb; - CData/*5:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready; - }; - struct { - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb; - CData/*6:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err; - CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode; - CData/*3:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk; - CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width; - CData/*7:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_ack; - CData/*1:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel; - CData/*3:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a; - CData/*3:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request; - CData/*2:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present; - CData/*0:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_removed; 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- CData/*0:0*/ main__DOT__swic__DOT__mpc_int; - CData/*0:0*/ main__DOT__swic__DOT__mic_int; - CData/*0:0*/ main__DOT__swic__DOT__utc_int; - CData/*0:0*/ main__DOT__swic__DOT__uoc_int; - CData/*0:0*/ main__DOT__swic__DOT__upc_int; - CData/*0:0*/ main__DOT__swic__DOT__uic_int; - CData/*0:0*/ main__DOT__swic__DOT__actr_ack; - CData/*0:0*/ main__DOT__swic__DOT__sys_cyc; - CData/*0:0*/ main__DOT__swic__DOT__sys_stb; - CData/*0:0*/ main__DOT__swic__DOT__sys_we; - CData/*7:0*/ main__DOT__swic__DOT__sys_addr; - CData/*0:0*/ main__DOT__swic__DOT__sys_ack; - CData/*0:0*/ main__DOT__swic__DOT__sel_timer; - CData/*0:0*/ main__DOT__swic__DOT__sel_pic; - CData/*0:0*/ main__DOT__swic__DOT__sel_apic; - }; - struct { - CData/*0:0*/ main__DOT__swic__DOT__sel_watchdog; - CData/*0:0*/ main__DOT__swic__DOT__sel_bus_watchdog; - CData/*0:0*/ main__DOT__swic__DOT__sel_dmac; - CData/*0:0*/ main__DOT__swic__DOT__dbg_cyc; - CData/*0:0*/ main__DOT__swic__DOT__dbg_stb; - CData/*0:0*/ main__DOT__swic__DOT__dbg_we; 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- CData/*5:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending; - CData/*2:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cline; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__in_cache; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__gie; - CData/*3:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel; - CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr; - CData/*4:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__UNUSED_BITS__DOT__unused_aw; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner; - CData/*0:0*/ main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner; - CData/*0:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb; - CData/*0:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_we; - CData/*6:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_addr; - CData/*3:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_sel; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc; - CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size; - CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__rx_valid; - }; - struct { - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready; - CData/*4:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_valid; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_zero_len; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_busy; - CData/*4:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel; - CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state; - CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size; - CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size; - CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size; - CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size; - CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr; - CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr; - CData/*7:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__fill; - CData/*7:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last; - CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes; - CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc; - CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size; - CData/*7:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill; - CData/*7:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last; - CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes; - CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty; - CData/*4:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr; - CData/*4:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next; - CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes; - CData/*6:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc; - CData/*1:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size; - CData/*5:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner; - CData/*0:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner; - CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie; - CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any; - CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write; - CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__enable_ints; - CData/*0:0*/ main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__disable_ints; - CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie; - CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any; - }; - struct { - CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write; - CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__enable_ints; - CData/*0:0*/ main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__disable_ints; - CData/*0:0*/ main__DOT__i2cscopei__DOT__read_from_data; - CData/*0:0*/ main__DOT__i2cscopei__DOT__write_to_control; - CData/*0:0*/ main__DOT__i2cscopei__DOT__read_address; - CData/*0:0*/ main__DOT__i2cscopei__DOT__bw_reset_request; - CData/*2:0*/ main__DOT__i2cscopei__DOT__br_config; - CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_triggered; - CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_primed; - CData/*0:0*/ main__DOT__i2cscopei__DOT__dw_trigger; - CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_stopped; - CData/*4:0*/ main__DOT__i2cscopei__DOT__dr_stop_pipe; - CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_force_write; - CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_run_timeout; - CData/*0:0*/ main__DOT__i2cscopei__DOT__new_data; - CData/*0:0*/ main__DOT__i2cscopei__DOT__dr_force_inhibit; - CData/*0:0*/ main__DOT__i2cscopei__DOT__imm_adr; - CData/*0:0*/ main__DOT__i2cscopei__DOT__lst_adr; - CData/*0:0*/ main__DOT__i2cscopei__DOT__record_ce; - CData/*0:0*/ main__DOT__i2cscopei__DOT__br_wb_ack; - CData/*0:0*/ main__DOT__i2cscopei__DOT__br_pre_wb_ack; - CData/*0:0*/ main__DOT__i2cscopei__DOT__br_level_interrupt; - CData/*3:0*/ main__DOT__rcv__DOT__state; - CData/*6:0*/ main__DOT__rcv__DOT__baud_counter; - CData/*0:0*/ main__DOT__rcv__DOT__zero_baud_counter; - CData/*0:0*/ main__DOT__rcv__DOT__q_uart; - CData/*0:0*/ main__DOT__rcv__DOT__qq_uart; - CData/*0:0*/ main__DOT__rcv__DOT__ck_uart; - CData/*6:0*/ main__DOT__rcv__DOT__chg_counter; - CData/*0:0*/ main__DOT__rcv__DOT__half_baud_time; - CData/*7:0*/ main__DOT__rcv__DOT__data_reg; - CData/*6:0*/ main__DOT__txv__DOT__baud_counter; - CData/*3:0*/ main__DOT__txv__DOT__state; - CData/*7:0*/ main__DOT__txv__DOT__lcl_data; - CData/*0:0*/ main__DOT__txv__DOT__r_busy; - CData/*0:0*/ main__DOT__txv__DOT__zero_baud_counter; - CData/*0:0*/ main__DOT__genbus__DOT__soft_reset; - CData/*0:0*/ main__DOT__genbus__DOT__r_wdt_reset; - CData/*0:0*/ main__DOT__genbus__DOT__rx_valid; - CData/*0:0*/ main__DOT__genbus__DOT__in_stb; - CData/*0:0*/ main__DOT__genbus__DOT__ps_full; - CData/*7:0*/ main__DOT__genbus__DOT__ps_data; - CData/*0:0*/ main__DOT__genbus__DOT__wbu_tx_stb; - CData/*7:0*/ main__DOT__genbus__DOT__wbu_tx_data; - CData/*0:0*/ main__DOT__genbus__DOT__exec_stb; - CData/*0:0*/ main__DOT__genbus__DOT__ofifo_rd; - CData/*0:0*/ main__DOT__genbus__DOT__ofifo_empty_n; - CData/*0:0*/ main__DOT__genbus__DOT__w_bus_busy; - CData/*0:0*/ main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy; - CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n; - CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd; - CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__hx_stb; - CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__hx_valid; - CData/*5:0*/ main__DOT__genbus__DOT__getinput__DOT__hx_hexbits; - CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__cw_stb; - CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__cod_busy; - CData/*6:0*/ main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv; - CData/*2:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len; - CData/*2:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len; - CData/*1:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw; - CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb; - CData/*0:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy; - CData/*7:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr; - }; - struct { - CData/*7:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cmd_addr; - CData/*2:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb; - CData/*1:0*/ main__DOT__genbus__DOT__runwb__DOT__wb_state; - CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__r_inc; - CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__r_new_addr; - CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__last_read_request; - CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__last_ack; - CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__zero_acks; - CData/*0:0*/ main__DOT__genbus__DOT__runwb__DOT__r_busy; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__dw_busy; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__cw_stb; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__cp_stb; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__dw_stb; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__ln_stb; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__ln_busy; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__cp_busy; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__byte_busy; - CData/*6:0*/ main__DOT__genbus__DOT__wroutput__DOT__dw_bits; - CData/*6:0*/ main__DOT__genbus__DOT__wroutput__DOT__ln_bits; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__r_active; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy; - CData/*2:0*/ main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__full_line; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy; - CData/*6:0*/ main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen; - CData/*6:0*/ main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__newv; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid; - CData/*3:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__vaddr; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__zmatch; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__hmatch; - CData/*2:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_hlfd; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table; - CData/*0:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match; - CData/*6:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr; - CData/*6:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr; - CData/*6:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__nxt_wrptr; - CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow; - CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow; - CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write; - CData/*0:0*/ main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read; - CData/*0:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow; - CData/*0:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow; - CData/*0:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write; - CData/*0:0*/ main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read; - CData/*0:0*/ main__DOT__spioi__DOT__led_demo; - CData/*7:0*/ main__DOT__spioi__DOT__r_led; - CData/*7:0*/ main__DOT__spioi__DOT__bounced; - CData/*0:0*/ main__DOT__spioi__DOT__sw_int; - CData/*4:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn; - CData/*4:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__s_btn; - CData/*4:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn; - CData/*0:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn_int; - }; - struct { - CData/*0:0*/ main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_int; - CData/*7:0*/ main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw; - CData/*7:0*/ main__DOT__spioi__DOT__knightrider__DOT__led_owner; - CData/*0:0*/ main__DOT__spioi__DOT__knightrider__DOT__led_dir; - CData/*0:0*/ main__DOT__spioi__DOT__knightrider__DOT__led_clk; - CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__br_ctr; - CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness; - CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness; - CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness; - CData/*4:0*/ main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness; 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- CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty; - CData/*5:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr; - CData/*5:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr; - CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr; - CData/*0:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd; - CData/*2:0*/ __VdfgTmp_h503d14d1__0; - CData/*1:0*/ __VdfgTmp_ha46ae6a3__0; - CData/*7:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data; - CData/*2:0*/ __Vdly__main__DOT__wbwide_xbar__DOT__sgrant; - CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v0; - CData/*3:0*/ __Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v1; - CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v1; - CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v2; - CData/*0:0*/ __Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v3; - CData/*3:0*/ __Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v4; 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- CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3; - CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3; - }; - struct { - CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0; - CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0; - CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0; - CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1; - CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1; - CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1; - CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2; - CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2; - CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2; - CData/*4:0*/ __Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3; - CData/*7:0*/ __Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3; - CData/*0:0*/ __Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3; - CData/*5:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount; - CData/*7:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count; - CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb; - CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout; - CData/*6:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done; - CData/*1:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate; - CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid; - CData/*3:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count; - CData/*4:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts; - CData/*4:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill; - CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid; - CData/*1:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr; - CData/*1:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr; - CData/*3:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy; - CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done; - CData/*0:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy; - CData/*0:0*/ __Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow; - CData/*5:0*/ __Vdlyvdim0__main__DOT__console__DOT__rxfifo__DOT__fifo__v0; - CData/*6:0*/ __Vdlyvval__main__DOT__console__DOT__rxfifo__DOT__fifo__v0; - CData/*0:0*/ __Vdlyvset__main__DOT__console__DOT__rxfifo__DOT__fifo__v0; - CData/*0:0*/ __Vdly__main__DOT__console__DOT__rxfifo__DOT__will_underflow; - CData/*5:0*/ __Vdly__main__DOT__console__DOT__rxfifo__DOT__rd_addr; - CData/*5:0*/ __Vdly__main__DOT__console__DOT__rxfifo__DOT__r_fill; - CData/*0:0*/ __Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow; - CData/*5:0*/ __Vdlyvdim0__main__DOT__console__DOT__txfifo__DOT__fifo__v0; - CData/*6:0*/ __Vdlyvval__main__DOT__console__DOT__txfifo__DOT__fifo__v0; - CData/*0:0*/ __Vdlyvset__main__DOT__console__DOT__txfifo__DOT__fifo__v0; - CData/*0:0*/ __Vdly__main__DOT__console__DOT__txfifo__DOT__will_underflow; - CData/*5:0*/ __Vdly__main__DOT__console__DOT__txfifo__DOT__rd_addr; - CData/*5:0*/ __Vdly__main__DOT__console__DOT__txfifo__DOT__r_fill; - CData/*4:0*/ __Vdly__main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__cmd_clear_cache; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__cmd_write; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__cmd_read; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__cmd_read_ack; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_zero; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__wdt_reset; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__wdbus_int; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero; - CData/*1:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_cyc; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb; - CData/*2:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0; - CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0; - CData/*5:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr; - CData/*5:0*/ __Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0; - CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_illegal; - }; - struct { - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__dbg_stb; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request; - CData/*1:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb; - CData/*6:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy; - CData/*6:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid; - CData/*5:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last; - CData/*4:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill; - CData/*4:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr; - CData/*3:0*/ __Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0; - CData/*0:0*/ __Vdlyvset__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0; - CData/*4:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr; - CData/*6:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last; - CData/*0:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner; - CData/*0:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_stopped; - CData/*4:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_stop_pipe; - CData/*0:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_force_inhibit; - CData/*0:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_force_write; - CData/*0:0*/ __Vdly__main__DOT__i2cscopei__DOT__dr_primed; - CData/*0:0*/ __Vdlyvset__main__DOT__i2cscopei__DOT__mem__v0; - CData/*6:0*/ __Vdly__main__DOT__rcv__DOT__chg_counter; - CData/*3:0*/ __Vdly__main__DOT__rcv__DOT__state; - CData/*7:0*/ __Vdly__main__DOT__rcv__DOT__data_reg; - CData/*6:0*/ __Vdly__main__DOT__rcv__DOT__baud_counter; - CData/*0:0*/ __Vdly__main__DOT__rcv__DOT__zero_baud_counter; - CData/*0:0*/ __Vdly__main__DOT__txv__DOT__r_busy; - CData/*7:0*/ __Vdly__main__DOT__txv__DOT__lcl_data; - CData/*0:0*/ __Vdly__main__DOT__txv__DOT__zero_baud_counter; - CData/*6:0*/ __Vdly__main__DOT__txv__DOT__baud_counter; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__r_wdt_reset; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__hx_stb; - CData/*2:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len; - CData/*1:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw; - CData/*2:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__cw_stb; - CData/*7:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr; - CData/*7:0*/ __Vdlyvdim0__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0; - CData/*0:0*/ __Vdlyvset__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0; - CData/*2:0*/ __Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb; - CData/*1:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state; - CData/*0:0*/ __Vdly__main__DOT__wbu_stb; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__last_ack; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__zero_acks; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__last_read_request; - CData/*6:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__dw_bits; - CData/*2:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len; - CData/*6:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wbu_tx_stb; - }; - struct { - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__cw_stb; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__cp_stb; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow; - CData/*5:0*/ __Vdlyvdim0__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0; - CData/*0:0*/ __Vdlyvset__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow; - CData/*6:0*/ __Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow; - CData/*0:0*/ __Vdlyvset__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow; - CData/*0:0*/ __Vdly__main__DOT__genbus__DOT__ofifo_empty_n; - CData/*7:0*/ __Vdly__o_gpio; - CData/*7:0*/ __Vdly__main__DOT__spioi__DOT__r_led; - CData/*7:0*/ __Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw; - CData/*7:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_owner; - CData/*0:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_dir; - CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness; - CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness; - CData/*4:0*/ __Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness; 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- VlWide<16>/*511:0*/ main__DOT__wbwide_bkram_idata; - IData/*31:0*/ main__DOT__wb32_wbdown_idata; - IData/*31:0*/ main__DOT__wb32_i2cdma_idata; - IData/*31:0*/ main__DOT__wb32_uart_idata; - IData/*31:0*/ main__DOT__wb32_emmc_idata; - IData/*31:0*/ main__DOT__wb32_fan_idata; - IData/*31:0*/ main__DOT__wb32_sdcard_idata; - IData/*31:0*/ main__DOT__wb32_ddr3_phy_idata; - IData/*31:0*/ main__DOT__wbu_data; - IData/*31:0*/ main__DOT__wbu_idata; - }; - struct { - IData/*31:0*/ main__DOT__wbu_zip_idata; - VlWide<6>/*191:0*/ main__DOT____Vcellout__wbwide_xbar__o_ssel; - VlWide<48>/*1535:0*/ main__DOT____Vcellout__wbwide_xbar__o_sdata; - VlWide<3>/*65:0*/ main__DOT____Vcellout__wbwide_xbar__o_saddr; - VlWide<64>/*2047:0*/ main__DOT____Vcellout__wbwide_xbar__o_mdata; - IData/*31:0*/ main__DOT__r_wb32_sio_data; - VlWide<12>/*383:0*/ main__DOT____Vcellout__wb32_xbar__o_sdata; - VlWide<3>/*95:0*/ main__DOT____Vcellout__wb32_xbar__o_saddr; - IData/*30:0*/ main__DOT____Vcellinp__emmcscopei____pinNumber4; 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- IData/*30:0*/ main__DOT__sdioscopei__DOT__imm_val; - IData/*31:0*/ main__DOT__sdioscopei__DOT__r_data; - IData/*31:0*/ main__DOT__sdioscopei__DOT__nxt_mem; - IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__index; - IData/*27:0*/ main__DOT__ddr3_controller_inst__DOT__instruction; - }; - struct { - VlWide<16>/*511:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_data; - VlWide<16>/*511:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned; - IData/*23:0*/ main__DOT__ddr3_controller_inst__DOT__aligned_cmd; - VlWide<16>/*511:0*/ main__DOT__ddr3_controller_inst__DOT__write_calib_data; - VlWide<16>/*511:0*/ main__DOT__ddr3_controller_inst__DOT__read_data_store; - VlWide<4>/*127:0*/ main__DOT__ddr3_controller_inst__DOT__write_pattern; - IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_addr; - IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__wb2_data; - IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result; - IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__nCK_to_cycles__Vstatic__result; - IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__delay; - IData/*31:0*/ main__DOT__ddr3_controller_inst__DOT__find_delay__Vstatic__k; - VlWide<16>/*511:0*/ main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data; - IData/*31:0*/ main__DOT__bkrami__DOT__WRITE_TO_MEMORY__DOT__ik; - IData/*31:0*/ main__DOT__clock_generator__DOT__r_delay; - IData/*31:0*/ main__DOT__clock_generator__DOT__times_three; - IData/*31:0*/ main__DOT__clock_generator__DOT__times_five; - IData/*31:0*/ main__DOT__clock_generator__DOT__times_seven; - IData/*27:0*/ main__DOT__u_i2cdma__DOT__r_baseaddr; - IData/*27:0*/ main__DOT__u_i2cdma__DOT__r_memlen; - IData/*27:0*/ main__DOT__u_i2cdma__DOT__current_addr; - IData/*31:0*/ main__DOT__u_i2cdma__DOT__next_baseaddr; - IData/*31:0*/ main__DOT__u_i2cdma__DOT__next_memlen; - IData/*26:0*/ main__DOT__u_fan__DOT__tach_count; - IData/*26:0*/ main__DOT__u_fan__DOT__tach_counter; - IData/*26:0*/ main__DOT__u_fan__DOT__tach_timer; - IData/*16:0*/ main__DOT__u_fan__DOT__trigger_counter; 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- IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b; - IData/*25:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg; - VlWide<4>/*127:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w; - VlWide<4>/*127:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w; - VlWide<4>/*127:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w; - VlWide<4>/*127:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg; - VlWide<8>/*255:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d; - VlWide<8>/*255:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d; - VlWide<8>/*255:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d; - VlWide<8>/*255:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - IData/*19:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg; - IData/*31:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data; - IData/*22:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout; - IData/*27:0*/ main__DOT__i2ci__DOT__pf_jump_addr; - }; - struct { - IData/*27:0*/ main__DOT__i2ci__DOT__pf_insn_addr; - IData/*27:0*/ main__DOT__i2ci__DOT__abort_address; - IData/*27:0*/ main__DOT__i2ci__DOT__jump_target; - IData/*31:0*/ main__DOT__i2ci__DOT__bus_read_data; - IData/*23:0*/ main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0; - VlWide<16>/*511:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__cache_word; - VlWide<16>/*511:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted; - VlWide<16>/*511:0*/ main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn; - VlWide<16>/*511:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data; - VlWide<16>/*511:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data; - VlWide<16>/*511:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data; - IData/*31:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_data; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ika; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ikb; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b; - IData/*25:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg; - VlWide<4>/*127:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w; - VlWide<4>/*127:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w; - VlWide<4>/*127:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w; - VlWide<4>/*127:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg; - VlWide<8>/*255:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d; - VlWide<8>/*255:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d; - VlWide<8>/*255:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d; - VlWide<8>/*255:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - IData/*19:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg; - IData/*31:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data; - IData/*22:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout; - IData/*31:0*/ main__DOT__swic__DOT__sys_data; - IData/*21:0*/ main__DOT__swic__DOT__cpu_addr; - IData/*31:0*/ main__DOT__swic__DOT__sys_idata; - IData/*31:0*/ main__DOT__swic__DOT__dbg_idata; - IData/*31:0*/ main__DOT__swic__DOT__dbg_odata; - IData/*31:0*/ main__DOT__swic__DOT__cmd_wdata; - IData/*21:0*/ main__DOT__swic__DOT__r_wdbus_data; - IData/*31:0*/ main__DOT__swic__DOT__pic_data; - IData/*31:0*/ main__DOT__swic__DOT__dmac_data; - IData/*31:0*/ main__DOT__swic__DOT__ctri_data; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__cpu_idata; - IData/*31:0*/ main__DOT__swic__DOT__dbg_cpu_status; - IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data; - IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data; - IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data; - IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data; - IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data; - IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data; - IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data; - IData/*31:0*/ main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data; - }; - struct { - IData/*30:0*/ main__DOT__swic__DOT__u_watchdog__DOT__r_value; - IData/*30:0*/ main__DOT__swic__DOT__u_timer_a__DOT__r_value; - IData/*30:0*/ main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_interval_count; - IData/*30:0*/ main__DOT__swic__DOT__u_timer_b__DOT__r_value; - IData/*30:0*/ main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_interval_count; - IData/*30:0*/ main__DOT__swic__DOT__u_timer_c__DOT__r_value; - IData/*30:0*/ main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_interval_count; - IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__r_counter; - IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__int_when; - IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__new_when; - IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__till_wb; - IData/*31:0*/ main__DOT__swic__DOT__u_jiffies__DOT__till_when; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_request_address; - IData/*21:0*/ main__DOT__swic__DOT__thecpu__DOT__pf_addr; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_data; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_result; - IData/*21:0*/ main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v; - IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv; - IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_val; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc; - IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim_immv; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_lock_pc; - IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim_immv; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_addr; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks; - IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim_immv; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword; - IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I; - IData/*22:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_brev_result; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc; - IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__pc_tag_lookup; - IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_tag_lookup; - IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup; - IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache; - IData/*27:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted; - }; - struct { - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__ik; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata; - IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag; - IData/*21:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr; - IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag; - IData/*18:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted; - IData/*31:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data; - IData/*31:0*/ main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_data; - IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src; - IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst; - IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length; - IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr; - IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr; - IData/*21:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr; - IData/*21:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data; - VlWide<17>/*519:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data; - IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src; - IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst; - IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len; - IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen; - IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg; - IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length; - IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr; - IData/*27:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg; - VlWide<32>/*1023:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg; - IData/*31:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__ik; - IData/*28:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr; - VlWide<32>/*1023:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data; - VlWide<16>/*511:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data; - VlWide<4>/*127:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel; - VlWide<4>/*127:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel; - IData/*31:0*/ main__DOT__i2cscopei__DOT__o_bus_data; - IData/*19:0*/ main__DOT__i2cscopei__DOT__br_holdoff; - IData/*19:0*/ main__DOT__i2cscopei__DOT__holdoff_counter; - IData/*30:0*/ main__DOT__i2cscopei__DOT__ck_addr; - IData/*30:0*/ main__DOT__i2cscopei__DOT__qd_data; - IData/*30:0*/ main__DOT__i2cscopei__DOT__lst_val; - IData/*30:0*/ main__DOT__i2cscopei__DOT__imm_val; - IData/*31:0*/ main__DOT__i2cscopei__DOT__r_data; - IData/*31:0*/ main__DOT__i2cscopei__DOT__nxt_mem; - IData/*18:0*/ main__DOT__genbus__DOT__r_wdt_timer; - IData/*31:0*/ main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k; - IData/*24:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr; - IData/*31:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr; - IData/*31:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cword; - IData/*31:0*/ main__DOT__genbus__DOT__runwb__DOT__wide_addr; - IData/*29:0*/ main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word; - IData/*31:0*/ main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k; - IData/*21:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter; - IData/*31:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__cword; - IData/*31:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k; - IData/*24:0*/ main__DOT__spioi__DOT__knightrider__DOT__led_ctr; - IData/*21:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr; - VlWide<16>/*511:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data; - VlWide<16>/*511:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data; - }; - struct { - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout; - IData/*19:0*/ __Vdly__main__DOT__emmcscopei__DOT__holdoff_counter; - IData/*30:0*/ __Vdly__main__DOT__emmcscopei__DOT__ck_addr; - IData/*31:0*/ __Vdlyvval__main__DOT__emmcscopei__DOT__mem__v0; - IData/*19:0*/ __Vdly__main__DOT__sdioscopei__DOT__holdoff_counter; - IData/*30:0*/ __Vdly__main__DOT__sdioscopei__DOT__ck_addr; - IData/*31:0*/ __Vdlyvval__main__DOT__sdioscopei__DOT__mem__v0; - IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v0; - IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v1; - IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v2; - IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v3; - IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v4; - IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v5; - IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v6; - IData/*21:0*/ __Vdly__main__DOT__wbwide_i2cdma_addr; - IData/*26:0*/ __Vdly__main__DOT__u_fan__DOT__tach_counter; - IData/*26:0*/ __Vdly__main__DOT__u_fan__DOT__tach_timer; - IData/*16:0*/ __Vdly__main__DOT__u_fan__DOT__trigger_counter; - IData/*23:0*/ __Vdly__main__DOT__u_fan__DOT__temp_tmp; - IData/*25:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter; - VlWide<4>/*127:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg; - VlWide<8>/*255:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg; - IData/*31:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - IData/*19:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg; - IData/*22:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout; - IData/*27:0*/ __Vdly__main__DOT__i2ci__DOT__pf_jump_addr; - IData/*21:0*/ __Vdly__main__DOT__wbwide_i2cm_addr; - VlWide<16>/*511:0*/ __Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn; - IData/*27:0*/ __Vdly__main__DOT__i2ci__DOT__pf_insn_addr; - IData/*25:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter; - VlWide<4>/*127:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg; - VlWide<8>/*255:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg; - IData/*31:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - IData/*19:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg; - IData/*22:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout; - IData/*30:0*/ __Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_value; - IData/*30:0*/ __Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value; - IData/*30:0*/ __Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value; - IData/*30:0*/ __Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__u_jiffies__DOT__r_counter; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__u_jiffies__DOT__int_when; - IData/*21:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_addr; - VlWide<16>/*511:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data; - IData/*27:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length; - IData/*27:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr; - IData/*27:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr; - VlWide<32>/*1023:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg; - VlWide<17>/*519:0*/ __Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0; - VlWide<16>/*511:0*/ __Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg; - IData/*19:0*/ __Vdly__main__DOT__i2cscopei__DOT__holdoff_counter; - IData/*30:0*/ __Vdly__main__DOT__i2cscopei__DOT__ck_addr; - IData/*31:0*/ __Vdlyvval__main__DOT__i2cscopei__DOT__mem__v0; - IData/*18:0*/ __Vdly__main__DOT__genbus__DOT__r_wdt_timer; - IData/*31:0*/ __Vdlyvval__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0; - IData/*31:0*/ __Vdly__main__DOT__genbus__DOT__runwb__DOT__wide_addr; - }; - struct { - IData/*29:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word; - IData/*21:0*/ __Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter; - IData/*31:0*/ __Vdlyvval__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0; - IData/*31:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks; - IData/*27:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor; - IData/*31:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result; - IData/*21:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr; - IData/*18:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag; - IData/*21:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr; - IData/*18:0*/ __Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0; - IData/*31:0*/ __VstlIterCount; - IData/*31:0*/ __VicoIterCount; - IData/*31:0*/ __VactIterCount; - VL_IN64(i_ddr3_controller_iserdes_dqs,63,0); - VL_IN64(i_ddr3_controller_iserdes_bitslip_reference,63,0); - VL_OUT64(o_ddr3_controller_dm,63,0); - QData/*63:0*/ main__DOT__wbwide_i2cdma_sel; - QData/*47:0*/ main__DOT____Vcellout__wb32_xbar__o_ssel; - QData/*63:0*/ main__DOT____Vcellout__wbu_xbar__o_sdata; - QData/*53:0*/ main__DOT____Vcellout__wbu_xbar__o_saddr; - QData/*44:0*/ main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data; - QData/*44:0*/ main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data; - QData/*36:0*/ main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data; - QData/*44:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data; - QData/*63:0*/ main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data; - QData/*63:0*/ main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data; - QData/*36:0*/ main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data; - QData/*63:0*/ main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data; - QData/*63:0*/ main__DOT__ddr3_controller_inst__DOT__stage1_dm; - QData/*63:0*/ main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned; - QData/*39:0*/ main__DOT__ddr3_controller_inst__DOT__dqs_store; - QData/*63:0*/ main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel; - QData/*47:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg; - QData/*39:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg; - QData/*63:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w; - QData/*63:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w; - QData/*63:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w; - QData/*63:0*/ main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg; - QData/*63:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel; - QData/*63:0*/ main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel; - QData/*47:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg; - QData/*39:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg; - QData/*63:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w; - QData/*63:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w; - QData/*63:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w; - QData/*63:0*/ main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg; - QData/*32:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result; - QData/*32:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_asr_result; - QData/*32:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result; - QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result; - QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_smpy_result; - QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_umpy_result; - QData/*62:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend; - QData/*32:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff; - QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel; - QData/*63:0*/ main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel; - QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel; - QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel; - QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel; - QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel; - QData/*63:0*/ main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel; - QData/*35:0*/ main__DOT__genbus__DOT__in_word; - }; - struct { - QData/*35:0*/ main__DOT__genbus__DOT__ififo_codword; - QData/*35:0*/ main__DOT__genbus__DOT__exec_word; - QData/*35:0*/ main__DOT__genbus__DOT__ofifo_codword; - QData/*35:0*/ main__DOT__genbus__DOT__getinput__DOT__cw_word; - QData/*35:0*/ main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg; - QData/*35:0*/ main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word; - QData/*35:0*/ main__DOT__genbus__DOT__wroutput__DOT__cw_codword; - QData/*35:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__a_addrword; - QData/*35:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word; - QData/*35:0*/ main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword; - QData/*63:0*/ main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel; - QData/*63:0*/ __Vdly__main__DOT__wbwide_i2cdma_sel; - QData/*47:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg; - QData/*39:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg; - QData/*63:0*/ __Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg; - QData/*47:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg; - QData/*39:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg; - QData/*63:0*/ __Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg; - QData/*35:0*/ __Vdlyvval__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0; - QData/*35:0*/ __Vdlyvval__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0; - QData/*62:0*/ __Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend; - VlUnpacked main__DOT__wbwide_xbar__DOT__request; - VlUnpacked main__DOT__wbwide_xbar__DOT__requested; - VlUnpacked main__DOT__wbwide_xbar__DOT__grant; - VlUnpacked main__DOT__wbwide_xbar__DOT__w_mpending; - VlUnpacked main__DOT__wbwide_xbar__DOT__mindex; - VlUnpacked main__DOT__wbwide_xbar__DOT__sindex; - VlUnpacked main__DOT__wbwide_xbar__DOT__m_addr; - VlUnpacked/*511:0*/, 4> main__DOT__wbwide_xbar__DOT__m_data; - VlUnpacked main__DOT__wbwide_xbar__DOT__m_sel; - VlUnpacked/*511:0*/, 4> main__DOT__wbwide_xbar__DOT__s_data; - VlUnpacked main__DOT__wb32_xbar__DOT__request; - VlUnpacked main__DOT__wb32_xbar__DOT__requested; - VlUnpacked main__DOT__wb32_xbar__DOT__grant; - VlUnpacked main__DOT__wb32_xbar__DOT__w_mpending; - VlUnpacked main__DOT__wb32_xbar__DOT__mindex; - VlUnpacked main__DOT__wb32_xbar__DOT__sindex; - VlUnpacked main__DOT__wb32_xbar__DOT__m_addr; - VlUnpacked main__DOT__wb32_xbar__DOT__m_data; - VlUnpacked main__DOT__wb32_xbar__DOT__m_sel; - VlUnpacked main__DOT__wb32_xbar__DOT__s_data; - VlUnpacked main__DOT__wbu_xbar__DOT__request; - VlUnpacked main__DOT__wbu_xbar__DOT__requested; - VlUnpacked main__DOT__wbu_xbar__DOT__grant; - VlUnpacked main__DOT__wbu_xbar__DOT__w_mpending; - VlUnpacked main__DOT__wbu_xbar__DOT__mindex; - VlUnpacked main__DOT__wbu_xbar__DOT__sindex; - VlUnpacked main__DOT__wbu_xbar__DOT__m_addr; - VlUnpacked main__DOT__wbu_xbar__DOT__m_data; - VlUnpacked main__DOT__wbu_xbar__DOT__m_sel; - VlUnpacked main__DOT__wbu_xbar__DOT__s_data; - VlUnpacked main__DOT__emmcscopei__DOT__mem; - VlUnpacked main__DOT__sdioscopei__DOT__mem; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__bank_active_row_q; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__bank_active_row_d; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__stage2_dm; - VlUnpacked/*511:0*/, 2> main__DOT__ddr3_controller_inst__DOT__stage2_data; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__unaligned_data; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__unaligned_dm; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q; - }; - struct { - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__cmd_d; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__added_read_pipe; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__delay_read_pipe; - VlUnpacked/*511:0*/, 2> main__DOT__ddr3_controller_inst__DOT__o_wb_data_q; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__data_start_index; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein; - VlUnpacked main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein; - VlUnpacked/*511:0*/, 16384> main__DOT__bkrami__DOT__mem; - VlUnpacked main__DOT__clock_generator__DOT__counter; - VlUnpacked main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a; - VlUnpacked main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b; - VlUnpacked main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem; - VlUnpacked main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a; - VlUnpacked main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b; - VlUnpacked main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat; - VlUnpacked main__DOT__console__DOT__rxfifo__DOT__fifo; - VlUnpacked main__DOT__console__DOT__txfifo__DOT__fifo; - VlUnpacked main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset; - VlUnpacked/*511:0*/, 64> main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache; - VlUnpacked main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags; - VlUnpacked main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags; - VlUnpacked/*511:0*/, 64> main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem; - VlUnpacked main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data; - VlUnpacked/*519:0*/, 16> main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem; - VlUnpacked main__DOT__i2cscopei__DOT__mem; - VlUnpacked main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__remap; - VlUnpacked main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl; - VlUnpacked main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__remap; - VlUnpacked main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl; - VlUnpacked main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo; - VlUnpacked main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo; - VlUnpacked main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem; - VlUnpacked __Vm_traceActivity; - }; - VlTriggerVec<1> __VstlTriggered; - VlTriggerVec<1> __VicoTriggered; - VlTriggerVec<9> __VactTriggered; - VlTriggerVec<9> __VnbaTriggered; - - // INTERNAL VARIABLES - Vmain__Syms* const vlSymsp; - - // CONSTRUCTORS - Vmain___024root(Vmain__Syms* symsp, const char* v__name); - ~Vmain___024root(); - VL_UNCOPYABLE(Vmain___024root); - - // INTERNAL METHODS - void __Vconfigure(bool first); -}; - - -#endif // guard diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__0.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__0.cpp deleted file mode 100644 index fd92356..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__0.cpp +++ /dev/null @@ -1,11041 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -VL_INLINE_OPT void Vmain___024root___ico_sequent__TOP__0(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___ico_sequent__TOP__0\n"); ); - // Init - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0; - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 = 0; - // Body - vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n - = (1U & (~ (IData)(vlSelf->i_reset))); - if (vlSelf->i_clk) { - vlSelf->o_sdcard_clk = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out) - >> 1U)); - vlSelf->o_sdcard_cmd = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - } else { - vlSelf->o_sdcard_clk = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out)); - vlSelf->o_sdcard_cmd = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out)); - } - vlSelf->cpu_sim_stall = (1U & ((~ (IData)(vlSelf->cpu_sim_cyc)) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb))); - vlSelf->cpu_sim_ack = ((IData)(vlSelf->cpu_sim_cyc) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)); - vlSelf->main__DOT____Vcellinp__swic__i_reset = - ((IData)(vlSelf->i_cpu_reset) | (IData)(vlSelf->i_reset)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc - = (IData)((((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - >> 1U) | (IData)(vlSelf->cpu_sim_cyc))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN - = (1U & (~ ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset)); - vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted)); - vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN - = (1U & (~ ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual)))); - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset)); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)) - | (IData)(vlSelf->i_reset))); - if (vlSelf->cpu_sim_cyc) { - vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb - = (1U & (IData)(vlSelf->cpu_sim_stb)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_we - = (1U & (IData)(vlSelf->cpu_sim_we)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr - = (0x7fU & (IData)(vlSelf->cpu_sim_addr)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_data - = vlSelf->cpu_sim_data; - } else { - vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb - = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - >> 1U)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_we - = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe) - >> 1U)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr - = (0x7fU & (IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - >> 0x1bU))); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_data - = (IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - >> 0x20U)); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v) - | (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - ? (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc) - : ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v) - | (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - ? (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc) - : ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 1U)))); - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]))); - if ((1U & (((~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]]) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]))); - if ((1U & (((~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]] >> 1U)) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]))); - if ((1U & (((~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]] >> 2U)) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U])))); - if ((((~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]] : 0U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]))) & ( - (0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]] : 0U) >> 1U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 1U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]] : 0U) >> 2U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 2U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]] : 0U) >> 3U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 3U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]] : 0U) >> 4U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 4U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]] : 0U) >> 5U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 5U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]] : 0U) >> 6U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 6U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]] : 0U) >> 7U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 7U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]] : 0U) >> 8U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 8U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]] : 0U) >> 9U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 9U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]] : 0U) >> 0xaU)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 0xaU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]] : 0U) >> 0xbU)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 0xbU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U])))); - if ((((~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wbu_xbar__DOT__request - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]] : 0U)) & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]))) & ( - (0U - >= - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) - & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty) - >> - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U])))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant)))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wbu_xbar__DOT__request - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]] : 0U) >> 1U)) & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]))) - & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U])))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant) - >> 1U)))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 0U; - } - if (vlSelf->i_reset) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request - = ((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U))) & ((1U == (3U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 6U))) - | (IData)(((0U - == - (0x2bc0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U))))); - if ((((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & ((IData)(((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U) & (0x200U == (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])))) - | ((~ (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U))) & (2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type)))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - if ((((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xbU))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request - = ((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U))) & ((1U == (3U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 6U))) - | (IData)(((0U - == - (0x2bc0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))))); - if ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & ((IData)(((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U) & (0x200U == (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])))) - | ((~ (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))) & (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - if ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xbU))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4 - = (((IData)(vlSelf->o_emmc_clk) << 0x19U) | - (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - << 0x17U) | (((IData)(vlSelf->o_emmc_cmd) - << 0x16U) | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0) - ? (IData)(vlSelf->o_emmc_cmd) - : (IData)(vlSelf->i_emmc_cmd)) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - << 8U) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - ? (IData)(vlSelf->o_emmc_dat) - : (IData)(vlSelf->i_emmc_dat))))))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request - = ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (0x3000000ULL == (0x3000000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x40U == (0xc0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))) - | (0U == (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 6U))))) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xbU) - | ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x240U - == - (0x3c0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))))); - if (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request - = ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (0x300000000ULL == (0x300000000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x40U == (0xc0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]))) - | (0U == (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 6U))))) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xbU) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x240U - == - (0x3c0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]))))); - if (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbu_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0 - = (((IData)(vlSelf->main__DOT__i2ci__DOT__r_wait) - << 0x17U) | (((IData)(vlSelf->main__DOT__i2ci__DOT__soft_halt_request) - << 0x16U) | (((IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted) - << 0x15U) | - (((IData)(vlSelf->main__DOT__i2ci__DOT__r_err) - << 0x14U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - << 0x13U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - << 0x12U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle) - << 0x10U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl) - << 0xfU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda) - << 0xeU) - | (((IData)(vlSelf->i_i2c_scl) - << 0xdU) - | (((IData)(vlSelf->i_i2c_sda) - << 0xcU) - | (IData)(vlSelf->main__DOT__i2ci__DOT__insn))))))))))))); - vlSelf->main__DOT__wbu_xbar__DOT__s_stall = (0xcU - | ((0xfffffffeU - & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - & (((IData)(vlSelf->cpu_sim_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - & (IData)(vlSelf->main__DOT__wbu_wbu_arbiter_stall)))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_zip_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce)) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt) - & ((~ (IData)((0U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal) - | (IData)(vlSelf->main__DOT__swic__DOT__cpu_break)))))))))))))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z) - ? (IData)(vlSelf->i_sdcard_cmd) : (IData)(vlSelf->o_sdcard_cmd)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 3U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 2U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 1U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z) - ? (IData)(vlSelf->i_sdcard_dat) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->o_sdcard_dat = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin) - << 3U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin) - << 2U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin) - << 1U) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin)))); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xaU)); - if ((IData)((0x240U == (0x3c0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request = 0U; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request = 0U; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xaU)); - if ((IData)((0x240U == (0x3c0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request = 0U; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request = 0U; - } - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbu_stb) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4 - = ((0x40000000U & ((IData)(vlSelf->main__DOT__i2ci__DOT__ovw_data) - << 0x15U)) | (((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_abort) - << 0x1dU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_stretch) - << 0x1cU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_insn) - << 0x18U) - | vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0)))); - vlSelf->main__DOT__wbu_xbar__DOT__m_stall = (1U - & ((vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U] - >> 2U) - | (((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - & ((2U - >= - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U]) - & (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] - >> - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U]))) - ? - ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mfull) - | ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U])) - : (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb)))); - if (vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) { - vlSelf->main__DOT__wbu_xbar__DOT__m_stall = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_i2cdma_stb) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__wbwide_zip_stb))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__wb32_wbdown_stb))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled) - 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& ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - == (0xeU | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))))))); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbu_cyc)); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall - = ((IData)(vlSelf->main__DOT__wbu_cyc) & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stall)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb) - 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<< 1U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xffbU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 2U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 3U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xff7U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 3U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 4U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xfefU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 4U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 5U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xfdfU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 5U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - 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<< 7U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 8U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xeffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 8U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 9U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xdffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 9U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 0xaU)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xbffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 0xaU)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 0xbU)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0x7ffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 0xbU)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest))); - 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vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc - = ((0x20U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - ? 5U : ((0x40U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - ? 6U : 7U)); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) { - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rA)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 4U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 4U; - } - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc - = ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 5U) & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB)) - ? 4U : 5U); - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc = 6U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 0U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 2U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 3U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 4U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 5U; - } -} - -void Vmain___024root___eval_ico(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_ico\n"); ); - // Body - if ((1ULL & vlSelf->__VicoTriggered.word(0U))) { - Vmain___024root___ico_sequent__TOP__0(vlSelf); - vlSelf->__Vm_traceActivity[1U] = 1U; - } -} - -void Vmain___024root___eval_act(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_act\n"); ); -} - -extern const VlUnpacked Vmain__ConstPool__TABLE_h7c414883_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h9e411d43_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h5b51c6c5_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h02e0efbb_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h809a37d6_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_heed7669e_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_hdf55cab5_0; -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h88ad91a4_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h5f0541c3_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_hd397e023_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h9becc847_0; - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__0(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__0\n"); ); - // Init - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__Vfuncout = 0; - QData/*39:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__Vfuncout = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__fill = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__Vfuncout = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__fill = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__i_bit = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__Vfuncout = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__fill = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__prior = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit = 0; - CData/*2:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__set; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__set = 0; - CData/*2:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__set; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__set = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__Vfuncout = 0; - QData/*39:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__Vfuncout = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__fill = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__Vfuncout = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__fill = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__i_bit = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__Vfuncout = 0; - CData/*6:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__fill = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__prior = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit = 0; - CData/*2:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__set; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__set = 0; - CData/*2:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__set; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__set = 0; - SData/*10:0*/ __Vtableidx3; - __Vtableidx3 = 0; - CData/*5:0*/ __Vtableidx4; - __Vtableidx4 = 0; - SData/*10:0*/ __Vtableidx6; - __Vtableidx6 = 0; - CData/*5:0*/ __Vtableidx11; - __Vtableidx11 = 0; - CData/*6:0*/ __Vtableidx12; - __Vtableidx12 = 0; - CData/*6:0*/ __Vtableidx13; - __Vtableidx13 = 0; - VlWide<16>/*511:0*/ __Vtemp_h211bbf5b__0; - VlWide<32>/*1023:0*/ __Vtemp_hc94fac31__0; - VlWide<32>/*1023:0*/ __Vtemp_hfa8722fc__0; - VlWide<32>/*1023:0*/ __Vtemp_hc94fac31__1; - VlWide<32>/*1023:0*/ __Vtemp_hb4dafc67__0; - VlWide<16>/*511:0*/ __Vtemp_h04488e48__0; - VlWide<16>/*511:0*/ __Vtemp_h0448bebe__0; - VlWide<16>/*511:0*/ __Vtemp_h0448985a__0; - VlWide<16>/*511:0*/ __Vtemp_h434d0da1__0; - VlWide<16>/*511:0*/ __Vtemp_hfc2bf96b__0; - VlWide<16>/*511:0*/ __Vtemp_h02cc08c7__0; - // Body - vlSelf->__Vdly__main__DOT__u_fan__DOT__pwm_counter - = vlSelf->main__DOT__u_fan__DOT__pwm_counter; - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe - = vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe; - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw - = vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw; - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr; - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr; - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter - = vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter; - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchbus__DOT__r_value - = vlSelf->main__DOT__swic__DOT__u_watchbus__DOT__r_value; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe; - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill; - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr; - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness; - vlSelf->__Vdly__main__DOT__rcv__DOT__data_reg = vlSelf->main__DOT__rcv__DOT__data_reg; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_dir - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_dir; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_owner - = vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner; - vlSelf->__Vdly__main__DOT__txv__DOT__baud_counter - = vlSelf->main__DOT__txv__DOT__baud_counter; - vlSelf->__Vdly__main__DOT__txv__DOT__zero_baud_counter - = vlSelf->main__DOT__txv__DOT__zero_baud_counter; - vlSelf->__Vdly__main__DOT__txv__DOT__r_busy = vlSelf->main__DOT__txv__DOT__r_busy; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0 = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr - = vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr - = vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr; - vlSelf->__Vdlyvset__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0 = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__wdbus_int - = vlSelf->main__DOT__swic__DOT__wdbus_int; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len; - vlSelf->__Vdly__main__DOT__rcv__DOT__chg_counter - = vlSelf->main__DOT__rcv__DOT__chg_counter; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__raddr - = vlSelf->main__DOT__i2cscopei__DOT__raddr; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__raddr - = vlSelf->main__DOT__sdioscopei__DOT__raddr; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__raddr - = vlSelf->main__DOT__emmcscopei__DOT__raddr; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stop_pipe - = vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stop_pipe - = vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stop_pipe - = vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n - = vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n; - vlSelf->__Vdly__main__DOT__genbus__DOT__ofifo_empty_n - = vlSelf->main__DOT__genbus__DOT__ofifo_empty_n; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__holdoff_counter - = vlSelf->main__DOT__i2cscopei__DOT__holdoff_counter; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__holdoff_counter - = vlSelf->main__DOT__sdioscopei__DOT__holdoff_counter; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__holdoff_counter - = vlSelf->main__DOT__emmcscopei__DOT__holdoff_counter; - vlSelf->__Vdly__main__DOT__rcv__DOT__zero_baud_counter - = vlSelf->main__DOT__rcv__DOT__zero_baud_counter; - vlSelf->__Vdly__main__DOT__rcv__DOT__baud_counter - = vlSelf->main__DOT__rcv__DOT__baud_counter; - vlSelf->__Vdly__main__DOT__rcv__DOT__state = vlSelf->main__DOT__rcv__DOT__state; - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read_ack - = vlSelf->main__DOT__swic__DOT__cmd_read_ack; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__ck_addr - = vlSelf->main__DOT__i2cscopei__DOT__ck_addr; - vlSelf->__Vdly__main__DOT__u_fan__DOT__temp_tmp - = vlSelf->main__DOT__u_fan__DOT__temp_tmp; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__ck_addr - = vlSelf->main__DOT__emmcscopei__DOT__ck_addr; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__ck_addr - = vlSelf->main__DOT__sdioscopei__DOT__ck_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data - = vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data; - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data - = vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data; - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data - = vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit; - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read - = vlSelf->main__DOT__swic__DOT__cmd_read; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_write - = vlSelf->main__DOT__i2cscopei__DOT__dr_force_write; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_inhibit - = vlSelf->main__DOT__i2cscopei__DOT__dr_force_inhibit; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_write - = vlSelf->main__DOT__sdioscopei__DOT__dr_force_write; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_inhibit - = vlSelf->main__DOT__sdioscopei__DOT__dr_force_inhibit; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_write - = vlSelf->main__DOT__emmcscopei__DOT__dr_force_write; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_inhibit - = vlSelf->main__DOT__emmcscopei__DOT__dr_force_inhibit; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present; - vlSelf->__Vdly__main__DOT__u_fan__DOT__trigger_counter - = vlSelf->main__DOT__u_fan__DOT__trigger_counter; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter; - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe - = vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__hx_stb - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight; - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_timer - = vlSelf->main__DOT__u_fan__DOT__tach_timer; - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_counter - = vlSelf->main__DOT__u_fan__DOT__tach_counter; - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_reset - = vlSelf->main__DOT__u_fan__DOT__tach_reset; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__cw_stb - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb; - vlSelf->__Vdly__main__DOT__genbus__DOT__wbu_tx_stb - = vlSelf->main__DOT__genbus__DOT__wbu_tx_stb; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__waddr - = vlSelf->main__DOT__i2cscopei__DOT__waddr; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_primed - = vlSelf->main__DOT__i2cscopei__DOT__dr_primed; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state - = vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state; - vlSelf->__Vdly__main__DOT__wbu_stb = vlSelf->main__DOT__wbu_stb; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__waddr - = vlSelf->main__DOT__emmcscopei__DOT__waddr; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__waddr - = vlSelf->main__DOT__sdioscopei__DOT__waddr; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_primed - = vlSelf->main__DOT__emmcscopei__DOT__dr_primed; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_primed - = vlSelf->main__DOT__sdioscopei__DOT__dr_primed; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow - = vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow - = vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding; - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0 = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0 = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cp_stb - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr; - vlSelf->__Vdly__main__DOT__txv__DOT__lcl_data = vlSelf->main__DOT__txv__DOT__lcl_data; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len; - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid - = vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wide_addr - = vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0 = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__zero_acks - = vlSelf->main__DOT__genbus__DOT__runwb__DOT__zero_acks; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_acks_needed - = vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cw_stb - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw; - vlSelf->__Vdlyvset__main__DOT__i2cscopei__DOT__mem__v0 = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state; - vlSelf->__Vdlyvset__main__DOT__emmcscopei__DOT__mem__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__sdioscopei__DOT__mem__v0 = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - vlSelf->__Vdly__main__DOT__swic__DOT__dbg_stb = vlSelf->main__DOT__swic__DOT__dbg_stb; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0 = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v2 = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_ack - = vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_ack; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_read_request - = vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_read_request; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len - = vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len; - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_timer - = vlSelf->main__DOT__genbus__DOT__r_wdt_timer; - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_reset - = vlSelf->main__DOT__genbus__DOT__r_wdt_reset; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda; - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0 = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0 = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__dir - = vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits - = vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg - = vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg; - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = vlSelf->main__DOT__i2ci__DOT__w_sda; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_addr - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state - = vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state; - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0 = 0U; - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__mnearfull - = vlSelf->main__DOT__wbu_xbar__DOT__mnearfull; - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow - = vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow; - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow - = vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v2 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v3 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v4 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v5 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v6 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v7 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v8 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v9 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v10 = 0U; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v11 = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable - = vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable; - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable - = vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable; - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state - = vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state; - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state - = vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state; - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_write - = vlSelf->main__DOT__swic__DOT__cmd_write; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__dw_bits - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid; - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v2 = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb; - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc; - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err; - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant - = vlSelf->main__DOT__wbu_xbar__DOT__sgrant; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift; - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err; - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first; - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data - = vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap; - vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__r_counter - = vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks; - vlSelf->__Vdly__main__DOT__swic__DOT__wdt_reset - = vlSelf->main__DOT__swic__DOT__wdt_reset; - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_clear_cache - = vlSelf->main__DOT__swic__DOT__cmd_clear_cache; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config - = vlSelf->main__DOT__i2cscopei__DOT__br_config; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config - = vlSelf->main__DOT__sdioscopei__DOT__br_config; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config - = vlSelf->main__DOT__emmcscopei__DOT__br_config; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stopped - = vlSelf->main__DOT__i2cscopei__DOT__dr_stopped; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stopped - = vlSelf->main__DOT__sdioscopei__DOT__dr_stopped; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stopped - = vlSelf->main__DOT__emmcscopei__DOT__dr_stopped; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag; - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_zero - = vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_zero; - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_value - = vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero - = vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero - = vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero - = vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_zero; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe; - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data - = vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data; - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data - = vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data; - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data - = vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value - = vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value - = vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value - = vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount; - vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckcount - = vlSelf->main__DOT__i2ci__DOT__i2c_ckcount; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge; - vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckedge - = vlSelf->main__DOT__i2ci__DOT__i2c_ckedge; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last; - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_addr - = vlSelf->main__DOT__u_fan__DOT__mem_addr; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_illegal - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal; - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data - = vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data; - vlSelf->__Vdly__main__DOT__spioi__DOT__r_led = vlSelf->main__DOT__spioi__DOT__r_led; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v2 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v3 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v4 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v5 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v6 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v7 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v8 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v9 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v10 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v11 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v12 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v13 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v14 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v15 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v16 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v17 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v18 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v19 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v20 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v21 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v22 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v23 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v24 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v25 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v26 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v27 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v28 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v29 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v30 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v31 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v32 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v33 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v34 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v35 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v36 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v37 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v38 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v39 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v40 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v41 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v42 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v43 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v44 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v45 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v46 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v47 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v48 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v49 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v50 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v51 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v52 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v53 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v54 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v55 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v56 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v57 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v58 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v59 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v60 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v61 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v62 = 0U; - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v63 = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_cyc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc; - vlSelf->__Vdlyvset__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0 = 0U; - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc; - vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__int_when - = vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_when; - vlSelf->__Vdly__o_gpio = vlSelf->o_gpio; - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__rd_addr - = vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr; - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__rd_addr - = vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr; - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__r_fill - = vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill; - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__r_fill - = vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill; - vlSelf->__Vdlyvset__main__DOT__console__DOT__rxfifo__DOT__fifo__v0 = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga - = vlSelf->main__DOT__u_fan__DOT__ctl_fpga; - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys - = vlSelf->main__DOT__u_fan__DOT__ctl_sys; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending; - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__bus_err - = vlSelf->main__DOT__u_i2cdma__DOT__bus_err; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU]; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0 = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU]; - vlSelf->__Vdlyvset__main__DOT__console__DOT__txfifo__DOT__fifo__v0 = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__inflight - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight; - vlSelf->__Vdly__main__DOT__u_fan__DOT__ign_mem_cyc - = vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc; - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_stb - = vlSelf->main__DOT__u_fan__DOT__mem_stb; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 = 0U; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 = 0U; - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted; - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted - = vlSelf->main__DOT__i2ci__DOT__r_halted; - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow - = vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow; - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow - = vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow; - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_underflow - = vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb; - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_insn_addr - = vlSelf->main__DOT__i2ci__DOT__pf_insn_addr; - vlSelf->__Vdly__main__DOT__wbwide_i2cm_addr = vlSelf->main__DOT__wbwide_i2cm_addr; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__rx_en = vlSelf->main__DOT__u_emmc__DOT__rx_en; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__rx_en - = vlSelf->main__DOT__u_sdcard__DOT__rx_en; - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_underflow - = vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow; - vlSelf->__Vdly__main__DOT__i2ci__DOT__imm_cycle - = vlSelf->main__DOT__i2ci__DOT__imm_cycle; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy - = vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[1U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[1U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[2U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[2U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[3U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[3U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[4U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[4U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[5U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[5U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[6U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[6U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[7U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[7U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[8U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[8U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[9U] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[9U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xaU] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xaU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xbU] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xbU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xcU] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xcU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xdU] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xdU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xeU] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xeU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU] - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid; - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_valid - = vlSelf->main__DOT__i2ci__DOT__pf_valid; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_illegal - = vlSelf->main__DOT__i2ci__DOT__pf_illegal; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout; - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_cyc = vlSelf->main__DOT__wbwide_i2cdma_cyc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg; - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_jump_addr - = vlSelf->main__DOT__i2ci__DOT__pf_jump_addr; - vlSelf->__Vdly__main__DOT__wbwide_i2cm_stb = vlSelf->main__DOT__wbwide_i2cm_stb; - vlSelf->__Vdly__main__DOT__wbwide_i2cm_cyc = vlSelf->main__DOT__wbwide_i2cm_cyc; - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending; - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending; - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending; - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__subaddr - = vlSelf->main__DOT__u_i2cdma__DOT__subaddr; - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_sel = vlSelf->main__DOT__wbwide_i2cdma_sel; - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_addr = vlSelf->main__DOT__wbwide_i2cdma_addr; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr; - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__r_overflow - = vlSelf->main__DOT__u_i2cdma__DOT__r_overflow; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en; - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__mnearfull - = vlSelf->main__DOT__wb32_xbar__DOT__mnearfull; - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc; - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts; - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0U; - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done; - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = vlSelf->main__DOT__wbwide_xbar__DOT__sgrant; - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb; - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = vlSelf->main__DOT__wb32_xbar__DOT__sgrant; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ika = 4U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ikb = 4U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ika = 4U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ikb = 4U; - vlSelf->main__DOT__wbu_xbar__DOT__iN = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__iN = 4U; - vlSelf->main__DOT__wb32_xbar__DOT__iN = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__iM = vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U]; - vlSelf->main__DOT__wbu_xbar__DOT__iM = vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__iM = vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]; - if (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_wstb) { - vlSelf->main__DOT__bkrami__DOT__WRITE_TO_MEMORY__DOT__ik = 0x40U; - if ((1U & (IData)(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v0 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v0 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v0 = 0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v0 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 1U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v1 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v1 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v1 = 8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v1 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 2U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v2 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v2 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v2 = 0x10U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v2 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 3U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v3 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v3 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v3 = 0x18U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v3 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 4U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v4 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[1U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v4 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v4 = 0x20U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v4 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 5U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v5 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[1U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v5 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v5 = 0x28U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v5 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 6U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v6 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[1U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v6 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v6 = 0x30U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v6 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 7U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v7 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[1U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v7 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v7 = 0x38U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v7 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 8U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v8 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[2U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v8 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v8 = 0x40U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v8 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 9U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v9 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[2U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v9 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v9 = 0x48U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v9 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0xaU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v10 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[2U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v10 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v10 = 0x50U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v10 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0xbU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v11 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[2U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v11 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v11 = 0x58U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v11 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0xcU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v12 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[3U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v12 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v12 = 0x60U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v12 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0xdU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v13 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[3U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v13 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v13 = 0x68U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v13 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0xeU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v14 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[3U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v14 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v14 = 0x70U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v14 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0xfU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v15 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[3U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v15 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v15 = 0x78U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v15 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x10U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v16 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[4U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v16 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v16 = 0x80U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v16 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x11U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v17 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[4U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v17 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v17 = 0x88U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v17 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x12U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v18 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[4U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v18 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v18 = 0x90U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v18 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x13U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v19 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[4U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v19 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v19 = 0x98U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v19 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x14U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v20 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[5U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v20 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v20 = 0xa0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v20 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x15U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v21 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[5U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v21 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v21 = 0xa8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v21 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x16U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v22 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[5U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v22 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v22 = 0xb0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v22 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x17U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v23 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[5U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v23 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v23 = 0xb8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v23 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x18U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v24 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[6U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v24 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v24 = 0xc0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v24 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x19U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v25 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[6U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v25 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v25 = 0xc8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v25 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x1aU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v26 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[6U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v26 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v26 = 0xd0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v26 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x1bU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v27 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[6U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v27 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v27 = 0xd8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v27 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x1cU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v28 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[7U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v28 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v28 = 0xe0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v28 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x1dU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v29 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[7U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v29 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v29 = 0xe8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v29 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x1eU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v30 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[7U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v30 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v30 = 0xf0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v30 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x1fU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v31 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[7U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v31 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v31 = 0xf8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v31 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x20U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v32 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[8U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v32 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v32 = 0x100U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v32 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x21U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v33 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[8U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v33 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v33 = 0x108U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v33 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x22U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v34 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[8U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v34 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v34 = 0x110U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v34 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x23U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v35 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[8U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v35 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v35 = 0x118U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v35 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x24U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v36 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[9U]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v36 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v36 = 0x120U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v36 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x25U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v37 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[9U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v37 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v37 = 0x128U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v37 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x26U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v38 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[9U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v38 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v38 = 0x130U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v38 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x27U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v39 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[9U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v39 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v39 = 0x138U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v39 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x28U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v40 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xaU]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v40 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v40 = 0x140U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v40 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x29U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v41 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xaU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v41 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v41 = 0x148U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v41 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x2aU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v42 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xaU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v42 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v42 = 0x150U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v42 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x2bU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v43 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xaU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v43 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v43 = 0x158U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v43 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x2cU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v44 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xbU]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v44 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v44 = 0x160U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v44 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x2dU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v45 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xbU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v45 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v45 = 0x168U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v45 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x2eU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v46 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xbU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v46 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v46 = 0x170U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v46 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x2fU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v47 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xbU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v47 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v47 = 0x178U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v47 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x30U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v48 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xcU]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v48 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v48 = 0x180U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v48 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x31U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v49 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xcU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v49 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v49 = 0x188U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v49 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x32U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v50 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xcU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v50 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v50 = 0x190U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v50 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x33U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v51 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xcU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v51 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v51 = 0x198U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v51 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x34U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v52 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xdU]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v52 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v52 = 0x1a0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v52 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x35U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v53 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xdU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v53 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v53 = 0x1a8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v53 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x36U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v54 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xdU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v54 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v54 = 0x1b0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v54 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x37U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v55 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xdU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v55 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v55 = 0x1b8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v55 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x38U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v56 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xeU]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v56 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v56 = 0x1c0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v56 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x39U)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v57 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xeU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v57 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v57 = 0x1c8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v57 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x3aU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v58 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xeU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v58 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v58 = 0x1d0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v58 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x3bU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v59 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xeU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v59 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v59 = 0x1d8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v59 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x3cU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v60 - = (0xffU & vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xfU]); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v60 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v60 = 0x1e0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v60 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x3dU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v61 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xfU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v61 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v61 = 0x1e8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v61 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x3eU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v62 - = (0xffU & (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xfU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v62 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v62 = 0x1f0U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v62 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - if ((1U & (IData)((vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - >> 0x3fU)))) { - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v63 - = (vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xfU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v63 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v63 = 0x1f8U; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v63 - = vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr; - } - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__ik = 0x40U; - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 = 0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 1U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 = 8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 2U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 = 0x10U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 3U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 = 0x18U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 4U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[1U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 = 0x20U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 5U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[1U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 = 0x28U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 6U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[1U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 = 0x30U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 7U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[1U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 = 0x38U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 8U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[2U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 = 0x40U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 9U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[2U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 = 0x48U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0xaU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[2U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 = 0x50U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0xbU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[2U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 = 0x58U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0xcU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[3U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 = 0x60U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0xdU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[3U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 = 0x68U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0xeU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[3U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 = 0x70U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0xfU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[3U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 = 0x78U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x10U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[4U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 = 0x80U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x11U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[4U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 = 0x88U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x12U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[4U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 = 0x90U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x13U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[4U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 = 0x98U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x14U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[5U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 = 0xa0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x15U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[5U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 = 0xa8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x16U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[5U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 = 0xb0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x17U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[5U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 = 0xb8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x18U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[6U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 = 0xc0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x19U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[6U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 = 0xc8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x1aU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[6U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 = 0xd0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x1bU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[6U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 = 0xd8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x1cU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[7U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 = 0xe0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x1dU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[7U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 = 0xe8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x1eU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[7U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 = 0xf0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x1fU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[7U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 = 0xf8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x20U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[8U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 = 0x100U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x21U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[8U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 = 0x108U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x22U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[8U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 = 0x110U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x23U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[8U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 = 0x118U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x24U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[9U]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 = 0x120U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x25U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[9U] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 = 0x128U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x26U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[9U] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 = 0x130U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x27U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[9U] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 = 0x138U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x28U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xaU]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 = 0x140U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x29U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xaU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 = 0x148U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x2aU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xaU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 = 0x150U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x2bU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xaU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 = 0x158U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x2cU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xbU]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 = 0x160U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x2dU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xbU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 = 0x168U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x2eU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xbU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 = 0x170U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x2fU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xbU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 = 0x178U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x30U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xcU]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 = 0x180U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x31U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xcU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 = 0x188U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x32U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xcU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 = 0x190U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x33U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xcU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 = 0x198U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x34U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xdU]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 = 0x1a0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x35U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xdU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 = 0x1a8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x36U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xdU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 = 0x1b0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x37U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xdU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 = 0x1b8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x38U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xeU]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 = 0x1c0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x39U)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xeU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 = 0x1c8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x3aU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xeU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 = 0x1d0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x3bU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xeU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 = 0x1d8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x3cU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 - = (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xfU]); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 = 0x1e0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x3dU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xfU] - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 = 0x1e8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x3eU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 - = (0xffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xfU] - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 = 0x1f0U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - >> 0x3fU)))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xfU] - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 = 0x1f8U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr; - } - } - vlSelf->__Vdly__main__DOT__u_fan__DOT__pwm_counter - = ((0x1387U <= (IData)(vlSelf->main__DOT__u_fan__DOT__pwm_counter)) - ? 0U : (0x1fffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_fan__DOT__pwm_counter)))); - if (vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset) { - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr = 0U; - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr = 0U; - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill = 0U; - } else { - if (vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd) { - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr))); - } - if (vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr) { - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr))); - } - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill - = (0x3fU & ((1U == (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd))) - ? ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill) - - (IData)(1U)) : ((2U == - (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) - | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd))) - ? ((IData)(1U) - + (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill)) - : ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr) - - (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr))))); - } - if (vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset) { - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr = 0U; - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr = 0U; - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill = 0U; - } else { - if (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr) { - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr))); - } - if (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd) { - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr))); - } - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill - = (0x3fU & ((1U == (((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd))) - ? ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill) - - (IData)(1U)) : ((2U == - (((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) - | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd))) - ? ((IData)(1U) - + (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill)) - : ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr) - - (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr))))); - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill = 0U; - } else { - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr))); - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))); - } - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill - = (0x1fU & ((1U == (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd))) - ? ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill) - - (IData)(1U)) : ((2U == - (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd))) - ? ((IData)(1U) - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill)) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))))); - } - if (vlSelf->main__DOT____Vcellinp__swic__i_reset) { - vlSelf->__Vdly__main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter = 0x14U; - } else if ((0U < (IData)(vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter))) { - vlSelf->__Vdly__main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter - = (0x1fU & ((IData)(vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter) - - (IData)(1U))); - } - if (vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchbus____pinNumber2) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchbus__DOT__r_value = 0x2000U; - vlSelf->__Vdly__main__DOT__swic__DOT__wdbus_int = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__wdbus_int)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchbus__DOT__r_value - = (0x3fffU & ((IData)(0x3fffU) + (IData)(vlSelf->main__DOT__swic__DOT__u_watchbus__DOT__r_value))); - vlSelf->__Vdly__main__DOT__swic__DOT__wdbus_int - = (1U == (IData)(vlSelf->main__DOT__swic__DOT__u_watchbus__DOT__r_value)); - } - if (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_clk) { - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness - = ((0x80U & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner)) - ? 0x1fU : ((0x1cU < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - ? 0x1cU : ((0x17U < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - ? 0x17U : ( - (0xfU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - ? 0xfU - : - ((0xbU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - ? 0xbU - : - ((7U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - ? 7U - : - ((5U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - ? 5U - : - ((3U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - ? 3U - : - ((1U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - ? 1U - : 0U))))))))); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness - = ((0x40U & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner)) - ? 0x1fU : ((0x1cU < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - ? 0x1cU : ((0x17U < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - ? 0x17U : ( - (0xfU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - ? 0xfU - : - ((0xbU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - ? 0xbU - : - ((7U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - ? 7U - : - ((5U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - ? 5U - : - ((3U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - ? 3U - : - ((1U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - ? 1U - : 0U))))))))); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness - = ((0x20U & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner)) - ? 0x1fU : ((0x1cU < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - ? 0x1cU : ((0x17U < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - ? 0x17U : ( - (0xfU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - ? 0xfU - : - ((0xbU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - ? 0xbU - : - ((7U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - ? 7U - : - ((5U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - ? 5U - : - ((3U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - ? 3U - : - ((1U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - ? 1U - : 0U))))))))); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness - = ((0x10U & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner)) - ? 0x1fU : ((0x1cU < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - ? 0x1cU : ((0x17U < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - ? 0x17U : ( - (0xfU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - ? 0xfU - : - ((0xbU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - ? 0xbU - : - ((7U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - ? 7U - : - ((5U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - ? 5U - : - ((3U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - ? 3U - : - ((1U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - ? 1U - : 0U))))))))); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness - = ((8U & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner)) - ? 0x1fU : ((0x1cU < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - ? 0x1cU : ((0x17U < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - ? 0x17U : ( - (0xfU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - ? 0xfU - : - ((0xbU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - ? 0xbU - : - ((7U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - ? 7U - : - ((5U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - ? 5U - : - ((3U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - ? 3U - : - ((1U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - ? 1U - : 0U))))))))); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness - = ((4U & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner)) - ? 0x1fU : ((0x1cU < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - ? 0x1cU : ((0x17U < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - ? 0x17U : ( - (0xfU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - ? 0xfU - : - ((0xbU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - ? 0xbU - : - ((7U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - ? 7U - : - ((5U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - ? 5U - : - ((3U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - ? 3U - : - ((1U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - ? 1U - : 0U))))))))); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness - = ((2U & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner)) - ? 0x1fU : ((0x1cU < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - ? 0x1cU : ((0x17U < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - ? 0x17U : ( - (0xfU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - ? 0xfU - : - ((0xbU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - ? 0xbU - : - ((7U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - ? 7U - : - ((5U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - ? 5U - : - ((3U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - ? 3U - : - ((1U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - ? 1U - : 0U))))))))); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness - = ((1U & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner)) - ? 0x1fU : ((0x1cU < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - ? 0x1cU : ((0x17U < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - ? 0x17U : ( - (0xfU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - ? 0xfU - : - ((0xbU - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - ? 0xbU - : - ((7U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - ? 7U - : - ((5U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - ? 5U - : - ((3U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - ? 3U - : - ((1U - < (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - ? 1U - : 0U))))))))); - } - if (((IData)(vlSelf->main__DOT__rcv__DOT__zero_baud_counter) - & (8U != (IData)(vlSelf->main__DOT__rcv__DOT__state)))) { - vlSelf->__Vdly__main__DOT__rcv__DOT__data_reg - = (((IData)(vlSelf->main__DOT__rcv__DOT__qq_uart) - << 7U) | (0x7fU & ((IData)(vlSelf->main__DOT__rcv__DOT__data_reg) - >> 1U))); - } - if ((0U == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner))) { - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_owner = 1U; - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_dir = 1U; - } else if (((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_clk) - & (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_dir))) { - if ((0x80U == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner))) { - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_dir - = (1U & (~ (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_dir))); - } else { - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_owner - = (0xfeU & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner) - << 1U)); - } - } else if (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_clk) { - if ((1U == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner))) { - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_dir - = (1U & (~ (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_dir))); - } else { - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_owner - = (0x7fU & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner) - >> 1U)); - } - } - vlSelf->__Vdly__main__DOT__txv__DOT__zero_baud_counter - = (1U == (IData)(vlSelf->main__DOT__txv__DOT__baud_counter)); - if ((0xfU == (IData)(vlSelf->main__DOT__txv__DOT__state))) { - vlSelf->__Vdly__main__DOT__txv__DOT__baud_counter = 0U; - vlSelf->__Vdly__main__DOT__txv__DOT__zero_baud_counter = 1U; - if (((IData)(vlSelf->main__DOT__genbus__DOT__ps_full) - & (~ (IData)(vlSelf->main__DOT__txv__DOT__r_busy)))) { - vlSelf->__Vdly__main__DOT__txv__DOT__baud_counter = 0x63U; - vlSelf->__Vdly__main__DOT__txv__DOT__zero_baud_counter = 0U; - } - } else if (vlSelf->main__DOT__txv__DOT__zero_baud_counter) { - if ((8U < (IData)(vlSelf->main__DOT__txv__DOT__state))) { - vlSelf->__Vdly__main__DOT__txv__DOT__baud_counter = 0U; - vlSelf->__Vdly__main__DOT__txv__DOT__zero_baud_counter = 1U; - } else { - vlSelf->__Vdly__main__DOT__txv__DOT__baud_counter - = ((8U == (IData)(vlSelf->main__DOT__txv__DOT__state)) - ? 0x62U : 0x63U); - } - } else { - vlSelf->__Vdly__main__DOT__txv__DOT__baud_counter - = (0x7fU & ((IData)(vlSelf->main__DOT__txv__DOT__baud_counter) - - (IData)(1U))); - } - __Vtableidx13 = (((IData)(vlSelf->main__DOT__txv__DOT__r_busy) - << 6U) | (((IData)(vlSelf->main__DOT__genbus__DOT__ps_full) - << 5U) | (((IData)(vlSelf->main__DOT__txv__DOT__state) - << 1U) - | (IData)(vlSelf->main__DOT__txv__DOT__zero_baud_counter)))); - if ((1U & Vmain__ConstPool__TABLE_h7c414883_0[__Vtableidx13])) { - vlSelf->main__DOT__txv__DOT__state = Vmain__ConstPool__TABLE_h9e411d43_0 - [__Vtableidx13]; - } - vlSelf->__Vdly__main__DOT__txv__DOT__r_busy = Vmain__ConstPool__TABLE_h5b51c6c5_0 - [__Vtableidx13]; - if (((3U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0 - = (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0 - = (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)); - } - if (vlSelf->main__DOT__genbus__DOT__r_wdt_reset) { - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__ofifo_empty_n = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow = 1U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cp_stb = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state = 1U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow = 1U; - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow = 0U; - } else { - if (((IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr - = (0x7ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr))); - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr - = (0x7fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr))); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)) - | (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n - = (1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow))); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)) - | (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__ofifo_empty_n - = (1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow))); - } - if (vlSelf->main__DOT__genbus__DOT__in_stb) { - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow = 0U; - } else if (vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read) { - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow - = ((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow) - | ((0x7fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr))) - == (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr))); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match; - } - if (vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd) { - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow - = ((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow) - & (IData)(vlSelf->main__DOT__genbus__DOT__in_stb)); - } else if (vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write) { - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow - = (((0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr))) - == (0x3fU & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr))) - & ((1U & (((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr)) - >> 6U)) != (1U & ((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr) - >> 6U)))); - } - if (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cp_stb = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cp_stb = 0U; - } - if (vlSelf->main__DOT__zip_cpu_int) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request = 1U; - } else if ((((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy))) - & (0x100000000ULL == (0xfc0000000ULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request = 0U; - } - if ((((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy))) - & (0ULL == (0xfc0000000ULL & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state = 1U; - } else if ((1U & (~ (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter - >> 0x15U)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state = 0U; - } - if (vlSelf->main__DOT__wbu_cyc) { - if (((IData)(vlSelf->main__DOT__wbu_cyc) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len = 0U; - } else if ((((IData)(vlSelf->main__DOT__wbu_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len - = (0x3ffU & ((IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len) - - (IData)(1U))); - } - } else { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len = 0U; - if ((((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy))) - & (0xc00000000ULL == (0xc00000000ULL - & vlSelf->main__DOT__genbus__DOT__ififo_codword)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len - = (0x3ffU & (IData)(vlSelf->main__DOT__genbus__DOT__ififo_codword)); - } - } - if (vlSelf->main__DOT__genbus__DOT__exec_stb) { - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow = 0U; - } else if (vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read) { - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow - = ((IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow) - | ((0x7ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr))) - == (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr))); - } - if (vlSelf->main__DOT__genbus__DOT__ofifo_rd) { - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow - = ((IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow) - & (IData)(vlSelf->main__DOT__genbus__DOT__exec_stb)); - } else if (vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write) { - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow - = (((0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr))) - == (0x3ffU & (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr))) - & ((1U & (((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr)) - >> 0xaU)) != (1U & ((IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr) - >> 0xaU)))); - } - } - if (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr) { - vlSelf->__Vdlyvval__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0 - = vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data; - vlSelf->__Vdlyvset__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0 - = (0x1fU & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr)); - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy) { - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len - = (0x7ffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size))); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len) - <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len = 0U; - } - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size - = (0x7fU & ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size)) - ? 1U : 2U) : ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size)) - ? 4U - : ( - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len) - > - ((IData)(0x40U) - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size))) - ? 0x40U - : - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size)))))); - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr - = (0x3fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr) - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size))); - } else if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr - = (0x3eU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr)); - } - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr - = (0x3cU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr)); - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr = 0U; - } - } - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid = 0U; - if (((((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last))) - & (0U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len))) - & (0U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__fill)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid = 1U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack))) { - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift - = (0x3fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift) - + ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc) - ? 1U : 0U))); - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift - = (0x3fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift) - + ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc) - ? 2U : 0U))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift - = (0x3eU & (IData)(vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift)); - } - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift - = (0x3fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift) - + ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc) - ? 4U : 0U))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift - = (0x3cU & (IData)(vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift)); - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift = 0U; - } - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr - = (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift - = (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr); - } - if (((IData)(vlSelf->main__DOT__rcv__DOT__qq_uart) - != (IData)(vlSelf->main__DOT__rcv__DOT__ck_uart))) { - vlSelf->__Vdly__main__DOT__rcv__DOT__chg_counter = 0U; - } else if ((0x7fU != (IData)(vlSelf->main__DOT__rcv__DOT__chg_counter))) { - vlSelf->__Vdly__main__DOT__rcv__DOT__chg_counter - = (0x7fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__rcv__DOT__chg_counter))); - } - if ((1U & ((~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U)) | (IData)(vlSelf->main__DOT__i2cscopei__DOT__write_to_control)))) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__raddr = 0U; - } else if (((IData)(vlSelf->main__DOT__i2cscopei__DOT__read_from_data) - & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - >> 4U))) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__raddr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__i2cscopei__DOT__raddr))); - } - if ((1U & ((~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U)) | (IData)(vlSelf->main__DOT__sdioscopei__DOT__write_to_control)))) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__raddr = 0U; - } else if (((IData)(vlSelf->main__DOT__sdioscopei__DOT__read_from_data) - & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - >> 4U))) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__raddr - = (0xfffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__sdioscopei__DOT__raddr))); - } - if ((1U & ((~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U)) | (IData)(vlSelf->main__DOT__emmcscopei__DOT__write_to_control)))) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__raddr = 0U; - } else if (((IData)(vlSelf->main__DOT__emmcscopei__DOT__read_from_data) - & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - >> 4U))) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__raddr - = (0xfffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__emmcscopei__DOT__raddr))); - } - if (((((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd)) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb)) - | (IData)(vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter = 0U; - } else if ((1U & (~ (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter - >> 0x15U)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter - = (0x3fffffU & ((IData)(1U) + vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter)); - } - if ((4U & (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config))) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stop_pipe - = ((0x1eU & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - << 1U)) | (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stopped)); - if (((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_triggered) - & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stopped)))) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__holdoff_counter - = (0xfffffU & ((IData)(1U) + vlSelf->main__DOT__i2cscopei__DOT__holdoff_counter)); - } - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__ck_addr - = ((((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_force_write) - | (IData)(vlSelf->main__DOT__i2cscopei__DOT__new_data)) - | (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stopped)) - ? 0U : (0x7fffffffU & ((IData)(1U) - + vlSelf->main__DOT__i2cscopei__DOT__ck_addr))); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_inhibit - = vlSelf->main__DOT__i2cscopei__DOT__dr_force_write; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_write - = (1U & ((((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_run_timeout) - & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_force_write))) - & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_force_inhibit))) - | (((IData)(vlSelf->main__DOT__i2cscopei__DOT__dw_trigger) - & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_triggered))) - | (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_primed))))); - if (vlSelf->main__DOT__i2cscopei__DOT__record_ce) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__waddr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__i2cscopei__DOT__waddr))); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_primed - = ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_primed) - | (0x3ffU == (IData)(vlSelf->main__DOT__i2cscopei__DOT__waddr))); - } - } else { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stop_pipe = 0U; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__holdoff_counter = 0U; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__ck_addr = 0U; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_write = 1U; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_inhibit = 0U; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__waddr = 0U; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_primed = 0U; - } - if ((4U & (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config))) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stop_pipe - = ((0x1eU & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - << 1U)) | (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stopped)); - if (((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_triggered) - & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stopped)))) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__holdoff_counter - = (0xfffffU & ((IData)(1U) + vlSelf->main__DOT__sdioscopei__DOT__holdoff_counter)); - } - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__ck_addr - = ((((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_force_write) - | (IData)(vlSelf->main__DOT__sdioscopei__DOT__new_data)) - | (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stopped)) - ? 0U : (0x7fffffffU & ((IData)(1U) - + vlSelf->main__DOT__sdioscopei__DOT__ck_addr))); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_inhibit - = vlSelf->main__DOT__sdioscopei__DOT__dr_force_write; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_write - = (1U & ((((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_run_timeout) - & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_force_write))) - & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_force_inhibit))) - | (((IData)(vlSelf->main__DOT__sdioscopei__DOT__dw_trigger) - & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_triggered))) - | (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_primed))))); - if (vlSelf->main__DOT__sdioscopei__DOT__record_ce) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__waddr - = (0xfffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__sdioscopei__DOT__waddr))); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_primed - = ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_primed) - | (0xfffU == (IData)(vlSelf->main__DOT__sdioscopei__DOT__waddr))); - } - } else { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stop_pipe = 0U; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__holdoff_counter = 0U; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__ck_addr = 0U; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_write = 1U; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_inhibit = 0U; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__waddr = 0U; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_primed = 0U; - } - if ((4U & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config))) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stop_pipe - = ((0x1eU & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - << 1U)) | (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stopped)); - if (((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_triggered) - & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stopped)))) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__holdoff_counter - = (0xfffffU & ((IData)(1U) + vlSelf->main__DOT__emmcscopei__DOT__holdoff_counter)); - } - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__ck_addr - = ((((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_force_write) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__new_data)) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stopped)) - ? 0U : (0x7fffffffU & ((IData)(1U) - + vlSelf->main__DOT__emmcscopei__DOT__ck_addr))); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_inhibit - = vlSelf->main__DOT__emmcscopei__DOT__dr_force_write; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_write - = (1U & ((((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_run_timeout) - & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_force_write))) - & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_force_inhibit))) - | (((IData)(vlSelf->main__DOT__emmcscopei__DOT__dw_trigger) - & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_triggered))) - | (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_primed))))); - if (vlSelf->main__DOT__emmcscopei__DOT__record_ce) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__waddr - = (0xfffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__emmcscopei__DOT__waddr))); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_primed - = ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_primed) - | (0xfffU == (IData)(vlSelf->main__DOT__emmcscopei__DOT__waddr))); - } - } else { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stop_pipe = 0U; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__holdoff_counter = 0U; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__ck_addr = 0U; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_write = 1U; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_inhibit = 0U; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__waddr = 0U; - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_primed = 0U; - } - if ((((0xfU == (IData)(vlSelf->main__DOT__rcv__DOT__state)) - & (~ (IData)(vlSelf->main__DOT__rcv__DOT__ck_uart))) - & (IData)(vlSelf->main__DOT__rcv__DOT__half_baud_time))) { - vlSelf->__Vdly__main__DOT__rcv__DOT__zero_baud_counter = 0U; - vlSelf->__Vdly__main__DOT__rcv__DOT__baud_counter = 0x63U; - } else if ((9U == (IData)(vlSelf->main__DOT__rcv__DOT__state))) { - vlSelf->__Vdly__main__DOT__rcv__DOT__zero_baud_counter = 1U; - vlSelf->__Vdly__main__DOT__rcv__DOT__baud_counter = 0U; - } else if (((IData)(vlSelf->main__DOT__rcv__DOT__zero_baud_counter) - & (8U > (IData)(vlSelf->main__DOT__rcv__DOT__state)))) { - vlSelf->__Vdly__main__DOT__rcv__DOT__zero_baud_counter = 0U; - vlSelf->__Vdly__main__DOT__rcv__DOT__baud_counter = 0x63U; - } else { - if ((1U == (IData)(vlSelf->main__DOT__rcv__DOT__baud_counter))) { - vlSelf->__Vdly__main__DOT__rcv__DOT__zero_baud_counter = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__rcv__DOT__zero_baud_counter)))) { - vlSelf->__Vdly__main__DOT__rcv__DOT__baud_counter - = (0x7fU & ((IData)(vlSelf->main__DOT__rcv__DOT__baud_counter) - - (IData)(1U))); - } - } - __Vtableidx12 = (((IData)(vlSelf->main__DOT__rcv__DOT__zero_baud_counter) - << 6U) | (((IData)(vlSelf->main__DOT__rcv__DOT__half_baud_time) - << 5U) | (((IData)(vlSelf->main__DOT__rcv__DOT__ck_uart) - << 4U) - | (IData)(vlSelf->main__DOT__rcv__DOT__state)))); - if (Vmain__ConstPool__TABLE_h02e0efbb_0[__Vtableidx12]) { - vlSelf->__Vdly__main__DOT__rcv__DOT__state - = Vmain__ConstPool__TABLE_h809a37d6_0[__Vtableidx12]; - } - if ((1U & ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_cyc))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read_ack = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read = 0U; - } else if (vlSelf->main__DOT__swic__DOT__dbg_cpu_read) { - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read_ack = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read = 1U; - } else { - if (vlSelf->main__DOT__swic__DOT__cmd_read_ack) { - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read_ack = 0U; - } - if (vlSelf->main__DOT__swic__DOT__cmd_read) { - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read = 0U; - } - } - if (vlSelf->main__DOT__u_fan__DOT__i2cd_valid) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__temp_tmp - = ((0xffff00U & (vlSelf->main__DOT__u_fan__DOT__temp_tmp - << 8U)) | (IData)(vlSelf->main__DOT__u_fan__DOT__i2cd_data)); - } - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) - & (0x1eU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_bit)))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_bit = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor = 0U; - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe - = ((2U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe) - << 1U)) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - << 1U); - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff - >> 0x20U))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - = (1U | vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result); - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign) - ? (- vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result) - : 0U); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_bit - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign))) - ? (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_bit))) - : 0U); - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy))) { - if ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor - >> 0x1fU)) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor - = (- vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor); - } - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr; - } - } - if ((1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr = 0U; - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__set - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout = 0U; - if ((1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__set))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout))); - } - if ((2U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__set))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout))); - } - if ((4U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__set))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout))); - } - if ((8U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__set))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout))); - } - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr - = (0x3ffU & (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr) - << 2U) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr)) - + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__45__Vfuncout)) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__set - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout = 0U; - if ((1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__set))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout))); - } - if ((2U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__set))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout))); - } - if ((4U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__set))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout))); - } - if ((8U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__set))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout))); - } - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr - = (3U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr) - + (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__46__Vfuncout))); - } - if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr = 0U; - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__set - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout = 0U; - if ((1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__set))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout))); - } - if ((2U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__set))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout))); - } - if ((4U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__set))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout))); - } - if ((8U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__set))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout))); - } - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr - = (0x3ffU & (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr) - << 2U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr)) - + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__87__Vfuncout)) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__set - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout = 0U; - if ((1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__set))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout))); - } - if ((2U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__set))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout))); - } - if ((4U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__set))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout))); - } - if ((8U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__set))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout - = (7U & ((IData)(1U) + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout))); - } - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr - = (3U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr) - + (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__COUNTONES__88__Vfuncout))); - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter = 0U; - } else if ((1U & (~ (IData)((0x3ffU == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter)))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter))); - } - if (vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc) { - if ((1U == (((IData)(vlSelf->main__DOT__u_fan__DOT__mem_stb) - << 1U) | (IData)(vlSelf->main__DOT__u_fan__DOT__mem_ack)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight - = (3U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight) - - (IData)(1U))); - } else if ((2U == (((IData)(vlSelf->main__DOT__u_fan__DOT__mem_stb) - << 1U) | (IData)(vlSelf->main__DOT__u_fan__DOT__mem_ack)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight - = (3U & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight))); - } - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight = 0U; - } - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr - = ((1U & (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb))) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))) - ? 1U : (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr)))); - if ((1U & ((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table = 1U; - } else if (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table - = (0x209U >= (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr)); - } - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr - = ((1U & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid) - & (0x3ffU == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb)))) - ? 0U : (3U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - + (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill)))); - if ((1U & (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc))) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding = 0U; - } else if ((2U == ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall))) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding - = (0x7ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding))); - } else if ((1U == ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall))) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding - = (0x7ffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding) - - (IData)(1U))); - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)))))) { - vlSelf->__Vdlyvval__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0 - = (((IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1fU)) << 0x1eU) | (0x3fffffffU - & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word))); - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0 - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[1U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[1U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[2U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[2U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[3U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[3U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[4U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[4U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[5U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[5U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[6U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[6U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[7U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[7U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[8U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[8U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[9U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[9U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xaU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xbU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xcU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xdU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xeU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xfU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU]; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr; - } - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr - = ((1U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid) - & (0x3ffU == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb)))) - ? 0U : (3U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - + (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill)))); - if (((IData)(vlSelf->main__DOT__genbus__DOT__ps_full) - & (~ (IData)(vlSelf->main__DOT__txv__DOT__r_busy)))) { - vlSelf->__Vdly__main__DOT__txv__DOT__lcl_data - = vlSelf->main__DOT__genbus__DOT__ps_data; - } else if (vlSelf->main__DOT__txv__DOT__zero_baud_counter) { - vlSelf->__Vdly__main__DOT__txv__DOT__lcl_data - = (0x80U | (0x7fU & ((IData)(vlSelf->main__DOT__txv__DOT__lcl_data) - >> 1U))); - } - if ((((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy))) - & (0ULL == (0xf00000000ULL & vlSelf->main__DOT__genbus__DOT__ififo_codword)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wide_addr - = (IData)(vlSelf->main__DOT__genbus__DOT__ififo_codword); - } else if ((((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy))) - & (0x200000000ULL == (0xe00000000ULL - & vlSelf->main__DOT__genbus__DOT__ififo_codword)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wide_addr - = (vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr - + (((IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x1fU)) << 0x1eU) | - (0x3fffffffU & (IData)(vlSelf->main__DOT__genbus__DOT__ififo_codword)))); - } else if ((((IData)(vlSelf->main__DOT__wbu_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))) - & (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_inc))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wide_addr - = ((IData)(1U) + vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack))) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0 - = (0xffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr - >> 6U)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0 - = (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr - >> 3U)); - } - if ((1U & (((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | (~ (IData)(vlSelf->main__DOT__wbu_cyc))) - | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__zero_acks = 1U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_acks_needed = 0U; - } else if ((2U == ((((IData)(vlSelf->main__DOT__wbu_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))) - << 1U) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__zero_acks = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_acks_needed - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed))); - } else if ((1U == ((((IData)(vlSelf->main__DOT__wbu_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))) - << 1U) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__zero_acks - = (1U == (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed)); - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_acks_needed - = (0x3ffU & ((IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed) - - (IData)(1U))); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp = 0U; - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = 0U; - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div) - & (0xeU == (0xeU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = 1U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_fpu) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = 1U; - } - if ((IData)(((0xeU == (0xeU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA))) - & (0x1aU == (0x1eU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = 1U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = 1U; - } - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU) ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_ljmp) - : (0x7c87c000U == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_ljmp; - } - } - } - if (vlSelf->main__DOT__i2cscopei__DOT__record_ce) { - vlSelf->__Vdlyvval__main__DOT__i2cscopei__DOT__mem__v0 - = vlSelf->main__DOT__i2cscopei__DOT__r_data; - vlSelf->__Vdlyvset__main__DOT__i2cscopei__DOT__mem__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__i2cscopei__DOT__mem__v0 - = vlSelf->main__DOT__i2cscopei__DOT__waddr; - } - vlSelf->__Vdlyvval__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0 - = (((IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word - >> 0x1fU)) << 0x1eU) | (0x3fffffffU - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word))); - vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0 - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr; - if (vlSelf->main__DOT__emmcscopei__DOT__record_ce) { - vlSelf->__Vdlyvval__main__DOT__emmcscopei__DOT__mem__v0 - = vlSelf->main__DOT__emmcscopei__DOT__r_data; - vlSelf->__Vdlyvset__main__DOT__emmcscopei__DOT__mem__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__emmcscopei__DOT__mem__v0 - = vlSelf->main__DOT__emmcscopei__DOT__waddr; - } - if (vlSelf->main__DOT__sdioscopei__DOT__record_ce) { - vlSelf->__Vdlyvval__main__DOT__sdioscopei__DOT__mem__v0 - = vlSelf->main__DOT__sdioscopei__DOT__r_data; - vlSelf->__Vdlyvset__main__DOT__sdioscopei__DOT__mem__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__sdioscopei__DOT__mem__v0 - = vlSelf->main__DOT__sdioscopei__DOT__waddr; - } - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb - = ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full))) - ? 0U : (0xfU & ((2U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill)) - ? (0xfU & ((0x7ffffff8U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb) - << 3U)) - | ((0x18U >> (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr)) - >> 1U))) - : ((1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill)) - ? (0xfU & ((0x7ffffff8U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb) - << 3U)) - | (((0x10U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill) - << 4U)) - >> (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr)) - >> 1U))) - : ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb) - << 3U))))); - if ((1U & (((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc))) - | (IData)(vlSelf->main__DOT__swic__DOT__no_dbg_err)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__dbg_stb = 0U; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stb)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stall))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__dbg_stb - = ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)); - } - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid - = ((~ (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog)) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid) - & (0x3ffU == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb)))) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl; - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id; - } - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb - = ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full))) - ? 0U : (0xfU & ((2U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill)) - ? (0xfU & ((0x7ffffff8U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb) - << 3U)) - | ((0x18U >> (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr)) - >> 1U))) - : ((1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill)) - ? (0xfU & ((0x7ffffff8U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb) - << 3U)) - | (((0x10U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill) - << 4U)) - >> (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr)) - >> 1U))) - : ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb) - << 3U))))); - if ((1U & ((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__wbu_cyc))))) { - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v0 = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available) { - vlSelf->__Vdlyvval__main__DOT__wbu_xbar__DOT__grant__v1 - = vlSelf->main__DOT__wbu_xbar__DOT__request - [0U]; - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v1 = 1U; - } else if (vlSelf->main__DOT__wbu_xbar__DOT__m_stb) { - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v2 = 1U; - } - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_sgn - = ((2U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_sgn) - << 1U)) | (1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid - = ((~ (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog)) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid) - & (0x3ffU == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb)))) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb))); - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr - = ((0x38U & (IData)(vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr)) - | (7U & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr)))); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr - = (0x38U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U)); - } - if (vlSelf->main__DOT__wbu_cyc) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_ack - = ((IData)(vlSelf->main__DOT__wbu_we) ? - (((((IData)(vlSelf->main__DOT__wbu_stb) - ? 1U : 0U) + (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed)) - + ((((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy))) - & (0x400000000ULL == (0xc00000000ULL - & vlSelf->main__DOT__genbus__DOT__ififo_codword))) - ? 1U : 0U)) <= ((IData)(1U) + - ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - ? 1U : 0U))) - : (((IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len) - + (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed)) - <= ((IData)(1U) + ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - ? 1U : 0U)))); - } else { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_ack = 1U; - if (((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (0xc00000000ULL == (0xc00000000ULL & vlSelf->main__DOT__genbus__DOT__ififo_codword)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_ack - = (1U >= (0x3ffU & (IData)(vlSelf->main__DOT__genbus__DOT__ififo_codword))); - } - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc - = (0xffffffeU & vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc); - if ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU)) { - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc - = ((1U & vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc) - | (0xffffffeU & (((IData)(1U) - + (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc - >> 1U)) - << 1U))); - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc - = (2U | (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc)); - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc - = (0xffffffcU & (((IData)(1U) + (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc - >> 2U)) - << 2U)); - } - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr - = (0x3fU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - ? ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr)) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr))); - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr - = (0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr); - if ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr - = (0x38U & (IData)(vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr)); - } - } - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_read_request - = (1U & ((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | ((IData)(vlSelf->main__DOT__wbu_cyc) - ? ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - | (((IData)(vlSelf->main__DOT__wbu_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))) - ? (2U >= (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len)) - : (((IData)(vlSelf->main__DOT__wbu_stb) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - ? (1U >= (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len)) - : (1U >= (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len))))) - : ((((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)) - | (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy)) - | (3U != (3U & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x22U))))) - | (1U >= (0x3ffU & (IData)(vlSelf->main__DOT__genbus__DOT__ififo_codword))))))); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__genbus__DOT__soft_reset))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_timer = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_reset = 1U; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbu_cyc)) - | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_timer = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_reset = 0U; - } else if ((0x7ffffU == vlSelf->main__DOT__genbus__DOT__r_wdt_timer)) { - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_reset = 1U; - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_timer = 0U; - } else { - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_timer - = (0x7ffffU & ((IData)(1U) + vlSelf->main__DOT__genbus__DOT__r_wdt_timer)); - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_reset = 0U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign) { - if ((1U & (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - >> 0x1fU)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend = 0ULL; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - = ((0x7ffffffe00000000ULL & vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend) - | (0x1ffffffffULL & (- (0x100000000ULL - | (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend)))))); - } - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - = (0x7ffffffffffffffeULL & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - << 1U)); - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff - >> 0x20U))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - = ((0xffffffffULL & vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend) - | ((QData)((IData)((0x7fffffffU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff)))) - << 0x20U)); - } - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - = (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - } - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign) - ? ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor - >> 0x1fU) ^ (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - >> 0x1fU))) - : ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor))))))); - if (vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write) { - vlSelf->__Vdlyvval__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0 - = vlSelf->main__DOT__genbus__DOT__in_word; - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0 - = (0x3fU & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr)); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid = 1U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) { - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid - = (1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign))); - } - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0 - = ((0xf00U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - << 8U)) | ((0xc0U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - << 5U)) - | (0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0 - = (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr)); - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stall))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_addr - = ((0x3ffff8U & vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_addr) - | (7U & ((IData)(1U) + vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr))); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_addr - = (0x3ffff8U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U)); - } - if (vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write) { - vlSelf->__Vdlyvval__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0 - = vlSelf->main__DOT__genbus__DOT__exec_word; - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0 - = (0x3ffU & (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr)); - } - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_err) - >> vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U])); - if ((4U & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (1U & (~ (IData)(vlSelf->main__DOT__wbu_err))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__wbu_cyc))) - | (IData)(vlSelf->main__DOT__wbu_err)))) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr = 0U; - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc))))) { - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v0 = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available) { - vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v1 - = vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U]; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v1 = 1U; - } else if ((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))) { - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v2 = 1U; - } - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 1U))))) { - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v3 = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available) { - vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v4 - = vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U]; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v4 = 1U; - } else if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))) { - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v5 = 1U; - } - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 2U))))) { - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v6 = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available) { - vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v7 - = vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U]; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v7 = 1U; - } else if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))) { - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v8 = 1U; - } - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 3U))))) { - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v9 = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__requested_channel_is_available) { - vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v10 - = vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U]; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v10 = 1U; - } else if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))) { - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v11 = 1U; - } - } - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__r_counter = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_zero = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_value = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i = 0U; - } else { - if (vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__enable_ints) { - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable - = (0x7fffU & ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable) - | (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x10U))); - } else if (vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__disable_ints) { - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable - = ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable) - & (~ (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x10U))); - } - if (vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__enable_ints) { - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable - = (0x7fffU & ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable) - | (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x10U))); - } else if (vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__disable_ints) { - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable - = ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable) - & (~ (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x10U))); - } - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state - = ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write) - ? ((IData)(vlSelf->main__DOT__swic__DOT__main_int_vector) - | ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state) - & (~ vlSelf->main__DOT__swic__DOT__sys_data))) - : ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state) - | (IData)(vlSelf->main__DOT__swic__DOT__main_int_vector))); - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state - = ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write) - ? ((IData)(vlSelf->main__DOT__swic__DOT__alt_int_vector) - | ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state) - & (~ vlSelf->main__DOT__swic__DOT__sys_data))) - : ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state) - | (IData)(vlSelf->main__DOT__swic__DOT__alt_int_vector))); - if ((0U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack = 0U; - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack = 1U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack = 1U; - } - } else if ((3U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack) - | (3U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr) - >> 1U)))) : - ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack) - | (7U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr))))); - } else if ((1U == (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack - = (2U >= (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending)); - } else if ((2U == (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)) - | (0U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending)))); - } - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__r_counter - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv) - & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 0xbU)); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 0xaU)); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 8U)); - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag = 1U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag = 1U; - } - if ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i = 1U; - } - } - if (vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__wb_write) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_zero - = (0U == (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data)); - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_value - = (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data); - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)))) { - if ((1U == vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value)) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_zero = 1U; - } - } - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & (IData)(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_zero)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_value - = (0x7fffffffU & (vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value - - (IData)(1U))); - } - } - } - if (vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero - = (0U == (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data)); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value - = (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data); - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)))) { - if ((1U == vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value)) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero) - & (IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload))) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero = 0U; - } - } - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & (IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running))) { - if (vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero) { - if (vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value - = vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_interval_count; - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value - = (0x7fffffffU & (vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value - - (IData)(1U))); - } - } - } - if (vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero - = (0U == (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data)); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value - = (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data); - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)))) { - if ((1U == vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value)) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero) - & (IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload))) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero = 0U; - } - } - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & (IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running))) { - if (vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero) { - if (vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value - = vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_interval_count; - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value - = (0x7fffffffU & (vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value - - (IData)(1U))); - } - } - } - if (vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero - = (0U == (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data)); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value - = (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data); - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_running) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)))) { - if ((1U == vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value)) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_zero) - & (IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload))) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero = 0U; - } - } - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & (IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_running))) { - if (vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_zero) { - if (vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value - = vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_interval_count; - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value - = (0x7fffffffU & (vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value - - (IData)(1U))); - } - } - } - } - if (((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset))) { - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_write = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_clear_cache = 0U; - } else { - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_write)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_write - = vlSelf->main__DOT__swic__DOT__dbg_cpu_write; - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__dbg_cmd_write) - & (IData)(vlSelf->main__DOT__swic__DOT__clear_cache_request)) - & (IData)(vlSelf->main__DOT__swic__DOT__halt_request))) { - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_clear_cache = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_halt) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_clear_cache = 0U; - } - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr = 0U; - } else { - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr))); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr))); - } else if (((1U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr))); - } else if (((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr))); - } - } - if (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr = 0x3ffU; - } else { - if (((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb))) { - if ((7U == (7U & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x21U))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr))); - } - } - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr - = (0x3ffU & ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))) - ? ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr) - - (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - & (0xe00000000ULL - == (0xe00000000ULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword))) - ? 0U : 1U)) : ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr) - - (IData)(1U)))); - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word - = (0x3fffffffU & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword)); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__dw_bits - = (0x3fU & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x1eU))); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy)))) { - if ((1U < (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__dw_bits - = (0x3fU & (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word - >> 0x18U)); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word - = ((0x3fU & vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word) - | (0x3fffffc0U & (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word - << 6U))); - } else if ((1U & (~ ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits) - >> 6U)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__dw_bits = 0x40U; - } - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb - = (1U & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__full_line) - | (~ ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits) - >> 6U)))); - } else if (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy) { - if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb = 0U; - } - } else { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb - = ((((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy)) - & (~ ((IData)(vlSelf->main__DOT__wbu_cyc) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy))))) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl))) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__hx_stb = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__cw_stb = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wbu_tx_stb = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len = 0U; - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount = 0xc8U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckedge = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckcount = 0xfffU; - vlSelf->__Vdly__main__DOT__spioi__DOT__r_led = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga = 0x1387U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys = 0x1387U; - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__bus_err = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_jump_addr = 0U; - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present - = ((6U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present) - << 1U)) | (IData)(vlSelf->i_sdcard_detect)); - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__hx_stb - = vlSelf->main__DOT__genbus__DOT__rx_valid; - } - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb - = ((6U & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb) - << 1U)) | ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cod_busy)))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb)) - | (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__cw_stb - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wbu_tx_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__ps_full))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wbu_tx_stb - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb; - } - if ((1U & (((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb)) - | (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))))) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb))))) { - if ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len = 0U; - } else if ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len - = (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))) - ? 1U : 0U); - } else if (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len - = (7U & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len))); - } - } - if ((((IData)(vlSelf->main__DOT____Vcellinp__u_i2cdma__S_VALID) - & (IData)(vlSelf->main__DOT__i2cdma_ready)) - & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid) - & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready))))) { - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid = 1U; - } else if (vlSelf->main__DOT__u_i2cdma__DOT__skd_ready) { - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid = 0U; - } - if ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len = 0U; - } else if ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))) - & ((0U == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)) - | (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len - = ((3U == (3U & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits) - >> 4U))) ? 2U : ((2U - == - (3U - & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits) - >> 4U))) - ? 1U - : - ((2U - == - (7U - & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits) - >> 3U))) - ? 2U - : - ((1U - == - (7U - & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits) - >> 3U))) - ? - (7U - & ((IData)(2U) - + - (3U - & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits) - >> 1U)))) - : 6U)))); - } else if (((((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb)) - | (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))))) - & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len))) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len = 0U; - } - if (((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen - = ((0x40U & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_bits)) - ? 0U : (0x7fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen)))); - } - if ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (0x600000000ULL == (0xe00000000ULL - & vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word))) - & (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr - = (0xffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr))); - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw - = (3U & (IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x22U))); - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len - = ((0U == (7U & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x21U)))) - ? 1U : ((2U == (0xfU & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x20U)))) - ? 6U : (7U & ((3U == (0xfU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x20U)))) - ? ((IData)(2U) - + (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x1eU)))) - : ((1U - == - (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x22U)))) - ? 2U - : ( - (2U - == - (3U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - >> 0x22U)))) - ? 1U - : 6U)))))); - } else if (((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy)) - & (0U < (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len)))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len - = (7U & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len) - - (IData)(1U))); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge)) - | (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch))))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount - = (0xfffU & ((0U < (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount)) - ? ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount) - - (IData)(1U)) : (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount))); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge) - ? (0U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount)) - : (1U >= (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount))); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckedge)) - | (~ (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_stretch))))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckcount - = (0xfffU & ((0U < (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckcount)) - ? ((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckcount) - - (IData)(1U)) : (IData)(vlSelf->main__DOT__i2ci__DOT__ckcount))); - vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckedge - = ((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckedge) - ? (0U == (IData)(vlSelf->main__DOT__i2ci__DOT__ckcount)) - : (1U >= (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckcount))); - } - if ((((IData)(vlSelf->main__DOT__wb32_spio_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 9U)) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x24U)))) { - vlSelf->__Vdly__main__DOT__spioi__DOT__r_led - = (0xffU & ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x25U))) - ? (((IData)(vlSelf->main__DOT__spioi__DOT__r_led) - & (~ ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - << 0x18U) | - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - >> 8U)))) | - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - << 0x18U) | (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - >> 8U)))) - : vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U])); - } - if ((1U & ((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 7U) & (~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x1aU))))) { - if ((0U == (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U)))) { - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1cU)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga - = ((0x1f00U & (IData)(vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga)) - | (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1dU)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga - = ((0xffU & (IData)(vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga)) - | (0x1f00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U])); - } - } - if ((0U != (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U)))) { - if ((1U == (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x18U)))) { - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1cU)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys - = ((0x1f00U & (IData)(vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys)) - | (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1dU)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys - = ((0xffU & (IData)(vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys)) - | (0x1f00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U])); - } - } - } - } else { - if ((0x1387U <= (IData)(vlSelf->main__DOT__u_fan__DOT__ctl_fpga))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga = 0x1387U; - } - if ((0x1387U <= (IData)(vlSelf->main__DOT__u_fan__DOT__ctl_sys))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys = 0x1387U; - } - } - if (((IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__bus_err = 1U; - } else if ((0x10U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)))) { - if ((2U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) { - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__bus_err - = ((1U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - ? ((IData)(vlSelf->main__DOT__u_i2cdma__DOT__bus_err) - & (0ULL == (0xf0000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - : ((IData)(vlSelf->main__DOT__u_i2cdma__DOT__bus_err) - & (0ULL == (0xf0000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel)))); - } - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc) - | ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr))); - } - if ((((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle))) - & (0xc0U == (0xf0U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn)))) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready)) - & (0xcU == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn))))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__jump_target; 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- } - if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted = 1U; - } - if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready)) - & (0x900U == (0xf00U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted = 1U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) { - if (((IData)(((0U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - >> 0x13U))) & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1eU)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted = 1U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted = 1U; - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted = 0U; - } - } - if (((((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready)) - & (0x200U == (0xf00U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)))) - & (IData)(vlSelf->main__DOT__i2ci__DOT__soft_halt_request))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = 1U; - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT__soft_halt_request) - & (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_abort))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = 1U; - } - if ((((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_illegal))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = 1U; - } - if ((((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready)) - & (0x900U == (0xf00U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = 1U; - } - if (vlSelf->main__DOT__i2ci__DOT__bus_write) { - if (((IData)(((0U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - >> 0x13U))) & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xeU)))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = 1U; - } - if (vlSelf->main__DOT__i2ci__DOT__bus_manual) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = 1U; - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT__bus_jump) - & (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = 0U; - } - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc) - | ((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_jump_addr - = (0xfffffffU & ((IData)(1U) + vlSelf->main__DOT__i2ci__DOT__pf_jump_addr)); - } - if ((((((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle))) - & (0xc0U == (0xf0U & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_insn)))) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready)) - & (0xcU == (IData)(vlSelf->main__DOT__i2ci__DOT__half_insn))))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_jump_addr - = vlSelf->main__DOT__i2ci__DOT__jump_target; - } - if (vlSelf->main__DOT__i2ci__DOT__i2c_abort) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_jump_addr - = vlSelf->main__DOT__i2ci__DOT__abort_address; - } - if (vlSelf->main__DOT__i2ci__DOT__bus_jump) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_jump_addr - = (0xfffffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U]); - } - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc))))) { - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v0 = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available) { - vlSelf->__Vdlyvval__main__DOT__wb32_xbar__DOT__grant__v1 - = vlSelf->main__DOT__wb32_xbar__DOT__request - [0U]; - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v1 = 1U; - } else if (vlSelf->main__DOT__wb32_xbar__DOT__m_stb) { - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v2 = 1U; - } - } - __Vtableidx11 = (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb) - << 5U) | (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb) - << 4U) | (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - << 3U) - | (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner) - << 2U) - | (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc)))))); - if (Vmain__ConstPool__TABLE_heed7669e_0[__Vtableidx11]) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner - = Vmain__ConstPool__TABLE_hdf55cab5_0[__Vtableidx11]; - } - if ((1U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]))) { - if ((1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb)) - | (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = ((2U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb)) - | (1U & (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wbu_xbar__DOT__request - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]] : 0U) & (~ ( - (0U - >= - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) - & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U])))))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = (2U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = (2U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb)); - } - if ((1U & ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_err)))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = (2U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb)); - } - if ((2U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - >> 1U)) | (~ ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall) - >> 1U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = ((1U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb)) - | (2U & (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) ? (0xfffffffeU - & vlSelf->main__DOT__wbu_xbar__DOT__request - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]]) : 0U) - & ((~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]))) - << 1U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = (1U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = (1U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb)); - } - if ((1U & ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_err) - >> 1U)))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb - = (1U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb)); - } - if (vlSelf->main__DOT__wbwide_wbdown_stall) { - if ((1U & ((~ (IData)(vlSelf->main__DOT__wb32_wbdown_stb)) - | (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))) { - VL_SHIFTL_WWI(512,512,32, __Vtemp_h211bbf5b__0, vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data, - ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift) - << 5U)); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0U] - = __Vtemp_h211bbf5b__0[0U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[1U] - = __Vtemp_h211bbf5b__0[1U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[2U] - = __Vtemp_h211bbf5b__0[2U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[3U] - = __Vtemp_h211bbf5b__0[3U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[4U] - = __Vtemp_h211bbf5b__0[4U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[5U] - = __Vtemp_h211bbf5b__0[5U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[6U] - = __Vtemp_h211bbf5b__0[6U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[7U] - = __Vtemp_h211bbf5b__0[7U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[8U] - = __Vtemp_h211bbf5b__0[8U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[9U] - = __Vtemp_h211bbf5b__0[9U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xaU] - = __Vtemp_h211bbf5b__0[0xaU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xbU] - = __Vtemp_h211bbf5b__0[0xbU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xcU] - = __Vtemp_h211bbf5b__0[0xcU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xdU] - = __Vtemp_h211bbf5b__0[0xdU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xeU] - = __Vtemp_h211bbf5b__0[0xeU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xfU] - = __Vtemp_h211bbf5b__0[0xfU]; - } - if ((((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first)) - | ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb) - & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr - = ((0xf0U & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr)) - | (0xfU & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr) - + (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift)))); - } - } else { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[1U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[1U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[2U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[2U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[3U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[3U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[4U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[4U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[5U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[5U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[6U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[6U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[7U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[7U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[8U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[8U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[9U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[9U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xaU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xaU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xbU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xbU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xcU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xcU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xdU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xdU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xeU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xeU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xfU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xfU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr - = (0xf0U & (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - << 4U)); - } - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err - = ((~ (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc))) - | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)))) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant - = ((2U & (IData)(vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant)) - | (1U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))); - if ((1U & (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] & ((~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant - = (1U | (IData)(vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant - = (2U & (IData)(vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant - = ((1U & (IData)(vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant)) - | (2U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] >> 1U) & ((~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant - = (2U | (IData)(vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant - = (1U & (IData)(vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant) - & (0xf000U >> vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U])); - if ((0x1000U & vlSelf->main__DOT__wb32_xbar__DOT__grant - [0U])) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (1U & (~ (IData)(vlSelf->main__DOT__wb32_wbdown_err))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc))) - | (IData)(vlSelf->main__DOT__wb32_wbdown_err)))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag = 0U; - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0x1eU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) { - if ((1U & (~ (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 5U)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap - = (1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv))); - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 9U)); - } - } - if (((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & (0x1eU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 0xbU)); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag = 1U; - } - } - vlSelf->__Vdly__main__DOT__swic__DOT__wdt_reset - = ((~ (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__wb_write)) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))) - & (1U == vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value)); - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_triggered)) - | (~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stopped = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stopped)))) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stopped - = (vlSelf->main__DOT__i2cscopei__DOT__holdoff_counter - >= vlSelf->main__DOT__i2cscopei__DOT__br_holdoff); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_triggered)) - | (~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stopped = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stopped)))) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stopped - = (vlSelf->main__DOT__sdioscopei__DOT__holdoff_counter - >= vlSelf->main__DOT__sdioscopei__DOT__br_holdoff); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_triggered)) - | (~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stopped = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stopped)))) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stopped - = (vlSelf->main__DOT__emmcscopei__DOT__holdoff_counter - >= vlSelf->main__DOT__emmcscopei__DOT__br_holdoff); - } - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err - = ((~ (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) - & (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err)) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err)))); - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr = 0U; - } else if ((1U & (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr = 0U; - } else if ((1U & (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr))); - } - if ((1U & (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe = 0U; - if ((((IData)(vlSelf->main__DOT__swic__DOT__cmd_waddr) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe = 1U; - } - if ((7U == (7U & ((IData)(vlSelf->main__DOT__swic__DOT__cmd_waddr) - >> 1U)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe = 1U; - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe = 0U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_addr - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr; - } else { - if (vlSelf->main__DOT__u_fan__DOT__mem_stb) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_addr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_fan__DOT__mem_addr))); - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr))); - } - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal = 0U; - } else { - if (((IData)(vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc) - & (IData)(vlSelf->main__DOT__u_fan__DOT__mem_ack))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid = 1U; - } else if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid; - } - if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__mem_ack))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid - = (1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready))); - } else if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid = 0U; - } - if ((1U & (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal))))) { - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal - = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_illegal; - } - } - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_illegal = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_illegal - = ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc))) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache - == (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U)))); - } - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v4 - = (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] + vlSelf->main__DOT__clock_generator__DOT__times_five); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v6 - = (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] + vlSelf->main__DOT__clock_generator__DOT__times_seven); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v2 - = (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] + vlSelf->main__DOT__clock_generator__DOT__times_three); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v5 - = (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] + (vlSelf->main__DOT__clock_generator__DOT__times_three - << 1U)); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v0 - = (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] + vlSelf->main__DOT__clock_generator__DOT__r_delay); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v1 - = (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] + (vlSelf->main__DOT__clock_generator__DOT__r_delay - << 1U)); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v3 - = (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] + (vlSelf->main__DOT__clock_generator__DOT__r_delay - << 2U)); - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) { - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb = 0U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stall))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb = 0U; - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_cyc = 0U; - } - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__needload) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_cyc = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb = 1U; - } - if (vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr) { - vlSelf->__Vdlyvval__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0 - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_shift; - vlSelf->__Vdlyvset__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0 - = (0x1fU & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr)); - } - if ((1U & ((((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc))) - | ((IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_cyc) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 3U))) | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err)))) { - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc = 0U; - } else if ((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb)))) { - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc = 1U; - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_set) - & VL_LTS_III(32, 0U, vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_wb)) - & ((vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_when - >> 0x1fU) | (~ (IData)(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_set))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__int_when - = vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_when; - } - if ((IData)((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) & (0x100U == (0x700U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 9U)) & (0xf000000000ULL == - (0xf000000000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))))) { - vlSelf->__Vdly__o_gpio = (0xffU & (((IData)(vlSelf->o_gpio) - & (~ (( - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - << 0x10U) - | (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - >> 0x10U)))) - | (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - << 0x10U) - | (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - >> 0x10U))))); - } - if (vlSelf->main__DOT__console__DOT__rx_uart_reset) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__r_fill = 0U; - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow = 0U; - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_underflow = 1U; - } else { - if ((1U == (((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write) - << 1U) | (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read)))) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__r_fill - = (0x3fU & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - - (IData)(1U))); - } else if ((2U == (((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write) - << 1U) | (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read)))) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__r_fill - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill))); - } - if (vlSelf->main__DOT__console__DOT__rxf_wb_read) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow - = ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow) - & (IData)(vlSelf->main__DOT__w_console_rx_stb)); - } else if (vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow - = ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow) - | ((0x3fU & ((IData)(2U) + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr))) - == (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr))); - } else if (((0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr))) - == (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr))) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow = 1U; - } - if (vlSelf->main__DOT__w_console_rx_stb) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_underflow = 0U; - } else if (vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_underflow - = ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow) - | ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next) - == (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr))); - } - } - if (vlSelf->main__DOT__console__DOT__tx_uart_reset) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__r_fill = 0x3fU; - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow = 0U; - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_underflow = 1U; - } else { - if ((1U == (((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write) - << 1U) | (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read)))) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__r_fill - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill))); - } else if ((2U == (((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write) - << 1U) | (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read)))) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__r_fill - = (0x3fU & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - - (IData)(1U))); - } - if (vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow - = ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow) - & (IData)(vlSelf->main__DOT__console__DOT__txf_wb_write)); - } else if (vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow - = ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow) - | ((0x3fU & ((IData)(2U) + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr))) - == (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr))); - } else if (((0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr))) - == (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr))) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow = 1U; - } - if (vlSelf->main__DOT__console__DOT__txf_wb_write) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_underflow = 0U; - } else if (vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_underflow - = ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow) - | ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next) - == (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr))); - } - } - if (vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write) { - vlSelf->__Vdlyvval__main__DOT__console__DOT__rxfifo__DOT__fifo__v0 - = vlSelf->main__DOT__w_console_rx_data; - vlSelf->__Vdlyvset__main__DOT__console__DOT__rxfifo__DOT__fifo__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__console__DOT__rxfifo__DOT__fifo__v0 - = vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr; - } - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done - = ((~ ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done))) - & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb)))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done - = ((~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done))) - & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb)))); - if ((1U & ((((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err))) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce)))) - | (3U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - ? 1U : 0U); - } else if ((1U == (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - << 1U) | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending - = (0x1fU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending) - - (IData)(1U))); - } else if ((2U == (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - << 1U) | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending - = (0x1fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending))); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce)))) { - if ((0U != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock - = (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock) - - (IData)(1U))); - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock = 3U; - } - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] = 0U; - } else { - if ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full))) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)))) { - __Vtemp_hc94fac31__0[0U] = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - __Vtemp_hc94fac31__0[1U] = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - __Vtemp_hc94fac31__0[2U] = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - __Vtemp_hc94fac31__0[3U] = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - __Vtemp_hc94fac31__0[4U] = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - __Vtemp_hc94fac31__0[5U] = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - __Vtemp_hc94fac31__0[6U] = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - __Vtemp_hc94fac31__0[7U] = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - __Vtemp_hc94fac31__0[8U] = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - __Vtemp_hc94fac31__0[9U] = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - __Vtemp_hc94fac31__0[0xaU] = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - __Vtemp_hc94fac31__0[0xbU] = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - __Vtemp_hc94fac31__0[0xcU] = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - __Vtemp_hc94fac31__0[0xdU] = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - __Vtemp_hc94fac31__0[0xeU] = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - __Vtemp_hc94fac31__0[0xfU] = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - __Vtemp_hc94fac31__0[0x10U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]; - __Vtemp_hc94fac31__0[0x11U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]; - __Vtemp_hc94fac31__0[0x12U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]; - __Vtemp_hc94fac31__0[0x13U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]; - __Vtemp_hc94fac31__0[0x14U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]; - __Vtemp_hc94fac31__0[0x15U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]; - __Vtemp_hc94fac31__0[0x16U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]; - __Vtemp_hc94fac31__0[0x17U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]; - __Vtemp_hc94fac31__0[0x18U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]; - __Vtemp_hc94fac31__0[0x19U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]; - __Vtemp_hc94fac31__0[0x1aU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]; - __Vtemp_hc94fac31__0[0x1bU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]; - __Vtemp_hc94fac31__0[0x1cU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]; - __Vtemp_hc94fac31__0[0x1dU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]; - __Vtemp_hc94fac31__0[0x1eU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]; - __Vtemp_hc94fac31__0[0x1fU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]; - VL_SHIFTR_WWI(1024,1024,32, __Vtemp_hfa8722fc__0, __Vtemp_hc94fac31__0, - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift) - << 3U)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] - = (Vmain__ConstPool__CONST_h93e1b771_0[0U] - | __Vtemp_hfa8722fc__0[0U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] - = (Vmain__ConstPool__CONST_h93e1b771_0[1U] - | __Vtemp_hfa8722fc__0[1U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] - = (Vmain__ConstPool__CONST_h93e1b771_0[2U] - | __Vtemp_hfa8722fc__0[2U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] - = (Vmain__ConstPool__CONST_h93e1b771_0[3U] - | __Vtemp_hfa8722fc__0[3U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] - = (Vmain__ConstPool__CONST_h93e1b771_0[4U] - | __Vtemp_hfa8722fc__0[4U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] - = (Vmain__ConstPool__CONST_h93e1b771_0[5U] - | __Vtemp_hfa8722fc__0[5U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] - = (Vmain__ConstPool__CONST_h93e1b771_0[6U] - | __Vtemp_hfa8722fc__0[6U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] - = (Vmain__ConstPool__CONST_h93e1b771_0[7U] - | __Vtemp_hfa8722fc__0[7U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] - = (Vmain__ConstPool__CONST_h93e1b771_0[8U] - | __Vtemp_hfa8722fc__0[8U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] - = (Vmain__ConstPool__CONST_h93e1b771_0[9U] - | __Vtemp_hfa8722fc__0[9U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] - = (Vmain__ConstPool__CONST_h93e1b771_0[0xaU] - | __Vtemp_hfa8722fc__0[0xaU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] - = (Vmain__ConstPool__CONST_h93e1b771_0[0xbU] - | __Vtemp_hfa8722fc__0[0xbU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] - = (Vmain__ConstPool__CONST_h93e1b771_0[0xcU] - | __Vtemp_hfa8722fc__0[0xcU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] - = (Vmain__ConstPool__CONST_h93e1b771_0[0xdU] - | __Vtemp_hfa8722fc__0[0xdU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] - = (Vmain__ConstPool__CONST_h93e1b771_0[0xeU] - | __Vtemp_hfa8722fc__0[0xeU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] - = (Vmain__ConstPool__CONST_h93e1b771_0[0xfU] - | __Vtemp_hfa8722fc__0[0xfU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] - | __Vtemp_hfa8722fc__0[0x10U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] - | __Vtemp_hfa8722fc__0[0x11U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] - | __Vtemp_hfa8722fc__0[0x12U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] - | __Vtemp_hfa8722fc__0[0x13U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] - | __Vtemp_hfa8722fc__0[0x14U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] - | __Vtemp_hfa8722fc__0[0x15U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] - | __Vtemp_hfa8722fc__0[0x16U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] - | __Vtemp_hfa8722fc__0[0x17U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] - | __Vtemp_hfa8722fc__0[0x18U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] - | __Vtemp_hfa8722fc__0[0x19U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] - | __Vtemp_hfa8722fc__0[0x1aU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] - | __Vtemp_hfa8722fc__0[0x1bU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] - | __Vtemp_hfa8722fc__0[0x1cU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] - | __Vtemp_hfa8722fc__0[0x1dU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] - | __Vtemp_hfa8722fc__0[0x1eU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] - | __Vtemp_hfa8722fc__0[0x1fU]); - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU]; - } - } else if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready))) { - __Vtemp_hc94fac31__1[0U] = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - __Vtemp_hc94fac31__1[1U] = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - __Vtemp_hc94fac31__1[2U] = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - __Vtemp_hc94fac31__1[3U] = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - __Vtemp_hc94fac31__1[4U] = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - __Vtemp_hc94fac31__1[5U] = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - __Vtemp_hc94fac31__1[6U] = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - __Vtemp_hc94fac31__1[7U] = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - __Vtemp_hc94fac31__1[8U] = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - __Vtemp_hc94fac31__1[9U] = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - __Vtemp_hc94fac31__1[0xaU] = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - __Vtemp_hc94fac31__1[0xbU] = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - __Vtemp_hc94fac31__1[0xcU] = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - __Vtemp_hc94fac31__1[0xdU] = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - __Vtemp_hc94fac31__1[0xeU] = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - __Vtemp_hc94fac31__1[0xfU] = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - __Vtemp_hc94fac31__1[0x10U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]; - __Vtemp_hc94fac31__1[0x11U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]; - __Vtemp_hc94fac31__1[0x12U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]; - __Vtemp_hc94fac31__1[0x13U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]; - __Vtemp_hc94fac31__1[0x14U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]; - __Vtemp_hc94fac31__1[0x15U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]; - __Vtemp_hc94fac31__1[0x16U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]; - __Vtemp_hc94fac31__1[0x17U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]; - __Vtemp_hc94fac31__1[0x18U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]; - __Vtemp_hc94fac31__1[0x19U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]; - __Vtemp_hc94fac31__1[0x1aU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]; - __Vtemp_hc94fac31__1[0x1bU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]; - __Vtemp_hc94fac31__1[0x1cU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]; - __Vtemp_hc94fac31__1[0x1dU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]; - __Vtemp_hc94fac31__1[0x1eU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]; - __Vtemp_hc94fac31__1[0x1fU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]; - VL_SHIFTR_WWI(1024,1024,32, __Vtemp_hb4dafc67__0, __Vtemp_hc94fac31__1, - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift) - << 3U)); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] - | __Vtemp_hb4dafc67__0[0U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] - | __Vtemp_hb4dafc67__0[1U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] - | __Vtemp_hb4dafc67__0[2U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] - | __Vtemp_hb4dafc67__0[3U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] - | __Vtemp_hb4dafc67__0[4U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] - | __Vtemp_hb4dafc67__0[5U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] - | __Vtemp_hb4dafc67__0[6U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] - | __Vtemp_hb4dafc67__0[7U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] - | __Vtemp_hb4dafc67__0[8U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] - | __Vtemp_hb4dafc67__0[9U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] - | __Vtemp_hb4dafc67__0[0xaU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] - | __Vtemp_hb4dafc67__0[0xbU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] - | __Vtemp_hb4dafc67__0[0xcU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] - | __Vtemp_hb4dafc67__0[0xdU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] - | __Vtemp_hb4dafc67__0[0xeU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] - | __Vtemp_hb4dafc67__0[0xfU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] - | __Vtemp_hb4dafc67__0[0x10U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] - | __Vtemp_hb4dafc67__0[0x11U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] - | __Vtemp_hb4dafc67__0[0x12U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] - | __Vtemp_hb4dafc67__0[0x13U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] - | __Vtemp_hb4dafc67__0[0x14U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] - | __Vtemp_hb4dafc67__0[0x15U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] - | __Vtemp_hb4dafc67__0[0x16U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] - | __Vtemp_hb4dafc67__0[0x17U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] - | __Vtemp_hb4dafc67__0[0x18U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] - | __Vtemp_hb4dafc67__0[0x19U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] - | __Vtemp_hb4dafc67__0[0x1aU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] - | __Vtemp_hb4dafc67__0[0x1bU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] - | __Vtemp_hb4dafc67__0[0x1cU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] - | __Vtemp_hb4dafc67__0[0x1dU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] - | __Vtemp_hb4dafc67__0[0x1eU]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] - | __Vtemp_hb4dafc67__0[0x1fU]); - } - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill - = (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U]); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xfU]; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready))) { - VL_SHIFTL_WWI(512,512,32, __Vtemp_h04488e48__0, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg, 8U); - VL_SHIFTL_WWI(512,512,32, __Vtemp_h0448bebe__0, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg, 0x10U); - VL_SHIFTL_WWI(512,512,32, __Vtemp_h0448985a__0, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg, 0x20U); - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } else if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill - = (0x7fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill) - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] - = __Vtemp_h04488e48__0[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] - = __Vtemp_h04488e48__0[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] - = __Vtemp_h04488e48__0[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] - = __Vtemp_h04488e48__0[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] - = __Vtemp_h04488e48__0[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] - = __Vtemp_h04488e48__0[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] - = __Vtemp_h04488e48__0[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] - = __Vtemp_h04488e48__0[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] - = __Vtemp_h04488e48__0[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] - = __Vtemp_h04488e48__0[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] - = __Vtemp_h04488e48__0[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] - = __Vtemp_h04488e48__0[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] - = __Vtemp_h04488e48__0[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] - = __Vtemp_h04488e48__0[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] - = __Vtemp_h04488e48__0[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] - = __Vtemp_h04488e48__0[0xfU]; - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill - = (0x7fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill) - - (IData)(2U))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] - = __Vtemp_h0448bebe__0[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] - = __Vtemp_h0448bebe__0[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] - = __Vtemp_h0448bebe__0[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] - = __Vtemp_h0448bebe__0[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] - = __Vtemp_h0448bebe__0[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] - = __Vtemp_h0448bebe__0[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] - = __Vtemp_h0448bebe__0[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] - = __Vtemp_h0448bebe__0[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] - = __Vtemp_h0448bebe__0[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] - = __Vtemp_h0448bebe__0[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] - = __Vtemp_h0448bebe__0[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] - = __Vtemp_h0448bebe__0[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] - = __Vtemp_h0448bebe__0[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] - = __Vtemp_h0448bebe__0[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] - = __Vtemp_h0448bebe__0[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] - = __Vtemp_h0448bebe__0[0xfU]; - } - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill - = (0x7fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill) - - (IData)(4U))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] - = __Vtemp_h0448985a__0[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] - = __Vtemp_h0448985a__0[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] - = __Vtemp_h0448985a__0[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] - = __Vtemp_h0448985a__0[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] - = __Vtemp_h0448985a__0[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] - = __Vtemp_h0448985a__0[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] - = __Vtemp_h0448985a__0[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] - = __Vtemp_h0448985a__0[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] - = __Vtemp_h0448985a__0[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] - = __Vtemp_h0448985a__0[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] - = __Vtemp_h0448985a__0[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] - = __Vtemp_h0448985a__0[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] - = __Vtemp_h0448985a__0[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] - = __Vtemp_h0448985a__0[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] - = __Vtemp_h0448985a__0[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] - = __Vtemp_h0448985a__0[0xfU]; - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill - = (0x7fU & 0U); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - } - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr) { - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[1U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU]; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0x10U] - = (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last) - << 7U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes)); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0 - = (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr)); - } - if (vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write) { - vlSelf->__Vdlyvval__main__DOT__console__DOT__txfifo__DOT__fifo__v0 - = vlSelf->main__DOT__console__DOT__txf_wb_data; - vlSelf->__Vdlyvset__main__DOT__console__DOT__txfifo__DOT__fifo__v0 = 1U; - vlSelf->__Vdlyvdim0__main__DOT__console__DOT__txfifo__DOT__fifo__v0 - = vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr; - } - if ((((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle = 0U; - } else if (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle)) - & (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid) - & ((3U == (0xfU & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - >> 4U))) | (0xdU - == - (0xfU - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - >> 4U))))) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready)) - & ((3U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn)) - | (0xdU == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn))))))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle = 1U; - } else { - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle = 0U; - } - if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)) - | ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_ready)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle = 0U; - } - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__rx_en = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en = 0U; - } else { - if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U))) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xbU) | - (2U == (3U - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 8U)))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = 0U; - } else if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 6U) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U))) - & ((2U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U))) | - (3U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr))); - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__rx_en = 0U; - } else if ((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__rx_en = 1U; - } - if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U))) & (((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xbU) - | (2U == (3U - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 8U)))) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - != (1U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xcU)))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = 0U; - } else if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U) & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U))) & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U))) - & ((2U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U))) | - (3U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))); - } - if ((1U & (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent)) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid = 0U; - } else if ((1U & (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid = 1U; - } - if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en = 0U; - } else if ((((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request; - } - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__rx_en = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en = 0U; - } else { - if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xbU) | - (2U == (3U - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 8U)))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = 0U; - } else if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 8U) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U))) - & ((2U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])) - | (3U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr))); - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__rx_en = 0U; - } else if ((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__rx_en = 1U; - } - if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))) & (((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xbU) - | (2U == (3U - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 8U)))) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - != (1U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xcU)))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = 0U; - } else if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U) & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U))) & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U))) - & ((2U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])) - | (3U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))); - } - if ((1U & (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent)) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid = 0U; - } else if ((1U & (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid = 1U; - } - if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en = 0U; - } else if ((((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request; - } - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & ((((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_wF) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - == (0xeU | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))) | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy))))); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted - = ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | ((IData)(vlSelf->main__DOT__swic__DOT__cmd_halt) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted) - | (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)) - & (~ (IData)((0U != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock))))) - & (((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal))))))); - __Vtableidx3 = (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count) - << 7U) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) - << 6U) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - << 5U) | - (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width) - << 3U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate) - << 1U) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset)))))); - if (Vmain__ConstPool__TABLE_h88ad91a4_0[__Vtableidx3]) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count - = Vmain__ConstPool__TABLE_h5f0541c3_0[__Vtableidx3]; - } - __Vtableidx6 = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count) - << 7U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) - << 6U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - << 5U) | - (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width) - << 3U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate) - << 1U) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset)))))); - if (Vmain__ConstPool__TABLE_h88ad91a4_0[__Vtableidx6]) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count - = Vmain__ConstPool__TABLE_h5f0541c3_0[__Vtableidx6]; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg - = (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)) - ? 0U : ((2U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg) - << 1U)) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge))); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg - = (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)) - ? 0U : ((2U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg) - << 1U)) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - ? 0U : ((0x3cU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg) - << 2U)) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pck_sreg - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - ? 0U : ((0x3cU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pck_sreg) - << 2U)) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge))); - __Vtableidx4 = (((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight) - << 4U) | ((8U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - << 2U)) | ((4U - & ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - << 1U)) - | (((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - << 1U) - | (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc))))); - if (Vmain__ConstPool__TABLE_hd397e023_0[__Vtableidx4]) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__inflight - = Vmain__ConstPool__TABLE_h9becc847_0[__Vtableidx4]; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ign_mem_cyc = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_stb = 0U; - } else if (vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_stb - = (1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__last_stb))); - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__last_stb) - & (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight) - + ((IData)(vlSelf->main__DOT__u_fan__DOT__mem_stb) - ? 1U : 0U)) == ((IData)(vlSelf->main__DOT__u_fan__DOT__mem_ack) - ? 1U : 0U)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ign_mem_cyc = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_stb = 0U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__ign_mem_cyc = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_stb = 0U; - } - } else if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle)) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_illegal))))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_stb = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__ign_mem_cyc = 1U; - } - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - & (((0xfffffffeU & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (((~ (IData)(vlSelf->cpu_sim_cyc)) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)) - << 1U))) | ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack))) - >> vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U])); - if ((4U & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack = 0U; - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__wbu_cyc))) - | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack = 0U; - } - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb - = ((~ ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb))) - & ((2U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - ? ((0x88U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done))) - : ((0x30U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done))))); - if ((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending - = (1U & (((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce))) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped))))); - } - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb - = ((~ ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb))) - & ((2U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - ? ((0x88U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done))) - : ((0x30U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done))))); - if (vlSelf->main__DOT__i2ci__DOT__cpu_new_pc) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_insn_addr - = vlSelf->main__DOT__i2ci__DOT__pf_jump_addr; - vlSelf->__Vdly__main__DOT__wbwide_i2cm_addr - = (0x3fffffU & (vlSelf->main__DOT__i2ci__DOT__pf_jump_addr - >> 6U)); - } else { - if (((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_insn_addr = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_insn_addr - = (0xfffffffU & ((IData)(1U) + vlSelf->main__DOT__i2ci__DOT__pf_insn_addr)); - } - if (((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - & (~ ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 1U)))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cm_addr - = (0x3fffffU & ((IData)(1U) + vlSelf->main__DOT__wbwide_i2cm_addr)); - } - } - if ((((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_abort))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__imm_cycle = 0U; - } else if (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle)) - & (((IData)(vlSelf->main__DOT__i2ci__DOT__next_valid) - & ((3U == (0xfU & ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - >> 4U))) | (0xdU - == - (0xfU - & ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - >> 4U))))) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready)) - & ((3U == (IData)(vlSelf->main__DOT__i2ci__DOT__half_insn)) - | (0xdU == (IData)(vlSelf->main__DOT__i2ci__DOT__half_insn))))))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__imm_cycle = 1U; - } else { - if (vlSelf->main__DOT__i2ci__DOT__bus_jump) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__imm_cycle = 0U; - } - if ((((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - | ((IData)(vlSelf->main__DOT__i2ci__DOT__bus_override) - & (IData)(vlSelf->main__DOT__i2ci__DOT__ovw_ready)))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__imm_cycle = 0U; - } - } - if ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog)) - & (0U != ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U)))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout = 0x7fffffU; - } else if ((0U != vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout)) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog - = (1U >= vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout - = (0x7fffffU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout - - (IData)(1U))); - } - if ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog)) - & (0U != ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout = 0x7fffffU; - } else if ((0U != vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout)) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog - = (1U >= vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout - = (0x7fffffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout - - (IData)(1U))); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)))) { - if (((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid)))) { - VL_SHIFTL_WWI(512,512,32, __Vtemp_h434d0da1__0, vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word, 8U); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0U] - = __Vtemp_h434d0da1__0[0U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[1U] - = __Vtemp_h434d0da1__0[1U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[2U] - = __Vtemp_h434d0da1__0[2U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[3U] - = __Vtemp_h434d0da1__0[3U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[4U] - = __Vtemp_h434d0da1__0[4U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[5U] - = __Vtemp_h434d0da1__0[5U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[6U] - = __Vtemp_h434d0da1__0[6U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[7U] - = __Vtemp_h434d0da1__0[7U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[8U] - = __Vtemp_h434d0da1__0[8U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[9U] - = __Vtemp_h434d0da1__0[9U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xaU] - = __Vtemp_h434d0da1__0[0xaU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xbU] - = __Vtemp_h434d0da1__0[0xbU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xcU] - = __Vtemp_h434d0da1__0[0xcU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xdU] - = __Vtemp_h434d0da1__0[0xdU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xeU] - = __Vtemp_h434d0da1__0[0xeU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU] - = __Vtemp_h434d0da1__0[0xfU]; - } else if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U) & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid))))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x10U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[1U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x11U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[2U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x12U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[3U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x13U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[4U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x14U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[5U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x15U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[6U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x16U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[7U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x17U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[8U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x18U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[9U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x19U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xaU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1aU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xbU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1bU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xcU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1cU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xdU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1dU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xeU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1eU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1fU]; - VL_SHIFTL_WWI(512,512,32, __Vtemp_hfc2bf96b__0, vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted, 8U); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0U] - = __Vtemp_hfc2bf96b__0[0U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[1U] - = __Vtemp_hfc2bf96b__0[1U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[2U] - = __Vtemp_hfc2bf96b__0[2U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[3U] - = __Vtemp_hfc2bf96b__0[3U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[4U] - = __Vtemp_hfc2bf96b__0[4U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[5U] - = __Vtemp_hfc2bf96b__0[5U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[6U] - = __Vtemp_hfc2bf96b__0[6U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[7U] - = __Vtemp_hfc2bf96b__0[7U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[8U] - = __Vtemp_hfc2bf96b__0[8U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[9U] - = __Vtemp_hfc2bf96b__0[9U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xaU] - = __Vtemp_hfc2bf96b__0[0xaU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xbU] - = __Vtemp_hfc2bf96b__0[0xbU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xcU] - = __Vtemp_hfc2bf96b__0[0xcU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xdU] - = __Vtemp_hfc2bf96b__0[0xdU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xeU] - = __Vtemp_hfc2bf96b__0[0xeU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU] - = __Vtemp_hfc2bf96b__0[0xfU]; - } else { - VL_SHIFTL_WWI(512,512,32, __Vtemp_h02cc08c7__0, vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn, 8U); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0U] - = __Vtemp_h02cc08c7__0[0U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[1U] - = __Vtemp_h02cc08c7__0[1U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[2U] - = __Vtemp_h02cc08c7__0[2U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[3U] - = __Vtemp_h02cc08c7__0[3U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[4U] - = __Vtemp_h02cc08c7__0[4U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[5U] - = __Vtemp_h02cc08c7__0[5U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[6U] - = __Vtemp_h02cc08c7__0[6U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[7U] - = __Vtemp_h02cc08c7__0[7U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[8U] - = __Vtemp_h02cc08c7__0[8U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[9U] - = __Vtemp_h02cc08c7__0[9U]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xaU] - = __Vtemp_h02cc08c7__0[0xaU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xbU] - = __Vtemp_h02cc08c7__0[0xbU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xcU] - = __Vtemp_h02cc08c7__0[0xcU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xdU] - = __Vtemp_h02cc08c7__0[0xdU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xeU] - = __Vtemp_h02cc08c7__0[0xeU]; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU] - = __Vtemp_h02cc08c7__0[0xfU]; - } - } - if (((((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort)) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err)) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 0U; - } else if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy) { - if ((1U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state))) { - if ((0U == vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length)) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy = 0U; - } else if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 2U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 1U; - } - } else if ((2U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state))) { - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 0U; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request))))) { - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - = (0xfffffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen))); - } - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length - = ((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length - > (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen)) - ? (0xfffffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen))) - : 0U); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 3U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request = 1U; - } - } else if ((3U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state))) { - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request = 0U; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request))))) { - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 2U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 1U; - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen) - > vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length)) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen - = (0x7ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length); - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr - = (0xfffffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen))); - } - if ((0U == vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length)) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy = 0U; - } - } - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen - = (0x7ffU & ((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length - < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen)) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length - : (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 0U; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy = 1U; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 2U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 1U; - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = 0U; - } - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length; - } - } - if ((1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg = 0ULL; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg = 0xffffffffffffffffULL; - if ((0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if ((1U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]; - } - } - } - if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w; - } - } else if ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]; - } - } - } - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = 0xffffU; - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x1fU); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x1eU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x1dU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x1cU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x1bU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x1aU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x19U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x18U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x17U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x16U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x15U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x14U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x13U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x12U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x11U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0xfU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0xeU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0xdU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0xcU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0xbU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 0xaU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 9U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 8U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & (__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit - = (1U & __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__i_crc_data); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__44__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__fill; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__43__Vfuncout; - } - } - } else if (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - & (1U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - & (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U]; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - = (0xffffffffULL | ((QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg)) - << 0x20U)); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = 0xffffU; - } - if (vlSelf->main__DOT__u_emmc__DOT__rx_en) { - if ((0U != ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - = ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((3U == ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U)) ? ((0xffffcU - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 2U)) - | (2U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - << 1U))) - : ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - ? ((0xffffeU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 1U)) - | (1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data))) - : (0xffffeU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 1U)))) - : ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((3U == ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U)) ? ((0xfff00U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 8U)) - | (0xf0U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - << 4U))) - : ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - ? ((0xffff0U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 4U)) - | (0xfU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data))) - : (0xffff0U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 4U)))) - : ((3U == ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U)) ? ((0xf0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 0x10U)) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - << 8U)) - : ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - ? ((0xfff00U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 8U)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data)) - : (0xfff00U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 8U)))))); - } - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg = 0U; - } - if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg = 0ULL; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg = 0xffffffffffffffffULL; - if ((0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if ((1U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]; - } - } - } - if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w; - } - } else if ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]; - } - } - } - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = 0xffffU; - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x1fU); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x1eU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x1dU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x1cU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x1bU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x1aU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x19U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x18U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x17U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x16U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x15U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x14U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x13U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x12U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x11U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0xfU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0xeU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0xdU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0xcU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0xbU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 0xaU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 9U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 8U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & (__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit - = (1U & __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__i_crc_data); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__86__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__fill; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC32__85__Vfuncout; - } - } - } else if (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - & (1U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U]; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - = (0xffffffffULL | ((QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg)) - << 0x20U)); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = 0xffffU; - } - if (vlSelf->main__DOT__u_sdcard__DOT__rx_en) { - if ((0U != ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - = ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((3U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U)) ? ((0xffffcU - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 2U)) - | (2U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - << 1U))) - : ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - ? ((0xffffeU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 1U)) - | (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data))) - : (0xffffeU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 1U)))) - : ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((3U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U)) ? ((0xfff00U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 8U)) - | (0xf0U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - << 4U))) - : ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - ? ((0xffff0U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 4U)) - | (0xfU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data))) - : (0xffff0U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 4U)))) - : ((3U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U)) ? ((0xf0000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 0x10U)) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - << 8U)) - : ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - ? ((0xfff00U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 8U)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data)) - : (0xfff00U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 8U)))))); - } - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg = 0U; - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset) - | (IData)(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_valid = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_illegal = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count = 0U; - } else { - if ((((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - >> 1U))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid - = (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid))); - } else if (((IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid)))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid = 0U; - } - if (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - >> 1U))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_valid = 1U; - } else if (vlSelf->main__DOT__i2ci__DOT__pf_ready) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_valid - = ((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid) - | (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid)); - } - if ((1U & (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid)) - & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready))) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_illegal))))) { - if (vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_illegal - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal; - } else if (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 1U))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_illegal = 1U; - } - } - if (vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__r_valid) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid - = (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - | (1U < (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count)))); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid = 0U; - if (vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid = 1U; - } - if ((((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U)) & (~ (IData)((0x3fU == (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift)))))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid = 1U; - } - } - if ((((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count - = (0x7fU & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count) - - (IData)(1U))); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid)) - | ((IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid)))))) { - if (vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count = 0x3fU; - } else if (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count - = (0x3fU & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift))); - } - } - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc - = ((4U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc)) - ? ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc)) - ? 0x4000000U : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc)) - ? (0xffffffcU - & (((IData)(1U) - + (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc - >> 2U)) - << 2U)) : - (0xffffffcU & ( - ((IData)(1U) - + - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc - >> 2U)) - << 2U)))) - : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc)) - ? (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - : (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc)) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc)) - ? (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl) - : 0x4000000U))); - } - if ((1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill = 0U; - } else if ((1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type) - | (7U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))) { - if ((3U == ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) - << 1U))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__i_bit - = vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__fill - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__33__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__Vfuncout - = ((0x40U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__fill)) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__fill) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__32__Vfuncout; - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__i_bit - = vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__fill - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__fill) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__34__Vfuncout; - } - } - if ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg = 0ULL; - } else { - if ((0xc0U > (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count - = (0xffU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count) - + ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) - ? 1U : 0U))); - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - = ((0xfffffffffeULL & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - << 1U)) | (QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data))); - } - } - if ((1U & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = 0x3ffffffU; - } else if (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout)) - & (0U != ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) - << 1U)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = 0x3ffffffU; - } else { - if ((0U != vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter)) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter - = (0x3ffffffU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter - - (IData)(1U))); - } - if ((1U >= vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter)) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = 1U; - } - } - if ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg = 0ULL; - } else { - if ((0xc0U > (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count - = (0xffU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count) - + ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) - ? 1U : 0U))); - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - = ((0xfffffffffeULL & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - << 1U)) | (QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data))); - } - } - if ((1U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = 0x3ffffffU; - } else if (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout)) - & (0U != ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) - << 1U)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = 0x3ffffffU; - } else { - if ((0U != vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter)) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter - = (0x3ffffffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter - - (IData)(1U))); - } - if ((1U >= vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter)) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = 1U; - } - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg = 0xffffffffffffULL; - } else { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy) { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy = 0U; - } - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy - = (((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - & (0U < (0x1fffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk))))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done))); - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - = (((QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd)) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x27U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit) - ? 9U : 0U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x26U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x25U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x24U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x23U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x22U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x21U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x20U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x1fU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x1eU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x1dU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x1cU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x1bU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x1aU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x19U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x18U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x17U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x16U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x15U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x14U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x13U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x12U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x11U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0x10U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0xfU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0xeU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0xdU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0xcU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0xbU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 0xaU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 9U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 8U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 7U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 6U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 5U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 4U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 3U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 2U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd - >> 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__cmd)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__fill) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__31__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__fill; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - = (((QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd)) - << 0x28U) | (((QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg)) - << 8U) | (QData)((IData)( - (1U - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__30__Vfuncout) - << 1U)))))); - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl) - ? (3ULL | (0xfffffffffffcULL & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - << 2U))) : (1ULL | - (0xfffffffffffeULL - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - << 1U)))); - } - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg = 0xffffffffffffULL; - } else { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy = 0U; - } - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - & (0U < (0x1fffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk))))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done))); - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - = (((QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd)) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x27U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit) - ? 9U : 0U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x26U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x25U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x24U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x23U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x22U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x21U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x20U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x1fU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x1eU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x1dU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x1cU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x1bU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x1aU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x19U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x18U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x17U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x16U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x15U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x14U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x13U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x12U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x11U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0x10U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0xfU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0xeU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0xdU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0xcU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0xbU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 0xaU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 9U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 8U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 7U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 6U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 5U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 4U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 3U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 2U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)((__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd - >> 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__cmd)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__73__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__fill; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - = (((QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd)) - << 0x28U) | (((QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg)) - << 8U) | (QData)((IData)( - (1U - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__CMDCRC__72__Vfuncout) - << 1U)))))); - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl) - ? (3ULL | (0xfffffffffffcULL & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - << 2U))) : (1ULL | - (0xfffffffffffeULL - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - << 1U)))); - } - } - if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill = 0U; - } else if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type) - | (7U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))) { - if ((3U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) - << 1U))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__i_bit - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__fill - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__fill) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__75__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__Vfuncout - = ((0x40U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__fill)) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__fill) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__74__Vfuncout; - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__i_bit - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__fill - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__fill) - >> 6U) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__i_bit))) - ? (9U ^ (0x7eU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__fill) - << 1U))) : (0x7eU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__fill) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__STEPCRC__76__Vfuncout; - } - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset) - | ((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 1U)))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cm_cyc = 0U; - vlSelf->__Vdly__main__DOT__wbwide_i2cm_stb = 0U; - } else if (vlSelf->main__DOT__wbwide_i2cm_cyc) { - if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_i2cm_stb)) - | (~ ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 1U))))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cm_stb - = (1U & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__last_stb))); - } - if (((((~ (IData)(vlSelf->main__DOT__wbwide_i2cm_stb)) - | (~ ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 1U))) & (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__last_stb)) - & (((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight) - + ((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - ? 1U : 0U)) == ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)) - ? 1U : 0U)))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cm_cyc = 0U; - vlSelf->__Vdly__main__DOT__wbwide_i2cm_stb = 0U; - } - if (vlSelf->main__DOT__i2ci__DOT__cpu_new_pc) { - vlSelf->__Vdly__main__DOT__wbwide_i2cm_cyc = 0U; - vlSelf->__Vdly__main__DOT__wbwide_i2cm_stb = 0U; - } - } else if ((((IData)(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc) - | (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle)) - | ((((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid))) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal))))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cm_cyc = 1U; - vlSelf->__Vdly__main__DOT__wbwide_i2cm_stb = 1U; - } - if (((IData)(vlSelf->main__DOT__u_i2cdma__DOT__r_reset) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__bus_err))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_sel - = (0x8000000000000000ULL >> (0x3fU & vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr)); - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_addr - = (0x3fffffU & (vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr - >> 6U)); - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__subaddr - = (0x3fU & vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr); - } else if ((((~ (IData)(vlSelf->main__DOT__wbwide_i2cdma_stb)) - | (~ (IData)(vlSelf->__VdfgTmp_h503d14d1__0))) - & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT__wb_last) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__r_overflow)))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_sel - = (0x8000000000000000ULL >> (0x3fU & vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr)); - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_addr - = (0x3fffffU & (vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr - >> 6U)); - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__subaddr - = (0x3fU & vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr); - } else { - if (((IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid) - & (IData)(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_sel - = (((QData)((IData)((1U & (IData)(vlSelf->main__DOT__wbwide_i2cdma_sel)))) - << 0x3fU) | (vlSelf->main__DOT__wbwide_i2cdma_sel - >> 1U)); - } - if ((((IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid) - & (IData)(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready)) - & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__r_overflow)))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_addr - = (0x3fffffU & (((IData)(1U) + ((vlSelf->main__DOT__wbwide_i2cdma_addr - << 6U) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__subaddr))) - >> 6U)); - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__subaddr - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_i2cdma__DOT__subaddr))); - } - } - if ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (2U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type))) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr = 0U; - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr))); - } - if ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (2U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type))) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr = 0U; - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr))); - } - if (vlSelf->main__DOT__u_i2cdma__DOT__r_reset) { - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__r_overflow = 0U; - } else if ((((~ (IData)(vlSelf->main__DOT__wbwide_i2cdma_stb)) - | (~ (IData)(vlSelf->__VdfgTmp_h503d14d1__0))) - & (IData)(vlSelf->main__DOT__u_i2cdma__DOT__wb_last))) { - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__r_overflow = 0U; - } else if ((((IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid) - & (IData)(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready)) - & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - >> 8U))) { - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__r_overflow = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__r_overflow)))) { - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__r_overflow - = ((((IData)(1U) + ((vlSelf->main__DOT__wbwide_i2cdma_addr - << 6U) | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__subaddr))) - - vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr) - >= vlSelf->main__DOT__u_i2cdma__DOT__r_memlen); - } - if ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill = 0U; - } else if ((0U == ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill - = (7U & (IData)(vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)); - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill - = (0x1fU & ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((7U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)) - + ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - ? 1U : 0U)) : ((1U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ( - (7U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)) - + - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - ? 4U - : 0U)) - : ( - (7U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)) - + - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - ? 8U - : 0U))))); - } - if ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill = 0U; - } else if ((0U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill - = (7U & (IData)(vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)); - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill - = (0x1fU & ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((7U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)) - + ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - ? 1U : 0U)) : ((1U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ( - (7U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)) - + - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - ? 4U - : 0U)) - : ( - (7U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)) - + - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - ? 8U - : 0U))))); - } - if ((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) { - if ((1U & ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]))) { - if ((1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)) - | (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = ((6U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)) - | (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]] & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]))))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (6U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (6U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } - if ((1U & ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_err)))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (6U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) { - if ((1U & ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 1U)) | (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> 1U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = ((5U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)) - | (2U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]] & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U])) - << 1U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (5U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (5U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } - if ((1U & ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_err) - >> 1U)))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (5U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) { - if ((1U & ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 2U)) | (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> 2U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = ((3U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)) - | (4U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]] & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U])) - << 2U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (3U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (3U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } - if ((1U & ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_err) - >> 2U)))) { - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb - = (3U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb)); - } -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__0__Slow.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__0__Slow.cpp deleted file mode 100644 index 691d7c2..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__0__Slow.cpp +++ /dev/null @@ -1,10881 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -VL_ATTR_COLD void Vmain___024root___eval_static__TOP(Vmain___024root* vlSelf); - -VL_ATTR_COLD void Vmain___024root___eval_static(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_static\n"); ); - // Body - Vmain___024root___eval_static__TOP(vlSelf); - vlSelf->__Vm_traceActivity[6U] = 1U; - vlSelf->__Vm_traceActivity[5U] = 1U; - vlSelf->__Vm_traceActivity[4U] = 1U; - vlSelf->__Vm_traceActivity[3U] = 1U; - vlSelf->__Vm_traceActivity[2U] = 1U; - vlSelf->__Vm_traceActivity[1U] = 1U; - vlSelf->__Vm_traceActivity[0U] = 1U; -} - -VL_ATTR_COLD void Vmain___024root___eval_static__TOP(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_static__TOP\n"); ); - // Body - vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction = 0x4380005U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter = 5U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_aux = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_dm = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_col = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt_q = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__initial_dqs = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__lane = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8 = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_stb = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dq = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_stb = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_update = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_data = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_sel = 0U; - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_zero = 1U; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_zero = 1U; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero = 1U; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero = 1U; -} - -VL_ATTR_COLD void Vmain___024root___eval_initial__TOP(Vmain___024root* vlSelf); - -VL_ATTR_COLD void Vmain___024root___eval_initial(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_initial\n"); ); - // Body - Vmain___024root___eval_initial__TOP(vlSelf); - vlSelf->__Vm_traceActivity[6U] = 1U; - vlSelf->__Vm_traceActivity[5U] = 1U; - vlSelf->__Vm_traceActivity[4U] = 1U; - vlSelf->__Vm_traceActivity[3U] = 1U; - vlSelf->__Vm_traceActivity[2U] = 1U; - vlSelf->__Vm_traceActivity[1U] = 1U; - vlSelf->__Vm_traceActivity[0U] = 1U; - vlSelf->__Vtrigprevexpr___TOP__i_clk__0 = vlSelf->i_clk; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n__0 - = vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n; -} - -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0; - -VL_ATTR_COLD void Vmain___024root___eval_initial__TOP(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_initial__TOP\n"); ); - // Body - vlSelf->main__DOT__wbwide_xbar__DOT__iM = 3U; - vlSelf->main__DOT__wbwide_xbar__DOT__iN = 4U; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM = 3U; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__iM = 3U; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__iM = 3U; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__iM = 3U; - vlSelf->main__DOT__wb32_xbar__DOT__iN = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xffeU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xffdU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xffbU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xff7U & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xfefU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xfdfU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xfbfU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xf7fU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xeffU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xdffU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0xbffU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__requested[0U] - = (0x7ffU & vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wb32_xbar__DOT__iM = 0xcU; - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM = 0xcU; - vlSelf->main__DOT__wbu_xbar__DOT__iN = 1U; - vlSelf->main__DOT__wbu_xbar__DOT__requested[0U] - = (2U & vlSelf->main__DOT__wbu_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wbu_xbar__DOT__requested[0U] - = (1U & vlSelf->main__DOT__wbu_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wbu_xbar__DOT__iM = 2U; - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM = 2U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__ik = 0x40U; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k = 0U; - while (VL_GTS_III(32, 0x80U, vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k)) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv = 0x40U; - if ((VL_LTES_III(32, 0x30U, vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k) - & VL_GTES_III(32, 0x39U, vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv - = (0x7fU & vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv - = (0x40U | (0xfU & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv))); - } else { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv - = ((VL_LTES_III(32, 0x41U, vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k) - & VL_GTES_III(32, 0x5aU, vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k)) - ? (0x40U | (0x3fU & ((IData)(9U) - + vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k))) - : ((VL_LTES_III(32, 0x61U, vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k) - & VL_GTES_III(32, 0x7aU, vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k)) - ? ((0x40U & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv)) - | (0x3fU & ((IData)(3U) - + vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k))) - : ((0x40U == vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k) - ? (0x3eU | (0x40U & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv))) - : ((0x25U == vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k) - ? (0x3fU | (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv)) - : 0U)))); - } - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__remap[(0x7fU - & vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k)] - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k - = ((IData)(1U) + vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k); - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k = 0U; - while (VL_GTS_III(32, 0x80U, vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k)) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__newv - = (VL_LTES_III(32, 0x40U, vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k) - ? 0xaU : (0x7fU & ((9U >= vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k) - ? ((IData)(0x30U) - + (0xfU & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k)) - : ((0x23U >= (0x3fU - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k)) - ? ((IData)(0x37U) - + (0x3fU - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k)) - : ((0x3dU >= - (0x3fU - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k)) - ? ((IData)(0x3dU) - + (0x3fU - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k)) - : ((0x3eU - == - (0x3fU - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k)) - ? 0x40U - : 0x25U)))))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__remap[(0x7fU - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k)] - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__newv; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k - = ((IData)(1U) + vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k); - } - vlSelf->main__DOT__wbu_xbar__DOT__s_data[2U] = 0U; - vlSelf->main__DOT__wbu_xbar__DOT__s_data[3U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0xaU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0xcU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0xdU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0xeU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0xfU] = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[3U][0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__sindex[3U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[0U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[1U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[2U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[3U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[4U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[5U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[6U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[7U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[8U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[9U] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[0xaU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[0xbU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[0xcU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[0xdU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[0xeU] = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__sindex[0xfU] = 0U; - vlSelf->main__DOT__wbu_xbar__DOT__sindex[0U] = 0U; - vlSelf->main__DOT__wbu_xbar__DOT__sindex[1U] = 0U; - vlSelf->main__DOT__wbu_xbar__DOT__sindex[2U] = 0U; - vlSelf->main__DOT__wbu_xbar__DOT__sindex[3U] = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0xcU] = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[4U] = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0xdU] = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[5U] = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0xeU] = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[6U] = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0xfU] = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[7U] = 0U; - vlSelf->main__DOT__r_wb32_sio_ack = 0U; - vlSelf->main__DOT__r_sirefclk_en = 0U; - vlSelf->main__DOT__r_sirefclk_data = 0x4e20U; - vlSelf->main__DOT__r_cfg_ack = 0U; - vlSelf->o_wbu_uart_cts_n = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__sgrant = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__grant[0U] = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant = (0xeU - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - vlSelf->main__DOT__wbwide_xbar__DOT__grant[1U] = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant = (0xdU - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - vlSelf->main__DOT__wbwide_xbar__DOT__grant[2U] = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant = (0xbU - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - vlSelf->main__DOT__wbwide_xbar__DOT__grant[3U] = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant = (7U - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc - = (6U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb - = (6U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc - = (5U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb - = (5U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc - = (3U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb - = (3U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mempty = (1U - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull)); - vlSelf->main__DOT__wbwide_xbar__DOT__mfull = (0xeU - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mempty = (2U - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull)); - vlSelf->main__DOT__wbwide_xbar__DOT__mfull = (0xdU - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mempty = (4U - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull)); - vlSelf->main__DOT__wbwide_xbar__DOT__mfull = (0xbU - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mempty = (8U - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull)); - vlSelf->main__DOT__wbwide_xbar__DOT__mfull = (7U - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U] = 0U; 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- vlSelf->main__DOT__sdioscopei__DOT__br_level_interrupt = 0U; - vlSelf->o_ddr3_controller_bitslip = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = (0xfeU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = (0xfeU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = (0xfdU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = (0xfdU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = (0xfbU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = (0xfbU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = (0xf7U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = (0xf7U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = (0xefU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = (0xefU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = (0xdfU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = (0xdfU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = (0xbfU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = (0xbfU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = (0x7fU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = (0x7fU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[1U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] = 0xffffffU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] = 0xffffffU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] = 0xffffffU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] = 0xffffffU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[0U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[0U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[1U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[1U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[2U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[2U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[3U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[3U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[4U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[4U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[5U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[5U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[6U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[6U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[7U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[7U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 8U; - VL_WRITEF("TEST FUNCTIONS\n-----------------------------\n\nTest ns_to_cycles() function:\n"); - VL_WRITEF("\tns_to_cycles(15) = 2 [exact]\n"); - VL_WRITEF("\tns_to_cycles(14.5) = 2 [round-off]\n"); - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = 2U; - VL_WRITEF("\tns_to_cycles(11) = 2 [round-up]\n\nTest nCK_to_cycles() function:\n"); - VL_WRITEF("\tns_to_cycles(16) = 4 [exact]\n"); - VL_WRITEF("\tns_to_cycles(15) = 4 [round-off]\n"); - vlSelf->main__DOT__ddr3_controller_inst__DOT__nCK_to_cycles__Vstatic__result = 4U; - VL_WRITEF("\tns_to_cycles(13) = 4 [round-up]\n\nTest ns_to_nCK() function:\n"); - VL_WRITEF("\tns_to_cycles(15) = 6 [exact]\n"); - VL_WRITEF("\tns_to_cycles(14.875) = 6 [round-off]\n"); - VL_WRITEF("\tns_to_cycles(13.875) = 6 [round-up] \n\nTest nCK_to_ns() function:\n"); - VL_WRITEF("\tns_to_cycles(4) = 10.000000 [exact]\n"); - VL_WRITEF("\tns_to_cycles(14.875) = 8.000000 [round-off]\n"); - VL_WRITEF("\tns_to_cycles(13.875) = 13.000000 [round-up]\n\nTest nCK_to_ns() function:\n"); - VL_WRITEF("\tns_to_cycles(4) = 10.000000 [exact]\n"); - VL_WRITEF("\tns_to_cycles(14.875) = 8.000000 [round-off]\n"); - VL_WRITEF("\tns_to_cycles(13.875) = 13.000000 [round-up]\n\n"); - VL_WRITEF("Test $floor() function:\n\t$floor(5/2) = 2.000000\n\t$floor(9/4) = 2.000000\n\t$floor(9/4) = 2.000000\n\t$floor(9/5) = 1.000000\n\n\nDISPLAY CONTROLLER PARAMETERS\n-----------------------------\n\nCONTROLLER_CLK_PERIOD = 10.00\nDDR3_CLK_PERIOD = 2.50\nROW_BITS = 14\nCOL_BITS = 10\nBA_BITS = 3\nDQ_BITS = 8\nLANES = 8\nAUX_WIDTH = 1\nWB2_ADDR_BITS = 32\nWB2_DATA_BITS = 32\nserdes_ratio = 4\nwb_addr_bits = 21\nwb_data_bits = 512\nwb_sel_bits = 64\nwb2_sel_bits = 4\ncmd_len = 24\nDELAY_COUNTER_WIDTH = 16\nDELAY_SLOT_WIDTH = 19\n"); - VL_WRITEF("serdes_ratio = 4\nwb_addr_bits = 21\nwb_data_bits = 512\nwb_sel_bits = 64\n\n\nREAD_SLOT = 2\nWRITE_SLOT = 3\nACTIVATE_SLOT = 0\nPRECHARGE_SLOT = 1\n\n\nDELAYS:\n"); - VL_WRITEF("\tns_to_nCK(tRCD): 6\n"); - VL_WRITEF("\tns_to_nCK(tRP): 6\n"); - VL_WRITEF("\tns_to_nCK(tRTP): 4\n\ttCCD: 4\n\t(CL_nCK + tCCD + 2 - CWL_nCK): 7\n"); - VL_WRITEF("\t(CWL_nCK + 4 + ns_to_nCK(tWR)): 15\n"); - VL_WRITEF("\t(CWL_nCK + 4 + ns_to_nCK(tWTR)): 13\n\n\nPRECHARGE_TO_ACTIVATE_DELAY = 1\nACTIVATE_TO_WRITE_DELAY = 0\nACTIVATE_TO_READ_DELAY = 0\nREAD_TO_WRITE_DELAY = 1\nREAD_TO_READ_DELAY = 0\nREAD_TO_PRECHARGE_DELAY = 1\nWRITE_TO_WRITE_DELAY = 0\nWRITE_TO_READ_DELAY = 3\nWRITE_TO_PRECHARGE_DELAY = 4\nSTAGE2_DATA_DEPTH = 2\nREAD_ACK_PIPE_WIDTH = 5\n"); - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_wstb = 0U; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_stb = 0U; - vlSelf->main__DOT__wbwide_bkram_ack = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__r_memlen = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__r_reset = 1U; - vlSelf->main__DOT__wb32_i2cdma_ack = 0U; - vlSelf->main__DOT__wb32_i2cdma_idata = 0U; - vlSelf->main__DOT__wbwide_i2cdma_cyc = 0U; - vlSelf->main__DOT__wbwide_i2cdma_stb = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_data = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid = 0U; - vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data = 0U; - vlSelf->main__DOT__u_fan__DOT__ctl_fpga = 0x1387U; - vlSelf->main__DOT__u_fan__DOT__ctl_sys = 0x1387U; - vlSelf->main__DOT__u_fan__DOT__pre_ack = 0U; - vlSelf->main__DOT__wb32_fan_ack = 0U; - vlSelf->main__DOT__u_fan__DOT__i2c_wb_ack = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda = 1U; - vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc = 0U; - vlSelf->main__DOT__u_fan__DOT__mem_stb = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle = 0U; - vlSelf->main__DOT__u_fan__DOT__mem_addr = 0x1fU; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_illegal = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_scl = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_scl = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__stop_bit = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg = 0xffU; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = 0U; - vlSelf->main__DOT__u_emmc__DOT__rx_en = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk = 9U; - vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift = 0x18U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90 = 0U; - vlSelf->main__DOT__u_emmc__DOT__pp_cmd = 0U; - vlSelf->main__DOT__u_emmc__DOT__pp_data = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds = 0U; - vlSelf->main__DOT__u_emmc__DOT__cfg_ddr = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = 0xfcU; - vlSelf->main__DOT__emmc_int = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = 0U; - vlSelf->main__DOT__wb32_emmc_ack = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_ack = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_half = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__w_sdclk = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_id = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_arg = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = 0x3ffffffU; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data = 0xffffffffU; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data = 0xffffffffU; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck = 0U; - vlSelf->main__DOT__wb32_i2cs_ack = 0U; - vlSelf->main__DOT__i2ci__DOT__half_valid = 0U; - vlSelf->main__DOT__i2ci__DOT__imm_cycle = 0U; - vlSelf->main__DOT__i2ci__DOT__insn_valid = 0U; - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual = 0U; - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl = 1U; - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda = 1U; - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl = 1U; - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda = 1U; - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid = 0U; - vlSelf->main__DOT__wbwide_i2cm_cyc = 0U; - vlSelf->main__DOT__wbwide_i2cm_stb = 0U; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight = 0U; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle = 0U; - vlSelf->main__DOT__wbwide_i2cm_addr = 0x3fffffU; - vlSelf->main__DOT__i2ci__DOT__pf_valid = 0U; - vlSelf->main__DOT__i2ci__DOT__pf_illegal = 0U; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid = 0U; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_scl = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_scl = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_sda = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_sda = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__stop_bit = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg = 0xffU; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->main__DOT__i2ci__DOT__i2c_abort = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_we = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[1U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[2U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[3U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[4U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[5U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[6U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[7U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[8U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[9U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xaU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xbU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xcU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xdU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xeU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xfU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel = 0ULL; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_full = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = 0U; - vlSelf->main__DOT__u_sdcard__DOT__rx_en = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk = 9U; - vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift = 0x18U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90 = 0U; - vlSelf->main__DOT__u_sdcard__DOT__pp_cmd = 0U; - vlSelf->main__DOT__u_sdcard__DOT__pp_data = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds = 0U; - vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = 0xfcU; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_removed = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present = 0U; - vlSelf->main__DOT__sdcard_int = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = 0U; - vlSelf->main__DOT__wb32_sdcard_ack = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_ack = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = 0x3ffffffU; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data = 0xffffffffU; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data = 0xffffffffU; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__high_z = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z = 1U; - vlSelf->main__DOT__console__DOT__rxf_wb_read = 0U; - vlSelf->main__DOT__console__DOT__rx_uart_reset = 1U; - vlSelf->main__DOT__console__DOT__txf_wb_write = 0U; - vlSelf->main__DOT__console__DOT__tx_uart_reset = 1U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow = 0U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr = 0U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow = 1U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr = 0U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next = 1U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__osrc = 0U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill = 0U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow = 0U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr = 0U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow = 1U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr = 0U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next = 1U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__osrc = 0U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill = 0x3fU; - vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter = 0x14U; - vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__r_reset_hold = 1U; - vlSelf->main__DOT__swic__DOT__cmd_reset = 1U; - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - vlSelf->main__DOT__swic__DOT__cmd_clear_cache = 0U; - vlSelf->main__DOT__swic__DOT__cmd_step = 0U; - vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch = 1U; - vlSelf->main__DOT__swic__DOT__cmd_write = 0U; - vlSelf->main__DOT__swic__DOT__cmd_read = 0U; - vlSelf->main__DOT__swic__DOT__cmd_read_ack = 0U; - vlSelf->main__DOT__swic__DOT__r_wdbus_data = 0U; - vlSelf->main__DOT__swic__DOT__wdbus_ack = 0U; - vlSelf->main__DOT__swic__DOT__r_mmus_ack = 0U; - vlSelf->main__DOT__swic__DOT__last_sys_stb = 0U; - vlSelf->main__DOT__swic__DOT__dbg_pre_ack = 0U; - vlSelf->main__DOT__swic__DOT__dbg_ack = 0U; - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running = 0U; - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value = 0U; - vlSelf->main__DOT__swic__DOT__wdt_reset = 0U; - vlSelf->main__DOT__swic__DOT__wdt_ack = 0U; - vlSelf->main__DOT__swic__DOT__u_watchbus__DOT__r_value = 0x3fffU; - vlSelf->main__DOT__swic__DOT__wdbus_int = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_running = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value = 0U; - vlSelf->main__DOT__swic__DOT__tma_int = 0U; - vlSelf->main__DOT__swic__DOT__tma_ack = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value = 0U; - vlSelf->main__DOT__swic__DOT__tmb_int = 0U; - vlSelf->main__DOT__swic__DOT__tmb_ack = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value = 0U; - vlSelf->main__DOT__swic__DOT__tmc_int = 0U; - vlSelf->main__DOT__swic__DOT__tmc_ack = 0U; - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter = 0U; - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_now = 0U; - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_set = 0U; - vlSelf->main__DOT__swic__DOT__jif_int = 0U; - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_set = 0U; - vlSelf->main__DOT__swic__DOT__jif_ack = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Aid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rA = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_Rcc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_fpu = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc - = (0xffffffeU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak = 0U; 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- vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__CLEAR_DCACHE__DOT__r_clear_dcache = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_dbg_stall = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_stb = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_addr = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_DIV = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_FP = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_lock = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim_immv = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_bit = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay = 3U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_pc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_last = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__needload = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr = 0U; 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- vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel = 0xffffffffffffffffULL; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner = 1U; - vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner = 1U; - vlSelf->main__DOT__swic__DOT__dbg_cyc = 0U; - vlSelf->main__DOT__swic__DOT__dbg_stb = 0U; - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb = 0U; - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_we = 0U; - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_addr = 0U; - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_data = 0U; - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_sel = 0U; - vlSelf->main__DOT__swic__DOT__dbg_we = 0U; - vlSelf->main__DOT__swic__DOT__dbg_addr = 0U; - vlSelf->main__DOT__swic__DOT__dbg_idata = 0U; - vlSelf->main__DOT__swic__DOT__dbg_sel = 0U; - vlSelf->main__DOT__raw_cpu_dbg_ack = 0U; - vlSelf->main__DOT__wbu_zip_idata = 0U; - vlSelf->main__DOT__swic__DOT__no_dbg_err = 0U; - vlSelf->main__DOT__swic__DOT__mtc_int = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_ack = 0U; - vlSelf->main__DOT__swic__DOT__moc_int = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_ack = 0U; - vlSelf->main__DOT__swic__DOT__mpc_int = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_ack = 0U; - vlSelf->main__DOT__swic__DOT__mic_int = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_ack = 0U; - vlSelf->main__DOT__swic__DOT__utc_int = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_ack = 0U; - vlSelf->main__DOT__swic__DOT__uoc_int = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_ack = 0U; - vlSelf->main__DOT__swic__DOT__upc_int = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_ack = 0U; - vlSelf->main__DOT__swic__DOT__uic_int = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_ack = 0U; - vlSelf->main__DOT__swic__DOT__dmac_ack = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty = 1U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next = 1U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner = 1U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner = 0U; - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state = 0U; - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable = 0U; - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie = 0U; - vlSelf->main__DOT__swic__DOT__ctri_int = 0U; - vlSelf->main__DOT__swic__DOT__ctri_data = 0U; - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state = 0U; - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable = 0U; - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie = 0U; - vlSelf->main__DOT__swic__DOT__pic_interrupt = 0U; - vlSelf->main__DOT__swic__DOT__pic_data = 0U; - vlSelf->main__DOT__i2cscopei__DOT__br_config = 0U; - vlSelf->main__DOT__i2cscopei__DOT__br_holdoff = 0x1fcU; - vlSelf->main__DOT__i2cscopei__DOT__dr_triggered = 0U; - vlSelf->main__DOT__i2cscopei__DOT__holdoff_counter = 0U; - vlSelf->main__DOT__i2cscopei__DOT__dr_stopped = 0U; - vlSelf->main__DOT__i2cscopei__DOT__ck_addr = 0U; - vlSelf->main__DOT__i2cscopei__DOT__dr_force_write = 0U; - vlSelf->main__DOT__i2cscopei__DOT__lst_adr = 1U; - vlSelf->main__DOT__i2cscopei__DOT__imm_adr = 1U; - vlSelf->main__DOT__i2cscopei__DOT__record_ce = 0U; - vlSelf->main__DOT__i2cscopei__DOT__waddr = 0U; - vlSelf->main__DOT__i2cscopei__DOT__dr_primed = 0U; - vlSelf->main__DOT__i2cscopei__DOT__br_pre_wb_ack = 0U; - vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack = 0U; - vlSelf->main__DOT__i2cscopei__DOT__br_level_interrupt = 0U; - vlSelf->main__DOT__rcv__DOT__q_uart = 1U; - vlSelf->main__DOT__rcv__DOT__qq_uart = 1U; - vlSelf->main__DOT__rcv__DOT__ck_uart = 1U; - vlSelf->main__DOT__rcv__DOT__chg_counter = 0x7fU; - vlSelf->main__DOT__rcv__DOT__half_baud_time = 0U; - vlSelf->main__DOT__rcv__DOT__state = 0xfU; - vlSelf->main__DOT__wbu_rx_stb = 0U; - vlSelf->main__DOT__wbu_rx_data = 0U; - vlSelf->main__DOT__rcv__DOT__baud_counter = 0U; - vlSelf->main__DOT__rcv__DOT__zero_baud_counter = 1U; - vlSelf->main__DOT__txv__DOT__r_busy = 1U; - vlSelf->main__DOT__txv__DOT__state = 0xfU; - vlSelf->main__DOT__txv__DOT__lcl_data = 0xffU; - vlSelf->o_wbu_uart_tx = 1U; - vlSelf->main__DOT__txv__DOT__zero_baud_counter = 1U; - vlSelf->main__DOT__txv__DOT__baud_counter = 0U; - vlSelf->main__DOT__w_console_rx_stb = 0U; - vlSelf->main__DOT__genbus__DOT__ps_full = 0U; - vlSelf->main__DOT__genbus__DOT__r_wdt_reset = 1U; - vlSelf->main__DOT__genbus__DOT__r_wdt_timer = 0U; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb = 0U; - vlSelf->main__DOT__genbus__DOT__soft_reset = 1U; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len = 0U; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg = 0ULL; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw = 0U; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len = 0U; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb = 0U; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr = 0U; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb = 0U; - vlSelf->main__DOT__genbus__DOT__in_stb = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state = 0U; - vlSelf->main__DOT__wbu_cyc = 0U; - vlSelf->main__DOT__wbu_stb = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_new_addr = 1U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__zero_acks = 1U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_read_request = 1U; - vlSelf->main__DOT__genbus__DOT__exec_stb = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits = 0x40U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl = 1U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl = 1U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__full_line = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy = 0U; - vlSelf->main__DOT__genbus__DOT__wbu_tx_stb = 0U; - vlSelf->main__DOT__genbus__DOT__wbu_tx_data = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k = 0U; - while (VL_GTS_III(32, 0x400U, vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k)) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl[(0x3ffU - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k)] = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k - = ((IData)(1U) + vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k); - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__vaddr = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table = 1U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__zmatch = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__hmatch = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb = 0U; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow = 0U; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr = 0U; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow = 1U; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr = 0U; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n = 0U; - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow = 0U; - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr = 0U; - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow = 1U; - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr = 0U; - vlSelf->main__DOT__genbus__DOT__ofifo_empty_n = 0U; - vlSelf->o_gpio = 0x20U; - vlSelf->main__DOT__spioi__DOT__r_led = 0U; - vlSelf->main__DOT__spioi__DOT__led_demo = 1U; - vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw = 0U; - vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe = 0U; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner = 1U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel = 0ULL; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[1U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[2U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[3U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[4U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[5U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[6U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[7U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[8U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[9U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xaU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xbU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xcU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xdU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xeU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xfU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty = 1U; -} - -VL_ATTR_COLD void Vmain___024root___eval_final(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_final\n"); ); -} - -VL_ATTR_COLD void Vmain___024root___eval_triggers__stl(Vmain___024root* vlSelf); -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__stl(Vmain___024root* vlSelf); -#endif // VL_DEBUG -VL_ATTR_COLD void Vmain___024root___eval_stl(Vmain___024root* vlSelf); - -VL_ATTR_COLD void Vmain___024root___eval_settle(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_settle\n"); ); - // Init - CData/*0:0*/ __VstlContinue; - // Body - vlSelf->__VstlIterCount = 0U; - __VstlContinue = 1U; - while (__VstlContinue) { - __VstlContinue = 0U; - Vmain___024root___eval_triggers__stl(vlSelf); - if (vlSelf->__VstlTriggered.any()) { - __VstlContinue = 1U; - if (VL_UNLIKELY((0x64U < vlSelf->__VstlIterCount))) { -#ifdef VL_DEBUG - Vmain___024root___dump_triggers__stl(vlSelf); -#endif - VL_FATAL_MT("main.v", 97, "", "Settle region did not converge."); - } - vlSelf->__VstlIterCount = ((IData)(1U) - + vlSelf->__VstlIterCount); - Vmain___024root___eval_stl(vlSelf); - } - } -} - -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__stl(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___dump_triggers__stl\n"); ); - // Body - if ((1U & (~ (IData)(vlSelf->__VstlTriggered.any())))) { - VL_DBG_MSGF(" No triggers active\n"); - } - if ((1ULL & vlSelf->__VstlTriggered.word(0U))) { - VL_DBG_MSGF(" 'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n"); - } -} -#endif // VL_DEBUG - -extern const VlUnpacked Vmain__ConstPool__TABLE_h611c22d1_0; - -VL_ATTR_COLD void Vmain___024root___stl_sequent__TOP__0(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___stl_sequent__TOP__0\n"); ); - // Init - CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior = 0; - CData/*7:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior = 0; - CData/*1:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout; - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout = 0; - QData/*63:0*/ __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel; - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit = 0; - CData/*2:0*/ __Vtableidx10; - __Vtableidx10 = 0; - VlWide<16>/*511:0*/ __Vtemp_h3711b190__0; - VlWide<16>/*511:0*/ __Vtemp_h18146fff__0; - // Body - vlSelf->io_sdcard_cmd_tristate = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z; - vlSelf->o_fan_sda = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda; - vlSelf->o_fan_scl = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl; - vlSelf->o_i2c_sda = vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda; - vlSelf->o_i2c_scl = vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl; - vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n - = (1U & (~ (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__raw_cpu_dbg_stall = vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb; - vlSelf->main__DOT__wbwide_wbu_arbiter_cyc = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr - = vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wb32_wbdown_cyc = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc; - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__emmcscopei__DOT__bw_reset_request - = (1U & (~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U))); - vlSelf->main__DOT__sdioscopei__DOT__bw_reset_request - = (1U & (~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U))); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__r_valid - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_phase - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim_immv; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubreak - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_u - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubus_err_flag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_valid - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid; - vlSelf->main__DOT__i2cscopei__DOT__bw_reset_request - = (1U & (~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_busy - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb; - vlSelf->o_ddr3_controller_dqs_tri_control = (1U - & (~ - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs) - >> 2U))); - vlSelf->o_ddr3_controller_dq_tri_control = (1U - & (~ - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq) - >> 3U))); - vlSelf->o_ddr3_controller_toggle_dqs = (1U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_val)); - vlSelf->o_ddr3_controller_data[0U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0U]; - vlSelf->o_ddr3_controller_data[1U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][1U]; - vlSelf->o_ddr3_controller_data[2U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][2U]; - vlSelf->o_ddr3_controller_data[3U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][3U]; - vlSelf->o_ddr3_controller_data[4U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][4U]; - vlSelf->o_ddr3_controller_data[5U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][5U]; - vlSelf->o_ddr3_controller_data[6U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][6U]; - vlSelf->o_ddr3_controller_data[7U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][7U]; - vlSelf->o_ddr3_controller_data[8U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][8U]; - vlSelf->o_ddr3_controller_data[9U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][9U]; - vlSelf->o_ddr3_controller_data[0xaU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xaU]; - vlSelf->o_ddr3_controller_data[0xbU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xbU]; - vlSelf->o_ddr3_controller_data[0xcU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xcU]; - vlSelf->o_ddr3_controller_data[0xdU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xdU]; - vlSelf->o_ddr3_controller_data[0xeU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xeU]; - vlSelf->o_ddr3_controller_data[0xfU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xfU]; - vlSelf->o_ddr3_controller_dm = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [1U]; - vlSelf->o_sirefclk_ce = vlSelf->main__DOT__r_sirefclk_en; - vlSelf->cpu_sim_idata = vlSelf->main__DOT__wbu_zip_idata; - vlSelf->cpu_prof_stb = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_stb; - vlSelf->cpu_prof_addr = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_addr; - vlSelf->cpu_prof_ticks = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks; - vlSelf->o_led = vlSelf->main__DOT__w_led; - vlSelf->main__DOT__i2cdma_ready = (1U & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wb32_wbdown_err = vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->main__DOT__wb32_xbar__DOT__m_data[0U] = (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> 4U)); - vlSelf->main__DOT__wb32_xbar__DOT__m_sel[0U] = - (0xfU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data)); - vlSelf->main__DOT__wb32_xbar__DOT__m_addr[0U] = vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wb32_xbar__DOT__w_mpending[0U] - = vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->main__DOT__wbu_err = vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->main__DOT__wbu_xbar__DOT__m_data[0U] = (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> 4U)); - vlSelf->main__DOT__wbu_xbar__DOT__m_sel[0U] = (0xfU - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data)); - vlSelf->main__DOT__wbu_xbar__DOT__m_addr[0U] = vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbu_xbar__DOT__w_mpending[0U] - = vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value - = (0x3fU & ((1U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored)) - ? ((IData)(2U) + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored)) - : ((IData)(1U) + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored)))); - vlSelf->main__DOT__u_i2cdma__DOT__skd_valid = vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_waddr_plus_one - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr))); - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_waddr_plus_one - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I - = (((- (IData)((1U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I - >> 0x16U)))) << 0x16U) - | (0x3fffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim_immv; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cline - = (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag - = (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__rx_valid - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid; - vlSelf->main__DOT__genbus__DOT__w_bus_busy = vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cod_busy - = (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr - = (((- (IData)((1U & (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr - >> 0x18U)))) << 0x19U) - | vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck - = (((0U == (0xffU & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 0x18U)))) << 3U) - | (((0U == (0x3fU & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 0x12U)))) - << 2U) | (((0U == (0x3fU & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 0xcU)))) - << 1U) | (0U == (0x3fU & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 6U))))))); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__nxt_wrptr - = (0x7fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr))); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__nxt_wrptr - = (0x7ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr))); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr - = ((0x10U & (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - << 4U)) | ((8U & (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - << 2U)) | ((4U - & vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr) - | ((2U - & (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - >> 2U)) - | (1U - & (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - >> 4U)))))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] = 0U; - if ((0U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU])); - } - if ((1U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU])); - } - if ((2U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU])); - } - if ((3U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU])); - } - if ((4U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU])); - } - if ((5U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU])); - } - if ((6U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU])); - } - if ((7U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU])); - } - if ((8U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU])); - } - if ((9U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU])); - } - if ((0xaU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU])); - } - if ((0xbU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU])); - } - if ((0xcU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU])); - } - if ((0xdU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU])); - } - if ((0xeU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU])); - } - if ((0xfU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU])); - } - if ((0x10U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU])); - } - if ((0x11U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU])); - } - if ((0x12U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU])); - } - if ((0x13U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU])); - } - if ((0x14U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU])); - } - if ((0x15U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU])); - } - if ((0x16U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU])); - } - if ((0x17U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU])); - } - if ((0x18U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U])); - } - if ((0x19U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U])); - } - if ((0x1aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U])); - } - if ((0x1bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U])); - } - if ((0x1cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U])); - } - if ((0x1dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U])); - } - if ((0x1eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U])); - } - if ((0x1fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U])); - } - if ((0x20U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U])); - } - if ((0x21U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U])); - } - if ((0x22U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U])); - } - if ((0x23U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U])); - } - if ((0x24U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U])); - } - if ((0x25U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U])); - } - if ((0x26U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U])); - } - if ((0x27U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U])); - } - if ((0x28U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U])); - } - if ((0x29U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U])); - } - if ((0x2aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U])); - } - if ((0x2bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U])); - } - if ((0x2cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U])); - } - if ((0x2dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U])); - } - if ((0x2eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U])); - } - if ((0x2fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U])); - } - if ((0x30U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U])); - } - if ((0x31U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U])); - } - if ((0x32U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U])); - } - if ((0x33U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U])); - } - if ((0x34U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U])); - } - if ((0x35U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U])); - } - if ((0x36U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U])); - } - if ((0x37U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U])); - } - if ((0x38U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U])); - } - if ((0x39U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U])); - } - if ((0x3aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U])); - } - if ((0x3bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U])); - } - if ((0x3cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U])); - } - if ((0x3dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U])); - } - if ((0x3eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U])); - } - if ((0x3fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U])); - } - if (vlSelf->i_clk) { - vlSelf->o_sdcard_clk = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out) - >> 1U)); - vlSelf->o_sdcard_cmd = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - } else { - vlSelf->o_sdcard_clk = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out)); - vlSelf->o_sdcard_cmd = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out)); - } - vlSelf->cpu_sim_stall = (1U & ((~ (IData)(vlSelf->cpu_sim_cyc)) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb))); - vlSelf->cpu_sim_ack = ((IData)(vlSelf->cpu_sim_cyc) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)); - vlSelf->main__DOT__wb32_sirefclk_stb = (IData)( - (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) - & (0x200U - == - (0x700U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))); - vlSelf->main__DOT____Vcellinp__swic__i_reset = - ((IData)(vlSelf->i_cpu_reset) | (IData)(vlSelf->i_reset)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc - = (IData)((((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - >> 1U) | (IData)(vlSelf->cpu_sim_cyc))); - vlSelf->main__DOT__wbwide_xbar__DOT__s_err = (8U - | ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err))); - vlSelf->main__DOT__wbu_xbar__DOT__s_err = (0xcU - | ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN - = (1U & (~ ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy - = (1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy))); - vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted)); - vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN - = (1U & (~ ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual)))); - __Vtemp_h3711b190__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x10U]; - __Vtemp_h3711b190__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x11U]; - __Vtemp_h3711b190__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x12U]; - __Vtemp_h3711b190__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x13U]; - __Vtemp_h3711b190__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x14U]; - __Vtemp_h3711b190__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x15U]; - __Vtemp_h3711b190__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x16U]; - __Vtemp_h3711b190__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x17U]; - __Vtemp_h3711b190__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x18U]; - __Vtemp_h3711b190__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x19U]; - __Vtemp_h3711b190__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1aU]; - __Vtemp_h3711b190__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1bU]; - __Vtemp_h3711b190__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1cU]; - __Vtemp_h3711b190__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1dU]; - __Vtemp_h3711b190__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1eU]; - __Vtemp_h3711b190__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1fU]; - VL_SHIFTL_WWI(512,512,32, __Vtemp_h18146fff__0, __Vtemp_h3711b190__0, - ((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift) - << 3U)); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0U] - = __Vtemp_h18146fff__0[0U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[1U] - = __Vtemp_h18146fff__0[1U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[2U] - = __Vtemp_h18146fff__0[2U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[3U] - = __Vtemp_h18146fff__0[3U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[4U] - = __Vtemp_h18146fff__0[4U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[5U] - = __Vtemp_h18146fff__0[5U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[6U] - = __Vtemp_h18146fff__0[6U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[7U] - = __Vtemp_h18146fff__0[7U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[8U] - = __Vtemp_h18146fff__0[8U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[9U] - = __Vtemp_h18146fff__0[9U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xaU] - = __Vtemp_h18146fff__0[0xaU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xbU] - = __Vtemp_h18146fff__0[0xbU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xcU] - = __Vtemp_h18146fff__0[0xcU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xdU] - = __Vtemp_h18146fff__0[0xdU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xeU] - = __Vtemp_h18146fff__0[0xeU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xfU] - = __Vtemp_h18146fff__0[0xfU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel - = ((0x3fU >= (0x1ffffffcU & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift) - << 2U))) ? (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel - << - (0x1ffffffcU - & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift) - << 2U))) - : 0ULL); - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy - = (1U & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy))); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read - = ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - & (IData)(vlSelf->main__DOT__console__DOT__rxf_wb_read)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset - [(0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset - [(0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__regid - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U) | (0xfU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim_immv)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_invalidate_result - = ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)); - vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__exec_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__ps_full) - & (IData)(vlSelf->main__DOT__genbus__DOT__wbu_tx_stb)); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd - = ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U)); - vlSelf->o_ddr3_controller_odelay_data_cntvaluein - = vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - vlSelf->o_ddr3_controller_odelay_dqs_cntvaluein - = vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - vlSelf->o_ddr3_controller_idelay_data_cntvaluein - = vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - vlSelf->o_ddr3_controller_idelay_dqs_cntvaluein - = vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - vlSelf->main__DOT__wbu_xbar__DOT__s_data[0U] = - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xfU]; - vlSelf->main__DOT__wbu_xbar__DOT__s_data[1U] = vlSelf->main__DOT__wbu_zip_idata; - vlSelf->main__DOT____Vcellinp__u_i2cdma__S_VALID - = ((IData)(vlSelf->main__DOT__i2c_valid) & - (2U == (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid))); - vlSelf->main__DOT__u_i2cdma__DOT____Vcellinp__sskd__i_data - = (((IData)(vlSelf->main__DOT__i2c_last) << 8U) - | (IData)(vlSelf->main__DOT__i2c_data)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds) - & (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff - = (0x1ffffffffULL & ((QData)((IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - >> 0x1fU))) - - (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor)))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[1U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0x10U]; - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any - = (0U != ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state) - & (IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable))); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any - = (0U != ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state) - & (IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable))); - vlSelf->main__DOT__genbus__DOT__rx_valid = ((IData)(vlSelf->main__DOT__wbu_rx_stb) - & ((IData)(vlSelf->main__DOT__wbu_rx_data) - >> 7U)); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size - = (0x7fU & ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? 1U : ((1U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? 1U : 2U)) : ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? - ((IData)(4U) - - - (3U - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : - ((IData)(0x40U) - - - (0x3fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))))); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size) - > (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size - = (0x7fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen)); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size; - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size = 1U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel - = (((QData)((IData)((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel)))) - << 0x3fU) | (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - >> 1U)); - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size - = ((3U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len)) - ? 1U : 2U); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel - = (((QData)((IData)((3U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel)))) - << 0x3eU) | (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - >> 2U)); - } - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size - = (((4U <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len)) - & (8U > (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len))) - ? (0x7fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - - (IData)(4U))) : 4U); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel - = (((QData)((IData)((0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel)))) - << 0x3cU) | (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - >> 4U)); - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size = 0x40U; - if ((0x40U > ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size - = (0x7fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size))); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel = 0xffffffffffffffffULL; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr - = (0xfffffffU & ((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen)) - - (IData)(1U))); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift - = (0x3fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift - = (0x3fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill)); - } - vlSelf->io_emmc_dat_tristate = ((0x80U & ((~ ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1fU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 7U)) - | ((0x40U & ((~ - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1eU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 6U)) - | ((0x20U & - ((~ ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1dU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 5U)) - | ((0x10U - & ((~ - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1cU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 4U)) - | ((8U - & ((~ - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1bU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 3U)) - | (7U - & (~ - ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1aU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data))) - << 2U) - | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x19U)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data))) - << 1U) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))))))))))); - if (vlSelf->cpu_sim_cyc) { - vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb - = (1U & (IData)(vlSelf->cpu_sim_stb)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_we - = (1U & (IData)(vlSelf->cpu_sim_we)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr - = (0x7fU & (IData)(vlSelf->cpu_sim_addr)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_data - = vlSelf->cpu_sim_data; - } else { - vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb - = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - >> 1U)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_we - = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe) - >> 1U)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr - = (0x7fU & (IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - >> 0x1bU))); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_data - = (IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - >> 0x20U)); - } - vlSelf->main__DOT__u_i2cdma__DOT__skd_ready = (1U - & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT__r_reset) - | ((~ (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__bus_err)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U) & (IData)(((0x40000U == (0x70000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U) & ((4U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U))); - vlSelf->main__DOT__console__DOT__rxf_wb_data = - ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__osrc) - ? (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__last_write) - : (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_data)); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write - = ((IData)(vlSelf->main__DOT__w_console_rx_stb) - & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow)) - | (IData)(vlSelf->main__DOT__console__DOT__rxf_wb_read))); - vlSelf->main__DOT__i2cscopei__DOT__dw_trigger = - ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_primed) - & (((~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted)) - | ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 1U))); - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][1U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][2U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][3U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][4U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][5U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][6U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][7U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][8U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][9U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xaU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xbU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xcU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xdU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xeU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xfU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0U] - = vlSelf->main__DOT__wbwide_bkram_idata[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][1U] - = vlSelf->main__DOT__wbwide_bkram_idata[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][2U] - = vlSelf->main__DOT__wbwide_bkram_idata[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][3U] - = vlSelf->main__DOT__wbwide_bkram_idata[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][4U] - = vlSelf->main__DOT__wbwide_bkram_idata[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][5U] - = vlSelf->main__DOT__wbwide_bkram_idata[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][6U] - = vlSelf->main__DOT__wbwide_bkram_idata[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][7U] - = vlSelf->main__DOT__wbwide_bkram_idata[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][8U] - = vlSelf->main__DOT__wbwide_bkram_idata[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][9U] - = vlSelf->main__DOT__wbwide_bkram_idata[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xaU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xbU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xcU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xdU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xeU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xfU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xfU]; - vlSelf->main__DOT__i2c_ready = (1U & ((~ (IData)(vlSelf->main__DOT__i2c_valid)) - | ((0U == (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid)) - | ((1U - == (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid)) - | (((~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid)) - & (2U - == (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid))) - | (2U - < (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid))))))); - vlSelf->main__DOT__w_console_tx_data = ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__osrc) - ? (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__last_write) - : (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_data)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result - = ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_sgn)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_smpy_result - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_umpy_result); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table) - & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch) - & (0xe00000000ULL == (0xe00000000ULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn - = (0xffU & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - ? vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - : (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn))); - if (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle)) - & (0U == (0xf0U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn - = (0xf0U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - << 4U)); - } - vlSelf->main__DOT__i2ci__DOT__next_insn = (0xffU - & ((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - ? - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - : (IData)(vlSelf->main__DOT__i2ci__DOT__pf_insn))); - if (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle)) - & (0U == (0xf0U & (IData)(vlSelf->main__DOT__i2ci__DOT__next_insn))))) { - vlSelf->main__DOT__i2ci__DOT__next_insn = (0xf0U - & ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - << 4U)); - } - __Vtableidx10 = (7U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel - = Vmain__ConstPool__TABLE_h611c22d1_0[__Vtableidx10]; - vlSelf->io_sdcard_dat_tristate = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z) - << 3U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z) - << 2U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z) - << 1U) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z)))); - vlSelf->main__DOT__emmcscopei__DOT__write_to_control - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - & ((~ vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]) - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))))); - vlSelf->main__DOT__emmcscopei__DOT__read_from_data - = ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & ((~ (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel)))))); - vlSelf->main__DOT__sdioscopei__DOT__write_to_control - = ((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 2U) & ((~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U)) & (0xf00ULL == - (0xf00ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel)))); - vlSelf->main__DOT__sdioscopei__DOT__read_from_data - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 2U) & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 2U)) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U) & (0xf00ULL - == - (0xf00ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_valid - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid))); - vlSelf->main__DOT__i2cscopei__DOT__write_to_control - = ((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 1U) & ((~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U)) & (0xf0ULL == (0xf0ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel)))); - vlSelf->main__DOT__i2cscopei__DOT__read_from_data - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 1U) & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 1U)) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U) & (0xf0ULL - == - (0xf0ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table - = ((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)) - & (0x200000000ULL == (0xe00000000ULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword))))); - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][8U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][9U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xaU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xbU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xcU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xdU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xeU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xfU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_we = ((8U - & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0x12U] - << 3U)) - | ((4U - & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x12U] - << 2U)) - | ((2U - & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x12U] - << 1U)) - | (1U - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[0U] - = (((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0U]))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[1U] - = (((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0U]))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[2U] - = (((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0U]))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[3U] - = (((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0U]))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending; - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill = 0U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill - = ((0x3c0U & (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill)) - | (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v) - | (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - ? (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc) - : ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v) - | (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - ? (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc) - : ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc) - | ((0x10U & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr)) - ? ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 1U)) : ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase) - << 1U)))); - vlSelf->main__DOT__wbwide_xbar__DOT__s_ack = ((0xfffffffcU - & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & ((vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U] - & (0xeU - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - << 2U))) - | ((0xfffffffeU - & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wbwide_bkram_ack) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount) - == ((IData)(1U) + (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & (((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid) - & (3U <= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr)))) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - & (0x30U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount) - == ((IData)(1U) + (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & (((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid) - & (3U <= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr)))) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - & (0x30U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill = 0U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill - = ((0x3c0U & (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill)) - | (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset - = ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)); - vlSelf->__VdfgTmp_ha46ae6a3__0 = ((2U & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - >> 4U)) - | (1U & (~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 5U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done - = (1U & (~ (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid)) - | (0U != (0x18U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid)))); - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = 0U; - } - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - = (((QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[0U]))); - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xfU; - if ((0U != (0xfU & (IData)(__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel)))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xeU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 4U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xdU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 8U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xcU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0xcU))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xbU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x10U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xaU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x14U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 9U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x18U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 8U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x1cU))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 7U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x20U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 6U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x24U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 5U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x28U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 4U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x2cU))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 3U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x30U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 2U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x34U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 1U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x38U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x3cU))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__i_subaddr - = __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done - = (1U & (~ (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid)) - | (0U != (0x18U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid)))); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = 0U; - } - vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3 - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)); - vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3 - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dq; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__pc_tag_lookup - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_tag_lookup); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - & ((~ ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn) - >> 0xbU)) & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = (0xc0000000U | ((0x3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - << 0x18U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = ((0xffc01fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift) - << 0x10U) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown) - << 0xfU) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90) - << 0xeU) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__pp_cmd) - << 0xdU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = ((0xffffe000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data) - << 0xcU) | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width) - << 0xaU)) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds) - << 9U) | - (((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) - << 8U) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_ckspd))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = (0xc0000000U | ((0x3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - << 0x18U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = ((0xffc01fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift) - << 0x10U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown) - << 0xfU) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90) - << 0xeU) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_cmd) - << 0xdU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = ((0xffffe000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data) - << 0xcU) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width) - << 0xaU)) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds) - << 9U) | - (((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - << 8U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_ckspd))))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0x1fffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy) - << 0x1fU) | ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err)) - << 0x1eU) | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger) - << 0x1dU)))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0xe0ffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel) - << 0x18U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0xfffff800U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0xff8fffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | ((0x400000U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc)) - << 0x16U)) | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size) - << 0x14U))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0xfff8ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | ((0x40000U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc)) - << 0x12U)) | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size) - << 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready - = ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready - = ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb)); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)); - vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr - = ((0xf0000000U & vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr) - | vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr); - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[4U]; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb - = (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x10U))); - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old - = vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr; - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout - = ((0xffffU & vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout) - | ((((8U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - >> 0x18U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old - >> 0x18U)) << 0x18U) - | (0xff0000U & (((4U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - >> 0x10U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old - >> 0x10U)) - << 0x10U)))); - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout - = ((0xffff0000U & vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout) - | ((0xff00U & (((2U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - >> 8U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old - >> 8U)) << 8U)) - | (0xffU & ((1U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb)) - ? __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - : __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old)))); - vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr - = vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout; - vlSelf->main__DOT__u_i2cdma__DOT__next_memlen = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__next_memlen = - ((0xf0000000U & vlSelf->main__DOT__u_i2cdma__DOT__next_memlen) - | vlSelf->main__DOT__u_i2cdma__DOT__r_memlen); - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[4U]; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb - = (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x10U))); - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old - = vlSelf->main__DOT__u_i2cdma__DOT__next_memlen; - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout - = ((0xffffU & vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout) - | ((((8U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - >> 0x18U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old - >> 0x18U)) << 0x18U) - | (0xff0000U & (((4U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - >> 0x10U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old - >> 0x10U)) - << 0x10U)))); - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout - = ((0xffff0000U & vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout) - | ((0xff00U & (((2U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - >> 8U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old - >> 8U)) << 8U)) - | (0xffU & ((1U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb)) - ? __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - : __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old)))); - vlSelf->main__DOT__u_i2cdma__DOT__next_memlen = vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0U] = vlSelf->main__DOT__emmcscopei__DOT__o_bus_data; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[1U] = vlSelf->main__DOT__i2cscopei__DOT__o_bus_data; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[2U] = vlSelf->main__DOT__sdioscopei__DOT__o_bus_data; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[3U] = vlSelf->main__DOT__i2ci__DOT__bus_read_data; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[4U] = vlSelf->main__DOT__wb32_i2cdma_idata; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[5U] = vlSelf->main__DOT__wb32_uart_idata; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[6U] = vlSelf->main__DOT__wb32_emmc_idata; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[7U] = vlSelf->main__DOT__wb32_fan_idata; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[8U] = vlSelf->main__DOT__wb32_sdcard_idata; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[9U] = vlSelf->main__DOT__r_wb32_sio_data; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0xbU] - = vlSelf->main__DOT__wb32_ddr3_phy_idata; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[0U] - = main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[1U] - = main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[2U] - = main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[3U] - = main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4U] = 0U; - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 0U; - if ((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row)))) { - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4U] - = (1U | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux) - << 1U)); - } else if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we)) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4U] - = (1U | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux) - << 1U)); - } - } - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xf0ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - << 0x1bU) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request) - << 0x1aU) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - << 0x19U) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request) - << 0x18U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr)) - << 0x15U) | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy) - << 0x14U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfff83fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode) - << 0x10U) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err) - << 0xfU) | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - << 0xeU)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffffcfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - << 0xcU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type)))) - << 0xbU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - << 0xaU) | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type) - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffffff80U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd)); - vlSelf->main__DOT__wb32_spio_stb = (IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) - & (0x300U - == - (0x700U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))); - vlSelf->main__DOT__genbus__DOT__ofifo_rd = ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb)) - & (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd - = ((~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy)) - & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)); - vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0 - = (((IData)(vlSelf->main__DOT__spio_int) << 3U) - | ((4U & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - >> 3U)) | ((2U & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - >> 4U)) | (IData)(vlSelf->main__DOT__sdcard_int)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xf0ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - << 0x1bU) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request) - << 0x1aU) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - << 0x19U) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request) - << 0x18U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr)) - << 0x15U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy) - << 0x14U) | (0x80000U - & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present)) - << 0x13U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfff83fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_removed) - << 0x12U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode) - << 0x10U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err) - << 0xfU) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - << 0xeU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffffcfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - << 0xcU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)))) - << 0xbU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - << 0xaU) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type) - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffffff80U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd)); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy - = (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))) - & (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)))); - if (((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid))) - & (1U == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw)))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy = 1U; - } - if (((((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid)) - & (1U == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw))) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len))) - & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy = 1U; - } - vlSelf->o_emmc_dat = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U); - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data - = (((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last) - << 4U) | (0xfU & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr))]; - vlSelf->main__DOT__i2ci__DOT__s_tvalid = ((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - & ((~ - ((IData)(vlSelf->main__DOT__i2ci__DOT__insn) - >> 0xbU)) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_wait)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_haf314c36__0 - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb)); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbu_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data - = (0xfULL | (((QData)((IData)(vlSelf->main__DOT__wbu_we)) - << 0x3fU) | (((QData)((IData)( - (0x7ffffffU - & vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr))) - << 0x24U) | ((QData)((IData)(vlSelf->main__DOT__wbu_data)) - << 4U)))); - vlSelf->main__DOT__swic__DOT__dc_ack = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid)) - | ((0x40U > (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full))))))); - vlSelf->main__DOT__i2cscope_int = (IData)(((((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - >> 4U) - & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config))) - & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_level_interrupt)))); - vlSelf->main__DOT__sdioscope_int = (IData)(((((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - >> 4U) - & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config))) - & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_level_interrupt)))); - vlSelf->main__DOT__emmcscope_int = (IData)(((((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - >> 4U) - & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config))) - & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_level_interrupt)))); - vlSelf->main__DOT__w_console_busy = ((IData)(vlSelf->main__DOT__genbus__DOT__ps_full) - | (IData)(vlSelf->main__DOT__genbus__DOT__wbu_tx_stb)); - vlSelf->main__DOT__wb32_xbar__DOT__mindex[0U] = vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbu_xbar__DOT__mindex[0U] = vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data - = ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((0x1000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((0x800U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((0x20U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | ((0x10U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | ((8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U)) - | (1U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data)))))))))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xfU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xeU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xdU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xcU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xbU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xaU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 9U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 8U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data - = ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((0x2000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((0x1000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((0x800U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((0x20U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((0x10U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | ((8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))))))))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xfU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xeU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xdU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xcU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xbU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xaU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 9U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 8U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffffff0U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xeU)) | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 1U))) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xfU)) | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xffffff0fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xcU)) | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 3U))) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xdU)) | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 2U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffff0ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xaU)) | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 5U))) - | ((0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xbU)) | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 4U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xffff0fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 8U)) | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 7U))) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 9U)) | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 6U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfff0ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 6U)) | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 9U))) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 7U)) | (0x10000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 8U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xff0fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 4U)) | (0x400000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xbU))) - | ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 5U)) | (0x100000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xaU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xf0ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 2U)) | (0x4000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xdU))) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 3U)) | (0x1000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xcU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xfU))) | ((0x20000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 1U)) - | (0x10000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xeU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffeULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | (IData)((IData)((1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffeffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 1U))))) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffeffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 2U))))) - << 0x20U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffeffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 3U))))) - << 0x30U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffdULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 4U))))) - << 1U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffdffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 5U))))) - << 0x11U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffdffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 6U))))) - << 0x21U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffdffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 7U))))) - << 0x31U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffbULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 8U))))) - << 2U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffbffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 9U))))) - << 0x12U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffbffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xaU))))) - << 0x22U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffbffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xbU))))) - << 0x32U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffff7ULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xcU))))) - << 3U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffff7ffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xdU))))) - << 0x13U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffff7ffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xeU))))) - << 0x23U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfff7ffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xfU))))) - << 0x33U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffefULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x10U))))) - << 4U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffefffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x11U))))) - << 0x14U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffefffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x12U))))) - << 0x24U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffefffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x13U))))) - << 0x34U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffdfULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x14U))))) - << 5U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffdfffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x15U))))) - << 0x15U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffdfffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x16U))))) - << 0x25U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffdfffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x17U))))) - << 0x35U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffbfULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x18U))))) - << 6U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffbfffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x19U))))) - << 0x16U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffbfffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1aU))))) - << 0x26U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffbfffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1bU))))) - << 0x36U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffff7fULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1cU))))) - << 7U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffff7fffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1dU))))) - << 0x17U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffff7fffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1eU))))) - << 0x27U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xff7fffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1fU))))) - << 0x37U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffeffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x20U))))) - << 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffeffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x21U))))) - << 0x18U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffeffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x22U))))) - << 0x28U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfeffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x23U))))) - << 0x38U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffdffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x24U))))) - << 9U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffdffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x25U))))) - << 0x19U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffdffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x26U))))) - << 0x29U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfdffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x27U))))) - << 0x39U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffbffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x28U))))) - << 0xaU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffbffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x29U))))) - << 0x1aU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffbffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2aU))))) - << 0x2aU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfbffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2bU))))) - << 0x3aU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffff7ffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2cU))))) - << 0xbU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffff7ffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2dU))))) - << 0x1bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffff7ffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2eU))))) - << 0x2bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xf7ffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2fU))))) - << 0x3bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffefffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x30U))))) - << 0xcU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffefffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x31U))))) - << 0x1cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffefffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x32U))))) - << 0x2cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xefffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x33U))))) - << 0x3cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffdfffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x34U))))) - << 0xdU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffdfffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x35U))))) - << 0x1dU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffdfffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x36U))))) - << 0x2dU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xdfffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x37U))))) - << 0x3dU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffbfffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x38U))))) - << 0xeU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffbfffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x39U))))) - << 0x1eU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffbfffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3aU))))) - << 0x2eU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xbfffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3bU))))) - << 0x3eU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffff7fffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3cU))))) - << 0xfU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffff7fffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3dU))))) - << 0x1fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffff7fffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3eU))))) - << 0x2fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0x7fffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3fU))))) - << 0x3fU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | ((0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | (1U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data)))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior - = (0xffffU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffffffff0000ULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | (IData)((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | ((0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) - | ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x10U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffff0000ffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout)) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | ((0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) - | ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x20U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffff0000ffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout)) - << 0x20U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | ((0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) - | ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x30U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout)) - << 0x30U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffffff8ULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | (IData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x20U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x10U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffffff7ULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x30U))))) - << 3U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffffff8fULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x21U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x11U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 1U))))))) - << 4U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffffff7fULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x31U))))) - << 7U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffff8ffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x22U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x12U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 2U))))))) - << 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffff7ffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x32U))))) - << 0xbU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffff8fffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x23U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x13U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 3U))))))) - << 0xcU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffff7fffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x33U))))) - << 0xfU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffff8ffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x24U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x14U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 4U))))))) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffff7ffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x34U))))) - << 0x13U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffff8fffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x25U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x15U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 5U))))))) - << 0x14U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffff7fffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x35U))))) - << 0x17U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffff8ffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x26U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x16U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 6U))))))) - << 0x18U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffff7ffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x36U))))) - << 0x1bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffff8fffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x27U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x17U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 7U))))))) - << 0x1cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffff7fffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x37U))))) - << 0x1fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffff8ffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x28U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x18U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 8U))))))) - << 0x20U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffff7ffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x38U))))) - << 0x23U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffff8fffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x29U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x19U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 9U))))))) - << 0x24U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffff7fffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x39U))))) - << 0x27U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffff8ffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2aU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1aU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xaU))))))) - << 0x28U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffff7ffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3aU))))) - << 0x2bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffff8fffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2bU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1bU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xbU))))))) - << 0x2cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffff7fffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3bU))))) - << 0x2fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfff8ffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2cU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1cU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xcU))))))) - << 0x30U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfff7ffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3cU))))) - << 0x33U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xff8fffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2dU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1dU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xdU))))))) - << 0x34U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xff7fffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3dU))))) - << 0x37U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xf8ffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2eU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1eU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xeU))))))) - << 0x38U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xf7ffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3eU))))) - << 0x3bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0x8fffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2fU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1fU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xfU))))))) - << 0x3cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0x7fffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3fU))))) - << 0x3fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x12U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x14U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x8000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x14U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x12U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U])); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) | (1U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data)))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x19U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1aU)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1bU)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1cU)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 2U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xfU)) | - (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U])))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xbU)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 4U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffff3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 9U)) | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 6U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 9U)) | ( - (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 8U)) - | (0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 4U)) | - ((0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xbU)) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffff3fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 2U)) | - (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xdU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x10U)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 1U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xeU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 3U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x12U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 1U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xff3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 5U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x14U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x17U)) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 6U)) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xaU)) - | ((0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x19U)) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0x3fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xcU)) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x1bU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 2U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x13U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 4U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xfU)) | - ((0x10U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffff3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xdU)) | - (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 2U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 5U)) | ( - (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xcU)) - | (0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 3U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 8U)) | - ((0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 7U)) | - (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xaU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffff3fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 6U)) | - (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 9U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xcU)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 5U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xaU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 1U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xeU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 3U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xff3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 1U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x10U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x13U)) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 2U)) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 6U)) - | ((0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x15U)) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0x3fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 8U)) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x17U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 6U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x17U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 8U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x13U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 4U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffff3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0x11U)) | - (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 2U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 1U)) | ( - (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x10U)) - | (0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 1U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xcU)) - | ((0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 3U)) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xeU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffff3fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xaU)) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 5U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 8U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 9U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 5U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xaU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xff3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 3U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xcU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xfU)) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 2U)) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 2U)) - | ((0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x11U)) - | (0x8000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0x3fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 4U)) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x13U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xaU)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x1bU)) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xcU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x17U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 8U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x19U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffff3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0x15U)) | - (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 6U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 3U)) | ( - (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x14U)) - | (0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 5U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x10U)) - | ((0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 1U)) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x12U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffff3fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xeU)) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 1U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 4U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xdU)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 9U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 6U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xbU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xff3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 7U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 8U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xbU)) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 6U)) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 9U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 2U)) - | ((0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xdU)) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0x3fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xc0000000U & ((0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xfU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x1dU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (4U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x200000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x800000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x100U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x2000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x400U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x8000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x1000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x1dU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x4000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U])); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x19U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1aU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1bU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1cU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1dU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1eU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 2U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xfU)) | - (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U])))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xbU)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 4U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 8U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 9U)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 5U)) | ( - (0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xaU)) - | (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xeU)) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 3U)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xcU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0x11U)) - | ((0x20000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 4U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0x13U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x17U)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 6U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xaU)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x19U)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x1dU)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xcU)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x1bU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | ((4U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x11U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 2U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xdU)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 2U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 6U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xbU)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 7U)) | ( - (0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 8U)) - | (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 9U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xcU)) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 5U)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xaU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xfU)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 2U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 2U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0x11U)) - | (0x80000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x15U)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 4U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x13U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 8U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x17U)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x1bU)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xaU)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x19U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 2U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x13U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 4U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xfU)) | - ((0x10U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 4U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xdU)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 9U)) | ( - (0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 6U)) - | (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xbU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xaU)) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 7U)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xdU)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 4U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xbU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfff80000U & ((0x200000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xfU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x13U)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 2U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 6U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x15U)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x19U)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 8U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x17U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 4U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x15U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 6U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x11U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 2U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x13U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 2U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xfU)) - | (0x40U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xbU)) | - ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 4U)) | - (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 8U)) | - ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 9U)) | - (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xbU)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 6U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 9U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 2U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xdU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x11U)) - | ((0x800000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 4U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x13U)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x17U)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 6U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 6U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x17U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 8U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x13U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 4U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffffffc0U & ((0x100U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x11U)) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xdU)) | - ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 2U)) | - (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 6U)) | - ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xbU)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 9U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 8U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 4U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xbU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xfU)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 2U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 2U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x11U)) - | (0x2000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x15U)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 4U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x13U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 8U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x19U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xaU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x15U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 6U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x17U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 2U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x13U)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xfU)) | - ((0x400U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 4U)) | - ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xdU)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 7U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xaU)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 5U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 6U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 9U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xdU)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 4U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xbU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfe000000U & ((0x8000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xfU)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x13U)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 2U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xaU)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x1bU)) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xcU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x17U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 8U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x19U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 4U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x15U)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0x11U)) - | ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 2U)) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x13U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 2U)) | - ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xfU)) - | (0x1000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 5U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xcU)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 3U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 8U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 7U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xaU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xbU)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 6U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 9U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 2U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xdU)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x11U)) - | ((0x20000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xcU)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x1dU)) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xeU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x19U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xaU)) | - (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x1bU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 6U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x17U)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0x13U)) - | ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 4U)) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffff000U & ((0x4000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0x11U)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 3U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xeU)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 1U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xaU)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 5U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xcU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 9U)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 8U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 4U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xbU)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xfU)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 2U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data - = ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((0x1000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((0x800U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((0x20U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | ((0x10U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | ((8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U)) - | (1U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data)))))))))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xfU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xeU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xdU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xcU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xbU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xaU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 9U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 8U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data - = ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((0x2000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((0x1000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((0x800U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((0x20U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((0x10U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | ((8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))))))))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xfU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xeU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xdU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xcU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xbU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xaU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 9U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 8U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffffff0U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xeU)) | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 1U))) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xfU)) | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xffffff0fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xcU)) | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 3U))) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xdU)) | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffff0ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xaU)) | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 5U))) - | ((0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xbU)) | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 4U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xffff0fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 8U)) | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 7U))) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 9U)) | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 6U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfff0ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 6U)) | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 9U))) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 7U)) | (0x10000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 8U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xff0fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 4U)) | (0x400000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xbU))) - | ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 5U)) | (0x100000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xaU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xf0ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 2U)) | (0x4000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xdU))) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 3U)) | (0x1000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xcU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xfU))) | ((0x20000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 1U)) - | (0x10000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xeU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffeULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | (IData)((IData)((1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffeffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 1U))))) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffeffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 2U))))) - << 0x20U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffeffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 3U))))) - << 0x30U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffdULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 4U))))) - << 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffdffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 5U))))) - << 0x11U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffdffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 6U))))) - << 0x21U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffdffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 7U))))) - << 0x31U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffbULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 8U))))) - << 2U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffbffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 9U))))) - << 0x12U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffbffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xaU))))) - << 0x22U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffbffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xbU))))) - << 0x32U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffff7ULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xcU))))) - << 3U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffff7ffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xdU))))) - << 0x13U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffff7ffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xeU))))) - << 0x23U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfff7ffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xfU))))) - << 0x33U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffefULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x10U))))) - << 4U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffefffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x11U))))) - << 0x14U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffefffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x12U))))) - << 0x24U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffefffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x13U))))) - << 0x34U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffdfULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x14U))))) - << 5U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffdfffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x15U))))) - << 0x15U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffdfffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x16U))))) - << 0x25U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffdfffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x17U))))) - << 0x35U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffbfULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x18U))))) - << 6U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffbfffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x19U))))) - << 0x16U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffbfffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1aU))))) - << 0x26U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffbfffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1bU))))) - << 0x36U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffff7fULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1cU))))) - << 7U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffff7fffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1dU))))) - << 0x17U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffff7fffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1eU))))) - << 0x27U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xff7fffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1fU))))) - << 0x37U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffeffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x20U))))) - << 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffeffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x21U))))) - << 0x18U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffeffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x22U))))) - << 0x28U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfeffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x23U))))) - << 0x38U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffdffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x24U))))) - << 9U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffdffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x25U))))) - << 0x19U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffdffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x26U))))) - << 0x29U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfdffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x27U))))) - << 0x39U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffbffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x28U))))) - << 0xaU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffbffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x29U))))) - << 0x1aU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffbffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2aU))))) - << 0x2aU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfbffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2bU))))) - << 0x3aU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffff7ffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2cU))))) - << 0xbU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffff7ffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2dU))))) - << 0x1bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffff7ffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2eU))))) - << 0x2bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xf7ffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2fU))))) - << 0x3bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffefffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x30U))))) - << 0xcU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffefffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x31U))))) - << 0x1cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffefffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x32U))))) - << 0x2cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xefffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x33U))))) - << 0x3cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffdfffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x34U))))) - << 0xdU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffdfffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x35U))))) - << 0x1dU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffdfffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x36U))))) - << 0x2dU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xdfffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x37U))))) - << 0x3dU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffbfffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x38U))))) - << 0xeU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffbfffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x39U))))) - << 0x1eU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffbfffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3aU))))) - << 0x2eU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xbfffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3bU))))) - << 0x3eU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffff7fffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3cU))))) - << 0xfU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffff7fffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3dU))))) - << 0x1fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffff7fffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3eU))))) - << 0x2fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0x7fffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3fU))))) - << 0x3fU)); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | ((0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | (1U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data)))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior - = (0xffffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & (IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffffffff0000ULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | (IData)((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout))); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | ((0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) - | ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x10U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__1.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__1.cpp deleted file mode 100644 index 611de5d..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__1.cpp +++ /dev/null @@ -1,9038 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -extern const VlUnpacked Vmain__ConstPool__TABLE_h4c25b041_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h7fc47693_0; -extern const VlWide<18>/*575:0*/ Vmain__ConstPool__CONST_hb679b2e5_0; -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h97873ec7_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h179527bd_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h164a10d3_0; -extern const VlWide<15>/*479:0*/ Vmain__ConstPool__CONST_hbd99daea_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h40cc9f5d_0; - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__1(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__1\n"); ); - // Init - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__i_crc_data = 0; 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- __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__i_crc_data = 0; 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- __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__i_crc_data = 0; - SData/*8:0*/ __Vtableidx5; - __Vtableidx5 = 0; - CData/*4:0*/ __Vtableidx7; - __Vtableidx7 = 0; - CData/*7:0*/ __Vtableidx9; - __Vtableidx9 = 0; - IData/*31:0*/ __Vdlyvval__main__DOT__clock_generator__DOT__counter__v7; - __Vdlyvval__main__DOT__clock_generator__DOT__counter__v7 = 0; - VlWide<16>/*511:0*/ __Vtemp_hc1d82fb0__0; - VlWide<16>/*511:0*/ __Vtemp_hbcf58278__0; - VlWide<16>/*511:0*/ __Vtemp_hcfafa750__0; - VlWide<16>/*511:0*/ __Vtemp_haaa3c8b7__0; - VlWide<16>/*511:0*/ __Vtemp_hc1851150__0; - VlWide<16>/*511:0*/ __Vtemp_hfebc76e7__0; - // Body - if ((1U & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)))) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = 0U; - } else { - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__i_crc_data - = (1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__51__Vfuncout; - } - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__69__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__69__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__69__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__69__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__69__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__69__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__69__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__69__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__63__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__57__Vfuncout; - } - } - if ((1U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)))) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = 0U; - } else { - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__i_crc_data - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__93__Vfuncout; - } - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__111__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__105__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__105__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__105__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__105__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__105__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__105__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__105__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__105__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__99__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__99__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__99__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__99__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__99__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__99__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__99__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__99__Vfuncout; - } - } - if ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = 0U; - } else { - if ((((3U == ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U)) & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb)))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__i_crc_data - = (1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__48__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__Vfuncout - = ((0x8000U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__prior)) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__47__Vfuncout; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__i_crc_data - = (1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__49__Vfuncout; - } - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = 0U; - } else if ((((3U == ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U)) & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb)))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__66__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__Vfuncout - = ((0x8000U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__prior)) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__65__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__60__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__Vfuncout - = ((0x8000U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__prior)) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__59__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__54__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__Vfuncout - = ((0x8000U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__prior)) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__53__Vfuncout; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))))) { - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__67__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__61__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__prior - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__55__Vfuncout; - } - } - if ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = 0U; - } else { - if ((((3U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U)) & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb)))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__i_crc_data - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__89__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__90__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__89__Vfuncout - = ((0x8000U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__89__prior)) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__89__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__89__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__89__Vfuncout; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__i_crc_data - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__91__Vfuncout; - } - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = 0U; - } else if ((((3U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U)) & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb)))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__107__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__108__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__107__Vfuncout - = ((0x8000U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__107__prior)) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__107__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__107__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__107__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__102__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__102__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__102__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__102__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__102__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__102__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__102__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__101__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__102__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__101__Vfuncout - = ((0x8000U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__101__prior)) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__101__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__101__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__101__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__96__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__Vfuncout - = ((0x8000U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__prior)) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__95__Vfuncout; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))))) { - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__109__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__103__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__103__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__103__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__103__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__103__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__103__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__103__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__103__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__i_crc_data - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__prior - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__i_crc_data))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__prior) - << 1U))) - : (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__prior) - << 1U))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__STEPCRC__97__Vfuncout; - } - } - if ((1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b))) { - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 - = (0xffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0U; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b; - } - if ((2U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b))) { - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 - = (0xffU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 8U; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b; - } - if ((4U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b))) { - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 - = (0xffU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0x10U; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b; - } - if ((8U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b))) { - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0x18U; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b; - } - if ((1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a))) { - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 - = (0xffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0U; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a; - } - if ((2U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a))) { - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 - = (0xffU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 8U; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a; - } - if ((4U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a))) { - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 - = (0xffU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0x10U; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a; - } - if ((8U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a))) { - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0x18U; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a; - } - if ((1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b))) { - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 - = (0xffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0U; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b; - } - if ((2U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b))) { - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 - = (0xffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 8U; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b; - } - if ((4U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b))) { - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 - = (0xffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0x10U; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b; - } - if ((8U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b))) { - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0x18U; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b; - } - if ((1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a))) { - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 - = (0xffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0U; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a; - } - if ((2U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a))) { - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 - = (0xffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - >> 8U)); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 8U; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a; - } - if ((4U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a))) { - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 - = (0xffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - >> 0x10U)); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0x10U; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a; - } - if ((8U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a))) { - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - >> 0x18U); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 1U; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0x18U; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a; - } - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = ((6U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)) - | (1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))); - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (1U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (1U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (1U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 3U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (1U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (6U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = ((5U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)) - | (2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 1U) & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (2U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 1U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (2U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 1U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (2U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 1U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 3U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (2U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (5U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = ((3U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)) - | (4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 2U) & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (4U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 2U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (4U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 2U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (4U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 2U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 3U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (4U | (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant - = (3U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant)); - } - if ((1U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]))) { - if ((1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xffeU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (1U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]] : 0U) & (~ ( - (0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U])))))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffeU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffeU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffeU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((2U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 1U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 1U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xffdU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (2U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) ? (0xfffffffeU - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]]) : 0U) - & ((~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]))) - << 1U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffdU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffdU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffdU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((4U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 2U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 2U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xffbU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (4U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) ? (0xfffffffcU - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]]) : 0U) - & ((~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]))) - << 2U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffbU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffbU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xffbU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((8U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 3U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 3U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xff7U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (8U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) ? (0xfffffff8U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]]) : 0U) - & ((~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]))) - << 3U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xff7U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xff7U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xff7U & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((0x10U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 4U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 4U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xfefU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (0x10U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) ? (0xfffffff0U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]]) - : 0U) & ((~ ((0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]))) - << 4U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfefU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfefU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfefU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((0x20U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 5U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 5U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xfdfU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (0x20U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) ? (0xffffffe0U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]]) - : 0U) & ((~ ((0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]))) - << 5U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfdfU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfdfU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfdfU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((0x40U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 6U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xfbfU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (0x40U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) ? (0xffffffc0U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]]) - : 0U) & ((~ ((0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]))) - << 6U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfbfU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfbfU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xfbfU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((0x80U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 7U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 7U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xf7fU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (0x80U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) ? (0xffffff80U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]]) - : 0U) & ((~ ((0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]))) - << 7U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xf7fU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xf7fU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xf7fU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((0x100U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 8U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xeffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (0x100U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) ? (0xffffff00U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]]) - : 0U) & ((~ ( - (0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]))) - << 8U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xeffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xeffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xeffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((0x200U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 9U))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xdffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (0x200U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) ? (0xfffffe00U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]]) - : 0U) & ((~ ( - (0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]))) - << 9U)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xdffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xdffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xdffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((0x400U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 0xaU)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 0xaU))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0xbffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (0x400U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) ? (0xfffffc00U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]]) - : 0U) & ((~ ( - (0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]))) - << 0xaU)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xbffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xbffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if (vlSelf->i_reset) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0xbffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - if ((0x800U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]))) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 0xbU)) | (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 0xbU))))) { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = ((0x7ffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)) - | (0x800U & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) ? (0xfffff800U - & vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]]) - : 0U) & ((~ ( - (0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]))) - << 0xbU)))); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0x7ffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - } else { - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb - = (0x7ffU & (IData)(vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xffeU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (1U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & (vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (1U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); 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- if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 2U) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (4U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xffbU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xff7U & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (8U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 3U) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (8U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xff7U & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xfefU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (0x10U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 4U) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x10U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xfefU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xfdfU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (0x20U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 5U) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x20U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xfdfU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xfbfU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (0x40U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 6U) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x40U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xfbfU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xf7fU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (0x80U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 7U) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x80U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xf7fU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xeffU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (0x100U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 8U) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x100U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xeffU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xdffU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (0x200U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 9U) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x200U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xdffU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0xbffU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (0x400U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 0xaU) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x400U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0xbffU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = ((0x7ffU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)) - | (0x800U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))); - if ((1U & ((vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 0xbU) & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty))))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x800U | (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - if (vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant - = (0x7ffU & (IData)(vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant)); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__high_z = 0U; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_ack - = vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__uins_ctr____pinNumber5; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_ack - = vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__upstall_ctr____pinNumber5; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_ack - = vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__umstall_ctr____pinNumber5; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_ack - = vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__utask_ctr____pinNumber5; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_ack - = vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mins_ctr____pinNumber5; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_ack - = vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mpstall_ctr____pinNumber5; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_ack - = vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mmstall_ctr____pinNumber5; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_ack - = vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mtask_ctr____pinNumber5; - vlSelf->o_sys_pwm = (((IData)(vlSelf->main__DOT__u_fan__DOT__ctl_sys) - >= (IData)(vlSelf->main__DOT__u_fan__DOT__pwm_counter)) - | (0x1387U <= (IData)(vlSelf->main__DOT__u_fan__DOT__ctl_sys))); - vlSelf->o_fpga_pwm = (((IData)(vlSelf->main__DOT__u_fan__DOT__ctl_fpga) - >= (IData)(vlSelf->main__DOT__u_fan__DOT__pwm_counter)) - | (0x1387U <= (IData)(vlSelf->main__DOT__u_fan__DOT__ctl_fpga))); - vlSelf->o_sirefclk_word = ((0x80U & (vlSelf->main__DOT__clock_generator__DOT__counter - [1U] >> 0x18U)) - | ((0x40U & (vlSelf->main__DOT__clock_generator__DOT__counter - [2U] >> 0x19U)) - | ((0x20U & (vlSelf->main__DOT__clock_generator__DOT__counter - [3U] - >> 0x1aU)) - | ((0x10U & (vlSelf->main__DOT__clock_generator__DOT__counter - [4U] - >> 0x1bU)) - | ((8U & (vlSelf->main__DOT__clock_generator__DOT__counter - [5U] - >> 0x1cU)) - | ((4U & - (vlSelf->main__DOT__clock_generator__DOT__counter - [6U] - >> 0x1dU)) - | ((2U - & (vlSelf->main__DOT__clock_generator__DOT__counter - [7U] - >> 0x1eU)) - | (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] - >> 0x1fU)))))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_ckspd - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_ckspd - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__pc_tag_lookup - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags - [(7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))] << 3U) | (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))); - if (vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset) { - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty = 1U; - } else if ((1U == (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd)))) { - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty - = (1U >= (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill)); - } else if ((2U == (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd)))) { - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty = 0U; - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__ps_full) - & (~ (IData)(vlSelf->main__DOT__txv__DOT__r_busy)))) { - vlSelf->o_wbu_uart_tx = 0U; - } else if (vlSelf->main__DOT__txv__DOT__zero_baud_counter) { - vlSelf->o_wbu_uart_tx = (1U & (IData)(vlSelf->main__DOT__txv__DOT__lcl_data)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_tag_lookup - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags - [(7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))] << 3U) | (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_last - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_v_from_last) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_invalidate_result))); - vlSelf->main__DOT__i2cscopei__DOT__br_level_interrupt - = (1U & (IData)(((4U == (5U & (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config))) - & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - >> 4U)))); - vlSelf->main__DOT__sdioscopei__DOT__br_level_interrupt - = (1U & (IData)(((4U == (5U & (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config))) - & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - >> 4U)))); - vlSelf->main__DOT__emmcscopei__DOT__br_level_interrupt - = (1U & (IData)(((4U == (5U & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config))) - & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - >> 4U)))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim_immv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv; - } - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full - = ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset)) - & ((1U != (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd))) - & ((2U == (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd))) - ? (0x1fU == (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill)) - : (0x20U == (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p) - << 1U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p) - << 1U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p) - << 1U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p) - << 1U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_umpy_result - = ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input)) - * (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_smpy_result - = VL_MULS_QQQ(64, (((QData)((IData)((- (IData)( - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input - >> 0x1fU))))) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input))), - (((QData)((IData)((- (IData)( - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input - >> 0x1fU))))) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input)))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__pre_sign - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl - = (((0U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU) != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1fU))) | ((2U - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU) - == - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1fU)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl - = (((((0U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU) != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1fU))) | ( - (2U - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU) - == - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1fU)))) - | (6U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) - | (5U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c = 0U; - if ((1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 3U)))) { - if ((4U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) { - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c - = (1U & ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_asr_result) - : (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result - >> 0x20U)))); - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c - = (1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result)); - } - } else if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c - = (1U & (IData)((1ULL & (((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))) - >> 0x20U)))); - } - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c - = (1U & (IData)((1ULL & (((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - - (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))) - >> 0x20U)))); - } - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - = ((8U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? ((4U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result))) - : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result - >> 0x20U)) : (IData)( - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result - >> 0x20U))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? ((0xffff0000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata) - | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)) - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_brev_result))) - : ((4U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_asr_result - >> 1U)) : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result)) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result - >> 1U)) : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - ^ vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))) - : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - | vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr) - : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - + vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr) - : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))))); - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_hi) - ? (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result - >> 0x20U)) : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result)); - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)))) { - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data - = vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data; - } - if (((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mins_ctr____pinNumber5) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we))) { - vlSelf->main__DOT__swic__DOT__mic_int = (1U - & (IData)( - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__sys_data)) - >> 0x20U))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data - = vlSelf->main__DOT__swic__DOT__sys_data; - } else if (vlSelf->main__DOT__swic__DOT__cpu_i_count) { - vlSelf->main__DOT__swic__DOT__mic_int = (1U - & (IData)( - (1ULL - & ((1ULL - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data))) - >> 0x20U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data); - } else { - vlSelf->main__DOT__swic__DOT__mic_int = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mpstall_ctr____pinNumber5) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we))) { - vlSelf->main__DOT__swic__DOT__mpc_int = (1U - & (IData)( - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__sys_data)) - >> 0x20U))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data - = vlSelf->main__DOT__swic__DOT__sys_data; - } else if (vlSelf->main__DOT__swic__DOT__cpu_pf_stall) { - vlSelf->main__DOT__swic__DOT__mpc_int = (1U - & (IData)( - (1ULL - & ((1ULL - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data))) - >> 0x20U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data); - } else { - vlSelf->main__DOT__swic__DOT__mpc_int = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mmstall_ctr____pinNumber5) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we))) { - vlSelf->main__DOT__swic__DOT__moc_int = (1U - & (IData)( - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__sys_data)) - >> 0x20U))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data - = vlSelf->main__DOT__swic__DOT__sys_data; - } else if (vlSelf->main__DOT__swic__DOT__cpu_op_stall) { - vlSelf->main__DOT__swic__DOT__moc_int = (1U - & (IData)( - (1ULL - & ((1ULL - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data))) - >> 0x20U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data); - } else { - vlSelf->main__DOT__swic__DOT__moc_int = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[1U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[2U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[3U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[4U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[5U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[6U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[7U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[8U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[9U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xaU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xbU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xcU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xdU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xeU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr)][0xfU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[1U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[2U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[3U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[4U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[5U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[6U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[7U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[8U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[9U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xaU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xbU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xcU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xdU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xeU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))][0xfU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result - = ((2U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__req_data) - >> 6U))) ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xfU] - >> 0x10U) : ((3U - == - (3U - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__req_data) - >> 6U))) - ? - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xfU] - >> 0x18U) - : - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xfU])); - vlSelf->main__DOT__swic__DOT__wdbus_ack = ((~ ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__sys_cyc)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_bus_watchdog))); - if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x12U]; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) - & (0ULL == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[1U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[2U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[3U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[4U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[5U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[6U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[7U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[8U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[9U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xaU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xbU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xcU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xdU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xeU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 6U))][0xfU]; - if (vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty = 1U; - } else if ((1U == (((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd)))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty - = (1U >= (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill)); - } else if ((2U == (((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd)))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[1U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[2U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[3U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[4U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[5U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[6U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[7U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[8U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[9U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xaU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xbU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xcU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xdU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xeU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache - [(0x3fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 6U))][0xfU]; - vlSelf->main__DOT__r_sirefclk_ack = ((~ (IData)(vlSelf->i_reset)) - & (IData)(vlSelf->main__DOT__wb32_sirefclk_stb)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__clk90 - = ((~ (IData)(vlSelf->i_reset)) & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__clk90 - = ((~ (IData)(vlSelf->i_reset)) & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90)); - vlSelf->main__DOT__wb32_spio_ack = ((~ (IData)(vlSelf->i_reset)) - & (IData)(vlSelf->main__DOT__wb32_spio_stb)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out - = (3U & (- (IData)(((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2fU))))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy - = ((~ (IData)(vlSelf->i_reset)) & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy))); - if ((4U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av - = ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av - : (0xeb800000U | ((0x7f0000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av) - | ((0x10U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags))))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl)); - } - __Vtableidx7 = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce)); - if (Vmain__ConstPool__TABLE_h4c25b041_0[__Vtableidx7]) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F - = Vmain__ConstPool__TABLE_h7fc47693_0[__Vtableidx7]; - } - if ((4U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc))) { - if ((0U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v - + (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I - << 2U)); - } else if ((1U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv - = (((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv - : (0xeb800000U | ((0x7f0000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv) - | ((0x10U - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags))))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - : 0U)) + vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I); - } else if ((2U == (2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl; - } - } - if (vlSelf->main__DOT__u_i2cdma__DOT__skd_ready) { - vlSelf->main__DOT__wbwide_i2cdma_data[0U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[1U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[2U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[3U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[4U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[5U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[6U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[7U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[8U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[9U] = - (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) | - (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[0xaU] - = (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) - | (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[0xbU] - = (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) - | (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[0xcU] - = (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) - | (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[0xdU] - = (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) - | (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[0xeU] - = (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) - | (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); - vlSelf->main__DOT__wbwide_i2cdma_data[0xfU] - = (((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x18U) | ((0xff0000U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 0x10U)) - | ((0xff00U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - << 8U)) - | (0xffU & (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data))))); 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(0x1fU == (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill)) - : (0x20U == (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill))))); - if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy)))) { - vlSelf->main__DOT__wbu_data = (((IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x1fU)) - << 0x1eU) | - (0x3fffffffU - & (IData)(vlSelf->main__DOT__genbus__DOT__ififo_codword))); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__gie - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - >> 4U)); - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)))))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr - = ((1U & (IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x20U))) ? ((1U & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1fU))) - ? ((1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1eU))) - ? - ((0x1000000U - & ((IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1dU)) - << 0x18U)) - | (0xffffffU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 6U)))) - : - (0xffffffU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 6U)))) - : ((1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1eU))) - ? - ((0x1fc0000U - & ((- (IData)( - (1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1dU))))) - << 0x12U)) - | (0x3ffffU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0xcU)))) - : - (0x3ffffU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0xcU))))) - : ((1U & (IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1fU))) ? ((1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1eU))) - ? - ((0x1fff000U - & ((- (IData)( - (1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1dU))))) - << 0xcU)) - | (0xfffU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x12U)))) - : - (0xfffU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x12U)))) - : ((1U & (IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1eU))) ? - ((0x1ffffc0U & ((- (IData)((1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1dU))))) - << 6U)) | (0x3fU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x18U)))) - : (0x3fU & (IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x18U)))))); - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0U]; 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- vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U] - = vlSelf->main__DOT__wbwide_i2cm_addr; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x10U]; 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(IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_we) - : (IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_we)); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset)) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe) - >> 1U)))); - vlSelf->main__DOT__wbwide_bkram_idata[0U] = vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr][0U]; - vlSelf->main__DOT__wbwide_bkram_idata[1U] = vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr][1U]; 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- vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x12U] - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid)) - | (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall))))) { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_addr - = (0x3fffffU & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U]); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x12U] - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)) - | (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall))))) { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr - = (0x3fffffU & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U]); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x12U] - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - >> 0x16U)); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z = 1U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign))) - & (~ (IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff - >> 0x20U))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z = 0U; - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch - = ((((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__cword - == (((IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word - >> 0x1fU)) << 0x1eU) | - (0x3fffffffU & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word)))) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch)) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched))) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__vaddr)); - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb))))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch = 0U; - } - if (vlSelf->main__DOT__swic__DOT__dc_cyc) { - if ((((IData)(vlSelf->main__DOT__swic__DOT__dc_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__dc_stb)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc)))) { - vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner = 0U; - } - } else { - vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner = 1U; - } - vlSelf->main__DOT__wbwide_bkram_ack = ((~ (IData)(vlSelf->i_reset)) - & ((IData)(vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 1U))); - vlSelf->main__DOT__swic__DOT__jif_ack = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_jiffies__i_wb_stb)); - vlSelf->main__DOT__swic__DOT__tmc_ack = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_c__i_wb_stb)); - vlSelf->main__DOT__swic__DOT__tmb_ack = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_b__i_wb_stb)); - vlSelf->main__DOT__swic__DOT__tma_ack = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_a__i_wb_stb)); - vlSelf->main__DOT__swic__DOT__wdt_ack = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchdog__i_wb_stb)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size; - } - vlSelf->main__DOT__swic__DOT__sys_ack = ((4U & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? ((2U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? (IData)(vlSelf->main__DOT__swic__DOT__last_sys_stb) - : (IData)(vlSelf->main__DOT__swic__DOT__dmac_ack)) - : (IData)(vlSelf->main__DOT__swic__DOT__last_sys_stb)) - : ((2U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? (IData)(vlSelf->main__DOT__swic__DOT__last_sys_stb) - : - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? (IData)(vlSelf->main__DOT__swic__DOT__last_sys_stb) - : (IData)(vlSelf->main__DOT__swic__DOT__r_mmus_ack)))); - if ((1U & ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__sys_cyc))))) { - vlSelf->main__DOT__swic__DOT__sys_ack = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel = 0ULL; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel = 0ULL; - } else if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy) { - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel; - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel = 0ULL; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel = 0ULL; - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - = (0x8000000000000000ULL >> (0x3fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - = (0x8000000000000000ULL >> (0x3fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)); - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - = (0xc000000000000000ULL >> (0x3eU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - = ((0x4000000000000000ULL | ((QData)((IData)( - (1U - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - << 0x3fU)) - >> (0x3eU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)); - } - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - = (0xf000000000000000ULL >> (0x3cU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - = ((2U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? ((1U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? (0x1000000000000000ULL >> - (0x3cU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : (0x3000000000000000ULL >> - (0x3cU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))) - : ((1U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? (0x7000000000000000ULL >> - (0x3cU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : (0xf000000000000000ULL >> - (0x3cU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)))); - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel = 0xffffffffffffffffULL; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - = (0xffffffffffffffffULL >> (0x3fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)); - } - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg - = vlSelf->main__DOT__swic__DOT__cmd_waddr; - } - vlSelf->main__DOT__wb32_wbdown_idata = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant) - ? vlSelf->main__DOT__wb32_xbar__DOT__s_data - [vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U]] : 0U); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_dbg_stall - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (0xeU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__last_write_to_cc - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))))); - if ((1U & ((((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc))) - | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc))) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } else { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU]; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__iflags - = (0xfU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__iflags - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0x1eU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__flags - = (0xfU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__flags - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags; - } - __Vtableidx9 = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay) - << 6U) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) - << 5U) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal) - << 4U) | - (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v) - << 3U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance) - << 2U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__rvsrc - = Vmain__ConstPool__TABLE_h97873ec7_0[__Vtableidx9]; - if ((2U & Vmain__ConstPool__TABLE_h179527bd_0[__Vtableidx9])) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay - = Vmain__ConstPool__TABLE_h164a10d3_0[__Vtableidx9]; - } - if (((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mtask_ctr____pinNumber5) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we))) { - vlSelf->main__DOT__swic__DOT__mtc_int = (1U - & (IData)( - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__sys_data)) - >> 0x20U))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data - = vlSelf->main__DOT__swic__DOT__sys_data; - } else if (vlSelf->main__DOT__swic__DOT__cmd_halt) { - vlSelf->main__DOT__swic__DOT__mtc_int = 0U; - } else { - vlSelf->main__DOT__swic__DOT__mtc_int = (1U - & (IData)( - (1ULL - & ((1ULL - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data))) - >> 0x20U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase = 0U; - } else { - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak = 1U; - } else if (((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & (0x1eU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubreak) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 7U)); - } - if (((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & (0x1eU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubus_err_flag) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 0xaU)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_u) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 8U)); - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag = 1U; - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u = 1U; - } - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase; - } else if ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & (0x1fU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase - = (1U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 1U)); - } - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy) { - if (((((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full))) - & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[1U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[1U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel - = (((QData)((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[3U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[2U]))); - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[8U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xfU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[8U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xfU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel = 0ULL; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_stb - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid))); - vlSelf->main__DOT__i2cscopei__DOT__o_bus_data = - ((IData)(vlSelf->main__DOT__i2cscopei__DOT__read_address) - ? ((0x10U & (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe)) - ? vlSelf->main__DOT__i2cscopei__DOT__nxt_mem - : vlSelf->main__DOT__i2cscopei__DOT__qd_data) - : (0xa00000U | (((~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U)) << 0x1fU) | - ((0x40000000U & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - << 0x1aU)) - | (((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_triggered) - << 0x1dU) | (((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_primed) - << 0x1cU) - | ((0x8000000U - & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - << 0x1aU)) - | ((0x4000000U - & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - << 0x1aU)) - | (((0U - == (IData)(vlSelf->main__DOT__i2cscopei__DOT__raddr)) - << 0x19U) - | vlSelf->main__DOT__i2cscopei__DOT__br_holdoff))))))))); - vlSelf->main__DOT__emmcscopei__DOT__o_bus_data - = ((IData)(vlSelf->main__DOT__emmcscopei__DOT__read_address) - ? ((0x10U & (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe)) - ? vlSelf->main__DOT__emmcscopei__DOT__nxt_mem - : vlSelf->main__DOT__emmcscopei__DOT__qd_data) - : (0xc00000U | (((~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U)) << 0x1fU) - | ((0x40000000U & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - << 0x1aU)) - | (((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_triggered) - << 0x1dU) | (((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_primed) - << 0x1cU) - | ((0x8000000U - & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - << 0x1aU)) - | ((0x4000000U - & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - << 0x1aU)) - | (((0U - == (IData)(vlSelf->main__DOT__emmcscopei__DOT__raddr)) - << 0x19U) - | vlSelf->main__DOT__emmcscopei__DOT__br_holdoff))))))))); - vlSelf->main__DOT__sdioscopei__DOT__o_bus_data - = ((IData)(vlSelf->main__DOT__sdioscopei__DOT__read_address) - ? ((0x10U & (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe)) - ? vlSelf->main__DOT__sdioscopei__DOT__nxt_mem - : vlSelf->main__DOT__sdioscopei__DOT__qd_data) - : (0xc00000U | (((~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U)) << 0x1fU) - | ((0x40000000U & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - << 0x1aU)) - | (((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_triggered) - << 0x1dU) | (((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_primed) - << 0x1cU) - | ((0x8000000U - & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - << 0x1aU)) - | ((0x4000000U - & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - << 0x1aU)) - | (((0U - == (IData)(vlSelf->main__DOT__sdioscopei__DOT__raddr)) - << 0x19U) - | vlSelf->main__DOT__sdioscopei__DOT__br_holdoff))))))))); - if (((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__uins_ctr____pinNumber5) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we))) { - vlSelf->main__DOT__swic__DOT__uic_int = (1U - & (IData)( - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__sys_data)) - >> 0x20U))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data - = vlSelf->main__DOT__swic__DOT__sys_data; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__cpu_i_count) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U))) { - vlSelf->main__DOT__swic__DOT__uic_int = (1U - & (IData)( - (1ULL - & ((1ULL - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data))) - >> 0x20U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data); - } else { - vlSelf->main__DOT__swic__DOT__uic_int = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__upstall_ctr____pinNumber5) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we))) { - vlSelf->main__DOT__swic__DOT__upc_int = (1U - & (IData)( - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__sys_data)) - >> 0x20U))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data - = vlSelf->main__DOT__swic__DOT__sys_data; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__cpu_pf_stall) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U))) { - vlSelf->main__DOT__swic__DOT__upc_int = (1U - & (IData)( - (1ULL - & ((1ULL - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data))) - >> 0x20U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data); - } else { - vlSelf->main__DOT__swic__DOT__upc_int = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__umstall_ctr____pinNumber5) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we))) { - vlSelf->main__DOT__swic__DOT__uoc_int = (1U - & (IData)( - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__sys_data)) - >> 0x20U))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data - = vlSelf->main__DOT__swic__DOT__sys_data; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__cpu_op_stall) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U))) { - vlSelf->main__DOT__swic__DOT__uoc_int = (1U - & (IData)( - (1ULL - & ((1ULL - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data))) - >> 0x20U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data); - } else { - vlSelf->main__DOT__swic__DOT__uoc_int = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__utask_ctr____pinNumber5) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we))) { - vlSelf->main__DOT__swic__DOT__utc_int = (1U - & (IData)( - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__sys_data)) - >> 0x20U))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data - = vlSelf->main__DOT__swic__DOT__sys_data; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__utc_int = (1U - & (IData)( - (1ULL - & ((1ULL - + (QData)((IData)(vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data))) - >> 0x20U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data - = ((IData)(1U) + vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data); - } else { - vlSelf->main__DOT__swic__DOT__utc_int = 0U; - } - vlSelf->main__DOT__w_sirefclk_unused_stb = (1U - & (IData)( - (1ULL - & (((QData)((IData)( - vlSelf->main__DOT__clock_generator__DOT__counter - [0U])) - + (QData)((IData)( - (vlSelf->main__DOT__clock_generator__DOT__r_delay - << 3U)))) - >> 0x20U)))); - __Vdlyvval__main__DOT__clock_generator__DOT__counter__v7 - = (vlSelf->main__DOT__clock_generator__DOT__counter - [0U] + (vlSelf->main__DOT__clock_generator__DOT__r_delay - << 3U)); - vlSelf->main__DOT__w_led = ((IData)(vlSelf->main__DOT__spioi__DOT__led_demo) - ? (IData)(vlSelf->main__DOT__spioi__DOT__bounced) - : (IData)(vlSelf->main__DOT__spioi__DOT__r_led)); - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_lock_pc - = (0xfffffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc - - (IData)(4U))); - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__pp_data = 0U; - vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift = 0x18U; - } else { - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U)))) { - vlSelf->main__DOT__u_emmc__DOT__pp_data - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xcU)); - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1aU)))) { - vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift - = (0x1fU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0x10U)); - } - } - vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift - = (0x18U & (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift)); - if (vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read) { - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_data - = vlSelf->main__DOT__console__DOT__txfifo__DOT__fifo - [vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next]; - } - if (vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read) { - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_data - = vlSelf->main__DOT__console__DOT__rxfifo__DOT__fifo - [vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next]; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift = 0x18U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x22U)))) { - vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift - = (0x1fU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0x10U)); - } - vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift - = (0x1cU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift)); - vlSelf->main__DOT__uart_debug = ((0x7fffU & vlSelf->main__DOT__uart_debug) - | (((IData)(vlSelf->main__DOT__console__DOT__txf_status) - << 0x14U) - | ((0xf0000U - & ((IData)(vlSelf->main__DOT__console__DOT__rxf_status) - << 0x10U)) - | (0x8000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)) - << 0xfU))))); - vlSelf->main__DOT__uart_debug = ((0xffff80ffU & vlSelf->main__DOT__uart_debug) - | (0x7f00U & ( - (((IData)( - (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 5U) - & (0x300U - == - (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])))) - & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 5U) - & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x14U)))) - ? - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[5U] - : - ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow) - ? 0U - : (IData)(vlSelf->main__DOT__w_console_tx_data))) - << 8U))); - vlSelf->main__DOT__uart_debug = ((0xffffff00U & vlSelf->main__DOT__uart_debug) - | (((IData)(vlSelf->main__DOT__w_console_rx_stb) - << 7U) | ((IData)(vlSelf->main__DOT__w_console_rx_stb) - ? (IData)(vlSelf->main__DOT__w_console_rx_data) - : (IData)(vlSelf->main__DOT__console__DOT__rxf_wb_data)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - : ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid)))); - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem)); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe = 0U; - } - vlSelf->main__DOT__wb32_uart_idata = ((2U & (IData)(vlSelf->main__DOT__console__DOT__r_wb_addr)) - ? ((1U & (IData)(vlSelf->main__DOT__console__DOT__r_wb_addr)) - ? (((IData)(vlSelf->__VdfgTmp_ha46ae6a3__0) - << 0xdU) - | ((((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__console__DOT__txf_wb_write)) - << 0xcU) - | ((0x400U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)) - << 0xaU)) - | (((IData)(vlSelf->main__DOT__console__DOT____VdfgTmp_h60af6732__0) - << 8U) - | ((IData)(vlSelf->main__DOT__console__DOT____VdfgTmp_h60af6732__0) - ? (IData)(vlSelf->main__DOT__console__DOT__txf_wb_data) - : 0U))))) - : (( - ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write)) - & (IData)(vlSelf->main__DOT__w_console_rx_stb)) - << 0xcU) - | (((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow) - << 8U) - | (IData)(vlSelf->main__DOT__console__DOT__rxf_wb_data)))) - : ((1U & (IData)(vlSelf->main__DOT__console__DOT__r_wb_addr)) - ? (((IData)(vlSelf->main__DOT__console__DOT__txf_status) - << 0x10U) - | (IData)(vlSelf->main__DOT__console__DOT__rxf_status)) - : 0U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_pc - = (((((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U)) == (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup - == (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))) & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask) - >> (7U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - >> 9U))))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_invalidate_result))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal))); - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda - = ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual) - ? (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda) - : (IData)(vlSelf->main__DOT__i2ci__DOT__w_sda))); - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl - = ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual) - ? (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl) - : (IData)(vlSelf->main__DOT__i2ci__DOT__w_scl))); - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_fpu) - << 2U) | ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div)) - << 1U) | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div)))); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index - = (3U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)); - if (((IData)(vlSelf->main__DOT__w_console_rx_stb) - & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow) - | ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read) - & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next) - == (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr)))))) { - vlSelf->main__DOT__console__DOT__rxfifo__DOT__last_write - = vlSelf->main__DOT__w_console_rx_data; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out - = ((2U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 6U)) | (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 3U)); - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack))) { - __Vtemp_hc1851150__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x30U]; - __Vtemp_hc1851150__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x31U]; - __Vtemp_hc1851150__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x32U]; - __Vtemp_hc1851150__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x33U]; - __Vtemp_hc1851150__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x34U]; - __Vtemp_hc1851150__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x35U]; - __Vtemp_hc1851150__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x36U]; - __Vtemp_hc1851150__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x37U]; - __Vtemp_hc1851150__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x38U]; - __Vtemp_hc1851150__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x39U]; - __Vtemp_hc1851150__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3aU]; - __Vtemp_hc1851150__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3bU]; - __Vtemp_hc1851150__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3cU]; - __Vtemp_hc1851150__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3dU]; - __Vtemp_hc1851150__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3eU]; - __Vtemp_hc1851150__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3fU]; - VL_SHIFTL_WWI(512,512,32, __Vtemp_hfebc76e7__0, __Vtemp_hc1851150__0, - (vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem - [(0x1fU & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr))] - << 5U)); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0U] - = __Vtemp_hfebc76e7__0[0U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[1U] - = __Vtemp_hfebc76e7__0[1U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[2U] - = __Vtemp_hfebc76e7__0[2U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[3U] - = __Vtemp_hfebc76e7__0[3U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[4U] - = __Vtemp_hfebc76e7__0[4U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[5U] - = __Vtemp_hfebc76e7__0[5U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[6U] - = __Vtemp_hfebc76e7__0[6U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[7U] - = __Vtemp_hfebc76e7__0[7U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[8U] - = __Vtemp_hfebc76e7__0[8U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[9U] - = __Vtemp_hfebc76e7__0[9U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xaU] - = __Vtemp_hfebc76e7__0[0xaU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xbU] - = __Vtemp_hfebc76e7__0[0xbU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xcU] - = __Vtemp_hfebc76e7__0[0xcU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xdU] - = __Vtemp_hfebc76e7__0[0xdU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xeU] - = __Vtemp_hfebc76e7__0[0xeU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xfU] - = __Vtemp_hfebc76e7__0[0xfU]; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - = (0x3fffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U)); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v) - >> (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U)))); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable - = (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce)); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending - = ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable)) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb))); - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err)))) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag - != vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv)))); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v) - >> (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cline))); - } - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid - = ((((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid))) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag - == vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending)); - if (((((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag - == vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag; - } else if ((((3U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state)) - & ((7U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag) - == (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)))) & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid = 0U; - } - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss - = (((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we))) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag - != vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv)))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__CLEAR_DCACHE__DOT__r_clear_dcache) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid = 0U; - } - vlSelf->main__DOT__r_wb32_sio_data = ((0x400U & - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]) - ? 0x20230723U - : ((0x200U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]) - ? ((0x100U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]) - ? - (((IData)(vlSelf->main__DOT__spioi__DOT__led_demo) - << 0x18U) - | (((IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn) - << 0x10U) - | (((IData)(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw) - << 8U) - | (IData)(vlSelf->main__DOT__spioi__DOT__r_led)))) - : - (((~ (IData)(vlSelf->main__DOT__r_sirefclk_en)) - << 0x1fU) - | vlSelf->main__DOT__r_sirefclk_data)) - : ((0x100U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]) - ? - (((IData)(vlSelf->main__DOT__gpioi__DOT__r_gpio) - << 0x10U) - | (IData)(vlSelf->o_gpio)) - : 0x82055U))); - if (((IData)(vlSelf->main__DOT__console__DOT__txf_wb_write) - & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow) - | ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read) - & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next) - == (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr)))))) { - vlSelf->main__DOT__console__DOT__txfifo__DOT__last_write - = vlSelf->main__DOT__console__DOT__txf_wb_data; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z - = (1U & (~ ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((~ (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2fU))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_cmd)))))); - if ((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 3U) & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 3U))))) { - vlSelf->main__DOT__i2ci__DOT__bus_read_data = 0U; - if ((0x2000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) { - vlSelf->main__DOT__i2ci__DOT__bus_read_data - = ((0x1000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]) - ? ((0xfffff000U & vlSelf->main__DOT__i2ci__DOT__bus_read_data) - | (IData)(vlSelf->main__DOT__i2ci__DOT__ckcount)) - : ((0xf0000000U & vlSelf->main__DOT__i2ci__DOT__bus_read_data) - | vlSelf->main__DOT__i2ci__DOT__pf_insn_addr)); - } else if ((0x1000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) { - vlSelf->main__DOT__i2ci__DOT__bus_read_data - = ((0xffff0000U & vlSelf->main__DOT__i2ci__DOT__bus_read_data) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl) - << 0xfU) | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda) - << 0xeU) | (((IData)(vlSelf->i_i2c_scl) - << 0xdU) - | (((IData)(vlSelf->i_i2c_sda) - << 0xcU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual) - << 0xbU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted) - << 0xaU) - | (IData)(vlSelf->main__DOT__i2ci__DOT__ovw_data)))))))); - } else { - vlSelf->main__DOT__i2ci__DOT__bus_read_data - = (((IData)(vlSelf->main__DOT__i2ci__DOT__half_insn) - << 0x1cU) | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual) - << 0x18U) | vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0)); - } - } - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__sdclk) - >> 7U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__sdclk) - >> 7U)); - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy) { - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes - = ((0U != (3U & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill) - >> 6U))) ? 0x40U : - (0x3fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill))); - } else if ((0U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes - = (0x7fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill)); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack))) { - __Vtemp_hc1d82fb0__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U]; - __Vtemp_hc1d82fb0__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U]; - __Vtemp_hc1d82fb0__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U]; - __Vtemp_hc1d82fb0__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U]; - __Vtemp_hc1d82fb0__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U]; - __Vtemp_hc1d82fb0__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U]; - __Vtemp_hc1d82fb0__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U]; - __Vtemp_hc1d82fb0__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U]; - __Vtemp_hc1d82fb0__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U]; - __Vtemp_hc1d82fb0__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U]; - __Vtemp_hc1d82fb0__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU]; - __Vtemp_hc1d82fb0__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU]; - __Vtemp_hc1d82fb0__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU]; - __Vtemp_hc1d82fb0__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU]; - __Vtemp_hc1d82fb0__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU]; - __Vtemp_hc1d82fb0__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU]; - VL_SHIFTL_WWI(512,512,32, __Vtemp_hbcf58278__0, __Vtemp_hc1d82fb0__0, - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift) - << 3U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U] - = __Vtemp_hbcf58278__0[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U] - = __Vtemp_hbcf58278__0[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U] - = __Vtemp_hbcf58278__0[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U] - = __Vtemp_hbcf58278__0[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U] - = __Vtemp_hbcf58278__0[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U] - = __Vtemp_hbcf58278__0[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U] - = __Vtemp_hbcf58278__0[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U] - = __Vtemp_hbcf58278__0[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U] - = __Vtemp_hbcf58278__0[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U] - = __Vtemp_hbcf58278__0[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU] - = __Vtemp_hbcf58278__0[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU] - = __Vtemp_hbcf58278__0[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU] - = __Vtemp_hbcf58278__0[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU] - = __Vtemp_hbcf58278__0[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU] - = __Vtemp_hbcf58278__0[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU] - = __Vtemp_hbcf58278__0[0xfU]; - } else if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU] = 0U; - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU] = 0U; - } - if ((1U & ((((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc))) - | (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err)) - | ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 3U))))) { - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel = 0ULL; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[1U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[2U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[3U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[4U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[5U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[6U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[7U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[8U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[9U] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xaU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xbU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xcU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xdU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xeU] = 0U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xfU] = 0U; - } else if ((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - & (~ (IData)(vlSelf->main__DOT__wbu_wbu_arbiter_stall))))) { - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr - = (0x3fffffU & (IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - >> 4U))); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb = 1U; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel - = ((0x3fU >= (0x3cU & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr) - << 2U))) ? (((QData)((IData)( - (0xfU - & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel)))) - << 0x3cU) - >> (0x3cU - & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr) - << 2U))) - : 0ULL); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we - = (1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe)); - __Vtemp_hcfafa750__0[0U] = Vmain__ConstPool__CONST_hbd99daea_0[0U]; - __Vtemp_hcfafa750__0[1U] = Vmain__ConstPool__CONST_hbd99daea_0[1U]; - __Vtemp_hcfafa750__0[2U] = Vmain__ConstPool__CONST_hbd99daea_0[2U]; - __Vtemp_hcfafa750__0[3U] = Vmain__ConstPool__CONST_hbd99daea_0[3U]; - __Vtemp_hcfafa750__0[4U] = Vmain__ConstPool__CONST_hbd99daea_0[4U]; - __Vtemp_hcfafa750__0[5U] = Vmain__ConstPool__CONST_hbd99daea_0[5U]; - __Vtemp_hcfafa750__0[6U] = Vmain__ConstPool__CONST_hbd99daea_0[6U]; - __Vtemp_hcfafa750__0[7U] = Vmain__ConstPool__CONST_hbd99daea_0[7U]; - __Vtemp_hcfafa750__0[8U] = Vmain__ConstPool__CONST_hbd99daea_0[8U]; - __Vtemp_hcfafa750__0[9U] = Vmain__ConstPool__CONST_hbd99daea_0[9U]; - __Vtemp_hcfafa750__0[0xaU] = Vmain__ConstPool__CONST_hbd99daea_0[0xaU]; - __Vtemp_hcfafa750__0[0xbU] = Vmain__ConstPool__CONST_hbd99daea_0[0xbU]; - __Vtemp_hcfafa750__0[0xcU] = Vmain__ConstPool__CONST_hbd99daea_0[0xcU]; - __Vtemp_hcfafa750__0[0xdU] = Vmain__ConstPool__CONST_hbd99daea_0[0xdU]; - __Vtemp_hcfafa750__0[0xeU] = Vmain__ConstPool__CONST_hbd99daea_0[0xeU]; - __Vtemp_hcfafa750__0[0xfU] = (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata); - VL_SHIFTR_WWI(512,512,32, __Vtemp_haaa3c8b7__0, __Vtemp_hcfafa750__0, - (0x1e0U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr) - << 5U))); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0U] - = __Vtemp_haaa3c8b7__0[0U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[1U] - = __Vtemp_haaa3c8b7__0[1U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[2U] - = __Vtemp_haaa3c8b7__0[2U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[3U] - = __Vtemp_haaa3c8b7__0[3U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[4U] - = __Vtemp_haaa3c8b7__0[4U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[5U] - = __Vtemp_haaa3c8b7__0[5U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[6U] - = __Vtemp_haaa3c8b7__0[6U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[7U] - = __Vtemp_haaa3c8b7__0[7U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[8U] - = __Vtemp_haaa3c8b7__0[8U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[9U] - = __Vtemp_haaa3c8b7__0[9U]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xaU] - = __Vtemp_haaa3c8b7__0[0xaU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xbU] - = __Vtemp_haaa3c8b7__0[0xbU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xcU] - = __Vtemp_haaa3c8b7__0[0xcU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xdU] - = __Vtemp_haaa3c8b7__0[0xdU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xeU] - = __Vtemp_haaa3c8b7__0[0xeU]; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xfU] - = __Vtemp_haaa3c8b7__0[0xfU]; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)))) { - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next = 1U; - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill; - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes - = (0x7fU & ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? 1U : ((2U < (0x7fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])) - ? 2U : (0x7fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U]))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? ((4U < (0x7fU & - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])) - ? 4U : (0x7fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])) - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U]))); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid)) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes - = (0x7fU & ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? 1U : ((4U <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill)) - ? 2U : ((3U - == - (3U - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))) - ? 1U - : 0U))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? ((8U <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill)) - ? 4U : ((4U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill)) - ? (3U - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill)) - : 0U)) - : 0U))); - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next = 1U; - } else if (((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next - = (1U & ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? (1U == (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])) - : (2U >= (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U]))) - : ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - | (4U >= (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U]))))); - if ((0x80U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next = 0U; - } - } else if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next - = (1U & ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? (2U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill)) - : (4U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))) - : ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - | (8U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))))); - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next = 0U; - } - } - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write = 0U; - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid = 1U; - } else if ((1U & (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid = 0U; - } - if (((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock)) - & (0U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall = 1U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall = 0U; - } - if (((((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR)) - & (0xeU == (0xeU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - != (0xfU | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write = 1U; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write = 0U; - } - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = 0xfcU; - vlSelf->main__DOT__u_emmc__DOT__pp_cmd = 0U; - } else { - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed - = (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]); - if ((2U > (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = 2U; - } else if ((0U == (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = 1U; - } - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U)))) { - vlSelf->main__DOT__u_emmc__DOT__pp_cmd - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xdU)); - } - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_FP = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI - = (0U == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_nxt_half - = (0x7fffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword); - } - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = 0U; - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en - = (1U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 7U)); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) { - if ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner = 0U; - } - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner = 1U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl - = (0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl - = (0xffU != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl = 0U; - } - if ((1U & (~ (IData)((0U != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl = 0U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_wF) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal))); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted) - & ((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)))); - } - if ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = 0U; - } else { - if (vlSelf->main__DOT__swic__DOT__pic_interrupt) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = 1U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = 1U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = 1U; - } - if (((((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = 1U; - } - } - } - if (vlSelf->main__DOT__console__DOT__tx_uart_reset) { - vlSelf->main__DOT__console__DOT__txfifo__DOT__osrc = 0U; - } else if (((IData)(vlSelf->main__DOT__console__DOT__txf_wb_write) - & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow) - | ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read) - & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next) - == (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr)))))) { - vlSelf->main__DOT__console__DOT__txfifo__DOT__osrc = 1U; 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(IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill) - : 0U); - if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x12U]; - } - __Vtableidx5 = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done) - << 8U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - << 7U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - << 6U) | - (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent) - << 5U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - << 4U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - << 3U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done) - << 2U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset) - << 1U) - | (IData)(vlSelf->i_reset))))))))); - vlSelf->main__DOT__sdcard_int = Vmain__ConstPool__TABLE_h40cc9f5d_0 - [__Vtableidx5]; - vlSelf->main__DOT__wb32_fan_idata = ((1U & ((IData)(vlSelf->i_reset) - | (~ - ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 7U)))) - ? 0U : ((IData)(vlSelf->main__DOT__u_fan__DOT__i2c_wb_ack) - ? vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data - : vlSelf->main__DOT__u_fan__DOT__pre_data)); - vlSelf->main__DOT__wb32_i2cdma_idata = 0U; - vlSelf->main__DOT__wb32_i2cdma_idata = ((2U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - ? ((0xf0000000U - & vlSelf->main__DOT__wb32_i2cdma_idata) - | ((1U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - ? vlSelf->main__DOT__u_i2cdma__DOT__r_memlen - : vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr)) - : ((1U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - ? - ((0xf0000000U - & vlSelf->main__DOT__wb32_i2cdma_idata) - | vlSelf->main__DOT__u_i2cdma__DOT__current_addr) - : - ((0xfffffffcU - & vlSelf->main__DOT__wb32_i2cdma_idata) - | ((((~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__wb_last)) - & (vlSelf->main__DOT__u_i2cdma__DOT__current_addr - != vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr)) - << 1U) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__bus_err))))); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack - = ((~ (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc))) - | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)))) - & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty) - ? (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null) - : (((IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data) - >> 4U) & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))); - vlSelf->main__DOT__wbu_zip_idata = vlSelf->main__DOT__swic__DOT__dbg_odata; - vlSelf->main__DOT__wb32_emmc_idata = 0U; - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel))) { - vlSelf->main__DOT__wb32_emmc_idata = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data; - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel))) { - vlSelf->main__DOT__wb32_emmc_idata = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a; - } else if ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel))) { - vlSelf->main__DOT__wb32_emmc_idata = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b; - } - vlSelf->main__DOT__wb32_sdcard_idata = 0U; - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel))) { - vlSelf->main__DOT__wb32_sdcard_idata = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data; - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel))) { - vlSelf->main__DOT__wb32_sdcard_idata = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a; - } else if ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel))) { - vlSelf->main__DOT__wb32_sdcard_idata = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b; - } - if ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc = 0U; - } else if (((((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc = 0U; - } - if ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc = 0U; - } else if (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out - = (3U & (- (IData)((1U & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1bU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out - = (3U & (- (IData)((1U & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1aU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out - = (3U & (- (IData)((1U & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x19U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out - = (3U & (- (IData)((1U & ((IData)(vlSelf->i_reset) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z - = (1U & (~ ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1bU)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z - = (1U & (~ ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1aU)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z - = (1U & (~ ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x19U)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z - = (1U & (~ ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data)))))); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr - = vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_dir - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_dir; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_owner; - vlSelf->main__DOT__txv__DOT__baud_counter = vlSelf->__Vdly__main__DOT__txv__DOT__baud_counter; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr - = vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr; - if (vlSelf->__Vdlyvset__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0] - = vlSelf->__Vdlyvval__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0; - } - vlSelf->main__DOT__swic__DOT__u_watchbus__DOT__r_value - = vlSelf->__Vdly__main__DOT__swic__DOT__u_watchbus__DOT__r_value; - vlSelf->main__DOT__genbus__DOT__ofifo_empty_n = vlSelf->__Vdly__main__DOT__genbus__DOT__ofifo_empty_n; - vlSelf->main__DOT__rcv__DOT__baud_counter = vlSelf->__Vdly__main__DOT__rcv__DOT__baud_counter; - vlSelf->main__DOT__swic__DOT__cmd_read = vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read; - vlSelf->main__DOT__i2cscopei__DOT__dr_force_inhibit - = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_inhibit; - vlSelf->main__DOT__sdioscopei__DOT__dr_force_inhibit - = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_inhibit; - vlSelf->main__DOT__emmcscopei__DOT__dr_force_inhibit - = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_inhibit; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow - = vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed - = vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_acks_needed; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len - = vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len; - vlSelf->main__DOT__genbus__DOT__r_wdt_timer = vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_timer; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend; - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0; - } - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow - = vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks; - vlSelf->main__DOT__i2cscopei__DOT__holdoff_counter - = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__holdoff_counter; - vlSelf->main__DOT__sdioscopei__DOT__holdoff_counter - = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__holdoff_counter; - vlSelf->main__DOT__emmcscopei__DOT__holdoff_counter - = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__holdoff_counter; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount; - vlSelf->main__DOT__i2ci__DOT__i2c_ckcount = vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckcount; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr - = vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill - = vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__r_fill; - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill - = vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__r_fill; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x10U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x11U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x12U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x13U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x14U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x15U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x16U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x17U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x18U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x19U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1aU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1bU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1cU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1dU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1eU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg[0x1fU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr; - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][0U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][1U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][2U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][3U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][4U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][5U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][6U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][7U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][8U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][9U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][0xaU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][0xbU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][0xcU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][0xdU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][0xeU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][0xfU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0][0x10U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0[0x10U]; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU] - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight; - if (vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v0) { - vlSelf->main__DOT__wbu_xbar__DOT__grant[0U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v1) { - vlSelf->main__DOT__wbu_xbar__DOT__grant[0U] - = vlSelf->__Vdlyvval__main__DOT__wbu_xbar__DOT__grant__v1; - } - if (vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v2) { - vlSelf->main__DOT__wbu_xbar__DOT__grant[0U] = 0U; - } - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow - = vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__inflight; - vlSelf->main__DOT__wbwide_i2cdma_sel = vlSelf->__Vdly__main__DOT__wbwide_i2cdma_sel; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid; - vlSelf->main__DOT__u_fan__DOT__pwm_counter = vlSelf->__Vdly__main__DOT__u_fan__DOT__pwm_counter; - vlSelf->main__DOT__txv__DOT__lcl_data = vlSelf->__Vdly__main__DOT__txv__DOT__lcl_data; - vlSelf->main__DOT__txv__DOT__zero_baud_counter - = vlSelf->__Vdly__main__DOT__txv__DOT__zero_baud_counter; - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0; - } - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill - = vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill; - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1); - } - if (vlSelf->main__DOT__console__DOT__tx_uart_reset) { - vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr = 0U; - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__rd_addr = 0U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next = 1U; - } else { - if (vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write) { - vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr - = vlSelf->main__DOT__console__DOT__txfifo__DOT__w_waddr_plus_one; - } - if (vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read) { - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__rd_addr - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr))); - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next - = (0x3fU & ((IData)(2U) + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr))); - } - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4); - } - if (vlSelf->main__DOT__console__DOT__rx_uart_reset) { - vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr = 0U; - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__rd_addr = 0U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next = 1U; - } else { - if (vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write) { - vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr - = vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_waddr_plus_one; - } - if (vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read) { - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__rd_addr - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr))); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next - = (0x3fU & ((IData)(2U) + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr))); - } - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5); 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- vlSelf->main__DOT__spioi__DOT__led_demo = 1U; - vlSelf->main__DOT__i2ci__DOT__ovw_data = 0U; - vlSelf->main__DOT__i2ci__DOT__ckcount = 0xfffU; - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl = 1U; - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda = 1U; - vlSelf->main__DOT__i2ci__DOT__r_aborted = 0U; - } else { - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))))) { - vlSelf->main__DOT__genbus__DOT__soft_reset - = ((IData)(vlSelf->main__DOT__genbus__DOT__rx_valid) - & (3U == (0x7fU & (IData)(vlSelf->main__DOT__wbu_rx_data)))); - } - if (((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__full_line - = ((~ ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_bits) - >> 6U)) & (0x49U <= (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen))); 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- vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda = 1U; - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_abort) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted)))) { - vlSelf->main__DOT__i2ci__DOT__r_aborted = 1U; - } - if (vlSelf->main__DOT__i2ci__DOT__bus_write) { - if (((IData)(((0U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - >> 0x15U))) & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xeU)))) { - vlSelf->main__DOT__i2ci__DOT__r_aborted = 0U; - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT__bus_jump) - & (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted))) { - vlSelf->main__DOT__i2ci__DOT__r_aborted = 0U; - } - } - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6); 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- } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34); - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data = 0xffffffffU; - } else { - if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid)) - & (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period))) { - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (1U | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 1U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xfefefefeU | ((0x1000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 7U)) - | ((0x10000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xfU)) - | ((0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x17U)) - | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x1fU))))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)) - & (3U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - ? 0xfU : 0x1fU); - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xfU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 4U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xf0f0f0f0U | ((0xf000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 4U)) - | ((0xf0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xcU)) - | ((0xf00U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x14U)) - | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x1cU))))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 7U; - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xff000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data) - | ((0xff0000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 8U)) - | ((0xff00U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x10U)) - | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x18U)))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 3U; - } - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period))) { - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (3U | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 2U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & (0xfefe0000U - | ((0x1000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 7U)) - | (0x10000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xfU))))) - | (0xffffU & (0xfefeU | - ((0x100U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x16U)) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x1eU)))))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 0xfU; - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & (0xf0f00000U - | ((0xf000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 4U)) - | (0xf0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xcU))))) - | (0xffffU & (0xf0f0U | - ((0xf00U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x10U)) - | (0xfU & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x18U)))))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 3U; - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffffU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & ((0xff000000U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data) - | (0xff0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 8U)))) - | (0xffffU & ((0xff00U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 8U)) - | (0xffU & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x10U))))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 1U; - } - } else if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xfU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 4U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xfefefefeU | ((0x1000000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 7U)) | ( - (0x10000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xeU)) - | ((0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x15U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x1cU)))))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 7U; - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffffU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xf0f0f0f0U | ((0xf000000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 4U)) | ( - (0xf0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 8U)) - | ((0xf00U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xcU)) - | (0xfU - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x10U)))))); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 1U; - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 0U; - } - } else if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_half) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr))) - & (0U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = (0x1fU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts) - - (IData)(1U))); - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period))) { - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (1U | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 1U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xfefefefeU | ((0x1000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 7U)) - | ((0x10000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xfU)) - | ((0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x17U)) - | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x1fU))))); - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xfU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 4U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xf0f0f0f0U | ((0xf000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 4U)) - | ((0xf0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xcU)) - | ((0xf00U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x14U)) - | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x1cU))))); - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xff000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg) - | ((0xff0000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 8U)) - | ((0xff00U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x10U)) - | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x18U)))); - } - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period))) { - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (3U | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 2U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & (0xfefe0000U - | ((0x1000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 7U)) - | (0x10000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xfU))))) - | (0xffffU & (0xfefeU | - ((0x100U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x16U)) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x1eU)))))); - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & (0xf0f00000U - | ((0xf000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 4U)) - | (0xf0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xcU))))) - | (0xffffU & (0xf0f0U | - ((0xf00U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x10U)) - | (0xfU & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x18U)))))); - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffffU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & ((0xff000000U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg) - | (0xff0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 8U)))) - | (0xffffU & ((0xff00U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 8U)) - | (0xffU & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x10U))))); - } - } else if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xfU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 4U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xfefefefeU | ((0x1000000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 7U)) | ( - (0x10000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xeU)) - | ((0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x15U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x1cU)))))); - } else if ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffffU | (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xf0f0f0f0U | ((0xf000000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 4U)) | ( - (0xf0000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 8U)) - | ((0xf00U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xcU)) - | (0xfU - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x10U)))))); - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - } - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_half))) - ? 1U : 0U); - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period)) - ? ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfefefefeU : ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xf0f0f0f0U - : 0U)) - : ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period)) - ? ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - ? ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfefefefeU : - ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xf0f0f0f0U : 0U)) - : ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfffffefeU : - ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfffff0f0U : 0xffff0000U))) - : ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfffffefeU : ((1U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfffff0f0U - : 0xffff0000U)))); - } - } - if ((2U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - if ((1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data = 0xffffffffU; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 0U; - } - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 1U; - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 3U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - = ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - ? vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - : (0xffffU | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg) - << 0x10U))) - : ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - ? vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - : (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x20U))) - : ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - ? vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - : vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U]) - : vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U]))); - } - } else if ((1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 1U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data; - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 2U; - } - } - } else { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - ? vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - : 0xffffffffU); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 0U; - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last) - ? 2U : 1U); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 1U; - } - } - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40); - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 0U; - } else if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid)) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period))) { - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (1U | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xfefefefeU | ((0x1000000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 7U)) | ( - (0x10000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xfU)) - | ((0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x17U)) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x1fU))))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr)) - & (3U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - ? 0xfU : 0x1fU); - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xfU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 4U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xf0f0f0f0U | ((0xf000000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 4U)) | ( - (0xf0000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xcU)) - | ((0xf00U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x14U)) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x1cU))))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 7U; - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xff000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data) - | ((0xff0000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 8U)) | ( - (0xff00U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x10U)) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x18U)))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 3U; - } - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period))) { - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (3U | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 2U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & (0xfefe0000U - | ((0x1000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 7U)) - | (0x10000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xfU))))) - | (0xffffU & (0xfefeU | ((0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x16U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x1eU)))))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 0xfU; - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & (0xf0f00000U - | ((0xf000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 4U)) - | (0xf0000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xcU))))) - | (0xffffU & (0xf0f0U | ((0xf00U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x10U)) - | (0xfU - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x18U)))))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 3U; - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffffU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & ((0xff000000U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data) - | (0xff0000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 8U)))) - | (0xffffU & ((0xff00U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 8U)) - | (0xffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x10U))))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 1U; - } - } else if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xfU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 4U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xfefefefeU | ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 7U)) - | ((0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xeU)) - | ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x15U)) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x1cU)))))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 7U; - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffffU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xf0f0f0f0U | ((0xf000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 4U)) - | ((0xf0000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 8U)) - | ((0xf00U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0xcU)) - | (0xfU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - >> 0x10U)))))); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 1U; - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = 0U; - } - } else if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr))) - & (0U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = (0x1fU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts) - - (IData)(1U))); - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period))) { - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (1U | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xfefefefeU | ((0x1000000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 7U)) | ( - (0x10000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xfU)) - | ((0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x17U)) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x1fU))))); - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xfU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 4U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xf0f0f0f0U | ((0xf000000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 4U)) | ( - (0xf0000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xcU)) - | ((0xf00U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x14U)) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x1cU))))); - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xff000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg) - | ((0xff0000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 8U)) | ( - (0xff00U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x10U)) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x18U)))); - } - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period))) { - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (3U | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 2U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & (0xfefe0000U - | ((0x1000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 7U)) - | (0x10000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xfU))))) - | (0xffffU & (0xfefeU | ((0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x16U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x1eU)))))); - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & (0xf0f00000U - | ((0xf000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 4U)) - | (0xf0000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xcU))))) - | (0xffffU & (0xf0f0U | ((0xf00U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x10U)) - | (0xfU - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x18U)))))); - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffffU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0xffff0000U & ((0xff000000U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg) - | (0xff0000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 8U)))) - | (0xffffU & ((0xff00U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 8U)) - | (0xffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x10U))))); - } - } else if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xfU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 4U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xfefefefeU | ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 7U)) - | ((0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xeU)) - | ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x15U)) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x1cU)))))); - } else if ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = (0xffffU | (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = (0xf0f0f0f0U | ((0xf000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 4U)) - | ((0xf0000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 8U)) - | ((0xf00U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0xcU)) - | (0xfU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - >> 0x10U)))))); - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - } - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = 0xffffffffU; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half))) - ? 1U : 0U); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - = ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period)) - ? ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfefefefeU : ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xf0f0f0f0U - : 0U)) : - ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period)) - ? ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - ? ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfefefefeU : ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xf0f0f0f0U - : 0U)) - : ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfffffefeU : ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfffff0f0U - : 0xffff0000U))) - : ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfffffefeU : ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? 0xfffff0f0U - : 0xffff0000U)))); - } - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53); 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- } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63), - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem - [vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63], vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63); - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][0U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][1U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][2U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][3U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][4U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][5U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][6U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][7U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][8U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][9U] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][0xaU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][0xbU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][0xcU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][0xdU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][0xeU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0][0xfU] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0[0xfU]; - } - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe - = vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill - = vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill; - vlSelf->main__DOT__wbwide_i2cm_addr = vlSelf->__Vdly__main__DOT__wbwide_i2cm_addr; - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v0) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v0), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v0], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v0); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v1) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v1), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v1], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v1); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v2) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v2), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v2], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v2); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v3) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v3), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v3], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v3); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v4) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v4), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v4], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v4); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v5) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v5), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v5], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v5); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v6) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v6), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v6], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v6); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v7) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v7), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v7], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v7); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v8) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v8), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v8], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v8); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v9) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v9), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v9], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v9); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v10) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v10), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v10], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v10); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v11) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v11), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v11], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v11); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v12) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v12), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v12], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v12); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v13) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v13), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v13], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v13); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v14) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v14), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v14], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v14); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v15) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v15), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v15], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v15); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v16) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v16), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v16], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v16); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v17) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v17), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v17], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v17); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v18) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v18), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v18], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v18); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v19) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v19), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v19], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v19); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v20) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v20), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v20], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v20); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v21) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v21), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v21], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v21); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v22) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v22), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v22], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v22); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v23) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v23), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v23], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v23); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v24) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v24), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v24], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v24); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v25) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v25), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v25], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v25); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v26) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v26), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v26], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v26); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v27) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v27), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v27], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v27); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v28) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v28), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v28], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v28); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v29) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v29), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v29], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v29); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v30) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v30), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v30], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v30); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v31) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v31), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v31], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v31); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v32) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v32), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v32], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v32); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v33) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v33), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v33], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v33); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v34) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v34), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v34], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v34); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v35) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v35), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v35], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v35); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v36) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v36), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v36], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v36); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v37) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v37), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v37], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v37); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v38) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v38), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v38], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v38); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v39) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v39), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v39], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v39); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v40) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v40), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v40], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v40); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v41) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v41), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v41], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v41); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v42) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v42), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v42], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v42); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v43) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v43), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v43], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v43); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v44) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v44), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v44], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v44); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v45) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v45), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v45], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v45); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v46) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v46), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v46], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v46); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v47) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v47), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v47], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v47); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v48) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v48), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v48], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v48); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v49) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v49), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v49], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v49); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v50) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v50), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v50], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v50); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v51) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v51), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v51], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v51); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v52) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v52), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v52], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v52); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v53) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v53), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v53], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v53); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v54) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v54), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v54], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v54); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v55) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v55), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v55], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v55); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v56) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v56), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v56], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v56); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v57) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v57), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v57], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v57); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v58) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v58), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v58], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v58); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v59) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v59), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v59], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v59); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v60) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v60), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v60], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v60); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v61) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v61), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v61], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v61); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v62) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v62), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v62], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v62); - } - if (vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v63) { - VL_ASSIGNSEL_WI(512,8,(IData)(vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v63), - vlSelf->main__DOT__bkrami__DOT__mem - [vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v63], vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v63); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift; - vlSelf->main__DOT__i2cscopei__DOT__dr_primed = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_primed; - vlSelf->main__DOT__emmcscopei__DOT__dr_primed = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_primed; - vlSelf->main__DOT__sdioscopei__DOT__dr_primed = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_primed; - vlSelf->main__DOT__i2ci__DOT__pf_illegal = vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_illegal; - vlSelf->main__DOT__clock_generator__DOT__counter[1U] - = vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v0; - vlSelf->main__DOT__clock_generator__DOT__counter[2U] - = vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v1; - vlSelf->main__DOT__clock_generator__DOT__counter[3U] - = vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v2; - vlSelf->main__DOT__clock_generator__DOT__counter[4U] - = vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v3; - vlSelf->main__DOT__clock_generator__DOT__counter[5U] - = vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v4; - vlSelf->main__DOT__clock_generator__DOT__counter[6U] - = vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v5; - vlSelf->main__DOT__clock_generator__DOT__counter[7U] - = vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v6; - vlSelf->main__DOT__clock_generator__DOT__counter[0U] - = __Vdlyvval__main__DOT__clock_generator__DOT__counter__v7; - if (vlSelf->__Vdlyvset__main__DOT__console__DOT__txfifo__DOT__fifo__v0) { - vlSelf->main__DOT__console__DOT__txfifo__DOT__fifo[vlSelf->__Vdlyvdim0__main__DOT__console__DOT__txfifo__DOT__fifo__v0] - = vlSelf->__Vdlyvval__main__DOT__console__DOT__txfifo__DOT__fifo__v0; - } - if (vlSelf->__Vdlyvset__main__DOT__console__DOT__rxfifo__DOT__fifo__v0) { - vlSelf->main__DOT__console__DOT__rxfifo__DOT__fifo[vlSelf->__Vdlyvdim0__main__DOT__console__DOT__rxfifo__DOT__fifo__v0] - = vlSelf->__Vdlyvval__main__DOT__console__DOT__rxfifo__DOT__fifo__v0; - } - if (vlSelf->__Vdlyvset__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0) { - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0] - = vlSelf->__Vdlyvval__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0; - } - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr - = vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag; - vlSelf->o_gpio = vlSelf->__Vdly__o_gpio; - vlSelf->main__DOT__spioi__DOT__r_led = vlSelf->__Vdly__main__DOT__spioi__DOT__r_led; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_clk - = (1U & (((IData)(3U) + vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr) - >> 0x19U)); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - = (0x1ffffffU & ((IData)(3U) + vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr)); - vlSelf->main__DOT__rcv__DOT__half_baud_time = ( - (~ (IData)(vlSelf->main__DOT__rcv__DOT__ck_uart)) - & (0x30U - <= (IData)(vlSelf->main__DOT__rcv__DOT__chg_counter))); - vlSelf->main__DOT__i2cscopei__DOT__dr_run_timeout - = (1U & ((~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U)) | (0x7ffffffeU <= vlSelf->main__DOT__i2cscopei__DOT__ck_addr))); - vlSelf->main__DOT__sdioscopei__DOT__dr_run_timeout - = (1U & ((~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U)) | (0x7ffffffeU <= vlSelf->main__DOT__sdioscopei__DOT__ck_addr))); - vlSelf->main__DOT__emmcscopei__DOT__dr_run_timeout - = (1U & ((~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U)) | (0x7ffffffeU <= vlSelf->main__DOT__emmcscopei__DOT__ck_addr))); - vlSelf->main__DOT__genbus__DOT__in_stb = ((~ (IData)(vlSelf->i_reset)) - & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb) - >> 2U)); - if (vlSelf->main__DOT__genbus__DOT__ps_full) { - if ((1U & (~ (IData)(vlSelf->main__DOT__txv__DOT__r_busy)))) { - vlSelf->main__DOT__genbus__DOT__ps_full = 0U; - } - } else if (vlSelf->main__DOT__genbus__DOT__wbu_tx_stb) { - vlSelf->main__DOT__genbus__DOT__ps_full = 1U; - vlSelf->main__DOT__genbus__DOT__ps_data = (0x80U - | (0x7fU - & (IData)(vlSelf->main__DOT__genbus__DOT__wbu_tx_data))); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)))) { - vlSelf->main__DOT__genbus__DOT__ps_full = 1U; - vlSelf->main__DOT__genbus__DOT__ps_data = vlSelf->main__DOT__w_console_tx_data; - } - vlSelf->main__DOT__i2cscopei__DOT__record_ce = - (1U & (((~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__lst_adr)) - | (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__imm_adr))) - & (~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - >> 2U)))); - vlSelf->main__DOT__i2cscopei__DOT__r_data = ((1U - & ((~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__lst_adr)) - | (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__imm_adr)))) - ? - (((IData)(vlSelf->main__DOT__i2cscopei__DOT__lst_adr) - << 0x1fU) - | vlSelf->main__DOT__i2cscopei__DOT__lst_val) - : vlSelf->main__DOT__i2cscopei__DOT__qd_data); - vlSelf->main__DOT__emmcscopei__DOT__record_ce = - (1U & (((~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__lst_adr)) - | (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__imm_adr))) - & (~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - >> 2U)))); - vlSelf->main__DOT__emmcscopei__DOT__r_data = ((1U - & ((~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__lst_adr)) - | (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__imm_adr)))) - ? - (((IData)(vlSelf->main__DOT__emmcscopei__DOT__lst_adr) - << 0x1fU) - | vlSelf->main__DOT__emmcscopei__DOT__lst_val) - : vlSelf->main__DOT__emmcscopei__DOT__qd_data); - vlSelf->main__DOT__sdioscopei__DOT__record_ce = - (1U & (((~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__lst_adr)) - | (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__imm_adr))) - & (~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - >> 2U)))); - vlSelf->main__DOT__sdioscopei__DOT__r_data = ((1U - & ((~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__lst_adr)) - | (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__imm_adr)))) - ? - (((IData)(vlSelf->main__DOT__sdioscopei__DOT__lst_adr) - << 0x1fU) - | vlSelf->main__DOT__sdioscopei__DOT__lst_val) - : vlSelf->main__DOT__sdioscopei__DOT__qd_data); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid - = ((~ ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)))) - & (8U <= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb - = (1U & ((~ (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full))) - & ((2U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill)) - ? (0x1fU & (0x18U >> (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr))) - : (0x1fU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill) - & ((0x10U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill) - << 4U)) - >> (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr))))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid - = ((~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)))) - & (8U <= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb - = (1U & ((~ (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full))) - & ((2U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill)) - ? (0x1fU & (0x18U >> (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr))) - : (0x1fU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill) - & ((0x10U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill) - << 4U)) - >> (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff - = (0x1ffffffffULL & ((QData)((IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend - >> 0x1fU))) - - (QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor)))); - if (vlSelf->main__DOT__genbus__DOT__r_wdt_reset) { - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr = 0U; - vlSelf->main__DOT__genbus__DOT__exec_word = - (0xc0000000ULL | (QData)((IData)((0x3fffffffU - & vlSelf->main__DOT__wbu_idata)))); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid = 0U; - } else { - if (vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write) { - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr - = vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__nxt_wrptr; - } - if (vlSelf->main__DOT__wbu_cyc) { - vlSelf->main__DOT__genbus__DOT__exec_word - = (0xe00000000ULL | (((QData)((IData)( - (vlSelf->main__DOT__wbu_idata - >> 0x1eU))) - << 0x1fU) | (QData)((IData)( - (((IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_inc) - << 0x1eU) - | (0x3fffffffU - & vlSelf->main__DOT__wbu_idata)))))); - vlSelf->main__DOT__genbus__DOT__exec_word - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - ? (0x140000000ULL | (0x3fffffffULL - & vlSelf->main__DOT__genbus__DOT__exec_word)) - : ((IData)(vlSelf->main__DOT__wbu_we) - ? (0x80000000ULL | (0x3fffffffULL - & vlSelf->main__DOT__genbus__DOT__exec_word)) - : (0xe00000000ULL | vlSelf->main__DOT__genbus__DOT__exec_word))); - } else { - vlSelf->main__DOT__genbus__DOT__exec_word - = (0x200000000ULL | (QData)((IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr))); - } - if (vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write) { - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr - = vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__nxt_wrptr; - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid = 0U; - } - } - vlSelf->main__DOT__genbus__DOT__in_word = ((0x2eU - == - (0x3fU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - >> 0x1eU)))) - ? vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - : ( - (1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - >> 0x23U))) - ? - (0xc00000000ULL - | (QData)((IData)( - ((0x40000000U - & ((IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - >> 0x1eU)) - << 0x1eU)) - | (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__rd_len))))) - : - ((1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - >> 0x22U))) - ? - ((1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - >> 0x21U))) - ? vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - : - (0x600000000ULL - | (((QData)((IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cword - >> 0x1eU))) - << 0x1fU) - | (QData)((IData)( - ((0x40000000U - & ((IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - >> 0x1eU)) - << 0x1eU)) - | (0x3fffffffU - & vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cword))))))) - : - ((1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - >> 0x21U))) - ? - ((1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - >> 0x1eU))) - ? - (0x200000000ULL - | (((QData)((IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr - >> 0x1eU))) - << 0x1fU) - | (QData)((IData)( - (0x40000000U - | (0x3fffffffU - & vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr)))))) - : (QData)((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr))) - : vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word)))); - vlSelf->main__DOT__genbus__DOT__exec_stb = ((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | ((IData)(vlSelf->main__DOT__wbu_cyc) - ? - ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)) - : - ((((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy))) - & (0xc00000000ULL - == - (0xc00000000ULL - & vlSelf->main__DOT__genbus__DOT__ififo_codword))) - & (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_new_addr)))); - if (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy) { - if (((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__zmatch) - ? ((0x3fffffffULL & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword) - | ((QData)((IData)((6U | (1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word - >> 0x1eU)))))) - << 0x1eU)) : ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__hmatch) - ? ((0x3fffffffULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword) - | ((QData)((IData)( - (0x20U - | (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_hlfd) - << 1U) - | (1U - & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word - >> 0x1eU))))))) - << 0x1eU)) - : ((0xffffffULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword) - | ((QData)((IData)( - (0x400U - | ((0x380U - & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld) - << 1U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word - >> 0x1eU)) - << 6U)) - | (0x3fU - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld))))))) - << 0x18U)))); - } - } else { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__a_addrword; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner = 0U; - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__wbu_cyc))) - | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbu_xbar__DOT__mempty = 1U; - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__mnearfull = 0U; - } else if ((1U == ((((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stall))) - << 1U) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = (0x3fU & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending) - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__mnearfull - = vlSelf->main__DOT__wbu_xbar__DOT__mfull; - vlSelf->main__DOT__wbu_xbar__DOT__mempty = - (1U == (IData)(vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending)); - } else if ((2U == ((((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stall))) - << 1U) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))); - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__mnearfull - = (IData)(((0x3cU == (0x3cU & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))) - & (0U != (3U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))))); - vlSelf->main__DOT__wbu_xbar__DOT__mempty = 0U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size; - } - vlSelf->cpu_prof_ticks = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks; - if (vlSelf->main__DOT__wbwide_wbdown_stall) { - if ((1U & ((~ (IData)(vlSelf->main__DOT__wb32_wbdown_stb)) - | (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift = 1U; - } - } else { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift - = ((0U != vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U]) - ? 1U : (0xfU & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__i_subaddr))); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance; - vlSelf->main__DOT__clock_generator__DOT__times_five - = ((vlSelf->main__DOT__r_sirefclk_data << 2U) - + vlSelf->main__DOT__r_sirefclk_data); - vlSelf->main__DOT__clock_generator__DOT__times_seven - = ((vlSelf->main__DOT__r_sirefclk_data << 3U) - - vlSelf->main__DOT__r_sirefclk_data); - vlSelf->main__DOT__clock_generator__DOT__times_three - = ((vlSelf->main__DOT__r_sirefclk_data << 1U) - + vlSelf->main__DOT__r_sirefclk_data); - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel - = (((QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[3U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[2U]))); - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x10U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[1U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x11U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[2U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x12U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[3U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x13U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[4U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x14U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[5U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x15U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[6U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x16U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[7U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x17U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[8U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x18U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[9U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x19U]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xaU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1aU]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xbU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1bU]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xcU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1cU]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xdU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1dU]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xeU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1eU]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data[0xfU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1fU]; - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_wstb - = (1U & ((~ (IData)(vlSelf->i_reset)) & (((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)) - >> 1U))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) { - if ((IData)(((6U == (6U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stall)) - | vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr = 1U; - } - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr = 0U; - } - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_when - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_when - = (vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_when - - vlSelf->main__DOT__swic__DOT__sys_data); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill = 0U; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill - = ((0x3c0U & (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill)) - | (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill)); - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill = 0U; - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill - = ((0x3c0U & (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill)) - | (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0 - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr))]; - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_illegal = 0U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle = 0U; - } else if (((IData)(vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle = 0U; - } - vlSelf->main__DOT__raw_cpu_dbg_ack = ((~ ((((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc))) - | (IData)(vlSelf->main__DOT__swic__DOT__no_dbg_err)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_cyc)))) - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_ack)); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack - = ((((~ (IData)(vlSelf->i_reset)) & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U)); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted))) { - vlSelf->main__DOT__i2ci__DOT__soft_halt_request = 0U; - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__mid_axis_pkt = 0U; - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__r_channel = 0U; - } else { - if (((((IData)(vlSelf->main__DOT__i2ci__DOT__bus_write) - & (0U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]))) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - >> 0x16U)) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xeU)))) { - vlSelf->main__DOT__i2ci__DOT__soft_halt_request = 1U; - } - if ((((IData)(vlSelf->main__DOT__i2ci__DOT__s_tvalid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__insn_ready)) - & ((((4U == (7U & ((IData)(vlSelf->main__DOT__i2ci__DOT__insn) - >> 8U))) | (5U == (7U - & ((IData)(vlSelf->main__DOT__i2ci__DOT__insn) - >> 8U)))) - | (6U == (7U & ((IData)(vlSelf->main__DOT__i2ci__DOT__insn) - >> 8U)))) | (7U == - (7U & - ((IData)(vlSelf->main__DOT__i2ci__DOT__insn) - >> 8U)))))) { - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__mid_axis_pkt = 1U; - } else if (((IData)(vlSelf->main__DOT__i2c_valid) - & (IData)(vlSelf->main__DOT__i2c_ready))) { - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__mid_axis_pkt - = (1U & (~ (IData)(vlSelf->main__DOT__i2c_last))); - } - if ((((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - & (0xd00U == (0xf00U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)))) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready))) { - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__r_channel - = (3U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)); - } - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger - = (1U & ((~ ((((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort)) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger)) - | ((((IData)(vlSelf->main__DOT__swic__DOT__alt_int_vector) - << 0x10U) | (((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0) - << 6U) | (((IData)(vlSelf->main__DOT__swic__DOT__ctri_int) - << 5U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tma_int) - << 4U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tmb_int) - << 3U) - | (((IData)(vlSelf->main__DOT__swic__DOT__tmc_int) - << 2U) - | ((IData)(vlSelf->main__DOT__swic__DOT__jif_int) - << 1U))))))) - >> (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel))))); - if (vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data - = vlSelf->i_emmc_cmd; - } - vlSelf->o_emmc_cmd = (1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2fU))); - if (vlSelf->main__DOT__i2ci__DOT__cpu_new_pc) { - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift - = (0x3fU & vlSelf->main__DOT__i2ci__DOT__pf_jump_addr); - } else if (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - >> 1U))) { - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift = 0U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - | (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck)))))) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__resp_started) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data - = (0U != ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in))); - } else if ((1U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U))) | - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data = 0U; - } - } - if (vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset) { - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle = 0U; - } else if (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & (IData)(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc))) { - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)))) { - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle = 0U; - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset) - | (IData)(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc))) { - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal = 0U; - } else if (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 1U))) { - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal = 1U; - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data - = vlSelf->i_emmc_dat; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data - = (0xffU & ((2U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck)) - ? ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat) - >> 8U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat))); - if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 6U) & (3U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) & (0U - != - (0xfU - & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U)))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]; - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_data; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = 0U; - if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 6U) & (3U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) & (0U - != - (0xfU - & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U)))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b - = (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U))); - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = 0xfU; - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - } - if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 6U) & (2U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) & (0U - != - (0xfU - & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U)))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]; - } - if (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_data; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = 0U; - if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 6U) & (2U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) & (0U - != - (0xfU - & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U)))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a - = (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U))); - } - if (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = 0xfU; - } - if (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = 0U; - } else { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd - = (0x7fU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]); - } else { - if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err)))) { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_err) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = 2U; - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode; - } - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_id; - } - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_err)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = 1U; - } else if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U))) & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xfU))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = 0U; - } - } - if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 8U) & (3U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) - & (0U != (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]; - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_data; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = 0U; - if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 8U) & (3U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) - & (0U != (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b - = (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U))); - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = 0xfU; - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - } - if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 8U) & (2U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) - & (0U != (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]; - } - if (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_data; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = 0U; - if ((((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 8U) & (2U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) - & (0U != (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a - = (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U))); - } - if (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = 0xfU; - } - if (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = 0U; - vlSelf->main__DOT__u_sdcard__DOT__pp_cmd = 0U; - vlSelf->main__DOT__u_sdcard__DOT__pp_data = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = 0U; - } else { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd - = (0x7fU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]); - } else { - if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err)))) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = 2U; - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode; - } - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id; - } - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U)))) { - vlSelf->main__DOT__u_sdcard__DOT__pp_cmd - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xdU)); - vlSelf->main__DOT__u_sdcard__DOT__pp_data - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xcU)); - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = 1U; - } else if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))) & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xfU))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = 0U; - } - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc))) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = (0xeU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)); - } else if ((1U == ((2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall))) - << 1U)) | (1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = (0x3fU & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending) - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = ((0xeU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)) - | (1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull))); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = ((0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)) - | (1U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))); - } else if ((2U == ((2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall))) - << 1U)) | (1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = ((0xeU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)) - | (IData)(((0x3cU == (0x3cU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))) - & (0U != (3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending)))))); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 1U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 1U)))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = (0xdU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)); - } else if ((1U == ((2U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 1U)) << 1U))) - | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending - = (0x3fU & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending) - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = ((0xdU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)) - | (2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull))); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = ((0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)) - | ((1U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending)) - << 1U)); - } else if ((2U == ((2U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 1U)) << 1U))) - | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending))); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = ((0xdU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)) - | ((IData)(((0x3cU == (0x3cU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending))) - & (0U != (3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending))))) - << 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 2U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 2U)))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = (0xbU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)); - } else if ((1U == ((2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 1U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 2U)) - << 1U))) | - (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending - = (0x3fU & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending) - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = ((0xbU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)) - | (4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull))); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = ((0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)) - | ((1U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending)) - << 2U)); - } else if ((2U == ((2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 1U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 2U)) - << 1U))) | - (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending))); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = ((0xbU & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)) - | ((IData)(((0x3cU == (0x3cU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending))) - & (0U != (3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending))))) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 3U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 3U)))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = (7U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)); - } else if ((1U == (((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 3U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 3U)))) - << 1U) | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending - = (0x3fU & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending) - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = ((7U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)) - | (8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull))); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = ((7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)) - | ((1U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending)) - << 3U)); - } else if ((2U == (((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 3U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 3U)))) - << 1U) | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U))))) { - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending))); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull - = ((7U & (IData)(vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull)) - | ((IData)(((0x3cU == (0x3cU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending))) - & (0U != (3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending))))) - << 3U)); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc))) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__mempty = 1U; - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__mnearfull = 0U; - } else if ((1U == ((((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stall))) - << 1U) | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = (0x3fU & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending) - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__mnearfull - = vlSelf->main__DOT__wb32_xbar__DOT__mfull; - vlSelf->main__DOT__wb32_xbar__DOT__mempty = - (1U == (IData)(vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending)); - } else if ((2U == ((((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stall))) - << 1U) | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))); - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__mnearfull - = (IData)(((0x3cU == (0x3cU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))) - & (0U != (3U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending))))); - vlSelf->main__DOT__wb32_xbar__DOT__mempty = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I - = (((- (IData)((1U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I - >> 0x16U)))) << 0x16U) - | (0x3fffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim_immv; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0xbU] - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[3U] - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0xaU] - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[2U] - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[9U] - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[1U] - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[8U] - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0U] - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result - = ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_sgn)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_smpy_result - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_umpy_result); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim_immv; - if (vlSelf->i_clk) { - vlSelf->o_sdcard_cmd = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out) - >> 1U)); - vlSelf->o_sdcard_clk = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out) - >> 1U)); - } else { - vlSelf->o_sdcard_cmd = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out)); - vlSelf->o_sdcard_clk = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out)); - } - if (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } else if ((((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskd_ready)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } - if (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } else if ((((IData)(vlSelf->main__DOT__wbwide_zip_stb) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskd_ready)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw = 0U; - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw - = (0xffU & ((IData)(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe) - >> 8U)); - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe - = ((0xff00U & ((IData)(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe) - << 8U)) | (IData)(vlSelf->i_sw)); - vlSelf->main__DOT__spioi__DOT__sw_int = ((IData)(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw) - != (0xffU - & ((IData)(vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe) - >> 7U))); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn_int - = ((~ (IData)(vlSelf->i_reset)) & (IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_int)); - if (((IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)))) { - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_we - = vlSelf->main__DOT____Vcellinp__swic__i_dbg_we; - } - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr - = (0x3fffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - << 0xaU) | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - >> 0x16U))); - if ((((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_write)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall))) - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_cpu_write))) { - vlSelf->main__DOT__swic__DOT__cmd_wdata = vlSelf->main__DOT__swic__DOT__dbg_idata; - vlSelf->main__DOT__swic__DOT__cmd_waddr = (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr)); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset)) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - | vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr) - >> 0x1fU))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__cword - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl - [vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr]; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__vaddr - = ((~ ((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))) - & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr) - < (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled) - << 0xaU) | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr)))); - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_stb - = (1U & ((~ (IData)(vlSelf->i_reset)) & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 1U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__pre_sign) - != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - >> 0x1fU)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_hi - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)); - } - vlSelf->main__DOT__swic__DOT__last_sys_stb = ((~ (IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset)) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_stb)); - vlSelf->main__DOT__swic__DOT__r_mmus_ack = ((~ (IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_addr) - >> 7U))); - vlSelf->main__DOT__swic__DOT__dmac_ack = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (IData)(vlSelf->main__DOT__swic__DOT__dmac_stb)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubreak - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] = 0U; - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_interval_count = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_interval_count = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_interval_count = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_running = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen = 0x400U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc = 0U; - } else { - if (vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__wb_write) { - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running - = (0U != (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data)); - } else if (vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_zero) { - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running = 0U; - } - if (vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write) { - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_interval_count - = (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running - = (0U != (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data)); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload)))) { - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running = 0U; - } - if (vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write) { - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_interval_count - = (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running - = (0U != (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data)); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload)))) { - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running = 0U; - } - if (vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write) { - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_interval_count - = (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data); - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_running - = (0U != (0x7fffffffU & vlSelf->main__DOT__swic__DOT__sys_data)); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_zero) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload)))) { - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_running = 0U; - } - if (((((IData)(vlSelf->main__DOT__swic__DOT__dmac_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__sys_addr) - >> 1U)))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen - = (0x7ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc - = (1U & (~ (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x16U))); - } - } - } - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] = 0U; - if ((0U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU])); - } - if ((1U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU])); - } - if ((2U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU])); - } - if ((3U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xfU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xfU])); - } - if ((4U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU])); - } - if ((5U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU])); - } - if ((6U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU])); - } - if ((7U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xeU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xeU])); - } - if ((8U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU])); - } - if ((9U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU])); - } - if ((0xaU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU])); - } - if ((0xbU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xdU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xdU])); - } - if ((0xcU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU])); - } - if ((0xdU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU])); - } - if ((0xeU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU])); - } - if ((0xfU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xcU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xcU])); - } - if ((0x10U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU])); - } - if ((0x11U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU])); - } - if ((0x12U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU])); - } - if ((0x13U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xbU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xbU])); - } - if ((0x14U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU])); - } - if ((0x15U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU])); - } - if ((0x16U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU])); - } - if ((0x17U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0xaU]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0xaU])); - } - if ((0x18U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U])); - } - if ((0x19U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U])); - } - if ((0x1aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U])); - } - if ((0x1bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[9U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[9U])); - } - if ((0x1cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U])); - } - if ((0x1dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U])); - } - if ((0x1eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U])); - } - if ((0x1fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[8U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[8U])); - } - if ((0x20U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U])); - } - if ((0x21U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U])); - } - if ((0x22U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U])); - } - if ((0x23U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[7U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[7U])); - } - if ((0x24U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U])); - } - if ((0x25U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U])); - } - if ((0x26U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U])); - } - if ((0x27U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[6U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[6U])); - } - if ((0x28U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U])); - } - if ((0x29U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U])); - } - if ((0x2aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U])); - } - if ((0x2bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[5U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[5U])); - } - if ((0x2cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U])); - } - if ((0x2dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U])); - } - if ((0x2eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U])); - } - if ((0x2fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[4U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[4U])); - } - if ((0x30U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U])); - } - if ((0x31U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U])); - } - if ((0x32U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U])); - } - if ((0x33U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[3U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[3U])); - } - if ((0x34U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U])); - } - if ((0x35U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U])); - } - if ((0x36U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U])); - } - if ((0x37U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[2U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[2U])); - } - if ((0x38U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U])); - } - if ((0x39U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U])); - } - if ((0x3aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U])); - } - if ((0x3bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[1U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[1U])); - } - if ((0x3cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] - = ((0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]) - | (0xff000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U])); - } - if ((0x3dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] - = ((0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]) - | (0xff0000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U])); - } - if ((0x3eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] - = ((0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]) - | (0xff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U])); - } - if ((0x3fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U] - = ((0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data[0U]) - | (0xffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg[0U])); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubus_err_flag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag; - vlSelf->cpu_prof_stb = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_stb; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[1U] = vlSelf->main__DOT__i2cscopei__DOT__o_bus_data; - vlSelf->main__DOT__i2cscopei__DOT__nxt_mem = vlSelf->main__DOT__i2cscopei__DOT__mem - [vlSelf->main__DOT__i2cscopei__DOT__this_addr]; - if ((4U & (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config))) { - if (vlSelf->main__DOT__i2cscopei__DOT__dw_trigger) { - vlSelf->main__DOT__i2cscopei__DOT__dr_triggered = 1U; - } - } else { - vlSelf->main__DOT__i2cscopei__DOT__dr_triggered = 0U; - } - vlSelf->main__DOT__i2cscopei__DOT__read_address - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U)); - if (vlSelf->main__DOT__i2cscopei__DOT__write_to_control) { - if (((~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[1U] - >> 0x1fU)) & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U))) { - vlSelf->main__DOT__i2cscopei__DOT__br_holdoff - = (0xfffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[1U]); - } - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config - = ((4U & (IData)(vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config)) - | (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[1U] - >> 0x1aU))); - } - if (vlSelf->main__DOT__i2cscopei__DOT__bw_reset_request) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config - = (4U | (IData)(vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config)); - } else if ((4U & (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config))) { - if (((IData)(vlSelf->main__DOT__i2cscopei__DOT__write_to_control) - & (~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[1U] - >> 0x1fU)))) { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config - = (3U & (IData)(vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config)); - } - } else { - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config - = (3U & (IData)(vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config)); - } - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0U] = vlSelf->main__DOT__emmcscopei__DOT__o_bus_data; - vlSelf->main__DOT__emmcscopei__DOT__nxt_mem = vlSelf->main__DOT__emmcscopei__DOT__mem - [vlSelf->main__DOT__emmcscopei__DOT__this_addr]; - if ((4U & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config))) { - if (vlSelf->main__DOT__emmcscopei__DOT__dw_trigger) { - vlSelf->main__DOT__emmcscopei__DOT__dr_triggered = 1U; - } - } else { - vlSelf->main__DOT__emmcscopei__DOT__dr_triggered = 0U; - } - vlSelf->main__DOT__emmcscopei__DOT__read_address - = (1U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]); - if (vlSelf->main__DOT__emmcscopei__DOT__write_to_control) { - if (((~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0U] - >> 0x1fU)) & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U))) { - vlSelf->main__DOT__emmcscopei__DOT__br_holdoff - = (0xfffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0U]); - } - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config - = ((4U & (IData)(vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config)) - | (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0U] - >> 0x1aU))); - } - if (vlSelf->main__DOT__emmcscopei__DOT__bw_reset_request) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config - = (4U | (IData)(vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config)); - } else if ((4U & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config))) { - if (((IData)(vlSelf->main__DOT__emmcscopei__DOT__write_to_control) - & (~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0U] - >> 0x1fU)))) { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config - = (3U & (IData)(vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config)); - } - } else { - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config - = (3U & (IData)(vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config)); - } - vlSelf->main__DOT__wb32_xbar__DOT__s_data[2U] = vlSelf->main__DOT__sdioscopei__DOT__o_bus_data; - vlSelf->main__DOT__sdioscopei__DOT__nxt_mem = vlSelf->main__DOT__sdioscopei__DOT__mem - [vlSelf->main__DOT__sdioscopei__DOT__this_addr]; - if ((4U & (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config))) { - if (vlSelf->main__DOT__sdioscopei__DOT__dw_trigger) { - vlSelf->main__DOT__sdioscopei__DOT__dr_triggered = 1U; - } - } else { - vlSelf->main__DOT__sdioscopei__DOT__dr_triggered = 0U; - } - vlSelf->main__DOT__sdioscopei__DOT__read_address - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U)); - if (vlSelf->main__DOT__sdioscopei__DOT__write_to_control) { - if (((~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[2U] - >> 0x1fU)) & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U))) { - vlSelf->main__DOT__sdioscopei__DOT__br_holdoff - = (0xfffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[2U]); - } - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config - = ((4U & (IData)(vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config)) - | (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[2U] - >> 0x1aU))); - } - if (vlSelf->main__DOT__sdioscopei__DOT__bw_reset_request) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config - = (4U | (IData)(vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config)); - } else if ((4U & (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config))) { - if (((IData)(vlSelf->main__DOT__sdioscopei__DOT__write_to_control) - & (~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[2U] - >> 0x1fU)))) { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config - = (3U & (IData)(vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config)); - } - } else { - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config - = (3U & (IData)(vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config)); - } - vlSelf->main__DOT__clock_generator__DOT__r_delay - = vlSelf->main__DOT__r_sirefclk_data; - vlSelf->o_led = vlSelf->main__DOT__w_led; - vlSelf->main__DOT__spioi__DOT__bounced = ((0xfeU - & (IData)(vlSelf->main__DOT__spioi__DOT__bounced)) - | ((0x1fU - == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - | ((0U - != (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness)) - & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr) - <= (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness))))); - vlSelf->main__DOT__spioi__DOT__bounced = ((0xfdU - & (IData)(vlSelf->main__DOT__spioi__DOT__bounced)) - | (((0x1fU - == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - | ((0U - != (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)) - & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr) - <= (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness)))) - << 1U)); - vlSelf->main__DOT__spioi__DOT__bounced = ((0xfbU - & (IData)(vlSelf->main__DOT__spioi__DOT__bounced)) - | (((0x1fU - == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - | ((0U - != (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)) - & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr) - <= (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness)))) - << 2U)); - vlSelf->main__DOT__spioi__DOT__bounced = ((0xf7U - & (IData)(vlSelf->main__DOT__spioi__DOT__bounced)) - | (((0x1fU - == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - | ((0U - != (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)) - & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr) - <= (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness)))) - << 3U)); - vlSelf->main__DOT__spioi__DOT__bounced = ((0xefU - & (IData)(vlSelf->main__DOT__spioi__DOT__bounced)) - | (((0x1fU - == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - | ((0U - != (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)) - & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr) - <= (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness)))) - << 4U)); - vlSelf->main__DOT__spioi__DOT__bounced = ((0xdfU - & (IData)(vlSelf->main__DOT__spioi__DOT__bounced)) - | (((0x1fU - == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - | ((0U - != (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)) - & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr) - <= (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness)))) - << 5U)); - vlSelf->main__DOT__spioi__DOT__bounced = ((0xbfU - & (IData)(vlSelf->main__DOT__spioi__DOT__bounced)) - | (((0x1fU - == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - | ((0U - != (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)) - & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr) - <= (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness)))) - << 6U)); - vlSelf->main__DOT__spioi__DOT__bounced = ((0x7fU - & (IData)(vlSelf->main__DOT__spioi__DOT__bounced)) - | (((0x1fU - == (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - | ((0U - != (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)) - & ((IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr) - <= (IData)(vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness)))) - << 7U)); - if (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } else if ((((IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskd_ready)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } - if ((1U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall)))) { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel - = ((0xf0U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel)) - | ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wbu_xbar__DOT__m_sel - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]] : 0U)); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe - = ((2U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe)) - | ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]))))); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - = ((0xffffffff00000000ULL & vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata) - | (IData)((IData)((((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> - ((IData)(0x24U) - + - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U])))) - ? ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) ? - vlSelf->main__DOT__wbu_xbar__DOT__m_data - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]] : 0U) - : 0U)))); - } - } else { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel - = (0xf0U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel)); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe - = (2U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe)); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - = (0xffffffff00000000ULL & vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata); - } - if ((2U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall) - >> 1U)))) { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel - = ((0xfU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel)) - | (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wbu_xbar__DOT__m_sel - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]] : 0U) << 4U)); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe - = ((1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U])))) - << 1U)); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - = ((0xffffffffULL & vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata) - | ((QData)((IData)((((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> - ((IData)(0x24U) - + - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U])))) - ? ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) ? - vlSelf->main__DOT__wbu_xbar__DOT__m_data - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]] : 0U) - : 0U))) << 0x20U)); - } - } else { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel - = (0xfU & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel)); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe - = (1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe)); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - = (0xffffffffULL & vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata); - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0U] - = (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[1U] - = (IData)((vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel - >> 0x20U)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[2U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[3U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[4U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[5U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[6U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[7U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[8U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[9U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xaU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xbU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xcU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xdU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xeU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xfU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x10U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x11U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x12U] - = (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we) - << 0x16U) | vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe - = (((((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem)) - & ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_opn)) - == (1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB)) - & ((0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB)) - == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)))); - } - vlSelf->main__DOT__wb32_xbar__DOT__s_data[5U] = vlSelf->main__DOT__wb32_uart_idata; - vlSelf->main__DOT__console__DOT__r_wb_addr = (3U - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 8U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__rvsrc) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_pc) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_last)); - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask = 0U; - } else { - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__svmask) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask - = (((~ ((IData)(1U) << (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__saddr))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask)) - | (0xffU & ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort))) - << (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__saddr)))); - } - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__needload))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask - = ((~ ((IData)(1U) << (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U)))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask)); - } - } - vlSelf->o_i2c_sda = vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda; - vlSelf->cpu_prof_addr = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_addr; - vlSelf->o_i2c_scl = vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_u - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err)))) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) - | ((~ ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack))) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - = ((4U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? 0U : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_val))); - vlSelf->main__DOT__w_console_rx_data = (0x7fU & (IData)(vlSelf->main__DOT__wbu_rx_data)); - vlSelf->main__DOT__u_sdcard__DOT__sdclk = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid - = ((((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb))); - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc = 0x4000000U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xfU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc - = (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl); - } else if ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase))) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc; - } - vlSelf->main__DOT__wb32_xbar__DOT__s_data[9U] = vlSelf->main__DOT__r_wb32_sio_data; - if (((IData)(vlSelf->main__DOT__wb32_sirefclk_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 9U))) { - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x27U)))) { - vlSelf->main__DOT__r_sirefclk_en = (1U - & (~ - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - >> 0x1fU))); - } - } - vlSelf->main__DOT__console__DOT__txf_wb_data = - (0x7fU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[5U]); - vlSelf->io_sdcard_cmd_tristate = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset)) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe)))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy = 1U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy = 0U; - } - if ((1U & (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie))) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped = 0U; - } else if ((((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock))) - & (1U >= (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped = 1U; - } - vlSelf->main__DOT__console__DOT__txf_wb_write = - (((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 5U) & (0x300U == (0x300U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])))) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 5U)) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x14U))); - vlSelf->main__DOT__console__DOT__rxf_wb_data = - ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__osrc) - ? (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__last_write) - : (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_data)); - vlSelf->main__DOT__w_console_rx_stb = ((IData)(vlSelf->main__DOT__wbu_rx_stb) - & (~ ((IData)(vlSelf->main__DOT__wbu_rx_data) - >> 7U))); - vlSelf->main__DOT__console__DOT__rxf_wb_read = - (((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 5U) & (0x200U == (0x300U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])))) - & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 5U))) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x14U))); - vlSelf->main__DOT__wb32_xbar__DOT__s_data[3U] = vlSelf->main__DOT__i2ci__DOT__bus_read_data; - vlSelf->main__DOT__u_emmc__DOT__sdclk = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__w_sdclk; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim; - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0x1fU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc - = (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc; - } - if (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } else if ((((IData)(vlSelf->main__DOT__wbwide_i2cdma_stb) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } - if ((1U & (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent = 0U; - } else if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent = 1U; - } - vlSelf->main__DOT__wb32_xbar__DOT__s_data[7U] = vlSelf->main__DOT__wb32_fan_idata; - vlSelf->main__DOT__u_fan__DOT__i2c_wb_ack = ((~ (IData)(vlSelf->i_reset)) - & (IData)(vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb)); - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 7U))) - | (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x1aU)))) { - vlSelf->main__DOT__u_fan__DOT__pre_data = 0U; - } else { - vlSelf->main__DOT__u_fan__DOT__pre_data = 0U; - if ((0x2000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) { - if ((0x1000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) { - vlSelf->main__DOT__u_fan__DOT__pre_data - = vlSelf->main__DOT__u_fan__DOT__temp_data; - } else { - vlSelf->main__DOT__u_fan__DOT__pre_data - = ((0xf8000000U & vlSelf->main__DOT__u_fan__DOT__pre_data) - | vlSelf->main__DOT__u_fan__DOT__tach_count); - } - } else { - vlSelf->main__DOT__u_fan__DOT__pre_data - = ((0xffffe000U & vlSelf->main__DOT__u_fan__DOT__pre_data) - | ((0x1000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - ? (IData)(vlSelf->main__DOT__u_fan__DOT__ctl_sys) - : (IData)(vlSelf->main__DOT__u_fan__DOT__ctl_fpga))); - } - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb) - & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 7U)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data = 0U; - if ((0x2000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data - = ((0x1000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - ? ((0xfffff000U & vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount)) - : ((0xffffffe0U & vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr))); - } else if ((0x1000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data - = ((0xffff0000U & vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl) - << 0xfU) | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda) - << 0xeU) | (((IData)(vlSelf->i_fan_scl) - << 0xdU) - | (((IData)(vlSelf->i_fan_sda) - << 0xcU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual) - << 0xbU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted) - << 0xaU) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data)))))))); - } else { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data - = (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn) - << 0x1cU) | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual) - << 0x18U) | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait) - << 0x17U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request) - << 0x16U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted) - << 0x15U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl) - << 0xfU) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda) - << 0xeU) - | (((IData)(vlSelf->i_fan_scl) - << 0xdU) - | (((IData)(vlSelf->i_fan_sda) - << 0xcU) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))))))))))))))); - } - } - vlSelf->main__DOT__wb32_xbar__DOT__s_data[4U] = vlSelf->main__DOT__wb32_i2cdma_idata; - if (vlSelf->main__DOT__u_i2cdma__DOT__r_reset) { - vlSelf->main__DOT__u_i2cdma__DOT__current_addr - = vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr; - } else if (((IData)(vlSelf->main__DOT__wbwide_i2cdma_stb) - & (~ (IData)(vlSelf->__VdfgTmp_h503d14d1__0)))) { - vlSelf->main__DOT__u_i2cdma__DOT__current_addr - = (0xfffffffU & ((IData)(1U) + ((vlSelf->main__DOT__wbwide_i2cdma_addr - << 6U) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__subaddr)))); - } - vlSelf->cpu_sim_idata = vlSelf->main__DOT__wbu_zip_idata; - vlSelf->main__DOT__swic__DOT__dbg_odata = ((1U - == (IData)(vlSelf->main__DOT__swic__DOT__dbg_pre_addr)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg - : ( - (0U - == (IData)(vlSelf->main__DOT__swic__DOT__dbg_pre_addr)) - ? vlSelf->main__DOT__swic__DOT__dbg_cpu_status - : vlSelf->main__DOT__swic__DOT__sys_idata)); - vlSelf->main__DOT__wb32_xbar__DOT__s_data[6U] = vlSelf->main__DOT__wb32_emmc_idata; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel = 0U; - if ((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U) & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U))))) { - if ((2U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel = 1U; - } else if ((3U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel = 2U; - } - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data = 0U; - if ((0U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word; - } else if ((1U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg; - } else if ((4U == (7U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x10U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl; - } - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U)) | ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__s_data[8U] = vlSelf->main__DOT__wb32_sdcard_idata; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel = 0U; - if ((1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U) & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U))))) { - if ((2U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel = 1U; - } else if ((3U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel = 2U; - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data = 0U; - if ((0U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word; - } else if ((1U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg; - } else if ((4U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl; - } - if ((1U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U)) | ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data = 0U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period = 0U; - vlSelf->o_emmc_dat = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_half - = (1U & ((IData)(vlSelf->i_reset) | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown)) - | (0U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd))) - | ((1U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - | ((2U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - ? - ((0x200U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - ? 1U - : 2U) - : - (0x100U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter))))))); - vlSelf->io_sdcard_dat_tristate = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z) - << 3U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z) - << 2U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z) - << 1U) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z)))); - vlSelf->main__DOT__rcv__DOT__chg_counter = vlSelf->__Vdly__main__DOT__rcv__DOT__chg_counter; - vlSelf->main__DOT__w_console_tx_data = ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__osrc) - ? (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__last_write) - : (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_data)); - vlSelf->main__DOT__txv__DOT__r_busy = vlSelf->__Vdly__main__DOT__txv__DOT__r_busy; - vlSelf->main__DOT__genbus__DOT__wbu_tx_stb = vlSelf->__Vdly__main__DOT__genbus__DOT__wbu_tx_stb; - vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow - = vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_underflow; - vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe - = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stop_pipe; - vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe - = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stop_pipe; - vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe - = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stop_pipe; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr - = (((- (IData)((1U & (vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr - >> 0x18U)))) << 0x19U) - | vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr - = vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wide_addr; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner; - vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_zero - = vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_zero; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero - = vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero - = vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_zero - = vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero; -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__1__Slow.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__1__Slow.cpp deleted file mode 100644 index 96f0998..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__1__Slow.cpp +++ /dev/null @@ -1,9554 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -extern const VlWide<18>/*575:0*/ Vmain__ConstPool__CONST_hb679b2e5_0; -extern const VlWide<15>/*479:0*/ Vmain__ConstPool__CONST_hbd99daea_0; -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0; - -VL_ATTR_COLD void Vmain___024root___stl_sequent__TOP__1(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___stl_sequent__TOP__1\n"); ); - // Init - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wb32_xbar__DOT____VdfgTmp_h4f7f05b5__0; - main__DOT__wb32_xbar__DOT____VdfgTmp_h4f7f05b5__0 = 0; - CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0; - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 = 0; - CData/*0:0*/ main__DOT__wbu_xbar__DOT____VdfgTmp_h4f7f05b5__0; - main__DOT__wbu_xbar__DOT____VdfgTmp_h4f7f05b5__0 = 0; - CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0; - main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0 = 0; - CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0; - main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0 = 0; - CData/*0:0*/ main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0; - main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0 = 0; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0; - main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0 = 0; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0; - main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0 = 0; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_h832f938f__0; - main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_h832f938f__0 = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior = 0; - CData/*1:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit = 0; - VlWide<16>/*511:0*/ __Vtemp_he3c3974d__0; - VlWide<16>/*511:0*/ __Vtemp_h0ca773d0__0; - VlWide<16>/*511:0*/ __Vtemp_hb780e8f4__0; - VlWide<16>/*511:0*/ __Vtemp_hdb251f8c__0; - VlWide<16>/*511:0*/ __Vtemp_h12b8adbe__0; - VlWide<16>/*511:0*/ __Vtemp_hbc743227__0; - VlWide<16>/*511:0*/ __Vtemp_h6409050d__0; - VlWide<16>/*511:0*/ __Vtemp_h8c81192e__0; - VlWide<16>/*511:0*/ __Vtemp_h5dad54bf__0; - VlWide<16>/*511:0*/ __Vtemp_h01ff8f7b__0; - VlWide<16>/*511:0*/ __Vtemp_hf1acda43__0; - VlWide<32>/*1023:0*/ __Vtemp_h7be7356a__0; - VlWide<32>/*1023:0*/ __Vtemp_h448dc795__0; - VlWide<32>/*1023:0*/ __Vtemp_h9b90904f__0; - // Body - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & (IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffff0000ffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout)) - << 0x10U)); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | ((0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) - | ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x20U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & (IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffff0000ffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout)) - << 0x20U)); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | ((0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) - | ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x30U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & (IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout)) - << 0x30U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffffff8ULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | (IData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x20U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x10U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w))))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffffff7ULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x30U))))) - << 3U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffffff8fULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x21U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x11U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 1U))))))) - << 4U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffffff7fULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x31U))))) - << 7U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffff8ffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x22U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x12U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 2U))))))) - << 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffff7ffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x32U))))) - << 0xbU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffff8fffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x23U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x13U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 3U))))))) - << 0xcU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffff7fffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x33U))))) - << 0xfU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffff8ffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x24U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x14U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 4U))))))) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffff7ffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x34U))))) - << 0x13U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffff8fffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x25U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x15U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 5U))))))) - << 0x14U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffff7fffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x35U))))) - << 0x17U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffff8ffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x26U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x16U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 6U))))))) - << 0x18U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffff7ffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x36U))))) - << 0x1bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffff8fffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x27U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x17U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 7U))))))) - << 0x1cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffff7fffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x37U))))) - << 0x1fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffff8ffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x28U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x18U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 8U))))))) - << 0x20U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffff7ffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x38U))))) - << 0x23U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffff8fffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x29U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x19U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 9U))))))) - << 0x24U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffff7fffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x39U))))) - << 0x27U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffff8ffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2aU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1aU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xaU))))))) - << 0x28U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffff7ffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3aU))))) - << 0x2bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffff8fffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2bU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1bU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xbU))))))) - << 0x2cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffff7fffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3bU))))) - << 0x2fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfff8ffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2cU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1cU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xcU))))))) - << 0x30U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfff7ffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3cU))))) - << 0x33U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xff8fffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2dU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1dU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xdU))))))) - << 0x34U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xff7fffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3dU))))) - << 0x37U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xf8ffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2eU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1eU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xeU))))))) - << 0x38U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xf7ffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3eU))))) - << 0x3bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0x8fffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2fU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1fU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xfU))))))) - << 0x3cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0x7fffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3fU))))) - << 0x3fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x10U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x12U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x14U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x10U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x10U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x8000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x14U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x12U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x10U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U])); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) | (1U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data)))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x19U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1aU)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1bU)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1cU)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 2U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xfU)) | - (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U])))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xbU)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 4U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffff3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 9U)) | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 6U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 9U)) | ( - (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 8U)) - | (0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 4U)) | - ((0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xbU)) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffff3fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 2U)) | - (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xdU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x10U)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 1U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xeU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 3U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x12U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 1U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xff3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 5U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x14U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x17U)) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 6U)) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xaU)) - | ((0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x19U)) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0x3fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xcU)) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x1bU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 2U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x13U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 4U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xfU)) | - ((0x10U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffff3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xdU)) | - (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 5U)) | ( - (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xcU)) - | (0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 3U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 8U)) | - ((0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 7U)) | - (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xaU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffff3fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 6U)) | - (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 9U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xcU)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 5U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xaU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 1U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xeU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 3U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xff3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 1U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x10U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x13U)) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 2U)) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 6U)) - | ((0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x15U)) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0x3fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 8U)) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x17U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 6U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x17U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 8U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x13U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 4U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffff3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0x11U)) | - (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 1U)) | ( - (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x10U)) - | (0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 1U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xcU)) - | ((0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 3U)) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xeU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffff3fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xaU)) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 5U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 8U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 9U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 5U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xaU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xff3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 3U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xcU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xfU)) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 2U)) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 2U)) - | ((0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x11U)) - | (0x8000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0x3fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 4U)) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x13U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xaU)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x1bU)) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xcU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x17U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 8U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x19U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffff3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0x15U)) | - (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 6U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 3U)) | ( - (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x14U)) - | (0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 5U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x10U)) - | ((0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 1U)) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x12U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffff3fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xeU)) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 1U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 4U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xdU)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 9U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 6U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xbU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xff3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 7U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 8U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xbU)) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 6U)) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 9U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 2U)) - | ((0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xdU)) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0x3fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xc0000000U & ((0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xfU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x1dU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (4U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x200000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x800000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x100U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x2000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x400U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x8000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x1000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x1dU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x4000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U])); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x19U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1aU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1bU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1cU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1dU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1eU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 2U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xfU)) | - (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U])))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xbU)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 4U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 8U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 9U)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 5U)) | ( - (0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xaU)) - | (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xeU)) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 3U)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xcU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0x11U)) - | ((0x20000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 4U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0x13U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x17U)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 6U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xaU)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x19U)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x1dU)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xcU)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x1bU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | ((4U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x11U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xdU)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 2U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 6U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xbU)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 7U)) | ( - (0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 8U)) - | (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 9U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xcU)) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 5U)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xaU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xfU)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 2U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 2U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0x11U)) - | (0x80000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x15U)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 4U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x13U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 8U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x17U)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x1bU)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xaU)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x19U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 2U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x13U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 4U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xfU)) | - ((0x10U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 4U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xdU)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 9U)) | ( - (0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 6U)) - | (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xbU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xaU)) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 7U)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xdU)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 4U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xbU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfff80000U & ((0x200000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xfU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x13U)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 2U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 6U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x15U)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x19U)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 8U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x17U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 4U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x15U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 6U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x11U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 2U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x13U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 2U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xfU)) - | (0x40U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xbU)) | - ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 4U)) | - (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 8U)) | - ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 9U)) | - (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xbU)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 6U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 9U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 2U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xdU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x11U)) - | ((0x800000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 4U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x13U)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x17U)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 6U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 6U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x17U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 8U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x13U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 4U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffffffc0U & ((0x100U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x11U)) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xdU)) | - ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 2U)) | - (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 6U)) | - ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xbU)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 9U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 8U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 4U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xbU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xfU)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 2U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 2U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x11U)) - | (0x2000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x15U)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 4U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x13U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 8U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x19U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xaU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x15U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 6U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x17U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 2U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x13U)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xfU)) | - ((0x400U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 4U)) | - ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xdU)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 7U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xaU)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 5U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 6U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 9U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xdU)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 4U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xbU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfe000000U & ((0x8000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xfU)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x13U)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 2U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xaU)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x1bU)) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xcU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x17U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 8U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x19U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 4U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x15U)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0x11U)) - | ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 2U)) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x13U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 2U)) | - ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xfU)) - | (0x1000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 5U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xcU)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 3U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 8U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 7U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xaU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xbU)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 6U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 9U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 2U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xdU)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x11U)) - | ((0x20000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xcU)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x1dU)) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xeU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x19U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xaU)) | - (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x1bU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 6U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x17U)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0x13U)) - | ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 4U)) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffff000U & ((0x4000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0x11U)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 3U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xeU)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 1U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xaU)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 5U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xcU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 9U)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 8U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 4U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xbU)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xfU)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 2U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U])); - if (vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U]; - } else { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[1U] - = Vmain__ConstPool__CONST_hb679b2e5_0[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[2U] - = Vmain__ConstPool__CONST_hb679b2e5_0[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[3U] - = Vmain__ConstPool__CONST_hb679b2e5_0[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[4U] - = Vmain__ConstPool__CONST_hb679b2e5_0[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[5U] - = Vmain__ConstPool__CONST_hb679b2e5_0[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[6U] - = Vmain__ConstPool__CONST_hb679b2e5_0[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[7U] - = Vmain__ConstPool__CONST_hb679b2e5_0[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[8U] - = Vmain__ConstPool__CONST_hb679b2e5_0[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[9U] - = Vmain__ConstPool__CONST_hb679b2e5_0[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xaU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xbU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xcU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xdU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xeU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xfU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x10U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x11U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_i2cm_addr; - } - vlSelf->main__DOT__wb32_xbar__DOT__s_stall = (0xf000U - | (0xfffff800U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & ((IData)(vlSelf->main__DOT__wb32_ddr3_phy_stall) - << 0xbU)))); - vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0 - = (((IData)(vlSelf->main__DOT__i2ci__DOT__r_wait) - << 0x17U) | (((IData)(vlSelf->main__DOT__i2ci__DOT__soft_halt_request) - << 0x16U) | (((IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted) - << 0x15U) | - (((IData)(vlSelf->main__DOT__i2ci__DOT__r_err) - << 0x14U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - << 0x13U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - << 0x12U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle) - << 0x10U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl) - << 0xfU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda) - << 0xeU) - | (((IData)(vlSelf->i_i2c_scl) - << 0xdU) - | (((IData)(vlSelf->i_i2c_sda) - << 0xcU) - | (IData)(vlSelf->main__DOT__i2ci__DOT__insn))))))))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb - = (1U & (((0xffU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter)) - - (IData)(1U)) >> 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter) - - (IData)(1U)))); - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0 - = (1U & (((IData)(1U) + (3U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 8U))) - >> 2U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0 - = (3U & ((IData)(1U) + ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0xffU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0) - << 8U)); - if ((1U >= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = (0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - } else if ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter) - >> 9U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = (0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd) - - (IData)(3U)))); - } - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((1U >= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)) - ? 0x300U : ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)) - ? 0x100U : ((0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed) - - (IData)(3U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed; - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__clk90; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb - = (1U & (((0xffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter)) - - (IData)(1U)) >> 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter) - - (IData)(1U)))); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0 - = (1U & (((IData)(1U) + (3U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 8U))) - >> 2U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0 - = (3U & ((IData)(1U) + ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0xffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0) - << 8U)); - if ((1U >= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = (0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - } else if ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter) - >> 9U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = (0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd) - - (IData)(3U)))); - } - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((1U >= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)) - ? 0x300U : ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)) - ? 0x100U : ((0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed) - - (IData)(3U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed; - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__clk90; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd; - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__swic__DOT__dbg_cmd_write = ((IData)(vlSelf->main__DOT__swic__DOT__dbg_stb) - & ((IData)(vlSelf->main__DOT__swic__DOT__dbg_we) - & (0U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_dbg_stall))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0U] - = (IData)(vlSelf->main__DOT__wbwide_i2cdma_sel); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[1U] - = (IData)((vlSelf->main__DOT__wbwide_i2cdma_sel - >> 0x20U)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[2U] - = vlSelf->main__DOT__wbwide_i2cdma_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[3U] - = vlSelf->main__DOT__wbwide_i2cdma_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[4U] - = vlSelf->main__DOT__wbwide_i2cdma_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[5U] - = vlSelf->main__DOT__wbwide_i2cdma_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[6U] - = vlSelf->main__DOT__wbwide_i2cdma_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[7U] - = vlSelf->main__DOT__wbwide_i2cdma_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[8U] - = vlSelf->main__DOT__wbwide_i2cdma_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[9U] - = vlSelf->main__DOT__wbwide_i2cdma_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xaU] - = vlSelf->main__DOT__wbwide_i2cdma_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xbU] - = vlSelf->main__DOT__wbwide_i2cdma_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xcU] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xdU] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xeU] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xfU] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x10U] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x11U] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x12U] - = (0x400000U | vlSelf->main__DOT__wbwide_i2cdma_addr); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0U] - = (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[1U] - = (IData)((vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel - >> 0x20U)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[2U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[3U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[4U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[5U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[6U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[7U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[8U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[9U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xaU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xbU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xcU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xdU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xeU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xfU] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x10U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x11U] - = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x12U] - = (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we) - << 0x16U) | vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data - = (((QData)((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_we)) - << 0x2cU) | (((QData)((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr)) - << 0x24U) | (((QData)((IData)( - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xfU])) - << 4U) | (QData)((IData)( - (0xfU - & (IData)( - (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel - >> 0x3cU)))))))); - vlSelf->main__DOT__wbu_wbu_arbiter_stall = ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb) - & ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__swic__DOT__ext_err = (1U & ( - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 2U) - | (IData)(vlSelf->main__DOT__swic__DOT__wdbus_int))); - vlSelf->main__DOT__wbwide_wbu_arbiter_stb = ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full)) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[8U] - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0U] - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[9U] - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[1U] - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0xaU] - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[2U] - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[0xbU] - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[3U] - = (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U) & (IData)(((0U == (0x70000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U) & ((0U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge - = ((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck)) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 7U)) << 1U) | (IData)((8U == (0x88U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk))))); - vlSelf->o_emmc_cmd = (1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2fU))); - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) { - vlSelf->main__DOT__swic__DOT__dc_stb = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb; - vlSelf->main__DOT__swic__DOT__dc_cyc = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc; - } else { - vlSelf->main__DOT__swic__DOT__dc_stb = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb; - vlSelf->main__DOT__swic__DOT__dc_cyc = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc; - } - vlSelf->main__DOT__wbwide_xbar__DOT__sindex[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex; - vlSelf->main__DOT__wbwide_xbar__DOT__sindex[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex; - vlSelf->main__DOT__wbwide_xbar__DOT__sindex[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex; - vlSelf->o_emmc_clk = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__sdclk) - >> 7U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__rvsrc) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_pc) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_last)); - vlSelf->main__DOT__i2ci__DOT__bus_write = (1U & - (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 3U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt - = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt_q) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en - = (1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0x18U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n - = (1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0x17U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xfeU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (1U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xfdU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (2U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xfbU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (4U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xf7U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (8U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xefU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (0x10U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xdfU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (0x20U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xbfU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (0x40U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0x7fU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (0x80U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = ((0x800000U & ((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero)) - << 0x17U)) | ((0x700000U & - (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - << 1U)) | - (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) - | ((0x40000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 6U)) - | ((0x20000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 6U)) - | ((0x1c000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 2U)) - | (0x3fffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction))))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = ((0xfffbffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U]) | (0x400U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0xfU))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] - = (0x500000U | (((2U != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate)) - << 0x17U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | - (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] - = (0xc00000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0xb00000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[0U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [0U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [0U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[0U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [0U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [0U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[0U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [0U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [0U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[0U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [0U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [0U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[1U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [1U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [1U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[1U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [1U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [1U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[1U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [1U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [1U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[1U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [1U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [1U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[2U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [2U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [2U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[2U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [2U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [2U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[2U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [2U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [2U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[2U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [2U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [2U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[3U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [3U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [3U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[3U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [3U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [3U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[3U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [3U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [3U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[3U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [3U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [3U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[4U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [4U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [4U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[4U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [4U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [4U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[4U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [4U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [4U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[4U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [4U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [4U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[5U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [5U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [5U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[5U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [5U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [5U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[5U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [5U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [5U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[5U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [5U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [5U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[6U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [6U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [6U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[6U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [6U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [6U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[6U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [6U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [6U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[6U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [6U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [6U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[7U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [7U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [7U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[7U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [7U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [7U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[7U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [7U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [7U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[7U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [7U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [7U] - (IData)(1U)))); - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 1U; - if ((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row)))) { - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt = 1U; - if ((4U >= vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank])) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 4U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[0U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] - = (0x480000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank) - << 0xeU) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[1U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0x80000U | vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [0U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[2U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = (0x80000U | vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[3U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] - = (0x80000U | vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [2U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[4U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] - = (0x80000U | vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [3U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[5U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[6U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[7U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 3U; - } else if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we)) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt = 0U; - if ((1U >= vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank])) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 1U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] - = (0x500000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank) - << 0xeU) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0xf7ffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [0U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = (0xf7ffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] - = (0xf7ffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [2U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] - = (0xf7ffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [3U]); - } - } else if (((~ ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank))) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 3U; - if ((0U >= vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank])) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 0U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0x300000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank) - << 0xeU) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row)))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - | (0xffU & ((IData)(1U) << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row; - } else if (((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row))) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = (0x200000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank) - << 0xeU) - | (0x3ffU - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row))))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((~ ((IData)(1U) << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank))) - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - } - } - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending) - & (~ (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank) - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending))))) { - if ((((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] - != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row))) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank])) - & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy)))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = (0x200000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank) - << 0xeU) - | (0x3ffU - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row))))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((~ ((IData)(1U) << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank))) - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - } else if ((((~ ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank))) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank])) - & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy)))) { - if ((0U >= vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank])) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] = 0U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0x300000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank) - << 0xeU) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row)))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - | (0xffU & ((IData)(1U) << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row; - } - } - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending) { - if ((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row)))) { - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - } else if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we)) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - } - } - } - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank))) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank] - != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row)))))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 1U; - } else if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we)) - & (0U != vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 1U; - } else if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we) - & (0U != vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 1U; - } - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_d - = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall) - : (((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 2U) & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall) - : (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall)))); - if ((1U & (~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 2U)))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_d = 0U; - } - vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb - = (1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 7U) & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x1aU))); - main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0 - = ((0U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state)) - | (2U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error)))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce = 0U; - } - main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0 - = ((0U == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state)) - | (2U == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__pre_sign) - != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - >> 0x1fU)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - = ((0U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index))) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_val - : ((1U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index))) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result)); - vlSelf->main__DOT__swic__DOT__cpu_we = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - = ((4U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? 0U : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_val))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_wF)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy))); - main__DOT__wbu_xbar__DOT____VdfgTmp_h4f7f05b5__0 - = ((IData)(vlSelf->main__DOT__wbu_cyc) & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb)); - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc) { - __Vtemp_he3c3974d__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0U]; - __Vtemp_he3c3974d__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[1U]; - __Vtemp_he3c3974d__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[2U]; - __Vtemp_he3c3974d__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[3U]; - __Vtemp_he3c3974d__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[4U]; - __Vtemp_he3c3974d__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[5U]; - __Vtemp_he3c3974d__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[6U]; - __Vtemp_he3c3974d__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[7U]; - __Vtemp_he3c3974d__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[8U]; - __Vtemp_he3c3974d__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[9U]; - __Vtemp_he3c3974d__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xaU]; - __Vtemp_he3c3974d__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xbU]; - __Vtemp_he3c3974d__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xcU]; - __Vtemp_he3c3974d__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xdU]; - __Vtemp_he3c3974d__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xeU]; - __Vtemp_he3c3974d__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xfU]; - } else { - __Vtemp_he3c3974d__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0U]; - __Vtemp_he3c3974d__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[1U]; - __Vtemp_he3c3974d__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[2U]; - __Vtemp_he3c3974d__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[3U]; - __Vtemp_he3c3974d__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[4U]; - __Vtemp_he3c3974d__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[5U]; - __Vtemp_he3c3974d__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[6U]; - __Vtemp_he3c3974d__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[7U]; - __Vtemp_he3c3974d__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[8U]; - __Vtemp_he3c3974d__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[9U]; - __Vtemp_he3c3974d__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xaU]; - __Vtemp_he3c3974d__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xbU]; - __Vtemp_he3c3974d__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xcU]; - __Vtemp_he3c3974d__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xdU]; - __Vtemp_he3c3974d__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xeU]; - __Vtemp_he3c3974d__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xfU]; - } - VL_SHIFTL_WWI(512,512,32, __Vtemp_h0ca773d0__0, __Vtemp_he3c3974d__0, - (0x1e0U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc - << 3U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0U] - = __Vtemp_h0ca773d0__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[1U] - = __Vtemp_h0ca773d0__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[2U] - = __Vtemp_h0ca773d0__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[3U] - = __Vtemp_h0ca773d0__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[4U] - = __Vtemp_h0ca773d0__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[5U] - = __Vtemp_h0ca773d0__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[6U] - = __Vtemp_h0ca773d0__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[7U] - = __Vtemp_h0ca773d0__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[8U] - = __Vtemp_h0ca773d0__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[9U] - = __Vtemp_h0ca773d0__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xaU] - = __Vtemp_h0ca773d0__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xbU] - = __Vtemp_h0ca773d0__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xcU] - = __Vtemp_h0ca773d0__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xdU] - = __Vtemp_h0ca773d0__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xeU] - = __Vtemp_h0ca773d0__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU] - = __Vtemp_h0ca773d0__0[0xfU]; - vlSelf->__VdfgTmp_h503d14d1__0 = (7U & (~ ((4U - & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - << 2U)) - | ((2U - & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - << 1U)) - | (1U - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step)); - main__DOT__wb32_xbar__DOT____VdfgTmp_h4f7f05b5__0 - = ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt)); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full - = ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_full)); - vlSelf->main__DOT__wbwide_xbar__DOT__request[0U] - = (((IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)) - ? (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded) - : 0U); - vlSelf->main__DOT__wbwide_xbar__DOT__request[1U] - = (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid)) - ? (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__decoded) - : 0U); - vlSelf->main__DOT__wbwide_xbar__DOT__request[3U] - = (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid)) - ? (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__decoded) - : 0U); - vlSelf->main__DOT__swic__DOT__cpu_break = ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid)); - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wreg) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) { - vlSelf->main__DOT__swic__DOT__cpu_addr = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr; - vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl; - } else { - vlSelf->main__DOT__swic__DOT__cpu_addr = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr; - vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc; - } - vlSelf->main__DOT__console__DOT__rxf_status = (0x6000U - | (((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill) - << 2U) - | ((2U - & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - >> 4U)) - | (1U - & (~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache)); - vlSelf->main__DOT__console__DOT__txf_status = (0x6000U - | (((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill) - << 2U) - | (IData)(vlSelf->__VdfgTmp_ha46ae6a3__0))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z) - ? (IData)(vlSelf->i_sdcard_cmd) : (IData)(vlSelf->o_sdcard_cmd)); - vlSelf->main__DOT__emmcscopei__DOT__dw_trigger - = ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_primed) - & (((~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config)) - & (IData)(vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3)) - | ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 1U))); - vlSelf->main__DOT__sdioscopei__DOT__dw_trigger - = ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_primed) - & (((~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config)) - & (IData)(vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3)) - | ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 1U))); - vlSelf->main__DOT__swic__DOT__cpu_i_count = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_v_from_last - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup - == (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))) & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask) - >> (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) - & ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate)) - | (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) - & ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate)) - | (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate)))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn - = vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn; - if ((((IData)(vlSelf->main__DOT__wb32_spio_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 9U)) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x26U)))) { - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn - = ((IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn) - & (~ ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - << 0x10U) | (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - >> 0x10U)))); - } - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn - = ((IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn) - | (IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__s_btn)); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_int - = (0U != (IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn)); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write - = ((IData)(vlSelf->main__DOT__genbus__DOT__exec_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow)) - | (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd))); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read - = (1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow)) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)) - | (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd)))); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write - = ((IData)(vlSelf->main__DOT__genbus__DOT__in_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow)) - | (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd))); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read - = (1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow)) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)) - | (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 3U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 2U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 1U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z) - ? (IData)(vlSelf->i_sdcard_dat) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->o_sdcard_dat = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin) - << 3U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin) - << 2U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin) - << 1U) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin)))); - vlSelf->main__DOT__swic__DOT__main_int_vector = - (((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0) - << 6U) | (((IData)(vlSelf->main__DOT__swic__DOT__ctri_int) - << 5U) | (((IData)(vlSelf->main__DOT__swic__DOT__tma_int) - << 4U) | (((IData)(vlSelf->main__DOT__swic__DOT__tmb_int) - << 3U) | - (((IData)(vlSelf->main__DOT__swic__DOT__tmc_int) - << 2U) - | (((IData)(vlSelf->main__DOT__swic__DOT__jif_int) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__dmac_int))))))); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb - = ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len)) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len))) - | ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy)) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid)) - & (1U == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw)))))); - vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem - [(0x1fU & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr))]; - if (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty) { - vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data - = vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__req_data - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__gie) - << 0xcU) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_haf314c36__0) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_haf314c36__0)); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbu_stb) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - ? vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data - : vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__dc_ack)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack - = ((IData)(vlSelf->main__DOT__swic__DOT__dc_ack) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill; - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last) - ? 0U : ((0x3fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill)) - | (0xc0U & ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill) - >> 6U) - (IData)(1U)) - << 6U)))); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill - = (0xffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill) - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last = 0U; - if ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last - = ((0U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill) - >> 6U))) | (IData)((0x40U - == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill)))); - } - vlSelf->main__DOT__swic__DOT__alt_int_vector = - (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0xeU) | ((0x2000U & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0xdU)) | ((0x1000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0xcU)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0xbU) - | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 0xaU) - | (((IData)(vlSelf->main__DOT__emmcscope_int) - << 9U) - | (((IData)(vlSelf->main__DOT__swic__DOT__mtc_int) - << 7U) - | (((IData)(vlSelf->main__DOT__swic__DOT__moc_int) - << 6U) - | (((IData)(vlSelf->main__DOT__swic__DOT__mpc_int) - << 5U) - | (((IData)(vlSelf->main__DOT__swic__DOT__mic_int) - << 4U) - | (((IData)(vlSelf->main__DOT__swic__DOT__utc_int) - << 3U) - | (((IData)(vlSelf->main__DOT__swic__DOT__uoc_int) - << 2U) - | (((IData)(vlSelf->main__DOT__swic__DOT__upc_int) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__uic_int)))))))))))))); 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- vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__dbg_cmd_write) - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_sel)); - if (vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U]; - } else { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x12U]; - } - if (vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U]; 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- vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x12U]; - } - vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - ? vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data - : vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data); - vlSelf->main__DOT__wbu_xbar__DOT__s_stall = (0xcU - | ((0xfffffffeU - & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - & (((IData)(vlSelf->cpu_sim_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - & (IData)(vlSelf->main__DOT__wbu_wbu_arbiter_stall)))); - vlSelf->main__DOT__swic__DOT__dc_err = ((~ (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__ext_err)); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr - = ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full)) - & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - & (IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb))); 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- vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0xf1ffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xbU] << 0xbU) | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xaU] << 0xaU) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [9U] << 9U)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0x8fffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xeU] << 0xeU) | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xdU] << 0xdU) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xcU] << 0xcU)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0x7fffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xfU] << 0xfU)); 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- } - if ((((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xbU))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request - = ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (0x3000000ULL == (0x3000000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x40U == (0xc0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))) - | (0U == (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 6U))))) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xbU) - | ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x240U - == - (0x3c0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))))); - if (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request - = ((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U))) & ((1U == (3U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 6U))) - | (IData)(((0U - == - (0x2bc0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))))); - if ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & ((IData)(((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U) & (0x200U == (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])))) - | ((~ (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))) & (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - if ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xbU))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request - = ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (0x300000000ULL == (0x300000000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x40U == (0xc0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]))) - | (0U == (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 6U))))) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xbU) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x240U - == - (0x3c0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]))))); - if (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - ? 0U : (3U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pck_sreg) - << 2U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge)) - >> (7U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift) - >> 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - ? ((((~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 7U)) & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck)) - << 1U) | (IData)((0x80U == (0x88U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk))))) - : 0U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0 - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((~ (IData)(vlSelf->o_emmc_cmd)) | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_cmd))); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge - = ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck)) - & (IData)(vlSelf->o_emmc_clk)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal)); - vlSelf->main__DOT__i2ci__DOT__bus_manual = ((IData)(vlSelf->main__DOT__i2ci__DOT__bus_write) - & (IData)( - (((0x1000000U - == - (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - >> 0xbU)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xdU)))); - vlSelf->main__DOT__i2ci__DOT__bus_jump = ((IData)(vlSelf->main__DOT__i2ci__DOT__bus_write) - & (IData)( - ((((0x2000000U - == - (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) - & (0xf000ULL - == - (0xf000ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted))) - & (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted)))); - vlSelf->main__DOT__i2ci__DOT__bus_override = ((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted)) - & ((IData)(vlSelf->main__DOT__i2ci__DOT__bus_write) - & (IData)( - ((0x1000000U - == - (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xcU)))))); - vlSelf->o_ddr3_controller_cmd[0U] = (IData)((((QData)((IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U])) - << 0x18U) - | (QData)((IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [0U])))); - vlSelf->o_ddr3_controller_cmd[1U] = ((vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [2U] << 0x10U) - | (IData)( - ((((QData)((IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U])) - << 0x18U) - | (QData)((IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [0U]))) - >> 0x20U))); - vlSelf->o_ddr3_controller_cmd[2U] = ((vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [3U] << 8U) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [2U] >> 0x10U)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write - = ((IData)(vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 7U)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch - = (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl)) - | ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid)) - & (IData)(main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge) - & (IData)(main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0)); - vlSelf->main__DOT__i2ci__DOT__i2c_stretch = (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__w_scl)) - | ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__s_tvalid)) - & (IData)(main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0))); - vlSelf->main__DOT__i2ci__DOT__insn_ready = ((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckedge) - & (IData)(main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags - = ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)) - << 3U) | ((4U & ((4U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - >> 0x1dU)) - ^ (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)) - << 2U))) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c) - << 1U) - | (0U - == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result)))) - : ((3U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? ((4U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - >> 0x1dU)) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z))) - : 0U)); - if (main__DOT__wbu_xbar__DOT____VdfgTmp_h4f7f05b5__0) { - vlSelf->main__DOT__wbu_xbar__DOT__m_stb = (1U - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__mfull))); - vlSelf->main__DOT__wbu_xbar__DOT__request[0U] - = vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded; - } else { - vlSelf->main__DOT__wbu_xbar__DOT__m_stb = 0U; - vlSelf->main__DOT__wbu_xbar__DOT__request[0U] = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase) - ? (0x80000000U | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_nxt_half) - << 0x10U) | (0xffffU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU]))) - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU]); - vlSelf->main__DOT__swic__DOT__dc_stall = (IData)( - (((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 2U) - | (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner))); - if (main__DOT__wb32_xbar__DOT____VdfgTmp_h4f7f05b5__0) { - vlSelf->main__DOT__wb32_xbar__DOT__m_stb = - (1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull))); - vlSelf->main__DOT__wb32_xbar__DOT__request[0U] - = vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded; - } else { - vlSelf->main__DOT__wb32_xbar__DOT__m_stb = 0U; - vlSelf->main__DOT__wb32_xbar__DOT__request[0U] = 0U; - } - vlSelf->main__DOT__wb32_wbdown_stb = ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb)); - vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - ? (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)))) - ? 1U : ((0x40U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - ? 2U : 3U)) : 0U); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__pic_interrupt)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 5U) & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Aid)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)) - & ((~ (IData)((0U != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((~ (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 5U)) & (IData)((0x1eU - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB))) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready)); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU]; - if (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU] = 0U; - } - if (vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) { - __Vtemp_hdb251f8c__0[0U] = Vmain__ConstPool__CONST_hbd99daea_0[0U]; - __Vtemp_hdb251f8c__0[1U] = Vmain__ConstPool__CONST_hbd99daea_0[1U]; - __Vtemp_hdb251f8c__0[2U] = Vmain__ConstPool__CONST_hbd99daea_0[2U]; - __Vtemp_hdb251f8c__0[3U] = Vmain__ConstPool__CONST_hbd99daea_0[3U]; - __Vtemp_hdb251f8c__0[4U] = Vmain__ConstPool__CONST_hbd99daea_0[4U]; - __Vtemp_hdb251f8c__0[5U] = Vmain__ConstPool__CONST_hbd99daea_0[5U]; - __Vtemp_hdb251f8c__0[6U] = Vmain__ConstPool__CONST_hbd99daea_0[6U]; - __Vtemp_hdb251f8c__0[7U] = Vmain__ConstPool__CONST_hbd99daea_0[7U]; - __Vtemp_hdb251f8c__0[8U] = Vmain__ConstPool__CONST_hbd99daea_0[8U]; - __Vtemp_hdb251f8c__0[9U] = Vmain__ConstPool__CONST_hbd99daea_0[9U]; - __Vtemp_hdb251f8c__0[0xaU] = Vmain__ConstPool__CONST_hbd99daea_0[0xaU]; - __Vtemp_hdb251f8c__0[0xbU] = Vmain__ConstPool__CONST_hbd99daea_0[0xbU]; - __Vtemp_hdb251f8c__0[0xcU] = Vmain__ConstPool__CONST_hbd99daea_0[0xcU]; - __Vtemp_hdb251f8c__0[0xdU] = Vmain__ConstPool__CONST_hbd99daea_0[0xdU]; - __Vtemp_hdb251f8c__0[0xeU] = Vmain__ConstPool__CONST_hbd99daea_0[0xeU]; - __Vtemp_hdb251f8c__0[0xfU] = vlSelf->main__DOT__wb32_wbdown_idata; - VL_SHIFTR_WWI(512,512,32, __Vtemp_h12b8adbe__0, __Vtemp_hdb251f8c__0, - (0x1e0U & ((IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data) - << 5U))); - __Vtemp_hb780e8f4__0[1U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U] - | __Vtemp_h12b8adbe__0[1U]); - __Vtemp_hb780e8f4__0[2U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U] - | __Vtemp_h12b8adbe__0[2U]); - __Vtemp_hb780e8f4__0[3U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U] - | __Vtemp_h12b8adbe__0[3U]); - __Vtemp_hb780e8f4__0[4U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U] - | __Vtemp_h12b8adbe__0[4U]); - __Vtemp_hb780e8f4__0[5U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U] - | __Vtemp_h12b8adbe__0[5U]); - __Vtemp_hb780e8f4__0[6U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U] - | __Vtemp_h12b8adbe__0[6U]); - __Vtemp_hb780e8f4__0[7U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U] - | __Vtemp_h12b8adbe__0[7U]); - __Vtemp_hb780e8f4__0[8U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U] - | __Vtemp_h12b8adbe__0[8U]); - __Vtemp_hb780e8f4__0[9U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U] - | __Vtemp_h12b8adbe__0[9U]); - __Vtemp_hb780e8f4__0[0xaU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU] - | __Vtemp_h12b8adbe__0[0xaU]); - __Vtemp_hb780e8f4__0[0xbU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU] - | __Vtemp_h12b8adbe__0[0xbU]); - __Vtemp_hb780e8f4__0[0xcU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU] - | __Vtemp_h12b8adbe__0[0xcU]); - __Vtemp_hb780e8f4__0[0xdU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU] - | __Vtemp_h12b8adbe__0[0xdU]); - __Vtemp_hb780e8f4__0[0xeU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU] - | __Vtemp_h12b8adbe__0[0xeU]); - __Vtemp_hb780e8f4__0[0xfU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU] - | __Vtemp_h12b8adbe__0[0xfU]); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U] - = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U] - | __Vtemp_h12b8adbe__0[0U]); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U] - = __Vtemp_hb780e8f4__0[1U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U] - = __Vtemp_hb780e8f4__0[2U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U] - = __Vtemp_hb780e8f4__0[3U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U] - = __Vtemp_hb780e8f4__0[4U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U] - = __Vtemp_hb780e8f4__0[5U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U] - = __Vtemp_hb780e8f4__0[6U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U] - = __Vtemp_hb780e8f4__0[7U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U] - = __Vtemp_hb780e8f4__0[8U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U] - = __Vtemp_hb780e8f4__0[9U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU] - = __Vtemp_hb780e8f4__0[0xaU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU] - = __Vtemp_hb780e8f4__0[0xbU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU] - = __Vtemp_hb780e8f4__0[0xcU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU] - = __Vtemp_hb780e8f4__0[0xdU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU] - = __Vtemp_hb780e8f4__0[0xeU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU] - = __Vtemp_hb780e8f4__0[0xfU]; - } - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbu_cyc)); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((2U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | (0U == (0x4000000U & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U))))); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((1U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((0U == (0x4000000U & (0x4000000U ^ (0x7ffffffU - & (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))) - << 1U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__fill; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill - = (0xffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))); - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill - = (0xffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill) - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size))); - } - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read - = ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)) - & (IData)(vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6)); - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write - = ((IData)(vlSelf->main__DOT__console__DOT__txf_wb_write) - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - | (IData)(vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)); - vlSelf->main__DOT__swic__DOT__reset_request = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0) - & (vlSelf->main__DOT__swic__DOT__dbg_idata - >> 3U)); - vlSelf->main__DOT__swic__DOT__step_request = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0) - & (vlSelf->main__DOT__swic__DOT__dbg_idata - >> 2U)); - vlSelf->main__DOT__swic__DOT__halt_request = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0) - & vlSelf->main__DOT__swic__DOT__dbg_idata); - vlSelf->main__DOT__swic__DOT__clear_cache_request - = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0) - & (vlSelf->main__DOT__swic__DOT__dbg_idata - >> 4U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x80000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U])))); 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- vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xffbU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 2U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x18U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xff7U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 3U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x20U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xfefU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 4U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x28U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xfdfU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 5U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x30U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xfbfU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 6U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x38U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xf7fU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 7U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x40U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xeffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 8U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x48U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xdffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 9U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xe0U & (0x60U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xbffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 0xaU)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0x80U & (0x80U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0x7ffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 0xbU)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err - = ((IData)(vlSelf->main__DOT__swic__DOT__dc_err) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)); 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- if ((IData)((0x240U == (0x3c0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request = 0U; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck - = ((1U & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid))) - ? 0U : (3U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg) - << 2U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge)) - >> (7U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift) - >> 2U))))); - vlSelf->io_emmc_cmd_tristate = (1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0))); - vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4 - = (((IData)(vlSelf->o_emmc_clk) << 0x19U) | - (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - << 0x17U) | (((IData)(vlSelf->o_emmc_cmd) - << 0x16U) | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0) - ? (IData)(vlSelf->o_emmc_cmd) - : (IData)(vlSelf->i_emmc_cmd)) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - << 8U) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - ? (IData)(vlSelf->o_emmc_dat) - : (IData)(vlSelf->i_emmc_dat))))))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck - = (1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)) - & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg) - << 1U) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge)) - >> (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) - & ((~ (IData)(vlSelf->o_emmc_clk)) & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (IData)((((0x1000000U == (0x3000000U & - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - >> 0xbU)) & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1dU)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (IData)(((((0x2000000U == (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (0xf0000000ULL == (0xf0000000ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted))) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted)) - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (IData)(((0x1000000U == (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1cU)))))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready - = (1U & (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait)) - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready) - | ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn) - >> 0xbU))) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual))); - vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4 - = ((0x40000000U & ((IData)(vlSelf->main__DOT__i2ci__DOT__ovw_data) - << 0x15U)) | (((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_abort) - << 0x1dU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_stretch) - << 0x1cU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_insn) - << 0x18U) - | vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0)))); - vlSelf->main__DOT__i2ci__DOT__half_ready = (1U - & (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_wait)) - & ((IData)(vlSelf->main__DOT__i2ci__DOT__insn_ready) - | ((IData)(vlSelf->main__DOT__i2ci__DOT__insn) - >> 0xbU))) - | (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0 - = (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__iflags)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0 - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__flags)); - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])); - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available - = (0U != (3U & ((vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))) - & (~ vlSelf->main__DOT__wbu_xbar__DOT__requested - [0U])))); - if ((4U & vlSelf->main__DOT__wbu_xbar__DOT__request - [0U])) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available = 1U; - } - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available - = vlSelf->main__DOT__wbu_xbar__DOT__m_stb; - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - if ((1U & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbu_xbar__DOT__requested - [0U])))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbu_xbar__DOT__request - [0U]))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (6U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbu_xbar__DOT__requested - [0U] >> 1U))))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] >> 1U)))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (5U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((4U & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] >> 2U)))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (3U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if (((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty)))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel = 1U; - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - } - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U])))); - if ((((~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) ? 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vlSelf->main__DOT__wbu_xbar__DOT__request - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]] : 0U) >> 1U)) & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]))) - & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U])))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant) - >> 1U)))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbu_xbar__DOT__m_stall = (1U - & ((vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U] - >> 2U) - | (((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - & ((2U - >= - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U]) - & (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] - >> - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U]))) - ? - ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mfull) - | ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U])) - : (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb)))); - if (vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) { - vlSelf->main__DOT__wbu_xbar__DOT__m_stall = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_ljmp - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase) - & (0xfcf8U == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x10U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div - = (IData)((0x3800000U == (0x87800000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_fpu - = (IData)(((0x6000000U == (0x86000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - & ((7U != (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1cU))) & (0U - != - (3U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x17U)))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI - = (0xffU & ((6U == (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x18U))) ? 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- } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 0xbU)) & (~ (vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U] >> 0xbU))))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0x800U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 0xbU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0x17ffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((0x1000U & vlSelf->main__DOT__wb32_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0x1000U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 0xcU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xfffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if (((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty)))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U])))); - if ((((~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]] : 0U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]))) & ( - (0U - >= - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]] : 0U) >> 1U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 1U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]] : 0U) >> 2U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 2U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]] : 0U) >> 3U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 3U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]] : 0U) >> 4U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 4U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]] : 0U) >> 5U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 5U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]] : 0U) >> 6U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 6U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]] : 0U) >> 7U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 7U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]] : 0U) >> 8U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 8U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]] : 0U) >> 9U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 9U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]] : 0U) >> 0xaU)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 0xaU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]] : 0U) >> 0xbU)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 0xbU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 0U; - } - if (vlSelf->i_reset) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 1U; - } - vlSelf->main__DOT__wb32_xbar__DOT__m_stall = (1U - & ((vlSelf->main__DOT__wb32_xbar__DOT__grant - [0U] - >> 0xcU) - | (((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant) - & ((0xcU - >= - vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U]) - & (vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] - >> - vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U]))) - ? - ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - | ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U])) - : (IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb)))); - if (vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) { - vlSelf->main__DOT__wb32_xbar__DOT__m_stall = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0U] - = (IData)(((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) : - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[1U] - = (IData)((((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) : - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel)) - >> 0x20U)); - if (vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) { - vlSelf->main__DOT__wbwide_zip_stb = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb)); - vlSelf->main__DOT__wbwide_zip_addr = vlSelf->main__DOT__swic__DOT__cpu_addr; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[2U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[3U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[4U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[5U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[6U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[7U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[8U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[9U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xaU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xbU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xcU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xdU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xeU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x10U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x11U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU]; - vlSelf->main__DOT__wbwide_zip_cyc = vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc; - } else { - vlSelf->main__DOT__wbwide_zip_stb = vlSelf->main__DOT__swic__DOT__dc_stb; - vlSelf->main__DOT__wbwide_zip_addr = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x10U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x11U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xfU]; - vlSelf->main__DOT__wbwide_zip_cyc = vlSelf->main__DOT__swic__DOT__dc_cyc; - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x12U] - = ((0x400000U & (((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__cpu_we) - : (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner))) - << 0x16U)) | vlSelf->main__DOT__wbwide_zip_addr); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__wb32_wbdown_stb))); - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr - = ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - & (IData)(vlSelf->main__DOT__wb32_wbdown_stb)); - vlSelf->main__DOT__swic__DOT__sys_cyc = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__dbg_cyc)); - vlSelf->main__DOT__swic__DOT__dbg_stall = ((IData)(vlSelf->main__DOT__swic__DOT__cmd_read) - | (((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall) - & (0x20U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))))) - | (((IData)(vlSelf->main__DOT__swic__DOT__dbg_addr) - >> 6U) - & (IData)(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc)))); - if (vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc) { - vlSelf->main__DOT__swic__DOT__sys_data = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - vlSelf->main__DOT__swic__DOT__sys_we = vlSelf->main__DOT__swic__DOT__cpu_we; - vlSelf->main__DOT__swic__DOT__sys_addr = (0xffU - & vlSelf->main__DOT__swic__DOT__cpu_addr); - vlSelf->main__DOT__swic__DOT__sys_stb = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl)); - } else { - vlSelf->main__DOT__swic__DOT__sys_data = vlSelf->main__DOT__swic__DOT__dbg_idata; - vlSelf->main__DOT__swic__DOT__sys_we = vlSelf->main__DOT__swic__DOT__dbg_we; - vlSelf->main__DOT__swic__DOT__sys_addr = (0xffU - & (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))); - vlSelf->main__DOT__swic__DOT__sys_stb = ((IData)(vlSelf->main__DOT__swic__DOT__dbg_stb) - & (0x40U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr)))); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_brev_result - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x1fU) | ((0x40000000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x1dU)) - | ((0x20000000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x1bU)) - | ((0x10000000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x19U)) - | ((0x8000000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x17U)) - | ((0x4000000U & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x15U)) | - ((0x2000000U & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x13U)) - | ((0x1000000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x11U)) - | ((0x800000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0xfU)) - | ((0x400000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0xdU)) - | ((0x200000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0xbU)) - | ((0x100000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 9U)) - | ((0x80000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 7U)) - | ((0x40000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 5U)) - | ((0x20000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 3U)) - | ((0x10000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 1U)) - | ((0x8000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 1U)) - | ((0x4000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 3U)) - | ((0x2000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 5U)) - | ((0x1000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 7U)) - | ((0x800U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U)) - | ((0x400U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0xbU)) - | ((0x200U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0xdU)) - | ((0x100U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0xfU)) - | ((0x80U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x11U)) - | ((0x40U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x13U)) - | ((0x20U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x15U)) - | ((0x10U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x17U)) - | ((8U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x19U)) - | ((4U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1bU)) - | ((2U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1dU)) - | (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1fU)))))))))))))))))))))))))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow - = (1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v) - >> (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U))) & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag - == (0x7ffffU - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address = 0U; - if ((0x4000000U == (0xe000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address = 1U; - } - if ((0x8000000U == (0x8000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address = 1U; - } - main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_h832f938f__0 - = ((0U != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U)) | ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 5U) & (0U != (0x1fU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce - = (1U & ((~ (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__last_write_to_cc)) - | ((IData)(vlSelf->main__DOT__swic__DOT__cpu_break) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep)))) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)))); - if (vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc) { - vlSelf->main__DOT__swic__DOT__cpu_err = ((IData)(vlSelf->main__DOT__swic__DOT__ext_err) - & (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)); - vlSelf->main__DOT__swic__DOT__cpu_idata[0U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[1U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[2U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[3U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[4U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[5U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[6U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[7U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[8U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[9U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU]; - } else { - vlSelf->main__DOT__swic__DOT__cpu_err = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0U] - = vlSelf->main__DOT__swic__DOT__sys_idata; - vlSelf->main__DOT__swic__DOT__cpu_idata[1U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[2U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[3U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[4U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[5U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[6U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[7U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[8U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[9U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU] = 0U; - } - vlSelf->main__DOT__swic__DOT__cpu_ack = (((IData)(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_ack)) - | ((IData)(vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U) - & (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)))); - vlSelf->main__DOT__swic__DOT__cpu_stall = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)) - | ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 2U))); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4 - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - << 0x1cU) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck) - << 0x1aU) | ((0x2000000U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - << 0x12U)) - | ((0x1000000U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - << 0x15U)) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - << 0x17U) - | ((0x600000U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2eU)) - << 0x15U)) - | (((IData)( - (3U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in))) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - << 8U) - | (0xffU - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - ? - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out))))))))))))))); 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- vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags - = (0x20U | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 0xdU) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag) - << 0xbU) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag) - << 0xaU) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap) - << 9U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u) - << 8U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak) - << 7U) - | ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step)) - << 6U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep) - << 4U) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0)))))))))); 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(IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0))) - == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F))); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall - = ((IData)(vlSelf->main__DOT__wbu_cyc) & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stall)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_he52a0fcf__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_fpu) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_noop - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - & (0x7800000U == (0x7800000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_lock - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - & (0x7400000U == (0x7c00000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - if ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU)) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0 - = (0xfU & ((IData)((0x4000000U == (0x6800000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))) - ? 0xdU : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x13U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op - = (0x1fU & ((0x4000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? ((0x2000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? ((0x1000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 0xdU : 0x18U) : - ((0x1000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 0x13U : 0x12U)) : ( - (0x2000000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? - ((0x1000000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 0x10U - : 2U) - : - ((0x1000000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 1U - : 0U)))); - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0 - = (0xfU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xeU)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op - = (0x1fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x16U)); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 4U)) & (7U != (7U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h9ed30f6d__0 - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - | (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU)) | (0xcU == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc - = ((0xcU == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))) ? 0U : ((0xdU - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - ? 1U - : ((0x40000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 3U - : 2U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I - = (0x7fffffU & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU) ? ((0x7fff00U & - ((- (IData)( - (1U - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI) - >> 7U)))) - << 8U)) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI)) - : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? ((0x7fc000U & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xdU)))) - << 0xeU)) - | (0x3fffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - : ((0x7c0000U & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x11U)))) - << 0x12U)) - | (0x3ffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? ((0x7fe000U & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xcU)))) - << 0xdU)) - | (0x1fffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem - = (IData)(((0x10U == (0x18U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op))) - & (0U != (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))); - main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0 - = ((~ (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU)) & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (0xdU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr - = ((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - << 6U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr - = (0xfffffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size))); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last)) - & ((~ ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb)))) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - = ((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr - << 6U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall)))) { - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size))) { - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - = (0x1fffffffU & ((IData)(1U) - + vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)); - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc) - ? (0x1fffffffU & ((IData)(2U) - + vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) - : (0x1ffffffeU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)); - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - = ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size)) - ? ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc) - ? (0x1fffffffU & ((IData)(4U) - + vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) - : (0x1ffffffcU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc) - ? (0x1fffffffU & ((IData)(0x40U) - + vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) - : (0x1fffffc0U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr))); - } - } - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall - = ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stall)); - if (vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U]; - } else { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x12U]; - } - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr - = ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr)); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty - = ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty)); - vlSelf->main__DOT__swic__DOT____VdfgTmp_h9a48e2a3__0 - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stall)) - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_stb)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src) - | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst) - | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len) - | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen - = ((0xfffffc00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen) - | (0x3ffU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen - = (0x3ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen - = ((0xfffffbffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen) - | ((0U == (0x3ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen)) - << 0xaU)); - vlSelf->main__DOT__swic__DOT__sel_bus_watchdog - = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (2U == (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))); - vlSelf->main__DOT__swic__DOT__sel_dmac = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (0x10U - == - (0xf0U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT__sel_watchdog = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (1U - == (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))); - vlSelf->main__DOT__swic__DOT__sel_apic = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (3U - == (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))); - vlSelf->main__DOT__swic__DOT__sel_pic = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (0U - == (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))); - vlSelf->main__DOT__swic__DOT__sel_timer = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (4U - == - (0xfcU - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT__actr_ack = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (8U - == - (0xf8U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_asr_result - = (0x1ffffffffULL & ((0U != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 5U)) ? (- (QData)((IData)( - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU)))) - : VL_SHIFTRS_QQI(33,33,5, - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - << 1U), - (0x1fU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)))); - if ((0U == (2U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - } else if ((2U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U); - } else if ((3U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U); - } - if ((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[1U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[2U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[3U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[4U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[5U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[6U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[7U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[8U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[9U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xfU] = 0U; - VL_SHIFTR_WWI(512,512,32, __Vtemp_hbc743227__0, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift, - (0x18U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 3U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0U] - = __Vtemp_hbc743227__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[1U] - = __Vtemp_hbc743227__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[2U] - = __Vtemp_hbc743227__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[3U] - = __Vtemp_hbc743227__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[4U] - = __Vtemp_hbc743227__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[5U] - = __Vtemp_hbc743227__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[6U] - = __Vtemp_hbc743227__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[7U] - = __Vtemp_hbc743227__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[8U] - = __Vtemp_hbc743227__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[9U] - = __Vtemp_hbc743227__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xaU] - = __Vtemp_hbc743227__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xbU] - = __Vtemp_hbc743227__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xcU] - = __Vtemp_hbc743227__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xdU] - = __Vtemp_hbc743227__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xeU] - = __Vtemp_hbc743227__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xfU] - = __Vtemp_hbc743227__0[0xfU]; - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0U] - = Vmain__ConstPool__CONST_hbd99daea_0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[1U] - = Vmain__ConstPool__CONST_hbd99daea_0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[2U] - = Vmain__ConstPool__CONST_hbd99daea_0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[3U] - = Vmain__ConstPool__CONST_hbd99daea_0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[4U] - = Vmain__ConstPool__CONST_hbd99daea_0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[5U] - = Vmain__ConstPool__CONST_hbd99daea_0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[6U] - = Vmain__ConstPool__CONST_hbd99daea_0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[7U] - = Vmain__ConstPool__CONST_hbd99daea_0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[8U] - = Vmain__ConstPool__CONST_hbd99daea_0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[9U] - = Vmain__ConstPool__CONST_hbd99daea_0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xaU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xbU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xcU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xdU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xeU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift; - VL_SHIFTR_WWI(512,512,32, __Vtemp_h6409050d__0, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift, - (0x1f8U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 3U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0U] - = __Vtemp_h6409050d__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[1U] - = __Vtemp_h6409050d__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[2U] - = __Vtemp_h6409050d__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[3U] - = __Vtemp_h6409050d__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[4U] - = __Vtemp_h6409050d__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[5U] - = __Vtemp_h6409050d__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[6U] - = __Vtemp_h6409050d__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[7U] - = __Vtemp_h6409050d__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[8U] - = __Vtemp_h6409050d__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[9U] - = __Vtemp_h6409050d__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xaU] - = __Vtemp_h6409050d__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xbU] - = __Vtemp_h6409050d__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xcU] - = __Vtemp_h6409050d__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xdU] - = __Vtemp_h6409050d__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xeU] - = __Vtemp_h6409050d__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xfU] - = __Vtemp_h6409050d__0[0xfU]; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable - = ((0xffU != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) & ((~ (IData)((0U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address))); - if (main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_h832f938f__0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result = 0ULL; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result = 0ULL; - } else if ((0x20U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result - = (0x1ffffffffULL & (QData)((IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result - = (0x1ffffffffULL & ((QData)((IData)((1U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata))) - << 0x20U)); - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result - = (0x1ffffffffULL & (((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - << 1U) >> (0x1fU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result - = (0x1ffffffffULL & ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - << (0x1fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))); - } - vlSelf->main__DOT__swic__DOT__cpu_pf_stall = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce)) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt) - & ((~ (IData)((0U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal) - | (IData)(vlSelf->main__DOT__swic__DOT__cpu_break)))))))))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__cpu_err)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err - = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_err) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)); - VL_SHIFTL_WWI(512,512,32, __Vtemp_h8c81192e__0, vlSelf->main__DOT__swic__DOT__cpu_idata, 0x1e0U); - VL_SHIFTL_WWI(512,512,32, __Vtemp_h5dad54bf__0, __Vtemp_h8c81192e__0, - (0x18U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0) - << 3U))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid) { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xfU]; - } else if ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__cpu_idata[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__cpu_idata[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__cpu_idata[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__cpu_idata[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__cpu_idata[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__cpu_idata[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__cpu_idata[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__cpu_idata[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__cpu_idata[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__cpu_idata[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU]; - } else { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xfU]; - } - VL_SHIFTL_WWI(512,512,32, __Vtemp_hf1acda43__0, __Vtemp_h01ff8f7b__0, - (0x1f8U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0) - << 3U))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0U] - = __Vtemp_h5dad54bf__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[1U] - = __Vtemp_h5dad54bf__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[2U] - = __Vtemp_h5dad54bf__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[3U] - = __Vtemp_h5dad54bf__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[4U] - = __Vtemp_h5dad54bf__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[5U] - = __Vtemp_h5dad54bf__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[6U] - = __Vtemp_h5dad54bf__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[7U] - = __Vtemp_h5dad54bf__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[8U] - = __Vtemp_h5dad54bf__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[9U] - = __Vtemp_h5dad54bf__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xaU] - = __Vtemp_h5dad54bf__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xbU] - = __Vtemp_h5dad54bf__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xcU] - = __Vtemp_h5dad54bf__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xdU] - = __Vtemp_h5dad54bf__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xeU] - = __Vtemp_h5dad54bf__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xfU] - = __Vtemp_h5dad54bf__0[0xfU]; - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0U] - = __Vtemp_hf1acda43__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[1U] - = __Vtemp_hf1acda43__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[2U] - = __Vtemp_hf1acda43__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[3U] - = __Vtemp_hf1acda43__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[4U] - = __Vtemp_hf1acda43__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[5U] - = __Vtemp_hf1acda43__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[6U] - = __Vtemp_hf1acda43__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[7U] - = __Vtemp_hf1acda43__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[8U] - = __Vtemp_hf1acda43__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[9U] - = __Vtemp_hf1acda43__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xaU] - = __Vtemp_hf1acda43__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xbU] - = __Vtemp_hf1acda43__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xcU] - = __Vtemp_hf1acda43__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xdU] - = __Vtemp_hf1acda43__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xeU] - = __Vtemp_hf1acda43__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xfU] - = __Vtemp_hf1acda43__0[0xfU]; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__cpu_ack)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack - = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_ack) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)); - vlSelf->main__DOT__zip_cpu_int = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cpu_stall)) - & (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stall - = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_stall) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)) - | (IData)(vlSelf->main__DOT__swic__DOT__cpu_stall))); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchbus____pinNumber2 - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | ((~ (IData)(vlSelf->main__DOT__wbwide_zip_cyc)) - | ((IData)(vlSelf->main__DOT__wbwide_zip_stb) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U))))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_zip_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc - = (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc) - << 3U) | (((IData)(vlSelf->main__DOT__wbwide_zip_cyc) - << 2U) | (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - << 1U) | (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_stb = (( - ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc) - & ((~ - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 3U)) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid))) - << 3U) - | ((((IData)(vlSelf->main__DOT__wbwide_zip_cyc) - & ((~ - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 2U)) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid))) - << 2U) - | ((((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & ((~ - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 1U)) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid))) - << 1U) - | ((IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc) - & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)))))); - vlSelf->main__DOT__wbwide_xbar__DOT__request[2U] - = (((IData)(vlSelf->main__DOT__wbwide_zip_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid)) - ? (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__decoded) - : 0U); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_ready - = ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid)) - & (IData)(main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready - = ((~ ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait))) - & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid)) - & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc)) - & (IData)(main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0)))); - vlSelf->main__DOT__i2ci__DOT__ovw_ready = ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__half_valid)) - & (IData)(main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0)); - vlSelf->main__DOT__i2ci__DOT__pf_ready = ((~ ((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - | (IData)(vlSelf->main__DOT__i2ci__DOT__r_wait))) - & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__half_valid)) - & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc)) - & (IData)(main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0)))); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB - = ((0xdU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - | ((IData)((((0x40000U == (0x80040000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special))) - & (0xcU != (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))) - | ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU) & (((0xcU != (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x17U)) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB - = ((0x10U & (((IData)(main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xdU) : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - << 4U)) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA - = ((0x10U & (((IData)(main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x12U) : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - << 4U)) | (0xfU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1bU))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next)))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xfU]; - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 1U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 2U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 3U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 4U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 5U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 6U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 7U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 8U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 9U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xaU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xbU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xcU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xdU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xeU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xfU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x10U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x11U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x12U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x13U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x14U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x15U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x16U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x17U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x18U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x19U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1aU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1bU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1cU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1dU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1eU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1fU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x20U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x21U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x22U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x23U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x24U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x25U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x26U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x27U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x28U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x29U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2aU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2bU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2cU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2dU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2eU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2fU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x30U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x31U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x32U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x33U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x34U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x35U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x36U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x37U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x38U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x39U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3aU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3bU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3cU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3dU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3eU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3fU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last)))) { - __Vtemp_h448dc795__0[0U] = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - __Vtemp_h448dc795__0[1U] = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - __Vtemp_h448dc795__0[2U] = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - __Vtemp_h448dc795__0[3U] = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - __Vtemp_h448dc795__0[4U] = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - __Vtemp_h448dc795__0[5U] = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - __Vtemp_h448dc795__0[6U] = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - __Vtemp_h448dc795__0[7U] = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - __Vtemp_h448dc795__0[8U] = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - __Vtemp_h448dc795__0[9U] = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - __Vtemp_h448dc795__0[0xaU] = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - __Vtemp_h448dc795__0[0xbU] = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - __Vtemp_h448dc795__0[0xcU] = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - __Vtemp_h448dc795__0[0xdU] = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - __Vtemp_h448dc795__0[0xeU] = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - __Vtemp_h448dc795__0[0xfU] = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - __Vtemp_h448dc795__0[0x10U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U]; - __Vtemp_h448dc795__0[0x11U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U]; - __Vtemp_h448dc795__0[0x12U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U]; - __Vtemp_h448dc795__0[0x13U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U]; - __Vtemp_h448dc795__0[0x14U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U]; - __Vtemp_h448dc795__0[0x15U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U]; - __Vtemp_h448dc795__0[0x16U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U]; - __Vtemp_h448dc795__0[0x17U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U]; - __Vtemp_h448dc795__0[0x18U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U]; - __Vtemp_h448dc795__0[0x19U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U]; - __Vtemp_h448dc795__0[0x1aU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU]; - __Vtemp_h448dc795__0[0x1bU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU]; - __Vtemp_h448dc795__0[0x1cU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU]; - __Vtemp_h448dc795__0[0x1dU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU]; - __Vtemp_h448dc795__0[0x1eU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU]; - __Vtemp_h448dc795__0[0x1fU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU]; - VL_SHIFTR_WWI(1024,1024,32, __Vtemp_h9b90904f__0, __Vtemp_h448dc795__0, - (0x1f8U & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - << 3U))); - __Vtemp_h7be7356a__0[1U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[1U] - | __Vtemp_h9b90904f__0[1U]); - __Vtemp_h7be7356a__0[2U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[2U] - | __Vtemp_h9b90904f__0[2U]); - __Vtemp_h7be7356a__0[3U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[3U] - | __Vtemp_h9b90904f__0[3U]); - __Vtemp_h7be7356a__0[4U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[4U] - | __Vtemp_h9b90904f__0[4U]); - __Vtemp_h7be7356a__0[5U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[5U] - | __Vtemp_h9b90904f__0[5U]); - __Vtemp_h7be7356a__0[6U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[6U] - | __Vtemp_h9b90904f__0[6U]); - __Vtemp_h7be7356a__0[7U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[7U] - | __Vtemp_h9b90904f__0[7U]); - __Vtemp_h7be7356a__0[8U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[8U] - | __Vtemp_h9b90904f__0[8U]); - __Vtemp_h7be7356a__0[9U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[9U] - | __Vtemp_h9b90904f__0[9U]); - __Vtemp_h7be7356a__0[0xaU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xaU] - | __Vtemp_h9b90904f__0[0xaU]); - __Vtemp_h7be7356a__0[0xbU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xbU] - | __Vtemp_h9b90904f__0[0xbU]); - __Vtemp_h7be7356a__0[0xcU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xcU] - | __Vtemp_h9b90904f__0[0xcU]); - __Vtemp_h7be7356a__0[0xdU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xdU] - | __Vtemp_h9b90904f__0[0xdU]); - __Vtemp_h7be7356a__0[0xeU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xeU] - | __Vtemp_h9b90904f__0[0xeU]); - __Vtemp_h7be7356a__0[0xfU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xfU] - | __Vtemp_h9b90904f__0[0xfU]); - __Vtemp_h7be7356a__0[0x10U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - | __Vtemp_h9b90904f__0[0x10U]); - __Vtemp_h7be7356a__0[0x11U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - | __Vtemp_h9b90904f__0[0x11U]); - __Vtemp_h7be7356a__0[0x12U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - | __Vtemp_h9b90904f__0[0x12U]); - __Vtemp_h7be7356a__0[0x13U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - | __Vtemp_h9b90904f__0[0x13U]); - __Vtemp_h7be7356a__0[0x14U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - | __Vtemp_h9b90904f__0[0x14U]); - __Vtemp_h7be7356a__0[0x15U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - | __Vtemp_h9b90904f__0[0x15U]); - __Vtemp_h7be7356a__0[0x16U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - | __Vtemp_h9b90904f__0[0x16U]); - __Vtemp_h7be7356a__0[0x17U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - | __Vtemp_h9b90904f__0[0x17U]); - __Vtemp_h7be7356a__0[0x18U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - | __Vtemp_h9b90904f__0[0x18U]); - __Vtemp_h7be7356a__0[0x19U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - | __Vtemp_h9b90904f__0[0x19U]); - __Vtemp_h7be7356a__0[0x1aU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - | __Vtemp_h9b90904f__0[0x1aU]); - __Vtemp_h7be7356a__0[0x1bU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - | __Vtemp_h9b90904f__0[0x1bU]); - __Vtemp_h7be7356a__0[0x1cU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - | __Vtemp_h9b90904f__0[0x1cU]); - __Vtemp_h7be7356a__0[0x1dU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - | __Vtemp_h9b90904f__0[0x1dU]); - __Vtemp_h7be7356a__0[0x1eU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - | __Vtemp_h9b90904f__0[0x1eU]); - __Vtemp_h7be7356a__0[0x1fU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - | __Vtemp_h9b90904f__0[0x1fU]); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0U] - | __Vtemp_h9b90904f__0[0U]); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[1U] - = __Vtemp_h7be7356a__0[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[2U] - = __Vtemp_h7be7356a__0[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[3U] - = __Vtemp_h7be7356a__0[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[4U] - = __Vtemp_h7be7356a__0[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[5U] - = __Vtemp_h7be7356a__0[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[6U] - = __Vtemp_h7be7356a__0[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[7U] - = __Vtemp_h7be7356a__0[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[8U] - = __Vtemp_h7be7356a__0[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[9U] - = __Vtemp_h7be7356a__0[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xaU] - = __Vtemp_h7be7356a__0[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xbU] - = __Vtemp_h7be7356a__0[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xcU] - = __Vtemp_h7be7356a__0[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xdU] - = __Vtemp_h7be7356a__0[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xeU] - = __Vtemp_h7be7356a__0[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xfU] - = __Vtemp_h7be7356a__0[0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = __Vtemp_h7be7356a__0[0x10U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = __Vtemp_h7be7356a__0[0x11U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = __Vtemp_h7be7356a__0[0x12U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = __Vtemp_h7be7356a__0[0x13U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = __Vtemp_h7be7356a__0[0x14U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = __Vtemp_h7be7356a__0[0x15U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = __Vtemp_h7be7356a__0[0x16U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = __Vtemp_h7be7356a__0[0x17U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = __Vtemp_h7be7356a__0[0x18U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = __Vtemp_h7be7356a__0[0x19U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = __Vtemp_h7be7356a__0[0x1aU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = __Vtemp_h7be7356a__0[0x1bU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = __Vtemp_h7be7356a__0[0x1cU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = __Vtemp_h7be7356a__0[0x1dU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = __Vtemp_h7be7356a__0[0x1eU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = __Vtemp_h7be7356a__0[0x1fU]; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] = 0U; - if ((0U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x80000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((1U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x40000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((2U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x20000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((3U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x10000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((4U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x8000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((5U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x4000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((6U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x2000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((7U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x1000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((8U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x800000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((9U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x400000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xaU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x200000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xbU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x100000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xcU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x80000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xdU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x40000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xeU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x20000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xfU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x10000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x10U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x8000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x11U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x4000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x12U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x2000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x13U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x1000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x14U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x800U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x15U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x400U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x16U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x200U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x17U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x100U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x18U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x80U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x19U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x40U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x20U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x10U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (8U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (4U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (2U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (1U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x20U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x80000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x21U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x40000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x22U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x20000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x23U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x10000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x24U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x8000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x25U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x4000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x26U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x2000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x27U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x1000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x28U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x800000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x29U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x400000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x200000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x100000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x80000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x40000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x20000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x10000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x30U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x8000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x31U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x4000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x32U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x2000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x33U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x1000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x34U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x800U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x35U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x400U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x36U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x200U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x37U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x100U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__2.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__2.cpp deleted file mode 100644 index 2a929fe..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__2.cpp +++ /dev/null @@ -1,8737 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -extern const VlWide<18>/*575:0*/ Vmain__ConstPool__CONST_hb679b2e5_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h40cc9f5d_0; - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__2(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__2\n"); ); - // Init - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior = 0; - CData/*7:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior = 0; - CData/*1:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit = 0; - SData/*8:0*/ __Vtableidx2; - __Vtableidx2 = 0; - // Body - vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb - = vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__req_data - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__gie) - << 0xcU) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0)); - vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc = vlSelf->__Vdly__main__DOT__u_fan__DOT__ign_mem_cyc; - vlSelf->main__DOT__i2ci__DOT__pf_jump_addr = vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_jump_addr; - vlSelf->main__DOT__i2ci__DOT__pf_insn_addr = vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_insn_addr; - vlSelf->main__DOT__wbwide_i2cm_cyc = vlSelf->__Vdly__main__DOT__wbwide_i2cm_cyc; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr; - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending - = vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending - = vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending - = vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending; - vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending - = vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_i2cm_stb = vlSelf->__Vdly__main__DOT__wbwide_i2cm_stb; - vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe - = vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe; - vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw - = vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl[vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0] - = vlSelf->__Vdlyvval__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags - = ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)) - << 3U) | ((4U & ((4U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result - >> 0x1dU)) - ^ (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0)) - << 2U))) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c) - << 1U) - | (0U - == vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result)))) - : ((3U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index)) - ? ((4U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result - >> 0x1dU)) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z))) - : 0U)); - if (vlSelf->__Vdlyvset__main__DOT__i2cscopei__DOT__mem__v0) { - vlSelf->main__DOT__i2cscopei__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__i2cscopei__DOT__mem__v0] - = vlSelf->__Vdlyvval__main__DOT__i2cscopei__DOT__mem__v0; - } - if (vlSelf->__Vdlyvset__main__DOT__emmcscopei__DOT__mem__v0) { - vlSelf->main__DOT__emmcscopei__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__emmcscopei__DOT__mem__v0] - = vlSelf->__Vdlyvval__main__DOT__emmcscopei__DOT__mem__v0; - } - if (vlSelf->__Vdlyvset__main__DOT__sdioscopei__DOT__mem__v0) { - vlSelf->main__DOT__sdioscopei__DOT__mem[vlSelf->__Vdlyvdim0__main__DOT__sdioscopei__DOT__mem__v0] - = vlSelf->__Vdlyvval__main__DOT__sdioscopei__DOT__mem__v0; - } - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness - = vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness; - vlSelf->main__DOT__wbwide_wbu_arbiter_stb = ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full)) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock; - vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr - = vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__rd_addr; - vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr - = vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__rd_addr; - vlSelf->main__DOT__i2ci__DOT__r_halted = vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted; - vlSelf->main__DOT__u_fan__DOT__ctl_sys = vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys; - vlSelf->main__DOT__u_fan__DOT__ctl_fpga = vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr; - vlSelf->main__DOT__u_i2cdma__DOT__subaddr = vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__subaddr; - vlSelf->main__DOT__wbwide_i2cdma_addr = vlSelf->__Vdly__main__DOT__wbwide_i2cdma_addr; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first - = vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U]; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 3U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 2U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z) - ? ((IData)(vlSelf->i_sdcard_dat) - >> 1U) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z) - ? (IData)(vlSelf->i_sdcard_dat) : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin))); - vlSelf->o_sdcard_dat = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin) - << 3U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin) - << 2U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin) - << 1U) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg; - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr - = ((0x10U & (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - << 4U)) | ((8U & (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - << 2U)) | ((4U - & vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr) - | ((2U - & (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - >> 2U)) - | (1U - & (vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr - >> 4U)))))); - vlSelf->main__DOT__w_console_busy = ((IData)(vlSelf->main__DOT__genbus__DOT__ps_full) - | (IData)(vlSelf->main__DOT__genbus__DOT__wbu_tx_stb)); - if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy)))) { - vlSelf->main__DOT__genbus__DOT__wbu_tx_data - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__remap - [vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_bits]; - } - vlSelf->main__DOT__i2cscopei__DOT__lst_adr = (1U - & ((~ - ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U)) - | (IData)(vlSelf->main__DOT__i2cscopei__DOT__imm_adr))); - if ((4U & (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config))) { - vlSelf->main__DOT__i2cscopei__DOT__lst_val - = vlSelf->main__DOT__i2cscopei__DOT__imm_val; - vlSelf->main__DOT__i2cscopei__DOT__imm_val - = ((((IData)(vlSelf->main__DOT__i2cscopei__DOT__new_data) - | (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_force_write)) - | (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stopped)) - ? vlSelf->main__DOT__i2cscopei__DOT__qd_data - : vlSelf->main__DOT__i2cscopei__DOT__ck_addr); - } else { - vlSelf->main__DOT__i2cscopei__DOT__lst_val = 0U; - vlSelf->main__DOT__i2cscopei__DOT__imm_val = 0U; - } - vlSelf->main__DOT__emmcscopei__DOT__lst_adr = (1U - & ((~ - ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U)) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__imm_adr))); - if ((4U & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config))) { - vlSelf->main__DOT__emmcscopei__DOT__lst_val - = vlSelf->main__DOT__emmcscopei__DOT__imm_val; - vlSelf->main__DOT__emmcscopei__DOT__imm_val - = ((((IData)(vlSelf->main__DOT__emmcscopei__DOT__new_data) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_force_write)) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stopped)) - ? vlSelf->main__DOT__emmcscopei__DOT__qd_data - : vlSelf->main__DOT__emmcscopei__DOT__ck_addr); - } else { - vlSelf->main__DOT__emmcscopei__DOT__lst_val = 0U; - vlSelf->main__DOT__emmcscopei__DOT__imm_val = 0U; - } - vlSelf->main__DOT__sdioscopei__DOT__lst_adr = (1U - & ((~ - ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U)) - | (IData)(vlSelf->main__DOT__sdioscopei__DOT__imm_adr))); - if ((4U & (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config))) { - vlSelf->main__DOT__sdioscopei__DOT__lst_val - = vlSelf->main__DOT__sdioscopei__DOT__imm_val; - vlSelf->main__DOT__sdioscopei__DOT__imm_val - = ((((IData)(vlSelf->main__DOT__sdioscopei__DOT__new_data) - | (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_force_write)) - | (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stopped)) - ? vlSelf->main__DOT__sdioscopei__DOT__qd_data - : vlSelf->main__DOT__sdioscopei__DOT__ck_addr); - } else { - vlSelf->main__DOT__sdioscopei__DOT__lst_val = 0U; - vlSelf->main__DOT__sdioscopei__DOT__imm_val = 0U; - } - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__nxt_wrptr - = (0x7fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr))); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cword - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl - [vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cmd_addr]; - if (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)))))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__rd_len - = (0x3ffU & ((1U & (IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x22U))) - ? ((IData)(9U) + ((0x1c0U - & ((IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1fU)) - << 6U)) - | (0x3fU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x18U))))) - : ((IData)(1U) + (7U & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1fU)))))); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cmd_addr - = (0xffU & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr) - - ((0xc0U & ((IData)((vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x1fU)) - << 6U)) | (0x3fU - & (IData)( - (vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - >> 0x18U)))))); - } - if ((0U == (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state))) { - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_inc - = (1U & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x1eU))); - vlSelf->main__DOT__wbu_we = (1U & (~ (IData)( - (vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x23U)))); - } - vlSelf->main__DOT__wbu_idata = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - ? vlSelf->main__DOT__wbu_xbar__DOT__s_data - [vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U]] : 0U); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__nxt_wrptr - = (0x7ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr))); - vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__exec_stb) - | (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)); - if (vlSelf->main__DOT__genbus__DOT__r_wdt_reset) { - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_new_addr = 1U; - } else if (((((~ (IData)(vlSelf->main__DOT__wbu_cyc)) - & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy))) - & (2U != (3U & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x22U)))))) { - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_new_addr - = ((0U == (0xfU & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x20U)))) - | (1U == (7U & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x21U))))); - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched)) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match))))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_hlfd - = (7U & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__maddr) - - (IData)(2U))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld - = (0x3ffU & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__maddr) - - (IData)(0xaU))); - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__zmatch - = ((~ (((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch)))) - & (2U == (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__hmatch - = ((~ (((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)))) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch)))) - & (0xbU > (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr))); - if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__a_addrword; - } - vlSelf->main__DOT__wbu_xbar__DOT__w_mpending[0U] - = vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__wbu_cyc))) - | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->main__DOT__wbu_xbar__DOT__mfull = 0U; - } else if ((1U == ((((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stall))) - << 1U) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->main__DOT__wbu_xbar__DOT__mfull = 0U; - } else if ((2U == ((((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stall))) - << 1U) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->main__DOT__wbu_xbar__DOT__mfull = vlSelf->main__DOT__wbu_xbar__DOT__mnearfull; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel - = ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size)) - ? (((QData)((IData)((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel)))) - << 0x3fU) | (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - >> 1U)) : (((QData)((IData)( - (3U - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel)))) - << 0x3eU) - | (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - >> 2U))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size)) - ? (((QData)((IData)((0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel)))) - << 0x3cU) | (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel - >> 4U)) : 0xffffffffffffffffULL)); - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel; - } - if (vlSelf->main__DOT__wbwide_wbdown_stall) { - if ((1U & ((~ (IData)(vlSelf->main__DOT__wb32_wbdown_stb)) - | (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel; - } - } else { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel - = ((1U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)) - ? (((QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[0U]))) - : 0ULL); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__pc_tag_lookup - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_tag_lookup); - if ((1U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall)))) { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - = ((0x3ffffff8000000ULL & vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr) - | (IData)((IData)(((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wbu_xbar__DOT__m_addr - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]] : 0U)))); - } - } else { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - = (0x3ffffff8000000ULL & vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr); - } - if ((2U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall) - >> 1U)))) { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - = ((0x7ffffffULL & vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wbu_xbar__DOT__m_addr - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]] : 0U))) - << 0x1bU)); - } - } else { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - = (0x7ffffffULL & vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr); - } - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err - = ((((~ (IData)(vlSelf->i_reset)) & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 3U)); - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid = 0U; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__rx_valid)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid - = (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last) - | (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last))) - | (0U != (3U & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill) - >> 6U)))); - } - vlSelf->cpu_sim_ack = ((IData)(vlSelf->cpu_sim_cyc) - & (IData)(vlSelf->main__DOT__raw_cpu_dbg_ack)); - vlSelf->main__DOT__swic__DOT__dbg_ack = ((~ ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_cyc)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__dbg_pre_ack) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_read_ack))); - vlSelf->main__DOT__swic__DOT__ctri_int = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie) - & (IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any))); - vlSelf->main__DOT__swic__DOT__tma_int = ((~ (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write)) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))) - & (1U - == vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value)); - vlSelf->main__DOT__swic__DOT__tmb_int = ((~ (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write)) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))) - & (1U - == vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value)); - vlSelf->main__DOT__swic__DOT__tmc_int = ((~ (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write)) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt))) - & (1U - == vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)) - | (IData)(vlSelf->i_reset))); - if (((8U == (0x1fU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))) - & (0U != (7U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count) - >> 5U))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_data - = (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg); - } - if ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data = 0U; - } else if ((2U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data - = (IData)((0xffffffffULL & ((0xffffffff000000ULL - & ((QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data)) - << 0x18U)) - | (((0x27U - >= ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) - ? (((QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data)) - << 0x18U) - >> - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) - : 0ULL) - >> 8U)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data - = (0xffU & (IData)(((0x27U >= ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) ? - (0xffffffffffULL & - (((QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data)) - << 0x18U) >> ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U))) - : 0ULL))); - } else if ((1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data - = (IData)((0xffffffffULL & ((0xffffffff000000ULL - & ((QData)((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data)) - << 0x18U)) - | (((0x27U - >= ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) - ? (((QData)((IData)( - (0xffU - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data) - >> 8U)))) - << 0x20U) - >> - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) - : 0ULL) - >> 8U)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data - = (0xffU & (IData)(((0x27U >= ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) ? - (0xffffffffffULL & - (((QData)((IData)( - (0xffU - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data) - >> 8U)))) - << 0x20U) >> ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U))) - : 0ULL))); - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data) - << 0x18U); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data - = (0xffU & 0U); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid - = ((~ (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (2U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type))) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout)) - | (4U <= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr)))) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data) - & ((8U == (0x1fU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))) - & (0U != (7U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count) - >> 5U)))))); - if (((8U == (0x1fU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))) - & (0U != (7U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count) - >> 5U))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_data - = (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg); - } - if ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data = 0U; - } else if ((2U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data - = (IData)((0xffffffffULL & ((0xffffffff000000ULL - & ((QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data)) - << 0x18U)) - | (((0x27U - >= ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) - ? (((QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data)) - << 0x18U) - >> - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) - : 0ULL) - >> 8U)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data - = (0xffU & (IData)(((0x27U >= ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) ? - (0xffffffffffULL & - (((QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data)) - << 0x18U) >> ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U))) - : 0ULL))); - } else if ((1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data - = (IData)((0xffffffffULL & ((0xffffffff000000ULL - & ((QData)((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data)) - << 0x18U)) - | (((0x27U - >= ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) - ? (((QData)((IData)( - (0xffU - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data) - >> 8U)))) - << 0x20U) - >> - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) - : 0ULL) - >> 8U)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data - = (0xffU & (IData)(((0x27U >= ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U)) ? - (0xffffffffffULL & - (((QData)((IData)( - (0xffU - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data) - >> 8U)))) - << 0x20U) >> ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr) - << 3U))) - : 0ULL))); - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data) - << 0x18U); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data - = (0xffU & 0U); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid - = ((~ (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (2U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type))) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout)) - | (4U <= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr)))) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data) - & ((8U == (0x1fU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))) - & (0U != (7U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count) - >> 5U)))))); - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending; - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending; - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc))) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - } else if ((1U == ((2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall))) - << 1U)) | (1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - } else if ((2U == ((2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall))) - << 1U)) | (1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = ((0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)) - | (1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 1U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - } else if ((1U == ((2U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 1U)) << 1U))) - | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - } else if ((2U == ((2U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 1U)) << 1U))) - | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = ((0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)) - | (2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 2U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - } else if ((1U == ((2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 1U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 2U)) - << 1U))) | - (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - } else if ((2U == ((2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 1U) & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 2U)) - << 1U))) | - (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = ((0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)) - | (4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 3U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - } else if ((1U == (((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 3U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 3U)))) - << 1U) | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)); - } else if ((2U == (((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 3U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 3U)))) - << 1U) | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mfull - = ((7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)) - | (8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull))); 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- vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U]; - } else { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[1U] - = Vmain__ConstPool__CONST_hb679b2e5_0[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[2U] - = Vmain__ConstPool__CONST_hb679b2e5_0[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[3U] - = Vmain__ConstPool__CONST_hb679b2e5_0[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[4U] - = Vmain__ConstPool__CONST_hb679b2e5_0[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[5U] - = Vmain__ConstPool__CONST_hb679b2e5_0[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[6U] - = Vmain__ConstPool__CONST_hb679b2e5_0[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[7U] - = Vmain__ConstPool__CONST_hb679b2e5_0[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[8U] - = Vmain__ConstPool__CONST_hb679b2e5_0[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[9U] - = Vmain__ConstPool__CONST_hb679b2e5_0[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xaU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xbU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xcU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xdU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xeU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0xfU] - = Vmain__ConstPool__CONST_hb679b2e5_0[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x10U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x11U] - = Vmain__ConstPool__CONST_hb679b2e5_0[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_i2cm_addr; - } - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - if (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled = 0U; - } else if ((0x3ffU == (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__request[1U] - = (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid)) - ? (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__decoded) - : 0U); - vlSelf->main__DOT__i2cscopei__DOT__this_addr = - (0x3ffU & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__read_from_data) - ? ((IData)(1U) + ((IData)(vlSelf->main__DOT__i2cscopei__DOT__raddr) - + (IData)(vlSelf->main__DOT__i2cscopei__DOT__waddr))) - : ((IData)(vlSelf->main__DOT__i2cscopei__DOT__raddr) - + (IData)(vlSelf->main__DOT__i2cscopei__DOT__waddr)))); - vlSelf->main__DOT__emmcscopei__DOT__this_addr = - (0xfffU & ((IData)(vlSelf->main__DOT__emmcscopei__DOT__read_from_data) - ? ((IData)(1U) + ((IData)(vlSelf->main__DOT__emmcscopei__DOT__raddr) - + (IData)(vlSelf->main__DOT__emmcscopei__DOT__waddr))) - : ((IData)(vlSelf->main__DOT__emmcscopei__DOT__raddr) - + (IData)(vlSelf->main__DOT__emmcscopei__DOT__waddr)))); - vlSelf->main__DOT__sdioscopei__DOT__this_addr = - (0xfffU & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__read_from_data) - ? ((IData)(1U) + ((IData)(vlSelf->main__DOT__sdioscopei__DOT__raddr) - + (IData)(vlSelf->main__DOT__sdioscopei__DOT__waddr))) - : ((IData)(vlSelf->main__DOT__sdioscopei__DOT__raddr) - + (IData)(vlSelf->main__DOT__sdioscopei__DOT__waddr)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_wF)); - if (((IData)(vlSelf->main__DOT__wb32_sirefclk_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 9U))) { - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x24U)))) { - vlSelf->main__DOT__r_sirefclk_data = ((0x3fffff00U - & vlSelf->main__DOT__r_sirefclk_data) - | (0xffU - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x25U)))) { - vlSelf->main__DOT__r_sirefclk_data = ((0x3fff00ffU - & vlSelf->main__DOT__r_sirefclk_data) - | (0xff00U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U])); 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- vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U]; - } else { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data[0x12U]; - } - vlSelf->main__DOT__wbu_wbu_arbiter_stall = ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb) - & ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_we = - (1U & ((IData)(vlSelf->cpu_sim_cyc) ? (IData)(vlSelf->cpu_sim_we) - : ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe) - >> 1U))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb)) - | (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall))))) { - vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - = (((QData)((IData)((1U & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x3fU))))) - << 0x24U) | (0xfffffffffULL & vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data)); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable = 0U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable - = (((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB)) - & (7U != (7U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB) - >> 1U)))) & (7U != - (7U & - ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA) - >> 1U)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB) - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA)))); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__saddr - = (7U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr) - >> 3U)); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__svmask - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache))) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__needload - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc))) - & ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal)))) - & (((0U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_v_from_last))) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid)) - | ((0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U)) != vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge - = ((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck)) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 7U)) << 1U) | (IData)((8U == (0x88U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk))))); - vlSelf->o_sirefclk_ce = vlSelf->main__DOT__r_sirefclk_en; - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_abort))) { - vlSelf->main__DOT__i2ci__DOT__insn_valid = 0U; - } else if (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual) - | (IData)(vlSelf->main__DOT__i2ci__DOT__bus_manual))) { - vlSelf->main__DOT__i2ci__DOT__insn_valid = 0U; - } else if (vlSelf->main__DOT__i2ci__DOT__next_valid) { - vlSelf->main__DOT__i2ci__DOT__insn_valid = - ((IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle) - | ((3U != (0xfU & ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - >> 4U))) & (0xdU != - (0xfU & - ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - >> 4U))))); - } else if (((((~ (IData)(vlSelf->main__DOT__i2ci__DOT__half_valid)) - | (3U == (IData)(vlSelf->main__DOT__i2ci__DOT__half_insn))) - | (0xdU == (IData)(vlSelf->main__DOT__i2ci__DOT__half_insn))) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready))) { - vlSelf->main__DOT__i2ci__DOT__insn_valid = 0U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_lock)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal))); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_break - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - & (0x7000000U == (0x7c00000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wF - = ((8U == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h9ed30f6d__0) - | (0U == - (7U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x13U)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_he52a0fcf__0) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU) - & ((0xdU - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - & ((9U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - & ((8U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - & (7U - != - (7U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1cU)))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B - = ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB) - & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0))) - << 6U) | ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB) - & (0xfU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0))) - << 5U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_DIV - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - & (0x7800000U == (0x7c00000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_noop)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ALU - = ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU) - | (0xcU == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U)))) | (8U - == - (0xfU - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U)))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_noop)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_lock - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_lock; - } - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_waddr_plus_one - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr))); - vlSelf->main__DOT__console__DOT__tx_uart_reset - = (((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 5U) & (IData)(((0U == (0x300U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x14U)))) & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 5U)) - | (((IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 5U) & (0x300U == (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])))) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 5U)) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[5U] - >> 0xcU) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x15U))))); - vlSelf->main__DOT__wbu_rx_stb = (((IData)(vlSelf->main__DOT__rcv__DOT__zero_baud_counter) - & (8U == (IData)(vlSelf->main__DOT__rcv__DOT__state))) - & (IData)(vlSelf->main__DOT__rcv__DOT__ck_uart)); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write - = ((IData)(vlSelf->main__DOT__w_console_rx_stb) - & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow)) - | (IData)(vlSelf->main__DOT__console__DOT__rxf_wb_read))); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_waddr_plus_one - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr))); - vlSelf->main__DOT__console__DOT__rx_uart_reset = 0U; - if ((0x20U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)))) { - if ((IData)(((0U == (0x300U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x14U)))) { - vlSelf->main__DOT__console__DOT__rx_uart_reset = 1U; - } - if (((IData)(((0x200U == (0x300U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x15U))) & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[5U] - >> 0xcU))) { - vlSelf->main__DOT__console__DOT__rx_uart_reset = 1U; - } - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2c_valid)) - | (IData)(vlSelf->main__DOT__i2c_ready)))) { - vlSelf->main__DOT__i2c_data = vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg; - vlSelf->main__DOT__i2c_last = vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte; - } - vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted)); - vlSelf->o_emmc_clk = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__sdclk) - >> 7U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce)); - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal))); - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid = 0U; - } else { - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase = 0U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_M) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_valid)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal - = ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wR)) - | (~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R) - >> 5U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_valid) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)); - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid = 0U; - } - } - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - if (((IData)(vlSelf->main__DOT__u_fan__DOT__i2cd_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__i2cd_last))) { - vlSelf->main__DOT__u_fan__DOT__temp_data = - ((vlSelf->main__DOT__u_fan__DOT__temp_tmp - << 8U) | (IData)(vlSelf->main__DOT__u_fan__DOT__i2cd_data)); - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request = 0U; - } else if (((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (0U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]))) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - >> 0x16U)) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1eU)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request = 1U; - } - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda - = ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual) - ? (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda) - : (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl - = ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual) - ? (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl) - : (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl))); - if (vlSelf->i_reset) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc = 1U; - vlSelf->main__DOT__i2ci__DOT__cpu_new_pc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__w_sdclk = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_reset = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_counter = 0U; - vlSelf->main__DOT__u_fan__DOT__tach_count = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_timer = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount = 0xc8U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter = 0U; - vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl = 1U; - vlSelf->main__DOT__u_fan__DOT__pp_ms = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__trigger_counter = 0x1869fU; - } else { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc = 0U; - if ((((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle))) - & (0xc0U == (0xf0U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn)))) - | (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready)) - & (0xcU == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc = 1U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc = 1U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc = 1U; - } - vlSelf->main__DOT__i2ci__DOT__cpu_new_pc = 0U; - if ((((((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle))) - & (0xc0U == (0xf0U & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_insn)))) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready)) - & (0xcU == (IData)(vlSelf->main__DOT__i2ci__DOT__half_insn))))) { - vlSelf->main__DOT__i2ci__DOT__cpu_new_pc = 1U; - } - if (vlSelf->main__DOT__i2ci__DOT__i2c_abort) { - vlSelf->main__DOT__i2ci__DOT__cpu_new_pc = 1U; - } - if (vlSelf->main__DOT__i2ci__DOT__bus_jump) { - vlSelf->main__DOT__i2ci__DOT__cpu_new_pc = 1U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk - = (0xffU & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown)) - | (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd))) - ? ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown) - ? 0U : ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90) - ? 0x66U : 0x33U)) - : ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - ? ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90) - ? 0x3cU : 0xfU) : - ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - ? ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90) - ? ((0x200U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - ? 0xf0U : 0xfU) - : ((0x200U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - ? 0xffU : 0U)) - : ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90) - ? (- (IData)((1U - & VL_REDXOR_16( - (0x300U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)))))) - : (- (IData)((1U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 9U))))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__w_sdclk - = (0xffU & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown)) - | (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd))) - ? ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown) - ? 0U : ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90) - ? 0x66U : 0x33U)) - : ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - ? ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90) - ? 0x3cU : 0xfU) : - ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - ? ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90) - ? ((0x200U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - ? 0xf0U : 0xfU) - : ((0x200U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - ? 0xffU : 0U)) - : ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90) - ? (- (IData)((1U - & VL_REDXOR_16( - (0x300U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)))))) - : (- (IData)((1U - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 9U))))))))); - if (vlSelf->main__DOT__u_fan__DOT__tach_reset) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_reset = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_timer = 0x5f5e0ffU; - vlSelf->main__DOT__u_fan__DOT__tach_count - = vlSelf->main__DOT__u_fan__DOT__tach_counter; - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_counter - = (((IData)(vlSelf->main__DOT__u_fan__DOT__ck_tach) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__last_tach))) - ? 1U : 0U); - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_counter - = (0x7ffffffU & (vlSelf->main__DOT__u_fan__DOT__tach_counter - + (((IData)(vlSelf->main__DOT__u_fan__DOT__ck_tach) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__last_tach))) - ? 1U : 0U))); - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_timer - = (0x7ffffffU & (vlSelf->main__DOT__u_fan__DOT__tach_timer - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_reset - = (1U >= vlSelf->main__DOT__u_fan__DOT__tach_timer); - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) { - if (vlSelf->main__DOT__u_fan__DOT__i2cd_valid) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data - = (0x200U | (((IData)(vlSelf->main__DOT__u_fan__DOT__i2cd_last) - << 8U) | (IData)(vlSelf->main__DOT__u_fan__DOT__i2cd_data))); - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data - = (0x1ffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data)); - } - } else { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data - = (0x1ffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data)); - } - if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (0x3000000U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]))) - & (0xf0000000ULL == (0xf0000000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount - = (0xfffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U]); - } - if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err = 1U; - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted = 1U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) { - if (((IData)(((0U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - >> 0x14U))) & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1eU)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err = 0U; - } - if (((IData)(((0U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - >> 0x15U))) & (IData)( - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1eU)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted = 0U; - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted = 0U; - } - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - | (IData)(vlSelf->main__DOT__u_fan__DOT__pp_ms))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait = 0U; - } else { - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - & (0x800U == (0xf00U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait = 1U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait = 0U; - } - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter - = (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown)) - ? 0x300U : (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb - = vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid; - } - if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (0x1000000U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]))) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1dU)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda - = (IData)((0x800U != (0x4800U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U]))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl - = (IData)((0x800U != (0x8800U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U]))); - } else if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl = 1U; - } - if ((0U == vlSelf->main__DOT__u_fan__DOT__trigger_counter)) { - vlSelf->main__DOT__u_fan__DOT__pp_ms = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__trigger_counter = 0x1869fU; - } else { - vlSelf->main__DOT__u_fan__DOT__pp_ms = - (1U >= vlSelf->main__DOT__u_fan__DOT__trigger_counter); - vlSelf->__Vdly__main__DOT__u_fan__DOT__trigger_counter - = (0x1ffffU & (vlSelf->main__DOT__u_fan__DOT__trigger_counter - - (IData)(1U))); - } - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0U] - = (IData)(vlSelf->main__DOT__wbwide_i2cdma_sel); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[1U] - = (IData)((vlSelf->main__DOT__wbwide_i2cdma_sel - >> 0x20U)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[2U] - = vlSelf->main__DOT__wbwide_i2cdma_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[3U] - = vlSelf->main__DOT__wbwide_i2cdma_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[4U] - = vlSelf->main__DOT__wbwide_i2cdma_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[5U] - = vlSelf->main__DOT__wbwide_i2cdma_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[6U] - = vlSelf->main__DOT__wbwide_i2cdma_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[7U] - = vlSelf->main__DOT__wbwide_i2cdma_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[8U] - = vlSelf->main__DOT__wbwide_i2cdma_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[9U] - = vlSelf->main__DOT__wbwide_i2cdma_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xaU] - = vlSelf->main__DOT__wbwide_i2cdma_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xbU] - = vlSelf->main__DOT__wbwide_i2cdma_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xcU] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xdU] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xeU] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xfU] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x10U] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x11U] - = vlSelf->main__DOT__wbwide_i2cdma_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x12U] - = (0x400000U | vlSelf->main__DOT__wbwide_i2cdma_addr); - if (((((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__r_reset)) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__bus_err)) - | ((IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_cyc = 0U; - vlSelf->main__DOT__wbwide_i2cdma_stb = 0U; - } else if (vlSelf->main__DOT__wbwide_i2cdma_cyc) { - if ((1U & (~ (IData)(vlSelf->__VdfgTmp_h503d14d1__0)))) { - vlSelf->main__DOT__wbwide_i2cdma_stb = 0U; - } - if ((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_cyc = 0U; - } - } else if (vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid) { - if (((IData)(vlSelf->main__DOT__u_i2cdma__DOT__r_overflow) - & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__wb_last)))) { - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_cyc = 0U; - vlSelf->main__DOT__wbwide_i2cdma_stb = 0U; - } else { - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_cyc = 1U; - vlSelf->main__DOT__wbwide_i2cdma_stb = 1U; - } - } - if ((1U & ((((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc))) - | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err)) - | ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last = 1U; - } else if (vlSelf->main__DOT__wbwide_wbdown_stall) { - if ((1U & ((~ (IData)(vlSelf->main__DOT__wb32_wbdown_stb)) - | (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last - = (0ULL == (0xfffffffffffffffULL & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel)); - } - } else { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last - = (0ULL == (0xfffffffffffffffULL & (((QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U])) - << 0x20U) - | (QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[0U]))))); - if ((1U & (~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last = 1U; - } - } - vlSelf->main__DOT__swic__DOT__dbg_pre_addr = (3U - & ((IData)(vlSelf->main__DOT__swic__DOT__dbg_addr) - >> 5U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset - [(0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))]; - if ((0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc; - } else if ((0xeU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg - = ((0xffff0000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg) - | ((0x10U & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg - = (0xeb800000U | (0x7fffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg - = ((0xffffffdfU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg) - | (0x20U & ((IData)(vlSelf->main__DOT__swic__DOT__dbg_addr) - << 1U))); - } - vlSelf->main__DOT__swic__DOT__sys_idata = ((4U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? ( - (2U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? vlSelf->main__DOT__swic__DOT__pic_data - : vlSelf->main__DOT__swic__DOT__dmac_data) - : - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? - ((4U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? - ((2U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data) - : - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data)) - : - ((2U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data) - : - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data - : vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data))) - : - ((2U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter - : - (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value)) - : - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? - (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value) - : - (((IData)(vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload) - << 0x1fU) - | vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value))))) - : ( - (2U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? vlSelf->main__DOT__swic__DOT__ctri_data - : vlSelf->main__DOT__swic__DOT__r_wdbus_data) - : - ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__ack_idx)) - ? vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value - : 0U))); - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel = 0U; - vlSelf->main__DOT__swic__DOT__jif_int = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel = 0xffffffffffffffffULL; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step = 0U; - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_set = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel = 0xffffffffffffffffULL; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload = 0U; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload = 0U; - } else { - if (((((IData)(vlSelf->main__DOT__swic__DOT__dmac_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__sys_addr) - >> 1U)))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc - = (1U & (~ (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x12U))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger - = (1U & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1dU)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel - = (0x1fU & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x18U)); - } - } - } - vlSelf->main__DOT__swic__DOT__jif_int = 0U; - if ((((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & (IData)(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_set)) - & (vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter - == vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_when))) { - vlSelf->main__DOT__swic__DOT__jif_int = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_set) - & VL_GTES_III(32, 0U, vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_wb))) { - vlSelf->main__DOT__swic__DOT__jif_int = 1U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag = 0U; - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v - = ((IData)(vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v) - | (0xffU & ((IData)(1U) << (7U & - ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr) - >> 3U))))); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb = 0U; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - ? (5U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr))) - : (6U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr)))); - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line = 0U; - } - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb - = ((~ ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall) - ? (7U == (7U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr)) - : (3U == (3U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - >> 1U))))); - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr - = (0x3fU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr) - + ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - ? 1U : 0U))); - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - = ((0x3ffff8U & vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr) - | (7U & ((IData)(1U) + vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr))); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb - = (1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb))); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl - = (1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb))); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v - = ((~ ((IData)(1U) << (7U & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)))) - & (IData)(vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr = 1U; - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[1U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[2U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[3U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[4U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[5U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[6U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[7U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[8U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[9U] - = vlSelf->main__DOT__swic__DOT__cpu_idata[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xaU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xbU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xcU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xdU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xeU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xfU] - = vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel = 0xffffffffffffffffULL; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag - = (1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err))); - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = 0U; - } - } else { - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = 0U; - } - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - = (0x3fffffU & ((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 2U) : - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr = 0U; - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = 0U; - } - } - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr - = (0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v) - >> (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - >> 3U)))) & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag - == (0x7ffffU - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - >> 3U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[1U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[2U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[3U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[4U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[5U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[6U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[7U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[8U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[9U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xaU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xbU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xcU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xdU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xeU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__in_cache)); - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - = (0x3fffffU & ((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 2U) : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))); - } - if (((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = 0U; - } - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__in_cache - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable)); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = 0U; - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - = (0x3fffffU & ((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 2U) : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl - = (0xffU != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl - = (0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl - = (0xffU != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl - = (0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr - = (0x3fU & ((0x38U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr) - - (IData)(1U))); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 3U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - = (0x3ffff8U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = 2U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - = (0x3fffffU & ((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 2U) : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U))); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl - = (0xffU != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl - = (0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl - = (0xffU != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl - = (0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)); - } - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__CLEAR_DCACHE__DOT__r_clear_dcache) { - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v = 0U; - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie))) - & (0x1eU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step - = (1U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 6U)); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_set) - & VL_LTS_III(32, 0U, vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_wb))) { - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_set = 1U; - } else if (vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_now) { - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_set = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - = ((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) ? ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel)) - >> (3U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)) - : (((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel)) - << 0x3cU) >> (0x3fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel = 0xffffffffffffffffULL; - } - if (vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write) { - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload - = ((vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1fU) & (0U != (0x7fffffffU - & vlSelf->main__DOT__swic__DOT__sys_data))); - } - if (vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write) { - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload - = ((vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1fU) & (0U != (0x7fffffffU - & vlSelf->main__DOT__swic__DOT__sys_data))); - } - if (vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write) { - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload - = ((vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1fU) & (0U != (0x7fffffffU - & vlSelf->main__DOT__swic__DOT__sys_data))); - } - } - vlSelf->main__DOT__swic__DOT__dbg_cpu_status = - ((((IData)(vlSelf->main__DOT__gpio_int) << 0x1bU) - | (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0x1aU) | ((0x2000000U & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0x19U)) - | ((0x1000000U & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0x18U)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0x17U) | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 0x16U) - | (((IData)(vlSelf->main__DOT__emmcscope_int) - << 0x15U) - | ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0) - << 0xcU)))))))) - | (((IData)(vlSelf->main__DOT__swic__DOT__cpu_break) - << 0xbU) | (((IData)(vlSelf->main__DOT__swic__DOT__pic_interrupt) - << 0xaU) | ((0x300U & ((IData)(vlSelf->main__DOT__swic__DOT__cpu_dbg_cc) - << 8U)) - | (((IData)(vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch) - << 5U) | - (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - << 3U) | - ((2U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall)) - << 1U)) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)))))))); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg = 0U; - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_arg; - } else if (((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U)) & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U)) & (0x10000U - == (0x70000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])))) { - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg - = ((0xffffff00U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg) - | (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg - = ((0xffff00ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg) - | (0xff00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1aU)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg - = ((0xff00ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg) - | (0xff0000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1bU)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg - = ((0xffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg) - | (0xff000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])); - } - } - if ((1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_id = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_arg = 0U; - } else { - if ((8U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_id - = (0x3fU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_arg - = ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - ? 0U : (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - >> 8U))); - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90 = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90 - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xeU)); - if ((0x100U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90 = 1U; - } - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg = 0U; - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg; - } else if (((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U)) & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U)) & (1U == (7U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))) { - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg - = ((0xffffff00U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg) - | (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg - = ((0xffff00ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg) - | (0xff00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x22U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg - = ((0xff00ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg) - | (0xff0000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])); - } - if ((1U & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x23U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg - = ((0xffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg) - | (0xff000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])); - } - } - if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg = 0U; - } else { - if ((8U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id - = (0x3fU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg - = ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - ? 0U : (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - >> 8U))); - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90 = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90 - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xeU)); - if ((0x100U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90 = 1U; - } - } - if ((1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg = 0xffffffffU; - if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w; - } - } - } else if (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - & (1U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - & (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg = 0xffffffffU; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - ? vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b - : vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a); - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data = 0xffffffffU; - } else { - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed))) - ? 2U : ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - & (1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed))) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)))) - ? 1U : 0U)); - } - if ((2U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - if ((1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data = 0xffffffffU; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 0U; - } - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 1U; - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 3U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - = ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - ? vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - : (0xffffU | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg) - << 0x10U))) - : ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - ? vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - : (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x20U))) - : ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width)) - ? ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) - ? vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - : vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U]) - : vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U]))); - } - } else if ((1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 1U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data; - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 2U; - } - } - } else { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - ? vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - : 0xffffffffU); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 0U; - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last) - ? 2U : 1U); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = 1U; - } - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half - = (1U & ((IData)(vlSelf->i_reset) | ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown)) - | (0U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd))) - | ((1U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - | ((2U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - ? - ((0x200U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - ? 1U - : 2U) - : - (0x100U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter))))))); - if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err = 1U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err - = (1U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode)); - } - if ((1U & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_err = 0U; - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_err - = (1U & (IData)(((((0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err)) - | (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err))) - | (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err))) - | (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err))))); - } - if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err = 1U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err - = (1U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode)); - } - if ((1U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err = 0U; - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err - = (1U & (IData)(((((0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err)) - | (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err))) - | (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err))) - | (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err))))); - } - vlSelf->main__DOT__console__DOT____VdfgTmp_h60af6732__0 - = (1U & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)) - | (IData)(vlSelf->main__DOT__w_console_busy))); - vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6 - = (1U & ((~ (IData)(vlSelf->main__DOT__w_console_busy)) - & (~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__ps_full) - & (IData)(vlSelf->main__DOT__genbus__DOT__wbu_tx_stb)); - if (vlSelf->__Vdlyvset__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl[vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0] - = vlSelf->__Vdlyvval__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0; - } - vlSelf->main__DOT__wbu_xbar__DOT__s_data[0U] = - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data[0xfU]; - vlSelf->main__DOT__wbu_xbar__DOT__s_data[1U] = vlSelf->main__DOT__wbu_zip_idata; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched; - vlSelf->main__DOT__wbu_xbar__DOT__mnearfull = vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__mnearfull; - vlSelf->main__DOT__wbu_xbar__DOT__m_addr[0U] = vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc - = vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last; - vlSelf->main__DOT__swic__DOT__cmd_read_ack = vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read_ack; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull - = vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull; - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc))) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->main__DOT__wb32_xbar__DOT__mfull = 0U; - } else if ((1U == ((((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stall))) - << 1U) | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->main__DOT__wb32_xbar__DOT__mfull = 0U; - } else if ((2U == ((((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stall))) - << 1U) | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)))) { - vlSelf->main__DOT__wb32_xbar__DOT__mfull = vlSelf->main__DOT__wb32_xbar__DOT__mnearfull; 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- main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x200000U & (0x200000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 2U)); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr; - vlSelf->main__DOT__i2cscopei__DOT__raddr = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__raddr; - vlSelf->main__DOT__i2cscopei__DOT__waddr = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__waddr; - vlSelf->main__DOT__emmcscopei__DOT__raddr = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__raddr; - vlSelf->main__DOT__emmcscopei__DOT__waddr = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__waddr; - vlSelf->main__DOT__sdioscopei__DOT__raddr = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__raddr; - vlSelf->main__DOT__sdioscopei__DOT__waddr = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__waddr; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x80000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x100000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x200000U & (0x200000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 2U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge - = ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck)) - & (IData)(vlSelf->o_emmc_clk)); - vlSelf->main__DOT__u_fan__DOT__tach_reset = vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_reset; - vlSelf->main__DOT__u_fan__DOT__tach_counter = vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_counter; - vlSelf->main__DOT__u_fan__DOT__tach_timer = vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_timer; - vlSelf->main__DOT__u_fan__DOT__temp_tmp = vlSelf->__Vdly__main__DOT__u_fan__DOT__temp_tmp; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted; - if (vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U]; - } else { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data[0x12U]; - } - vlSelf->main__DOT__u_i2cdma__DOT__r_overflow = vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__r_overflow; - vlSelf->__VdfgTmp_h503d14d1__0 = (7U & (~ ((4U - & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - << 2U)) - | ((2U - & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)) - << 1U)) - | (1U - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))))); - vlSelf->main__DOT__wbwide_i2cdma_cyc = vlSelf->__Vdly__main__DOT__wbwide_i2cdma_cyc; - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0; - } - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data - = vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data - = vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data - = vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data - = vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data - = vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data - = vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data - = vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data; - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data - = vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data; - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value - = vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value; - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value - = vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value; - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value - = vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value; - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value - = vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_value; - vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0 - = (((IData)(vlSelf->main__DOT__spio_int) << 3U) - | ((4U & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - >> 3U)) | ((2U & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - >> 4U)) | (IData)(vlSelf->main__DOT__sdcard_int)))); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow - = vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_underflow; - vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow - = vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U]; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U]; - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read - = ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow)) - & (IData)(vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6)); - if (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_bits - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_bits = 0x40U; - } - vlSelf->main__DOT__i2cscopei__DOT__imm_adr = (1U - & ((~ - ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U)) - | (~ - (((IData)(vlSelf->main__DOT__i2cscopei__DOT__new_data) - | (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_force_write)) - | (IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stopped))))); - vlSelf->main__DOT__emmcscopei__DOT__imm_adr = (1U - & ((~ - ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U)) - | (~ - (((IData)(vlSelf->main__DOT__emmcscopei__DOT__new_data) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_force_write)) - | (IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stopped))))); - vlSelf->main__DOT__sdioscopei__DOT__imm_adr = (1U - & ((~ - ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U)) - | (~ - (((IData)(vlSelf->main__DOT__sdioscopei__DOT__new_data) - | (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_force_write)) - | (IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stopped))))); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data - = (0xfULL | (((QData)((IData)(vlSelf->main__DOT__wbu_we)) - << 0x3fU) | (((QData)((IData)( - (0x7ffffffU - & vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr))) - << 0x24U) | ((QData)((IData)(vlSelf->main__DOT__wbu_data)) - << 4U)))); - if ((1U & ((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__wbu_cyc))))) { - vlSelf->main__DOT__wbu_xbar__DOT__mgrant = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available) { - vlSelf->main__DOT__wbu_xbar__DOT__mgrant = 1U; - } else if (vlSelf->main__DOT__wbu_xbar__DOT__m_stb) { - vlSelf->main__DOT__wbu_xbar__DOT__mgrant = 0U; - } - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__maddr - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch - = ((~ (IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset)) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table) - & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch) - & (0xe00000000ULL == (0xe00000000ULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word)))); - if ((1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__a_addrword - = ((2U != (0xfU & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 0x20U)))) - ? vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - : ((8U & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck)) - ? ((4U & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck)) - ? ((2U & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck)) - ? ((1U & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck)) - ? (0x300000000ULL | (QData)((IData)( - (0x3f000000U - & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword) - << 0x18U))))) - : (0x340000000ULL | (QData)((IData)( - (0x3ffc0000U - & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword) - << 0x12U)))))) - : (0x380000000ULL | (QData)((IData)( - (0x3ffff000U - & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword) - << 0xcU)))))) - : (0x3c0000000ULL | (QData)((IData)( - (0x3fffffc0U - & ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword) - << 6U)))))) - : vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword)); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel - = ((0x3fU >= (0x1ffffffcU & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift) - << 2U))) ? (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel - << - (0x1ffffffcU - & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift) - << 2U))) - : 0ULL); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data - = (((QData)((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_we)) - << 0x2cU) | (((QData)((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr)) - << 0x24U) | (((QData)((IData)( - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data[0xfU])) - << 4U) | (QData)((IData)( - (0xfU - & (IData)( - (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel - >> 0x3cU)))))))); - vlSelf->main__DOT__wbwide_wbu_arbiter_cyc = vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT__request[3U] - = (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid)) - ? (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__decoded) - : 0U); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc - = ((2U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)) - | ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant) - & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U])))); - if ((1U & ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_err)))) { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc - = (2U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)); - } - vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc - = ((1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)) - | (0xfffffffeU & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant) - & (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U])) << 1U)))); - if ((1U & ((IData)(vlSelf->i_reset) | ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_err) - >> 1U)))) { - vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc - = (1U & (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__rx_valid - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset)) - & ((1U != (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd))) - & ((2U == (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd))) - ? (0xfU == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill)) - : (0x10U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill))))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid) - ? (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_word) - : (IData)(vlSelf->main__DOT__u_fan__DOT__mem_data)); - } - vlSelf->main__DOT__swic__DOT__dbg_cyc = (1U & ( - (~ - ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc)))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__no_dbg_err)))); - vlSelf->main__DOT__swic__DOT__dbg_pre_ack = ((~ - ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc)))) - & (((IData)(vlSelf->main__DOT__swic__DOT__dbg_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stall))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_cpu_read)))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)); - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)))) { - vlSelf->main__DOT__i2ci__DOT__pf_insn = (0xffU - & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid) - ? - ((vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU] - << 8U) - | (vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU] - >> 0x18U)) - : - ((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid) - ? - ((vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0xfU] - << 8U) - | (vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0xfU] - >> 0x18U)) - : - ((vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xfU] - << 8U) - | (vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xfU] - >> 0x18U))))); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data - = ((~ (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data - = ((~ (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb)); - vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant) - & (((0xfffff800U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_ddr3_phy_ack) - << 0xbU))) | ((0xfffffc00U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__r_cfg_ack) - << 0xaU))) - | ((0xfffffe00U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__r_wb32_sio_ack) - << 9U))) - | ((0xffffff00U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_sdcard_ack) - << 8U))) - | ((0xffffff80U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_fan_ack) - << 7U))) - | ((0xffffffc0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_emmc_ack) - << 6U))) - | ((0xffffffe0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_uart_ack) - << 5U))) - | ((0xfffffff0U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_i2cdma_ack) - << 4U))) - | ((0xfffffff8U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wb32_i2cs_ack) - << 3U))) - | ((0xfffffffcU - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack) - << 2U))) - | ((0xfffffffeU - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack))))))))))))) - >> vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U])); - if ((0x1000U & vlSelf->main__DOT__wb32_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack = 0U; - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc))) - | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack = 0U; - } - vlSelf->main__DOT__wbu_xbar__DOT__m_data[0U] = (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> 4U)); - vlSelf->main__DOT__wbu_xbar__DOT__m_sel[0U] = (0xfU - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data)); - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid = 1U; - } else if ((((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort))) - & ((7U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr) - >> 3U)) == (7U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid = 0U; - } - vlSelf->main__DOT__swic__DOT__cpu_we = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags - [(7U & ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending)))) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U) : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)))]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__CLEAR_DCACHE__DOT__r_clear_dcache - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (((IData)(vlSelf->main__DOT__swic__DOT__cmd_clear_cache) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 0xfU)))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall))))) { - if ((0U == (2U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - } else if ((2U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U) | (0xffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)); - } else if ((3U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU] - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U) | ((0xff0000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U)) - | ((0xff00U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 8U)) - | (0xffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)))); - } - } - if (((((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_abort)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__bus_manual))) { - vlSelf->main__DOT__i2ci__DOT__half_valid = 0U; - } else if (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__next_valid))) { - vlSelf->main__DOT__i2ci__DOT__half_valid = 0U; - if (((((3U != (0xfU & ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - >> 4U))) & (0xdU != - (0xfU & - ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - >> 4U)))) - & (0U != (0xfU & (IData)(vlSelf->main__DOT__i2ci__DOT__next_insn)))) - & (9U != (0xfU & ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - >> 4U))))) { - vlSelf->main__DOT__i2ci__DOT__half_valid = 1U; - } - } else if (vlSelf->main__DOT__i2ci__DOT__half_ready) { - vlSelf->main__DOT__i2ci__DOT__half_valid = 0U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor - = (0U == vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr); - } - if (vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN) { - if (((((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckedge) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_stretch))) - & (8U == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir)))) { - vlSelf->main__DOT__i2c_valid = 1U; - } else if (vlSelf->main__DOT__i2c_ready) { - vlSelf->main__DOT__i2c_valid = 0U; - } - } else { - vlSelf->main__DOT__i2c_valid = 0U; - } - if (vlSelf->main__DOT__i2ci__DOT__i2c_ckedge) { - if ((8U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - if ((4U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - if ((2U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - if ((1U & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy)))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0U; - } - } else if ((1U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - if ((1U & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy)))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0U; - } - } else if ((1U & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_stretch)))) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 1U; - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda)) - | (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl))))) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0xaU; - } - } - } else if ((2U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - if ((1U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_stretch)))) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0xcU; - if (((IData)(vlSelf->main__DOT__i2ci__DOT__w_sda) - != (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda))) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0xaU; - } - } - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - if ((((~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0U; - } - } - } else if ((1U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda))))) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 3U; - } - } else { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - if (vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state - = (((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda)) - ? 9U : 2U); - } - } - } else if ((4U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - if ((2U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - if ((1U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda - = (1U & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir) - | (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack)))); - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 8U; - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda - = (1U & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir) - | (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack)))); - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - if ((1U & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)))) { - if (vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir) { - if (vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 7U; - } - } else if (((IData)(vlSelf->main__DOT__i2ci__DOT__w_sda) - != (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 7U; - } - } - if (vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 6U; - } - } - } else if ((1U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - if (vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg - = ((0xfeU & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg) - << 1U)) | (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda)); - if ((0U < (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits - = (7U & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits) - - (IData)(1U))); - } - if (((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir) - & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda) - != (1U & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg) - >> 7U))))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0xaU; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state - = ((0U == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits)) - ? 6U : 4U); - } - } else { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - } - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda - = (1U & (((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg) - >> 7U) | (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir)))); - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - if (((IData)(vlSelf->main__DOT__i2ci__DOT__w_sda) - == (1U & (((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg) - >> 7U) | (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir)))))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 5U; - } - if (vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 4U; - } - } - } else if ((2U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - if ((1U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - if (vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0U; - } - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg - = (0xffU & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__dir = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - if (((IData)(vlSelf->main__DOT__i2ci__DOT__s_tvalid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__insn_ready))) { - if ((0x400U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - if ((0x200U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - if ((0x100U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 4U; - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 4U; - } - } else if ((0x100U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 4U; - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 4U; - } - } else if ((0x200U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - if ((0x100U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__dir = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 4U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg - = (0xffU & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)); - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 3U; - } - } else if ((0x100U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0xbU; - } - } - } - } else if ((1U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state - = ((4U & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits)) - ? 4U : 2U); - vlSelf->main__DOT__i2ci__DOT__w_scl = 0U; - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg - = (0xffU & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__dir = 0U; - if (((IData)(vlSelf->main__DOT__i2ci__DOT__s_tvalid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__insn_ready))) { - if ((0x400U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - if ((0x200U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - if ((0x100U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 1U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - } - } else if ((0x100U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack = 0U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 1U; - } else { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - } - } else if ((0x200U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - if ((0x100U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__dir = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg - = (0xffU & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)); - } - } else if ((0x100U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 0U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 1U; - } - } - } - } - if ((1U & (~ (IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)))) { - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = 1U; - vlSelf->main__DOT__i2ci__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = 0U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc); - } - vlSelf->main__DOT__u_fan__DOT__last_tach = vlSelf->main__DOT__u_fan__DOT__ck_tach; - vlSelf->main__DOT__u_fan__DOT__i2cd_data = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg; - vlSelf->main__DOT__u_fan__DOT__i2cd_valid = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN) - & ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch))) - & (8U - == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir)))); - vlSelf->main__DOT__u_fan__DOT__i2cd_last = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte; - vlSelf->o_fan_sda = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda; - vlSelf->o_fan_scl = vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted)); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid = 0U; - } else if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid = 0U; - } else if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle) - | ((3U != (0xfU & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - >> 4U))) & (0xdU - != (0xfU - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - >> 4U))))); - } else if (((((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid)) - | (3U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn))) - | (0xdU == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn))) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid = 0U; - } - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x80000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x100000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x200000U & (0x200000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 2U)); - vlSelf->main__DOT__swic__DOT__dc_stall = (IData)( - (((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 2U) - | (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT__request[0U] - = (((IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)) - ? (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded) - : 0U); - if (vlSelf->main__DOT__u_i2cdma__DOT__r_reset) { - vlSelf->main__DOT__u_i2cdma__DOT__wb_last = 1U; - } else if (((IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid) - & (IData)(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready))) { - vlSelf->main__DOT__u_i2cdma__DOT__wb_last = - (1U & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data) - >> 8U)); - } - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data - = (((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last) - << 4U) | (0xfU & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr))); - if (vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset) { - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } else if ((((IData)(vlSelf->main__DOT__wb32_wbdown_stb) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready)) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset - [(0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset - [(0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))]; - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stb)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stall))))) { - vlSelf->main__DOT__swic__DOT__dbg_addr = ((IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb) - ? (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_addr) - : (IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr)); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__wdbus_int) - | (IData)(vlSelf->main__DOT__swic__DOT__cpu_err))) { - vlSelf->main__DOT__swic__DOT__r_wdbus_data - = vlSelf->main__DOT__wbwide_zip_addr; - } - if (vlSelf->main__DOT__swic__DOT__sys_stb) { - vlSelf->main__DOT__swic__DOT__ack_idx = vlSelf->main__DOT__swic__DOT__w_ack_idx; - } - vlSelf->main__DOT__swic__DOT__pic_data = 0U; - vlSelf->main__DOT__swic__DOT__pic_data = (((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie) - << 0x1fU) - | (((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable) - << 0x10U) - | (((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any) - << 0xfU) - | (IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state)))); - vlSelf->main__DOT__swic__DOT__ctri_data = 0U; - vlSelf->main__DOT__swic__DOT__ctri_data = (((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie) - << 0x1fU) - | (((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable) - << 0x10U) - | (((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any) - << 0xfU) - | (IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state)))); - vlSelf->main__DOT__swic__DOT__dmac_data = 0U; - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))) { - vlSelf->main__DOT__swic__DOT__dmac_data = ( - (0xf0000000U - & vlSelf->main__DOT__swic__DOT__dmac_data) - | ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)) - ? - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length) - : - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy) - ? - (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr - << 6U) - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst))); - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))) { - vlSelf->main__DOT__swic__DOT__dmac_data = ( - (0xf0000000U - & vlSelf->main__DOT__swic__DOT__dmac_data) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy) - ? - (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - << 6U) - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src)); - } else { - vlSelf->main__DOT__swic__DOT__dmac_data = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg; - } - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read - = ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - & (IData)(vlSelf->main__DOT__console__DOT__rxf_wb_read)); - vlSelf->main__DOT__console__DOT__rxf_status = (0x6000U - | (((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill) - << 2U) - | ((2U - & ((IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill) - >> 4U)) - | (1U - & (~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)))))); - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write - = ((IData)(vlSelf->main__DOT__console__DOT__txf_wb_write) - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - | (IData)(vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6))); - vlSelf->__VdfgTmp_ha46ae6a3__0 = ((2U & ((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill) - >> 4U)) - | (1U & (~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)))); - vlSelf->main__DOT__gpio_int = ((IData)(vlSelf->main__DOT__gpioi__DOT__q_gpio) - != (IData)(vlSelf->main__DOT__gpioi__DOT__r_gpio)); - vlSelf->main__DOT__gpioi__DOT__r_gpio = vlSelf->main__DOT__gpioi__DOT__q_gpio; - vlSelf->main__DOT__swic__DOT__cpu_dbg_cc = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err) - << 2U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep))); - __Vtableidx2 = (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done) - << 8U) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - << 7U) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - << 6U) | - (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent) - << 5U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - << 4U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - << 3U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done) - << 2U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset) - << 1U) - | (IData)(vlSelf->i_reset))))))))); - vlSelf->main__DOT__emmc_int = Vmain__ConstPool__TABLE_h40cc9f5d_0 - [__Vtableidx2]; - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr = 0U; - } else if ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr - = vlSelf->main__DOT__u_emmc__DOT__cfg_ddr; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data - = ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((0x1000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((0x800U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((0x20U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | ((0x10U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | ((8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U)) - | (1U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data)))))))))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xfU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xeU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xdU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xcU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xbU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xaU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 9U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 8U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data - = ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((0x2000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((0x1000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((0x800U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((0x20U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((0x10U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | ((8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))))))))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xfU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xeU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xdU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xcU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xbU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 0xaU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 9U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 8U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__36__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__35__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffffff0U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xeU)) | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 1U))) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xfU)) | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xffffff0fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xcU)) | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 3U))) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xdU)) | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 2U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffff0ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xaU)) | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 5U))) - | ((0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xbU)) | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 4U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xffff0fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 8U)) | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 7U))) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 9U)) | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 6U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfff0ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 6U)) | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 9U))) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 7U)) | (0x10000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 8U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xff0fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 4U)) | (0x400000U & - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xbU))) - | ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 5U)) | (0x100000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xaU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xf0ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 2U)) | (0x4000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xdU))) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 3U)) | (0x1000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xcU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xfU))) | ((0x20000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 1U)) - | (0x10000000U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xeU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffeULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | (IData)((IData)((1U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffeffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 1U))))) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffeffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 2U))))) - << 0x20U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffeffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 3U))))) - << 0x30U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffdULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 4U))))) - << 1U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffdffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 5U))))) - << 0x11U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffdffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 6U))))) - << 0x21U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffdffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 7U))))) - << 0x31U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffbULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 8U))))) - << 2U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffbffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 9U))))) - << 0x12U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffbffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xaU))))) - << 0x22U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffbffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xbU))))) - << 0x32U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffff7ULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xcU))))) - << 3U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffff7ffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xdU))))) - << 0x13U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffff7ffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xeU))))) - << 0x23U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfff7ffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xfU))))) - << 0x33U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffefULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x10U))))) - << 4U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffefffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x11U))))) - << 0x14U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffefffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x12U))))) - << 0x24U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffefffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x13U))))) - << 0x34U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffdfULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x14U))))) - << 5U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffdfffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x15U))))) - << 0x15U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffdfffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x16U))))) - << 0x25U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffdfffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x17U))))) - << 0x35U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffbfULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x18U))))) - << 6U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffbfffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x19U))))) - << 0x16U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffbfffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1aU))))) - << 0x26U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffbfffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1bU))))) - << 0x36U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffff7fULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1cU))))) - << 7U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffff7fffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1dU))))) - << 0x17U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffff7fffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1eU))))) - << 0x27U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xff7fffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1fU))))) - << 0x37U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffeffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x20U))))) - << 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffeffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x21U))))) - << 0x18U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffeffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x22U))))) - << 0x28U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfeffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x23U))))) - << 0x38U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffdffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x24U))))) - << 9U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffdffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x25U))))) - << 0x19U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffdffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x26U))))) - << 0x29U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfdffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x27U))))) - << 0x39U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffbffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x28U))))) - << 0xaU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffbffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x29U))))) - << 0x1aU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffbffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2aU))))) - << 0x2aU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfbffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2bU))))) - << 0x3aU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffff7ffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2cU))))) - << 0xbU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffff7ffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2dU))))) - << 0x1bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffff7ffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2eU))))) - << 0x2bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xf7ffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2fU))))) - << 0x3bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffefffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x30U))))) - << 0xcU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffefffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x31U))))) - << 0x1cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffefffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x32U))))) - << 0x2cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xefffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x33U))))) - << 0x3cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffdfffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x34U))))) - << 0xdU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffdfffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x35U))))) - << 0x1dU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffdfffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x36U))))) - << 0x2dU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xdfffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x37U))))) - << 0x3dU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffbfffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x38U))))) - << 0xeU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffbfffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x39U))))) - << 0x1eU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffbfffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3aU))))) - << 0x2eU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xbfffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3bU))))) - << 0x3eU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffff7fffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3cU))))) - << 0xfU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffff7fffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3dU))))) - << 0x1fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffff7fffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3eU))))) - << 0x2fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0x7fffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3fU))))) - << 0x3fU)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | ((0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | (1U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data)))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior - = (0xffffU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffffffff0000ULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | (IData)((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | ((0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) - | ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x10U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffff0000ffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout)) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | ((0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) - | ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x20U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffff0000ffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout)) - << 0x20U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | ((0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) - | ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) - | ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((4U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((2U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U))))))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x30U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__38__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__37__Vfuncout)) - << 0x30U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffffff8ULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | (IData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x20U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x10U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffffff7ULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x30U))))) - << 3U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffffff8fULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x21U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x11U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 1U))))))) - << 4U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffffff7fULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x31U))))) - << 7U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffff8ffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x22U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x12U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 2U))))))) - << 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffff7ffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x32U))))) - << 0xbU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffff8fffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x23U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x13U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 3U))))))) - << 0xcU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffff7fffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x33U))))) - << 0xfU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffff8ffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x24U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x14U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 4U))))))) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffff7ffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x34U))))) - << 0x13U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffff8fffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x25U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x15U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 5U))))))) - << 0x14U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffff7fffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x35U))))) - << 0x17U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffff8ffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x26U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x16U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 6U))))))) - << 0x18U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffff7ffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x36U))))) - << 0x1bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffff8fffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x27U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x17U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 7U))))))) - << 0x1cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffff7fffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x37U))))) - << 0x1fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffff8ffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x28U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x18U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 8U))))))) - << 0x20U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffff7ffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x38U))))) - << 0x23U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffff8fffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x29U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x19U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 9U))))))) - << 0x24U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffff7fffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x39U))))) - << 0x27U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffff8ffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2aU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1aU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xaU))))))) - << 0x28U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffff7ffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3aU))))) - << 0x2bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffff8fffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2bU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1bU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xbU))))))) - << 0x2cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffff7fffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3bU))))) - << 0x2fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfff8ffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2cU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1cU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xcU))))))) - << 0x30U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfff7ffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3cU))))) - << 0x33U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xff8fffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2dU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1dU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xdU))))))) - << 0x34U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xff7fffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3dU))))) - << 0x37U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xf8ffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2eU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1eU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xeU))))))) - << 0x38U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xf7ffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3eU))))) - << 0x3bU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0x8fffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2fU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1fU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xfU))))))) - << 0x3cU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0x7fffffffffffffffULL & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3fU))))) - << 0x3fU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x12U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x14U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x8000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x14U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x12U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x10U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U])); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) | (1U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data)))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) | (1U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x19U)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1aU)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1bU)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data - = ((8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1cU)) | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | - ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U))))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__40__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__39__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 2U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xfU)) | - (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U])))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xbU)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 4U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffff3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 9U)) | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 6U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 9U)) | ( - (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 8U)) - | (0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 4U)) | - ((0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xbU)) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffff3fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 2U)) | - (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xdU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x10U)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 1U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xeU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 3U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x12U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 1U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xff3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 5U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x14U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x17U)) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 6U)) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xaU)) - | ((0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x19U)) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0x3fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xcU)) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x1bU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 2U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x13U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 4U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xfU)) | - ((0x10U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffff3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xdU)) | - (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 2U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 5U)) | ( - (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xcU)) - | (0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 3U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 8U)) | - ((0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 7U)) | - (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xaU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffff3fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 6U)) | - (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 9U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xcU)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 5U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xaU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 1U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xeU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 3U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xff3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 1U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x10U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x13U)) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 2U)) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 6U)) - | ((0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x15U)) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0x3fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 8U)) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x17U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 6U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x17U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 8U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x13U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 4U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffff3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0x11U)) | - (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 2U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 1U)) | ( - (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x10U)) - | (0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 1U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xcU)) - | ((0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 3U)) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xeU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffff3fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xaU)) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 5U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 8U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 9U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 5U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xaU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xff3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 3U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xcU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xfU)) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 2U)) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 2U)) - | ((0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x11U)) - | (0x8000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0x3fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 4U)) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x13U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xaU)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x1bU)) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xcU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x17U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 8U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x19U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffff3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0x15U)) | - (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 6U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 3U)) | ( - (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x14U)) - | (0x100U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 5U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x10U)) - | ((0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 1U)) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x12U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffff3fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xeU)) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 1U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 4U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xdU)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 9U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 6U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xbU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xff3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 7U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 8U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xbU)) - | ((0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 6U)) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 9U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 2U)) - | ((0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xdU)) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0x3fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xc0000000U & ((0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xfU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffeU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffeffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffdU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x1dU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffdffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (4U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffbU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffbffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffff7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffefU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffefffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x200000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffdfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffdfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffbfU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffbfffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x800000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffff7fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xff7fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x100U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffeffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfeffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x2000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffdffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfdffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x400U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffbffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfbffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x8000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x1000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffefffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xefffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffdfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xdfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x1dU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x1bU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x19U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x17U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x15U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x13U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x11U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffbfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x4000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U])); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xbfffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U])); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 2U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 3U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 4U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 5U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 6U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 7U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 8U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 9U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x19U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1aU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1bU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1cU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1dU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - = ((0xffff0000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data - = ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0x1eU)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior - = (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - >> 0x10U); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__prior; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__i_crc_data)); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__prior) - << 1U))); - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__42__Vfuncout; - __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout - = __Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - = ((0xffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | ((IData)(__Vfunc_main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__41__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 2U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xfU)) | - (1U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U])))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xbU)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 4U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xdU)))))); -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__2__Slow.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__2__Slow.cpp deleted file mode 100644 index c6482b8..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__2__Slow.cpp +++ /dev/null @@ -1,5095 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -VL_ATTR_COLD void Vmain___024root___stl_sequent__TOP__2(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___stl_sequent__TOP__2\n"); ); - // Init - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0; - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0; - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 = 0; - CData/*0:0*/ main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0; - main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0 = 0; - CData/*0:0*/ main__DOT__swic__DOT____VdfgTmp_hcb574c13__0; - main__DOT__swic__DOT____VdfgTmp_hcb574c13__0 = 0; - VlWide<4>/*127:0*/ __Vtemp_hd96f9696__0; - VlWide<4>/*127:0*/ __Vtemp_h6aa6ab78__0; - // Body - if ((0x38U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x80U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x39U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x40U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x20U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x10U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (8U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (4U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (2U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (1U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[2U] - = (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[3U] - = (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x20U)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last)))) { - VL_SHIFTR_WWI(128,128,6, __Vtemp_h6aa6ab78__0, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel, - (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)); - __Vtemp_hd96f9696__0[1U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[1U] - | __Vtemp_h6aa6ab78__0[1U]); - __Vtemp_hd96f9696__0[2U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[2U] - | __Vtemp_h6aa6ab78__0[2U]); - __Vtemp_hd96f9696__0[3U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[3U] - | __Vtemp_h6aa6ab78__0[3U]); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[0U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[0U] - | __Vtemp_h6aa6ab78__0[0U]); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[1U] - = __Vtemp_hd96f9696__0[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[2U] - = __Vtemp_hd96f9696__0[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[3U] - = __Vtemp_hd96f9696__0[3U]; - } - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x80000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x100000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x200000U & (0x200000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 2U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xffeU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xffdU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 1U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xffbU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 2U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 3U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xff7U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 3U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 4U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xfefU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 4U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 5U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xfdfU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 5U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 6U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xfbfU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 6U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 7U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xf7fU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 7U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 8U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xeffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 8U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 9U)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xdffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 9U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 0xaU)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0xbffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 0xaU)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 0xbU)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((0x7ffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0) - << 0xbU)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd - = ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty)) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - vlSelf->main__DOT__wbwide_wbdown_stall = (1U & - ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first) - | (((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full))) - | ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last)) - | ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null)))))); - vlSelf->main__DOT__swic__DOT__dbg_cpu_read = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h9a48e2a3__0) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_we)) - & (0x20U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))))); - vlSelf->main__DOT__swic__DOT__dbg_cpu_write = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h9a48e2a3__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__dbg_we) - & (IData)( - ((0x20U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))) - & (0xfU - == (IData)(vlSelf->main__DOT__swic__DOT__dbg_sel)))))); - vlSelf->main__DOT__swic__DOT__dmac_stb = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_dmac)); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchdog__i_wb_stb - = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_watchdog)); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write - = (((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_apic)) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write - = (((IData)(vlSelf->main__DOT__swic__DOT__sys_cyc) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_pic))) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0 = - ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_timer)); - vlSelf->main__DOT__swic__DOT__w_ack_idx = 0U; - if (vlSelf->main__DOT__swic__DOT__sel_watchdog) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (1U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_bus_watchdog) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (2U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_apic) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (3U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_timer) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (4U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__actr_ack) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (5U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_dmac) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (6U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_pic) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = 7U; - } - main__DOT__swic__DOT____VdfgTmp_hcb574c13__0 = - ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__actr_ack)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | (~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - == (0xeU | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled - = (1U & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we)) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending) - >> 4U)))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__wbwide_zip_stb))); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])); - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]))); - if ((1U & (((~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]]) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]))); - if ((1U & (((~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]] >> 1U)) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]))); - if ((1U & (((~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]] >> 2U)) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 0U; - } - if (vlSelf->i_reset) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__requested[0U] - = (6U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U]); - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = ((6U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]) | (IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0)); - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U] | ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = (1U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = ((6U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]) | (IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0)); - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U] | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = (1U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = ((6U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]) | (IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0)); - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U] | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = (1U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]); - } - vlSelf->main__DOT__wbwide_xbar__DOT__requested[0U] - = (5U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U]); - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = ((5U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 1U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 1U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U] >> 1U) | ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = (2U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = ((5U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 1U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 1U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U] >> 1U) | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = (2U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = ((5U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 1U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 1U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U] >> 1U) | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = (2U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]); - } - vlSelf->main__DOT__wbwide_xbar__DOT__requested[0U] - = (3U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U]); - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = ((3U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 2U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 2U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U] >> 2U) | ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = (4U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = ((3U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 2U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 2U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U] >> 2U) | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = (4U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = ((3U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 2U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 2U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U] >> 2U) | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = (4U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]); 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- } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); 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- } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); 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- } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); 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- } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); 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- } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); 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- } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant = 0U; - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant = 0U; - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant = 0U; - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 3U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = - ((0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)) - | (1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U] >> 3U) | ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]))) - ? ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U])) : (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))))); - if ((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = - ((0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)) - | (2U & ((0x3ffffffeU & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U] >> 2U)) | (( - (1U - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) - & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]))) - ? - (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 1U) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U])) - : - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 1U)) - << 1U)))); - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = - ((0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)) - | (4U & ((0x7ffffffcU & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U] >> 1U)) | (( - (1U - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U) - & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]))) - ? - (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 2U) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U])) - : - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 2U)) - << 2U)))); - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = - ((7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)) - | (8U & ((0xfffffff8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U]) | (((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U) & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]))) - ? (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 3U) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U])) : - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 3U)) << 3U)))); - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)); - } - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write - = ((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_a__i_wb_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write - = ((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_b__i_wb_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write - = ((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_c__i_wb_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce) - & ((5U == (7U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U))) | (0xcU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc))))); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = 0U; - if ((0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]; - } else { - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex)); - } - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = 3U; - } - } - if ((0U != (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__iN = 4U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = 0U; - if ((0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]; - } else { - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex)); - } - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = 3U; - } - } - if ((0U != (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__iN = 4U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = 0U; - if ((0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]; - } else { - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex)); - } - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = 3U; - } - } - if ((0U != (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__iN = 4U; - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - & (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall - = (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 1U) & (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall - = (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 2U) & (IData)(vlSelf->main__DOT__wbwide_zip_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall - = (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 3U) & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall - = (((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - & ((IData)(vlSelf->main__DOT__swic__DOT__cmd_halt) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U))) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)) - & (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI)) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - == (0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR)) - | (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - | ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg) - == (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU - == (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U)))) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)))) - | (((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F) - >> 3U)) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA) - & (IData)( - ((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))) - & ((0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - & (IData)( - ((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))) - & ((0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))))) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR) - & (IData)(((0xeU == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - != (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U))))))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write)))))))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid)); - vlSelf->main__DOT__swic__DOT__cpu_op_stall = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc - = ((0x20U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - ? 5U : ((0x40U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - ? 6U : 7U)); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) { - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rA)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 4U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 4U; - } - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc - = ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 5U) & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB)) - ? 4U : 5U); - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc = 6U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 0U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 2U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 3U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 4U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 5U; - } -} - -VL_ATTR_COLD void Vmain___024root___stl_sequent__TOP__0(Vmain___024root* vlSelf); -VL_ATTR_COLD void Vmain___024root___stl_sequent__TOP__1(Vmain___024root* vlSelf); - -VL_ATTR_COLD void Vmain___024root___eval_stl(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_stl\n"); ); - // Body - if ((1ULL & vlSelf->__VstlTriggered.word(0U))) { - Vmain___024root___stl_sequent__TOP__0(vlSelf); - vlSelf->__Vm_traceActivity[6U] = 1U; - vlSelf->__Vm_traceActivity[5U] = 1U; - vlSelf->__Vm_traceActivity[4U] = 1U; - vlSelf->__Vm_traceActivity[3U] = 1U; - vlSelf->__Vm_traceActivity[2U] = 1U; - vlSelf->__Vm_traceActivity[1U] = 1U; - vlSelf->__Vm_traceActivity[0U] = 1U; - Vmain___024root___stl_sequent__TOP__1(vlSelf); - Vmain___024root___stl_sequent__TOP__2(vlSelf); - } -} - -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__ico(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___dump_triggers__ico\n"); ); - // Body - if ((1U & (~ (IData)(vlSelf->__VicoTriggered.any())))) { - VL_DBG_MSGF(" No triggers active\n"); - } - if ((1ULL & vlSelf->__VicoTriggered.word(0U))) { - VL_DBG_MSGF(" 'ico' region trigger index 0 is active: Internal 'ico' trigger - first iteration\n"); - } -} -#endif // VL_DEBUG - -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__act(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___dump_triggers__act\n"); ); - // Body - if ((1U & (~ (IData)(vlSelf->__VactTriggered.any())))) { - VL_DBG_MSGF(" No triggers active\n"); - } - if ((1ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 0 is active: @(posedge i_clk)\n"); - } - if ((2ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 1 is active: @([changed] main.wbwide_xbar.ARBITRATE_REQUESTS[0].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((4ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 2 is active: @([changed] main.wbwide_xbar.ARBITRATE_REQUESTS[1].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((8ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 3 is active: @([changed] main.wbwide_xbar.ARBITRATE_REQUESTS[2].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((0x10ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 4 is active: @([changed] main.wbwide_xbar.ARBITRATE_REQUESTS[3].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((0x20ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 5 is active: @([changed] main.wb32_xbar.ARBITRATE_REQUESTS[0].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((0x40ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 6 is active: @([changed] main.wbu_xbar.ARBITRATE_REQUESTS[0].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((0x80ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 7 is active: @(posedge i_clk or negedge main.__Vcellinp__ddr3_controller_inst__i_rst_n)\n"); - } - if ((0x100ULL & vlSelf->__VactTriggered.word(0U))) { - VL_DBG_MSGF(" 'act' region trigger index 8 is active: @(negedge i_clk)\n"); - } -} -#endif // VL_DEBUG - -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__nba(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___dump_triggers__nba\n"); ); - // Body - if ((1U & (~ (IData)(vlSelf->__VnbaTriggered.any())))) { - VL_DBG_MSGF(" No triggers active\n"); - } - if ((1ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 0 is active: @(posedge i_clk)\n"); - } - if ((2ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 1 is active: @([changed] main.wbwide_xbar.ARBITRATE_REQUESTS[0].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((4ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 2 is active: @([changed] main.wbwide_xbar.ARBITRATE_REQUESTS[1].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((8ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 3 is active: @([changed] main.wbwide_xbar.ARBITRATE_REQUESTS[2].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((0x10ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 4 is active: @([changed] main.wbwide_xbar.ARBITRATE_REQUESTS[3].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((0x20ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 5 is active: @([changed] main.wb32_xbar.ARBITRATE_REQUESTS[0].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((0x40ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 6 is active: @([changed] main.wbu_xbar.ARBITRATE_REQUESTS[0].MINDEX_MULTIPLE_SLAVES.r_regrant)\n"); - } - if ((0x80ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 7 is active: @(posedge i_clk or negedge main.__Vcellinp__ddr3_controller_inst__i_rst_n)\n"); - } - if ((0x100ULL & vlSelf->__VnbaTriggered.word(0U))) { - VL_DBG_MSGF(" 'nba' region trigger index 8 is active: @(negedge i_clk)\n"); - } -} -#endif // VL_DEBUG - -VL_ATTR_COLD void Vmain___024root___ctor_var_reset(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___ctor_var_reset\n"); ); - // Body - vlSelf->i_clk = VL_RAND_RESET_I(1); - vlSelf->i_reset = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->i_ddr3_controller_iserdes_data); - vlSelf->i_ddr3_controller_iserdes_dqs = VL_RAND_RESET_Q(64); - vlSelf->i_ddr3_controller_iserdes_bitslip_reference = VL_RAND_RESET_Q(64); - vlSelf->i_ddr3_controller_idelayctrl_rdy = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(96, vlSelf->o_ddr3_controller_cmd); - vlSelf->o_ddr3_controller_dqs_tri_control = VL_RAND_RESET_I(1); - vlSelf->o_ddr3_controller_dq_tri_control = VL_RAND_RESET_I(1); - vlSelf->o_ddr3_controller_toggle_dqs = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->o_ddr3_controller_data); - vlSelf->o_ddr3_controller_dm = VL_RAND_RESET_Q(64); - vlSelf->o_ddr3_controller_odelay_data_cntvaluein = VL_RAND_RESET_I(5); - vlSelf->o_ddr3_controller_odelay_dqs_cntvaluein = VL_RAND_RESET_I(5); - vlSelf->o_ddr3_controller_idelay_data_cntvaluein = VL_RAND_RESET_I(5); - vlSelf->o_ddr3_controller_idelay_dqs_cntvaluein = VL_RAND_RESET_I(5); - vlSelf->o_ddr3_controller_odelay_data_ld = VL_RAND_RESET_I(8); - vlSelf->o_ddr3_controller_odelay_dqs_ld = VL_RAND_RESET_I(8); - vlSelf->o_ddr3_controller_idelay_data_ld = VL_RAND_RESET_I(8); - vlSelf->o_ddr3_controller_idelay_dqs_ld = VL_RAND_RESET_I(8); - vlSelf->o_ddr3_controller_bitslip = VL_RAND_RESET_I(8); - vlSelf->o_sirefclk_word = VL_RAND_RESET_I(8); - vlSelf->o_sirefclk_ce = VL_RAND_RESET_I(1); - vlSelf->i_fan_sda = VL_RAND_RESET_I(1); - vlSelf->i_fan_scl = VL_RAND_RESET_I(1); - vlSelf->o_fan_sda = VL_RAND_RESET_I(1); - vlSelf->o_fan_scl = VL_RAND_RESET_I(1); - vlSelf->o_fpga_pwm = VL_RAND_RESET_I(1); - vlSelf->o_sys_pwm = VL_RAND_RESET_I(1); - vlSelf->i_fan_tach = VL_RAND_RESET_I(1); - vlSelf->o_emmc_clk = VL_RAND_RESET_I(1); - vlSelf->i_emmc_ds = VL_RAND_RESET_I(1); - vlSelf->io_emmc_cmd_tristate = VL_RAND_RESET_I(1); - vlSelf->o_emmc_cmd = VL_RAND_RESET_I(1); - vlSelf->i_emmc_cmd = VL_RAND_RESET_I(1); - vlSelf->io_emmc_dat_tristate = VL_RAND_RESET_I(8); - vlSelf->o_emmc_dat = VL_RAND_RESET_I(8); - vlSelf->i_emmc_dat = VL_RAND_RESET_I(8); - vlSelf->i_emmc_detect = VL_RAND_RESET_I(1); - vlSelf->i_i2c_sda = VL_RAND_RESET_I(1); - vlSelf->i_i2c_scl = VL_RAND_RESET_I(1); - vlSelf->o_i2c_sda = VL_RAND_RESET_I(1); - vlSelf->o_i2c_scl = VL_RAND_RESET_I(1); - vlSelf->o_sdcard_clk = VL_RAND_RESET_I(1); - vlSelf->i_sdcard_ds = VL_RAND_RESET_I(1); - vlSelf->io_sdcard_cmd_tristate = VL_RAND_RESET_I(1); - vlSelf->o_sdcard_cmd = VL_RAND_RESET_I(1); - vlSelf->i_sdcard_cmd = VL_RAND_RESET_I(1); - vlSelf->io_sdcard_dat_tristate = VL_RAND_RESET_I(4); - vlSelf->o_sdcard_dat = VL_RAND_RESET_I(4); - vlSelf->i_sdcard_dat = VL_RAND_RESET_I(4); - vlSelf->i_sdcard_detect = VL_RAND_RESET_I(1); - vlSelf->cpu_sim_cyc = VL_RAND_RESET_I(1); - vlSelf->cpu_sim_stb = VL_RAND_RESET_I(1); - vlSelf->cpu_sim_we = VL_RAND_RESET_I(1); - vlSelf->cpu_sim_addr = VL_RAND_RESET_I(7); - vlSelf->cpu_sim_data = VL_RAND_RESET_I(32); - vlSelf->cpu_sim_stall = VL_RAND_RESET_I(1); - vlSelf->cpu_sim_ack = VL_RAND_RESET_I(1); - vlSelf->cpu_sim_idata = VL_RAND_RESET_I(32); - vlSelf->cpu_prof_stb = VL_RAND_RESET_I(1); - vlSelf->cpu_prof_addr = VL_RAND_RESET_I(28); - vlSelf->cpu_prof_ticks = VL_RAND_RESET_I(32); - vlSelf->i_cpu_reset = VL_RAND_RESET_I(1); - vlSelf->i_clk200 = VL_RAND_RESET_I(1); - vlSelf->i_wbu_uart_rx = VL_RAND_RESET_I(1); - vlSelf->o_wbu_uart_tx = VL_RAND_RESET_I(1); - vlSelf->o_wbu_uart_cts_n = VL_RAND_RESET_I(1); - vlSelf->i_gpio = VL_RAND_RESET_I(16); - vlSelf->o_gpio = VL_RAND_RESET_I(8); - vlSelf->i_sw = VL_RAND_RESET_I(8); - vlSelf->i_btn = VL_RAND_RESET_I(5); - vlSelf->o_led = VL_RAND_RESET_I(8); - vlSelf->main__DOT__emmcscope_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscope_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmc_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdcard_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscope_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__gpio_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__spio_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__r_sirefclk_en = VL_RAND_RESET_I(1); - vlSelf->main__DOT__r_sirefclk_data = VL_RAND_RESET_I(30); - vlSelf->main__DOT__w_sirefclk_unused_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__r_sirefclk_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cdma_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2c_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2c_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2c_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2c_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__w_console_rx_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__w_console_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__w_console_rx_data = VL_RAND_RESET_I(7); - vlSelf->main__DOT__w_console_tx_data = VL_RAND_RESET_I(7); - vlSelf->main__DOT__uart_debug = VL_RAND_RESET_I(32); - vlSelf->main__DOT__raw_cpu_dbg_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__raw_cpu_dbg_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__zip_cpu_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_rx_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__wbu_rx_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__w_led = VL_RAND_RESET_I(8); - vlSelf->main__DOT__wbwide_i2cdma_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_i2cdma_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_i2cdma_addr = VL_RAND_RESET_I(22); - VL_RAND_RESET_W(512, vlSelf->main__DOT__wbwide_i2cdma_data); - vlSelf->main__DOT__wbwide_i2cdma_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__wbwide_i2cm_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_i2cm_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_i2cm_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__wbwide_zip_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_zip_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_zip_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__wbwide_wbu_arbiter_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_wbu_arbiter_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_wbdown_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_bkram_ack = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__wbwide_bkram_idata); - vlSelf->main__DOT__wbwide_ddr3_controller_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_wbdown_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_wbdown_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_wbdown_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_wbdown_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_buildtime_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__wb32_buildtime_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_gpio_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__wb32_gpio_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_sirefclk_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_sirefclk_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__wb32_sirefclk_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_spio_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_spio_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__wb32_spio_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_spio_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_version_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__wb32_version_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_i2cs_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_i2cdma_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_i2cdma_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_uart_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_uart_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_emmc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_emmc_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_fan_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_fan_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_sdcard_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_sdcard_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_ddr3_phy_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_ddr3_phy_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_ddr3_phy_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbu_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbu_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbu_wbu_arbiter_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_zip_idata = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(192, vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel); - VL_RAND_RESET_W(1536, vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata); - VL_RAND_RESET_W(66, vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe = VL_RAND_RESET_I(3); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb = VL_RAND_RESET_I(3); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc = VL_RAND_RESET_I(3); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr = VL_RAND_RESET_I(4); - VL_RAND_RESET_W(2048, vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata); - vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc = VL_RAND_RESET_I(4); - vlSelf->main__DOT__r_wb32_sio_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__r_wb32_sio_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel = VL_RAND_RESET_Q(48); - VL_RAND_RESET_W(384, vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata); - VL_RAND_RESET_W(96, vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe = VL_RAND_RESET_I(12); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb = VL_RAND_RESET_I(12); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc = VL_RAND_RESET_I(12); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_ssel = VL_RAND_RESET_I(8); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata = VL_RAND_RESET_Q(64); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr = VL_RAND_RESET_Q(54); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_swe = VL_RAND_RESET_I(2); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb = VL_RAND_RESET_I(2); - vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc = VL_RAND_RESET_I(2); - vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4 = VL_RAND_RESET_I(31); - vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3 = VL_RAND_RESET_I(1); - vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4 = VL_RAND_RESET_I(31); - vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3 = VL_RAND_RESET_I(1); - vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT____Vcellinp__u_i2cdma__S_VALID = VL_RAND_RESET_I(1); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr = VL_RAND_RESET_I(7); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT____Vcellinp__swic__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4 = VL_RAND_RESET_I(31); - vlSelf->main__DOT__r_cfg_ack = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbwide_xbar__DOT__request[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[__Vi0] = VL_RAND_RESET_I(3); - } - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[__Vi0] = VL_RAND_RESET_I(4); - } - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__sgrant = VL_RAND_RESET_I(3); - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbwide_xbar__DOT__w_mpending[__Vi0] = VL_RAND_RESET_I(6); - } - vlSelf->main__DOT__wbwide_xbar__DOT__mfull = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__mnearfull = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__mempty = VL_RAND_RESET_I(4); - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[__Vi0] = VL_RAND_RESET_I(2); - } - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbwide_xbar__DOT__sindex[__Vi0] = VL_RAND_RESET_I(2); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stb = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__m_we = VL_RAND_RESET_I(4); - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[__Vi0] = VL_RAND_RESET_I(22); - } - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - VL_RAND_RESET_W(512, vlSelf->main__DOT__wbwide_xbar__DOT__m_data[__Vi0]); - } - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[__Vi0] = VL_RAND_RESET_Q(64); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__s_stall = VL_RAND_RESET_I(4); - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - VL_RAND_RESET_W(512, vlSelf->main__DOT__wbwide_xbar__DOT__s_data[__Vi0]); - } - vlSelf->main__DOT__wbwide_xbar__DOT__s_ack = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__s_err = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__iN = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbwide_xbar__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(577, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__decoded = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskd_ready = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__iskid__o_data); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__iskid__i_reset = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(577, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__decoded = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskd_ready = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(577, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__decoded = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskd_ready = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__iskid__o_data); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_data); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(577, vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__requested_channel_is_available = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__reindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__iskid__DOT__LOGIC__DOT__r_data); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(599, vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_data); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__request[__Vi0] = VL_RAND_RESET_I(13); - } - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__requested[__Vi0] = VL_RAND_RESET_I(12); - } - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__grant[__Vi0] = VL_RAND_RESET_I(13); - } - vlSelf->main__DOT__wb32_xbar__DOT__mgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__sgrant = VL_RAND_RESET_I(12); - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__w_mpending[__Vi0] = VL_RAND_RESET_I(6); - } - vlSelf->main__DOT__wb32_xbar__DOT__mfull = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__mnearfull = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__mempty = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__mindex[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 16; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__sindex[__Vi0] = VL_RAND_RESET_I(1); - } - vlSelf->main__DOT__wb32_xbar__DOT__m_stb = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__m_addr[__Vi0] = VL_RAND_RESET_I(8); - } - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__m_data[__Vi0] = VL_RAND_RESET_I(32); - } - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__m_sel[__Vi0] = VL_RAND_RESET_I(4); - } - vlSelf->main__DOT__wb32_xbar__DOT__m_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__s_stall = VL_RAND_RESET_I(16); - for (int __Vi0 = 0; __Vi0 < 16; ++__Vi0) { - vlSelf->main__DOT__wb32_xbar__DOT__s_data[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__iN = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_xbar__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded = VL_RAND_RESET_I(13); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data = VL_RAND_RESET_Q(45); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data = VL_RAND_RESET_Q(45); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data = VL_RAND_RESET_Q(37); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = VL_RAND_RESET_I(13); - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data = VL_RAND_RESET_Q(45); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest = VL_RAND_RESET_I(12); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request = VL_RAND_RESET_I(12); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__request[__Vi0] = VL_RAND_RESET_I(3); - } - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__requested[__Vi0] = VL_RAND_RESET_I(2); - } - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__grant[__Vi0] = VL_RAND_RESET_I(3); - } - vlSelf->main__DOT__wbu_xbar__DOT__mgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__sgrant = VL_RAND_RESET_I(2); - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__w_mpending[__Vi0] = VL_RAND_RESET_I(6); - } - vlSelf->main__DOT__wbu_xbar__DOT__mfull = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__mnearfull = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__mempty = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__mindex[__Vi0] = VL_RAND_RESET_I(2); - } - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__sindex[__Vi0] = VL_RAND_RESET_I(1); - } - vlSelf->main__DOT__wbu_xbar__DOT__m_stb = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__m_addr[__Vi0] = VL_RAND_RESET_I(27); - } - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__m_data[__Vi0] = VL_RAND_RESET_I(32); - } - for (int __Vi0 = 0; __Vi0 < 1; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__m_sel[__Vi0] = VL_RAND_RESET_I(4); - } - vlSelf->main__DOT__wbu_xbar__DOT__m_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__s_stall = VL_RAND_RESET_I(4); - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__wbu_xbar__DOT__s_data[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__wbu_xbar__DOT__s_err = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__iN = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbu_xbar__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__decoded = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data = VL_RAND_RESET_Q(37); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr = VL_RAND_RESET_I(27); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = VL_RAND_RESET_I(3); - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest = VL_RAND_RESET_I(2); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__iM = VL_RAND_RESET_I(32); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__read_from_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__write_to_control = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__o_bus_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__emmcscopei__DOT__read_address = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__raddr = VL_RAND_RESET_I(12); - vlSelf->main__DOT__emmcscopei__DOT__waddr = VL_RAND_RESET_I(12); - for (int __Vi0 = 0; __Vi0 < 4096; ++__Vi0) { - vlSelf->main__DOT__emmcscopei__DOT__mem[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__emmcscopei__DOT__bw_reset_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__br_config = VL_RAND_RESET_I(3); - vlSelf->main__DOT__emmcscopei__DOT__br_holdoff = VL_RAND_RESET_I(20); - vlSelf->main__DOT__emmcscopei__DOT__holdoff_counter = VL_RAND_RESET_I(20); - vlSelf->main__DOT__emmcscopei__DOT__dr_triggered = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__dr_primed = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__dw_trigger = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__dr_stopped = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe = VL_RAND_RESET_I(5); - vlSelf->main__DOT__emmcscopei__DOT__ck_addr = VL_RAND_RESET_I(31); - vlSelf->main__DOT__emmcscopei__DOT__qd_data = VL_RAND_RESET_I(31); - vlSelf->main__DOT__emmcscopei__DOT__dr_force_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__dr_run_timeout = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__new_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__dr_force_inhibit = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__imm_adr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__lst_adr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__lst_val = VL_RAND_RESET_I(31); - vlSelf->main__DOT__emmcscopei__DOT__imm_val = VL_RAND_RESET_I(31); - vlSelf->main__DOT__emmcscopei__DOT__record_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__r_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__br_pre_wb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__emmcscopei__DOT__this_addr = VL_RAND_RESET_I(12); - vlSelf->main__DOT__emmcscopei__DOT__nxt_mem = VL_RAND_RESET_I(32); - vlSelf->main__DOT__emmcscopei__DOT__br_level_interrupt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__read_from_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__write_to_control = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__o_bus_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__sdioscopei__DOT__read_address = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__raddr = VL_RAND_RESET_I(12); - vlSelf->main__DOT__sdioscopei__DOT__waddr = VL_RAND_RESET_I(12); - for (int __Vi0 = 0; __Vi0 < 4096; ++__Vi0) { - vlSelf->main__DOT__sdioscopei__DOT__mem[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__sdioscopei__DOT__bw_reset_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__br_config = VL_RAND_RESET_I(3); - vlSelf->main__DOT__sdioscopei__DOT__br_holdoff = VL_RAND_RESET_I(20); - vlSelf->main__DOT__sdioscopei__DOT__holdoff_counter = VL_RAND_RESET_I(20); - vlSelf->main__DOT__sdioscopei__DOT__dr_triggered = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__dr_primed = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__dw_trigger = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__dr_stopped = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe = VL_RAND_RESET_I(5); - vlSelf->main__DOT__sdioscopei__DOT__ck_addr = VL_RAND_RESET_I(31); - vlSelf->main__DOT__sdioscopei__DOT__qd_data = VL_RAND_RESET_I(31); - vlSelf->main__DOT__sdioscopei__DOT__dr_force_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__dr_run_timeout = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__new_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__dr_force_inhibit = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__imm_adr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__lst_adr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__lst_val = VL_RAND_RESET_I(31); - vlSelf->main__DOT__sdioscopei__DOT__imm_val = VL_RAND_RESET_I(31); - vlSelf->main__DOT__sdioscopei__DOT__record_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__r_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__br_pre_wb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__sdioscopei__DOT__this_addr = VL_RAND_RESET_I(12); - vlSelf->main__DOT__sdioscopei__DOT__nxt_mem = VL_RAND_RESET_I(32); - vlSelf->main__DOT__sdioscopei__DOT__br_level_interrupt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = VL_RAND_RESET_I(32); - vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address = VL_RAND_RESET_I(5); - vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction = VL_RAND_RESET_I(28); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter = VL_RAND_RESET_I(16); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q = VL_RAND_RESET_I(8); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d = VL_RAND_RESET_I(8); - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[__Vi0] = VL_RAND_RESET_I(14); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[__Vi0] = VL_RAND_RESET_I(14); - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_aux = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_dm = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_col = VL_RAND_RESET_I(10); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank = VL_RAND_RESET_I(3); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row = VL_RAND_RESET_I(14); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank = VL_RAND_RESET_I(3); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row = VL_RAND_RESET_I(14); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned = VL_RAND_RESET_Q(64); - for (int __Vi0 = 0; __Vi0 < 2; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[__Vi0] = VL_RAND_RESET_Q(64); - } - VL_RAND_RESET_W(512, vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned); - for (int __Vi0 = 0; __Vi0 < 2; ++__Vi0) { - VL_RAND_RESET_W(512, vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[__Vi0]); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[__Vi0] = VL_RAND_RESET_Q(64); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[__Vi0] = VL_RAND_RESET_I(8); - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col = VL_RAND_RESET_I(10); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank = VL_RAND_RESET_I(3); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row = VL_RAND_RESET_I(14); - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 4; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[__Vi0] = VL_RAND_RESET_I(24); - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt_q = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_d = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_q = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs = VL_RAND_RESET_I(3); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_val = VL_RAND_RESET_I(3); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_q = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq = VL_RAND_RESET_I(4); - vlSelf->main__DOT__ddr3_controller_inst__DOT__aligned_cmd = VL_RAND_RESET_I(24); - vlSelf->main__DOT__ddr3_controller_inst__DOT__serial_index = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__serial_index_q = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__test_OFB = VL_RAND_RESET_I(8); - vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate = VL_RAND_RESET_I(5); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store = VL_RAND_RESET_Q(40); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat = VL_RAND_RESET_I(4); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index = VL_RAND_RESET_I(6); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored = VL_RAND_RESET_I(6); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index = VL_RAND_RESET_I(6); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig = VL_RAND_RESET_I(6); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index = VL_RAND_RESET_I(6); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value = VL_RAND_RESET_I(6); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data = VL_RAND_RESET_I(4); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback = VL_RAND_RESET_I(5); - vlSelf->main__DOT__ddr3_controller_inst__DOT__initial_dqs = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__lane = VL_RAND_RESET_I(3); - vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8 = VL_RAND_RESET_I(6); - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement = VL_RAND_RESET_I(16); - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max = VL_RAND_RESET_I(4); - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[__Vi0] = VL_RAND_RESET_I(4); - } - for (int __Vi0 = 0; __Vi0 < 5; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[__Vi0] = VL_RAND_RESET_I(2); - } - for (int __Vi0 = 0; __Vi0 < 5; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[__Vi0] = VL_RAND_RESET_I(2); - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__index_read_pipe = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 2; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[__Vi0] = VL_RAND_RESET_I(16); - } - for (int __Vi0 = 0; __Vi0 < 2; ++__Vi0) { - VL_RAND_RESET_W(512, vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[__Vi0]); - } - for (int __Vi0 = 0; __Vi0 < 16; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[__Vi0] = VL_RAND_RESET_I(2); - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col = VL_RAND_RESET_I(10); - VL_RAND_RESET_W(512, vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dq = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store); - VL_RAND_RESET_W(128, vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern); - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[__Vi0] = VL_RAND_RESET_I(7); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[__Vi0] = VL_RAND_RESET_I(5); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[__Vi0] = VL_RAND_RESET_I(5); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[__Vi0] = VL_RAND_RESET_I(5); - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev = VL_RAND_RESET_I(5); - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[__Vi0] = VL_RAND_RESET_I(5); - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_update = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr = VL_RAND_RESET_I(32); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_sel = VL_RAND_RESET_I(4); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_read_lane = VL_RAND_RESET_I(3); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_cntvaluein = VL_RAND_RESET_I(5); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_cntvaluein = VL_RAND_RESET_I(5); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_cntvaluein = VL_RAND_RESET_I(5); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_cntvaluein = VL_RAND_RESET_I(5); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_ld = VL_RAND_RESET_I(8); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_ld = VL_RAND_RESET_I(8); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_ld = VL_RAND_RESET_I(8); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_ld = VL_RAND_RESET_I(8); - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane = VL_RAND_RESET_I(3); - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = VL_RAND_RESET_I(32); - vlSelf->main__DOT__ddr3_controller_inst__DOT__nCK_to_cycles__Vstatic__result = VL_RAND_RESET_I(32); - vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__delay = VL_RAND_RESET_I(32); - vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__slot_number = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__read_slot = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__write_slot = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__anticipate_activate_slot = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__get_slot__Vstatic__anticipate_precharge_slot = VL_RAND_RESET_I(2); - vlSelf->main__DOT__ddr3_controller_inst__DOT__find_delay__Vstatic__k = VL_RAND_RESET_I(32); - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_h133f9401__0 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_hddcbe2f8__0 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1 = VL_RAND_RESET_I(2); - for (int __Vi0 = 0; __Vi0 < 16384; ++__Vi0) { - VL_RAND_RESET_W(512, vlSelf->main__DOT__bkrami__DOT__mem[__Vi0]); - } - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_wstb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_addr = VL_RAND_RESET_I(14); - VL_RAND_RESET_W(512, vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_data); - vlSelf->main__DOT__bkrami__DOT__EXTRA_MEM_CLOCK_CYCLE__DOT__last_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__bkrami__DOT__WRITE_TO_MEMORY__DOT__ik = VL_RAND_RESET_I(32); - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__clock_generator__DOT__counter[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__clock_generator__DOT__r_delay = VL_RAND_RESET_I(32); - vlSelf->main__DOT__clock_generator__DOT__times_three = VL_RAND_RESET_I(32); - vlSelf->main__DOT__clock_generator__DOT__times_five = VL_RAND_RESET_I(32); - vlSelf->main__DOT__clock_generator__DOT__times_seven = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__u_i2cdma__DOT__r_memlen = VL_RAND_RESET_I(28); - vlSelf->main__DOT__u_i2cdma__DOT__subaddr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_i2cdma__DOT__current_addr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_i2cdma__DOT__next_memlen = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_i2cdma__DOT__wb_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_i2cdma__DOT__bus_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_i2cdma__DOT__r_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_i2cdma__DOT__r_overflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_i2cdma__DOT__skd_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_i2cdma__DOT__skd_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data = VL_RAND_RESET_I(9); - vlSelf->main__DOT__u_i2cdma__DOT____Vcellinp__sskd__i_data = VL_RAND_RESET_I(9); - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_data = VL_RAND_RESET_I(9); - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__pwm_counter = VL_RAND_RESET_I(13); - vlSelf->main__DOT__u_fan__DOT__ctl_fpga = VL_RAND_RESET_I(13); - vlSelf->main__DOT__u_fan__DOT__ctl_sys = VL_RAND_RESET_I(13); - vlSelf->main__DOT__u_fan__DOT__ck_tach = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__last_tach = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__pipe_tach = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_fan__DOT__tach_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__tach_count = VL_RAND_RESET_I(27); - vlSelf->main__DOT__u_fan__DOT__tach_counter = VL_RAND_RESET_I(27); - vlSelf->main__DOT__u_fan__DOT__tach_timer = VL_RAND_RESET_I(27); - vlSelf->main__DOT__u_fan__DOT__i2c_wb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__ign_mem_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__mem_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__mem_addr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_fan__DOT__mem_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_fan__DOT__mem_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__i2cd_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__i2cd_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__i2cd_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_fan__DOT__pp_ms = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__trigger_counter = VL_RAND_RESET_I(17); - vlSelf->main__DOT__u_fan__DOT__temp_tmp = VL_RAND_RESET_I(24); - vlSelf->main__DOT__u_fan__DOT__temp_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_fan__DOT__pre_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__pre_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn = VL_RAND_RESET_I(12); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount = VL_RAND_RESET_I(12); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ckcount = VL_RAND_RESET_I(12); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__abort_address = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__jump_target = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__soft_halt_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_read_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_data = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_fetch__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__o_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__last_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__invalid_bus_cycle = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_word = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_illegal = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = VL_RAND_RESET_I(3); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__stop_bit = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__cfg_ddr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_emmc__DOT__sdclk = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__pp_cmd = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__pp_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__rx_en = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_half = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__w_sdclk = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_ckspd = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_id = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_arg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd = VL_RAND_RESET_I(7); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_arg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ika = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__ikb = VL_RAND_RESET_I(32); - for (int __Vi0 = 0; __Vi0 < 1024; ++__Vi0) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a[__Vi0] = VL_RAND_RESET_I(32); - } - for (int __Vi0 = 0; __Vi0 < 1024; ++__Vi0) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_sel = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__clk90 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0 = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg = VL_RAND_RESET_Q(48); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg = VL_RAND_RESET_Q(40); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = VL_RAND_RESET_I(26); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill = VL_RAND_RESET_I(7); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg = VL_RAND_RESET_Q(64); - VL_RAND_RESET_W(128, vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w); - VL_RAND_RESET_W(128, vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w); - VL_RAND_RESET_W(128, vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w); - VL_RAND_RESET_W(128, vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg); - VL_RAND_RESET_W(256, vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d); - VL_RAND_RESET_W(256, vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d); - VL_RAND_RESET_W(256, vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d); - VL_RAND_RESET_W(256, vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg = VL_RAND_RESET_I(20); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout = VL_RAND_RESET_I(23); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__resp_started = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__io_started = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0 = 0; - vlSelf->main__DOT__i2ci__DOT__cpu_new_pc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__pf_jump_addr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__i2ci__DOT__pf_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__pf_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__pf_insn = VL_RAND_RESET_I(8); - vlSelf->main__DOT__i2ci__DOT__pf_insn_addr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__i2ci__DOT__pf_illegal = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__half_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__imm_cycle = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__next_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__next_insn = VL_RAND_RESET_I(8); - vlSelf->main__DOT__i2ci__DOT__insn_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__half_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__i2c_abort = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__insn_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__insn = VL_RAND_RESET_I(12); - vlSelf->main__DOT__i2ci__DOT__half_insn = VL_RAND_RESET_I(4); - vlSelf->main__DOT__i2ci__DOT__i2c_ckedge = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__i2c_stretch = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__i2c_ckcount = VL_RAND_RESET_I(12); - vlSelf->main__DOT__i2ci__DOT__ckcount = VL_RAND_RESET_I(12); - vlSelf->main__DOT__i2ci__DOT__abort_address = VL_RAND_RESET_I(28); - vlSelf->main__DOT__i2ci__DOT__jump_target = VL_RAND_RESET_I(28); - vlSelf->main__DOT__i2ci__DOT__r_wait = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__soft_halt_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__r_halted = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__r_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__r_aborted = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__w_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__w_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__bus_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__bus_override = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__bus_manual = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__ovw_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__bus_jump = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__bus_read_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__i2ci__DOT__s_tvalid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__ovw_data = VL_RAND_RESET_I(10); - vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_fetch__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__mid_axis_pkt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__r_channel = VL_RAND_RESET_I(2); - vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid = VL_RAND_RESET_I(2); - vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0 = 0; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__last_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__invalid_bus_cycle = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight = VL_RAND_RESET_I(2); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_illegal = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__r_valid = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count = VL_RAND_RESET_I(7); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift = VL_RAND_RESET_I(6); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__last_byte = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__will_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state = VL_RAND_RESET_I(4); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = VL_RAND_RESET_I(3); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg = VL_RAND_RESET_I(8); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_scl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_sda = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__stop_bit = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_data); - VL_RAND_RESET_W(512, vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data); - VL_RAND_RESET_W(512, vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_shift = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__i_subaddr = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_full = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 32; ++__Vi0) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem[__Vi0] = VL_RAND_RESET_I(5); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_sdcard__DOT__sdclk = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__pp_cmd = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__pp_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__rx_en = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_half = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__w_sdclk = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_ckspd = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_id = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_arg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd = VL_RAND_RESET_I(7); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_arg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ika = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__ikb = VL_RAND_RESET_I(32); - for (int __Vi0 = 0; __Vi0 < 1024; ++__Vi0) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a[__Vi0] = VL_RAND_RESET_I(32); - } - for (int __Vi0 = 0; __Vi0 < 1024; ++__Vi0) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_sel = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_a = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_addr_b = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_a = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_strb_b = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_a = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__mem_wr_data_b = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present = VL_RAND_RESET_I(3); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_removed = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__clk90 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0 = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg = VL_RAND_RESET_Q(48); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_ds = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg = VL_RAND_RESET_Q(40); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = VL_RAND_RESET_I(26); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill = VL_RAND_RESET_I(7); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__new_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_period = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg = VL_RAND_RESET_Q(64); - VL_RAND_RESET_W(128, vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w); - VL_RAND_RESET_W(128, vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w); - VL_RAND_RESET_W(128, vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w); - VL_RAND_RESET_W(128, vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg); - VL_RAND_RESET_W(256, vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d); - VL_RAND_RESET_W(256, vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d); - VL_RAND_RESET_W(256, vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d); - VL_RAND_RESET_W(256, vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill = VL_RAND_RESET_I(5); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg = VL_RAND_RESET_I(20); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_strb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb = VL_RAND_RESET_I(4); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rnxt_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout = VL_RAND_RESET_I(23); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 16; ++__Vi0) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat[__Vi0] = VL_RAND_RESET_I(1); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat = VL_RAND_RESET_I(16); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pck_sreg = VL_RAND_RESET_I(6); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__resp_started = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__io_started = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__o_pin = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__o_pin = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__o_pin = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT____Vcellout__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__o_pin = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out = VL_RAND_RESET_I(8); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__high_z = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_clk_oddr__DOT__r_out = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__r_out = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__high_z = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__r_out = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__high_z = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__r_out = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__high_z = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__r_out = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__high_z = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__r_out = VL_RAND_RESET_I(2); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in = VL_RAND_RESET_I(2); - vlSelf->main__DOT__console__DOT__rx_uart_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__rxf_wb_data = VL_RAND_RESET_I(7); - vlSelf->main__DOT__console__DOT__rxf_status = VL_RAND_RESET_I(16); - vlSelf->main__DOT__console__DOT__rxf_wb_read = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__txf_status = VL_RAND_RESET_I(16); - vlSelf->main__DOT__console__DOT__txf_wb_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__tx_uart_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__txf_wb_data = VL_RAND_RESET_I(7); - vlSelf->main__DOT__console__DOT__r_wb_addr = VL_RAND_RESET_I(2); - vlSelf->main__DOT__console__DOT__r_wb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT____Vcellinp__txfifo____pinNumber6 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT____VdfgTmp_h60af6732__0 = 0; - for (int __Vi0 = 0; __Vi0 < 64; ++__Vi0) { - vlSelf->main__DOT__console__DOT__rxfifo__DOT__fifo[__Vi0] = VL_RAND_RESET_I(7); - } - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_data = VL_RAND_RESET_I(7); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__last_write = VL_RAND_RESET_I(7); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__wr_addr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__rd_addr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_next = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_overflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__osrc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_waddr_plus_one = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_read = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__r_fill = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__rxfifo__DOT__w_fill = VL_RAND_RESET_I(10); - for (int __Vi0 = 0; __Vi0 < 64; ++__Vi0) { - vlSelf->main__DOT__console__DOT__txfifo__DOT__fifo[__Vi0] = VL_RAND_RESET_I(7); - } - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_data = VL_RAND_RESET_I(7); - vlSelf->main__DOT__console__DOT__txfifo__DOT__last_write = VL_RAND_RESET_I(7); - vlSelf->main__DOT__console__DOT__txfifo__DOT__wr_addr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__txfifo__DOT__rd_addr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_next = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__txfifo__DOT__will_underflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__txfifo__DOT__osrc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_waddr_plus_one = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_read = VL_RAND_RESET_I(1); - vlSelf->main__DOT__console__DOT__txfifo__DOT__r_fill = VL_RAND_RESET_I(6); - vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill = VL_RAND_RESET_I(10); - vlSelf->main__DOT__swic__DOT__main_int_vector = VL_RAND_RESET_I(15); - vlSelf->main__DOT__swic__DOT__alt_int_vector = VL_RAND_RESET_I(15); - vlSelf->main__DOT__swic__DOT__ctri_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__tma_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__tmb_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__tmc_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__jif_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dmac_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__mtc_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__moc_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__mpc_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__mic_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__utc_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__uoc_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__upc_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__uic_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__actr_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sys_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sys_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sys_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sys_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__swic__DOT__sys_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__cpu_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__swic__DOT__sys_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__sys_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sel_timer = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sel_pic = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sel_apic = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sel_watchdog = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sel_bus_watchdog = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__sel_dmac = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_addr = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__dbg_idata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__dbg_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_odata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__dbg_sel = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__no_dbg_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_break = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_cmd_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_cpu_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_cpu_read = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__reset_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__halt_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__step_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__clear_cache_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cmd_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cmd_halt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cmd_step = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cmd_clear_cache = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cmd_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cmd_read = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cmd_waddr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__cmd_wdata = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__cpu_dbg_cc = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__wdt_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__wdt_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__wdbus_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__r_wdbus_data = VL_RAND_RESET_I(22); - vlSelf->main__DOT__swic__DOT__pic_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__wdbus_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_op_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_pf_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_i_count = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dmac_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dc_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dmac_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__dmac_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dc_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dc_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dc_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ctri_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__tma_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__tmb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__tmc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__jif_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_we = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__cpu_idata); - vlSelf->main__DOT__swic__DOT__cpu_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__pic_interrupt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cpu_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ext_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__w_ack_idx = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__ack_idx = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__last_sys_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__cmd_read_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchdog__i_wb_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchbus____pinNumber2 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_a__i_wb_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_b__i_wb_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_c__i_wb_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_jiffies__i_wb_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__r_mmus_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_pre_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dbg_pre_addr = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__dbg_cpu_status = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__r_reset_hold = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mtask_ctr____pinNumber5 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mmstall_ctr____pinNumber5 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mpstall_ctr____pinNumber5 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mins_ctr____pinNumber5 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__utask_ctr____pinNumber5 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__umstall_ctr____pinNumber5 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__upstall_ctr____pinNumber5 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__uins_ctr____pinNumber5 = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0 = 0; - vlSelf->main__DOT__swic__DOT____VdfgTmp_h9a48e2a3__0 = 0; - vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0 = 0; - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_running = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_zero = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__r_value = VL_RAND_RESET_I(31); - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__wb_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_watchbus__DOT__r_value = VL_RAND_RESET_I(14); - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_running = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_zero = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__r_value = VL_RAND_RESET_I(31); - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_auto_reload = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__GEN_RELOAD__DOT__r_interval_count = VL_RAND_RESET_I(31); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_running = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_zero = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__r_value = VL_RAND_RESET_I(31); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_auto_reload = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__GEN_RELOAD__DOT__r_interval_count = VL_RAND_RESET_I(31); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_running = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_zero = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__r_value = VL_RAND_RESET_I(31); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_auto_reload = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__GEN_RELOAD__DOT__r_interval_count = VL_RAND_RESET_I(31); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_set = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_set = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_now = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_when = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_when = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_wb = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_when = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wreg = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 32; ++__Vi0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__flags = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__iflags = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags = VL_RAND_RESET_I(16); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags = VL_RAND_RESET_I(16); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubreak = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_u = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ubus_err_flag = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_opn = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_phase = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wR = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ALU = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_M = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_DIV = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_FP = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wF = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_break = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_lock = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_I = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_fpu = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_Rcc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Av = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_Bv = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_wF = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_sim_immv = VL_RAND_RESET_I(23); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_sim_immv = VL_RAND_RESET_I(23); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_alu_pc_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_pc_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_val = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_dbg_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__last_write_to_cc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Aid = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rA = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OPLOCK__DOT__r_op_lock = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim_immv = VL_RAND_RESET_I(23); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_OP_PC__DOT__r_op_pc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OPT_CIS_OP_PHASE__DOT__r_op_phase = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PC__DOT__r_alu_pc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_lock_pc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__r_alu_sim_immv = VL_RAND_RESET_I(23); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__regid = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__CLEAR_DCACHE__DOT__r_clear_dcache = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SETDBG__DOT__r_dbg_reg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_addr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_haf314c36__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__o_sim_immv = VL_RAND_RESET_I(23); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_noop = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_lock = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_pc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_cc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_fpu = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_ljmp = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_nxt_half = VL_RAND_RESET_I(15); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_I = VL_RAND_RESET_I(23); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I = VL_RAND_RESET_I(23); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI = VL_RAND_RESET_I(8); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_insn_is_pipeable = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h9ed30f6d__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_he52a0fcf__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_brev_result = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__c = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__pre_sign = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__set_ovfl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__keep_sgn_on_ovfl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result = VL_RAND_RESET_Q(33); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_asr_result = VL_RAND_RESET_Q(33); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result = VL_RAND_RESET_Q(33); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__mpy_result = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_heed50945__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_smpy_result = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_umpy_result = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_a_input = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_mpy_b_input = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_sgn = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__r_hi = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend = VL_RAND_RESET_Q(63); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__diff = VL_RAND_RESET_Q(33); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__pre_sign = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_z = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_c = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_bit = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__zero_divisor = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 64; ++__Vi0) { - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache[__Vi0]); - } - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags[__Vi0] = VL_RAND_RESET_I(16); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask = VL_RAND_RESET_I(8); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_pc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v_from_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__rvsrc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_v_from_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__pc_tag_lookup = VL_RAND_RESET_I(19); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_tag_lookup = VL_RAND_RESET_I(19); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup = VL_RAND_RESET_I(19); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache = VL_RAND_RESET_I(19); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__svmask = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__needload = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_addr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__saddr = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_invalidate_result = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__ik = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_gbl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_wb_cyc_lcl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v = VL_RAND_RESET_I(8); - for (int __Vi0 = 0; __Vi0 < 8; ++__Vi0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[__Vi0] = VL_RAND_RESET_I(19); - } - for (int __Vi0 = 0; __Vi0 < 64; ++__Vi0) { - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem[__Vi0]); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr = VL_RAND_RESET_I(6); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_gbl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__lock_lcl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wr = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wdata); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_wsel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_waddr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag = VL_RAND_RESET_I(19); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cline = VL_RAND_RESET_I(3); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag = VL_RAND_RESET_I(19); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_cstb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__in_cache = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_itag = VL_RAND_RESET_I(19); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__req_data = VL_RAND_RESET_I(13); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__gie = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data); - for (int __Vi0 = 0; __Vi0 < 16; ++__Vi0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data[__Vi0] = VL_RAND_RESET_I(12); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__UNUSED_BITS__DOT__unused_aw = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0 = 0; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_addr = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_sel = VL_RAND_RESET_I(4); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen = VL_RAND_RESET_I(11); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_trigger = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr = VL_RAND_RESET_I(22); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__rx_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr = VL_RAND_RESET_I(22); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel = VL_RAND_RESET_Q(64); - VL_RAND_RESET_W(520, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_zero_len = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen = VL_RAND_RESET_I(11); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr = VL_RAND_RESET_I(28); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_subaddr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__base_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding = VL_RAND_RESET_I(11); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__fill = VL_RAND_RESET_I(8); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill = VL_RAND_RESET_I(8); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__sreg); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len = VL_RAND_RESET_I(11); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len = VL_RAND_RESET_I(11); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift = VL_RAND_RESET_I(6); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size = VL_RAND_RESET_I(2); - VL_RAND_RESET_W(1024, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill = VL_RAND_RESET_I(8); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill = VL_RAND_RESET_I(8); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_bytes = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift = VL_RAND_RESET_I(6); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__s_data); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 16; ++__Vi0) { - VL_RAND_RESET_W(520, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem[__Vi0]); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill = VL_RAND_RESET_I(7); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__ik = VL_RAND_RESET_I(32); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size = VL_RAND_RESET_I(2); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr = VL_RAND_RESET_I(29); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr = VL_RAND_RESET_I(6); - VL_RAND_RESET_W(1024, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data); - VL_RAND_RESET_W(512, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data); - VL_RAND_RESET_W(128, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel); - VL_RAND_RESET_W(128, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding = VL_RAND_RESET_I(10); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__ALT__DOT__last_owner = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state = VL_RAND_RESET_I(15); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable = VL_RAND_RESET_I(15); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__enable_ints = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__disable_ints = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state = VL_RAND_RESET_I(15); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable = VL_RAND_RESET_I(15); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__enable_ints = VL_RAND_RESET_I(1); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__disable_ints = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__read_from_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__write_to_control = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__o_bus_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__i2cscopei__DOT__read_address = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__raddr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__i2cscopei__DOT__waddr = VL_RAND_RESET_I(10); - for (int __Vi0 = 0; __Vi0 < 1024; ++__Vi0) { - vlSelf->main__DOT__i2cscopei__DOT__mem[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__i2cscopei__DOT__bw_reset_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__br_config = VL_RAND_RESET_I(3); - vlSelf->main__DOT__i2cscopei__DOT__br_holdoff = VL_RAND_RESET_I(20); - vlSelf->main__DOT__i2cscopei__DOT__holdoff_counter = VL_RAND_RESET_I(20); - vlSelf->main__DOT__i2cscopei__DOT__dr_triggered = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__dr_primed = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__dw_trigger = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__dr_stopped = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe = VL_RAND_RESET_I(5); - vlSelf->main__DOT__i2cscopei__DOT__ck_addr = VL_RAND_RESET_I(31); - vlSelf->main__DOT__i2cscopei__DOT__qd_data = VL_RAND_RESET_I(31); - vlSelf->main__DOT__i2cscopei__DOT__dr_force_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__dr_run_timeout = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__new_data = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__dr_force_inhibit = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__imm_adr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__lst_adr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__lst_val = VL_RAND_RESET_I(31); - vlSelf->main__DOT__i2cscopei__DOT__imm_val = VL_RAND_RESET_I(31); - vlSelf->main__DOT__i2cscopei__DOT__record_ce = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__r_data = VL_RAND_RESET_I(32); - vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__br_pre_wb_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__i2cscopei__DOT__this_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__i2cscopei__DOT__nxt_mem = VL_RAND_RESET_I(32); - vlSelf->main__DOT__i2cscopei__DOT__br_level_interrupt = VL_RAND_RESET_I(1); - vlSelf->main__DOT__rcv__DOT__state = VL_RAND_RESET_I(4); - vlSelf->main__DOT__rcv__DOT__baud_counter = VL_RAND_RESET_I(7); - vlSelf->main__DOT__rcv__DOT__zero_baud_counter = VL_RAND_RESET_I(1); - vlSelf->main__DOT__rcv__DOT__q_uart = VL_RAND_RESET_I(1); - vlSelf->main__DOT__rcv__DOT__qq_uart = VL_RAND_RESET_I(1); - vlSelf->main__DOT__rcv__DOT__ck_uart = VL_RAND_RESET_I(1); - vlSelf->main__DOT__rcv__DOT__chg_counter = VL_RAND_RESET_I(7); - vlSelf->main__DOT__rcv__DOT__half_baud_time = VL_RAND_RESET_I(1); - vlSelf->main__DOT__rcv__DOT__data_reg = VL_RAND_RESET_I(8); - vlSelf->main__DOT__txv__DOT__baud_counter = VL_RAND_RESET_I(7); - vlSelf->main__DOT__txv__DOT__state = VL_RAND_RESET_I(4); - vlSelf->main__DOT__txv__DOT__lcl_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__txv__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__txv__DOT__zero_baud_counter = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__soft_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__r_wdt_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__rx_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__in_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__in_word = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__ps_full = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__ps_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__genbus__DOT__wbu_tx_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wbu_tx_data = VL_RAND_RESET_I(8); - vlSelf->main__DOT__genbus__DOT__ififo_codword = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__exec_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__exec_word = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__ofifo_rd = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__ofifo_codword = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__ofifo_empty_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__w_bus_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__r_wdt_timer = VL_RAND_RESET_I(19); - vlSelf->main__DOT__genbus__DOT____Vcellinp__wroutput__i_bus_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits = VL_RAND_RESET_I(6); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cod_busy = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 128; ++__Vi0) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__remap[__Vi0] = VL_RAND_RESET_I(7); - } - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__k = VL_RAND_RESET_I(32); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__newv = VL_RAND_RESET_I(7); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len = VL_RAND_RESET_I(3); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len = VL_RAND_RESET_I(3); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw = VL_RAND_RESET_I(2); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr = VL_RAND_RESET_I(8); - for (int __Vi0 = 0; __Vi0 < 256; ++__Vi0) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_word = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cmd_addr = VL_RAND_RESET_I(8); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_addr = VL_RAND_RESET_I(25); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__w_addr = VL_RAND_RESET_I(32); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__rd_len = VL_RAND_RESET_I(10); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__cword = VL_RAND_RESET_I(32); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb = VL_RAND_RESET_I(3); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state = VL_RAND_RESET_I(2); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_acks_needed = VL_RAND_RESET_I(10); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_len = VL_RAND_RESET_I(10); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_inc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_new_addr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_read_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__zero_acks = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__runwb__DOT__wide_addr = VL_RAND_RESET_I(32); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__byte_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits = VL_RAND_RESET_I(7); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_bits = VL_RAND_RESET_I(7); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__r_active = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len = VL_RAND_RESET_I(3); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word = VL_RAND_RESET_I(30); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_out_nl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__last_in_nl = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__full_line = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen = VL_RAND_RESET_I(7); - for (int __Vi0 = 0; __Vi0 < 128; ++__Vi0) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__remap[__Vi0] = VL_RAND_RESET_I(7); - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__newv = VL_RAND_RESET_I(7); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__mkbytes__DOT__k = VL_RAND_RESET_I(32); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter = VL_RAND_RESET_I(22); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__a_addrword = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck = VL_RAND_RESET_I(4); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_word = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_filled = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 1024; ++__Vi0) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl[__Vi0] = VL_RAND_RESET_I(32); - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__pmatch = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dmatch = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__vaddr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__cword = VL_RAND_RESET_I(32); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__maddr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__zmatch = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__hmatch = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_dbld = VL_RAND_RESET_I(10); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__adr_hlfd = VL_RAND_RESET_I(3); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword = VL_RAND_RESET_Q(36); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr = VL_RAND_RESET_I(10); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__w_match = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__k = VL_RAND_RESET_I(32); - for (int __Vi0 = 0; __Vi0 < 64; ++__Vi0) { - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo[__Vi0] = VL_RAND_RESET_Q(36); - } - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_wrptr = VL_RAND_RESET_I(7); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr = VL_RAND_RESET_I(7); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__nxt_wrptr = VL_RAND_RESET_I(7); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 1024; ++__Vi0) { - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo[__Vi0] = VL_RAND_RESET_Q(36); - } - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_wrptr = VL_RAND_RESET_I(11); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr = VL_RAND_RESET_I(11); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__nxt_wrptr = VL_RAND_RESET_I(11); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write = VL_RAND_RESET_I(1); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read = VL_RAND_RESET_I(1); - vlSelf->main__DOT__gpioi__DOT__r_gpio = VL_RAND_RESET_I(16); - vlSelf->main__DOT__gpioi__DOT__x_gpio = VL_RAND_RESET_I(16); - vlSelf->main__DOT__gpioi__DOT__q_gpio = VL_RAND_RESET_I(16); - vlSelf->main__DOT__spioi__DOT__led_demo = VL_RAND_RESET_I(1); - vlSelf->main__DOT__spioi__DOT__r_led = VL_RAND_RESET_I(8); - vlSelf->main__DOT__spioi__DOT__bounced = VL_RAND_RESET_I(8); - vlSelf->main__DOT__spioi__DOT__sw_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__s_btn = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe = VL_RAND_RESET_I(10); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_int = VL_RAND_RESET_I(1); - vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe = VL_RAND_RESET_I(16); - vlSelf->main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw = VL_RAND_RESET_I(8); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_owner = VL_RAND_RESET_I(8); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_dir = VL_RAND_RESET_I(1); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_ctr = VL_RAND_RESET_I(25); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__led_clk = VL_RAND_RESET_I(1); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__br_ctr = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_stb = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_we = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_ack = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_addr = VL_RAND_RESET_I(22); - VL_RAND_RESET_W(512, vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_data); - VL_RAND_RESET_W(512, vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__rtn_data); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_sel = VL_RAND_RESET_Q(64); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_shift = VL_RAND_RESET_I(4); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_full = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty = VL_RAND_RESET_I(1); - for (int __Vi0 = 0; __Vi0 < 32; ++__Vi0) { - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem[__Vi0] = VL_RAND_RESET_I(4); - } - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr = VL_RAND_RESET_I(6); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_wr = VL_RAND_RESET_I(1); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd = VL_RAND_RESET_I(1); - vlSelf->__VdfgTmp_h503d14d1__0 = 0; - vlSelf->__VdfgTmp_ha46ae6a3__0 = 0; - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout = VL_RAND_RESET_I(32); - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout = VL_RAND_RESET_I(32); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data = VL_RAND_RESET_I(8); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant = VL_RAND_RESET_I(3); - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v1 = VL_RAND_RESET_I(4); - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v1 = 0; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v2 = 0; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v3 = 0; - vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v4 = VL_RAND_RESET_I(4); - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v4 = 0; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v5 = 0; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v6 = 0; - vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v7 = VL_RAND_RESET_I(4); - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v7 = 0; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v8 = 0; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v9 = 0; - vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v10 = VL_RAND_RESET_I(4); - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v10 = 0; - vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v11 = 0; - vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__mnearfull = VL_RAND_RESET_I(4); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__1__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__2__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__3__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant = VL_RAND_RESET_I(12); - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__wb32_xbar__DOT__grant__v1 = VL_RAND_RESET_I(13); - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v1 = 0; - vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v2 = 0; - vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb = VL_RAND_RESET_I(12); - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__mnearfull = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant = VL_RAND_RESET_I(2); - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__wbu_xbar__DOT__grant__v1 = VL_RAND_RESET_I(3); - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v1 = 0; - vlSelf->__Vdlyvset__main__DOT__wbu_xbar__DOT__grant__v2 = 0; - vlSelf->__Vdly__main__DOT____Vcellout__wbu_xbar__o_sstb = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__COUNT_PENDING_TRANSACTIONS__BRA__0__KET____DOT__lclpending = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__mnearfull = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__holdoff_counter = VL_RAND_RESET_I(20); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stopped = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stop_pipe = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_inhibit = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_write = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__ck_addr = VL_RAND_RESET_I(31); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__waddr = VL_RAND_RESET_I(12); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_primed = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__emmcscopei__DOT__mem__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__emmcscopei__DOT__mem__v0 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvset__main__DOT__emmcscopei__DOT__mem__v0 = 0; - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__holdoff_counter = VL_RAND_RESET_I(20); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stopped = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stop_pipe = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_inhibit = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_write = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__ck_addr = VL_RAND_RESET_I(31); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__waddr = VL_RAND_RESET_I(12); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_primed = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__sdioscopei__DOT__mem__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__sdioscopei__DOT__mem__v0 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvset__main__DOT__sdioscopei__DOT__mem__v0 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v0 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v0 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v0 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v1 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v1 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v1 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v1 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v2 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v2 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v2 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v2 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v3 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v3 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v3 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v3 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v4 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v4 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v4 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v4 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v5 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v5 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v5 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v5 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v6 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v6 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v6 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v6 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v7 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v7 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v7 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v7 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v8 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v8 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v8 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v8 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v9 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v9 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v9 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v9 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v10 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v10 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v10 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v10 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v11 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v11 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v11 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v11 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v12 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v12 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v12 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v12 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v13 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v13 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v13 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v13 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v14 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v14 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v14 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v14 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v15 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v15 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v15 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v15 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v16 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v16 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v16 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v16 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v17 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v17 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v17 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v17 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v18 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v18 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v18 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v18 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v19 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v19 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v19 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v19 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v20 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v20 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v20 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v20 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v21 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v21 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v21 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v21 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v22 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v22 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v22 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v22 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v23 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v23 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v23 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v23 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v24 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v24 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v24 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v24 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v25 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v25 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v25 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v25 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v26 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v26 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v26 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v26 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v27 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v27 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v27 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v27 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v28 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v28 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v28 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v28 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v29 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v29 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v29 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v29 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v30 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v30 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v30 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v30 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v31 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v31 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v31 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v31 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v32 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v32 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v32 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v32 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v33 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v33 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v33 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v33 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v34 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v34 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v34 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v34 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v35 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v35 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v35 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v35 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v36 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v36 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v36 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v36 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v37 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v37 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v37 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v37 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v38 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v38 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v38 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v38 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v39 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v39 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v39 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v39 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v40 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v40 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v40 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v40 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v41 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v41 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v41 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v41 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v42 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v42 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v42 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v42 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v43 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v43 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v43 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v43 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v44 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v44 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v44 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v44 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v45 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v45 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v45 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v45 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v46 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v46 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v46 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v46 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v47 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v47 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v47 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v47 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v48 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v48 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v48 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v48 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v49 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v49 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v49 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v49 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v50 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v50 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v50 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v50 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v51 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v51 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v51 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v51 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v52 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v52 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v52 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v52 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v53 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v53 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v53 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v53 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v54 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v54 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v54 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v54 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v55 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v55 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v55 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v55 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v56 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v56 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v56 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v56 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v57 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v57 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v57 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v57 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v58 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v58 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v58 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v58 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v59 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v59 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v59 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v59 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v60 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v60 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v60 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v60 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v61 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v61 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v61 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v61 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v62 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v62 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v62 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v62 = 0; - vlSelf->__Vdlyvdim0__main__DOT__bkrami__DOT__mem__v63 = 0; - vlSelf->__Vdlyvlsb__main__DOT__bkrami__DOT__mem__v63 = 0; - vlSelf->__Vdlyvval__main__DOT__bkrami__DOT__mem__v63 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__bkrami__DOT__mem__v63 = 0; - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v0 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v1 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v2 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v3 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v4 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v5 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvval__main__DOT__clock_generator__DOT__counter__v6 = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__bus_err = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_cyc = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_addr = VL_RAND_RESET_I(22); - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__subaddr = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__r_overflow = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbwide_i2cdma_sel = VL_RAND_RESET_Q(64); - vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_sys = VL_RAND_RESET_I(13); - vlSelf->__Vdly__main__DOT__u_fan__DOT__ctl_fpga = VL_RAND_RESET_I(13); - vlSelf->__Vdly__main__DOT__u_fan__DOT__pwm_counter = VL_RAND_RESET_I(13); - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_reset = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_counter = VL_RAND_RESET_I(27); - vlSelf->__Vdly__main__DOT__u_fan__DOT__tach_timer = VL_RAND_RESET_I(27); - vlSelf->__Vdly__main__DOT__u_fan__DOT__trigger_counter = VL_RAND_RESET_I(17); - vlSelf->__Vdly__main__DOT__u_fan__DOT__temp_tmp = VL_RAND_RESET_I(24); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_jump_addr = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckcount = VL_RAND_RESET_I(12); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__ign_mem_cyc = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_addr = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn_addr = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_illegal = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = VL_RAND_RESET_I(4); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__rx_en = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr = VL_RAND_RESET_I(10); - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 0; - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0; - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0; - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 0; - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0; - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0; - vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg = VL_RAND_RESET_Q(48); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg = VL_RAND_RESET_Q(40); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rsp_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = VL_RAND_RESET_I(26); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_count = VL_RAND_RESET_I(4); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg = VL_RAND_RESET_Q(64); - VL_RAND_RESET_W(128, vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg); - VL_RAND_RESET_W(256, vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg = VL_RAND_RESET_I(20); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb = VL_RAND_RESET_I(4); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout = VL_RAND_RESET_I(23); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2ci__DOT__imm_cycle = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_jump_addr = VL_RAND_RESET_I(28); - vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckedge = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckcount = VL_RAND_RESET_I(12); - vlSelf->__Vdly__main__DOT__i2ci__DOT__r_halted = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbwide_i2cm_cyc = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbwide_i2cm_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__inflight = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__wbwide_i2cm_addr = VL_RAND_RESET_I(22); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(512, vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_count = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_insn_addr = VL_RAND_RESET_I(28); - vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_illegal = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state = VL_RAND_RESET_I(4); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__dir = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__ign_fifo_fill = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__wr_addr = VL_RAND_RESET_I(6); - vlSelf->__Vdlyvdim0__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0 = VL_RAND_RESET_I(5); - vlSelf->__Vdlyvset__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem__v0 = 0; - vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__rx_en = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_wraddr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_pipe_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr = VL_RAND_RESET_I(10); - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 0; - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0; - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0; - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 0; - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0; - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2 = 0; - vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0; - vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0; - vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3 = 0; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg = VL_RAND_RESET_Q(48); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg = VL_RAND_RESET_Q(40); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rsp_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout_counter = VL_RAND_RESET_I(26); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_count = VL_RAND_RESET_I(4); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg = VL_RAND_RESET_Q(64); - VL_RAND_RESET_W(128, vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg); - VL_RAND_RESET_W(256, vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_1w_reg = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_sreg = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg = VL_RAND_RESET_I(20); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__subaddr = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb = VL_RAND_RESET_I(4); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_timeout = VL_RAND_RESET_I(23); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_overflow = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__console__DOT__rxfifo__DOT__fifo__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__console__DOT__rxfifo__DOT__fifo__v0 = VL_RAND_RESET_I(7); - vlSelf->__Vdlyvset__main__DOT__console__DOT__rxfifo__DOT__fifo__v0 = 0; - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__will_underflow = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__rd_addr = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__console__DOT__rxfifo__DOT__r_fill = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_overflow = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__console__DOT__txfifo__DOT__fifo__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__console__DOT__txfifo__DOT__fifo__v0 = VL_RAND_RESET_I(7); - vlSelf->__Vdlyvset__main__DOT__console__DOT__txfifo__DOT__fifo__v0 = 0; - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__will_underflow = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__rd_addr = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__console__DOT__txfifo__DOT__r_fill = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_clear_cache = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_write = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__cmd_read_ack = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_value = VL_RAND_RESET_I(31); - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchdog__DOT__r_zero = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__wdt_reset = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__u_watchbus__DOT__r_value = VL_RAND_RESET_I(14); - vlSelf->__Vdly__main__DOT__swic__DOT__wdbus_int = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_value = VL_RAND_RESET_I(31); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_a__DOT__r_zero = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_value = VL_RAND_RESET_I(31); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_b__DOT__r_zero = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_value = VL_RAND_RESET_I(31); - vlSelf->__Vdly__main__DOT__swic__DOT__u_timer_c__DOT__r_zero = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__r_counter = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__int_when = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__delay = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_cyc = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0 = VL_RAND_RESET_I(16); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache_tags__v0 = 0; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_addr = VL_RAND_RESET_I(22); - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0 = 0; - VL_RAND_RESET_W(512, vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__cache__v0 = 0; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_illegal = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__dbg_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mtc_data = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__moc_data = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mpc_data = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__mic_data = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__utc_data = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uoc_data = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__upc_data = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__ACCOUNTING_COUNTERS__DOT__uic_data = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length = VL_RAND_RESET_I(28); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen = VL_RAND_RESET_I(11); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr = VL_RAND_RESET_I(28); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr = VL_RAND_RESET_I(28); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__fsm_state = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len = VL_RAND_RESET_I(11); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding = VL_RAND_RESET_I(11); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len = VL_RAND_RESET_I(11); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__pre_shift = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(1024, vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__sreg); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__wr_addr = VL_RAND_RESET_I(5); - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0 = 0; - VL_RAND_RESET_W(520, vlSelf->__Vdlyvval__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem__v0 = 0; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill = VL_RAND_RESET_I(7); - VL_RAND_RESET_W(512, vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state = VL_RAND_RESET_I(15); - vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable = VL_RAND_RESET_I(15); - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state = VL_RAND_RESET_I(15); - vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable = VL_RAND_RESET_I(15); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__holdoff_counter = VL_RAND_RESET_I(20); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stopped = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stop_pipe = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_inhibit = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_write = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__ck_addr = VL_RAND_RESET_I(31); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__waddr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_primed = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__i2cscopei__DOT__mem__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__i2cscopei__DOT__mem__v0 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvset__main__DOT__i2cscopei__DOT__mem__v0 = 0; - vlSelf->__Vdly__main__DOT__rcv__DOT__chg_counter = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__rcv__DOT__state = VL_RAND_RESET_I(4); - vlSelf->__Vdly__main__DOT__rcv__DOT__data_reg = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__rcv__DOT__baud_counter = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__rcv__DOT__zero_baud_counter = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__txv__DOT__r_busy = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__txv__DOT__lcl_data = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__txv__DOT__zero_baud_counter = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__txv__DOT__baud_counter = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_timer = VL_RAND_RESET_I(19); - vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_reset = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__hx_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__cw_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__compression_tbl__v0 = 0; - vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__wbu_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wide_addr = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_acks_needed = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_ack = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__zero_acks = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__r_len = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_read_request = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_word = VL_RAND_RESET_I(30); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__dw_bits = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__linelen = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__ln_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__wbu_tx_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter = VL_RAND_RESET_I(22); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cw_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_addr = VL_RAND_RESET_I(10); - vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__compression_tbl__v0 = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__rd_addr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_within_table = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__matched = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cp_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0 = VL_RAND_RESET_Q(36); - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0 = 0; - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr = VL_RAND_RESET_I(7); - vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0 = VL_RAND_RESET_Q(36); - vlSelf->__Vdlyvset__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0 = 0; - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr = VL_RAND_RESET_I(11); - vlSelf->__Vdly__main__DOT__genbus__DOT__ofifo_empty_n = VL_RAND_RESET_I(1); - vlSelf->__Vdly__o_gpio = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__spioi__DOT__r_led = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_BUTTON__DOT__btn_pipe = VL_RAND_RESET_I(10); - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__rr_sw = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__spioi__DOT__GEN_SWITCHES__DOT__sw_pipe = VL_RAND_RESET_I(16); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_owner = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__led_dir = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__0__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__1__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__2__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__3__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__4__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__5__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__6__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__spioi__DOT__knightrider__DOT__GEN_BRIGHTNESS__BRA__7__KET____DOT__brightness = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__ign_fifo_fill = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__wr_addr = VL_RAND_RESET_I(6); - vlSelf->__Vdlyvdim0__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0 = VL_RAND_RESET_I(4); - vlSelf->__Vdlyvset__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__mem__v0 = 0; - vlSelf->__Vdly__main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__rd_addr = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__emmcscopei__DOT__raddr = VL_RAND_RESET_I(12); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__sdioscopei__DOT__raddr = VL_RAND_RESET_I(12); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock = VL_RAND_RESET_I(2); - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0 = VL_RAND_RESET_I(32); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__core__DOT__regset__v0 = 0; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PROFILER__DOT__prof_ticks = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc = VL_RAND_RESET_I(28); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__thempy__DOT__IMPY__DOT__MPN1__DOT__MPN2__DOT__MPY3CK__DOT__mpypipe = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__last_bit = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_dividend = VL_RAND_RESET_Q(63); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_divisor = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVIDE__DOT__thedivide__DOT__r_sign = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_result = VL_RAND_RESET_I(32); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr = VL_RAND_RESET_I(22); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_iv = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cachable = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag = VL_RAND_RESET_I(19); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cache_miss = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0 = VL_RAND_RESET_I(12); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__fifo_data__v0 = 0; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__wraddr = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__OPT_PIPE_FIFO__DOT__rdaddr = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v = VL_RAND_RESET_I(8); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr = VL_RAND_RESET_I(22); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_line_stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__end_of_line = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state = VL_RAND_RESET_I(2); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb = VL_RAND_RESET_I(1); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__set_vflag = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0 = VL_RAND_RESET_I(19); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0 = 0; - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__wr_addr = VL_RAND_RESET_I(6); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending = VL_RAND_RESET_I(5); - vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack = VL_RAND_RESET_I(1); - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v0 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v1 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v2 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v3 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v4 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v5 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v6 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v7 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v8 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v9 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v10 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v11 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v12 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v13 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v14 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v15 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v16 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v17 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v18 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v19 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v20 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v21 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v22 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v23 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v24 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v25 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v26 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v27 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v28 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v29 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v30 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v31 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v32 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v33 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v34 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v35 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v36 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v37 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v38 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v39 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v40 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v41 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v42 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v43 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v44 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v45 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v46 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v47 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v48 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v49 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v50 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v51 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v52 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v53 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v54 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v55 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v56 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v57 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v58 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v59 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v60 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v61 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v62 = 0; - vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 = 0; - vlSelf->__Vdlyvlsb__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 = 0; - vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 = VL_RAND_RESET_I(8); - vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_mem__v63 = 0; - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config = VL_RAND_RESET_I(3); - vlSelf->__Vdly__main__DOT__i2cscopei__DOT__raddr = VL_RAND_RESET_I(10); - vlSelf->__Vtrigprevexpr___TOP__i_clk__0 = VL_RAND_RESET_I(1); - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 = VL_RAND_RESET_I(4); - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 = VL_RAND_RESET_I(4); - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 = VL_RAND_RESET_I(4); - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 = VL_RAND_RESET_I(4); - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 = VL_RAND_RESET_I(13); - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 = VL_RAND_RESET_I(3); - vlSelf->__Vtrigprevexpr___TOP__main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n__0 = VL_RAND_RESET_I(1); - vlSelf->__VactDidInit = 0; - for (int __Vi0 = 0; __Vi0 < 7; ++__Vi0) { - vlSelf->__Vm_traceActivity[__Vi0] = 0; - } -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__3.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__3.cpp deleted file mode 100644 index 45b5438..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__3.cpp +++ /dev/null @@ -1,8624 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -extern const VlWide<15>/*479:0*/ Vmain__ConstPool__CONST_hbd99daea_0; - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__3(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__3\n"); ); - // Init - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior = 0; - CData/*1:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout = 0; - SData/*15:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior = 0; - CData/*0:0*/ __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit = 0; - VlWide<16>/*511:0*/ __Vtemp_hb780e8f4__0; - VlWide<16>/*511:0*/ __Vtemp_hdb251f8c__0; - VlWide<16>/*511:0*/ __Vtemp_h12b8adbe__0; - // Body - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 8U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 9U)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 5U)) | ( - (0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xaU)) - | (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xeU)) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 3U)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xcU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0x11U)) - | ((0x20000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 4U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0x13U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x17U)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 6U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xaU)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x19U)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x1dU)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xcU)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x1bU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xeU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | ((4U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x11U)) | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 2U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xdU)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 2U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 6U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xbU)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 7U)) | ( - (0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 8U)) - | (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 9U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xcU)) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 5U)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xaU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 3U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xfU)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 2U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 2U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0x11U)) - | (0x80000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x15U)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 4U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x13U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 8U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x17U)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x1bU)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xaU)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x19U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xcU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 2U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x13U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 4U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xfU)) | - ((0x10U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 4U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xdU)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 9U)) | ( - (0x400U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 6U)) - | (0x200U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xbU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xaU)) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 7U)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 5U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xdU)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 4U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xbU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfff80000U & ((0x200000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xfU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x13U)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 2U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 6U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x15U)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x19U)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 8U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x17U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xaU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 4U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x15U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 6U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x11U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 2U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x13U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 2U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xfU)) - | (0x40U - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xbU)) | - ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 4U)) | - (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 8U)) | - ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 9U)) | - (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xbU)) - | ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 6U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 9U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 2U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xdU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x11U)) - | ((0x800000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 4U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x13U)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x17U)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 6U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 6U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x17U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 8U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x13U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 4U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffffffc0U & ((0x100U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | ((0x80U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x11U)) - | (0x40U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xdU)) | - ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 2U)) | - (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 6U)) | - ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xbU)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 9U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 9U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 8U)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 4U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xbU)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xfU)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 2U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 2U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x11U)) - | (0x2000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x15U)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 4U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x13U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 6U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 8U)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x19U)) | - (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xaU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x15U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 6U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x17U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 2U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x13U)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xfU)) | - ((0x400U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 4U)) | - ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xdU)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xbU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 7U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xaU)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 5U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 6U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 9U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xdU)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 4U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xbU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfe000000U & ((0x8000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xfU)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x13U)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 2U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x11U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 4U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xaU)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x1bU)) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xcU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x17U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 8U)) | (8U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x19U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 4U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x15U)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0x11U)) - | ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 2U)) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x13U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 2U)) | - ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xfU)) - | (0x1000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xdU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 5U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xcU)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 3U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 8U)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 7U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xaU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xbU)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 6U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 9U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 2U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xdU)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 4U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x11U)) - | ((0x20000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xfU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0x80000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffffff8U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | ((4U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xcU)) | ((2U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x1dU)) - | (1U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xeU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffffffc7U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x19U)) | - ((0x10U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xaU)) | - (8U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x1bU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 6U)) | ( - (0x80U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x17U)) - | (0x40U - & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 8U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0x13U)) - | ((0x400U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 4U)) - | (0x200U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x15U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffff8fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffff000U & ((0x4000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | ((0x2000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0x11U)) - | (0x1000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 2U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffff7fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0x8000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xfU))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 3U)) | - ((0x20000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xeU)) - | (0x10000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 1U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xaU)) - | ((0x100000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 5U)) - | (0x80000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xcU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 9U)) - | ((0x800000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 8U)) - | (0x400000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 7U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 4U)) - | ((0x4000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xbU)) - | (0x2000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 6U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0x8fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xfU)) - | ((0x20000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 2U)) - | (0x10000000U & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xdU)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0x7fffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0x80000000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U])); - if ((1U & (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [(((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - ? (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))]; - } - if ((1U & (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [(((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)) - ? (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))]; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = 0xfcU; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed - = (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]); - if ((0U == (0xffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed = 1U; - } - } - if (vlSelf->i_reset) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter = 0U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb = 0U; - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual = 0U; - vlSelf->main__DOT__i2ci__DOT__insn = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__r_reset = 1U; - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown)) - ? 0x300U : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - if (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_busy)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb = 1U; - } else if (((0U == (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len)) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb = 0U; - } - if ((((IData)(vlSelf->main__DOT__i2ci__DOT__bus_write) - & (0x1000000U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]))) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xdU)))) { - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - >> 0xbU)); - } else if (vlSelf->main__DOT__i2ci__DOT__bus_jump) { - vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual = 0U; - } - if (vlSelf->main__DOT__i2ci__DOT__next_valid) { - vlSelf->main__DOT__i2ci__DOT__insn = ((IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle) - ? - ((0xf00U - & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__next_insn)) - : - ((0xffU - & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)) - | (0xf00U - & ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - << 4U)))); - } else if (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready))) { - vlSelf->main__DOT__i2ci__DOT__insn = ((0xffU - & (IData)(vlSelf->main__DOT__i2ci__DOT__insn)) - | ((IData)(vlSelf->main__DOT__i2ci__DOT__half_insn) - << 8U)); - } - if ((0x10U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)))) { - if ((2U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) { - vlSelf->main__DOT__u_i2cdma__DOT__r_reset = 1U; - } - } else if ((1U & (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 4U)))) { - vlSelf->main__DOT__u_i2cdma__DOT__r_reset - = (((0U == vlSelf->main__DOT__u_i2cdma__DOT__r_memlen) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__bus_err)) - | (0x10000000U <= (vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr - + vlSelf->main__DOT__u_i2cdma__DOT__r_memlen))); - } - } - if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg = 0xffffffffU; - if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width))) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w; - } - } - } else if (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - & (1U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg = 0xffffffffU; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_last - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - ? vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b - : vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - >= (0xffffU & (((0xfU >= ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? ((IData)(1U) << - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - (IData)(1U))))); - } - if ((((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)))) { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode = 1U; - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - >> 1U) & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x30U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)))) - | ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x88U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)))))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode = 3U; - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) - & (9U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode = 2U; - } - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_ercode = 0U; - } - } - if ((1U & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err = 0U; - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err - = ((((0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)) - << 1U) | (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err - = ((((0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)) - << 1U) | (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err - = ((((0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)) - << 1U) | (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err - = ((((0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr)) - << 1U) | (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc))); - } - if ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active)) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done)))) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode = 1U; - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - >> 1U) & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x30U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)))) - | ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg)) - & (0x88U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)))))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode = 3U; - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) - & (9U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode = 2U; - } - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_ercode = 0U; - } - } - if ((1U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err = 0U; - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__lcl_err - = ((((0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)) - << 1U) | (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__lcl_err - = ((((0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)) - << 1U) | (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__lcl_err - = ((((0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)) - << 1U) | (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__lcl_err - = ((((0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr)) - << 1U) | (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc))); - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_bits - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__dw_bits; - vlSelf->main__DOT__i2cscopei__DOT__ck_addr = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__ck_addr; - vlSelf->main__DOT__i2cscopei__DOT__dr_force_write - = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_force_write; - vlSelf->main__DOT__i2cscopei__DOT__dr_stopped = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__dr_stopped; - vlSelf->main__DOT__emmcscopei__DOT__ck_addr = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__ck_addr; - vlSelf->main__DOT__emmcscopei__DOT__dr_force_write - = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_force_write; - vlSelf->main__DOT__emmcscopei__DOT__dr_stopped - = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__dr_stopped; - vlSelf->main__DOT__sdioscopei__DOT__ck_addr = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__ck_addr; - vlSelf->main__DOT__sdioscopei__DOT__dr_force_write - = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_force_write; - vlSelf->main__DOT__sdioscopei__DOT__dr_stopped - = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__dr_stopped; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr - = vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__wr_addr; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__dffaddr; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__wbwide_wbu_arbiter_stb))); - vlSelf->main__DOT__wbu_xbar__DOT__sgrant = vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__sgrant; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_valid; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[1U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[1U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[2U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[2U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[3U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[3U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[4U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[4U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[5U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[5U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[6U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[6U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[7U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[7U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[8U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[8U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[9U] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[9U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xaU] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xaU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xbU] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xbU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xcU] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xcU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xdU] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xdU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xeU] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xeU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU] - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_insn[0xfU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__cache_valid; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid; - vlSelf->main__DOT__i2ci__DOT__pf_valid = vlSelf->__Vdly__main__DOT__i2ci__DOT__pf_valid; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__next_subaddr; - if (vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v0) { - vlSelf->main__DOT__wb32_xbar__DOT__grant[0U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v1) { - vlSelf->main__DOT__wb32_xbar__DOT__grant[0U] - = vlSelf->__Vdlyvval__main__DOT__wb32_xbar__DOT__grant__v1; - } - if (vlSelf->__Vdlyvset__main__DOT__wb32_xbar__DOT__grant__v2) { - vlSelf->main__DOT__wb32_xbar__DOT__grant[0U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags[vlSelf->__Vdlyvdim0__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0] - = vlSelf->__Vdlyvval__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_vtags__v0; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr; - vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl)); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__nbits; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc; - vlSelf->main__DOT__u_fan__DOT__trigger_counter - = vlSelf->__Vdly__main__DOT__u_fan__DOT__trigger_counter; - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_i2cdma_stb) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__mem - [(0x1fU & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__rd_addr))]; - if (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty) { - vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data - = vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_data; - } - vlSelf->main__DOT__swic__DOT__wdbus_int = vlSelf->__Vdly__main__DOT__swic__DOT__wdbus_int; - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable - = vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable; - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state - = vlSelf->__Vdly__main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state; - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable - = vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable; - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state - = vlSelf->__Vdly__main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_length; - vlSelf->main__DOT__console__DOT__txf_status = (0x6000U - | (((IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__w_fill) - << 2U) - | (IData)(vlSelf->__VdfgTmp_ha46ae6a3__0))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate; - if (vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b[vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0))) - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b[vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1))) - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b[vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2))) - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b[vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3))) - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a[vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0))) - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a[vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1))) - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a[vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2))) - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a[vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3))) - & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [vlSelf->__Vdlyvdim0__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3)))); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__crc_fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__nedge_crc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__3__KET____DOT__pedge_crc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__nedge_crc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__2__KET____DOT__pedge_crc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__nedge_crc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__1__KET____DOT__pedge_crc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__nedge_crc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__GEN_RAIL_CRC__BRA__0__KET____DOT__pedge_crc; - vlSelf->main__DOT__i2cscopei__DOT__new_data = (1U - & ((~ - ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U)) - | (vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4 - != vlSelf->main__DOT__i2cscopei__DOT__qd_data))); - vlSelf->main__DOT__emmcscopei__DOT__new_data = - (1U & ((~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U)) | (vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4 - != vlSelf->main__DOT__emmcscopei__DOT__qd_data))); - vlSelf->main__DOT__sdioscopei__DOT__new_data = - (1U & ((~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U)) | (vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4 - != vlSelf->main__DOT__sdioscopei__DOT__qd_data))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb)) - | (~ (IData)((0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))))))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - = vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg; - if (((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid))) - & (1U == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw)))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word - = (0xb80000000ULL | (0x3fffffffULL - & vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_word)); - } - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy))))) { - if (vlSelf->main__DOT__genbus__DOT__ofifo_rd) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cw_stb = 1U; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - = vlSelf->main__DOT__genbus__DOT__ofifo_codword; - } else { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cw_stb - = (1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb)) - & (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent))) - | ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state)) - & (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter - >> 0x15U))))); - if (((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - = (0x100000000ULL | (0x3fffffffULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword)); - } else { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - = (0x3fffffffULL & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword); - if (vlSelf->main__DOT__wbu_cyc) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - = (0x40000000ULL | (0x3fffffffULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword)); - } - } - } - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)); - vlSelf->main__DOT__wbu_xbar__DOT__s_err = (0xcU - | ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_err))); - vlSelf->main__DOT__wbu_arbiter_upsz__DOT____Vcellinp__UPSIZE__DOT__u_fifo__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift - = (0x3fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__shift - = (0x3fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill)); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__r_last)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid)) - | ((0x40U > (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full))))))); - if (vlSelf->main__DOT__u_fan__DOT__mem_ack) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__cache_word - = vlSelf->main__DOT__u_fan__DOT__mem_data; - } - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_set - = ((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_jiffies__i_wb_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__new_set = 0U; - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst = 0U; - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__enable_ints) - & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1fU))) { - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__disable_ints) - & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1fU))) { - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_mie = 0U; - } - if (((((IData)(vlSelf->main__DOT__swic__DOT__dmac_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) { - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length - = (0xfffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len); - } - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst - = (0xfffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst); - } - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__sys_addr) - >> 1U)))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src - = (0xfffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src); - } - } - } else if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - << 6U); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr - << 6U); - } - } - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__till_wb - = ((vlSelf->main__DOT__swic__DOT__sys_data - - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter) - - ((IData)(vlSelf->main__DOT__swic__DOT__cmd_halt) - ? 0U : 1U)); - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_now - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & (((IData)(1U) + vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter) - == vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_when))); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__r_valid - = vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid; - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack))) { - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x10U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[1U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x11U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[2U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x12U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[3U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x13U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[4U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x14U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[5U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x15U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[6U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x16U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[7U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x17U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[8U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x18U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[9U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x19U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0xaU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1aU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0xbU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1bU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0xcU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1cU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0xdU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1dU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0xeU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1eU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__cache_word[0xfU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1fU]; - } - if ((0x10U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data - = (0xffffU & (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - >> (7U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)))); - } else if ((8U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data - = (0xffffU & ((vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 8U) >> (7U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)))); - } - if ((1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full = 0U; - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill - = (3U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill) - >> 3U)); - if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid) - & (0x3ffU == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full = 1U; - } - } - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb - = (1U & ((~ ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck)))) - & ((~ (IData)(vlSelf->i_emmc_cmd)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__resp_started)))); - if ((0x10U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data - = (0xffffU & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - >> (7U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)))); - } else if ((8U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_data - = (0xffffU & ((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - << 8U) >> (7U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)))); - } - if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full = 0U; - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_fill - = (3U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill) - >> 3U)); - if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid) - & (0x3ffU == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_full = 1U; - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb - = (1U & ((~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - | (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck)))) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__resp_started) - | ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in) - >> 1U))) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in))))))); - vlSelf->main__DOT__r_cfg_ack = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 0xaU)); - vlSelf->main__DOT__r_wb32_sio_ack = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U)); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full - = ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_full)); - vlSelf->main__DOT__wb32_i2cdma_ack = (1U & ((~ (IData)(vlSelf->i_reset)) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 4U))); - vlSelf->main__DOT__wb32_i2cs_ack = (1U & ((~ (IData)(vlSelf->i_reset)) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 3U))); - if ((1U & ((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc))))) { - vlSelf->main__DOT__wb32_xbar__DOT__mgrant = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available) { - vlSelf->main__DOT__wb32_xbar__DOT__mgrant = 1U; - } else if (vlSelf->main__DOT__wb32_xbar__DOT__m_stb) { - vlSelf->main__DOT__wb32_xbar__DOT__mgrant = 0U; - } - } - vlSelf->main__DOT__sdioscopei__DOT__br_wb_ack = - ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_pre_wb_ack) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 2U)); - vlSelf->main__DOT__i2cscopei__DOT__br_wb_ack = - ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_pre_wb_ack) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 1U)); - vlSelf->main__DOT__emmcscopei__DOT__br_wb_ack = - ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_pre_wb_ack) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - vlSelf->main__DOT__wb32_uart_ack = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 5U) & (IData)(vlSelf->main__DOT__console__DOT__r_wb_ack)); - vlSelf->main__DOT__wb32_sdcard_ack = ((~ ((IData)(vlSelf->i_reset) - | (~ - ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 8U)))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__pre_ack)); - vlSelf->main__DOT__wb32_fan_ack = ((~ ((IData)(vlSelf->i_reset) - | (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 7U)))) - & (IData)(vlSelf->main__DOT__u_fan__DOT__pre_ack)); - vlSelf->main__DOT__wb32_emmc_ack = ((~ ((IData)(vlSelf->i_reset) - | (~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 6U)))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_ack)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack - = (IData)(((6U == (6U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack)))); - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort = 1U; - } - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__last_ack = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__bus_abort = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__illegal_cache - = (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr - >> 3U)); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_cline - = (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_ctag - = (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_addr - >> 3U)); - vlSelf->main__DOT__swic__DOT__sys_cyc = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__dbg_cyc)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal)) - ? 0xdU : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_opn)); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err)))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce) - | ((~ ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack))) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid))) - | ((~ ((((1U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce)))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc)))))); - if (vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN) { - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckedge)) - | ((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_stretch) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__insn_ready)))))) { - vlSelf->main__DOT__i2ci__DOT__i2c_abort = 0U; - } else { - vlSelf->main__DOT__i2ci__DOT__i2c_abort = 0U; - if (((((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir)) - & (8U == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda))) { - vlSelf->main__DOT__i2ci__DOT__i2c_abort = 1U; - } - if (((((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir)) - & (5U == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))) - & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda) - != (1U & ((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg) - >> 7U))))) { - vlSelf->main__DOT__i2ci__DOT__i2c_abort = 1U; - } - if (((0xbU == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state)) - & ((IData)(vlSelf->main__DOT__i2ci__DOT__w_sda) - != (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda)))) { - vlSelf->main__DOT__i2ci__DOT__i2c_abort = 1U; - } - if (((0xcU == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state)) - & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)) - | (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda))))) { - vlSelf->main__DOT__i2ci__DOT__i2c_abort = 1U; - } - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)) - | (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda))))) { - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy = 1U; - } else if (vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__stop_bit) { - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy = 0U; - } - } else { - vlSelf->main__DOT__i2ci__DOT__i2c_abort = 0U; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__channel_busy = 0U; - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc - = (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword); - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc - = ((3U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc) - | (0xffffffcU & (((IData)(1U) + - ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc - >> 2U) + ((0x3ff8000U - & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU] - >> 0x11U)))) - << 0xfU)) - | (0x7fffU - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU] - >> 2U))))) - << 2U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc - = (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_M - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_R - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_cc) - << 6U) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_pc) - << 5U) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_wR - = (1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - | (8U == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))))); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp))); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc - = ((((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - == (1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)))) & (0xfU - == (0xfU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))))))); - vlSelf->main__DOT__u_fan__DOT__ck_tach = (1U & - ((IData)(vlSelf->main__DOT__u_fan__DOT__pipe_tach) - >> 1U)); - vlSelf->main__DOT__u_fan__DOT__pipe_tach = ((2U - & ((IData)(vlSelf->main__DOT__u_fan__DOT__pipe_tach) - << 1U)) - | (IData)(vlSelf->i_fan_tach)); - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge) { - if ((8U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - if ((4U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - if ((2U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - if ((1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0U; - } - } else if ((1U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - if ((1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0U; - } - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 1U; - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda)) - | (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0xaU; - } - } - } else if ((2U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - if ((1U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0xcU; - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda) - != (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0xaU; - } - } - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - if ((((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0U; - } - } - } else if ((1U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 3U; - } - } else { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state - = (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda)) - ? 9U : 2U); - } - } - } else if ((4U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - if ((2U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - if ((1U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda - = (1U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir) - | (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 8U; - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda - = (1U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir) - | (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - if ((1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)))) { - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir) { - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 7U; - } - } else if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda) - != (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 7U; - } - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 6U; - } - } - } else if ((1U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg - = ((0xfeU & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg) - << 1U)) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda)); - if ((0U < (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits - = (7U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits) - - (IData)(1U))); - } - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir) - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda) - != (1U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg) - >> 7U))))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0xaU; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state - = ((0U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits)) - ? 6U : 4U); - } - } else { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - } - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda - = (1U & (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg) - >> 7U) | (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda) - == (1U & (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg) - >> 7U) | (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir)))))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 5U; - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 4U; - } - } - } else if ((2U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - if ((1U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0U; - } - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg - = (0xffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready))) { - if ((0x400U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - if ((0x200U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - if ((0x100U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 4U; - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 4U; - } - } else if ((0x100U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 4U; - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 4U; - } - } else if ((0x200U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - if ((0x100U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 4U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg - = (0xffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)); - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 3U; - } - } else if ((0x100U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0xbU; - } - } - } - } else if ((1U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state - = ((4U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits)) - ? 4U : 2U); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 0U; - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg - = (0xffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)); - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir = 0U; - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready))) { - if ((0x400U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - if ((0x200U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - if ((0x100U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__last_byte = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - } - } else if ((0x100U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__will_ack = 0U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 1U; - } else { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - } - } else if ((0x200U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - if ((0x100U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits = 7U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg - = (0xffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)); - } - } else if ((0x100U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 1U; - } - } - } - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)))) { - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda = 1U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl = 1U; - vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state = 0U; - } - if (((((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid = 0U; - } else if (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid = 0U; - if (((((3U != (0xfU & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - >> 4U))) & (0xdU != - (0xfU & - ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - >> 4U)))) - & (0U != (0xfU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn)))) - & (9U != (0xfU & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - >> 4U))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid = 1U; - } - } else if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)); - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid)) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready)))) { - vlSelf->main__DOT__u_i2cdma__DOT____Vcellout__sskd__o_data - = ((IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid) - ? (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_data) - : (IData)(vlSelf->main__DOT__u_i2cdma__DOT____Vcellinp__sskd__i_data)); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU]; - if (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU] = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU] = 0U; - } - if (vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) { - __Vtemp_hdb251f8c__0[0U] = Vmain__ConstPool__CONST_hbd99daea_0[0U]; - __Vtemp_hdb251f8c__0[1U] = Vmain__ConstPool__CONST_hbd99daea_0[1U]; - __Vtemp_hdb251f8c__0[2U] = Vmain__ConstPool__CONST_hbd99daea_0[2U]; - __Vtemp_hdb251f8c__0[3U] = Vmain__ConstPool__CONST_hbd99daea_0[3U]; - __Vtemp_hdb251f8c__0[4U] = Vmain__ConstPool__CONST_hbd99daea_0[4U]; - __Vtemp_hdb251f8c__0[5U] = Vmain__ConstPool__CONST_hbd99daea_0[5U]; - __Vtemp_hdb251f8c__0[6U] = Vmain__ConstPool__CONST_hbd99daea_0[6U]; - __Vtemp_hdb251f8c__0[7U] = Vmain__ConstPool__CONST_hbd99daea_0[7U]; - __Vtemp_hdb251f8c__0[8U] = Vmain__ConstPool__CONST_hbd99daea_0[8U]; - __Vtemp_hdb251f8c__0[9U] = Vmain__ConstPool__CONST_hbd99daea_0[9U]; - __Vtemp_hdb251f8c__0[0xaU] = Vmain__ConstPool__CONST_hbd99daea_0[0xaU]; - __Vtemp_hdb251f8c__0[0xbU] = Vmain__ConstPool__CONST_hbd99daea_0[0xbU]; - __Vtemp_hdb251f8c__0[0xcU] = Vmain__ConstPool__CONST_hbd99daea_0[0xcU]; - __Vtemp_hdb251f8c__0[0xdU] = Vmain__ConstPool__CONST_hbd99daea_0[0xdU]; - __Vtemp_hdb251f8c__0[0xeU] = Vmain__ConstPool__CONST_hbd99daea_0[0xeU]; - __Vtemp_hdb251f8c__0[0xfU] = vlSelf->main__DOT__wb32_wbdown_idata; - VL_SHIFTR_WWI(512,512,32, __Vtemp_h12b8adbe__0, __Vtemp_hdb251f8c__0, - (0x1e0U & ((IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellout__DOWNSIZE__DOT__u_fifo__o_data) - << 5U))); - __Vtemp_hb780e8f4__0[1U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U] - | __Vtemp_h12b8adbe__0[1U]); - __Vtemp_hb780e8f4__0[2U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U] - | __Vtemp_h12b8adbe__0[2U]); - __Vtemp_hb780e8f4__0[3U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U] - | __Vtemp_h12b8adbe__0[3U]); - __Vtemp_hb780e8f4__0[4U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U] - | __Vtemp_h12b8adbe__0[4U]); - __Vtemp_hb780e8f4__0[5U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U] - | __Vtemp_h12b8adbe__0[5U]); - __Vtemp_hb780e8f4__0[6U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U] - | __Vtemp_h12b8adbe__0[6U]); - __Vtemp_hb780e8f4__0[7U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U] - | __Vtemp_h12b8adbe__0[7U]); - __Vtemp_hb780e8f4__0[8U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U] - | __Vtemp_h12b8adbe__0[8U]); - __Vtemp_hb780e8f4__0[9U] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U] - | __Vtemp_h12b8adbe__0[9U]); - __Vtemp_hb780e8f4__0[0xaU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU] - | __Vtemp_h12b8adbe__0[0xaU]); - __Vtemp_hb780e8f4__0[0xbU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU] - | __Vtemp_h12b8adbe__0[0xbU]); - __Vtemp_hb780e8f4__0[0xcU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU] - | __Vtemp_h12b8adbe__0[0xcU]); - __Vtemp_hb780e8f4__0[0xdU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU] - | __Vtemp_h12b8adbe__0[0xdU]); - __Vtemp_hb780e8f4__0[0xeU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU] - | __Vtemp_h12b8adbe__0[0xeU]); - __Vtemp_hb780e8f4__0[0xfU] = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU] - | __Vtemp_h12b8adbe__0[0xfU]); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U] - = (vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0U] - | __Vtemp_h12b8adbe__0[0U]); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[1U] - = __Vtemp_hb780e8f4__0[1U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[2U] - = __Vtemp_hb780e8f4__0[2U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[3U] - = __Vtemp_hb780e8f4__0[3U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[4U] - = __Vtemp_hb780e8f4__0[4U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[5U] - = __Vtemp_hb780e8f4__0[5U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[6U] - = __Vtemp_hb780e8f4__0[6U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[7U] - = __Vtemp_hb780e8f4__0[7U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[8U] - = __Vtemp_hb780e8f4__0[8U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[9U] - = __Vtemp_hb780e8f4__0[9U]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xaU] - = __Vtemp_hb780e8f4__0[0xaU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xbU] - = __Vtemp_hb780e8f4__0[0xbU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xcU] - = __Vtemp_hb780e8f4__0[0xcU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xdU] - = __Vtemp_hb780e8f4__0[0xdU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xeU] - = __Vtemp_hb780e8f4__0[0xeU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__nxt_data[0xfU] - = __Vtemp_hb780e8f4__0[0xfU]; - } - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__debug_pc) - | ((0x10U & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr)) - ? ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 1U)) : ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ipc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase) - << 1U)))); - if (((IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)))) { - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_addr - = vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr; - } - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__w_any - = (0U != ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_state) - & (IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__r_int_enable))); - vlSelf->main__DOT__gpioi__DOT__q_gpio = vlSelf->main__DOT__gpioi__DOT__x_gpio; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err))); - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))))) { - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) { - if ((0x20U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl)) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep - = (1U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 4U)); - } - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep - = (1U & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 4U) & ((~ (IData)(vlSelf->main__DOT__swic__DOT__pic_interrupt)) - | (~ (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 5U))))); - } - } - if ((1U & (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent = 0U; - } else if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_sent = 1U; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo = 0U; - } else if ((((((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xcU)); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w) - | (0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_2w_reg)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data - = ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((0x1000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((0x800U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((0x20U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | ((0x10U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | ((8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U)) - | (1U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data)))))))))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xfU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xeU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xdU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xcU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xbU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xaU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 9U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 8U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data - = ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((0x2000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((0x1000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((0x800U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((0x20U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((0x10U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | ((8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))))))))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_2w - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xfU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xeU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xdU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xcU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xbU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 0xaU)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 9U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 8U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__78__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC16__77__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffffff0U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xeU)) | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 1U))) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xfU)) | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xffffff0fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xcU)) | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 3U))) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xdU)) | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffff0ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xaU)) | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 5U))) - | ((0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 0xbU)) | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 4U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xffff0fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 8U)) | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 7U))) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 9U)) | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 6U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfff0ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 6U)) | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 9U))) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 7U)) | (0x10000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 8U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xff0fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 4U)) | (0x400000U & - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xbU))) - | ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 5U)) | (0x100000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xaU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xf0ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 2U)) | (0x4000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xdU))) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 3U)) | (0x1000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xcU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w - = ((0xfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_2w) - | (((0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xfU))) | ((0x20000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - >> 1U)) - | (0x10000000U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_2w - << 0xeU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffeULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | (IData)((IData)((1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffeffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 1U))))) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffeffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 2U))))) - << 0x20U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffeffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 3U))))) - << 0x30U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffdULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 4U))))) - << 1U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffdffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 5U))))) - << 0x11U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffdffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 6U))))) - << 0x21U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffdffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 7U))))) - << 0x31U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffffbULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 8U))))) - << 2U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffbffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 9U))))) - << 0x12U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffbffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xaU))))) - << 0x22U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffbffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xbU))))) - << 0x32U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffff7ULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xcU))))) - << 3U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffff7ffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xdU))))) - << 0x13U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffff7ffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xeU))))) - << 0x23U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfff7ffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0xfU))))) - << 0x33U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffefULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x10U))))) - << 4U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffefffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x11U))))) - << 0x14U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffefffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x12U))))) - << 0x24U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffefffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x13U))))) - << 0x34U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffdfULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x14U))))) - << 5U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffdfffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x15U))))) - << 0x15U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffdfffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x16U))))) - << 0x25U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffdfffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x17U))))) - << 0x35U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffffbfULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x18U))))) - << 6U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffbfffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x19U))))) - << 0x16U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffbfffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1aU))))) - << 0x26U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffbfffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1bU))))) - << 0x36U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffff7fULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1cU))))) - << 7U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffff7fffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1dU))))) - << 0x17U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffff7fffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1eU))))) - << 0x27U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xff7fffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x1fU))))) - << 0x37U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffeffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x20U))))) - << 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffeffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x21U))))) - << 0x18U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffeffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x22U))))) - << 0x28U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfeffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x23U))))) - << 0x38U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffdffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x24U))))) - << 9U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffdffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x25U))))) - << 0x19U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffdffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x26U))))) - << 0x29U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfdffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x27U))))) - << 0x39U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffffbffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x28U))))) - << 0xaU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffbffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x29U))))) - << 0x1aU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffbffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2aU))))) - << 0x2aU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfbffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2bU))))) - << 0x3aU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffffffff7ffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2cU))))) - << 0xbU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffffffff7ffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2dU))))) - << 0x1bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xfffff7ffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2eU))))) - << 0x2bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xf7ffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x2fU))))) - << 0x3bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffefffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x30U))))) - << 0xcU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffefffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x31U))))) - << 0x1cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffefffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x32U))))) - << 0x2cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xefffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x33U))))) - << 0x3cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffdfffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x34U))))) - << 0xdU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffdfffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x35U))))) - << 0x1dU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffdfffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x36U))))) - << 0x2dU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xdfffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x37U))))) - << 0x3dU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffffbfffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x38U))))) - << 0xeU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffbfffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x39U))))) - << 0x1eU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffbfffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3aU))))) - << 0x2eU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xbfffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3bU))))) - << 0x3eU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffffffff7fffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3cU))))) - << 0xfU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffffffff7fffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3dU))))) - << 0x1fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0xffff7fffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3eU))))) - << 0x2fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - = ((0x7fffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_4w_reg - >> 0x3fU))))) - << 0x3fU)); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | ((0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U)) - | (1U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data)))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior - = (0xffffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & (IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffffffff0000ULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | (IData)((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout))); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | ((0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) - | ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) - | ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x10U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & (IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffff0000ffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout)) - << 0x10U)); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | ((0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) - | ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) - | ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x20U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & (IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffff0000ffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout)) - << 0x20U)); - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data - = ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | ((0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) - | ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) - | ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) - | ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) - | ((4U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) - | ((2U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U)) - | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U))))))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior - = (0xffffU & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_4w - >> 0x30U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 7U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 6U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 5U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 4U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & ((IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit - = (1U & (IData)(vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill - = vlSelf->__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__80__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - = ((0xffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w) - | ((QData)((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC8__79__Vfuncout)) - << 0x30U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffffff8ULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | (IData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x20U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x10U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w))))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffffff7ULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x30U))))) - << 3U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffffff8fULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x21U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x11U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 1U))))))) - << 4U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffffff7fULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x31U))))) - << 7U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffff8ffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x22U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x12U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 2U))))))) - << 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffffff7ffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x32U))))) - << 0xbU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffff8fffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x23U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x13U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 3U))))))) - << 0xcU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffffff7fffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x33U))))) - << 0xfU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffff8ffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x24U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x14U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 4U))))))) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffffff7ffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x34U))))) - << 0x13U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffff8fffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x25U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x15U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 5U))))))) - << 0x14U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffffff7fffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x35U))))) - << 0x17U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffff8ffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x26U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x16U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 6U))))))) - << 0x18U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffffff7ffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x36U))))) - << 0x1bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffff8fffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x27U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x17U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 7U))))))) - << 0x1cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffffff7fffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x37U))))) - << 0x1fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffff8ffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x28U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x18U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 8U))))))) - << 0x20U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffffff7ffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x38U))))) - << 0x23U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffff8fffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x29U)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x19U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 9U))))))) - << 0x24U)); - if (vlSelf->main__DOT__genbus__DOT__r_wdt_reset) { - vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cw_stb = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffffff7fffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x39U))))) - << 0x27U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffff8ffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2aU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1aU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xaU))))))) - << 0x28U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfffff7ffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3aU))))) - << 0x2bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffff8fffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2bU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1bU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xbU))))))) - << 0x2cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xffff7fffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3bU))))) - << 0x2fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfff8ffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2cU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1cU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xcU))))))) - << 0x30U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xfff7ffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3cU))))) - << 0x33U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xff8fffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2dU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1dU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xdU))))))) - << 0x34U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xff7fffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3dU))))) - << 0x37U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xf8ffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2eU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1eU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xeU))))))) - << 0x38U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0xf7ffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3eU))))) - << 0x3bU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0x8fffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)(((4U & ((IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x2fU)) - << 2U)) | ((2U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x1fU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0xfU))))))) - << 0x3cU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w - = ((0x7fffffffffffffffULL & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_4w) - | ((QData)((IData)((1U & (IData)((vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_4w - >> 0x3fU))))) - << 0x3fU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x10U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x12U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x14U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x10U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0x10U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 3U))); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr = 0U; - } else if ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_width - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__cfg_ddr - = vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x8000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x14U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x12U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0x10U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]) - | (0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8w_reg[3U])); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U)) | (1U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data)))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U)) | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[0U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U)) | (1U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[1U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x19U)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1aU)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[2U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1bU)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data - = ((8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1cU)) | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | - ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U))))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8w[3U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 3U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 2U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__82__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC4__81__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 2U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xfU)) | - (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U])))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xbU)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 4U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffff3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 9U)) | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 6U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 9U)) | ( - (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 8U)) - | (0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 4U)) | - ((0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xbU)) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffff3fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 2U)) | - (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xdU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x10U)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 1U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xeU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 3U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x12U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 1U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xff3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 5U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x14U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x17U)) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 6U)) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xaU)) - | ((0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x19U)) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U] - = ((0x3fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[0U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xcU)) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x1bU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 2U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x13U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 4U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xfU)) | - ((0x10U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffff3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xdU)) | - (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 5U)) | ( - (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xcU)) - | (0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 3U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 8U)) | - ((0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 7U)) | - (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xaU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffff3fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 6U)) | - (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 9U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xcU)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 5U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xaU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 1U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xeU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 3U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xff3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 1U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x10U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0x13U)) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 2U)) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 6U)) - | ((0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x15U)) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U] - = ((0x3fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[1U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 8U)) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x17U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 6U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x17U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 8U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x13U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 4U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffff3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0x11U)) | - (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 1U)) | ( - (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x10U)) - | (0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 1U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0xcU)) - | ((0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 3U)) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xeU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffff3fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xaU)) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 5U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 8U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 9U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 5U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xaU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xff3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 3U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xcU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xfU)) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 2U)) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 2U)) - | ((0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0x11U)) - | (0x8000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U] - = ((0x3fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[2U]) - | (0xc0000000U & ((0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 4U)) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0x13U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xaU)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x1bU)) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xcU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x17U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 8U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x19U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffff3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffffc0U & ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0x15U)) | - (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 6U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffff00U & ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 3U)) | ( - (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0x14U)) - | (0x100U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 5U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffffc7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfffff800U & ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 0x10U)) - | ((0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 1U)) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0x12U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffff3fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffffc000U & ((0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 0xeU)) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 1U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 4U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 0xdU)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 9U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 6U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 0xbU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xff3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xffc00000U & ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - >> 7U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 8U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xf8ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xff000000U & ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - << 0xbU)) - | ((0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - >> 6U)) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[0U] - << 9U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0xc7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xf8000000U & ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - >> 2U)) - | ((0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[2U] - << 0xdU)) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[1U] - >> 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U] - = ((0x3fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8w[3U]) - | (0xc0000000U & ((0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8w[3U] - << 0xfU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffeU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffeffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - << 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffdU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0x1dU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffdffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[0U] - >> 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (4U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffffbU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffbffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffff7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfff7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[1U] - >> 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 2U))); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffefU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffefffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x200000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffdfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffdfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[2U] - >> 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffffbfU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffbfffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x800000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffff7fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xff7fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[3U] - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x100U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffeffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfeffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x2000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffdffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfdffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[4U] - >> 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x13U))); - if (vlSelf->main__DOT__genbus__DOT__r_wdt_reset) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = 0U; - vlSelf->main__DOT__wbu_cyc = 0U; - vlSelf->__Vdly__main__DOT__wbu_stb = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 0U; - } else { - if ((((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb))) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__zip_cpu_int)))) { - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_sent = 0U; - } - if ((2U & (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state))) { - if ((1U & (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state))) { - vlSelf->main__DOT__wbu_cyc = 0U; - vlSelf->__Vdly__main__DOT__wbu_stb = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 1U; - if (((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (1U != (3U & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x22U)))))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 0U; - } - } else { - vlSelf->main__DOT__wbu_cyc = 1U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 1U; - if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid)))) { - vlSelf->__Vdly__main__DOT__wbu_stb = 0U; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__wbu_stb)) - | (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))) { - if (((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (0x400000000ULL == (0xc00000000ULL - & vlSelf->main__DOT__genbus__DOT__ififo_codword)))) { - if (vlSelf->main__DOT__genbus__DOT__w_bus_busy) { - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 0U; - } else { - vlSelf->__Vdly__main__DOT__wbu_stb = 1U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 1U; - } - } else if ((((~ (IData)(vlSelf->main__DOT__wbu_stb)) - & (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__zero_acks)) - | ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - & (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_ack)))) { - vlSelf->main__DOT__wbu_cyc = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = 0U; - } - } - if (vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) { - vlSelf->main__DOT__wbu_cyc = 0U; - vlSelf->__Vdly__main__DOT__wbu_stb = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = 3U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 1U; - } - } - } else if ((1U & (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state))) { - vlSelf->main__DOT__wbu_cyc = 1U; - if ((1U & ((~ (IData)(vlSelf->main__DOT__wbu_stb)) - | (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))))) { - vlSelf->__Vdly__main__DOT__wbu_stb - = (1U & (~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_read_request))); - } - if (((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - & (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_ack))) { - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = 0U; - vlSelf->main__DOT__wbu_cyc = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 0U; - } - if (vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) { - vlSelf->__Vdly__main__DOT__wbu_stb = 0U; - vlSelf->main__DOT__wbu_cyc = 0U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 0U; - } - } else { - vlSelf->main__DOT__wbu_cyc = 0U; - vlSelf->__Vdly__main__DOT__wbu_stb = 0U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 0U; - if (((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__w_bus_busy)))) { - if ((1U & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x23U)))) { - if ((1U & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x22U)))) { - vlSelf->__Vdly__main__DOT__wbu_stb = 1U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = 1U; - vlSelf->main__DOT__wbu_cyc = 1U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 1U; - } - } else if ((1U & (IData)((vlSelf->main__DOT__genbus__DOT__ififo_codword - >> 0x22U)))) { - vlSelf->__Vdly__main__DOT__wbu_stb = 1U; - vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state = 2U; - vlSelf->main__DOT__wbu_cyc = 1U; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy = 1U; - } - } - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x400U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffffbffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfbffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x8000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xf7ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[5U] - >> 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x1000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffefffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xefffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x20000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffdfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xdfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[6U] - >> 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x1dU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x1bU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x19U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x17U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x15U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x13U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0x11U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffffbfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x4000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U])); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xbfffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]) - | (0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__crc_8d_reg[7U])); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU)) | (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x10U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[0U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x11U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 2U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x12U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 3U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[1U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x13U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 4U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x14U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 5U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[2U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x15U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 6U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x16U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 7U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[3U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x17U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 8U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x18U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 9U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[4U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x19U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xaU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1aU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xbU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[5U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1bU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xcU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1cU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xdU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[6U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1dU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xeU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U]); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - = ((0xffff0000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data - = ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0x1eU)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_data - >> 0xfU))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior - = (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__di_crc_8d[7U] - >> 0x10U); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__prior; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data) - >> 1U)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit - = (1U & (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__i_crc_data)); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout - = ((IData)((((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - >> 0xfU) ^ (IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__i_bit))) - ? (0x1021U ^ (0xfffeU & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))) : (0xfffeU - & ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__prior) - << 1U))); - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__STEPCRC__84__Vfuncout; - __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout - = __Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - = ((0xffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | ((IData)(__Vfunc_main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__APPLYCRC2__83__Vfuncout) - << 0x10U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 2U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xfU)) | - (1U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U])))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xbU)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 4U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 8U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 9U)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 5U)) | ( - (0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xaU)) - | (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xeU)) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 3U)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xcU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0x11U)) - | ((0x20000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U]) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 4U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0x13U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x17U)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 6U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xaU)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x19U)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x1dU)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xcU)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x1bU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[0U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xeU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | ((4U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]) - | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x11U)) | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 2U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xdU)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 2U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 6U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xbU)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 7U)) | ( - (0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 8U)) - | (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 9U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xcU)) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 5U)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xaU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 3U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xfU)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 2U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 2U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0x11U)) - | (0x80000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x15U)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 4U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x13U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 8U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x17U)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x1bU)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xaU)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x19U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[1U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xcU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 2U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x13U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 4U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xfU)) | - ((0x10U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 4U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xdU)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 9U)) | ( - (0x400U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 6U)) - | (0x200U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xbU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xaU)) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 7U)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 5U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xdU)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 4U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 0xbU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfff80000U & ((0x200000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U]) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xfU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x13U)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 2U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 6U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x15U)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x19U)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 8U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x17U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[2U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xaU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 4U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x15U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 6U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x11U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 2U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x13U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 2U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0xfU)) - | (0x40U - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xbU)) | - ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 4U)) | - (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 8U)) | - ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 9U)) | - (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 7U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 0xbU)) - | ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 6U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 9U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 2U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xdU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0x11U)) - | ((0x800000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U]) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 4U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x13U)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x17U)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 6U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[3U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 6U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x17U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 8U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x13U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 4U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffffffc0U & ((0x100U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]) - | ((0x80U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x11U)) - | (0x40U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xdU)) | - ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 2U)) | - (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 6U)) | - ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xbU)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 9U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 9U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 8U)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 4U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 0xbU)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xfU)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 2U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 2U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0x11U)) - | (0x2000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x15U)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 4U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x13U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[4U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 6U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 8U)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x19U)) | - (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xaU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x15U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 6U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x17U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 2U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x13U)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0xfU)) | - ((0x400U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 4U)) | - ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xdU)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xbU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 7U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xaU)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 5U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 6U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 9U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xdU)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 4U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 0xbU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xfe000000U & ((0x8000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U]) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xfU)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x13U)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 2U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0x11U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[5U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 4U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xaU)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x1bU)) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xcU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x17U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 8U)) | (8U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x19U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 4U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x15U)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0x11U)) - | ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 2U)) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x13U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfffff000U & ((0x4000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 2U)) | - ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0xfU)) - | (0x1000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xdU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 5U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xcU)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 3U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 8U)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 7U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xaU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 0xbU)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 6U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 9U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 2U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xdU)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 4U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0x11U)) - | ((0x20000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U]) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xfU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[6U]) - | (0x80000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffffff8U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | ((4U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xcU)) | ((2U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0x1dU)) - | (1U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xeU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffffffc7U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffffff8U & ((0x20U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0x19U)) | - ((0x10U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xaU)) | - (8U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0x1bU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffffe3fU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffffffc0U & ((0x100U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 6U)) | ( - (0x80U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 0x17U)) - | (0x40U - & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 8U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfffff1ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffffe00U & ((0x800U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 0x13U)) - | ((0x400U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 4U)) - | (0x200U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 0x15U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffff8fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfffff000U & ((0x4000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U]) - | ((0x2000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 0x11U)) - | (0x1000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 2U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffff7fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0x8000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - >> 0xfU))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfff8ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffff0000U & ((0x40000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - << 3U)) | - ((0x20000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - >> 0xeU)) - | (0x10000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[0U] - << 1U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfff80000U & ((0x200000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - >> 0xaU)) - | ((0x100000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[2U] - << 5U)) - | (0x80000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[1U] - >> 0xcU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xfe3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xffc00000U & ((0x1000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - << 9U)) - | ((0x800000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - >> 8U)) - | (0x400000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[3U] - << 7U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0xf1ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xfe000000U & ((0x8000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - >> 4U)) - | ((0x4000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[5U] - << 0xbU)) - | (0x2000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[4U] - >> 6U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0x8fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0xf0000000U & ((0x40000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U] - << 0xfU)) - | ((0x20000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - >> 2U)) - | (0x10000000U & (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[6U] - << 0xdU)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U] - = ((0x7fffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__nxt_crc_8d[7U]) - | (0x80000000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__new_crc_8d[7U])); - if ((1U & (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_b - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [(((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - ? (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))]; - } - if ((1U & (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_a - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [(((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)) - ? (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr))]; - } - if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done = 1U; - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type; - } - if ((1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = 0U; - } else if (((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)) - & (0U != (3U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = 1U; - } - if ((1U & (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb = 0U; - } else if (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = (0xffffU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds) - ? ((IData)(0x10U) + ((0x1fffU - & ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk))) - + ((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) - ? 0x10U - : 0U))) - : ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((IData)(0x10U) + - ((0xfff8U & (((IData)(1U) - << (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk)) - << 3U)) - + ((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) - ? 0x10U : 0U))) - : ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((IData)(0x10U) - + ((0x3ffeU & - (((IData)(1U) - << (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk)) - << 1U)) - + ((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) - ? 0x10U - : 0U))) - : ((IData)(0x10U) - + ((0x1fffU & - ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk))) - + ((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) - ? 0x10U - : 0U))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc = 0U; - } else if ((3U == ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 1U))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = (0xffffU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count) - - (IData)(2U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb - = (3U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - if (vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase - = (0x22U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc - = ((0x22U >= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)) - & (2U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))); - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase - = (0x12U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc - = ((0x12U >= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)) - & (2U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))); - } - if ((2U > (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = 0U; - } - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = (0xffffU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count) - - (IData)(1U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb - = (2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - if (vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase - = (0x21U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc - = ((0x21U >= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)) - & (1U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))); - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase - = (0x11U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc - = ((0x11U >= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)) - & (1U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))); - } - if ((1U > (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = 0U; - } - } - if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_done = 1U; - } - if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = 0U; - } else if (((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count)) - & (0U != (3U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_frame_err = 1U; - } - if ((1U & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done)) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb = 0U; - } else if (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = (0xffffU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds) - ? ((IData)(0x10U) + ((0x1fffU - & ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk))) - + ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - ? 0x10U - : 0U))) - : ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((IData)(0x10U) + - ((0xfff8U & (((IData)(1U) - << (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk)) - << 3U)) - + ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - ? 0x10U : 0U))) - : ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width)) - ? ((IData)(0x10U) - + ((0x3ffeU & - (((IData)(1U) - << (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk)) - << 1U)) - + ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - ? 0x10U - : 0U))) - : ((IData)(0x10U) - + ((0x1fffU & - ((IData)(1U) - << (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk))) - + ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - ? 0x10U - : 0U))))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc = 0U; - } else if ((3U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 1U))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = (0xffffU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count) - - (IData)(2U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb - = (3U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - if (vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase - = (0x22U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc - = ((0x22U >= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)) - & (2U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))); - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase - = (0x12U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc - = ((0x12U >= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)) - & (2U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))); - } - if ((2U > (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = 0U; - } - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = (0xffffU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count) - - (IData)(1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__last_strb - = (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - if (vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase - = (0x21U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc - = ((0x21U >= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)) - & (1U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))); - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase - = (0x11U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__load_crc - = ((0x11U >= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count)) - & (1U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))); - } - if ((1U > (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count = 0U; - } - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__deword__DOT__r_len; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__linepacker__DOT__r_busy) - | (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__ln_stb)); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cp_stb; - vlSelf->main__DOT__i2cscopei__DOT__br_config = vlSelf->__Vdly__main__DOT__i2cscopei__DOT__br_config; - vlSelf->main__DOT__emmcscopei__DOT__br_config = vlSelf->__Vdly__main__DOT__emmcscopei__DOT__br_config; - vlSelf->main__DOT__sdioscopei__DOT__br_config = vlSelf->__Vdly__main__DOT__sdioscopei__DOT__br_config; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw - = vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb - = vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__cw_stb; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb - = vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_state; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__idle_counter; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__int_when - = vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__int_when; - vlSelf->main__DOT__swic__DOT__u_jiffies__DOT__r_counter - = vlSelf->__Vdly__main__DOT__swic__DOT__u_jiffies__DOT__r_counter; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_sreg; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_addr; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_strb; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid; - vlSelf->main__DOT__wb32_wbdown_stb = ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__wraddr; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_addr; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_cyc; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_ack; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_dvalid; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__dir - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__dir; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__sreg; - vlSelf->main__DOT__i2ci__DOT__w_sda = vlSelf->__Vdly__main__DOT__i2ci__DOT__w_sda; - vlSelf->main__DOT__i2ci__DOT__i2c_ckedge = vlSelf->__Vdly__main__DOT__i2ci__DOT__i2c_ckedge; - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state - = vlSelf->__Vdly__main__DOT__i2ci__DOT__u_axisi2c__DOT__state; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__nbits; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - vlSelf->main__DOT__u_i2cdma__DOT__bus_err = vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__bus_err; - vlSelf->main__DOT____Vcellinp__swic__i_dbg_addr - = (0x7fU & ((IData)(vlSelf->cpu_sim_cyc) ? (IData)(vlSelf->cpu_sim_addr) - : (IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_saddr - >> 0x1bU)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate; - if (vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b[vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0))) - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v0)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b[vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1))) - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v1)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b[vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2))) - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v2)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b[vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3))) - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b - [vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_b__v3)))); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr; - if (vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a[vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0))) - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v0)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a[vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1))) - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v1)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a[vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2))) - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v2)))); - } - if (vlSelf->__Vdlyvset__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a[vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3] - = (((~ ((IData)(0xffU) << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3))) - & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a - [vlSelf->__Vdlyvdim0__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3]) - | (0xffffffffULL & ((IData)(vlSelf->__Vdlyvval__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3) - << (IData)(vlSelf->__Vdlyvlsb__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fifo_a__v3)))); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__rx_done; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_timeout; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__rx_sreg; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__rx_done; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__rail_count; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_busy - = vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)); - vlSelf->main__DOT__i2cscopei__DOT__qd_data = vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4; - vlSelf->main__DOT__i2cscopei__DOT__bw_reset_request - = (1U & (~ ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 2U))); - vlSelf->main__DOT__i2cscopei__DOT__dw_trigger = - ((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_primed) - & (((~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted)) - | ((IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config) - >> 1U))); - vlSelf->main__DOT__i2cscope_int = (IData)(((((IData)(vlSelf->main__DOT__i2cscopei__DOT__dr_stop_pipe) - >> 4U) - & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_config))) - & (~ (IData)(vlSelf->main__DOT__i2cscopei__DOT__br_level_interrupt)))); - vlSelf->main__DOT__emmcscopei__DOT__qd_data = vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4; - vlSelf->main__DOT__emmcscopei__DOT__bw_reset_request - = (1U & (~ ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 2U))); - vlSelf->main__DOT__emmcscope_int = (IData)(((((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_stop_pipe) - >> 4U) - & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config))) - & (~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_level_interrupt)))); - vlSelf->main__DOT__sdioscopei__DOT__qd_data = vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4; - vlSelf->main__DOT__sdioscopei__DOT__bw_reset_request - = (1U & (~ ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 2U))); - vlSelf->main__DOT__sdioscope_int = (IData)(((((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_stop_pipe) - >> 4U) - & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config))) - & (~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_level_interrupt)))); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__cod_busy - = (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb)); - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid - = (1U & (vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__remap - [(0x7fU & (IData)(vlSelf->main__DOT__wbu_rx_data))] - >> 6U)); - } - if (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy)))) { - if ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg - = ((0x3fffffffULL & vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg) - | ((QData)((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits)) - << 0x1eU)); - } else if ((4U & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len) - >> 1U)))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg - = ((1U & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len)) - ? ((0xfffffffc0ULL & vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg) - | (IData)((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits))) - : ((0xffffff03fULL & vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg) - | ((QData)((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits)) - << 6U))); - } - } else { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg - = ((2U & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len)) - ? ((1U & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len)) - ? ((0xffffc0fffULL & vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg) - | ((QData)((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits)) - << 0xcU)) : ((0xfff03ffffULL - & vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg) - | ((QData)((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits)) - << 0x12U))) - : ((1U & (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len)) - ? ((0xfc0ffffffULL & vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg) - | ((QData)((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits)) - << 0x18U)) : ((0x3fffffffULL - & vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__shiftreg) - | ((QData)((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits)) - << 0x1eU)))); - } - } - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__addr_zcheck - = (((0U == (0xffU & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 0x18U)))) << 3U) - | (((0U == (0x3fU & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 0x12U)))) - << 2U) | (((0U == (0x3fU & (IData)((vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 0xcU)))) - << 1U) | (0U == (0x3fU & (IData)( - (vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_codword - >> 6U))))))); - if (((IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow)))) { - vlSelf->main__DOT__genbus__DOT__ofifo_codword - = vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo - [(0x3ffU & (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr))]; - } -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__4.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__4.cpp deleted file mode 100644 index 869a660..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__4.cpp +++ /dev/null @@ -1,19962 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -extern const VlUnpacked Vmain__ConstPool__TABLE_h13ae860a_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h3e5c4ef2_0; -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h611c22d1_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h92ecbd6e_0; -extern const VlUnpacked Vmain__ConstPool__TABLE_h695e6748_0; -extern const VlWide<15>/*479:0*/ Vmain__ConstPool__CONST_hbd99daea_0; - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__4(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__4\n"); ); - // Init - CData/*0:0*/ main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0; - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 = 0; - CData/*0:0*/ main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0; - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 = 0; - CData/*0:0*/ main__DOT__wbu_xbar__DOT____VdfgTmp_h4f7f05b5__0; - main__DOT__wbu_xbar__DOT____VdfgTmp_h4f7f05b5__0 = 0; - CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0; - main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0 = 0; - CData/*0:0*/ main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0; - main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0 = 0; - CData/*0:0*/ main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0; - main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0 = 0; - CData/*0:0*/ main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0; - main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0 = 0; - CData/*0:0*/ main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0; - main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0 = 0; - CData/*0:0*/ main__DOT__swic__DOT____VdfgTmp_hcb574c13__0; - main__DOT__swic__DOT____VdfgTmp_hcb574c13__0 = 0; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0; - main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0 = 0; - CData/*0:0*/ main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_h832f938f__0; - main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_h832f938f__0 = 0; - CData/*5:0*/ __Vtableidx1; - __Vtableidx1 = 0; - CData/*4:0*/ __Vtableidx8; - __Vtableidx8 = 0; - CData/*2:0*/ __Vtableidx10; - __Vtableidx10 = 0; - VlWide<16>/*511:0*/ __Vtemp_h3711b190__0; - VlWide<16>/*511:0*/ __Vtemp_h18146fff__0; - VlWide<16>/*511:0*/ __Vtemp_h8c81192e__0; - VlWide<16>/*511:0*/ __Vtemp_h5dad54bf__0; - VlWide<16>/*511:0*/ __Vtemp_h01ff8f7b__0; - VlWide<16>/*511:0*/ __Vtemp_hf1acda43__0; - VlWide<16>/*511:0*/ __Vtemp_he3c3974d__0; - VlWide<16>/*511:0*/ __Vtemp_h0ca773d0__0; - VlWide<16>/*511:0*/ __Vtemp_hbc743227__0; - VlWide<16>/*511:0*/ __Vtemp_h6409050d__0; - VlWide<32>/*1023:0*/ __Vtemp_h7be7356a__0; - VlWide<32>/*1023:0*/ __Vtemp_h448dc795__0; - VlWide<32>/*1023:0*/ __Vtemp_h9b90904f__0; - VlWide<4>/*127:0*/ __Vtemp_hd96f9696__0; - VlWide<4>/*127:0*/ __Vtemp_h6aa6ab78__0; - // Body - __Vtableidx1 = (((IData)(vlSelf->main__DOT__u_fan__DOT__mem_addr) - << 1U) | (IData)(vlSelf->main__DOT__u_fan__DOT__mem_stb)); - if (Vmain__ConstPool__TABLE_h13ae860a_0[__Vtableidx1]) { - vlSelf->main__DOT__u_fan__DOT__mem_data = Vmain__ConstPool__TABLE_h3e5c4ef2_0 - [__Vtableidx1]; - } - vlSelf->main__DOT__u_fan__DOT__mem_ack = ((~ (IData)(vlSelf->i_reset)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__mem_stb)); - if ((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]][0xfU]; - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x13U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x14U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x15U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x16U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x17U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x18U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x19U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1aU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1bU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1cU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1dU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1eU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1fU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]][0xfU]; - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x10U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x11U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x12U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x13U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x14U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x15U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x16U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x17U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x18U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x19U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1aU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1bU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1cU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1dU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1eU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1fU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]][0xfU]; - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x30U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x31U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x32U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x33U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x34U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x35U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x36U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x37U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x38U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x39U] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3aU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3bU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3cU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3dU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3eU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3fU] - = vlSelf->main__DOT__wbwide_xbar__DOT__s_data - [vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]][0xfU]; - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x30U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x31U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x32U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x33U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x34U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x35U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x36U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x37U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x38U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x39U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3aU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3bU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3cU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3dU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3eU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x3fU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = ((0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)) - | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_ack) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U])))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc))) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = ((0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)) - | (2U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_ack) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]) << 1U)))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 1U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = ((0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)) - | (4U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_ack) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]) << 2U)))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 2U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = ((7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)) - | ((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_ack) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]))) << 3U)); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 3U))) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__resp_started = 0U; - } else if (((~ (IData)(vlSelf->i_emmc_cmd)) & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__resp_started = 1U; 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- vlSelf->main__DOT__u_fan__DOT__pre_ack = (1U & - ((~ ((IData)(vlSelf->i_reset) - | (~ - ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 7U)))) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 7U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__pre_ack - = (1U & ((~ ((IData)(vlSelf->i_reset) | (~ - ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 6U)))) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) { - vlSelf->main__DOT__swic__DOT__cpu_addr = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_addr; - vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_gbl; - } else { - vlSelf->main__DOT__swic__DOT__cpu_addr = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_addr; - vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_cyc; - } - __Vtableidx10 = (7U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__pre_sel - = Vmain__ConstPool__TABLE_h611c22d1_0[__Vtableidx10]; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_opn - = (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)); - if ((((0xcU == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_noop)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_lock))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_opn = 0xdU; - } - } - __Vtableidx8 = ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)) - & (IData)((0x78800000U == (0xfffc0000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU])))) - << 4U) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp) - << 3U) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid) - << 2U) | - (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset))))); - if ((1U & Vmain__ConstPool__TABLE_h92ecbd6e_0[__Vtableidx8])) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch - = Vmain__ConstPool__TABLE_h695e6748_0[__Vtableidx8]; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb - = Vmain__ConstPool__TABLE_h695e6748_0[__Vtableidx8]; - main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0 - = ((0U == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state)) - | (2U == (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__state))); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__stop_bit - = ((IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN) - & ((((IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_scl)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda)) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_sda)))); - vlSelf->main__DOT__i2ci__DOT__s_tvalid = ((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - & ((~ - ((IData)(vlSelf->main__DOT__i2ci__DOT__insn) - >> 0xbU)) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_wait)))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address; - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc; - } - vlSelf->main__DOT__swic__DOT__cpu_i_count = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_pc_valid)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error)))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wF)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & (((IData)(vlSelf->main__DOT__swic__DOT__cmd_clear_cache) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 0xeU)))); - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN) { - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)) - | (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy = 1U; - } else if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__stop_bit) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy = 0U; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge)) - | ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready)))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = 0U; - } else { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = 0U; - if (((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir)) - & (8U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = 1U; - } - if (((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir)) - & (5U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))) - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda) - != (1U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg) - >> 7U))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = 1U; - } - if (((0xbU == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state)) - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda) - != (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = 1U; - } - if (((0xcU == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state)) - & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)) - | (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = 1U; - } - } - } else { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__channel_busy = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_abort = 0U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid)))) { - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_data - = vlSelf->main__DOT__u_i2cdma__DOT____Vcellinp__sskd__i_data; - } - vlSelf->main__DOT__gpioi__DOT__x_gpio = vlSelf->i_gpio; - vlSelf->main__DOT__swic__DOT__pic_interrupt = ( - (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)) - & ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie) - & (IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_last - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_fifo_last - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr) - >= (0xffffU & (((0xfU >= ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - ? ((IData)(1U) << - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - - (IData)(2U))) - : 0U) - (IData)(1U))))); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done - = (1U & (~ (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid)) - | (0U != (0x18U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)))) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid)))); - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__busy)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = 0U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb - = (1U & ((~ (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck))) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)))) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__io_started) - | (~ (IData)(vlSelf->i_emmc_dat))))); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response = 0U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response - = (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)); - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done - = (1U & (~ (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__data_phase) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__pending_crc)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__s2_valid)) - | (0U != (0x18U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__sync_fill)))) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__mem_valid)))); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__r_watchdog) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__busy)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_rxframe__DOT__w_done = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb - = ((~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - | (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck)))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__io_started)); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__aword_valid) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__tbl_busy)); - vlSelf->main__DOT__swic__DOT__alt_int_vector = - (((IData)(vlSelf->main__DOT__i2cscope_int) - << 0xeU) | ((0x2000U & ((~ (IData)(vlSelf->main__DOT__console__DOT__rxfifo__DOT__will_underflow)) - << 0xdU)) | ((0x1000U - & ((~ (IData)(vlSelf->main__DOT__console__DOT__txfifo__DOT__will_overflow)) - << 0xcU)) - | (((IData)(vlSelf->main__DOT__emmc_int) - << 0xbU) - | (((IData)(vlSelf->main__DOT__sdioscope_int) - << 0xaU) - | (((IData)(vlSelf->main__DOT__emmcscope_int) - << 9U) - | (((IData)(vlSelf->main__DOT__swic__DOT__mtc_int) - << 7U) - | (((IData)(vlSelf->main__DOT__swic__DOT__moc_int) - << 6U) - | (((IData)(vlSelf->main__DOT__swic__DOT__mpc_int) - << 5U) - | (((IData)(vlSelf->main__DOT__swic__DOT__mic_int) - << 4U) - | (((IData)(vlSelf->main__DOT__swic__DOT__utc_int) - << 3U) - | (((IData)(vlSelf->main__DOT__swic__DOT__uoc_int) - << 2U) - | (((IData)(vlSelf->main__DOT__swic__DOT__upc_int) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__uic_int)))))))))))))); - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len - = vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len - = vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len; - if (vlSelf->__Vdlyvset__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0) { - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo[vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0] - = vlSelf->__Vdlyvval__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__fifo__v0; - } - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr - = vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__r_rdptr; - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow - = vlSelf->__Vdly__main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__GEN_IDLES__DOT__buildcw__DOT__int_request; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb - = vlSelf->__Vdly__main__DOT__genbus__DOT__wroutput__DOT__cw_stb; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__zero_acks - = vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__zero_acks; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_ack - = vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_ack; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__last_read_request - = vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__last_read_request; - vlSelf->main__DOT__genbus__DOT__runwb__DOT__wb_state - = vlSelf->__Vdly__main__DOT__genbus__DOT__runwb__DOT__wb_state; - vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack - = vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n - = vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n; - vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = vlSelf->__Vdly__main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->main__DOT__genbus__DOT__r_wdt_reset = vlSelf->__Vdly__main__DOT__genbus__DOT__r_wdt_reset; - vlSelf->main__DOT__u_fan__DOT__mem_addr = vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_addr; - vlSelf->main__DOT__u_fan__DOT__mem_stb = vlSelf->__Vdly__main__DOT__u_fan__DOT__mem_stb; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][1U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][2U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][3U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][4U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][5U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][6U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][7U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][8U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][9U] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xaU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xbU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xcU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xdU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xeU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[0U][0xfU] - = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0U] - = vlSelf->main__DOT__wbwide_bkram_idata[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][1U] - = vlSelf->main__DOT__wbwide_bkram_idata[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][2U] - = vlSelf->main__DOT__wbwide_bkram_idata[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][3U] - = vlSelf->main__DOT__wbwide_bkram_idata[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][4U] - = vlSelf->main__DOT__wbwide_bkram_idata[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][5U] - = vlSelf->main__DOT__wbwide_bkram_idata[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][6U] - = vlSelf->main__DOT__wbwide_bkram_idata[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][7U] - = vlSelf->main__DOT__wbwide_bkram_idata[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][8U] - = vlSelf->main__DOT__wbwide_bkram_idata[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][9U] - = vlSelf->main__DOT__wbwide_bkram_idata[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xaU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xbU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xcU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xdU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xeU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[1U][0xfU] - = vlSelf->main__DOT__wbwide_bkram_idata[0xfU]; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_wr - = ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr)); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty - = ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_wr)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__r_empty)); - vlSelf->main__DOT__swic__DOT__cpu_stall = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)) - | ((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 2U))); - vlSelf->main__DOT__i2ci__DOT__insn_ready = ((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_ckedge) - & (IData)(main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0)); - if (vlSelf->i_reset) { - vlSelf->main__DOT__i2ci__DOT__half_insn = 0U; - } else if (vlSelf->main__DOT__i2ci__DOT__next_valid) { - vlSelf->main__DOT__i2ci__DOT__half_insn = ((IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle) - ? 0U - : - (0xfU - & (IData)(vlSelf->main__DOT__i2ci__DOT__next_insn))); - } else if (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready))) { - vlSelf->main__DOT__i2ci__DOT__half_insn = 0U; - } - vlSelf->main__DOT__i2ci__DOT__imm_cycle = vlSelf->__Vdly__main__DOT__i2ci__DOT__imm_cycle; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - = ((0U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index))) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_val - : ((1U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_index))) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_result - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_result)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid)); - if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_wR) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_valid) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wreg) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__dir; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__sreg; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_sda; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state; - vlSelf->main__DOT__u_i2cdma__DOT____Vcellinp__sskd__i_data - = (((IData)(vlSelf->main__DOT__i2c_last) << 8U) - | (IData)(vlSelf->main__DOT__i2c_data)); - if (vlSelf->i_reset) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid = 0U; - } else { - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle) - ? ((0xf00U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn)) - : ((0xffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)) - | (0xf00U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - << 4U)))); - } else if (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn - = ((0xffU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn)) - | ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn) - << 8U)); - } - if ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (0x1000000U == (0x3000000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]))) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1dU)))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - >> 0xbU)); - } else if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual = 0U; - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__skd_valid)) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__skd_ready)))) { - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid - = ((IData)(vlSelf->main__DOT____Vcellinp__u_i2cdma__S_VALID) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid)); - } - } - vlSelf->main__DOT____Vcellinp__u_i2cdma__S_VALID - = ((IData)(vlSelf->main__DOT__i2c_valid) & - (2U == (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid))); - vlSelf->main__DOT__u_i2cdma__DOT__skd_ready = (1U - & ((IData)(vlSelf->main__DOT__u_i2cdma__DOT__r_reset) - | ((~ (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)) - | (IData)(vlSelf->main__DOT__u_i2cdma__DOT__bus_err)))); - vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid - = vlSelf->__Vdly__main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err = 1U; - } else if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - > (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb = 1U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall)))) { - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len = 0U; - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len - = (0x7ffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb = 1U; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - = (0x3fffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr - >> 6U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr - = (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size; - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding) - == ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack) - ? 1U : 0U)) & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc = 0U; - } - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_err = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - = (0x3fffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - >> 6U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr - = (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__wb_outstanding; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_request; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)) - | (IData)(vlSelf->main__DOT__swic__DOT__dc_stall))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr = 0U; - } else if ((1U & (((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy)) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err)) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr - = (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last = 0U; - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy = 0U; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr - = (0x3fffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr - >> 6U)); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc = 0U; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb = 0U; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr - = (0x3fffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - >> 6U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr - = (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr); - } - if ((0x10000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full)))) { - if ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last) - & (0U != vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel)) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc = 1U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb = 1U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding) - + ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb) - ? 1U : 0U)) == ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack) - ? 1U : 0U))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy - = (1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last))); - } - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last; - } - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_addr; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_err; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_request; - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__w_any - = (0U != ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_state) - & (IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_int_enable))); - vlSelf->main__DOT__genbus__DOT__wroutput__DOT____Vcellinp__GEN_IDLES__DOT__buildcw__i_tx_busy - = ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_busy) - & (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb)); - if ((1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb)) - | (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy))))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_hexbits - = (0x3fU & vlSelf->main__DOT__genbus__DOT__getinput__DOT__tobits__DOT__remap - [(0x7fU & (IData)(vlSelf->main__DOT__wbu_rx_data))]); - } - vlSelf->main__DOT__genbus__DOT__ofifo_rd = ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cw_stb)) - & (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)); - vlSelf->main__DOT__genbus__DOT__w_bus_busy = vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd - = ((~ (IData)(vlSelf->main__DOT__genbus__DOT__runwb__DOT__r_busy)) - & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)); - vlSelf->main__DOT__wbu_err = vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__clear_table - = ((IData)(vlSelf->main__DOT__genbus__DOT__r_wdt_reset) - | ((IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__cp_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__wroutput__DOT__dw_stb)) - & (0x200000000ULL == (0xe00000000ULL - & vlSelf->main__DOT__genbus__DOT__wroutput__DOT__GEN_COMPRESSION__DOT__packit__DOT__r_cword))))); - if (((IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow)))) { - vlSelf->main__DOT__genbus__DOT__ififo_codword - = vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo - [(0x3fU & (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr))]; - } - if (vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset) { - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } else if ((((IData)(vlSelf->main__DOT__wbu_stb) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready)) - & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid = 0U; - } - main__DOT__wbu_xbar__DOT____VdfgTmp_h4f7f05b5__0 - = ((IData)(vlSelf->main__DOT__wbu_cyc) & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb)); - if (vlSelf->main__DOT____Vcellinp__swic__i_reset) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - } else if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - } else { - if (((((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_write)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall))) - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_cmd_write)) - & (((~ vlSelf->main__DOT__swic__DOT__dbg_idata) - & (IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0)) - | (IData)(vlSelf->main__DOT__swic__DOT__step_request)))) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 0U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cpu_break) - & (IData)(vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch))) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__dbg_cmd_write) - & (IData)(vlSelf->main__DOT__swic__DOT__halt_request)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__step_request)))) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - } - if (vlSelf->main__DOT__swic__DOT__dbg_cpu_write) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_step) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__step_request)))) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - } - if (vlSelf->main__DOT__swic__DOT__cmd_clear_cache) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - } - if (vlSelf->main__DOT__swic__DOT__clear_cache_request) { - vlSelf->main__DOT__swic__DOT__cmd_halt = 1U; - } - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_pending_interrupt)); - vlSelf->main__DOT__swic__DOT__cmd_step = ((~ (IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset)) - & ((~ - (((((((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__cpu_break)) - | (IData)(vlSelf->main__DOT__swic__DOT__reset_request)) - | (IData)(vlSelf->main__DOT__swic__DOT__clear_cache_request)) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_clear_cache)) - | (IData)(vlSelf->main__DOT__swic__DOT__halt_request)) - | (IData)(vlSelf->main__DOT__swic__DOT__dbg_cpu_write))) - & (((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_write)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall))) - & (IData)(vlSelf->main__DOT__swic__DOT__step_request)))); - __Vtemp_h3711b190__0[0U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x10U]; - __Vtemp_h3711b190__0[1U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x11U]; - __Vtemp_h3711b190__0[2U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x12U]; - __Vtemp_h3711b190__0[3U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x13U]; - __Vtemp_h3711b190__0[4U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x14U]; - __Vtemp_h3711b190__0[5U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x15U]; - __Vtemp_h3711b190__0[6U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x16U]; - __Vtemp_h3711b190__0[7U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x17U]; - __Vtemp_h3711b190__0[8U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x18U]; - __Vtemp_h3711b190__0[9U] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x19U]; - __Vtemp_h3711b190__0[0xaU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1aU]; - __Vtemp_h3711b190__0[0xbU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1bU]; - __Vtemp_h3711b190__0[0xcU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1cU]; - __Vtemp_h3711b190__0[0xdU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1dU]; - __Vtemp_h3711b190__0[0xeU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1eU]; - __Vtemp_h3711b190__0[0xfU] = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x1fU]; - VL_SHIFTL_WWI(512,512,32, __Vtemp_h18146fff__0, __Vtemp_h3711b190__0, - ((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__r_shift) - << 3U)); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0U] - = __Vtemp_h18146fff__0[0U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[1U] - = __Vtemp_h18146fff__0[1U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[2U] - = __Vtemp_h18146fff__0[2U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[3U] - = __Vtemp_h18146fff__0[3U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[4U] - = __Vtemp_h18146fff__0[4U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[5U] - = __Vtemp_h18146fff__0[5U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[6U] - = __Vtemp_h18146fff__0[6U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[7U] - = __Vtemp_h18146fff__0[7U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[8U] - = __Vtemp_h18146fff__0[8U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[9U] - = __Vtemp_h18146fff__0[9U]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xaU] - = __Vtemp_h18146fff__0[0xaU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xbU] - = __Vtemp_h18146fff__0[0xbU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xcU] - = __Vtemp_h18146fff__0[0xcU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xdU] - = __Vtemp_h18146fff__0[0xdU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xeU] - = __Vtemp_h18146fff__0[0xeU]; - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__i_wb_shifted[0xfU] - = __Vtemp_h18146fff__0[0xfU]; - if (vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc) { - vlSelf->main__DOT__swic__DOT__cpu_idata[0U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x20U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[1U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x21U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[2U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x22U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[3U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x23U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[4U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x24U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[5U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x25U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[6U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x26U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[7U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x27U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[8U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x28U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[9U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x29U]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2aU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2bU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2cU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2dU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2eU]; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_mdata[0x2fU]; - } else { - vlSelf->main__DOT__swic__DOT__cpu_idata[0U] - = vlSelf->main__DOT__swic__DOT__sys_idata; - vlSelf->main__DOT__swic__DOT__cpu_idata[1U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[2U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[3U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[4U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[5U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[6U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[7U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[8U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[9U] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU] = 0U; - } - vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__w_rd - = ((~ (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__u_fifo__DOT__r_empty)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 3U)); - vlSelf->main__DOT__swic__DOT__cpu_ack = (((IData)(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_ack)) - | ((IData)(vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U) - & (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)))); - vlSelf->main__DOT__swic__DOT__dc_ack = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U))); - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_err) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U])))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - | (1U & (~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr)))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc))) - | (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - | (2U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_err) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]) << 1U)))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - | (2U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr) - >> 1U)) << 1U))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr) - >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - | (4U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_err) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]) << 2U)))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - | (4U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr) - >> 2U)) << 2U))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 2U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr) - >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - | ((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_err) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]))) << 3U)); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = ((7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)) - | (8U & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr) - >> 3U)) << 3U))); - } - if ((1U & (((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 3U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr) - >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr)); - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__resp_started = 0U; - } else if (((0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck)) - & (0U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__resp_started = 1U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p) - << 1U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n)); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__u_fifo__DOT__w_rd - = ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty)) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack)); - vlSelf->main__DOT__wbwide_wbdown_stall = (1U & - ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_first) - | (((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_stb) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_full))) - | ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_last)) - | ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__fifo_empty)) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__s_null)))))); - vlSelf->main__DOT__zip_cpu_int = ((~ (IData)(vlSelf->main__DOT__swic__DOT__cpu_stall)) - & (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stall - = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_stall) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)) - | (IData)(vlSelf->main__DOT__swic__DOT__cpu_stall))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_haf314c36__0 - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb)); - if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase = 0U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase - = (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_phase)) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU] - >> 0x1fU)) & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal))); - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase = 0U; - } - vlSelf->main__DOT__i2ci__DOT__half_ready = (1U - & (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_wait)) - & ((IData)(vlSelf->main__DOT__i2ci__DOT__insn_ready) - | ((IData)(vlSelf->main__DOT__i2ci__DOT__insn) - >> 0xbU))) - | (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual))); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_sda - = (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda))); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__lst_scl - = (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl))); - vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0 - = (((IData)(vlSelf->main__DOT__i2ci__DOT__r_wait) - << 0x17U) | (((IData)(vlSelf->main__DOT__i2ci__DOT__soft_halt_request) - << 0x16U) | (((IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted) - << 0x15U) | - (((IData)(vlSelf->main__DOT__i2ci__DOT__r_err) - << 0x14U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - << 0x13U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - << 0x12U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle) - << 0x10U) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_scl) - << 0xfU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__o_sda) - << 0xeU) - | (((IData)(vlSelf->i_i2c_scl) - << 0xdU) - | (((IData)(vlSelf->i_i2c_sda) - << 0xcU) - | (IData)(vlSelf->main__DOT__i2ci__DOT__insn))))))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bisrc - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - ? (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)))) - ? 1U : ((0x40U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - ? 2U : 3U)) : 0U); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Aid)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB))) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Bv); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__stop_bit - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN) - & ((((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_scl)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda)) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_sda)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - & ((~ ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn) - >> 0xbU)) & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait)))); - main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0 - = ((0U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state)) - | (2U == (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__state))); - vlSelf->main__DOT__u_i2cdma__DOT__skd_valid = vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__REG_OUTPUT__DOT__ro_valid; - vlSelf->main__DOT__i2cdma_ready = (1U & (~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__i2c_ready = (1U & ((~ (IData)(vlSelf->main__DOT__i2c_valid)) - | ((0U == (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid)) - | ((1U - == (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid)) - | (((~ (IData)(vlSelf->main__DOT__u_i2cdma__DOT__sskd__DOT__LOGIC__DOT__r_valid)) - & (2U - == (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid))) - | (2U - < (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_TID__DOT__axis_tid))))))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size; - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size - = ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size)) - ? 1U : ((3U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len)) - ? 1U : 2U)); - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_size))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size - = (((4U <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len)) - & (8U > (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len))) - ? (0x7fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - - (IData)(4U))) : 4U); - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size = 0x40U; - if ((0x40U > ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__nxtstb_size - = (0x7fU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_len) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size))); - } - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr - = ((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - << 6U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__subaddr)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stall)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr - = (0xfffffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_addr - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdstb_size))); - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy) { - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last - = (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len) - <= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size)) - & (0x40U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill))); - } else if ((0U == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last = 1U; - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last - = ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? (1U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen)) - : ((0x7ffffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr - >> 1U)) != (0x7ffffffU - & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - >> 1U)))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((0x3ffffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr - >> 2U)) != (0x3ffffffU - & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - >> 2U))) - : ((0x3fffffU & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr - >> 6U)) != (0x3fffffU - & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - >> 6U))))); - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy) { - if (((((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full))) - & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - = (((QData)((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[0U]))); - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel = 0ULL; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid = 0U; - } else { - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready))) { - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last - = (1U < (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last - = (1U == (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])); - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last - = (2U < (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last - = (2U >= (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])); - } - } else if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last - = (4U < (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last - = (4U >= (0x7fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U])); - } else { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last - = (1U & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U] - >> 7U)); - } - if ((1U & (~ (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U] - >> 7U)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last = 0U; - } - } else if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready))) { - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last) - & (2U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last) - & (2U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))); - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last) - & (4U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last) - & (4U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))); - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_last - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size) - & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last) - & (8U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill)))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size) - & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last) - & (8U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill)))); - } - } - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_valid)) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid - = (((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready)) - | ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size)) - ? (1U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill)) - : (2U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size) - & (4U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill))))); - } - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty = 1U; - } else if ((1U == (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty - = (1U >= (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill)); - } else if ((2U == (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty = 0U; - } - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie = 0U; - } else if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie = 1U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ALU_SIM__DOT__regid - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U) | (0xfU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_SIM__DOT__r_op_sim_immv)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcA_v) - | (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - ? (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc) - : ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_pcB_v) - | (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - ? (0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_pc) - : ((0xffffffcU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_PC__DOT__r_upc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0 - = (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__iflags)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0 - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags_ce)) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_flags) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__flags)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__pic_interrupt)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_spreg_vl - >> 5U) & (0xeU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))); - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response - = (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type)); - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response = 0U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & (((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_mem_valid) - & (3U <= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr)))) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - & (0x30U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width = 0U; - vlSelf->main__DOT__u_emmc__DOT__cfg_ddr = 0U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width - = ((0x800U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]) - ? 2U : ((0x400U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]) - ? 1U : 0U)); - vlSelf->main__DOT__u_emmc__DOT__cfg_ddr = (1U - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 8U)); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) - & ((~ (IData)(vlSelf->o_emmc_clk)) & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__last_ck)))); - if ((1U & (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)) - | (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__io_started = 0U; - } else if (((~ (IData)(vlSelf->i_emmc_dat)) & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__io_started = 1U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_done - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__waiting_on_response) - & (((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_mem_valid) - & (3U <= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__mem_addr)))) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type) - & (0x30U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__resp_count))))); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width = 0U; - vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr = 0U; - } else { - if ((((((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xcU)); - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U)))) { - if ((0x800U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])) { - if ((0x400U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width = 1U; - } - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width - = ((0x400U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]) - ? 1U : 0U); - } - vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 8U)); - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - ? ((((~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - >> 7U)) & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__last_ck)) - << 1U) | (IData)((0x80U == (0x88U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk))))) - : 0U)); - if ((1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__io_started = 0U; - } else if (((0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck)) - & (0U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck) - & ((2U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat) - >> 7U)) | (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat))))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__io_started = 1U; - } - vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb - = vlSelf->__Vdly__main__DOT__genbus__DOT__getinput__DOT__hx_stb; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy - = (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))) - & (((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)))); - if (((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__cw_stb) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__GEN_COMPRESSION__DOT__unpack__DOT__r_stb))) - & (~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid))) - & (1U == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw)))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy = 1U; - } - if (((((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid)) - & (1U == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw))) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len))) - & ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len)))) { - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy = 1U; - } - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_write - = ((IData)(vlSelf->main__DOT__genbus__DOT__exec_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_overflow)) - | (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd))); - vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__w_read - = (1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__GEN_OUTBOUND_FIFO__DOT__busoutfifo__DOT__will_underflow)) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_empty_n)) - | (IData)(vlSelf->main__DOT__genbus__DOT__ofifo_rd)))); - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_write - = ((IData)(vlSelf->main__DOT__genbus__DOT__in_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_overflow)) - | (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd))); - if (vlSelf->__Vdlyvset__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0) { - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo[vlSelf->__Vdlyvdim0__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0] - = vlSelf->__Vdlyvval__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__fifo__v0; - } - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr - = vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__r_rdptr; - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow - = vlSelf->__Vdly__main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow; - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbu_cyc)) - | (IData)(vlSelf->i_reset))); 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- vlSelf->main__DOT__swic__DOT__cmd_clear_cache = vlSelf->__Vdly__main__DOT__swic__DOT__cmd_clear_cache; - vlSelf->main__DOT__swic__DOT__cmd_write = vlSelf->__Vdly__main__DOT__swic__DOT__cmd_write; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_halted)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_dbg_stall))); - VL_SHIFTL_WWI(512,512,32, __Vtemp_h8c81192e__0, vlSelf->main__DOT__swic__DOT__cpu_idata, 0x1e0U); - VL_SHIFTL_WWI(512,512,32, __Vtemp_h5dad54bf__0, __Vtemp_h8c81192e__0, - (0x18U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0) - << 3U))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_svalid) { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_iword[0xfU]; - } else if ((2U == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__state))) { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__cpu_idata[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__cpu_idata[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__cpu_idata[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__cpu_idata[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__cpu_idata[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__cpu_idata[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__cpu_idata[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__cpu_idata[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__cpu_idata[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__cpu_idata[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__cpu_idata[0xfU]; - } else { - __Vtemp_h01ff8f7b__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0U]; - __Vtemp_h01ff8f7b__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[1U]; - __Vtemp_h01ff8f7b__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[2U]; - __Vtemp_h01ff8f7b__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[3U]; - __Vtemp_h01ff8f7b__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[4U]; - __Vtemp_h01ff8f7b__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[5U]; - __Vtemp_h01ff8f7b__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[6U]; - __Vtemp_h01ff8f7b__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[7U]; - __Vtemp_h01ff8f7b__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[8U]; - __Vtemp_h01ff8f7b__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[9U]; - __Vtemp_h01ff8f7b__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xaU]; - __Vtemp_h01ff8f7b__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xbU]; - __Vtemp_h01ff8f7b__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xcU]; - __Vtemp_h01ff8f7b__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xdU]; - __Vtemp_h01ff8f7b__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xeU]; - __Vtemp_h01ff8f7b__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cached_rword[0xfU]; - } - VL_SHIFTL_WWI(512,512,32, __Vtemp_hf1acda43__0, __Vtemp_h01ff8f7b__0, - (0x1f8U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT____VdfgTmp_h05977c6b__0) - << 3U))); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cyc_lcl) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0U] - = __Vtemp_h5dad54bf__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[1U] - = __Vtemp_h5dad54bf__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[2U] - = __Vtemp_h5dad54bf__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[3U] - = __Vtemp_h5dad54bf__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[4U] - = __Vtemp_h5dad54bf__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[5U] - = __Vtemp_h5dad54bf__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[6U] - = __Vtemp_h5dad54bf__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[7U] - = __Vtemp_h5dad54bf__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[8U] - = __Vtemp_h5dad54bf__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[9U] - = __Vtemp_h5dad54bf__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xaU] - = __Vtemp_h5dad54bf__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xbU] - = __Vtemp_h5dad54bf__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xcU] - = __Vtemp_h5dad54bf__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xdU] - = __Vtemp_h5dad54bf__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xeU] - = __Vtemp_h5dad54bf__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xfU] - = __Vtemp_h5dad54bf__0[0xfU]; - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0U] - = __Vtemp_hf1acda43__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[1U] - = __Vtemp_hf1acda43__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[2U] - = __Vtemp_hf1acda43__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[3U] - = __Vtemp_hf1acda43__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[4U] - = __Vtemp_hf1acda43__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[5U] - = __Vtemp_hf1acda43__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[6U] - = __Vtemp_hf1acda43__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[7U] - = __Vtemp_hf1acda43__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[8U] - = __Vtemp_hf1acda43__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[9U] - = __Vtemp_hf1acda43__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xaU] - = __Vtemp_hf1acda43__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xbU] - = __Vtemp_hf1acda43__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xcU] - = __Vtemp_hf1acda43__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xdU] - = __Vtemp_hf1acda43__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xeU] - = __Vtemp_hf1acda43__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__pre_shifted[0xfU] - = __Vtemp_hf1acda43__0[0xfU]; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ack - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__cpu_ack)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ack - = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_ack) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)); - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v0) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[0U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v1) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[0U] - = vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v1; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v2) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[0U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v3) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[1U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v4) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[1U] - = vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v4; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v5) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[1U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v6) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[2U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v7) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[2U] - = vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v7; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v8) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[2U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v9) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[3U] = 0U; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v10) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[3U] - = vlSelf->__Vdlyvval__main__DOT__wbwide_xbar__DOT__grant__v10; - } - if (vlSelf->__Vdlyvset__main__DOT__wbwide_xbar__DOT__grant__v11) { - vlSelf->main__DOT__wbwide_xbar__DOT__grant[3U] = 0U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled - = (1U & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cyc) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_we)) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__stb)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stall)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__r_rd_pending) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__npending) - >> 4U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_haf314c36__0)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal - = vlSelf->__Vdly__main__DOT__swic__DOT__thecpu__DOT__pf_illegal; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__isrc) { - __Vtemp_he3c3974d__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0U]; - __Vtemp_he3c3974d__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[1U]; - __Vtemp_he3c3974d__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[2U]; - __Vtemp_he3c3974d__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[3U]; - __Vtemp_he3c3974d__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[4U]; - __Vtemp_he3c3974d__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[5U]; - __Vtemp_he3c3974d__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[6U]; - __Vtemp_he3c3974d__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[7U]; - __Vtemp_he3c3974d__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[8U]; - __Vtemp_he3c3974d__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[9U]; - __Vtemp_he3c3974d__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xaU]; - __Vtemp_he3c3974d__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xbU]; - __Vtemp_he3c3974d__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xcU]; - __Vtemp_he3c3974d__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xdU]; - __Vtemp_he3c3974d__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xeU]; - __Vtemp_he3c3974d__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc_cache[0xfU]; - } else { - __Vtemp_he3c3974d__0[0U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0U]; - __Vtemp_he3c3974d__0[1U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[1U]; - __Vtemp_he3c3974d__0[2U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[2U]; - __Vtemp_he3c3974d__0[3U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[3U]; - __Vtemp_he3c3974d__0[4U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[4U]; - __Vtemp_he3c3974d__0[5U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[5U]; - __Vtemp_he3c3974d__0[6U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[6U]; - __Vtemp_he3c3974d__0[7U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[7U]; - __Vtemp_he3c3974d__0[8U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[8U]; - __Vtemp_he3c3974d__0[9U] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[9U]; - __Vtemp_he3c3974d__0[0xaU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xaU]; - __Vtemp_he3c3974d__0[0xbU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xbU]; - __Vtemp_he3c3974d__0[0xcU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xcU]; - __Vtemp_he3c3974d__0[0xdU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xdU]; - __Vtemp_he3c3974d__0[0xeU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xeU]; - __Vtemp_he3c3974d__0[0xfU] = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_last_cache[0xfU]; - } - VL_SHIFTL_WWI(512,512,32, __Vtemp_h0ca773d0__0, __Vtemp_he3c3974d__0, - (0x1e0U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_pc - << 3U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0U] - = __Vtemp_h0ca773d0__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[1U] - = __Vtemp_h0ca773d0__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[2U] - = __Vtemp_h0ca773d0__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[3U] - = __Vtemp_h0ca773d0__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[4U] - = __Vtemp_h0ca773d0__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[5U] - = __Vtemp_h0ca773d0__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[6U] - = __Vtemp_h0ca773d0__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[7U] - = __Vtemp_h0ca773d0__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[8U] - = __Vtemp_h0ca773d0__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[9U] - = __Vtemp_h0ca773d0__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xaU] - = __Vtemp_h0ca773d0__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xbU] - = __Vtemp_h0ca773d0__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xcU] - = __Vtemp_h0ca773d0__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xdU] - = __Vtemp_h0ca773d0__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xeU] - = __Vtemp_h0ca773d0__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU] - = __Vtemp_h0ca773d0__0[0xfU]; - main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0 = - (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__half_ready))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_request_address - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_haf314c36__0) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_branch_pc - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pf_pc); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0)) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_gpreg_vl - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_Av); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_brev_result - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x1fU) | ((0x40000000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x1dU)) - | ((0x20000000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x1bU)) - | ((0x10000000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x19U)) - | ((0x8000000U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x17U)) - | ((0x4000000U & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x15U)) | - ((0x2000000U & - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x13U)) - | ((0x1000000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0x11U)) - | ((0x800000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0xfU)) - | ((0x400000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0xdU)) - | ((0x200000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 0xbU)) - | ((0x100000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 9U)) - | ((0x80000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 7U)) - | ((0x40000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 5U)) - | ((0x20000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 3U)) - | ((0x10000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 1U)) - | ((0x8000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 1U)) - | ((0x4000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 3U)) - | ((0x2000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 5U)) - | ((0x1000U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 7U)) - | ((0x800U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U)) - | ((0x400U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0xbU)) - | ((0x200U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0xdU)) - | ((0x100U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0xfU)) - | ((0x80U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x11U)) - | ((0x40U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x13U)) - | ((0x20U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x15U)) - | ((0x10U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x17U)) - | ((8U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x19U)) - | ((4U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1bU)) - | ((2U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1dU)) - | (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x1fU)))))))))))))))))))))))))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__cache_miss_inow - = (1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag_valid) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__c_v) - >> (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U))) & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__last_tag - == (0x7ffffU - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 9U))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address = 0U; - if ((0x4000000U == (0xe000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address = 1U; - } - if ((0x8000000U == (0x8000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address = 1U; - } - main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_h832f938f__0 - = ((0U != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 6U)) | ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 5U) & (0U != (0x1fU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)))); - if (vlSelf->i_reset) { - vlSelf->main__DOT__u_i2cdma__DOT__r_memlen = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn = 0U; - } else { - if ((0x10U & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)))) { - if ((2U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) { - if ((1U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) { - vlSelf->main__DOT__u_i2cdma__DOT__r_memlen - = (0xfffffffU & vlSelf->main__DOT__u_i2cdma__DOT__next_memlen); - } - if ((1U & (~ vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]))) { - vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr - = (0xfffffffU & vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr); - } - } - } - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle) - ? 0U : (0xfU & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn))); - } else if (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_insn = 0U; - } - } - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle - = vlSelf->__Vdly__main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_ckedge) - & (IData)(main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_len; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_busy; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack - = ((IData)(vlSelf->main__DOT__swic__DOT__dc_ack) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0U] - = (IData)(((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) : - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[1U] - = (IData)((((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_SEL__DOT__r_wb_sel - : 0xffffffffffffffffULL) : - ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_sel - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_sel)) - >> 0x20U)); - if (vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) { - vlSelf->main__DOT__wbwide_zip_addr = vlSelf->main__DOT__swic__DOT__cpu_addr; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[2U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[3U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[4U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[5U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[6U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[7U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[8U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[9U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xaU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xbU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xcU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xdU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xeU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x10U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x11U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0xfU]; - } else { - vlSelf->main__DOT__wbwide_zip_addr = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) - ? vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_addr - : vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x10U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x11U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_data[0xfU]; - } - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x12U] - = ((0x400000U & (((IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__cpu_we) - : (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner))) - << 0x16U)) | vlSelf->main__DOT__wbwide_zip_addr); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_last; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[1U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[2U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[3U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[4U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[5U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[6U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[7U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[8U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[9U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xaU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xbU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xcU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xdU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xeU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0xfU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellout__u_sfifo__o_data[0x10U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__mem - [(0xfU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__rd_addr))][0x10U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_iflags - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_IHALT_PHASE__DOT__r_ihalt_phase) - << 0xdU) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag) - << 0xbU) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag) - << 0xaU) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap) - << 9U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i) - << 8U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en) - << 7U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep) - << 4U) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0)))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_uflags - = (0x20U | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_UHALT_PHASE__DOT__r_uhalt_phase) - << 0xdU) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__USER_DIVERR__DOT__r_udiv_err_flag) - << 0xbU) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_BUSERR__DOT__r_ubus_err_flag) - << 0xaU) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_trap) - << 9U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_USER_ILLEGAL_INSN__DOT__r_ill_err_u) - << 8U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_TRAP_N_UBREAK__DOT__r_ubreak) - << 7U) - | ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__user_step)) - << 6U) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep) - << 4U) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0)))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond - = ((((8U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F)) - | (7U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F) - >> 4U))) & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hefd95ffe__0) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_hb0e009d2__0))) - == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_F))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__tx_mem_addr; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid; - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk = 9U; - vlSelf->main__DOT__u_sdcard__DOT__rx_en = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__rx_en; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = 0U; - } else { - if (((((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x23U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk - = (0xfU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0x18U)); - if ((0xcU <= (0xfU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0x18U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk = 0xcU; - } else if ((2U >= (0xfU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0x18U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk = 2U; - } - } - vlSelf->main__DOT__u_sdcard__DOT__rx_en = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__rx_en; - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type - = (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 8U)); - } - if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request) - & (~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xaU))) & (IData)(((0x200U != - (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])) - | (0U == - (3U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 6U))))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = 1U; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = 0U; - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_tx_request) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = 1U; - } else if ((1U & ((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en))) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = 0U; - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en; - vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__w_stb - = ((((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len) - == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__r_len)) - & (0U != (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__cw_len))) - | ((IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_stb) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__skd_busy)) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__hx_valid)) - & (1U == (IData)(vlSelf->main__DOT__genbus__DOT__getinput__DOT__formcw__DOT__lastcw)))))); - if ((((IData)(vlSelf->main__DOT__rcv__DOT__zero_baud_counter) - & (8U == (IData)(vlSelf->main__DOT__rcv__DOT__state))) - & (IData)(vlSelf->main__DOT__rcv__DOT__ck_uart))) { - vlSelf->main__DOT__wbu_rx_data = vlSelf->main__DOT__rcv__DOT__data_reg; - } - vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__w_read - = (1U & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__padififo__DOT__will_underflow)) - & ((~ (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_empty_n)) - | (IData)(vlSelf->main__DOT__genbus__DOT__INPUT_FIFO__DOT__ififo_rd)))); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskd_ready - = (1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - ? vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data - : vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbu_stb) | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid))); - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])); - if (((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty)))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel = 1U; - } - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available - = (0U != (3U & ((vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant))) - & (~ vlSelf->main__DOT__wbu_xbar__DOT__requested - [0U])))); - if ((4U & vlSelf->main__DOT__wbu_xbar__DOT__request - [0U])) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available = 1U; - } - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available - = vlSelf->main__DOT__wbu_xbar__DOT__m_stb; - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U])))); - if ((((~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wbu_xbar__DOT__request - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]] : 0U)) & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]))) & ( - (0U - >= - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U]) - & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty) - >> - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [0U])))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant)))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_cyc) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wbu_xbar__DOT__request - [vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]] : 0U) >> 1U)) & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]))) - & ((0U >= vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbu_xbar__DOT__sindex - [1U])))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant) - >> 1U)))) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 0U; - } - if (vlSelf->i_reset) { - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbu_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_merr - = vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->main__DOT__swic__DOT__ext_err = (1U & ( - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) - >> 2U) - | (IData)(vlSelf->main__DOT__swic__DOT__wdbus_int))); - if ((1U & ((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } else if ((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } else if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } else if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } - } - if ((1U & ((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> 3U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel)))) { - if (vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__requested_channel_is_available) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } else if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))) { - vlSelf->main__DOT__wbwide_xbar__DOT__mgrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)); - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_p - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_op_valid - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_ljmp))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_illegal)); - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_phase = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - = (0x80000000U | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_nxt_half) - << 0x10U) | (0xffffU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU]))); - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_phase = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__SHIFT_INSN__DOT__shifted[0xfU]; - } - vlSelf->main__DOT__i2ci__DOT__ovw_ready = ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__half_valid)) - & (IData)(main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0)); - vlSelf->main__DOT__i2ci__DOT__pf_ready = ((~ ((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - | (IData)(vlSelf->main__DOT__i2ci__DOT__r_wait))) - & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__half_valid)) - & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__cpu_new_pc)) - & (IData)(main__DOT__i2ci__DOT____VdfgTmp_hfc6f1b73__0)))); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_sda - = (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_sda))); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl - = (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_scl))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_v_from_last - = ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__tag_lookup - == (0x7ffffU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U))) & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__valid_mask) - >> (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__lastpc - >> 9U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_asr_result - = (0x1ffffffffULL & ((0U != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 5U)) ? (- (QData)((IData)( - (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU)))) - : VL_SHIFTRS_QQI(33,33,5, - ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - << 1U), - (0x1fU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)))); - if ((0U == (2U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata; - } else if ((2U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x10U); - } else if ((3U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift - = (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - << 0x18U); - } - if ((0xffU == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0U] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[1U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[2U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[3U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[4U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[5U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[6U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[7U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[8U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[9U] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xaU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xbU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xcU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xdU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xeU] = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xfU] = 0U; - VL_SHIFTR_WWI(512,512,32, __Vtemp_hbc743227__0, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift, - (0x18U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 3U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0U] - = __Vtemp_hbc743227__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[1U] - = __Vtemp_hbc743227__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[2U] - = __Vtemp_hbc743227__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[3U] - = __Vtemp_hbc743227__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[4U] - = __Vtemp_hbc743227__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[5U] - = __Vtemp_hbc743227__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[6U] - = __Vtemp_hbc743227__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[7U] - = __Vtemp_hbc743227__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[8U] - = __Vtemp_hbc743227__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[9U] - = __Vtemp_hbc743227__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xaU] - = __Vtemp_hbc743227__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xbU] - = __Vtemp_hbc743227__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xcU] - = __Vtemp_hbc743227__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xdU] - = __Vtemp_hbc743227__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xeU] - = __Vtemp_hbc743227__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xfU] - = __Vtemp_hbc743227__0[0xfU]; - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0U] - = Vmain__ConstPool__CONST_hbd99daea_0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[1U] - = Vmain__ConstPool__CONST_hbd99daea_0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[2U] - = Vmain__ConstPool__CONST_hbd99daea_0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[3U] - = Vmain__ConstPool__CONST_hbd99daea_0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[4U] - = Vmain__ConstPool__CONST_hbd99daea_0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[5U] - = Vmain__ConstPool__CONST_hbd99daea_0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[6U] - = Vmain__ConstPool__CONST_hbd99daea_0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[7U] - = Vmain__ConstPool__CONST_hbd99daea_0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[8U] - = Vmain__ConstPool__CONST_hbd99daea_0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[9U] - = Vmain__ConstPool__CONST_hbd99daea_0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xaU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xbU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xcU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xdU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xeU] - = Vmain__ConstPool__CONST_hbd99daea_0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift[0xfU] - = vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__pre_shift; - VL_SHIFTR_WWI(512,512,32, __Vtemp_h6409050d__0, vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__wide_preshift, - (0x1f8U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - << 3U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0U] - = __Vtemp_h6409050d__0[0U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[1U] - = __Vtemp_h6409050d__0[1U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[2U] - = __Vtemp_h6409050d__0[2U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[3U] - = __Vtemp_h6409050d__0[3U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[4U] - = __Vtemp_h6409050d__0[4U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[5U] - = __Vtemp_h6409050d__0[5U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[6U] - = __Vtemp_h6409050d__0[6U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[7U] - = __Vtemp_h6409050d__0[7U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[8U] - = __Vtemp_h6409050d__0[8U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[9U] - = __Vtemp_h6409050d__0[9U]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xaU] - = __Vtemp_h6409050d__0[0xaU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xbU] - = __Vtemp_h6409050d__0[0xbU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xcU] - = __Vtemp_h6409050d__0[0xcU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xdU] - = __Vtemp_h6409050d__0[0xdU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xeU] - = __Vtemp_h6409050d__0[0xeU]; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__GEN_WIDE_BUS__DOT__shifted_data[0xfU] - = __Vtemp_h6409050d__0[0xfU]; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__w_cachable - = ((0xffU != (vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr - >> 0x18U)) & ((~ (IData)((0U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__DATA_CACHE__DOT__mem__DOT__raw_cachable_address))); - if (main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT____VdfgTmp_h832f938f__0) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result = 0ULL; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result = 0ULL; - } else if ((0x20U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr)) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result - = (0x1ffffffffULL & (QData)((IData)((vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata - >> 0x1fU)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result - = (0x1ffffffffULL & ((QData)((IData)((1U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata))) - << 0x20U)); - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsr_result - = (0x1ffffffffULL & (((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - << 1U) >> (0x1fU - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__w_lsl_result - = (0x1ffffffffULL & ((QData)((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_wdata)) - << (0x1fU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_cpu_addr))); - } - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_sda - = (1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__lst_scl - = (1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready - = (1U & (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait)) - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_ready) - | ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn) - >> 0xbU))) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__fill; - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_last) - ? 0U : ((0x3fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill)) - | (0xc0U & ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill) - >> 6U) - (IData)(1U)) - << 6U)))); - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill - = (0xffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill) - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last = 0U; - if ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_ready)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_last))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_last - = ((0U == (3U & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill) - >> 6U))) | (IData)((0x40U - == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__next_fill)))); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__r_inc) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__last_request_addr - = (0xfffffffU & ((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen)) - - (IData)(1U))); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__fill; - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_valid) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill - = (0xffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill) - - (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__m_bytes))); - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_ack) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill - = (0xffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__next_fill) - + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__rdack_size))); - } - if (vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_data[0x12U]; - } else { - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[1U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_data[0x12U]; - } - if ((1U & (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc))) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding = 0U; - } else if ((2U == ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall))) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full - = (IData)(((0x3fcU == (0x3fcU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding))) - & (0U != (3U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding))))); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding - = (0x3ffU & ((IData)(1U) + (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding))); - } else if ((1U == ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall))) - << 1U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full - = (0x3ffU == (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding)); - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding - = (0x3ffU & ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding) - - (IData)(1U))); - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_valid)); - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy = 1U; - } else if ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy) - & (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck))) - & (0U == ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck) - & ((2U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat) - >> 7U)) | (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat))))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy = 1U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy = 0U; - } else if ((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy)) - & (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck))) - & (0U != ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck) - & ((2U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat) - >> 7U)) | (1U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat))))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy = 0U; - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active = 0U; - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = 0U; - } else { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid = 1U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit)); - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = 0x30U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active = 1U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (0U != (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount)))) { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active - = (2U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount)); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount - = (0x3fU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount) - - (IData)(2U))); - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active - = (1U < (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount)); - vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount - = (0x3fU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount) - - (IData)(1U))); - } - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__cmd_sample_ck - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - ? 0U : (3U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pck_sreg) - << 2U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_pedge)) - >> (7U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift) - >> 2U))))); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl = 0U; - } else { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit = 1U; - } else if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid; - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl; - } - } - vlSelf->main__DOT__rcv__DOT__data_reg = vlSelf->__Vdly__main__DOT__rcv__DOT__data_reg; - vlSelf->main__DOT__rcv__DOT__zero_baud_counter - = vlSelf->__Vdly__main__DOT__rcv__DOT__zero_baud_counter; - vlSelf->main__DOT__rcv__DOT__state = vlSelf->__Vdly__main__DOT__rcv__DOT__state; - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((2U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | (0U == (0x4000000U & (IData)((vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U))))); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((1U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((0U == (0x4000000U & (0x4000000U ^ (0x7ffffffU - & (IData)( - (vlSelf->main__DOT__wbu_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))) - << 1U)); - vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbu_cyc)); - vlSelf->main__DOT__swic__DOT__dc_err = ((~ (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__ext_err)); - vlSelf->main__DOT__swic__DOT__cpu_err = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc) - & ((IData)(vlSelf->main__DOT__swic__DOT__ext_err) - & (IData)(vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__high_z) - ? (IData)(vlSelf->i_sdcard_cmd) : (IData)(vlSelf->o_sdcard_cmd)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__pf_valid - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_ljmp - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase) - & (0xfcf8U == (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x10U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div - = (IData)((0x3800000U == (0x87800000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_fpu - = (IData)(((0x6000000U == (0x86000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - & ((7U != (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1cU))) & (0U - != - (3U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x17U)))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI - = (0xffU & ((6U == (7U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x18U))) ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x10U) - : ((0x800000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? ((0xfcU & ((- (IData)((1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x12U)))) - << 2U)) | (3U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x10U))) - : ((0x80U & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xfU)) | (0x7fU - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x10U)))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special - = (IData)((0x77000000U == (0xf7000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__last_stb - = ((~ (((IData)(vlSelf->__VdfgTmp_h503d14d1__0) - >> 1U) & (IData)(vlSelf->main__DOT__wbwide_i2cm_stb))) - & (2U <= ((IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__inflight) - + (((IData)(vlSelf->main__DOT__wbwide_i2cm_stb) - ? 1U : 0U) + ((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)) - | (IData)(vlSelf->main__DOT__i2ci__DOT__u_fetch__DOT__GEN_SUBSHIFT__DOT__rg_valid))))))); - main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0 - = (1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_ready))); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x80000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x380000U & (0x100000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0 - = (0U == (0x200000U & (0x200000U ^ (0x3fffffU - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__iskid__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_hc7d9c82c__0) - << 2U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_outstanding; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_ack - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__dc_ack)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall - = ((IData)(vlSelf->main__DOT__swic__DOT__dc_stall) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__fill; - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk = 9U; - } else { - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type - = (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 8U)); - } - if (((((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1bU)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk - = (0xfU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0x18U)); - if ((0xcU <= (0xfU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0x18U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk = 0xcU; - } else if ((2U >= (0xfU & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0x18U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk = 2U; - } - } - } - vlSelf->main__DOT__u_emmc__DOT__rx_en = vlSelf->__Vdly__main__DOT__u_emmc__DOT__rx_en; - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = 0U; - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = 1U; - } else if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_done; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__wait_for_busy; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0xfff8U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [2U] << 2U) | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [1U] << 1U) | vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0U]))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0xffc7U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [5U] << 5U) | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [4U] << 4U) | (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [3U] - << 3U)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0xfe3fU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [8U] << 8U) | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [7U] << 7U) | (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [6U] - << 6U)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0xf1ffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xbU] << 0xbU) | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xaU] << 0xaU) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [9U] << 9U)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0x8fffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xeU] << 0xeU) | ((vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xdU] << 0xdU) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xcU] << 0xcU)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat - = ((0x7fffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)) - | (vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__pre_dat - [0xfU] << 0xfU)); - vlSelf->main__DOT__genbus__DOT__rx_valid = ((IData)(vlSelf->main__DOT__wbu_rx_stb) - & ((IData)(vlSelf->main__DOT__wbu_rx_data) - >> 7U)); - vlSelf->main__DOT__rcv__DOT__ck_uart = vlSelf->main__DOT__rcv__DOT__qq_uart; - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_err - = ((IData)(vlSelf->main__DOT__swic__DOT__dc_err) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_err - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__dc_err)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_err - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)) - & (IData)(vlSelf->main__DOT__swic__DOT__cpu_err)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_err - = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_err) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_he52a0fcf__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_fpu) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_div)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_noop - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - & (0x7800000U == (0x7800000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_lock - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - & (0x7400000U == (0x7c00000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))); - if ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU)) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0 - = (0xfU & ((IData)((0x4000000U == (0x6800000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))) - ? 0xdU : (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x13U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op - = (0x1fU & ((0x4000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? ((0x2000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? ((0x1000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 0xdU : 0x18U) : - ((0x1000000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 0x13U : 0x12U)) : ( - (0x2000000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? - ((0x1000000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 0x10U - : 2U) - : - ((0x1000000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 1U - : 0U)))); - } else { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0 - = (0xfU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xeU)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op - = (0x1fU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x16U)); - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_ALU - = ((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 4U)) & (7U != (7U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h9ed30f6d__0 - = (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special) - | (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU)) | (0xcU == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc - = ((0xcU == (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))) ? 0U : ((0xdU - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - ? 1U - : ((0x40000U - & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword) - ? 3U - : 2U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_I - = (0x7fffffU & ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU) ? ((0x7fff00U & - ((- (IData)( - (1U - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI) - >> 7U)))) - << 8U)) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_IMMEDIATE__DOT__w_halfI)) - : ((2U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? ((0x7fc000U & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xdU)))) - << 0xeU)) - | (0x3fffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - : ((0x7c0000U & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x11U)))) - << 0x12U)) - | (0x3ffffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword))) - : ((1U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_immsrc)) - ? ((0x7fe000U & ((- (IData)( - (1U - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xcU)))) - << 0xdU)) - | (0x1fffU & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - : vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem - = (IData)(((0x10U == (0x18U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op))) - & (0U != (3U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))); - main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0 - = ((~ (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU)) & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (0xdU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)))); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_sda - = (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->i_i2c_sda))); - vlSelf->main__DOT__i2ci__DOT__i2c_stretch = (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__ck_scl)) - & (IData)(vlSelf->main__DOT__i2ci__DOT__w_scl)) - | ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__s_tvalid)) - & (IData)(main__DOT__i2ci__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0))); - vlSelf->main__DOT__i2ci__DOT__u_axisi2c__DOT__q_scl - = (1U & ((~ (IData)(vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->i_i2c_scl))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_sda - = (1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_sda))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl - = (1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_scl))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_ready - = ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid)) - & (IData)(main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready - = ((~ ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_wait))) - & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__half_valid)) - & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__cpu_new_pc)) - & (IData)(main__DOT__u_fan__DOT__u_i2ccpu__DOT____VdfgTmp_hfc6f1b73__0)))); - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size = 0U; - } else { - if (((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__enable_ints) - & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1fU))) { - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__disable_ints) - & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1fU))) { - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__r_mie = 0U; - } - if (((((IData)(vlSelf->main__DOT__swic__DOT__dmac_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__sys_addr) - >> 1U)))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size - = (3U & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x10U)); - } - } - } - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size - = (0x7fU & ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? 1U : ((1U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr) - ? 1U : 2U)) : ((1U - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size)) - ? - ((IData)(4U) - - - (3U - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr)) - : - ((IData)(0x40U) - - - (0x3fU - & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_addr))))); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size) - > (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_mm2s__DOT__first_size - = (0x7fU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_dma_fsm__DOT__r_transferlen)); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last)) - & ((~ ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__wb_pipeline_full) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb)))) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_busy))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - = ((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_addr - << 6U) | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__subaddr)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stall)))) { - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size))) { - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - = (0x1fffffffU & ((IData)(1U) - + vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)); - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc) - ? (0x1fffffffU & ((IData)(2U) - + vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) - : (0x1ffffffeU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)); - } - } else { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - = ((1U & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_size)) - ? ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc) - ? (0x1fffffffU & ((IData)(4U) - + vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) - : (0x1ffffffcU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) - : ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_inc) - ? (0x1fffffffU & ((IData)(0x40U) - + vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)) - : (0x1fffffc0U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr))); - } - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_arbiter__DOT__r_a_owner) { - vlSelf->main__DOT__swic__DOT__dc_stb = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_stb; - vlSelf->main__DOT__swic__DOT__dc_cyc = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_rd_cyc; - } else { - vlSelf->main__DOT__swic__DOT__dc_stb = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_stb; - vlSelf->main__DOT__swic__DOT__dc_cyc = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_wr_cyc; - } - if (vlSelf->main__DOT__swic__DOT__dmacvcpu__DOT__r_a_owner) { - vlSelf->main__DOT__wbwide_zip_stb = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - ? (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_gbl) - : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_stb)); - vlSelf->main__DOT__wbwide_zip_cyc = vlSelf->main__DOT__swic__DOT__cpu_gbl_cyc; - } else { - vlSelf->main__DOT__wbwide_zip_stb = vlSelf->main__DOT__swic__DOT__dc_stb; - vlSelf->main__DOT__wbwide_zip_cyc = vlSelf->main__DOT__swic__DOT__dc_cyc; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_valid - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out - = ((0xf0U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out)) - | (0xfU & (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat) - >> 8U) & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_dat)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_sto - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_rB - = ((0xdU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op)) - | ((IData)((((0x40000U == (0x80040000U & vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_special))) - & (0xcU != (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))))) - | ((vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1fU) & (((0xcU != (0xfU & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_cis_op) - >> 1U))) - & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x17U)) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_mem))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preB - = ((0x10U & (((IData)(main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0xdU) : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - << 4U)) | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_h20660d0e__0)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA - = ((0x10U & (((IData)(main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT____VdfgTmp_ha0d5d2cf__0) - ? (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x12U) : (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - << 4U)) | (0xfU & (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__iword - >> 0x1bU))); - vlSelf->main__DOT____Vcellinp__i2cscopei____pinNumber4 - = ((0x40000000U & ((IData)(vlSelf->main__DOT__i2ci__DOT__ovw_data) - << 0x15U)) | (((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_abort) - << 0x1dU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__i2c_stretch) - << 0x1cU) - | (((IData)(vlSelf->main__DOT__i2ci__DOT__half_insn) - << 0x18U) - | vlSelf->main__DOT__i2ci__DOT____VdfgTmp_h373818eb__0)))); - vlSelf->main__DOT__i2ci__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN - = (1U & (~ ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__i2ci__DOT__GEN_MANUAL__DOT__manual)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__last_stb - = (2U <= ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_fetch__DOT__inflight) - + (((IData)(vlSelf->main__DOT__u_fan__DOT__mem_stb) - ? 1U : 0U) + ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)))))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_ready) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__r_next)))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_data[0xfU]; - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 1U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 2U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 3U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 4U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 5U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 6U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 7U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 8U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 9U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xaU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xbU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xcU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xdU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xeU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0xfU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x10U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x11U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x12U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x13U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x14U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x15U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x16U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x17U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x18U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x19U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1aU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1bU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1cU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1dU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1eU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x1fU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x20U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x21U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x22U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x23U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x24U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x25U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x26U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x27U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x28U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x29U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2aU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2bU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2cU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2dU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2eU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x2fU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x30U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x31U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x32U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x33U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x34U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x35U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x36U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x37U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x38U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x39U))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3aU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3bU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3cU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = (0xffffff00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3dU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = (0xffff00ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3eU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = (0xff00ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]); - } - if ((1U & (~ (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x3fU))))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = (0xffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU]); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] = 0U; - if ((0U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x80000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((1U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x40000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((2U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x20000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((3U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x10000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((4U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x8000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((5U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x4000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((6U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x2000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((7U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x1000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((8U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x800000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((9U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x400000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xaU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x200000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xbU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x100000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xcU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x80000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xdU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x40000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xeU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x20000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0xfU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x10000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x10U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x8000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x11U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x4000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x12U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x2000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x13U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x1000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x14U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x800U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x15U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x400U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x16U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x200U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x17U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x100U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x18U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x80U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x19U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x40U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x20U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (0x10U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (8U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (4U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (2U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x1fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U] - = (1U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[3U]); - } - if ((0x20U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x80000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x21U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x40000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x22U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x20000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x23U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x10000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x24U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x8000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x25U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x4000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x26U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x2000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x27U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x1000000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x28U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x800000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x29U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x400000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x200000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x100000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x80000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x40000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x20000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x2fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x10000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x30U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x8000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x31U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x4000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x32U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x2000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x33U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x1000U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x34U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x800U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x35U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x400U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x36U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x200U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x37U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x100U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x38U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x80U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x39U < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x40U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3aU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x20U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3bU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (0x10U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3cU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (8U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3dU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (4U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3eU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (2U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - if ((0x3fU < (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_bytes))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U] - = (1U | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel[2U]); - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[0U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[1U] = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[2U] - = (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[3U] - = (IData)((vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_sel - >> 0x20U)); - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__m_valid) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__r_last)))) { - __Vtemp_h448dc795__0[0U] = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - __Vtemp_h448dc795__0[1U] = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - __Vtemp_h448dc795__0[2U] = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - __Vtemp_h448dc795__0[3U] = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - __Vtemp_h448dc795__0[4U] = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - __Vtemp_h448dc795__0[5U] = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - __Vtemp_h448dc795__0[6U] = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - __Vtemp_h448dc795__0[7U] = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - __Vtemp_h448dc795__0[8U] = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - __Vtemp_h448dc795__0[9U] = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - __Vtemp_h448dc795__0[0xaU] = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - __Vtemp_h448dc795__0[0xbU] = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - __Vtemp_h448dc795__0[0xcU] = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - __Vtemp_h448dc795__0[0xdU] = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - __Vtemp_h448dc795__0[0xeU] = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - __Vtemp_h448dc795__0[0xfU] = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - __Vtemp_h448dc795__0[0x10U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0U]; - __Vtemp_h448dc795__0[0x11U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[1U]; - __Vtemp_h448dc795__0[0x12U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[2U]; - __Vtemp_h448dc795__0[0x13U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[3U]; - __Vtemp_h448dc795__0[0x14U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[4U]; - __Vtemp_h448dc795__0[0x15U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[5U]; - __Vtemp_h448dc795__0[0x16U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[6U]; - __Vtemp_h448dc795__0[0x17U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[7U]; - __Vtemp_h448dc795__0[0x18U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[8U]; - __Vtemp_h448dc795__0[0x19U] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[9U]; - __Vtemp_h448dc795__0[0x1aU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xaU]; - __Vtemp_h448dc795__0[0x1bU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xbU]; - __Vtemp_h448dc795__0[0x1cU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xcU]; - __Vtemp_h448dc795__0[0x1dU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xdU]; - __Vtemp_h448dc795__0[0x1eU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xeU]; - __Vtemp_h448dc795__0[0x1fU] = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_txgears__DOT__sreg[0xfU]; - VL_SHIFTR_WWI(1024,1024,32, __Vtemp_h9b90904f__0, __Vtemp_h448dc795__0, - (0x1f8U & (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr - << 3U))); - __Vtemp_h7be7356a__0[1U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[1U] - | __Vtemp_h9b90904f__0[1U]); - __Vtemp_h7be7356a__0[2U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[2U] - | __Vtemp_h9b90904f__0[2U]); - __Vtemp_h7be7356a__0[3U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[3U] - | __Vtemp_h9b90904f__0[3U]); - __Vtemp_h7be7356a__0[4U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[4U] - | __Vtemp_h9b90904f__0[4U]); - __Vtemp_h7be7356a__0[5U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[5U] - | __Vtemp_h9b90904f__0[5U]); - __Vtemp_h7be7356a__0[6U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[6U] - | __Vtemp_h9b90904f__0[6U]); - __Vtemp_h7be7356a__0[7U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[7U] - | __Vtemp_h9b90904f__0[7U]); - __Vtemp_h7be7356a__0[8U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[8U] - | __Vtemp_h9b90904f__0[8U]); - __Vtemp_h7be7356a__0[9U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[9U] - | __Vtemp_h9b90904f__0[9U]); - __Vtemp_h7be7356a__0[0xaU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xaU] - | __Vtemp_h9b90904f__0[0xaU]); - __Vtemp_h7be7356a__0[0xbU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xbU] - | __Vtemp_h9b90904f__0[0xbU]); - __Vtemp_h7be7356a__0[0xcU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xcU] - | __Vtemp_h9b90904f__0[0xcU]); - __Vtemp_h7be7356a__0[0xdU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xdU] - | __Vtemp_h9b90904f__0[0xdU]); - __Vtemp_h7be7356a__0[0xeU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xeU] - | __Vtemp_h9b90904f__0[0xeU]); - __Vtemp_h7be7356a__0[0xfU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xfU] - | __Vtemp_h9b90904f__0[0xfU]); - __Vtemp_h7be7356a__0[0x10U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - | __Vtemp_h9b90904f__0[0x10U]); - __Vtemp_h7be7356a__0[0x11U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - | __Vtemp_h9b90904f__0[0x11U]); - __Vtemp_h7be7356a__0[0x12U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - | __Vtemp_h9b90904f__0[0x12U]); - __Vtemp_h7be7356a__0[0x13U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - | __Vtemp_h9b90904f__0[0x13U]); - __Vtemp_h7be7356a__0[0x14U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - | __Vtemp_h9b90904f__0[0x14U]); - __Vtemp_h7be7356a__0[0x15U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - | __Vtemp_h9b90904f__0[0x15U]); - __Vtemp_h7be7356a__0[0x16U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - | __Vtemp_h9b90904f__0[0x16U]); - __Vtemp_h7be7356a__0[0x17U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - | __Vtemp_h9b90904f__0[0x17U]); - __Vtemp_h7be7356a__0[0x18U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - | __Vtemp_h9b90904f__0[0x18U]); - __Vtemp_h7be7356a__0[0x19U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - | __Vtemp_h9b90904f__0[0x19U]); - __Vtemp_h7be7356a__0[0x1aU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - | __Vtemp_h9b90904f__0[0x1aU]); - __Vtemp_h7be7356a__0[0x1bU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - | __Vtemp_h9b90904f__0[0x1bU]); - __Vtemp_h7be7356a__0[0x1cU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - | __Vtemp_h9b90904f__0[0x1cU]); - __Vtemp_h7be7356a__0[0x1dU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - | __Vtemp_h9b90904f__0[0x1dU]); - __Vtemp_h7be7356a__0[0x1eU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - | __Vtemp_h9b90904f__0[0x1eU]); - __Vtemp_h7be7356a__0[0x1fU] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - | __Vtemp_h9b90904f__0[0x1fU]); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0U] - | __Vtemp_h9b90904f__0[0U]); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[1U] - = __Vtemp_h7be7356a__0[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[2U] - = __Vtemp_h7be7356a__0[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[3U] - = __Vtemp_h7be7356a__0[3U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[4U] - = __Vtemp_h7be7356a__0[4U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[5U] - = __Vtemp_h7be7356a__0[5U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[6U] - = __Vtemp_h7be7356a__0[6U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[7U] - = __Vtemp_h7be7356a__0[7U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[8U] - = __Vtemp_h7be7356a__0[8U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[9U] - = __Vtemp_h7be7356a__0[9U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xaU] - = __Vtemp_h7be7356a__0[0xaU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xbU] - = __Vtemp_h7be7356a__0[0xbU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xcU] - = __Vtemp_h7be7356a__0[0xcU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xdU] - = __Vtemp_h7be7356a__0[0xdU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xeU] - = __Vtemp_h7be7356a__0[0xeU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0xfU] - = __Vtemp_h7be7356a__0[0xfU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x10U] - = __Vtemp_h7be7356a__0[0x10U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x11U] - = __Vtemp_h7be7356a__0[0x11U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x12U] - = __Vtemp_h7be7356a__0[0x12U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x13U] - = __Vtemp_h7be7356a__0[0x13U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x14U] - = __Vtemp_h7be7356a__0[0x14U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x15U] - = __Vtemp_h7be7356a__0[0x15U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x16U] - = __Vtemp_h7be7356a__0[0x16U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x17U] - = __Vtemp_h7be7356a__0[0x17U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x18U] - = __Vtemp_h7be7356a__0[0x18U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x19U] - = __Vtemp_h7be7356a__0[0x19U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1aU] - = __Vtemp_h7be7356a__0[0x1aU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1bU] - = __Vtemp_h7be7356a__0[0x1bU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1cU] - = __Vtemp_h7be7356a__0[0x1cU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1dU] - = __Vtemp_h7be7356a__0[0x1dU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1eU] - = __Vtemp_h7be7356a__0[0x1eU]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_data[0x1fU] - = __Vtemp_h7be7356a__0[0x1fU]; - VL_SHIFTR_WWI(128,128,6, __Vtemp_h6aa6ab78__0, vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__pre_sel, - (0x3fU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_addr)); - __Vtemp_hd96f9696__0[1U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[1U] - | __Vtemp_h6aa6ab78__0[1U]); - __Vtemp_hd96f9696__0[2U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[2U] - | __Vtemp_h6aa6ab78__0[2U]); - __Vtemp_hd96f9696__0[3U] = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[3U] - | __Vtemp_h6aa6ab78__0[3U]); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[0U] - = (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[0U] - | __Vtemp_h6aa6ab78__0[0U]); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[1U] - = __Vtemp_hd96f9696__0[1U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[2U] - = __Vtemp_hd96f9696__0[2U]; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_s2mm__DOT__next_sel[3U] - = __Vtemp_hd96f9696__0[3U]; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__ign_sfifo_fill; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_wr - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_full)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_rxgears__DOT__m_valid)); - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort = 0U; - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err = 0U; - vlSelf->main__DOT__swic__DOT__dmac_int = 0U; - } else { - if (((((IData)(vlSelf->main__DOT__swic__DOT__dmac_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__swic__DOT__sys_addr) - >> 1U)))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size - = (3U & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x14U)); - } - } - } - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort = 0U; - } - if (vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err = 1U; - } - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_busy) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err)))) { - vlSelf->main__DOT__swic__DOT__dmac_int = 1U; - } - if ((((IData)(vlSelf->main__DOT__swic__DOT__dmac_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)) - & (0U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))))) { - if (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy))) { - if ((0x41425254U == vlSelf->main__DOT__swic__DOT__sys_data)) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort = 1U; - } - } else { - if ((IData)((0x40000000U != (0x60000000U - & vlSelf->main__DOT__swic__DOT__sys_data)))) { - vlSelf->main__DOT__swic__DOT__dmac_int = 0U; - } - if ((1U & ((~ (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1fU)) & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err)) - | (vlSelf->main__DOT__swic__DOT__sys_data - >> 0x1eU))))) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request - = (1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_zero_len))); - } - if ((0x40000000U & vlSelf->main__DOT__swic__DOT__sys_data)) { - vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err = 0U; - } - } - } - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err; - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = 0U; - } else { - if ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request) - & (~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xaU))) & (IData)(((0x200U != - (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])) - | (0U == - (3U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 6U))))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = 1U; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request = 0U; - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_tx_request) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = 1U; - } else if ((1U & ((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en))) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request = 0U; - } - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount; - vlSelf->main__DOT__rcv__DOT__qq_uart = vlSelf->main__DOT__rcv__DOT__q_uart; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_cc - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA) - == (0xeU | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__w_dcdR_pc - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_preA) - == (0xfU | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_sda - = (1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->i_fan_sda))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__i2c_stretch - = (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__ck_scl)) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__w_scl)) - | ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__s_tvalid)) - & (IData)(main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT____VdfgTmp_h17d9fffe__0))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__u_axisi2c__DOT__q_scl - = (1U & ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN)) - | (IData)(vlSelf->i_fan_scl))); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__wbwide_zip_cyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_stb = (( - ((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc) - & ((~ - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 3U)) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid))) - << 3U) - | ((((IData)(vlSelf->main__DOT__wbwide_zip_cyc) - & ((~ - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 2U)) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid))) - << 2U) - | ((((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - & ((~ - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 1U)) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid))) - << 1U) - | ((IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc) - & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull)) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)))))); - vlSelf->main__DOT__wbwide_xbar__DOT__request[2U] - = (((IData)(vlSelf->main__DOT__wbwide_zip_cyc) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid)) - ? (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__decoded) - : 0U); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__w_rd - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_sfifo__DOT__r_empty)) - & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__tx_ready)); - vlSelf->main__DOT__swic__DOT__main_int_vector = - (((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h29ee39ef__0) - << 6U) | (((IData)(vlSelf->main__DOT__swic__DOT__ctri_int) - << 5U) | (((IData)(vlSelf->main__DOT__swic__DOT__tma_int) - << 4U) | (((IData)(vlSelf->main__DOT__swic__DOT__tmb_int) - << 3U) | - (((IData)(vlSelf->main__DOT__swic__DOT__tmc_int) - << 2U) - | (((IData)(vlSelf->main__DOT__swic__DOT__jif_int) - << 1U) - | (IData)(vlSelf->main__DOT__swic__DOT__dmac_int))))))); - if ((1U & (~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_busy - = vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_valid)); - if ((((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy = 1U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy) - & (~ (IData)(vlSelf->i_emmc_dat)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy = 1U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy = 0U; - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy)) - & (IData)(vlSelf->i_emmc_dat)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy = 0U; - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active = 0U; - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl = 0U; - } else { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit = 1U; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_stop_bit - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid; - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount = 0x30U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl; - } else if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & (0U != (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount)))) { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active - = (2U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount)); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount - = (0x3fU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount) - - (IData)(2U))); - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active - = (1U < (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount)); - vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount - = (0x3fU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount) - - (IData)(1U))); - } - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck - = ((1U & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid))) - ? 0U : (3U & ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__ck_sreg) - << 2U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__next_dedge)) - >> (7U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift) - >> 2U))))); - vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3 - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT____Vcellinp__u_axisi2c__S_AXI_ARESETN - = (1U & (~ ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__GEN_MANUAL__DOT__manual)))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb - = ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__iskid__i_reset)) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - | (IData)(vlSelf->main__DOT__wbwide_zip_stb))); - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])); - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__stay_on_channel = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])); - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__stay_on_channel = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])); - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__stay_on_channel = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel - = (0U != (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])); - if ((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 3U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__stay_on_channel = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__requested[0U] - = (6U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U]); - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U]); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = ((6U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]) | (IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0)); - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U] | ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = (1U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = ((6U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]) | (IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0)); - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U] | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = (1U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = ((6U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]) | (IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0)); - if ((1U & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U] | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = (1U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]); - } - vlSelf->main__DOT__wbwide_xbar__DOT__requested[0U] - = (5U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U]); - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = ((5U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 1U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 1U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U] >> 1U) | ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = (2U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = ((5U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 1U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 1U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U] >> 1U) | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = (2U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = ((5U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 1U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 1U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U] >> 1U) | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = (2U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]); - } - vlSelf->main__DOT__wbwide_xbar__DOT__requested[0U] - = (3U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U]); - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = ((3U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 2U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 2U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U] >> 2U) | ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant)) - | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[1U] - = (4U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = ((3U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 2U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 2U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U] >> 2U) | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U)) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[2U] - = (4U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U]); - } - main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0 - = (1U & (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = ((3U & vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]) | ((IData)(main__DOT__wbwide_xbar__DOT____Vlvbound_he62f6d27__0) - << 2U)); - if ((1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 2U) & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U] >> 2U) | ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U)) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U)))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__requested[3U] - = (4U | vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U]); - } - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_zero_len = 1U; - } else if (((((IData)(vlSelf->main__DOT__swic__DOT__dmac_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy)))) { - if ((2U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))) { - if ((1U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))) { - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_zero_len - = (0U == (0xfffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len)); - } - } - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_request; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy - = vlSelf->__Vdly__main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy; - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = 0U; - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = 1U; - } else if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy = 0U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_done; - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdfrontend__DOT__wait_for_busy; - vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber4 - = (((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - << 0x1cU) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__sample_ck) - << 0x1aU) | ((0x2000000U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - << 0x12U)) - | ((0x1000000U - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__sdclk) - << 0x15U)) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - << 0x17U) - | ((0x600000U - & ((IData)( - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__tx_sreg - >> 0x2eU)) - << 0x15U)) - | (((IData)( - (3U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_in))) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_strb) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_cmd_data) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_strb) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__r_rx_data) - << 8U) - | (0xffU - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - ? - (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__w_out))))))))))))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts; - vlSelf->main__DOT__sdioscopei__DOT__dw_trigger - = ((IData)(vlSelf->main__DOT__sdioscopei__DOT__dr_primed) - & (((~ (IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config)) - & (IData)(vlSelf->main__DOT____Vcellinp__sdioscopei____pinNumber3)) - | ((IData)(vlSelf->main__DOT__sdioscopei__DOT__br_config) - >> 1U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds) - & (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed))); - vlSelf->main__DOT__rcv__DOT__q_uart = vlSelf->i_wbu_uart_rx; - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__wbwide_zip_cyc)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0x1fffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | (((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_busy) - << 0x1fU) | ((((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__r_err) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_err)) - << 0x1eU) | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_trigger) - << 0x1dU)))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0xe0ffffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__int_sel) - << 0x18U)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0xfffff800U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0xff8fffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | ((0x400000U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_inc)) - << 0x16U)) | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__s2mm_size) - << 0x14U))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg - = ((0xfff8ffffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__w_control_reg) - | ((0x40000U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_inc)) - << 0x12U)) | ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__mm2s_size) - << 0x10U))); - vlSelf->main__DOT__swic__DOT__cmd_reset = ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (((IData)(vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__r_reset_hold) - | (IData)(vlSelf->main__DOT__swic__DOT__wdt_reset)) - | (((IData)(vlSelf->main__DOT__swic__DOT__cpu_break) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch))) - | (IData)(vlSelf->main__DOT__swic__DOT__reset_request)))); - if (vlSelf->main__DOT____Vcellinp__swic__i_reset) { - vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__dbg_cmd_write) - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_sel))) { - vlSelf->main__DOT__swic__DOT__GEN_DBG_CATCH__DOT__r_dbg_catch - = (1U & (vlSelf->main__DOT__swic__DOT__dbg_idata - >> 5U)); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xf0ffffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - << 0x1bU) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request) - << 0x1aU) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en) - << 0x19U) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request) - << 0x18U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffc7ffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr)) - << 0x15U) | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__dat0_busy) - << 0x14U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfff83fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode) - << 0x10U) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err) - << 0xfU) | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - << 0xeU)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffffcfffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - << 0xcU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfffff7ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type)))) - << 0xbU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfffff8ffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - << 0xaU) | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type) - << 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffffff80U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_cmd)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb - = (1U & ((IData)(vlSelf->i_reset) | ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown)) - | (0U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd))) - | ((1U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - | ((2U - == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - ? - (((0x200U - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - ? 1U - : 2U) - >> 1U) - : (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk)))))); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown = 0U; - } else { - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_request = 0U; - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xfU)); - } - } - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((6U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | (IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest) - >> 1U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((5U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 1U)); - main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0 - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid) - & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest) - >> 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request - = ((3U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__NO_DEFAULT_REQUEST__DOT__r_request)) - | ((IData)(main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT____Vlvbound_he5148a9b__0) - << 2U)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_valid) - & (0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__prerequest))); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_request_NS - = vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__adcd__DOT__OPT_NONESEL_REQUEST__DOT__r_none_sel; - vlSelf->main__DOT__swic__DOT__wdt_reset = vlSelf->__Vdly__main__DOT__swic__DOT__wdt_reset; - vlSelf->main__DOT__swic__DOT__cpu_break = ((((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__break_en)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_BREAK__DOT__r_break_pending))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb - = (1U & (((0xffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter)) - - (IData)(1U)) >> 8U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter) - - (IData)(1U)))); - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0 - = (1U & (((IData)(1U) + (3U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 8U))) - >> 2U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0 - = (3U & ((IData)(1U) + ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0xffU & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0) - << 8U)); - if ((1U >= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = 1U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = (0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - } else if ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk - = (1U & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__counter) - >> 9U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = (0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd) - - (IData)(3U)))); - } - } - if (vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((1U >= (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)) - ? 0x300U : ((2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)) - ? 0x100U : ((0x300U & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & - ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed) - - (IData)(3U)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed; - } else { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__clk90; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd - = vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_invalidate_result - = ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT____Vcellinp__u_sfifo__i_reset - = ((IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_abort) - | (IData)(vlSelf->main__DOT__swic__DOT__cmd_reset)); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchbus____pinNumber2 - = (1U & ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | ((~ (IData)(vlSelf->main__DOT__wbwide_zip_cyc)) - | ((IData)(vlSelf->main__DOT__wbwide_zip_stb) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_mack) - >> 2U))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset - = ((IData)(vlSelf->main__DOT__swic__DOT__cmd_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)); - vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__r_reset_hold - = ((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (1U < (IData)(vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce - = (1U & ((~ (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_ha62fb8d9__0) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__last_write_to_cc)) - | ((IData)(vlSelf->main__DOT__swic__DOT__cpu_break) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__sleep)))) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__cmd_halt)) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)))); - vlSelf->io_emmc_dat_tristate = ((0x80U & ((~ ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1fU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 7U)) - | ((0x40U & ((~ - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1eU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 6U)) - | ((0x20U & - ((~ ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1dU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 5U)) - | ((0x10U - & ((~ - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1cU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 4U)) - | ((8U - & ((~ - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1bU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))) - << 3U)) - | (7U - & (~ - ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x1aU)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data))) - << 2U) - | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x19U)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data))) - << 1U) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - & ((~ - (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_data - >> 0x18U)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data)))))))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__sample_ck - = (1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)) - & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__ck_sreg) - << 1U) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_dedge)) - >> (3U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift) - >> 3U))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__cmd_sample_ck - = (1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active)) - & ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__pck_sreg) - << 1U) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__next_pedge)) - >> (IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift)))); - vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3 - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid)); - vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0 - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((~ (IData)(vlSelf->o_emmc_cmd)) | (IData)(vlSelf->main__DOT__u_emmc__DOT__pp_cmd))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_busy - = (1U & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__start_packet - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb) - & ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount) - == ((IData)(1U) + (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl)))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready - = ((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_stb)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__instruction_decoder__i_reset - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____Vcellinp__doalu__i_reset) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache)); - vlSelf->main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter - = vlSelf->__Vdly__main__DOT__swic__DOT__INITIAL_RESET_HOLD__DOT__reset_counter; - vlSelf->main__DOT__swic__DOT__cpu_pf_stall = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce)) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ill_err_i) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__step) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_PENDING_INTERRUPT__DOT__r_user_stepped)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__ibus_err_flag) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__DIVERR__DOT__r_idiv_err_flag) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pending_interrupt) - & ((~ (IData)((0U - != (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_bus_lock)))) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_ALU_PHASE__DOT__r_alu_phase)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_op_break) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__BUSLOCK__DOT__r_prelock_stall) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_illegal) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_ALU_ILLEGAL__DOT__r_alu_illegal) - | (IData)(vlSelf->main__DOT__swic__DOT__cpu_break)))))))))))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_valid; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts - = vlSelf->__Vdly__main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts; - vlSelf->main__DOT__emmcscopei__DOT__dw_trigger - = ((IData)(vlSelf->main__DOT__emmcscopei__DOT__dr_primed) - & (((~ (IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config)) - & (IData)(vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber3)) - | ((IData)(vlSelf->main__DOT__emmcscopei__DOT__br_config) - >> 1U))); - vlSelf->io_emmc_cmd_tristate = (1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0))); - vlSelf->main__DOT____Vcellinp__emmcscopei____pinNumber4 - = (((IData)(vlSelf->o_emmc_clk) << 0x19U) | - (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - << 0x17U) | (((IData)(vlSelf->o_emmc_cmd) - << 0x16U) | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT____VdfgTmp_h87c0e738__0) - ? (IData)(vlSelf->o_emmc_cmd) - : (IData)(vlSelf->i_emmc_cmd)) - << 0x14U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_strb) - << 0x13U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_cmd_data) - << 0x12U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - << 0x11U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_strb) - << 0x10U) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdfrontend__DOT__GEN_NO_SERDES__DOT__r_rx_data) - << 8U) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid) - ? (IData)(vlSelf->o_emmc_dat) - : (IData)(vlSelf->i_emmc_dat))))))))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_cfg_dbl - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds) - & (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) - & ((1U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate)) - | (0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_txframe__DOT__pstate)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_pipe_stalled) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_bus_err) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_error) - | (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_PIPE__DOT__r_op_pipe)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & ((0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))) - | (0xeU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id))))))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_stall)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_busy)) - | (~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - == (0xeU | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))))))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stb)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stall))))) { - if (vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb) { - vlSelf->main__DOT__swic__DOT__dbg_sel = vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_sel; - vlSelf->main__DOT__swic__DOT__dbg_idata - = vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_data; - } else { - vlSelf->main__DOT__swic__DOT__dbg_sel = 0xfU; - vlSelf->main__DOT__swic__DOT__dbg_idata - = vlSelf->main__DOT____Vcellinp__swic__i_dbg_data; - } - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb - = (1U & ((IData)(vlSelf->i_reset) | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown)) - | (0U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd))) - | ((1U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - | ((2U - == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd)) - ? - (((0x200U - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - ? 1U - : 2U) - >> 1U) - : (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk)))))); - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown = 0U; - } else { - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request = 1U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_request = 0U; - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown - = (1U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xfU)); - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready - = ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_mem_ready)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = (0xc0000000U | ((0x3fffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__lgblk) - << 0x18U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = ((0xffc01fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_sample_shift) - << 0x10U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk_shutdown) - << 0xfU) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_clk90) - << 0xeU) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_cmd) - << 0xdU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = ((0xffffe000U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__pp_data) - << 0xcU) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_width) - << 0xaU)) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cfg_ds) - << 9U) | - (((IData)(vlSelf->main__DOT__u_sdcard__DOT__cfg_ddr) - << 8U) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__clk_ckspd))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset - = (1U & (((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present))) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (0xf00000000ULL == (0xf00000000ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (0x52000000U == vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_mem) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_stalled)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_div) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid_alu)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb - = (1U & (((0xffU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter)) - - (IData)(1U)) >> 8U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter) - - (IData)(1U)))); - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_stb) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0 - = (1U & (((IData)(1U) + (3U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 8U))) - >> 2U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0 - = (3U & ((IData)(1U) + ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter) - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h50d55398__0; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0xffU & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT____Vconcswap_1_h561f6367__0) - << 8U)); - if ((1U >= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk = 1U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = (0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - } else if ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk - = (1U & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__counter) - >> 9U)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = (0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)); - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd) - - (IData)(3U)))); - } - } - if (vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_clk) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter - = ((1U >= (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)) - ? 0x300U : ((2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed)) - ? 0x100U : ((0x300U & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__nxt_counter)) - | (0xffU & - ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed) - - (IData)(3U)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_ckspeed; - } else { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_clk90 - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__clk90; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__w_ckspd - = vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_clkgen__DOT__ckspd; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_ce - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__set_cond)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall - = (((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__adf_ce_unconditional) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__mem_ce))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid)) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - & ((IData)(vlSelf->main__DOT__swic__DOT__cmd_halt) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U))) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A) - >> 6U) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)))) - | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h39e03a19__0) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy)) - & (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_zI)) - & ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - == (0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR)) - | (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_OPIPE__DOT__r_pipe)) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy)) - | ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__r_busy) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__div_busy) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_rdbusy))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_reg) - == (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (0xeU - == (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_he857573c__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U)))) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 6U) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_cc_invalid_for_dcd)))) - | (((~ ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_F) - >> 3U)) | (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rA) - & (IData)( - ((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))) - & ((0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB) - & (IData)( - ((0xeU - == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B))) - & ((0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B)) - != - (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U)))))))) - & (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_valid) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_WR__DOT__r_op_wR) - & (IData)(((0xeU == - (0xeU - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R))) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_R) - != (0xfU - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - << 4U))))))) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__GEN_OP_STALL__DOT__r_pending_sreg_write)))))))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__doalu__DOT__this_is_a_multiply_op - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__alu_ce) - & ((5U == (7U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn) - >> 1U))) | (0xcU == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__FWD_OPERATION__DOT__r_op_opn)))); - if (((IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)))) { - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_sel = 0xfU; - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_data - = vlSelf->main__DOT____Vcellinp__swic__i_dbg_data; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_busy - = (1U & ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__r_busy))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__start_packet - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_txframe__S_VALID) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & (~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_valid))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__w_no_response - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__active) - & ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cmd_type)) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb) - & ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__srcount) - == ((IData)(1U) + (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_sdcmd__DOT__cfg_dbl)))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready - = ((0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__ck_counts)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_stb)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset)); - if ((1U & ((IData)(vlSelf->i_reset) | (~ ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present) - >> 2U))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present = 0U; - } else if ((0x3ffU == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present = 1U; - } - vlSelf->main__DOT__swic__DOT__cpu_op_stall = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__master_ce) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_illegal) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_stall)); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src) - | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_src); - if (vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc) { - vlSelf->main__DOT__swic__DOT__sys_we = vlSelf->main__DOT__swic__DOT__cpu_we; - vlSelf->main__DOT__swic__DOT__sys_addr = (0xffU - & vlSelf->main__DOT__swic__DOT__cpu_addr); - vlSelf->main__DOT__swic__DOT__sys_data = vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_data[0U]; - } else { - vlSelf->main__DOT__swic__DOT__sys_we = vlSelf->main__DOT__swic__DOT__dbg_we; - vlSelf->main__DOT__swic__DOT__sys_addr = (0xffU - & (0x1fU - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))); - vlSelf->main__DOT__swic__DOT__sys_data = vlSelf->main__DOT__swic__DOT__dbg_idata; - } - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_src - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst) - | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_dst); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_dst - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len - = ((0xf0000000U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len) - | vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_length); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_len - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen = 0U; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen - = ((0xfffffc00U & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen) - | (0x3ffU & (IData)(vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__dma_transferlen))); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen - = vlSelf->main__DOT__swic__DOT__sys_data; - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen - = (0x3ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen); - vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen - = ((0xfffffbffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen) - | ((0U == (0x3ffU & vlSelf->main__DOT__swic__DOT__DMA__DOT__dma_controller__DOT__u_controller__DOT__next_tlen)) - << 0xaU)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pre_ready) - & ((1U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate)) - | (0U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_txframe__DOT__pstate)))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__card_detect_counter; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present - = vlSelf->__Vdly__main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__raw_card_present; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc - = ((0x20U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - ? 5U : ((0x40U & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A)) - ? 6U : 7U)); - } - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) { - if (((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT____VdfgTmp_h740acd49__0) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rA)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 4U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - == (0x1fU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_A))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__avsrc = 4U; - } - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__op_ce) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc - = ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_full_B) - >> 5U) & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_rB)) - ? 4U : 5U); - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_rB) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__OP_REG_ADVANEC__DOT__r_op_Bid) - == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__bvsrc = 6U; - } - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_ce - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__r_valid)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready - = (1U & ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dcd_stalled)) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_CIS_PHASE__DOT__r_phase)))); - if ((1U & (((((IData)(vlSelf->main__DOT____Vcellinp__swic__i_reset) - | (~ (IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc))) - | (IData)(vlSelf->main__DOT__swic__DOT__no_dbg_err)) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stall))) - | (~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stb))))) { - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb = 0U; - } else if (((IData)(vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb) - & (~ (IData)(vlSelf->main__DOT__raw_cpu_dbg_stall)))) { - vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb = 1U; - } - if (vlSelf->cpu_sim_cyc) { - vlSelf->main__DOT____Vcellinp__swic__i_dbg_data - = vlSelf->cpu_sim_data; - vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb - = (1U & (IData)(vlSelf->cpu_sim_stb)); - } else { - vlSelf->main__DOT____Vcellinp__swic__i_dbg_data - = (IData)((vlSelf->main__DOT____Vcellout__wbu_xbar__o_sdata - >> 0x20U)); - vlSelf->main__DOT____Vcellinp__swic__i_dbg_stb - = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - >> 1U)); - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_control__i_tx_mem_ready - = ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_mem_ready)); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl = 0U; - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = (0xc0000000U | ((0x3fffffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__lgblk) - << 0x18U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = ((0xffc01fffU & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | (((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_sample_shift) - << 0x10U) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk_shutdown) - << 0xfU) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_clk90) - << 0xeU) - | ((IData)(vlSelf->main__DOT__u_emmc__DOT__pp_cmd) - << 0xdU))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl - = ((0xffffe000U & vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__w_phy_ctrl) - | ((((IData)(vlSelf->main__DOT__u_emmc__DOT__pp_data) - << 0xcU) | ((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_width) - << 0xaU)) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cfg_ds) - << 9U) | - (((IData)(vlSelf->main__DOT__u_emmc__DOT__cfg_ddr) - << 8U) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__clk_ckspd))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset - = ((IData)(vlSelf->i_reset) | (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (0xf000000ULL - == (0xf000000ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (0x52000000U - == vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word = 0U; - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xf0ffffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - << 0x1bU) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request) - << 0x1aU) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en) - << 0x19U) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request) - << 0x18U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffc7ffffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((0U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__fif_rdaddr)) - << 0x15U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__dat0_busy) - << 0x14U) | (0x80000U - & ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_present)) - << 0x13U))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfff83fffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__GEN_CARD_DETECT__DOT__r_card_removed) - << 0x12U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_ecode) - << 0x10U) | (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd_err) - << 0xfU) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - << 0xeU))))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffffcfffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_fifo) - << 0xcU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfffff7ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)))) - << 0xbU)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xfffff8ffU & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - << 0xaU) | ((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type) - << 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word - = ((0xffffff80U & vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__w_cmd_word) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_cmd)); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__w_advance - = ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_new_pc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PFCACHE__DOT__pf__DOT__r_v) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready))); - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 0U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 0U; - if (vlSelf->main__DOT__swic__DOT__cmd_reset) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 0U; - } else if ((((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbgv) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce)) - & (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_switch_to_interrupt) - | ((~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 2U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__w_release_from_interrupt) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__r_clear_icache) - | (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__dbg_clear_pipe))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 3U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_ce) - & (((1U & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id) - >> 4U)) == (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__SET_GIE__DOT__r_gie)) - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__wr_reg_id)))))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 1U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__instruction_decoder__DOT__GEN_EARLY_BRANCH_LOGIC__DOT__r_early_branch_stb) - & (~ (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 4U; - } else if (((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__new_pc) - | ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_ready) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__pf_valid)))) { - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcset = 1U; - vlSelf->main__DOT__swic__DOT__thecpu__DOT__core__DOT__pfpcsrc = 5U; - } - vlSelf->main__DOT____Vcellinp__swic__i_dbg_cyc - = (IData)((((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_scyc) - >> 1U) | (IData)(vlSelf->cpu_sim_cyc))); - vlSelf->main__DOT__swic__DOT__dbg_stall = ((IData)(vlSelf->main__DOT__swic__DOT__cmd_read) - | (((IData)(vlSelf->main__DOT__swic__DOT__cmd_write) - & ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__w_dbg_stall) - & (0x20U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))))) - | (((IData)(vlSelf->main__DOT__swic__DOT__dbg_addr) - >> 6U) - & (IData)(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc)))); - vlSelf->main__DOT__swic__DOT__dbg_stb = vlSelf->__Vdly__main__DOT__swic__DOT__dbg_stb; - vlSelf->main__DOT__swic__DOT__sys_stb = ((IData)(vlSelf->main__DOT__swic__DOT__cpu_lcl_cyc) - ? ((IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__PRIORITY_DATA__DOT__pformem__DOT__r_a_owner) - & (IData)(vlSelf->main__DOT__swic__DOT__thecpu__DOT__mem_stb_lcl)) - : ((IData)(vlSelf->main__DOT__swic__DOT__dbg_stb) - & (0x40U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))))); - vlSelf->main__DOT__swic__DOT__no_dbg_err = 0U; - vlSelf->main__DOT__raw_cpu_dbg_stall = vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb; - vlSelf->cpu_sim_stall = (1U & ((~ (IData)(vlSelf->cpu_sim_cyc)) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb))); - vlSelf->main__DOT__wbu_xbar__DOT__s_stall = (0xcU - | ((0xfffffffeU - & ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - & (((IData)(vlSelf->cpu_sim_cyc) - | (IData)(vlSelf->main__DOT__swic__DOT__DELAY_THE_DEBUG_BUS__DOT__wbdelay__DOT__SKIDBUFFER__DOT__r_stb)) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbu_xbar__o_sstb) - & (IData)(vlSelf->main__DOT__wbu_wbu_arbiter_stall)))); - vlSelf->main__DOT__swic__DOT____VdfgTmp_h9a48e2a3__0 - = ((~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_stall)) - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_stb)); - vlSelf->main__DOT__swic__DOT__dbg_cmd_write = ((IData)(vlSelf->main__DOT__swic__DOT__dbg_stb) - & ((IData)(vlSelf->main__DOT__swic__DOT__dbg_we) - & (0U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT____Vcellinp__u_sdcmd__i_reset - = ((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__soft_reset)); - vlSelf->main__DOT__swic__DOT__dbg_cpu_read = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h9a48e2a3__0) - & ((~ (IData)(vlSelf->main__DOT__swic__DOT__dbg_we)) - & (0x20U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))))); - vlSelf->main__DOT__swic__DOT__dbg_cpu_write = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h9a48e2a3__0) - & ((IData)(vlSelf->main__DOT__swic__DOT__dbg_we) - & (IData)( - ((0x20U - == - (0x60U - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_addr))) - & (0xfU - == (IData)(vlSelf->main__DOT__swic__DOT__dbg_sel)))))); - vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0 - = ((IData)(vlSelf->main__DOT__swic__DOT__dbg_cmd_write) - & (IData)(vlSelf->main__DOT__swic__DOT__dbg_sel)); - vlSelf->main__DOT__swic__DOT__sel_bus_watchdog - = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (2U == (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))); - vlSelf->main__DOT__swic__DOT__sel_dmac = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (0x10U - == - (0xf0U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT__sel_watchdog = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (1U - == (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))); - vlSelf->main__DOT__swic__DOT__sel_apic = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (3U - == (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))); - vlSelf->main__DOT__swic__DOT__sel_pic = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (0U - == (IData)(vlSelf->main__DOT__swic__DOT__sys_addr))); - vlSelf->main__DOT__swic__DOT__sel_timer = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (4U - == - (0xfcU - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT__actr_ack = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (8U - == - (0xf8U - & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT__reset_request = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0) - & (vlSelf->main__DOT__swic__DOT__dbg_idata - >> 3U)); - vlSelf->main__DOT__swic__DOT__step_request = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0) - & (vlSelf->main__DOT__swic__DOT__dbg_idata - >> 2U)); - vlSelf->main__DOT__swic__DOT__halt_request = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0) - & vlSelf->main__DOT__swic__DOT__dbg_idata); - vlSelf->main__DOT__swic__DOT__clear_cache_request - = ((IData)(vlSelf->main__DOT__swic__DOT____VdfgTmp_h145b7951__0) - & (vlSelf->main__DOT__swic__DOT__dbg_idata - >> 4U)); - vlSelf->main__DOT__swic__DOT__dmac_stb = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_dmac)); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchdog__i_wb_stb - = ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_watchdog)); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write - = (((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_apic)) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write - = (((IData)(vlSelf->main__DOT__swic__DOT__sys_cyc) - & ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_pic))) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0 = - ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sel_timer)); - vlSelf->main__DOT__swic__DOT__w_ack_idx = 0U; - if (vlSelf->main__DOT__swic__DOT__sel_watchdog) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (1U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_bus_watchdog) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (2U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_apic) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (3U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_timer) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (4U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__actr_ack) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (5U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_dmac) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = (6U - | (IData)(vlSelf->main__DOT__swic__DOT__w_ack_idx)); - } - if (vlSelf->main__DOT__swic__DOT__sel_pic) { - vlSelf->main__DOT__swic__DOT__w_ack_idx = 7U; - } - main__DOT__swic__DOT____VdfgTmp_hcb574c13__0 = - ((IData)(vlSelf->main__DOT__swic__DOT__sys_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__actr_ack)); - vlSelf->main__DOT__swic__DOT__u_watchdog__DOT__wb_write - = ((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_watchdog__i_wb_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__enable_ints - = ((IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write) - & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0xfU)); - vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__disable_ints - = ((~ (vlSelf->main__DOT__swic__DOT__sys_data - >> 0xfU)) & (IData)(vlSelf->main__DOT__swic__DOT__PIC_WITH_ACCOUNTING__DOT__ALT_PIC__DOT__ctri__DOT__wb_write)); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__enable_ints - = ((IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write) - & (vlSelf->main__DOT__swic__DOT__sys_data - >> 0xfU)); - vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__disable_ints - = ((~ (vlSelf->main__DOT__swic__DOT__sys_data - >> 0xfU)) & (IData)(vlSelf->main__DOT__swic__DOT__MAIN_PIC__DOT__pic__DOT__wb_write)); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_jiffies__i_wb_stb - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0) - & (3U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_a__i_wb_stb - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0) - & (0U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_b__i_wb_stb - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0) - & (1U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_c__i_wb_stb - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb06aa5b__0) - & (2U == (3U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mtask_ctr____pinNumber5 - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb574c13__0) - & (0U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mmstall_ctr____pinNumber5 - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb574c13__0) - & (1U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mpstall_ctr____pinNumber5 - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb574c13__0) - & (2U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__mins_ctr____pinNumber5 - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb574c13__0) - & (3U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__utask_ctr____pinNumber5 - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb574c13__0) - & (4U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__umstall_ctr____pinNumber5 - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb574c13__0) - & (5U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__upstall_ctr____pinNumber5 - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb574c13__0) - & (6U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT____Vcellinp__ACCOUNTING_COUNTERS__DOT__uins_ctr____pinNumber5 - = ((IData)(main__DOT__swic__DOT____VdfgTmp_hcb574c13__0) - & (7U == (7U & (IData)(vlSelf->main__DOT__swic__DOT__sys_addr)))); - vlSelf->main__DOT__swic__DOT__u_timer_a__DOT__wb_write - = ((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_a__i_wb_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - vlSelf->main__DOT__swic__DOT__u_timer_b__DOT__wb_write - = ((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_b__i_wb_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); - vlSelf->main__DOT__swic__DOT__u_timer_c__DOT__wb_write - = ((IData)(vlSelf->main__DOT__swic__DOT____Vcellinp__u_timer_c__i_wb_stb) - & (IData)(vlSelf->main__DOT__swic__DOT__sys_we)); -} - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__5(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__5\n"); ); - // Init - CData/*1:0*/ main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 = 0; - IData/*27:0*/ __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0; - CData/*4:0*/ __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address = 0; - SData/*15:0*/ __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_counter; - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_counter = 0; - IData/*27:0*/ __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction; - __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction = 0; - CData/*4:0*/ __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction_address; - __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction_address = 0; - CData/*0:0*/ __Vdly__main__DOT__ddr3_controller_inst__DOT__reset_done; - __Vdly__main__DOT__ddr3_controller_inst__DOT__reset_done = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v0; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v0 = 0; - CData/*0:0*/ __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v0; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v0 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v1; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v1 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v2; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v2 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v3; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v3 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v4; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v4 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v5; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v5 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v6; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v6 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v7; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v7 = 0; - CData/*0:0*/ __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v8; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v8 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v0; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v0 = 0; - CData/*0:0*/ __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v0; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v0 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v1; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v1 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v2; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v2 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v3; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v3 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v4; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v4 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v5; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v5 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v6; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v6 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v7; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v7 = 0; - CData/*0:0*/ __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v8; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v8 = 0; - CData/*3:0*/ __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v0; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v0 = 0; - CData/*0:0*/ __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v0; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v0 = 0; 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- __Vdly__main__DOT__ddr3_controller_inst__DOT__index_wb_data - = vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v0 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v2 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v1 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v2 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v3 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v4 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v5 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v6 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v7 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v8 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v9 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v10 = 0U; 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- __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[2U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[3U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[1U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[2U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[3U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[4U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[5U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[6U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[7U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[8U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[8U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[9U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[9U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xaU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xaU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xbU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xbU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xcU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xcU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xdU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xdU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xeU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xeU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xfU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xfU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback - = vlSelf->main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_store - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dq_target_index - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index; - __Vdly__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev - = vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane_times_8 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8; - __Vdly__o_ddr3_controller_idelay_dqs_ld = vlSelf->o_ddr3_controller_idelay_dqs_ld; - __Vdly__o_ddr3_controller_idelay_data_ld = vlSelf->o_ddr3_controller_idelay_data_ld; - __Vdly__o_ddr3_controller_odelay_dqs_ld = vlSelf->o_ddr3_controller_odelay_dqs_ld; - __Vdly__o_ddr3_controller_odelay_data_ld = vlSelf->o_ddr3_controller_odelay_data_ld; - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback; - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_read_data - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data; - __Vdly__main__DOT__ddr3_controller_inst__DOT__train_delay - = vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_calib_stb - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_stb; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v0 = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__data_start_index__v0 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__data_start_index__v1 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__data_start_index__v2 = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane - = vlSelf->main__DOT__ddr3_controller_inst__DOT__lane; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v0 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v1 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v2 = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate - = vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v1 = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__reset_done - = vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done; - __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction_address - = vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address; - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_counter - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter; - __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction - = vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction; - __Vdly__main__DOT__ddr3_controller_inst__DOT__stage1_pending - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending; - __Vdly__main__DOT__ddr3_controller_inst__DOT__stage2_pending - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__stage2_data__v65 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v0 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v65 = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v0 = 0U; - if ((1U & (~ (IData)(vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n)))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 8U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dq = 0U; - if (vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n) { - vlSelf->main__DOT__wb32_ddr3_phy_ack = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 0xbU)); - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 8U; - if ((0x14U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 8U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 1U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 0x10U; - if (((~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 2U)) & (0xeU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate)))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 5U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v5 = 1U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v17 = 1U; - } - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_val - = ((6U & (IData)(__Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_val)) - | (1U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_q)))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_q - = ((2U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_q) - << 1U)) | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d)); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs - = ((6U & (IData)(__Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs)) - | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d) - | (0U != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_q)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_h133f9401__0 - = (1U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs)); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs - = ((5U & (IData)(__Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs)) - | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_h133f9401__0) - << 1U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_hddcbe2f8__0 - = (1U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_val)); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_val - = ((5U & (IData)(__Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_val)) - | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_hddcbe2f8__0) - << 1U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_h133f9401__0 - = (1U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs) - >> 1U)); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs - = ((3U & (IData)(__Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs)) - | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_h133f9401__0) - << 2U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_hddcbe2f8__0 - = (1U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_val) - >> 1U)); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_val - = ((3U & (IData)(__Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_val)) - | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_hddcbe2f8__0) - << 2U)); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dq - = ((8U & (IData)(__Vdly__main__DOT__ddr3_controller_inst__DOT__write_dq)) - | ((4U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq) - << 1U)) | ((2U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq) - << 1U)) - | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_q))))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dq - = ((7U & (IData)(__Vdly__main__DOT__ddr3_controller_inst__DOT__write_dq)) - | (8U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq) - << 1U))); - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d - [0U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v0 = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d - [1U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v1 = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d - [2U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v2 = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d - [3U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v3 - = vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v3 = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d - [4U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v4 - = vlSelf->main__DOT__ddr3_controller_inst__DOT____Vlvbound_ha8bc7f27__1; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v4 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v0 - = (0xffffU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> 1U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v0 = 1U; - if ((1U & vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U])) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__index_wb_data - = (1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data))); - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v1 - = (0xffffU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> 1U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v1 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [1U]; - if ((1U & vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [1U])) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__index_read_pipe - = (1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__index_read_pipe))); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v2 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max; - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__index_read_pipe; - } - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [0U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v0 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0U]); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v0 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v0 = 0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v1 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[2U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v1 = 0x40U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v2 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[4U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v2 = 0x80U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v3 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[6U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v3 = 0xc0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v4 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[8U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v4 = 0x100U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v5 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xaU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v5 = 0x140U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v6 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xcU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v6 = 0x180U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v7 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xeU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v7 = 0x1c0U; - } - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [0U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v8 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0U]); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v8 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v8 = 0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v9 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[2U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v9 = 0x40U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v10 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[4U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v10 = 0x80U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v11 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[6U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v11 = 0xc0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v12 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[8U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v12 = 0x100U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v13 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xaU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v13 = 0x140U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v14 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xcU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v14 = 0x180U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v15 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xeU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v15 = 0x1c0U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [2U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v1 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [1U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v16 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0U] - >> 8U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v16 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v16 = 8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v17 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[2U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v17 = 0x48U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v18 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[4U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v18 = 0x88U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v19 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[6U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v19 = 0xc8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v20 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[8U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v20 = 0x108U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v21 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xaU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v21 = 0x148U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v22 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xcU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v22 = 0x188U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v23 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xeU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v23 = 0x1c8U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [3U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v2 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [1U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v24 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0U] - >> 8U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v24 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v24 = 8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v25 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[2U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v25 = 0x48U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v26 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[4U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v26 = 0x88U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v27 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[6U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v27 = 0xc8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v28 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[8U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v28 = 0x108U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v29 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xaU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v29 = 0x148U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v30 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xcU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v30 = 0x188U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v31 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xeU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v31 = 0x1c8U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v3 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [4U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v3 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [2U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v32 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0U] - >> 0x10U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v32 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v32 = 0x10U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v33 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[2U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v33 = 0x50U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v34 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[4U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v34 = 0x90U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v35 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[6U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v35 = 0xd0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v36 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[8U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v36 = 0x110U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v37 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xaU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v37 = 0x150U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v38 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xcU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v38 = 0x190U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v39 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xeU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v39 = 0x1d0U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v4 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [5U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v4 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [2U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v40 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0U] - >> 0x10U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v40 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v40 = 0x10U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v41 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[2U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v41 = 0x50U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v42 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[4U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v42 = 0x90U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v43 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[6U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v43 = 0xd0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v44 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[8U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v44 = 0x110U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v45 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xaU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v45 = 0x150U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v46 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xcU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v46 = 0x190U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v47 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xeU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v47 = 0x1d0U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v5 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [6U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v5 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [3U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v48 - = (vlSelf->i_ddr3_controller_iserdes_data[0U] - >> 0x18U); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v48 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v48 = 0x18U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v49 - = (vlSelf->i_ddr3_controller_iserdes_data[2U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v49 = 0x58U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v50 - = (vlSelf->i_ddr3_controller_iserdes_data[4U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v50 = 0x98U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v51 - = (vlSelf->i_ddr3_controller_iserdes_data[6U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v51 = 0xd8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v52 - = (vlSelf->i_ddr3_controller_iserdes_data[8U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v52 = 0x118U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v53 - = (vlSelf->i_ddr3_controller_iserdes_data[0xaU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v53 = 0x158U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v54 - = (vlSelf->i_ddr3_controller_iserdes_data[0xcU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v54 = 0x198U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v55 - = (vlSelf->i_ddr3_controller_iserdes_data[0xeU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v55 = 0x1d8U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v6 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [7U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v6 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [3U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v56 - = (vlSelf->i_ddr3_controller_iserdes_data[0U] - >> 0x18U); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v56 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v56 = 0x18U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v57 - = (vlSelf->i_ddr3_controller_iserdes_data[2U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v57 = 0x58U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v58 - = (vlSelf->i_ddr3_controller_iserdes_data[4U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v58 = 0x98U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v59 - = (vlSelf->i_ddr3_controller_iserdes_data[6U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v59 = 0xd8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v60 - = (vlSelf->i_ddr3_controller_iserdes_data[8U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v60 = 0x118U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v61 - = (vlSelf->i_ddr3_controller_iserdes_data[0xaU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v61 = 0x158U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v62 - = (vlSelf->i_ddr3_controller_iserdes_data[0xcU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v62 = 0x198U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v63 - = (vlSelf->i_ddr3_controller_iserdes_data[0xeU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v63 = 0x1d8U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v7 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [8U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v7 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [4U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v64 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[1U]); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v64 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v64 = 0x20U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v65 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[3U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v65 = 0x60U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v66 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[5U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v66 = 0xa0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v67 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[7U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v67 = 0xe0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v68 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[9U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v68 = 0x120U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v69 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xbU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v69 = 0x160U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v70 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xdU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v70 = 0x1a0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v71 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xfU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v71 = 0x1e0U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v8 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [9U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v8 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [4U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v72 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[1U]); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v72 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v72 = 0x20U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v73 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[3U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v73 = 0x60U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v74 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[5U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v74 = 0xa0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v75 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[7U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v75 = 0xe0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v76 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[9U]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v76 = 0x120U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v77 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xbU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v77 = 0x160U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v78 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xdU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v78 = 0x1a0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v79 - = (0xffU & vlSelf->i_ddr3_controller_iserdes_data[0xfU]); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v79 = 0x1e0U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v9 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0xaU]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v9 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [5U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v80 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[1U] - >> 8U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v80 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v80 = 0x28U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v81 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[3U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v81 = 0x68U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v82 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[5U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v82 = 0xa8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v83 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[7U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v83 = 0xe8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v84 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[9U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v84 = 0x128U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v85 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xbU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v85 = 0x168U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v86 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xdU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v86 = 0x1a8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v87 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xfU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v87 = 0x1e8U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v10 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0xbU]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v10 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [5U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v88 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[1U] - >> 8U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v88 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v88 = 0x28U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v89 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[3U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v89 = 0x68U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v90 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[5U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v90 = 0xa8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v91 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[7U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v91 = 0xe8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v92 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[9U] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v92 = 0x128U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v93 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xbU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v93 = 0x168U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v94 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xdU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v94 = 0x1a8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v95 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xfU] - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v95 = 0x1e8U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v11 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0xcU]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v11 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [6U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v96 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[1U] - >> 0x10U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v96 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v96 = 0x30U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v97 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[3U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v97 = 0x70U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v98 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[5U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v98 = 0xb0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v99 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[7U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v99 = 0xf0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v100 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[9U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v100 = 0x130U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v101 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xbU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v101 = 0x170U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v102 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xdU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v102 = 0x1b0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v103 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xfU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v103 = 0x1f0U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v12 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0xdU]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v12 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [6U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v104 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[1U] - >> 0x10U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v104 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v104 = 0x30U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v105 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[3U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v105 = 0x70U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v106 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[5U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v106 = 0xb0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v107 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[7U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v107 = 0xf0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v108 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[9U] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v108 = 0x130U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v109 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xbU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v109 = 0x170U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v110 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xdU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v110 = 0x1b0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v111 - = (0xffU & (vlSelf->i_ddr3_controller_iserdes_data[0xfU] - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v111 = 0x1f0U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v13 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0xeU]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v13 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [0U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [7U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v112 - = (vlSelf->i_ddr3_controller_iserdes_data[1U] - >> 0x18U); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v112 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v112 = 0x38U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v113 - = (vlSelf->i_ddr3_controller_iserdes_data[3U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v113 = 0x78U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v114 - = (vlSelf->i_ddr3_controller_iserdes_data[5U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v114 = 0xb8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v115 - = (vlSelf->i_ddr3_controller_iserdes_data[7U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v115 = 0xf8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v116 - = (vlSelf->i_ddr3_controller_iserdes_data[9U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v116 = 0x138U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v117 - = (vlSelf->i_ddr3_controller_iserdes_data[0xbU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v117 = 0x178U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v118 - = (vlSelf->i_ddr3_controller_iserdes_data[0xdU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v118 = 0x1b8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v119 - = (vlSelf->i_ddr3_controller_iserdes_data[0xfU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v119 = 0x1f8U; - } - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v14 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0xfU]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v14 = 1U; - if ((1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [1U] >> ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - != vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [7U])))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v120 - = (vlSelf->i_ddr3_controller_iserdes_data[1U] - >> 0x18U); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v120 = 1U; - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v120 = 0x38U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v121 - = (vlSelf->i_ddr3_controller_iserdes_data[3U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v121 = 0x78U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v122 - = (vlSelf->i_ddr3_controller_iserdes_data[5U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v122 = 0xb8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v123 - = (vlSelf->i_ddr3_controller_iserdes_data[7U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v123 = 0xf8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v124 - = (vlSelf->i_ddr3_controller_iserdes_data[9U] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v124 = 0x138U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v125 - = (vlSelf->i_ddr3_controller_iserdes_data[0xbU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v125 = 0x178U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v126 - = (vlSelf->i_ddr3_controller_iserdes_data[0xdU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v126 = 0x1b8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v127 - = (vlSelf->i_ddr3_controller_iserdes_data[0xfU] - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v127 = 0x1f8U; - } - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v15 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v16 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [0U]; - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v16 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max; - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_counter - = (0xffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction); - } else if ((1U & ((vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0x1aU) & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter))))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_counter - = (0xffffU & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter) - - (IData)(1U))); - } - if ((1U & ((1U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter)) - | (~ (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0x1aU))))) { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address - = vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address; - if ((0x10U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - if ((8U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x1b80000U; - } else if ((4U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - if ((2U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout - = ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? 0x1b80000U : 0x5b80005U); - } else if ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = 0x30cU; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0xdb8030cU; - } else { - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = 0x23U; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x5880023U; - } - } else if ((2U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - if ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = 2U; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x7900002U; - } else { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x5b80003U; - } - } else { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout - = ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? 0x1810844U : 0x5b80002U); - } - } else if ((8U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - if ((4U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout - = ((2U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? 0x5b8000aU : 0x18108c4U) - : ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? 0x1830000U : 0x5b80002U)); - } else if ((2U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout - = ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? 0x5b80003U : 0x1830004U); - } else if ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = 2U; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x7900002U; - } else { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x7b00080U; - } - } else if ((4U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout - = ((2U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? 0x5b80003U : 0x3800720U) - : ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address)) - ? 0x1810844U : 0x1830000U)); - } else if ((2U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - if ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x1820040U; - } else { - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = 0x24U; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x5b80024U; - } - } else if ((1U & (IData)(__Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__instruction_address))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = 0xc350U; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x4b8c350U; - } else { - vlSelf->main__DOT__ddr3_controller_inst__DOT__ns_to_cycles__Vstatic__result = 0x4e20U; - __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout = 0x4384e20U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction - = __Vfunc_main__DOT__ddr3_controller_inst__DOT__read_rom_instruction__0__Vfuncout; - __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction_address - = ((0x16U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address)) - ? 0x13U : (0x1fU & ((IData)(1U) - + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address)))); - } else { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero = 0U; - } - __Vdly__main__DOT__ddr3_controller_inst__DOT__reset_done - = (IData)(((vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0x1bU) | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_calib_stb = 0U; - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d - [0U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v0 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d - [1U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d - [2U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v3 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d - [3U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v4 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d - [4U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v5 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d - [5U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v6 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d - [6U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v7 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d - [7U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d - [0U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v0 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d - [1U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d - [2U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v3 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d - [3U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v4 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d - [4U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v5 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d - [5U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v6 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d - [6U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v7 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d - [7U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [0U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v0 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [1U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [2U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v3 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [3U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v4 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [4U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v5 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [5U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v6 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [6U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v7 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [7U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [0U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v0 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [1U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [2U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v3 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [3U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v4 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [4U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v5 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [5U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v6 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [6U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v7 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [7U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [0U]; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v0 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [1U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v2 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [2U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v3 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [3U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v4 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [4U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v5 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [5U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v6 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [6U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v7 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [7U]; - __Vtemp_h6ea6d067__0[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__0[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__0[2U] = 0U; - __Vtemp_h6ea6d067__0[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hed0a7d04__0, __Vtemp_h6ea6d067__0, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v0 - = (((QData)((IData)(__Vtemp_hed0a7d04__0[3U])) - << 0x20U) | (QData)((IData)(__Vtemp_hed0a7d04__0[2U]))); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v0 = 1U; - __Vtemp_h6ea6d067__1[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__1[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__1[2U] = 0U; - __Vtemp_h6ea6d067__1[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h8320a046__0, __Vtemp_h6ea6d067__1, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v0 - = ((__Vtemp_h8320a046__0[1U] | (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [0U] - >> 0x20U))) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v0 = 0x1c0U; - __Vtemp_h6ea6d067__2[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__2[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__2[2U] = 0U; - __Vtemp_h6ea6d067__2[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h9842db6f__0, __Vtemp_h6ea6d067__2, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v1 - = (0xffU & ((__Vtemp_h9842db6f__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [0U] >> 0x20U))) - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v1 = 0x180U; - __Vtemp_h6ea6d067__3[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__3[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__3[2U] = 0U; - __Vtemp_h6ea6d067__3[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h89bb0ced__0, __Vtemp_h6ea6d067__3, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v2 - = (0xffU & ((__Vtemp_h89bb0ced__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [0U] >> 0x20U))) - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v2 = 0x140U; - __Vtemp_h6ea6d067__4[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__4[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__4[2U] = 0U; - __Vtemp_h6ea6d067__4[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h8b401198__0, __Vtemp_h6ea6d067__4, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v3 - = (0xffU & (__Vtemp_h8b401198__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [0U] >> 0x20U)))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v3 = 0x100U; - __Vtemp_h6ea6d067__5[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__5[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__5[2U] = 0U; - __Vtemp_h6ea6d067__5[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h22ceb480__0, __Vtemp_h6ea6d067__5, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v4 - = ((__Vtemp_h22ceb480__0[0U] | (IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [0U])) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v4 = 0xc0U; - __Vtemp_h6ea6d067__6[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__6[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__6[2U] = 0U; - __Vtemp_h6ea6d067__6[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h13e46b59__0, __Vtemp_h6ea6d067__6, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v5 - = (0xffU & ((__Vtemp_h13e46b59__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [0U])) >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v5 = 0x80U; - __Vtemp_h6ea6d067__7[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__7[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__7[2U] = 0U; - __Vtemp_h6ea6d067__7[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h35866c4b__0, __Vtemp_h6ea6d067__7, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v6 - = (0xffU & ((__Vtemp_h35866c4b__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [0U])) >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v6 = 0x40U; - __Vtemp_h6ea6d067__8[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U])))))))); - __Vtemp_h6ea6d067__8[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U]))))))) - >> 0x20U)); - __Vtemp_h6ea6d067__8[2U] = 0U; - __Vtemp_h6ea6d067__8[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h0975367d__0, __Vtemp_h6ea6d067__8, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v7 - = (0xffU & (__Vtemp_h0975367d__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [0U]))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v7 = 0U; - __Vtemp_h63f690ae__0[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__0[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__0[2U] = 0U; - __Vtemp_h63f690ae__0[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h3de8942d__0, __Vtemp_h63f690ae__0, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v1 - = (((QData)((IData)(__Vtemp_h3de8942d__0[3U])) - << 0x20U) | (QData)((IData)(__Vtemp_h3de8942d__0[2U]))); - __Vtemp_h63f690ae__1[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__1[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__1[2U] = 0U; - __Vtemp_h63f690ae__1[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hd558cea0__0, __Vtemp_h63f690ae__1, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v8 - = ((__Vtemp_hd558cea0__0[1U] | (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [1U] - >> 0x20U))) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v8 = 0x1c8U; - __Vtemp_h63f690ae__2[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__2[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__2[2U] = 0U; - __Vtemp_h63f690ae__2[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h8d975d18__0, __Vtemp_h63f690ae__2, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v9 - = (0xffU & ((__Vtemp_h8d975d18__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [1U] >> 0x20U))) - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v9 = 0x188U; - __Vtemp_h63f690ae__3[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__3[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__3[2U] = 0U; - __Vtemp_h63f690ae__3[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h99ba3b4b__0, __Vtemp_h63f690ae__3, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v10 - = (0xffU & ((__Vtemp_h99ba3b4b__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [1U] >> 0x20U))) - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v10 = 0x148U; - __Vtemp_h63f690ae__4[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__4[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__4[2U] = 0U; - __Vtemp_h63f690ae__4[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h1cf0ad81__0, __Vtemp_h63f690ae__4, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v11 - = (0xffU & (__Vtemp_h1cf0ad81__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [1U] >> 0x20U)))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v11 = 0x108U; - __Vtemp_h63f690ae__5[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__5[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__5[2U] = 0U; - __Vtemp_h63f690ae__5[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hf976ff2d__0, __Vtemp_h63f690ae__5, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v12 - = ((__Vtemp_hf976ff2d__0[0U] | (IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [1U])) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v12 = 0xc8U; - __Vtemp_h63f690ae__6[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__6[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__6[2U] = 0U; - __Vtemp_h63f690ae__6[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_ha5e653c1__0, __Vtemp_h63f690ae__6, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v13 - = (0xffU & ((__Vtemp_ha5e653c1__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [1U])) >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v13 = 0x88U; - __Vtemp_h63f690ae__7[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__7[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__7[2U] = 0U; - __Vtemp_h63f690ae__7[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_he1da6c12__0, __Vtemp_h63f690ae__7, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v14 - = (0xffU & ((__Vtemp_he1da6c12__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [1U])) >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v14 = 0x48U; - __Vtemp_h63f690ae__8[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U))))))))); - __Vtemp_h63f690ae__8[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h63f690ae__8[2U] = 0U; - __Vtemp_h63f690ae__8[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h0b67dce0__0, __Vtemp_h63f690ae__8, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v15 - = (0xffU & (__Vtemp_h0b67dce0__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [1U]))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v15 = 8U; - __Vtemp_h6a893729__0[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__0[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__0[2U] = 0U; - __Vtemp_h6a893729__0[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h81ba268b__0, __Vtemp_h6a893729__0, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v2 - = (((QData)((IData)(__Vtemp_h81ba268b__0[3U])) - << 0x20U) | (QData)((IData)(__Vtemp_h81ba268b__0[2U]))); - __Vtemp_h6a893729__1[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__1[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__1[2U] = 0U; - __Vtemp_h6a893729__1[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hbe955650__0, __Vtemp_h6a893729__1, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v16 - = ((__Vtemp_hbe955650__0[1U] | (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [2U] - >> 0x20U))) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v16 = 0x1d0U; - __Vtemp_h6a893729__2[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__2[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__2[2U] = 0U; - __Vtemp_h6a893729__2[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hd715d68e__0, __Vtemp_h6a893729__2, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v17 - = (0xffU & ((__Vtemp_hd715d68e__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [2U] >> 0x20U))) - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v17 = 0x190U; - __Vtemp_h6a893729__3[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__3[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__3[2U] = 0U; - __Vtemp_h6a893729__3[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_he7ccc2a9__0, __Vtemp_h6a893729__3, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v18 - = (0xffU & ((__Vtemp_he7ccc2a9__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [2U] >> 0x20U))) - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v18 = 0x150U; - __Vtemp_h6a893729__4[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__4[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__4[2U] = 0U; - __Vtemp_h6a893729__4[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hd91b7ec4__0, __Vtemp_h6a893729__4, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v19 - = (0xffU & (__Vtemp_hd91b7ec4__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [2U] >> 0x20U)))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v19 = 0x110U; - __Vtemp_h6a893729__5[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__5[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__5[2U] = 0U; - __Vtemp_h6a893729__5[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h12a1e2c7__0, __Vtemp_h6a893729__5, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v20 - = ((__Vtemp_h12a1e2c7__0[0U] | (IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [2U])) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v20 = 0xd0U; - __Vtemp_h6a893729__6[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__6[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__6[2U] = 0U; - __Vtemp_h6a893729__6[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h954d868e__0, __Vtemp_h6a893729__6, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v21 - = (0xffU & ((__Vtemp_h954d868e__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [2U])) >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v21 = 0x90U; - __Vtemp_h6a893729__7[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__7[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__7[2U] = 0U; - __Vtemp_h6a893729__7[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_heada342b__0, __Vtemp_h6a893729__7, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v22 - = (0xffU & ((__Vtemp_heada342b__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [2U])) >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v22 = 0x50U; - __Vtemp_h6a893729__8[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U))))))))); - __Vtemp_h6a893729__8[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_h6a893729__8[2U] = 0U; - __Vtemp_h6a893729__8[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hdeff39bc__0, __Vtemp_h6a893729__8, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v23 - = (0xffU & (__Vtemp_hdeff39bc__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [2U]))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v23 = 0x10U; - __Vtemp_hba64b852__0[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__0[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__0[2U] = 0U; - __Vtemp_hba64b852__0[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h7122da19__0, __Vtemp_hba64b852__0, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v3 - = (((QData)((IData)(__Vtemp_h7122da19__0[3U])) - << 0x20U) | (QData)((IData)(__Vtemp_h7122da19__0[2U]))); - __Vtemp_hba64b852__1[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__1[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__1[2U] = 0U; - __Vtemp_hba64b852__1[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h47724555__0, __Vtemp_hba64b852__1, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v24 - = ((__Vtemp_h47724555__0[1U] | (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [3U] - >> 0x20U))) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v24 = 0x1d8U; - __Vtemp_hba64b852__2[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__2[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__2[2U] = 0U; - __Vtemp_hba64b852__2[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h599a9ad2__0, __Vtemp_hba64b852__2, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v25 - = (0xffU & ((__Vtemp_h599a9ad2__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [3U] >> 0x20U))) - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v25 = 0x198U; - __Vtemp_hba64b852__3[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__3[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__3[2U] = 0U; - __Vtemp_hba64b852__3[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hea93f5fb__0, __Vtemp_hba64b852__3, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v26 - = (0xffU & ((__Vtemp_hea93f5fb__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [3U] >> 0x20U))) - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v26 = 0x158U; - __Vtemp_hba64b852__4[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__4[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__4[2U] = 0U; - __Vtemp_hba64b852__4[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h7b54af8a__0, __Vtemp_hba64b852__4, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v27 - = (0xffU & (__Vtemp_h7b54af8a__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [3U] >> 0x20U)))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v27 = 0x118U; - __Vtemp_hba64b852__5[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__5[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__5[2U] = 0U; - __Vtemp_hba64b852__5[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h62675ac5__0, __Vtemp_hba64b852__5, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v28 - = ((__Vtemp_h62675ac5__0[0U] | (IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [3U])) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v28 = 0xd8U; - __Vtemp_hba64b852__6[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__6[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__6[2U] = 0U; - __Vtemp_hba64b852__6[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h6c651d11__0, __Vtemp_hba64b852__6, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v29 - = (0xffU & ((__Vtemp_h6c651d11__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [3U])) >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v29 = 0x98U; - __Vtemp_hba64b852__7[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__7[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__7[2U] = 0U; - __Vtemp_hba64b852__7[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hd800ccf7__0, __Vtemp_hba64b852__7, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v30 - = (0xffU & ((__Vtemp_hd800ccf7__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [3U])) >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v30 = 0x58U; - __Vtemp_hba64b852__8[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U)))))))); - __Vtemp_hba64b852__8[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hba64b852__8[2U] = 0U; - __Vtemp_hba64b852__8[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h1017fee7__0, __Vtemp_hba64b852__8, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v31 - = (0xffU & (__Vtemp_h1017fee7__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [3U]))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v31 = 0x18U; - __Vtemp_he2e8daa2__0[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__0[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__0[2U] = 0U; - __Vtemp_he2e8daa2__0[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h08f78865__0, __Vtemp_he2e8daa2__0, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v4 - = (((QData)((IData)(__Vtemp_h08f78865__0[3U])) - << 0x20U) | (QData)((IData)(__Vtemp_h08f78865__0[2U]))); - __Vtemp_he2e8daa2__1[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__1[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__1[2U] = 0U; - __Vtemp_he2e8daa2__1[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h391791bc__0, __Vtemp_he2e8daa2__1, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v32 - = ((__Vtemp_h391791bc__0[1U] | (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [4U] - >> 0x20U))) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v32 = 0x1e0U; - __Vtemp_he2e8daa2__2[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__2[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__2[2U] = 0U; - __Vtemp_he2e8daa2__2[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h6d0d6a0e__0, __Vtemp_he2e8daa2__2, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v33 - = (0xffU & ((__Vtemp_h6d0d6a0e__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [4U] >> 0x20U))) - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v33 = 0x1a0U; - __Vtemp_he2e8daa2__3[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__3[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__3[2U] = 0U; - __Vtemp_he2e8daa2__3[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h982aa917__0, __Vtemp_he2e8daa2__3, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v34 - = (0xffU & ((__Vtemp_h982aa917__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [4U] >> 0x20U))) - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v34 = 0x160U; - __Vtemp_he2e8daa2__4[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__4[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__4[2U] = 0U; - __Vtemp_he2e8daa2__4[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h25996835__0, __Vtemp_he2e8daa2__4, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v35 - = (0xffU & (__Vtemp_h25996835__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [4U] >> 0x20U)))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v35 = 0x120U; - __Vtemp_he2e8daa2__5[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__5[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__5[2U] = 0U; - __Vtemp_he2e8daa2__5[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hcaeb2968__0, __Vtemp_he2e8daa2__5, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v36 - = ((__Vtemp_hcaeb2968__0[0U] | (IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [4U])) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v36 = 0xe0U; - __Vtemp_he2e8daa2__6[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__6[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__6[2U] = 0U; - __Vtemp_he2e8daa2__6[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_he03d2212__0, __Vtemp_he2e8daa2__6, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v37 - = (0xffU & ((__Vtemp_he03d2212__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [4U])) >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v37 = 0xa0U; - __Vtemp_he2e8daa2__7[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__7[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__7[2U] = 0U; - __Vtemp_he2e8daa2__7[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_ha903253e__0, __Vtemp_he2e8daa2__7, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v38 - = (0xffU & ((__Vtemp_ha903253e__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [4U])) >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v38 = 0x60U; - __Vtemp_he2e8daa2__8[0U] = (IData)((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U])))))))); - __Vtemp_he2e8daa2__8[1U] = (IData)(((((QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U])))))) - << 0x20U) - | (QData)((IData)( - ((vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x18U) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 0x10U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - << 8U)) - | (0xffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U]))))))) - >> 0x20U)); - __Vtemp_he2e8daa2__8[2U] = 0U; - __Vtemp_he2e8daa2__8[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hf7137b89__0, __Vtemp_he2e8daa2__8, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v39 - = (0xffU & (__Vtemp_hf7137b89__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [4U]))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v39 = 0x20U; - __Vtemp_h34e42f15__0[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__0[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__0[2U] = 0U; - __Vtemp_h34e42f15__0[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h07f1bed2__0, __Vtemp_h34e42f15__0, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v5 - = (((QData)((IData)(__Vtemp_h07f1bed2__0[3U])) - << 0x20U) | (QData)((IData)(__Vtemp_h07f1bed2__0[2U]))); - __Vtemp_h34e42f15__1[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__1[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__1[2U] = 0U; - __Vtemp_h34e42f15__1[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h70d21314__0, __Vtemp_h34e42f15__1, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v40 - = ((__Vtemp_h70d21314__0[1U] | (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [5U] - >> 0x20U))) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v40 = 0x1e8U; - __Vtemp_h34e42f15__2[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__2[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__2[2U] = 0U; - __Vtemp_h34e42f15__2[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h48fbca01__0, __Vtemp_h34e42f15__2, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v41 - = (0xffU & ((__Vtemp_h48fbca01__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [5U] >> 0x20U))) - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v41 = 0x1a8U; - __Vtemp_h34e42f15__3[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__3[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__3[2U] = 0U; - __Vtemp_h34e42f15__3[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hafd87b31__0, __Vtemp_h34e42f15__3, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v42 - = (0xffU & ((__Vtemp_hafd87b31__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [5U] >> 0x20U))) - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v42 = 0x168U; - __Vtemp_h34e42f15__4[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__4[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__4[2U] = 0U; - __Vtemp_h34e42f15__4[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h6a57d92f__0, __Vtemp_h34e42f15__4, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v43 - = (0xffU & (__Vtemp_h6a57d92f__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [5U] >> 0x20U)))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v43 = 0x128U; - __Vtemp_h34e42f15__5[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__5[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__5[2U] = 0U; - __Vtemp_h34e42f15__5[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hfb2b9050__0, __Vtemp_h34e42f15__5, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v44 - = ((__Vtemp_hfb2b9050__0[0U] | (IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [5U])) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v44 = 0xe8U; - __Vtemp_h34e42f15__6[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__6[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__6[2U] = 0U; - __Vtemp_h34e42f15__6[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hb39b32d8__0, __Vtemp_h34e42f15__6, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v45 - = (0xffU & ((__Vtemp_hb39b32d8__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [5U])) >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v45 = 0xa8U; - __Vtemp_h34e42f15__7[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__7[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__7[2U] = 0U; - __Vtemp_h34e42f15__7[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hb7f94261__0, __Vtemp_h34e42f15__7, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v46 - = (0xffU & ((__Vtemp_hb7f94261__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [5U])) >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v46 = 0x68U; - __Vtemp_h34e42f15__8[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U))))))))); - __Vtemp_h34e42f15__8[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 8U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 0x10U)) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - << 8U)) - | ((0xff00U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U]) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 8U)))))))) - >> 0x20U)); - __Vtemp_h34e42f15__8[2U] = 0U; - __Vtemp_h34e42f15__8[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hcb8462bd__0, __Vtemp_h34e42f15__8, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v47 - = (0xffU & (__Vtemp_hcb8462bd__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [5U]))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v47 = 0x28U; - __Vtemp_hb4162778__0[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__0[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__0[2U] = 0U; - __Vtemp_hb4162778__0[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h74f3730a__0, __Vtemp_hb4162778__0, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v6 - = (((QData)((IData)(__Vtemp_h74f3730a__0[3U])) - << 0x20U) | (QData)((IData)(__Vtemp_h74f3730a__0[2U]))); - __Vtemp_hb4162778__1[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__1[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__1[2U] = 0U; - __Vtemp_hb4162778__1[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hd0420400__0, __Vtemp_hb4162778__1, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v48 - = ((__Vtemp_hd0420400__0[1U] | (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [6U] - >> 0x20U))) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v48 = 0x1f0U; - __Vtemp_hb4162778__2[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__2[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__2[2U] = 0U; - __Vtemp_hb4162778__2[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hf73f2575__0, __Vtemp_hb4162778__2, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v49 - = (0xffU & ((__Vtemp_hf73f2575__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [6U] >> 0x20U))) - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v49 = 0x1b0U; - __Vtemp_hb4162778__3[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__3[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__3[2U] = 0U; - __Vtemp_hb4162778__3[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hf46f2807__0, __Vtemp_hb4162778__3, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v50 - = (0xffU & ((__Vtemp_hf46f2807__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [6U] >> 0x20U))) - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v50 = 0x170U; - __Vtemp_hb4162778__4[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__4[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__4[2U] = 0U; - __Vtemp_hb4162778__4[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hb944d609__0, __Vtemp_hb4162778__4, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v51 - = (0xffU & (__Vtemp_hb944d609__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [6U] >> 0x20U)))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v51 = 0x130U; - __Vtemp_hb4162778__5[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__5[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__5[2U] = 0U; - __Vtemp_hb4162778__5[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h5da5ade5__0, __Vtemp_hb4162778__5, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v52 - = ((__Vtemp_h5da5ade5__0[0U] | (IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [6U])) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v52 = 0xf0U; - __Vtemp_hb4162778__6[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__6[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__6[2U] = 0U; - __Vtemp_hb4162778__6[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hbecfd129__0, __Vtemp_hb4162778__6, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v53 - = (0xffU & ((__Vtemp_hbecfd129__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [6U])) >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v53 = 0xb0U; - __Vtemp_hb4162778__7[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__7[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__7[2U] = 0U; - __Vtemp_hb4162778__7[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_hc04d56a4__0, __Vtemp_hb4162778__7, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v54 - = (0xffU & ((__Vtemp_hc04d56a4__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [6U])) >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v54 = 0x70U; - __Vtemp_hb4162778__8[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U))))))))); - __Vtemp_hb4162778__8[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x10U))))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - << 8U)) - | ((0xff0000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U]) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 8U)) - | (0xffU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x10U)))))))) - >> 0x20U)); - __Vtemp_hb4162778__8[2U] = 0U; - __Vtemp_hb4162778__8[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h1129842a__0, __Vtemp_hb4162778__8, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v55 - = (0xffU & (__Vtemp_h1129842a__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [6U]))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v55 = 0x30U; - __Vtemp_hc7bc04b3__0[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__0[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__0[2U] = 0U; - __Vtemp_hc7bc04b3__0[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h5bc1289b__0, __Vtemp_hc7bc04b3__0, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v7 - = (((QData)((IData)(__Vtemp_h5bc1289b__0[3U])) - << 0x20U) | (QData)((IData)(__Vtemp_h5bc1289b__0[2U]))); - __Vtemp_hc7bc04b3__1[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__1[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__1[2U] = 0U; - __Vtemp_hc7bc04b3__1[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h4dd2798f__0, __Vtemp_hc7bc04b3__1, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v56 - = ((__Vtemp_h4dd2798f__0[1U] | (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [7U] - >> 0x20U))) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v56 = 0x1f8U; - __Vtemp_hc7bc04b3__2[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__2[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__2[2U] = 0U; - __Vtemp_hc7bc04b3__2[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_ha42e639f__0, __Vtemp_hc7bc04b3__2, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v57 - = (0xffU & ((__Vtemp_ha42e639f__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [7U] >> 0x20U))) - >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v57 = 0x1b8U; - __Vtemp_hc7bc04b3__3[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__3[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__3[2U] = 0U; - __Vtemp_hc7bc04b3__3[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_he9327814__0, __Vtemp_hc7bc04b3__3, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v58 - = (0xffU & ((__Vtemp_he9327814__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [7U] >> 0x20U))) - >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v58 = 0x178U; - __Vtemp_hc7bc04b3__4[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__4[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__4[2U] = 0U; - __Vtemp_hc7bc04b3__4[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_he257a0ab__0, __Vtemp_hc7bc04b3__4, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v59 - = (0xffU & (__Vtemp_he257a0ab__0[1U] - | (IData)((vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [7U] >> 0x20U)))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v59 = 0x138U; - __Vtemp_hc7bc04b3__5[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__5[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__5[2U] = 0U; - __Vtemp_hc7bc04b3__5[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h22ea5162__0, __Vtemp_hc7bc04b3__5, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v60 - = ((__Vtemp_h22ea5162__0[0U] | (IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [7U])) - >> 0x18U); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v60 = 0xf8U; - __Vtemp_hc7bc04b3__6[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__6[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__6[2U] = 0U; - __Vtemp_hc7bc04b3__6[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_h426db359__0, __Vtemp_hc7bc04b3__6, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v61 - = (0xffU & ((__Vtemp_h426db359__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [7U])) >> 0x10U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v61 = 0xb8U; - __Vtemp_hc7bc04b3__7[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__7[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__7[2U] = 0U; - __Vtemp_hc7bc04b3__7[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_ha3929202__0, __Vtemp_hc7bc04b3__7, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v62 - = (0xffU & ((__Vtemp_ha3929202__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [7U])) >> 8U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v62 = 0x78U; - __Vtemp_hc7bc04b3__8[0U] = (IData)((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U)))))))); - __Vtemp_hc7bc04b3__8[1U] = (IData)(((((QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - >> 0x18U)))))) - << 0x20U) - | (QData)((IData)( - ((0xff000000U - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U]) - | ((0xff0000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - >> 8U)) - | ((0xff00U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - >> 0x10U)) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - >> 0x18U))))))) - >> 0x20U)); - __Vtemp_hc7bc04b3__8[2U] = 0U; - __Vtemp_hc7bc04b3__8[3U] = 0U; - VL_SHIFTL_WWI(128,128,7, __Vtemp_he29f0e19__0, __Vtemp_hc7bc04b3__8, - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U]); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v63 - = (0xffU & (__Vtemp_he29f0e19__0[0U] - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data - [7U]))); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v63 = 0x38U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][0U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][1U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][2U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][3U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][4U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][5U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][6U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][7U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[8U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][8U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[9U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][9U]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xaU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][0xaU]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xbU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][0xbU]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xcU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][0xcU]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xdU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][0xdU]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xeU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][0xeU]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xfU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U][0xfU]; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v0 - = (0xffU & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - ? (((0x80U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U]) >> 8U)); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v0 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v0 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U]) >> 7U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v0 = 0x38U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v1 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U]) >> 6U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v1 = 0x30U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v2 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U]) >> 5U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v2 = 0x28U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v3 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U]) >> 4U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v3 = 0x20U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v4 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U]) >> 3U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v4 = 0x18U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v5 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U]) >> 2U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v5 = 0x10U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v6 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U]) >> 1U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v6 = 8U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v7 - = (1U & (((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x38U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x30U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x28U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x20U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x18U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x10U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 8U)) - << 1U)) - | (1U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [0U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [0U])); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v7 = 0U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v1 - = (0xffU & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - ? (((0x80U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U]) >> 8U)); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v8 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U]) >> 7U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v8 = 0x39U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v9 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U]) >> 6U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v9 = 0x31U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v10 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U]) >> 5U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v10 = 0x29U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v11 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U]) >> 4U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v11 = 0x21U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v12 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U]) >> 3U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v12 = 0x19U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v13 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U]) >> 2U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v13 = 0x11U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v14 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U]) >> 1U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v14 = 9U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v15 - = (1U & (((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x39U)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x31U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x29U)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x21U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x19U)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x11U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 9U)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 1U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [1U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [1U])); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v15 = 1U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v2 - = (0xffU & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - ? (((0x80U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U]) >> 8U)); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v16 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U]) >> 7U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v16 = 0x3aU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v17 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U]) >> 6U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v17 = 0x32U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v18 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U]) >> 5U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v18 = 0x2aU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v19 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U]) >> 4U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v19 = 0x22U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v20 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U]) >> 3U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v20 = 0x1aU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v21 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U]) >> 2U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v21 = 0x12U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v22 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U]) >> 1U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v22 = 0xaU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v23 - = (1U & (((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3aU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x32U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2aU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x22U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1aU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x12U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xaU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 2U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [2U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [2U])); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v23 = 2U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v3 - = (0xffU & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - ? (((0x80U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U]) >> 8U)); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v24 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U]) >> 7U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v24 = 0x3bU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v25 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U]) >> 6U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v25 = 0x33U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v26 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U]) >> 5U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v26 = 0x2bU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v27 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U]) >> 4U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v27 = 0x23U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v28 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U]) >> 3U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v28 = 0x1bU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v29 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U]) >> 2U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v29 = 0x13U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v30 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U]) >> 1U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v30 = 0xbU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v31 - = (1U & (((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3bU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x33U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2bU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x23U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1bU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x13U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xbU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 3U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [3U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [3U])); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v31 = 3U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v4 - = (0xffU & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - ? (((0x80U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U]) >> 8U)); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v32 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U]) >> 7U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v32 = 0x3cU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v33 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U]) >> 6U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v33 = 0x34U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v34 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U]) >> 5U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v34 = 0x2cU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v35 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U]) >> 4U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v35 = 0x24U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v36 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U]) >> 3U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v36 = 0x1cU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v37 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U]) >> 2U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v37 = 0x14U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v38 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U]) >> 1U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v38 = 0xcU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v39 - = (1U & (((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3cU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x34U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2cU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x24U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1cU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x14U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xcU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 4U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [4U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [4U])); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v39 = 4U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v5 - = (0xffU & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - ? (((0x80U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U]) >> 8U)); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v40 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U]) >> 7U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v40 = 0x3dU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v41 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U]) >> 6U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v41 = 0x35U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v42 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U]) >> 5U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v42 = 0x2dU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v43 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U]) >> 4U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v43 = 0x25U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v44 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U]) >> 3U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v44 = 0x1dU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v45 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U]) >> 2U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v45 = 0x15U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v46 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U]) >> 1U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v46 = 0xdU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v47 - = (1U & (((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3dU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x35U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2dU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x25U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1dU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x15U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xdU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 5U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [5U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [5U])); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v47 = 5U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v6 - = (0xffU & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - ? (((0x80U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U]) >> 8U)); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v48 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U]) >> 7U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v48 = 0x3eU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v49 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U]) >> 6U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v49 = 0x36U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v50 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U]) >> 5U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v50 = 0x2eU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v51 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U]) >> 4U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v51 = 0x26U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v52 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U]) >> 3U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v52 = 0x1eU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v53 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U]) >> 2U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v53 = 0x16U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v54 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U]) >> 1U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v54 = 0xeU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v55 - = (1U & (((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3eU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x36U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2eU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x26U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1eU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x16U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xeU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 6U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [6U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [6U])); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v55 = 6U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v7 - = (0xffU & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - ? (((0x80U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U]) >> 8U)); - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v56 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U]) >> 7U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v56 = 0x3fU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v57 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U]) >> 6U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v57 = 0x37U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v58 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U]) >> 5U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v58 = 0x2fU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v59 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U]) >> 4U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v59 = 0x27U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v60 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U]) >> 3U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v60 = 0x1fU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v61 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U]) >> 2U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v61 = 0x17U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v62 - = (1U & ((((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U]) >> 1U)); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v62 = 0xfU; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v63 - = (1U & (((0xfU >= (0x7fU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] >> 3U))) - ? (0xffffU & (((0x80U & - ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x3fU)) - << 7U)) - | ((0x40U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x37U)) - << 6U)) - | ((0x20U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x2fU)) - << 5U)) - | ((0x10U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x27U)) - << 4U)) - | ((8U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x1fU)) - << 3U)) - | ((4U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0x17U)) - << 2U)) - | ((2U - & ((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 0xfU)) - << 1U)) - | (1U - & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - >> 7U)))))))))) - << (0x7fU - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [7U] - >> 3U)))) - : 0U) | vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm - [7U])); - __Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v63 = 7U; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v64 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt_q - = vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d; - if ((0x14U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt_q = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q = 0U; - } - if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q)) - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__stage2_pending - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_aux; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned - = (~ vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_dm); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_col; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xfU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__stage1_pending = 0U; - } - if ((IData)((((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 2U) & (~ (IData)(vlSelf->main__DOT__wbwide_ddr3_controller_stall))))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__stage1_pending - = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 2U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_aux = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we - = (1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe) - >> 2U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_dm - = (((QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[5U])) - << 0x20U) | (QData)((IData)( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[4U]))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_col - = (0x3c0U & (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 6U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank - = (7U & (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0x10U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row - = (0x3fffU & ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0xdU) | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0x13U))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row - = (0x3fffU & (((IData)(5U) + (( - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0x14U) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0xcU))) - >> 7U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank - = (7U & (((IData)(5U) + ((vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - << 0x14U) - | (vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - >> 0xcU))) - >> 4U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x20U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[1U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x21U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[2U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x22U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[3U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x23U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[4U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x24U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[5U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x25U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[6U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x26U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[7U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x27U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[8U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x28U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[9U] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x29U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xaU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2aU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xbU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2bU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xcU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2cU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xdU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2dU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xeU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2eU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xfU] - = vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2fU]; - } else if ((0xeU != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__stage1_pending - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_stb; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_dm = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_aux - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_col - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[8U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[9U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xaU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xbU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xcU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xdU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xeU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_data[0xfU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xfU]; - } - if (((~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 2U)) & (0xeU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate)))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__stage2_pending = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__stage1_pending = 0U; - } - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__train_delay - = ((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay)) - ? 0U : (3U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay) - - (IData)(1U)))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_read_data - = ((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data)) - ? 0U : (0xfU & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data) - - (IData)(1U)))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback - = ((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback)) - ? 0U : (0x1fU & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback) - - (IData)(1U)))); - vlSelf->o_ddr3_controller_bitslip = 0U; - __Vdly__o_ddr3_controller_odelay_data_ld = 0U; - __Vdly__o_ddr3_controller_odelay_dqs_ld = 0U; - __Vdly__o_ddr3_controller_idelay_data_ld = 0U; - __Vdly__o_ddr3_controller_idelay_dqs_ld = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane_times_8 - = (0x3fU & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)); - __Vdly__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev - = vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_update) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v0 - = ((1U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_ld) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane))) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_cntvaluein) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane]); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v0 = 1U; - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein__v0 - = ((1U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_ld) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane))) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_cntvaluein) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane]); - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein__v0 - = ((1U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_ld) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane))) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_cntvaluein) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane]); - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein__v0 - = ((1U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_ld) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane))) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_cntvaluein) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane]); - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane; - __Vdly__o_ddr3_controller_odelay_data_ld - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_ld; - __Vdly__o_ddr3_controller_odelay_dqs_ld - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_ld; - __Vdly__o_ddr3_controller_idelay_data_ld - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_ld; - __Vdly__o_ddr3_controller_idelay_dqs_ld - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_ld; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane - = vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane; - } else if ((0xeU != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v1 - = (0x1fU & ((1U & ((IData)(vlSelf->o_ddr3_controller_odelay_data_ld) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane))) - ? ((IData)(1U) + vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v1 = 1U; - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__lane; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein__v1 - = (0x1fU & ((1U & ((IData)(vlSelf->o_ddr3_controller_odelay_dqs_ld) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane))) - ? ((IData)(1U) + vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])); - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__lane; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein__v1 - = (0x1fU & ((1U & ((IData)(vlSelf->o_ddr3_controller_idelay_data_ld) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane))) - ? ((IData)(1U) + vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])); - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__lane; - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein__v1 - = (0x1fU & ((1U & ((IData)(vlSelf->o_ddr3_controller_idelay_dqs_ld) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane))) - ? ((IData)(1U) + vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])); - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein__v1 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__lane; - } - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__initial_dqs) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dq_target_index - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value; - } - if ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index - = (0x3fU & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig) - - (IData)(2U))); - } - if (((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]) - & (0x1fU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev)))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__dq_target_index - = (0x3fU & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig) - - (IData)(2U))); - } - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc) - >> 0xbU))) { - if (((((((((0U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr)) - | (1U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) - | (2U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) - | (3U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) - | (4U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) - | (5U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) - | (6U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) - | (7U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr)))) { - if ((0U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein - [(7U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr - >> 4U))]; - } - } else if ((1U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein - [(7U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr - >> 4U))]; - } - } else if ((2U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein - [(7U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr - >> 4U))]; - } - } else if ((3U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein - [(7U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr - >> 4U))]; - } - } else if ((4U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = ((0xffff8000U & vlSelf->main__DOT__wb32_ddr3_phy_idata) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - << 0xbU) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address) - << 6U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate) - << 1U) - | (IData)(vlSelf->i_ddr3_controller_idelayctrl_rdy))))); - } - } else if ((5U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = ((vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [7U] << 0x1cU) | (( - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [6U] - << 0x18U) - | ((vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [5U] - << 0x14U) - | ((vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [4U] - << 0x10U) - | ((vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [3U] - << 0xcU) - | ((vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [2U] - << 8U) - | ((vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [1U] - << 4U) - | vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [0U]))))))); - } - } else if ((6U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store); - } - } else if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = (IData)(vlSelf->i_ddr3_controller_iserdes_bitslip_reference); - } - } else if ((8U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0U]; - } - } else if ((9U == (0xfU & vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[0U]; - } - } else if ((1U & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we)))) { - vlSelf->main__DOT__wb32_ddr3_phy_idata = 0xaaaaaaaaU; - } - } - if (((((((((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate)) - | (1U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - | (2U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - | (3U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - | (4U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - | (5U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - | (6U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - | (7U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate)))) { - if ((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if (((IData)(vlSelf->i_ddr3_controller_idelayctrl_rdy) - & (0xdU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address)))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane = 0U; - __Vdly__o_ddr3_controller_odelay_data_ld = 0xffU; - __Vdly__o_ddr3_controller_odelay_dqs_ld = 0xffU; - __Vdly__o_ddr3_controller_idelay_data_ld = 0xffU; - __Vdly__o_ddr3_controller_idelay_dqs_ld = 0xffU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter = 1U; - } else if ((0xdU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter = 1U; - } - } else if ((1U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if ((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay))) { - if ((0x78U == (0xffU & (IData)( - (vlSelf->i_ddr3_controller_iserdes_bitslip_reference - >> - (0x3fU - & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 2U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__initial_dqs = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored = 0U; - } else { - vlSelf->o_ddr3_controller_bitslip - = ((IData)(vlSelf->o_ddr3_controller_bitslip) - | (0xffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane)))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__train_delay = 3U; - } - } - } else if ((2U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_read_data = 4U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 3U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat = 0U; - } else if ((3U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if ((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat - = (0xfU & ((IData)(1U) + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_store - = (((QData)((IData)((0xffU - & (IData)( - (vlSelf->i_ddr3_controller_iserdes_dqs - >> - (0x3fU - & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))))) - << 0x20U) | (QData)((IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store - >> 8U)))); - if ((4U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 4U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored - = vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index = 0U; - } - } - } else if ((4U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if ((0x154U == ((0x27U >= (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index)) - ? (0x3ffU & (IData)( - (vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index)))) - : 0U))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat - = (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index) - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored)) - ? (1U & ((IData)(1U) + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat))) - : 0U); - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__initial_dqs = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 5U; - } else { - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 2U; - } - } else { - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index - = (0x3fU & ((IData)(1U) + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index))); - } - } else if ((5U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored) - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index))) { - __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v0 - = (0xfU & ((7U & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index) - >> 3U)) + - (5U <= (7U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index))))); - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v0 = 1U; - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__lane; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 6U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement - = (0xffffU & (0x3c3cU >> (7U - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index)))); - } else { - __Vdly__o_ddr3_controller_idelay_data_ld - = ((IData)(__Vdly__o_ddr3_controller_idelay_data_ld) - | (0xffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane)))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 2U; - __Vdly__o_ddr3_controller_idelay_dqs_ld - = ((IData)(__Vdly__o_ddr3_controller_idelay_dqs_ld) - | (0xffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane)))); - } - } else if ((6U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if ((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay))) { - if (((0xffU & (IData)((vlSelf->i_ddr3_controller_iserdes_bitslip_reference - >> (0x3fU - & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))) - == (0xffU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement)))) { - if ((7U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 7U; - } else { - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane - = (7U & ((IData)(1U) - + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 1U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max - = (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - > vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max) - : vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]); - } else { - vlSelf->o_ddr3_controller_bitslip - = ((IData)(vlSelf->o_ddr3_controller_bitslip) - | (0xffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane)))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__train_delay = 3U; - } - } - } else if ((0x11U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback = 0xdU; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter = 1U; - } - } else if ((8U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if ((0U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback - = (1U & (vlSelf->i_ddr3_controller_iserdes_data[ - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8) - >> 5U)] >> (0x1fU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8)))); - if ((1U == (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback) - << 1U) | (1U & (vlSelf->i_ddr3_controller_iserdes_data[ - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8) - >> 5U)] - >> (0x1fU - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8))))))) { - if ((7U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 9U; - } else { - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane - = (7U & ((IData)(1U) + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 7U; - } - } else { - __Vdly__o_ddr3_controller_odelay_data_ld - = ((IData)(__Vdly__o_ddr3_controller_odelay_data_ld) - | (0xffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane)))); - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 7U; - __Vdly__o_ddr3_controller_odelay_dqs_ld - = ((IData)(__Vdly__o_ddr3_controller_odelay_dqs_ld) - | (0xffU & ((IData)(1U) - << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane)))); - } - } - } else if ((9U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if (((0x16U == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address)) - & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q)))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_calib_stb = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0U] = 0xc1c1c1c1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[1U] = 0xc1c1c1c1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[2U] = 0x51515151U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[3U] = 0x51515151U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[4U] = 0xadadadadU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[5U] = 0xadadadadU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[6U] = 0xd0d0d0d0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[7U] = 0xd0d0d0d0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[8U] = 0x8c8c8c8cU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[9U] = 0x8c8c8c8cU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xaU] = 0x29292929U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xbU] = 0x29292929U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xcU] = 0x77777777U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xdU] = 0x77777777U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xeU] = 0x91919191U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xfU] = 0x91919191U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 0xaU; - } - } else if ((0xaU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_calib_stb = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0U] = 0x3d3d3d3dU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[1U] = 0x3d3d3d3dU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[2U] = 0x2c2c2c2cU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[3U] = 0x2c2c2c2cU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[4U] = 0xf1f1f1f1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[5U] = 0xf1f1f1f1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[6U] = 0x75757575U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[7U] = 0x75757575U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[8U] = 0xd2d2d2d2U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[9U] = 0xd2d2d2d2U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xaU] = 0xcfcfcfcfU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xbU] = 0xcfcfcfcfU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xcU] = 0xdbdbdbdbU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xdU] = 0xdbdbdbdbU; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xeU] = 0x80808080U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xfU] = 0x80808080U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 0xbU; - } else if ((0xbU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if ((1U & ((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q)) - & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_stb))))) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_calib_stb = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 0xcU; - } - } else if ((0xcU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if ((1U == vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U])) { - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][1U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][2U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][3U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][4U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][5U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][6U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][7U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[8U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][8U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[9U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][9U]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xaU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xaU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xbU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xbU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xcU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xcU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xdU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xdU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xeU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xeU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xfU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xfU]; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 0xdU; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__data_start_index__v0 = 1U; - __Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__data_start_index__v0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__lane; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[0U] = 0xd0ad51c1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[1U] = 0x9177298cU; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[2U] = 0x75f12c3dU; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[3U] = 0x80dbcfd2U; - } - } else if ((0xdU == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) { - if (((((QData)((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[ - (((IData)(0x3fU) - + vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]) - >> 5U)])) << ((0U - == - (0x1fU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])) - ? 0x20U - : - ((IData)(0x40U) - - - (0x1fU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])))) - | (((0U == (0x1fU & vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])) - ? 0ULL : ((QData)((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[ - (((IData)(0x1fU) - + - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]) - >> 5U)])) - << ((IData)(0x20U) - - (0x1fU & vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])))) - | ((QData)((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[ - (vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane] - >> 5U)])) - >> (0x1fU & vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane])))) - == (((QData)((IData)((((((0U == (0x1fU - & ((IData)(0x1c0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - ? 0U : ( - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (((IData)(7U) - + - (0x1ffU - & ((IData)(0x1c0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - >> 5U)] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x1c0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))))) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (0xfU & - (((IData)(0x1c0U) - + ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)) - >> 5U))] - >> (0x1fU - & ((IData)(0x1c0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))) - << 0x18U) | - ((0xff0000U - & ((((0U == - (0x1fU - & ((IData)(0x180U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - ? 0U - : (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (((IData)(7U) - + - (0x1ffU - & ((IData)(0x180U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - >> 5U)] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x180U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))))) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (0xfU - & (((IData)(0x180U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x180U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))) - << 0x10U)) - | ((0xff00U - & ((((0U - == - (0x1fU - & ((IData)(0x140U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - ? 0U - : - (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (((IData)(7U) - + - (0x1ffU - & ((IData)(0x140U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - >> 5U)] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x140U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))))) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (0xfU - & (((IData)(0x140U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x140U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))) - << 8U)) - | (0xffU - & (((0U - == - (0x1fU - & ((IData)(0x100U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - ? 0U - : - (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (((IData)(7U) - + - (0x1ffU - & ((IData)(0x100U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - >> 5U)] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x100U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))))) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (0xfU - & (((IData)(0x100U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x100U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))))))))) - << 0x20U) | (QData)((IData)(( - ((((0U - == - (0x1fU - & ((IData)(0xc0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - ? 0U - : - (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (((IData)(7U) - + - (0x1ffU - & ((IData)(0xc0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - >> 5U)] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0xc0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))))) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (0xfU - & (((IData)(0xc0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)) - >> 5U))] - >> - (0x1fU - & ((IData)(0xc0U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))) - << 0x18U) - | ((0xff0000U - & ((((0U - == - (0x1fU - & ((IData)(0x80U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - ? 0U - : - (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (((IData)(7U) - + - (0x1ffU - & ((IData)(0x80U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - >> 5U)] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x80U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))))) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (0xfU - & (((IData)(0x80U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x80U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))) - << 0x10U)) - | ((0xff00U - & ((((0U - == - (0x1fU - & ((IData)(0x40U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - ? 0U - : - (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (((IData)(7U) - + - (0x1ffU - & ((IData)(0x40U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))) - >> 5U)] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x40U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)))))) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (0xfU - & (((IData)(0x40U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x40U) - + - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))))) - << 8U)) - | (0xffU - & (((0U - == - (0x1fU - & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - << 3U))) - ? 0U - : - (vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[ - (((IData)(7U) - + - (0x1ffU - & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__lane) - 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vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data_unaligned[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm_unaligned = 0ULL; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_store = 0ULL; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index = 0U; - __Vdly__o_ddr3_controller_odelay_data_ld = 0U; - __Vdly__o_ddr3_controller_odelay_dqs_ld = 0U; - __Vdly__o_ddr3_controller_idelay_data_ld = 0U; - __Vdly__o_ddr3_controller_idelay_dqs_ld = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_calib_stb = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dq_target_index = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v2 = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__train_delay = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig = 0U; - vlSelf->o_ddr3_controller_bitslip = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane_times_8 = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__initial_dqs = 1U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__lane = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_aux = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_we = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_col = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_data[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__pause_counter = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[1U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[2U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[3U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[4U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[5U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[6U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[7U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[8U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[9U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xaU] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xbU] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xcU] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xdU] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xeU] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xfU] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[0U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[1U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[2U] = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe_max = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback = 0U; - __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_read_data = 0U; - __Vdlyvset__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v1 = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q = 1U; - vlSelf->main__DOT__wbwide_ddr3_controller_stall = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_write_lane = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_update = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_ld = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_data_cntvaluein = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_ld = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_odelay_dqs_cntvaluein = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_ld = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_data_cntvaluein = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_ld = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_phy_idelay_dqs_cntvaluein = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_sel = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_addr = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_data = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_we = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__wb2_stb = 0U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_q - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_q; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_val - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs_val; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dqs; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_dq; - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v2; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v3; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v4; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v5; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v6; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v7; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q__v8) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q[7U] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v2; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v3; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v4; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v5; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v6; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v7; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q__v8) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q[7U] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v2; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v3; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v4; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v5; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v6; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v7; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q__v8) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q[7U] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v2; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v3; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v4; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v5; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v6; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v7; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__bank_active_row_q__v8) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q[7U] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v2; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v3; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v4; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v5; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v6; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v7; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q__v8) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q[7U] = 0U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__index_read_pipe - = __Vdly__main__DOT__ddr3_controller_inst__DOT__index_read_pipe; - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v0; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v1) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v1; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v2) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v2; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v3) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v3; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v4) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v4; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v5) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[4U] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q__v10) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q[4U] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v0; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v1) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v0; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v2) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v2] - = (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe - [__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v2] - | (0xffffU & ((IData)(1U) << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v2)))); - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter - = __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_counter; - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v2; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v3; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v4; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v5; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v6; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_data__v7; - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v0), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v0); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v1), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v1); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v2), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v2); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v3), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v3); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v4), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v4); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v5), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v5); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v6), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v6); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v7), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v7); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v8), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v8); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v9), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v9); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v10), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v10); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v11), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v11); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v12), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v12); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v13), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v13); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v14), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v14); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v15), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v15); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v16), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v16); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v17), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v17); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v18), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v18); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v19), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v19); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v20), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v20); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v21), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v21); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v22), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v22); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v23), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v23); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v24), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v24); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v25), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v25); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v26), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v26); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v27), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v27); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v28), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v28); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v29), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v29); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v30), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v30); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v31), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v31); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v32), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v32); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v33), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v33); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v34), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v34); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v35), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v35); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v36), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v36); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v37), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v37); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v38), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v38); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v39), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v39); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v40), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v40); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v41), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v41); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v42), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v42); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v43), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v43); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v44), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v44); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v45), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v45); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v46), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v46); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v47), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v47); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v48), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v48); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v49), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v49); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v50), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v50); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v51), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v51); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v52), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v52); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v53), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v53); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v54), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v54); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v55), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v55); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v56), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v56); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v57), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v57); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v58), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v58); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v59), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v59); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v60), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v60); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v61), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v61); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v62), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v62); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_data__v63), - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v63); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][8U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][9U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xaU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xbU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xcU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xdU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xeU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xfU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_data__v64[0xfU]; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__stage2_data__v65) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[0U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[1U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[2U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[3U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[4U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[5U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[6U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_data[7U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[0U][0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data[1U][0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[0U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v2; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v3; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v4; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v5; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v6; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__unaligned_dm__v7; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v0))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v0)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v0))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v1))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v1)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v1))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v2))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v2)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v2))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v3))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v3)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v3))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v4))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v4)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v4))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v5))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v5)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v5))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v6))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v6)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v6))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v7))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v7)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v7))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v8))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v8)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v8))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v9))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v9)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v9))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v10))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v10)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v10))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v11))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v11)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v11))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v12))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v12)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v12))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v13))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v13)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v13))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v14))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v14)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v14))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v15))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v15)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v15))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v16))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v16)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v16))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v17))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v17)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v17))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v18))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v18)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v18))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v19))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v19)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v19))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v20))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v20)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v20))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v21))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v21)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v21))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v22))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v22)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v22))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v23))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v23)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v23))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v24))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v24)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v24))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v25))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v25)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v25))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v26))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v26)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v26))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v27))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v27)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v27))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v28))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v28)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v28))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v29))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v29)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v29))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v30))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v30)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v30))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v31))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v31)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v31))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v32))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v32)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v32))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v33))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v33)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v33))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v34))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v34)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v34))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v35))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v35)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v35))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v36))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v36)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v36))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v37))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v37)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v37))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v38))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v38)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v38))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v39))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v39)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v39))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v40))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v40)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v40))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v41))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v41)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v41))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v42))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v42)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v42))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v43))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v43)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v43))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v44))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v44)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v44))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v45))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v45)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v45))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v46))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v46)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v46))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v47))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v47)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v47))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v48))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v48)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v48))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v49))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v49)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v49))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v50))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v50)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v50))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v51))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v51)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v51))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v52))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v52)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v52))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v53))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v53)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v53))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v54))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v54)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v54))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v55))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v55)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v55))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v56))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v56)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v56))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v57))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v57)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v57))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v58))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v58)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v58))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v59))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v59)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v59))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v60))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v60)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v60))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v61))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v61)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v61))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v62))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v62)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v62))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] - = (((~ (1ULL << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v63))) - & vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [0U]) | ((QData)((IData)(__Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v63)) - << (IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v63))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v64; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__stage2_dm__v65) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__unaligned_dm[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[0U] = 0ULL; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm[1U] = 0ULL; - } - vlSelf->o_ddr3_controller_toggle_dqs = (1U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_val)); - vlSelf->o_ddr3_controller_dqs_tri_control = (1U - & (~ - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs) - >> 2U))); - vlSelf->o_ddr3_controller_dq_tri_control = (1U - & (~ - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq) - >> 3U))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_q - = ((IData)(vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n) - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d)); - vlSelf->o_ddr3_controller_data[0U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0U]; - vlSelf->o_ddr3_controller_data[1U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][1U]; - vlSelf->o_ddr3_controller_data[2U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][2U]; - vlSelf->o_ddr3_controller_data[3U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][3U]; - vlSelf->o_ddr3_controller_data[4U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][4U]; - vlSelf->o_ddr3_controller_data[5U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][5U]; - vlSelf->o_ddr3_controller_data[6U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][6U]; - vlSelf->o_ddr3_controller_data[7U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][7U]; - vlSelf->o_ddr3_controller_data[8U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][8U]; - vlSelf->o_ddr3_controller_data[9U] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][9U]; - vlSelf->o_ddr3_controller_data[0xaU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xaU]; - vlSelf->o_ddr3_controller_data[0xbU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xbU]; - vlSelf->o_ddr3_controller_data[0xcU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xcU]; - vlSelf->o_ddr3_controller_data[0xdU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xdU]; - vlSelf->o_ddr3_controller_data[0xeU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xeU]; - vlSelf->o_ddr3_controller_data[0xfU] = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_data - [1U][0xfU]; - vlSelf->o_ddr3_controller_dm = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_dm - [1U]; - vlSelf->main__DOT__wb32_xbar__DOT__s_data[0xbU] - = vlSelf->main__DOT__wb32_ddr3_phy_idata; - vlSelf->main__DOT__ddr3_controller_inst__DOT__train_delay - = __Vdly__main__DOT__ddr3_controller_inst__DOT__train_delay; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_data - = __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_read_data; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback - = __Vdly__main__DOT__ddr3_controller_inst__DOT__delay_before_write_level_feedback; - vlSelf->o_ddr3_controller_odelay_data_ld = __Vdly__o_ddr3_controller_odelay_data_ld; - vlSelf->o_ddr3_controller_odelay_dqs_ld = __Vdly__o_ddr3_controller_odelay_dqs_ld; - vlSelf->o_ddr3_controller_idelay_data_ld = __Vdly__o_ddr3_controller_idelay_data_ld; - vlSelf->o_ddr3_controller_idelay_dqs_ld = __Vdly__o_ddr3_controller_idelay_dqs_ld; - vlSelf->main__DOT__ddr3_controller_inst__DOT__lane_times_8 - = __Vdly__main__DOT__ddr3_controller_inst__DOT__lane_times_8; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev - = __Vdly__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein_prev; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dq_target_index - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dq_target_index; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_target_index_orig; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_repeat; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_count_repeat; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_store - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_store; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_bitslip_arrangement; - vlSelf->main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback - = __Vdly__main__DOT__ddr3_controller_inst__DOT__prev_write_level_feedback; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_stb - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_calib_stb; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[0U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[1U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[2U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_pattern[3U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__write_pattern[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[1U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[2U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[3U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[4U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[5U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[6U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[7U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[8U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[9U] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xaU] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xbU] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xcU] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xdU] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xeU] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__read_data_store[0xfU] - = __Vdly__main__DOT__ddr3_controller_inst__DOT__read_data_store[0xfU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored - = __Vdly__main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored; - vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction_address - = __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction_address; - vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data - = __Vdly__main__DOT__ddr3_controller_inst__DOT__index_wb_data; - vlSelf->main__DOT__ddr3_controller_inst__DOT__lane - = __Vdly__main__DOT__ddr3_controller_inst__DOT__lane; - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v1) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[1U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v1; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v2) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[2U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v2; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v3) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[3U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v3; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v4) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[4U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v4; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v5) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[5U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v5; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v6) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[6U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v6; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v7) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[7U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v7; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v8) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[8U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v8; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v9) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[9U] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v9; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v10) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xaU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v10; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v11) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xbU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v11; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v12) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xcU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v12; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v13) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xdU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v13; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v14) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xeU] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v14; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v15) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v16] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v16; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q__v17) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xfU] = 0U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending - = __Vdly__main__DOT__ddr3_controller_inst__DOT__stage1_pending; - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v0] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v0; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__data_start_index__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__data_start_index__v0] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__data_start_index__v1) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__data_start_index__v1] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__data_start_index__v2) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__data_start_index__v2] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__data_start_index__v2; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v0) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein__v0] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein__v0] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein__v0] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein__v0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v0] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v0; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v1) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein__v1] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein__v1] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein__v1] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein__v1; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[__Vdlyvdim0__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v1] - = __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v1; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein__v2) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[0U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[0U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[0U] = 0U; - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__added_read_pipe__v1) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__added_read_pipe[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__data_start_index[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[1U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[2U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[3U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[4U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[5U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[6U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein[7U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[1U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[2U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[3U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[4U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[5U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[6U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein[7U] = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein[7U] = 0U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending - = __Vdly__main__DOT__ddr3_controller_inst__DOT__stage2_pending; - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v0) { - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v0), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v0); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v1), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v1); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v2), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v2); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v3), - 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[1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v111); - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v112) { - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v112), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v112); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v113), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v113); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v114), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v114); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v115), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v115); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v116), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v116); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v117), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v117); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v118), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v118); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v119), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [0U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v119); - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v120) { - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v120), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v120); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v121), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v121); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v122), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v122); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v123), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v123); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v124), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v124); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v125), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v125); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v126), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v126); - VL_ASSIGNSEL_WI(512,8,(IData)(__Vdlyvlsb__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v127), - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [1U], __Vdlyvval__main__DOT__ddr3_controller_inst__DOT__o_wb_data_q__v127); - } - if (__Vdlyvset__main__DOT__ddr3_controller_inst__DOT__delay_read_pipe__v3) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_read_pipe[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[1U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[2U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[3U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[4U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[5U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[6U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[7U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[8U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[9U] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xaU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xbU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xcU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xdU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xeU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q[0xfU] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[0U][0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q[1U][0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_target_index_value - = (0x3fU & ((1U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored)) - ? ((IData)(2U) + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored)) - : ((IData)(1U) + (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__dqs_start_index_stored)))); - vlSelf->o_ddr3_controller_idelay_dqs_cntvaluein - = vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - vlSelf->o_ddr3_controller_idelay_data_cntvaluein - = vlSelf->main__DOT__ddr3_controller_inst__DOT__idelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - vlSelf->o_ddr3_controller_odelay_dqs_cntvaluein - = vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_dqs_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - vlSelf->o_ddr3_controller_odelay_data_cntvaluein - = vlSelf->main__DOT__ddr3_controller_inst__DOT__odelay_data_cntvaluein - [vlSelf->main__DOT__ddr3_controller_inst__DOT__lane]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dq; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d - = vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_dqs; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 5U; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[0U] - = main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[1U] - = main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[2U] - = main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0 - = vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_q - [4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[3U] - = main__DOT__ddr3_controller_inst__DOT____Vlvbound_h60cbe704__0; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4U] = 0U; - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 0U; - if ((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row)))) { - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dq_d = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__write_dqs_d = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__index = 8U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4U] - = (1U | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux) - << 1U)); - } else if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we)) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_update = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__shift_reg_read_pipe_d[4U] - = (1U | ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_aux) - << 1U)); - } - } - } - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][1U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][8U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][9U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xaU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xbU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xcU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xdU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xeU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__s_data[2U][0xfU] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_data_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__index_wb_data][0xfU]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__reset_done - = __Vdly__main__DOT__ddr3_controller_inst__DOT__reset_done; - vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - = __Vdly__main__DOT__ddr3_controller_inst__DOT__instruction; - vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate - = __Vdly__main__DOT__ddr3_controller_inst__DOT__state_calibrate; - vlSelf->main__DOT__wb32_ddr3_phy_stall = (1U & - (~ (IData)(vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n))); -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__5.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__5.cpp deleted file mode 100644 index 3f0579c..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h3334316c__5.cpp +++ /dev/null @@ -1,4443 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__6(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__6\n"); ); - // Body - vlSelf->main__DOT__wb32_xbar__DOT__iM = 0xdU; - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 0U; - if ((2U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (1U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (2U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((8U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (3U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x10U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (4U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x20U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (5U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x40U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (6U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x80U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (7U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x100U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (8U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x200U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (9U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x400U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (0xaU | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x800U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (0xbU | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0x1000U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (0xcU | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0U == (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - } -} - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__7(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__7\n"); ); - // Body - vlSelf->main__DOT__wbu_xbar__DOT__iM = 3U; - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 0U; - if ((2U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (1U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (2U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((0U == (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - } -} - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__8(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__8\n"); ); - // Body - vlSelf->main__DOT__wbwide_xbar__DOT__iM = 4U; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 0U; - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 3U; - } - if ((0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - } -} - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__9(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__9\n"); ); - // Body - vlSelf->main__DOT__wbwide_xbar__DOT__iM = 4U; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 0U; - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 3U; - } - if ((0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - } -} - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__10(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__10\n"); ); - // Body - vlSelf->main__DOT__wbwide_xbar__DOT__iM = 4U; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 0U; - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 3U; - } - if ((0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - } -} - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__11(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__11\n"); ); - // Body - vlSelf->main__DOT__wbwide_xbar__DOT__iM = 4U; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 0U; - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex)); - } - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex = 3U; - } - if ((0U == (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - } -} - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__12(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__12\n"); ); - // Body - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__3__KET____DOT__u_dat_ddr__DOT__w_in; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__2__KET____DOT__u_dat_ddr__DOT__w_in; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__1__KET____DOT__u_dat_ddr__DOT__w_in; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__DRIVE_DDR_IO__BRA__0__KET____DOT__u_dat_ddr__DOT__w_in; - vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__GEN_BIDIRECTIONAL__DOT__r_n - = vlSelf->main__DOT__u_sdcard__DOT__u_sdfrontend__DOT__GEN_IODDR_IO__DOT__u_cmd_ddr__DOT__w_in; -} - -extern const VlWide<16>/*511:0*/ Vmain__ConstPool__CONST_h93e1b771_0; - -VL_INLINE_OPT void Vmain___024root___nba_sequent__TOP__13(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_sequent__TOP__13\n"); ); - // Init - CData/*0:0*/ main__DOT__wb32_xbar__DOT____VdfgTmp_h4f7f05b5__0; - main__DOT__wb32_xbar__DOT____VdfgTmp_h4f7f05b5__0 = 0; - CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0; - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 = 0; - CData/*0:0*/ main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0; - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h97024913__0 = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb = 0; - IData/*31:0*/ __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt = 0; - CData/*3:0*/ __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout; - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout = 0; - QData/*63:0*/ __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel; - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel = 0; - // Body - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb - = vlSelf->__Vdly__main__DOT____Vcellout__wb32_xbar__o_sstb; - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - if ((1U & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbu_xbar__DOT__requested - [0U])))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbu_xbar__DOT__request - [0U]))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (6U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbu_xbar__DOT__requested - [0U] >> 1U))))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] >> 1U)))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (5U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((4U & vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] >> 2U)))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (3U & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if (((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbu_xbar__DOT__mempty)))) { - vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - } - if ((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall)))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe - = ((6U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)) - | (1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_we) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]))); - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_we) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[4U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[5U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[6U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[7U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[8U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[9U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]][0xfU]; - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - = ((0xffc00000U & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U]) - | vlSelf->main__DOT__wbwide_xbar__DOT__m_addr - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]]); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[0U] - = (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]]); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U] - = (IData)((vlSelf->main__DOT__wbwide_xbar__DOT__m_sel - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]] >> 0x20U)); - } - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe - = (6U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[1U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[2U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[3U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[4U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[5U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[6U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[7U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[8U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[9U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xaU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xbU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xcU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xdU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xeU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0xfU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - = (0xffc00000U & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U]); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[0U] = 0U; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U] = 0U; - } - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> 1U)))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe - = ((5U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)) - | (2U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_we) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]) << 1U))); - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_we) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x10U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x11U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x12U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x13U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x14U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x15U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x16U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x17U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x18U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x19U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1aU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1bU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1cU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1dU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1eU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1fU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]][0xfU]; - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x10U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x11U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x12U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x13U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x14U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x15U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x16U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x17U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x18U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x19U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1aU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1bU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1cU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1dU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1eU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1fU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - = ((0x3fffffU & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U]) - | (vlSelf->main__DOT__wbwide_xbar__DOT__m_addr - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]] << 0x16U)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - = ((0xfffff000U & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U]) - | (vlSelf->main__DOT__wbwide_xbar__DOT__m_addr - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]] >> 0xaU)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[2U] - = (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]]); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[3U] - = (IData)((vlSelf->main__DOT__wbwide_xbar__DOT__m_sel - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]] >> 0x20U)); - } - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe - = (5U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x10U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x11U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x12U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x13U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x14U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x15U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x16U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x17U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x18U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x19U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1aU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1bU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1cU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1dU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1eU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x1fU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U] - = (0x3fffffU & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[0U]); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - = (0xfffff000U & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U]); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[2U] = 0U; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[3U] = 0U; - } - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> 2U)))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe - = ((3U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)) - | (4U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_we) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]) << 2U))); - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_we) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]))) { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x20U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x21U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x22U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x23U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x24U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x25U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x26U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x27U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x28U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x29U] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2aU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2bU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2cU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2dU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2eU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2fU] - = vlSelf->main__DOT__wbwide_xbar__DOT__m_data - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]][0xfU]; - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x20U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x21U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x22U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x23U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x24U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x25U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x26U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x27U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x28U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x29U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2aU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2bU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2cU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2dU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2eU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2fU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - } - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - = ((0xfffU & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U]) - | (vlSelf->main__DOT__wbwide_xbar__DOT__m_addr - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]] << 0xcU)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] - = (3U & (vlSelf->main__DOT__wbwide_xbar__DOT__m_addr - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]] >> 0x14U)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[4U] - = (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_sel - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]]); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[5U] - = (IData)((vlSelf->main__DOT__wbwide_xbar__DOT__m_sel - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]] >> 0x20U)); - } - } else { - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe - = (3U & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_swe)); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x20U] - = Vmain__ConstPool__CONST_h93e1b771_0[0U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x21U] - = Vmain__ConstPool__CONST_h93e1b771_0[1U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x22U] - = Vmain__ConstPool__CONST_h93e1b771_0[2U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x23U] - = Vmain__ConstPool__CONST_h93e1b771_0[3U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x24U] - = Vmain__ConstPool__CONST_h93e1b771_0[4U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x25U] - = Vmain__ConstPool__CONST_h93e1b771_0[5U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x26U] - = Vmain__ConstPool__CONST_h93e1b771_0[6U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x27U] - = Vmain__ConstPool__CONST_h93e1b771_0[7U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x28U] - = Vmain__ConstPool__CONST_h93e1b771_0[8U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x29U] - = Vmain__ConstPool__CONST_h93e1b771_0[9U]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2aU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xaU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2bU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xbU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2cU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xcU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2dU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xdU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2eU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xeU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sdata[0x2fU] - = Vmain__ConstPool__CONST_h93e1b771_0[0xfU]; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U] - = (0xfffU & vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[1U]); - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_saddr[2U] = 0U; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[4U] = 0U; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[5U] = 0U; - } - if ((1U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xfffffffffff0ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | (IData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]] : 0U)))); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - = ((0xffffff00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]) - | ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]] : 0U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xffeU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]))))); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xfffffffffff0ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - = (0xffffff00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xffeU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((2U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 1U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xffffffffff0fULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]] : 0U))) - << 4U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - = ((0xffff00ffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]] : 0U) << 8U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[1U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xffdU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U])))) - << 1U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xffffffffff0fULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - = (0xffff00ffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[1U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xffdU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((4U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 2U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xfffffffff0ffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]] : 0U))) - << 8U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - = ((0xff00ffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]] : 0U) << 0x10U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[2U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xffbU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])))) - << 2U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xfffffffff0ffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - = (0xff00ffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[2U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xffbU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((8U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 3U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xffffffff0fffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]] : 0U))) - << 0xcU)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - = ((0xffffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]] : 0U) << 0x18U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xff7U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])))) - << 3U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xffffffff0fffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - = (0xffffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xff7U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((0x10U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 4U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xfffffff0ffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]] : 0U))) - << 0x10U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - = ((0xffffff00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - | ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]] : 0U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[4U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xfefU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])))) - << 4U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xfffffff0ffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - = (0xffffff00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[4U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xfefU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((0x20U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 5U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xffffff0fffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]] : 0U))) - << 0x14U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - = ((0xffff00ffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]] : 0U) << 8U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[5U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xfdfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])))) - << 5U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xffffff0fffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - = (0xffff00ffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[5U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xfdfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((0x40U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 6U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xfffff0ffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]] : 0U))) - << 0x18U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - = ((0xff00ffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]] : 0U) << 0x10U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xfbfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])))) - << 6U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xfffff0ffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - = (0xff00ffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xfbfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((0x80U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 7U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xffff0fffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]] : 0U))) - << 0x1cU)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - = ((0xffffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]] : 0U) << 0x18U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xf7fU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])))) - << 7U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xffff0fffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - = (0xffffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xf7fU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((0x100U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 8U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xfff0ffffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]] : 0U))) - << 0x20U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - = ((0xffffff00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]) - | ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]] : 0U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xeffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U])))) - << 8U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xfff0ffffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - = (0xffffff00U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xeffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((0x200U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 9U)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xff0fffffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]] : 0U))) - << 0x24U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - = ((0xffff00ffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]] : 0U) << 8U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U])))) ? - ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xdffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U])))) - << 9U)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xff0fffffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - = (0xffff00ffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xdffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((0x400U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 0xaU)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xf0ffffffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]] : 0U))) - << 0x28U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - = ((0xff00ffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]] : 0U) << 0x10U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0xaU] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU])))) - ? ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0xbffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU])))) - << 0xaU)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xf0ffffffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - = (0xff00ffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0xaU] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0xbffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - if ((0x800U & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant))) { - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> 0xbU)))) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = ((0xfffffffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel) - | ((QData)((IData)(((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_sel - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]] : 0U))) - << 0x2cU)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - = ((0xffffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_addr - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]] : 0U) << 0x18U)); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0xbU] - = (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU])))) - ? ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) ? vlSelf->main__DOT__wb32_xbar__DOT__m_data - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]] : 0U) : 0U); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = ((0x7ffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - | (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - >> ((IData)(0x24U) - + vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU])))) - << 0xbU)); - } - } else { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - = (0xfffffffffffULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U] - = (0xffffffU & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U]); - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[0xbU] = 0U; - vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe - = (0x7ffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)); - } - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = ((0xffeU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)) - | ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0U])))); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0xffeU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - } - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = ((0xffdU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)) - | (0xfffffffeU & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [1U])) << 1U)))); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0xffdU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - } - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = ((0xffbU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)) - | (0xfffffffcU & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])) << 2U)))); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0xffbU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - } - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = ((0xff7U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)) - | (0xfffffff8U & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])) << 3U)))); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0xff7U & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - } - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = ((0xfefU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)) - | (0xfffffff0U & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])) << 4U)))); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0xfefU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - } - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = ((0xfdfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)) - | (0xffffffe0U & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])) << 5U)))); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0xfdfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - } - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = ((0xfbfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)) - | (0xffffffc0U & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])) << 6U)))); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0xfbfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - } - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = ((0xf7fU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)) - | (0xffffff80U & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - & (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])) << 7U)))); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0xf7fU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); 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- vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex - = vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex; - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_reindex; - vlSelf->main__DOT__wbwide_xbar__DOT__m_we = ((8U - & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0x12U] - << 3U)) - | ((4U - & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x12U] - << 2U)) - | ((2U - & (vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x12U] - << 1U)) - | (1U - & vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x12U])))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[0U][0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[1U][0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[2U][0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[2U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[3U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[4U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[5U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][4U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[6U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][5U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[7U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][6U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[8U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][7U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[9U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][8U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xaU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][9U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xbU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xaU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xcU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xbU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xdU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xcU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xeU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xdU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0xfU]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xeU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0x10U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_data[3U][0xfU] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0x11U]; - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__m_addr[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[0U] - = (((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data[0U]))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[1U] - = (((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_data[0U]))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[2U] - = (((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_data[0U]))); - vlSelf->main__DOT__wbwide_xbar__DOT__m_sel[3U] - = (((QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_data[0U]))); - vlSelf->main__DOT__wb32_xbar__DOT__m_addr[0U] = vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_addr; - vlSelf->main__DOT__wb32_xbar__DOT__sgrant = vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__sgrant; - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - = (((QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[1U])) - << 0x20U) | (QData)((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_ssel[0U]))); - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout = 0U; - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xfU; - if ((0U != (0xfU & (IData)(__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel)))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xeU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 4U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xdU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 8U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xcU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0xcU))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xbU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x10U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0xaU; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x14U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 9U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x18U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 8U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x1cU))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 7U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x20U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 6U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x24U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 5U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x28U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 4U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x2cU))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 3U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x30U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 2U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x34U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 1U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x38U))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm = 0U; - if ((0U != (0xfU & (IData)((__Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__sel - >> 0x3cU))))) { - __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout - = (0xfU & vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__Vstatic__fm); - } - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__i_subaddr - = __Vfunc_main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__DOWNSIZE__DOT__subaddr_fn__71__Vfuncout; - vlSelf->main__DOT__wb32_sirefclk_stb = (IData)( - (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) - & (0x200U - == - (0x700U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))); - vlSelf->main__DOT__wb32_spio_stb = (IData)((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 9U) - & (0x300U - == - (0x700U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])))); - vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb - = (1U & (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 7U) & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U] - >> 0x1aU))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn - = (0xffU & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) - ? vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - : (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_insn))); - if (((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__imm_cycle)) - & (0U == (0xf0U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn - = (0xf0U & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_insn) - << 4U)); - } - vlSelf->main__DOT__i2ci__DOT__next_insn = (0xffU - & ((IData)(vlSelf->main__DOT__i2ci__DOT__r_halted) - ? - vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - : (IData)(vlSelf->main__DOT__i2ci__DOT__pf_insn))); - if (((~ (IData)(vlSelf->main__DOT__i2ci__DOT__imm_cycle)) - & (0U == (0xf0U & (IData)(vlSelf->main__DOT__i2ci__DOT__next_insn))))) { - vlSelf->main__DOT__i2ci__DOT__next_insn = (0xf0U - & ((IData)(vlSelf->main__DOT__i2ci__DOT__next_insn) - << 4U)); - } - vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr - = ((0xf0000000U & vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr) - | vlSelf->main__DOT__u_i2cdma__DOT__r_baseaddr); - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[4U]; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb - = (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x10U))); - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old - = vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr; - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout - = ((0xffffU & vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout) - | ((((8U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - >> 0x18U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old - >> 0x18U)) << 0x18U) - | (0xff0000U & (((4U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - >> 0x10U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old - >> 0x10U)) - << 0x10U)))); - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout - = ((0xffff0000U & vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout) - | ((0xff00U & (((2U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - >> 8U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old - >> 8U)) << 8U)) - | (0xffU & ((1U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__strb)) - ? __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__nxt - : __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__old)))); - vlSelf->main__DOT__u_i2cdma__DOT__next_baseaddr - = vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__28__Vfuncout; - vlSelf->main__DOT__u_i2cdma__DOT__next_memlen = 0U; - vlSelf->main__DOT__u_i2cdma__DOT__next_memlen = - ((0xf0000000U & vlSelf->main__DOT__u_i2cdma__DOT__next_memlen) - | vlSelf->main__DOT__u_i2cdma__DOT__r_memlen); - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - = vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[4U]; - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb - = (0xfU & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x10U))); - __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old - = vlSelf->main__DOT__u_i2cdma__DOT__next_memlen; - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout - = ((0xffffU & vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout) - | ((((8U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - >> 0x18U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old - >> 0x18U)) << 0x18U) - | (0xff0000U & (((4U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - >> 0x10U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old - >> 0x10U)) - << 0x10U)))); - vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout - = ((0xffff0000U & vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout) - | ((0xff00U & (((2U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb)) - ? (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - >> 8U) : (__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old - >> 8U)) << 8U)) - | (0xffU & ((1U & (IData)(__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__strb)) - ? __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__nxt - : __Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__old)))); - vlSelf->main__DOT__u_i2cdma__DOT__next_memlen = vlSelf->__Vfunc_main__DOT__u_i2cdma__DOT__apply_strb__29__Vfuncout; - vlSelf->main__DOT__i2ci__DOT__bus_write = (1U & - (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 3U)); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U) & ((4U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U))); - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 8U) & ((0U == (7U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[2U])) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 8U))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_phy_stb - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U) & (IData)(((0x40000U == (0x70000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U)))); - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 6U) & (IData)(((0U == (0x70000U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 6U)))); - vlSelf->main__DOT__emmcscopei__DOT__write_to_control - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - & ((~ vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U]) - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))))); - vlSelf->main__DOT__emmcscopei__DOT__read_from_data - = ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & ((~ (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - & (0xfU == (0xfU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel)))))); - vlSelf->main__DOT__sdioscopei__DOT__write_to_control - = ((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 2U) & ((~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U)) & (0xf00ULL == - (0xf00ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel)))); - vlSelf->main__DOT__sdioscopei__DOT__read_from_data - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 2U) & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 2U)) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 0x10U) & (0xf00ULL - == - (0xf00ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))))); - vlSelf->main__DOT__i2cscopei__DOT__write_to_control - = ((((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe)) - >> 1U) & ((~ (vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U)) & (0xf0ULL == (0xf0ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel)))); - vlSelf->main__DOT__i2cscopei__DOT__read_from_data - = (((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - >> 1U) & ((~ ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 1U)) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U] - >> 8U) & (0xf0ULL - == - (0xf0ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))))); - if ((1U & ((~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb)) - | (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall))))) { - vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_data - = (((QData)((IData)((1U & (IData)((vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x2cU))))) - << 0x24U) | (0xfffffffffULL & vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data)); - } - if ((1U & ((((IData)(vlSelf->i_reset) | (~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc))) - | ((IData)(vlSelf->main__DOT__wb32_wbdown_cyc) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) - | (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err)))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc = 0U; - } else if ((1U & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb)))) { - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc = 1U; - } - vlSelf->main__DOT__wb32_xbar__DOT__mindex[0U] = vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbu_xbar__DOT__mindex[0U] = vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__wbwide_xbar__DOT__mindex[3U] - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_mindex; - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn - = vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__r_btn; - if ((((IData)(vlSelf->main__DOT__wb32_spio_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 9U)) & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x26U)))) { - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn - = ((IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn) - & (~ ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - << 0x10U) | (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[9U] - >> 0x10U)))); - } - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn - = ((IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn) - | (IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__s_btn)); - vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_int - = (0U != (IData)(vlSelf->main__DOT__spioi__DOT__GEN_BUTTON__DOT__next_btn)); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write - = ((IData)(vlSelf->main__DOT__u_fan__DOT____Vcellinp__u_i2ccpu__i_wb_stb) - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_swe) - >> 7U)); - vlSelf->main__DOT__i2ci__DOT__bus_manual = ((IData)(vlSelf->main__DOT__i2ci__DOT__bus_write) - & (IData)( - (((0x1000000U - == - (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[3U] - >> 0xbU)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xdU)))); - vlSelf->main__DOT__i2ci__DOT__bus_jump = ((IData)(vlSelf->main__DOT__i2ci__DOT__bus_write) - & (IData)( - ((((0x2000000U - == - (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) - & (0xf000ULL - == - (0xf000ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted))) - & (IData)(vlSelf->main__DOT__i2ci__DOT__r_halted)))); - if (vlSelf->main__DOT__i2ci__DOT__r_halted) { - vlSelf->main__DOT__i2ci__DOT__bus_override - = ((~ (IData)(vlSelf->main__DOT__i2ci__DOT__r_aborted)) - & ((IData)(vlSelf->main__DOT__i2ci__DOT__bus_write) - & (IData)(((0x1000000U == (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[0U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0xcU))))); - vlSelf->main__DOT__i2ci__DOT__next_valid = - ((IData)(vlSelf->main__DOT__i2ci__DOT__bus_override) - & (IData)(vlSelf->main__DOT__i2ci__DOT__ovw_ready)); - if (vlSelf->main__DOT__i2ci__DOT__bus_manual) { - vlSelf->main__DOT__i2ci__DOT__next_valid = 0U; - } - } else { - vlSelf->main__DOT__i2ci__DOT__bus_override = 0U; - vlSelf->main__DOT__i2ci__DOT__next_valid = - ((IData)(vlSelf->main__DOT__i2ci__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__i2ci__DOT__pf_ready)); - if (((IData)(vlSelf->main__DOT__i2ci__DOT__insn_valid) - & (0x900U == (0xf00U & (IData)(vlSelf->main__DOT__i2ci__DOT__insn))))) { - vlSelf->main__DOT__i2ci__DOT__next_valid = 0U; - } - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request - = ((((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x20U))) & ((1U == (3U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 6U))) - | (IData)(((0U - == - (0x2bc0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))))); - if ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & ((IData)(((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U) & (0x200U == (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U])))) - | ((~ (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x21U))) & (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)))))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - if ((((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xbU))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request - = ((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (0x300000000ULL == (0x300000000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x40U == (0xc0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]))) - | (0U == (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 6U))))) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U] - >> 0xbU) - | ((~ (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x240U - == - (0x3c0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[8U]))))); - if (((((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - if (((IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__cmd_type)))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request - = ((((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb)) - & (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x18U))) & ((1U == (3U & - (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 6U))) - | (IData)(((0U - == - (0x2bc0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U))))); - if ((((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & ((IData)(((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U) & (0x200U == (0x300U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U])))) - | ((~ (IData)((vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x19U))) & (2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type)))))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - if ((((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request)) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xbU))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; - } - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request - = ((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__wb_cmd_stb) - & (0x3000000ULL == (0x3000000ULL & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x40U == (0xc0U & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))) - | (0U == (3U & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 6U))))) & ((vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U] - >> 0xbU) - | ((~ (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy)) - & (0x240U - == - (0x3c0U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[6U]))))); - if (((((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__tx_en) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_tx_request)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__rx_en)) - | (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__r_rx_request))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - if (((IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__cmd_busy) - & (2U == (IData)(vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__cmd_type)))) { - vlSelf->main__DOT__u_emmc__DOT__u_sdio__DOT__u_control__DOT__new_data_request = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_valid) - ? vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__iskid__DOT__LOGIC__DOT__r_data - : vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_data); - vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err - = vlSelf->__Vdly__main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err; - vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr - = vlSelf->__Vdly__main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb - = vlSelf->__Vdly__main__DOT____Vcellout__wbwide_xbar__o_sstb; - vlSelf->main__DOT__wbu_xbar__DOT__m_stall = (1U - & ((vlSelf->main__DOT__wbu_xbar__DOT__grant - [0U] - >> 2U) - | (((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mgrant) - & ((2U - >= - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U]) - & (vlSelf->main__DOT__wbu_xbar__DOT__request - [0U] - >> - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U]))) - ? - ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__mfull) - | ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wbu_xbar__DOT__mindex - [0U])) - : (IData)(vlSelf->main__DOT__wbu_xbar__DOT__m_stb)))); - if (vlSelf->main__DOT__wbu_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) { - vlSelf->main__DOT__wbu_xbar__DOT__m_stall = 0U; - } - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (IData)((((0x1000000U == (0x3000000U & - vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_sdata[7U] - >> 0xbU)) & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1dU)))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_jump - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (IData)(((((0x2000000U == (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (0xf0000000ULL == (0xf0000000ULL - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel))) - & (~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted))) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted)))); - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_halted) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override - = ((~ (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__r_aborted)) - & ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_write) - & (IData)(((0x1000000U == (0x3000000U - & vlSelf->main__DOT____Vcellout__wb32_xbar__o_saddr[1U])) - & (vlSelf->main__DOT____Vcellout__wb32_xbar__o_ssel - >> 0x1cU))))); - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__ovw_ready)); - if (vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_manual) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid = 0U; - } - } else { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__bus_override = 0U; - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid - = ((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_valid) - & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__pf_ready)); - if (((IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn_valid) - & (0x900U == (0xf00U & (IData)(vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__insn))))) { - vlSelf->main__DOT__u_fan__DOT__u_i2ccpu__DOT__next_valid = 0U; - } - } - if (vlSelf->main__DOT__i2ci__DOT__bus_jump) { - vlSelf->main__DOT__i2ci__DOT__next_valid = 0U; - } - if (((IData)(vlSelf->i_reset) | (IData)(vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__soft_reset))) { - vlSelf->main__DOT__u_sdcard__DOT__u_sdio__DOT__u_control__DOT__new_cmd_request = 0U; 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- main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x38U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xf7fU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 7U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x40U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xeffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 8U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xf8U & (0x48U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xdffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 9U)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0xe0U & (0x60U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0xbffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 0xaU)); - main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0 - = (0U == (0x80U & (0x80U ^ (0xffU & (IData)( - (vlSelf->main__DOT__wb32_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__iskid__o_data - >> 0x24U)))))); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest - = ((0x7ffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT__prerequest)) - | ((IData)(main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__adcd__DOT____Vlvbound_h16d777b1__0) - << 0xbU)); - vlSelf->main__DOT__wb32_wbdown_err = vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr; - vlSelf->main__DOT__wb32_wbdown_cyc = vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc; - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__iskid__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)) - | (IData)(vlSelf->i_reset))); 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- vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc - = (((IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc) - << 3U) | (((IData)(vlSelf->main__DOT__wbwide_zip_cyc) - << 2U) | (((IData)(vlSelf->main__DOT__wbwide_i2cm_cyc) - << 1U) | (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)))); - vlSelf->main__DOT__wbwide_xbar__DOT__sindex[0U] - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex; - vlSelf->main__DOT__wbwide_xbar__DOT__sindex[1U] - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex; - vlSelf->main__DOT__wbwide_xbar__DOT__sindex[2U] - = vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__r_sindex; - vlSelf->main__DOT__wbwide_xbar__DOT__sgrant = vlSelf->__Vdly__main__DOT__wbwide_xbar__DOT__sgrant; - vlSelf->main__DOT__wbu_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbu_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbu_xbar__DOT__dcd_stb)); - if (vlSelf->i_reset) { - vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc - = (0x7ffU & (IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_scyc)); - vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb = 0U; - } else if ((1U & (~ (IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall)))) { - vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb - = vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid; - } - main__DOT__wb32_xbar__DOT____VdfgTmp_h4f7f05b5__0 - = ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb)); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_valid - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stb) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT__s_err = (8U - | ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_err))); - vlSelf->main__DOT__u_wbdown__DOT____Vcellinp__DOWNSIZE__DOT__u_fifo__i_reset - = (1U & ((~ (IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc)) - | (IData)(vlSelf->i_reset))); - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]))); - if ((1U & (((~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U]]) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [0U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]))); - if ((1U & (((~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U]] >> 1U)) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [1U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant - = (1U & (~ ((IData)(vlSelf->main__DOT____Vcellinp__wbwide_xbar__i_mcyc) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]))); - if ((1U & (((~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U]] >> 2U)) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U])) & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> vlSelf->main__DOT__wbwide_xbar__DOT__sindex - [2U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available - = (0U != (7U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U])))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__requested_channel_is_available = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available - = (0U != (7U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U])))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__requested_channel_is_available = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available - = (0U != (7U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U])))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__requested_channel_is_available = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__requested_channel_is_available - = (0U != (7U & ((vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant))) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U])))); - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__requested_channel_is_available = 1U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 2U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U] >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] >> 3U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant = 0U; - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [2U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 2U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant = 0U; - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant)) - & (~ vlSelf->main__DOT__wbwide_xbar__DOT__requested - [3U])))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (8U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U]))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__0__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant = 0U; - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [0U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (1U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (~ (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__sgrant) - >> 1U)) & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__requested - [1U] >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (2U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 1U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((2U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__1__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); 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- } - if ((1U & (~ (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] >> 2U)))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((1U & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) & (~ ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mempty) - >> 1U))))) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); - } - if ((4U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U])) { - vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant - = (4U | (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__GEN_SINDEX__BRA__2__KET____DOT__SINDEX_MORE_THAN_ONE_MASTER__DOT__regrant)); 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- } - if ((0x800U & vlSelf->main__DOT__wb32_xbar__DOT__grant - [0U])) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0x800U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } else if ((1U & ((~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 0xbU)) & (~ (vlSelf->main__DOT__wb32_xbar__DOT__requested - [0U] >> 0xbU))))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0x800U | (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); - } - if ((1U & (~ (vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] >> 0xbU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant - = (0x17ffU & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant)); 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- } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]] : 0U) >> 2U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [2U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 2U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]] : 0U) >> 3U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [3U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 3U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]] : 0U) >> 4U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [4U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 4U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]] : 0U) >> 5U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [5U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 5U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]] : 0U) >> 6U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [6U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 6U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]] : 0U) >> 7U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [7U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 7U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]] : 0U) >> 8U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [8U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 8U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]] : 0U) >> 9U)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> - vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [9U])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 9U)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]] : 0U) >> 0xaU)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xaU])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 0xaU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant - = (1U & (~ ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU])))); - if ((((~ (((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) ? vlSelf->main__DOT__wb32_xbar__DOT__request - [vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]] : 0U) >> 0xbU)) & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) - & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]))) - & ((0U >= vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU]) & ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mempty) - >> vlSelf->main__DOT__wb32_xbar__DOT__sindex - [0xbU])))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 1U; - } - if ((1U & (~ ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__sgrant) - >> 0xbU)))) { - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 0U; - } - if (vlSelf->i_reset) { - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wbwide_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__0__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__1__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__2__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__3__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__4__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__5__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__6__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__7__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__8__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__9__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__10__KET____DOT__drop_sgrant = 1U; - vlSelf->main__DOT__wb32_xbar__DOT__SLAVE_GRANT__BRA__11__KET____DOT__drop_sgrant = 1U; - } -} - -VL_INLINE_OPT void Vmain___024root___nba_comb__TOP__0(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___nba_comb__TOP__0\n"); ); - // Body - vlSelf->main__DOT__wb32_xbar__DOT__s_stall = (0xf000U - | (0xfffff800U - & ((IData)(vlSelf->main__DOT____Vcellout__wb32_xbar__o_sstb) - & ((IData)(vlSelf->main__DOT__wb32_ddr3_phy_stall) - << 0xbU)))); - vlSelf->main__DOT__wbwide_xbar__DOT__s_stall = - (8U | ((0xfffffffcU & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - & ((IData)(vlSelf->main__DOT__wbwide_ddr3_controller_stall) - << 2U))) | ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - & (IData)(vlSelf->main__DOT__wbwide_wbdown_stall)))); - vlSelf->main__DOT__wbwide_xbar__DOT__s_ack = ((0xfffffffcU - & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & ((vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_ack_read_q - [0U] - & (0xeU - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate))) - << 2U))) - | ((0xfffffffeU - & ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & ((IData)(vlSelf->main__DOT__wbwide_bkram_ack) - << 1U))) - | ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - & (IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_ack)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt - = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt_q) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__write_calib_odt)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en - = (1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0x18U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n - = (1U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0x17U)); - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xfeU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (1U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[0U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [0U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xfdU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (2U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[1U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [1U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xfbU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (4U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[2U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [2U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xf7U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (8U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[3U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [3U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xefU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (0x10U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[4U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [4U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xdfU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (0x20U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[5U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [5U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0xbfU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (0x40U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[6U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [6U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((0x7fU & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)) - | (0x80U & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[7U] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [7U]; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = ((0x800000U & ((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_counter_is_zero)) - << 0x17U)) | ((0x700000U & - (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - << 1U)) | - (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) - | ((0x40000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 6U)) - | ((0x20000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 6U)) - | ((0x1c000U - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 2U)) - | (0x3fffU - & vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction))))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = ((0xfffbffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U]) | (0x400U & (vlSelf->main__DOT__ddr3_controller_inst__DOT__instruction - >> 0xfU))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] - = (0x500000U | (((2U != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__state_calibrate)) - << 0x17U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | - (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] - = (0xc00000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0xb00000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | - ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[0U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [0U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [0U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[0U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [0U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [0U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[0U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [0U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [0U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[0U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [0U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [0U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[1U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [1U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [1U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[1U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [1U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [1U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[1U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [1U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [1U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[1U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [1U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [1U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[2U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [2U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [2U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[2U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [2U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [2U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[2U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [2U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [2U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[2U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [2U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [2U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[3U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [3U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [3U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[3U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [3U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [3U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[3U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [3U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [3U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[3U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [3U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [3U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[4U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [4U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [4U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[4U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [4U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [4U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[4U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [4U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [4U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[4U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [4U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [4U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[5U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [5U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [5U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[5U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [5U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [5U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[5U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [5U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [5U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[5U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [5U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [5U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[6U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [6U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [6U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[6U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [6U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [6U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[6U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [6U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [6U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[6U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [6U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [6U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[7U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [7U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [7U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[7U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [7U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [7U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[7U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [7U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [7U] - (IData)(1U)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[7U] - = ((0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [7U]) ? 0U : (0xfU & (vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [7U] - (IData)(1U)))); - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 1U; - if ((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row)))) { - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt = 1U; - if ((4U >= vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank])) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 4U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[0U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] - = (0x480000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank) - << 0xeU) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[1U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0x80000U | vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [0U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[2U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = (0x80000U | vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[3U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] - = (0x80000U | vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [2U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[4U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] - = (0x80000U | vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [3U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[5U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[6U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[7U] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 3U; - } else if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we)) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt = 0U; - if ((1U >= vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank])) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 1U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] - = (0x500000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank) - << 0xeU) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_col))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0xf7ffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [0U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = (0xf7ffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[2U] - = (0xf7ffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [2U]); - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[3U] - = (0xf7ffffU & vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [3U]); - } - } else if (((~ ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank))) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 3U; - if ((0U >= vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank])) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 0U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0x300000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank) - << 0xeU) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row)))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - | (0xffU & ((IData)(1U) << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row; - } else if (((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row))) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = (0x200000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank) - << 0xeU) - | (0x3ffU - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row))))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((~ ((IData)(1U) << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank))) - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - } - } - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending) - & (~ (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank) - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending))))) { - if ((((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] - != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row))) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank])) - & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__precharge_slot_busy)))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] = 1U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[1U] - = (0x200000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank) - << 0xeU) - | (0x3ffU - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row))))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((~ ((IData)(1U) << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank))) - & (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d)); - } else if ((((~ ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_q) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank))) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_activate_counter_q - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank])) - & (~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__activate_slot_busy)))) { - if ((0U >= vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank])) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] = 0U; - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_precharge_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] = 3U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] = 0U; - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d[0U] - = (0x300000U | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_odt) - << 0x13U) | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_ck_en) - << 0x12U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_reset_n) - << 0x11U) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank) - << 0xeU) - | (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row)))))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d - = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - | (0xffU & ((IData)(1U) << (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank)))); - vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d[vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_bank] - = vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_next_row; - } - } - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_pending) { - if ((((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank] - == (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_row)))) { - if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - } else if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_we)) - & (0U == vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall = 0U; - } - } - } - if (vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending) { - if ((1U & ((~ ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank))) - | (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_status_d) - >> (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank)) - & (vlSelf->main__DOT__ddr3_controller_inst__DOT__bank_active_row_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank] - != (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_row)))))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 1U; - } else if (((~ (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we)) - & (0U != vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_read_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 1U; - } else if (((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_we) - & (0U != vlSelf->main__DOT__ddr3_controller_inst__DOT__delay_before_write_counter_d - [vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_bank]))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall = 1U; - } - } - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_d - = ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_q) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall) - : (((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_sstb) - >> 2U) & ((IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_pending) - ? (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage1_stall) - : (IData)(vlSelf->main__DOT__ddr3_controller_inst__DOT__stage2_stall)))); - if ((1U & (~ ((IData)(vlSelf->main__DOT____Vcellout__wbwide_xbar__o_scyc) - >> 2U)))) { - vlSelf->main__DOT__ddr3_controller_inst__DOT__o_wb_stall_d = 0U; - } - vlSelf->main__DOT__wb32_xbar__DOT__m_stall = (1U - & ((vlSelf->main__DOT__wb32_xbar__DOT__grant - [0U] - >> 0xcU) - | (((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mgrant) - & ((0xcU - >= - vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U]) - & (vlSelf->main__DOT__wb32_xbar__DOT__request - [0U] - >> - vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U]))) - ? - ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__mfull) - | ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wb32_xbar__DOT__mindex - [0U])) - : (IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stb)))); - if (vlSelf->main__DOT__wb32_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr) { - vlSelf->main__DOT__wb32_xbar__DOT__m_stall = 0U; - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = - ((0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)) - | (1U & ((vlSelf->main__DOT__wbwide_xbar__DOT__grant - [0U] >> 3U) | ((1U & ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [0U] >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U]))) - ? ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [0U])) : (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb))))); - if ((1U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall - = (0xeU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = - ((0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)) - | (2U & ((0x3ffffffeU & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [1U] >> 2U)) | (( - (1U - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 1U) - & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [1U] - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U]))) - ? - (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 1U) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [1U])) - : - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 1U)) - << 1U)))); - if ((2U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall - = (0xdU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = - ((0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)) - | (4U & ((0x7ffffffcU & (vlSelf->main__DOT__wbwide_xbar__DOT__grant - [2U] >> 1U)) | (( - (1U - & (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 2U) - & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [2U] - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U]))) - ? - (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 2U) - | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [2U])) - : - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 2U)) - << 2U)))); - if ((4U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall - = (0xbU & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)); - } - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall = - ((7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)) - | (8U & ((0xfffffff8U & vlSelf->main__DOT__wbwide_xbar__DOT__grant - [3U]) | (((IData)((((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mgrant) - >> 3U) & (vlSelf->main__DOT__wbwide_xbar__DOT__request - [3U] - >> - vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U]))) - ? (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__mfull) - >> 3U) | ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__s_stall) - >> vlSelf->main__DOT__wbwide_xbar__DOT__mindex - [3U])) : - ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stb) - >> 3U)) << 3U)))); - if ((8U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__DOUBLE_BUFFERRED_STALL__DOT__r_merr))) { - vlSelf->main__DOT__wbwide_xbar__DOT__m_stall - = (7U & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall)); - } - vlSelf->o_ddr3_controller_cmd[0U] = (IData)((((QData)((IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U])) - << 0x18U) - | (QData)((IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [0U])))); - vlSelf->o_ddr3_controller_cmd[1U] = ((vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [2U] << 0x10U) - | (IData)( - ((((QData)((IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [1U])) - << 0x18U) - | (QData)((IData)( - vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [0U]))) - >> 0x20U))); - vlSelf->o_ddr3_controller_cmd[2U] = ((vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [3U] << 8U) - | (vlSelf->main__DOT__ddr3_controller_inst__DOT__cmd_d - [2U] >> 0x10U)); - vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall - = ((IData)(vlSelf->main__DOT__u_wbdown__DOT__DOWNSIZE__DOT__r_cyc) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__m_stall)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - & (IData)(vlSelf->main__DOT__wbwide_i2cdma_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall - = (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 1U) & (IData)(vlSelf->main__DOT__wbwide_i2cm_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall - = (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 2U) & (IData)(vlSelf->main__DOT__wbwide_zip_cyc)); - vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall - = (((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__m_stall) - >> 3U) & (IData)(vlSelf->main__DOT__wbu_arbiter_upsz__DOT__UPSIZE__DOT__r_cyc)); - vlSelf->main__DOT__wb32_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wb32_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wb32_xbar__DOT__dcd_stb)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__0__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__0__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__0__KET____DOT__adcd__o_valid)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__1__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__1__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__1__KET____DOT__adcd__o_valid)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__2__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__2__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__2__KET____DOT__adcd__o_valid)); - vlSelf->main__DOT__wbwide_xbar__DOT__DECODE_REQUEST__BRA__3__KET____DOT__skd_stall - = ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellinp__DECODE_REQUEST__BRA__3__KET____DOT__adcd__i_stall) - & (IData)(vlSelf->main__DOT__wbwide_xbar__DOT____Vcellout__DECODE_REQUEST__BRA__3__KET____DOT__adcd__o_valid)); -} - -void Vmain___024root___nba_sequent__TOP__0(Vmain___024root* vlSelf); -void Vmain___024root___nba_sequent__TOP__1(Vmain___024root* vlSelf); -void Vmain___024root___nba_sequent__TOP__2(Vmain___024root* vlSelf); -void Vmain___024root___nba_sequent__TOP__3(Vmain___024root* vlSelf); -void Vmain___024root___nba_sequent__TOP__4(Vmain___024root* vlSelf); -void Vmain___024root___nba_sequent__TOP__5(Vmain___024root* vlSelf); - -void Vmain___024root___eval_nba(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_nba\n"); ); - // Body - if ((1ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__0(vlSelf); - vlSelf->__Vm_traceActivity[2U] = 1U; - Vmain___024root___nba_sequent__TOP__1(vlSelf); - Vmain___024root___nba_sequent__TOP__2(vlSelf); - Vmain___024root___nba_sequent__TOP__3(vlSelf); - Vmain___024root___nba_sequent__TOP__4(vlSelf); - } - if ((0x80ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__5(vlSelf); - vlSelf->__Vm_traceActivity[3U] = 1U; - } - if ((0x20ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__6(vlSelf); - } - if ((0x40ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__7(vlSelf); - } - if ((2ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__8(vlSelf); - } - if ((4ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__9(vlSelf); - } - if ((8ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__10(vlSelf); - } - if ((0x10ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__11(vlSelf); - } - if ((0x100ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__12(vlSelf); - vlSelf->__Vm_traceActivity[4U] = 1U; - } - if ((1ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_sequent__TOP__13(vlSelf); - vlSelf->__Vm_traceActivity[5U] = 1U; - } - if ((0x81ULL & vlSelf->__VnbaTriggered.word(0U))) { - Vmain___024root___nba_comb__TOP__0(vlSelf); - vlSelf->__Vm_traceActivity[6U] = 1U; - } -} - -void Vmain___024root___eval_triggers__ico(Vmain___024root* vlSelf); -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__ico(Vmain___024root* vlSelf); -#endif // VL_DEBUG -void Vmain___024root___eval_ico(Vmain___024root* vlSelf); -void Vmain___024root___eval_triggers__act(Vmain___024root* vlSelf); -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__act(Vmain___024root* vlSelf); -#endif // VL_DEBUG -void Vmain___024root___eval_act(Vmain___024root* vlSelf); -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__nba(Vmain___024root* vlSelf); -#endif // VL_DEBUG - -void Vmain___024root___eval(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval\n"); ); - // Init - CData/*0:0*/ __VicoContinue; - VlTriggerVec<9> __VpreTriggered; - IData/*31:0*/ __VnbaIterCount; - CData/*0:0*/ __VnbaContinue; - // Body - vlSelf->__VicoIterCount = 0U; - __VicoContinue = 1U; - while (__VicoContinue) { - __VicoContinue = 0U; - Vmain___024root___eval_triggers__ico(vlSelf); - if (vlSelf->__VicoTriggered.any()) { - __VicoContinue = 1U; - if (VL_UNLIKELY((0x64U < vlSelf->__VicoIterCount))) { -#ifdef VL_DEBUG - Vmain___024root___dump_triggers__ico(vlSelf); -#endif - VL_FATAL_MT("main.v", 97, "", "Input combinational region did not converge."); - } - vlSelf->__VicoIterCount = ((IData)(1U) - + vlSelf->__VicoIterCount); - Vmain___024root___eval_ico(vlSelf); - } - } - __VnbaIterCount = 0U; - __VnbaContinue = 1U; - while (__VnbaContinue) { - __VnbaContinue = 0U; - vlSelf->__VnbaTriggered.clear(); - vlSelf->__VactIterCount = 0U; - vlSelf->__VactContinue = 1U; - while (vlSelf->__VactContinue) { - vlSelf->__VactContinue = 0U; - Vmain___024root___eval_triggers__act(vlSelf); - if (vlSelf->__VactTriggered.any()) { - vlSelf->__VactContinue = 1U; - if (VL_UNLIKELY((0x64U < vlSelf->__VactIterCount))) { -#ifdef VL_DEBUG - Vmain___024root___dump_triggers__act(vlSelf); -#endif - VL_FATAL_MT("main.v", 97, "", "Active region did not converge."); - } - vlSelf->__VactIterCount = ((IData)(1U) - + vlSelf->__VactIterCount); - __VpreTriggered.andNot(vlSelf->__VactTriggered, vlSelf->__VnbaTriggered); - vlSelf->__VnbaTriggered.thisOr(vlSelf->__VactTriggered); - Vmain___024root___eval_act(vlSelf); - } - } - if (vlSelf->__VnbaTriggered.any()) { - __VnbaContinue = 1U; - if (VL_UNLIKELY((0x64U < __VnbaIterCount))) { -#ifdef VL_DEBUG - Vmain___024root___dump_triggers__nba(vlSelf); -#endif - VL_FATAL_MT("main.v", 97, "", "NBA region did not converge."); - } - __VnbaIterCount = ((IData)(1U) + __VnbaIterCount); - Vmain___024root___eval_nba(vlSelf); - } - } -} - -#ifdef VL_DEBUG -void Vmain___024root___eval_debug_assertions(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_debug_assertions\n"); ); - // Body - if (VL_UNLIKELY((vlSelf->i_clk & 0xfeU))) { - Verilated::overWidthError("i_clk");} - if (VL_UNLIKELY((vlSelf->i_reset & 0xfeU))) { - Verilated::overWidthError("i_reset");} - if (VL_UNLIKELY((vlSelf->i_ddr3_controller_idelayctrl_rdy - & 0xfeU))) { - Verilated::overWidthError("i_ddr3_controller_idelayctrl_rdy");} - if (VL_UNLIKELY((vlSelf->i_fan_sda & 0xfeU))) { - Verilated::overWidthError("i_fan_sda");} - if (VL_UNLIKELY((vlSelf->i_fan_scl & 0xfeU))) { - Verilated::overWidthError("i_fan_scl");} - if (VL_UNLIKELY((vlSelf->i_fan_tach & 0xfeU))) { - Verilated::overWidthError("i_fan_tach");} - if (VL_UNLIKELY((vlSelf->i_emmc_ds & 0xfeU))) { - Verilated::overWidthError("i_emmc_ds");} - if (VL_UNLIKELY((vlSelf->i_emmc_cmd & 0xfeU))) { - Verilated::overWidthError("i_emmc_cmd");} - if (VL_UNLIKELY((vlSelf->i_emmc_detect & 0xfeU))) { - Verilated::overWidthError("i_emmc_detect");} - if (VL_UNLIKELY((vlSelf->i_i2c_sda & 0xfeU))) { - Verilated::overWidthError("i_i2c_sda");} - if (VL_UNLIKELY((vlSelf->i_i2c_scl & 0xfeU))) { - Verilated::overWidthError("i_i2c_scl");} - if (VL_UNLIKELY((vlSelf->i_sdcard_ds & 0xfeU))) { - Verilated::overWidthError("i_sdcard_ds");} - if (VL_UNLIKELY((vlSelf->i_sdcard_cmd & 0xfeU))) { - Verilated::overWidthError("i_sdcard_cmd");} - if (VL_UNLIKELY((vlSelf->i_sdcard_dat & 0xf0U))) { - Verilated::overWidthError("i_sdcard_dat");} - if (VL_UNLIKELY((vlSelf->i_sdcard_detect & 0xfeU))) { - Verilated::overWidthError("i_sdcard_detect");} - if (VL_UNLIKELY((vlSelf->cpu_sim_cyc & 0xfeU))) { - Verilated::overWidthError("cpu_sim_cyc");} - if (VL_UNLIKELY((vlSelf->cpu_sim_stb & 0xfeU))) { - Verilated::overWidthError("cpu_sim_stb");} - if (VL_UNLIKELY((vlSelf->cpu_sim_we & 0xfeU))) { - Verilated::overWidthError("cpu_sim_we");} - if (VL_UNLIKELY((vlSelf->cpu_sim_addr & 0x80U))) { - Verilated::overWidthError("cpu_sim_addr");} - if (VL_UNLIKELY((vlSelf->i_cpu_reset & 0xfeU))) { - Verilated::overWidthError("i_cpu_reset");} - if (VL_UNLIKELY((vlSelf->i_clk200 & 0xfeU))) { - Verilated::overWidthError("i_clk200");} - if (VL_UNLIKELY((vlSelf->i_wbu_uart_rx & 0xfeU))) { - Verilated::overWidthError("i_wbu_uart_rx");} - if (VL_UNLIKELY((vlSelf->i_btn & 0xe0U))) { - Verilated::overWidthError("i_btn");} -} -#endif // VL_DEBUG diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h8b02a3a0__0.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h8b02a3a0__0.cpp deleted file mode 100644 index 19234e2..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h8b02a3a0__0.cpp +++ /dev/null @@ -1,87 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__ico(Vmain___024root* vlSelf); -#endif // VL_DEBUG - -void Vmain___024root___eval_triggers__ico(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_triggers__ico\n"); ); - // Body - vlSelf->__VicoTriggered.set(0U, (0U == vlSelf->__VicoIterCount)); -#ifdef VL_DEBUG - if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) { - Vmain___024root___dump_triggers__ico(vlSelf); - } -#endif -} - -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__act(Vmain___024root* vlSelf); -#endif // VL_DEBUG - -void Vmain___024root___eval_triggers__act(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_triggers__act\n"); ); - // Body - vlSelf->__VactTriggered.set(0U, ((IData)(vlSelf->i_clk) - & (~ (IData)(vlSelf->__Vtrigprevexpr___TOP__i_clk__0)))); - vlSelf->__VactTriggered.set(1U, ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant) - != (IData)(vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0))); - vlSelf->__VactTriggered.set(2U, ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant) - != (IData)(vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0))); - vlSelf->__VactTriggered.set(3U, ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant) - != (IData)(vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0))); - vlSelf->__VactTriggered.set(4U, ((IData)(vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant) - != (IData)(vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0))); - vlSelf->__VactTriggered.set(5U, ((IData)(vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant) - != (IData)(vlSelf->__Vtrigprevexpr___TOP__main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0))); - vlSelf->__VactTriggered.set(6U, ((IData)(vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant) - != (IData)(vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0))); - vlSelf->__VactTriggered.set(7U, (((IData)(vlSelf->i_clk) - & (~ (IData)(vlSelf->__Vtrigprevexpr___TOP__i_clk__0))) - | ((~ (IData)(vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n)) - & (IData)(vlSelf->__Vtrigprevexpr___TOP__main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n__0)))); - vlSelf->__VactTriggered.set(8U, ((~ (IData)(vlSelf->i_clk)) - & (IData)(vlSelf->__Vtrigprevexpr___TOP__i_clk__0))); - vlSelf->__Vtrigprevexpr___TOP__i_clk__0 = vlSelf->i_clk; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__1__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__2__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbwide_xbar__DOT__ARBITRATE_REQUESTS__BRA__3__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wb32_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant__0 - = vlSelf->main__DOT__wbu_xbar__DOT__ARBITRATE_REQUESTS__BRA__0__KET____DOT__MINDEX_MULTIPLE_SLAVES__DOT__r_regrant; - vlSelf->__Vtrigprevexpr___TOP__main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n__0 - = vlSelf->main__DOT____Vcellinp__ddr3_controller_inst__i_rst_n; - if (VL_UNLIKELY((1U & (~ (IData)(vlSelf->__VactDidInit))))) { - vlSelf->__VactDidInit = 1U; - vlSelf->__VactTriggered.set(1U, 1U); - vlSelf->__VactTriggered.set(2U, 1U); - vlSelf->__VactTriggered.set(3U, 1U); - vlSelf->__VactTriggered.set(4U, 1U); - vlSelf->__VactTriggered.set(5U, 1U); - vlSelf->__VactTriggered.set(6U, 1U); - } -#ifdef VL_DEBUG - if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) { - Vmain___024root___dump_triggers__act(vlSelf); - } -#endif -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h8b02a3a0__0__Slow.cpp b/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h8b02a3a0__0__Slow.cpp deleted file mode 100644 index c53b90f..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__DepSet_h8b02a3a0__0__Slow.cpp +++ /dev/null @@ -1,27 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -#ifdef VL_DEBUG -VL_ATTR_COLD void Vmain___024root___dump_triggers__stl(Vmain___024root* vlSelf); -#endif // VL_DEBUG - -VL_ATTR_COLD void Vmain___024root___eval_triggers__stl(Vmain___024root* vlSelf) { - if (false && vlSelf) {} // Prevent unused - Vmain__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp; - VL_DEBUG_IF(VL_DBG_MSGF("+ Vmain___024root___eval_triggers__stl\n"); ); - // Body - vlSelf->__VstlTriggered.set(0U, (0U == vlSelf->__VstlIterCount)); -#ifdef VL_DEBUG - if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) { - Vmain___024root___dump_triggers__stl(vlSelf); - } -#endif -} diff --git a/delete_later/rtl/obj_dir/Vmain___024root__Slow.cpp b/delete_later/rtl/obj_dir/Vmain___024root__Slow.cpp deleted file mode 100644 index a787cb8..0000000 --- a/delete_later/rtl/obj_dir/Vmain___024root__Slow.cpp +++ /dev/null @@ -1,27 +0,0 @@ -// Verilated -*- C++ -*- -// DESCRIPTION: Verilator output: Design implementation internals -// See Vmain.h for the primary calling header - -#include "verilated.h" -#include "verilated_dpi.h" - -#include "Vmain__Syms.h" -#include "Vmain__Syms.h" -#include "Vmain___024root.h" - -void Vmain___024root___ctor_var_reset(Vmain___024root* vlSelf); - -Vmain___024root::Vmain___024root(Vmain__Syms* symsp, const char* v__name) - : VerilatedModule{v__name} - , vlSymsp{symsp} - { - // Reset structure values - Vmain___024root___ctor_var_reset(this); -} - -void Vmain___024root::__Vconfigure(bool first) { - if (false && first) {} // Prevent unused -} - -Vmain___024root::~Vmain___024root() { -} diff --git a/delete_later/rtl/obj_dir/Vmain_classes.mk b/delete_later/rtl/obj_dir/Vmain_classes.mk deleted file mode 100644 index f840140..0000000 --- a/delete_later/rtl/obj_dir/Vmain_classes.mk +++ /dev/null @@ -1,65 +0,0 @@ -# Verilated -*- Makefile -*- -# DESCRIPTION: Verilator output: Make include file with class lists -# -# This file lists generated Verilated files, for including in higher level makefiles. -# See Vmain.mk for the caller. - -### Switches... -# C11 constructs required? 0/1 (always on now) -VM_C11 = 1 -# Timing enabled? 0/1 -VM_TIMING = 0 -# Coverage output mode? 0/1 (from --coverage) -VM_COVERAGE = 0 -# Parallel builds? 0/1 (from --output-split) -VM_PARALLEL_BUILDS = 1 -# Tracing output mode? 0/1 (from --trace/--trace-fst) -VM_TRACE = 1 -# Tracing output mode in VCD format? 0/1 (from --trace) -VM_TRACE_VCD = 1 -# Tracing output mode in FST format? 0/1 (from --trace-fst) -VM_TRACE_FST = 0 - -### Object file lists... -# Generated module classes, fast-path, compile with highest optimization -VM_CLASSES_FAST += \ - Vmain \ - Vmain___024root__DepSet_h8b02a3a0__0 \ - Vmain___024root__DepSet_h3334316c__0 \ - Vmain___024root__DepSet_h3334316c__1 \ - Vmain___024root__DepSet_h3334316c__2 \ - Vmain___024root__DepSet_h3334316c__3 \ - Vmain___024root__DepSet_h3334316c__4 \ - Vmain___024root__DepSet_h3334316c__5 \ - -# Generated module classes, non-fast-path, compile with low/medium optimization -VM_CLASSES_SLOW += \ - Vmain__ConstPool_0 \ - Vmain___024root__Slow \ - Vmain___024root__DepSet_h8b02a3a0__0__Slow \ - Vmain___024root__DepSet_h3334316c__0__Slow \ - Vmain___024root__DepSet_h3334316c__1__Slow \ - Vmain___024root__DepSet_h3334316c__2__Slow \ - -# Generated support classes, fast-path, compile with highest optimization -VM_SUPPORT_FAST += \ - Vmain__Dpi \ - Vmain__Trace__0 \ - -# Generated support classes, non-fast-path, compile with low/medium optimization -VM_SUPPORT_SLOW += \ - Vmain__Syms \ - Vmain__Trace__0__Slow \ - -# Global classes, need linked once per executable, fast-path, compile with highest optimization -VM_GLOBAL_FAST += \ - verilated \ - verilated_dpi \ - verilated_vcd_c \ - verilated_threads \ - -# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization -VM_GLOBAL_SLOW += \ - - -# Verilated -*- Makefile -*- diff --git a/delete_later/rtl/qflexpress.v b/delete_later/rtl/qflexpress.v deleted file mode 100644 index 1920e97..0000000 --- a/delete_later/rtl/qflexpress.v +++ /dev/null @@ -1,2314 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: qflexpress.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: To provide wishbone controlled read access (and read access -// *only*) to the QSPI flash, using a flash clock equal to the -// system clock, and nothing more. Indeed, this is designed to be a -// *very* stripped down version of a flash driver, with the goal of -// providing 1) very fast access for 2) very low logic count. -// -// Three modes/states of operation: -// 1. Startup/maintenance, places the device in the Quad XIP mode -// 2. Normal operations, takes 33 clocks to read a value -// - 16 subsequent clocks will read a piped value -// 3. Configuration--useful to allow an external controller issue erase -// or program commands (or other) without requiring us to -// clutter up the logic with a giant state machine -// -// STARTUP -// 1. Waits for the flash to come on line -// Start out idle for 300 uS -// 2. Sends a signal to remove the flash from any QSPI read mode. In our -// case, we'll send several clocks of an empty command. In SPI -// mode, it'll get ignored. In QSPI mode, it'll remove us from -// QSPI mode. -// 3. Explicitly places and leaves the flash into QSPI mode -// 0xEB 3(0x00) 0xa0 6(0x00) -// 4. All done -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -// 290 raw, 372 w/ pipe, 410 cfg, 499 cfg w/pipe -module qflexpress #( - // - // LGFLASHSZ is the size of the flash memory. It defines the - // {{{ - // number of bits in the address register and more. This - // controller will support flash sizes up to 2^LGFLASHSZ, - // where LGFLASHSZ goes up to 32. - parameter LGFLASHSZ=24, - // }}} - // OPT_PIPE makes it possible to string multiple requests - // {{{ - // together, with no intervening need to shutdown the - // QSPI connection and send a new address - parameter [0:0] OPT_PIPE = 1'b1, - // }}} - // OPT_CFG enables the configuration logic port, and hence the - // {{{ - // ability to erase and program the flash, as well as the - // ability to perform other commands such as read-manufacturer - // ID, adjust configuration registers, etc. - parameter [0:0] OPT_CFG = 1'b1, - // }}} - // OPT_STARTUP enables the startup logic - // {{{ - parameter [0:0] OPT_STARTUP = 1'b1, - // }}} - parameter OPT_CLKDIV = 0, - // - // OPT_ENDIANSWAP. Normally, I place the first byte read from - // {{{ - // the flash, and the lowest flash address, into bits [7:0], - // and then shift it up--to where upon return it is found in - // bits [31:24]. This is ideal for a big endian systems, not - // so much for little endian systems. The endian swap allows - // the bus to swap the return values in order to support little - // endian systems. - parameter [0:0] OPT_ENDIANSWAP = 1'b0, - // }}} - // RDDELAY is the number of clock cycles from when o_qspi_dat - // {{{ - // is valid until i_qspi_dat is valid. Read delays from - // 0-4 have been verified. DDR Registered I/O on a - // Xilinx device can be done with a RDDELAY=3. On Intel/Altera - // devices, RDDELAY=2 works. I'm using RDDELAY=0 for my iCE40 - // devices - parameter RDDELAY = 0, - // }}} - // NDUMMY is the number of "dummy" clock cycles between the - // {{{ - // 24-bits (or 32-bits) of the Quad I/O address and the first - // data bits. This includes the two clocks of the Quad output - // mode byte, 0xa0. The default is 10 for a Micron device. - // Windbond seems to want 2. Note your flash device carefully - // when you choose this value. - parameter NDUMMY = 6, - // }}} - // OPT_STARTUP_FILE: For dealing with multiple flash devices, - // {{{ - // the OPT_STARTUP_FILE allows a hex file to be provided - // containing the necessary script to place the design into - // the proper initial configuration. - parameter OPT_STARTUP_FILE="spansion.hex", - // }}} - // - localparam AW=LGFLASHSZ-2, - localparam DW=32 - ) ( - // {{{ - input wire i_clk, i_reset, - // - // Flash memory port - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [(AW-1):0] i_wb_addr, - input wire [(DW-1):0] i_wb_data, - input wire [DW/8-1:0] i_wb_sel, - // - output wire o_wb_stall, o_wb_ack, - output reg [(DW-1):0] o_wb_data, - // }}} - // Configuration port - // {{{ - input wire i_cfg_cyc, i_cfg_stb, i_cfg_we, - input wire [(DW-1):0] i_cfg_data, - input wire [DW/8-1:0] i_cfg_sel, - // - output wire o_cfg_stall, o_cfg_ack, - output wire [(DW-1):0] o_cfg_data, - // }}} - // Device - // {{{ - output reg o_qspi_sck, - output reg o_qspi_cs_n, - output reg [1:0] o_qspi_mod, - output wire [3:0] o_qspi_dat, - input wire [3:0] i_qspi_dat, - // }}} - // Debugging port - // {{{ - output wire o_dbg_trigger, - output wire [31:0] o_debug - // }}} - // }}} - ); - - // Local declarations - // {{{ - // OPT_ADDR32 enables 32 bit addressing, rather than 24bit - // {{{ - // Control this by controlling the LGFLASHSZ parameter above. - // Anything greater than 24 will use 32-bit addressing, - // otherwise the regular 24-bit addressing - localparam [0:0] OPT_ADDR32 = (LGFLASHSZ > 24); - // }}} - // OPT_ODDR will be true any time the clock has no clock division - // {{{ - localparam [0:0] OPT_ODDR = (OPT_CLKDIV == 0); - // }}} - // CKDV_BITS is the number of bits necessary to represent a - // {{{ - // counter that can do the CLKDIV division - localparam CKDV_BITS = (OPT_CLKDIV == 0) ? 0 - : ((OPT_CLKDIV < 2) ? 1 - : ((OPT_CLKDIV < 4) ? 2 - : ((OPT_CLKDIV < 8) ? 3 - : ((OPT_CLKDIV < 16) ? 4 - : ((OPT_CLKDIV < 32) ? 5 - : ((OPT_CLKDIV < 64) ? 6 - : ((OPT_CLKDIV < 128) ? 7 - : ((OPT_CLKDIV < 256) ? 8 : 9)))))))); - // }}} - localparam [4:0] CFG_MODE = 12; - localparam [4:0] QSPEED_BIT = 11; - // localparam [4:0] DSPEED_BIT = 10; // Unused in QSPI controller - localparam [4:0] DIR_BIT = 9; - localparam [4:0] USER_CS_n = 8; - // - localparam [1:0] NORMAL_SPI = 2'b00; - localparam [1:0] QUAD_WRITE = 2'b10; - localparam [1:0] QUAD_READ = 2'b11; - // Read commands are unused in this driver, since its based around - // XiP access - // {{{ - // localparam [7:0] DIO_READ_CMD = 8'hbb; - // localparam [7:0] QIO_READ_CMD = OPT_ADDR32 ? 8'hec : 8'heb; - // }}} - // -`ifdef FORMAL - localparam F_LGDEPTH=$clog2(3+RDDELAY+(OPT_ADDR32 ? 2:0)); - reg f_past_valid; -`endif - // - // - // Arbitrated bus registers and inputs - // - wire bus_cyc, bus_stb, bus_we, ign_wb_err, ign_cfg_err; - wire [(AW-1):0] bus_addr; - wire [31:0] bus_data; - wire [3:0] bus_sel; - reg bus_stall, bus_ack; - wire cfg_bus_stb, mem_bus_stb; - reg dly_ack, read_sck; - wire xtra_stall; - // clk_ctr must have enough bits for ... - // 6 address clocks, 4-bits each - // NDUMMY dummy clocks, including two mode bytes - // 8 data clocks - // (RDDELAY clocks not counted here) - reg [4:0] clk_ctr; - - // - // User override logic - // - reg cfg_mode, cfg_speed, cfg_dir, cfg_cs; - wire cfg_write, cfg_hs_write, cfg_ls_write, cfg_hs_read, - user_request, bus_request, pipe_req, cfg_noop, cfg_stb; - // - assign bus_request = (mem_bus_stb)&&(!bus_stall) - &&(!bus_we)&&(!cfg_mode); - assign cfg_stb = (OPT_CFG)&&(cfg_bus_stb)&&(!bus_stall); - assign cfg_noop = ((cfg_stb)&&((!bus_we)||(!i_cfg_data[CFG_MODE]) - ||(i_cfg_data[USER_CS_n]))) - ||((!OPT_CFG)&&(cfg_bus_stb)&&(!bus_stall)); - assign user_request = (cfg_stb)&&(i_cfg_we)&&(i_cfg_data[CFG_MODE]); - - assign cfg_write = (user_request)&&(!i_cfg_data[USER_CS_n]); - assign cfg_hs_write = (cfg_write)&&(i_cfg_data[QSPEED_BIT]) - &&(i_cfg_data[DIR_BIT]); - assign cfg_hs_read = (cfg_write)&&(i_cfg_data[QSPEED_BIT]) - &&(!i_cfg_data[DIR_BIT]); - assign cfg_ls_write = (cfg_write)&&(!i_cfg_data[QSPEED_BIT]); - - - reg ckstb, ckpos, ckneg, ckpre; - reg maintenance; - reg [1:0] m_mod; - reg m_cs_n; - reg m_clk; - reg [3:0] m_dat; - - reg [32+(OPT_ADDR32 ? 8:0)+4*(OPT_ODDR ? 0:1)-1:0] data_pipe; - reg pre_ack = 1'b0; - wire actual_sck; - - reg r_last_cfg; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Incoming bus arbiter - // {{{ - generate if (OPT_CFG) - begin : GEN_MEMCFG_ARBITER - // {{{ - wire cfg_bus_grant; - // - // Memory vs Configuration bus arbiter - // - wbarbiter #( - // {{{ - .DW(DW), .AW(AW+1), .SCHEME("PRIORITY") -`ifdef FORMAL - , .F_MAX_STALL(0), .F_MAX_ACK_DELAY(0) -`endif - // }}} - ) arbiter( - // {{{ - i_clk, i_reset, - i_wb_cyc, i_wb_stb, i_wb_we, { 1'b0, i_wb_addr }, - i_wb_data, i_wb_sel, - o_wb_stall, o_wb_ack, ign_wb_err, - i_cfg_cyc, i_cfg_stb, i_cfg_we, { 1'b1, i_wb_addr }, - i_cfg_data, i_cfg_sel, - o_cfg_stall, o_cfg_ack, ign_cfg_err, - bus_cyc, bus_stb, bus_we, { cfg_bus_grant, bus_addr }, bus_data, bus_sel, - bus_stall, bus_ack, 1'b0 - // }}} - ); - - assign cfg_bus_stb = bus_stb && cfg_bus_grant; - assign mem_bus_stb = bus_stb && !cfg_bus_grant; - assign o_cfg_data = o_wb_data; - - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, bus_data, bus_addr, ign_cfg_err, - ign_wb_err, r_last_cfg }; - // verilator lint_on UNUSED - // }}} - end else begin : NO_CFG_ARBITER - // {{{ - assign bus_cyc = i_wb_cyc; - assign bus_stb = i_wb_stb; - assign bus_we = i_wb_we; - assign bus_addr = i_wb_addr; - assign bus_data = i_wb_data; - assign bus_sel = i_wb_sel; - - assign o_wb_ack = bus_ack; - assign o_wb_stall = bus_stall; - - assign mem_bus_stb = bus_stb; - assign cfg_bus_stb = 0; - assign o_cfg_ack = i_cfg_stb; - assign o_cfg_stall = 0; - assign o_cfg_data = 0; - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // (Sub)Clock generation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_ODDR) - begin - // {{{ - always @(*) - begin - ckstb = 1'b1; - ckpos = 1'b1; - ckneg = 1'b1; - ckpre = 1'b1; - end - // }}} - end else if (OPT_CLKDIV == 1) - begin : CKSTB_ONE - // {{{ - reg clk_counter; - - initial clk_counter = 1'b1; - always @(posedge i_clk) - if (i_reset) - clk_counter <= 1'b1; - else if (clk_counter != 0) - clk_counter <= 1'b0; - else if (bus_request) - clk_counter <= (pipe_req); - else if ((maintenance)||(!o_qspi_cs_n && bus_stall)) - clk_counter <= 1'b1; - - always @(*) - begin - ckpre = (clk_counter == 1); - ckstb = (clk_counter == 0); - ckpos = (clk_counter == 1); - ckneg = (clk_counter == 0); - end - // }}} - end else begin : CKSTB_GEN - // {{{ - reg [CKDV_BITS-1:0] clk_counter; - - initial clk_counter = OPT_CLKDIV; - always @(posedge i_clk) - if (i_reset) - clk_counter <= OPT_CLKDIV; - else if (clk_counter != 0) - clk_counter <= clk_counter - 1; - else if (bus_request) - clk_counter <= (pipe_req ? OPT_CLKDIV : 0); - else if ((maintenance)||(!o_qspi_cs_n && bus_stall)) - clk_counter <= OPT_CLKDIV; - - initial ckpre = (OPT_CLKDIV == 1); - initial ckstb = 1'b0; - initial ckpos = (OPT_CLKDIV == 1); - always @(posedge i_clk) - if (i_reset) - begin - ckpre <= (OPT_CLKDIV == 1); - ckstb <= 1'b0; - ckpos <= (OPT_CLKDIV == 1); - end else // if (OPT_CLKDIV > 1) - begin - ckpre <= (clk_counter == 2); - ckstb <= (clk_counter == 1); - ckpos <= (clk_counter == (OPT_CLKDIV+1)/2+1); - end - - always @(*) - ckneg = ckstb; -`ifdef FORMAL - always @(*) - assert(!ckpos || !ckneg); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(ckpre))) - assert(ckstb); -`endif - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Maintenance / startup portion - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_STARTUP) - begin : GEN_STARTUP - localparam M_WAITBIT=10; - localparam M_LGADDR=5; -`ifdef FORMAL - // For formal, jump into the middle of the startup - localparam M_FIRSTIDX=9; -`else - localparam M_FIRSTIDX=0; -`endif - reg [M_WAITBIT:0] m_this_word; - reg [M_WAITBIT:0] m_cmd_word [0:(1< 3) - m_counter <= 3; -`endif - end - end else begin - m_midcount <= (m_counter > 1); - if (m_counter > 0) - m_counter <= m_counter - 1'b1; - end - - initial m_cs_n = 1'b1; - initial m_mod = NORMAL_SPI; - always @(posedge i_clk) - if (i_reset) - begin - m_cs_n <= 1'b1; - m_mod <= NORMAL_SPI; - m_bitcount <= 0; - end else if (ckstb) - begin - if (m_bitcount != 0) - m_bitcount <= m_bitcount - 1; - else if ((m_ce)&&(m_final)) - begin - m_cs_n <= 1'b1; - m_mod <= NORMAL_SPI; - m_bitcount <= 0; - end else if ((m_midcount)||(m_this_word[M_WAITBIT])) - begin - m_cs_n <= 1'b1; - m_mod <= NORMAL_SPI; - m_bitcount <= 0; - end else begin - m_cs_n <= 1'b0; - m_mod <= m_this_word[M_WAITBIT-1:M_WAITBIT-2]; - m_bitcount <= (!OPT_ODDR && m_cs_n) ? 4'h2 : 4'h1; - if (!m_this_word[M_WAITBIT-1]) - m_bitcount <= (!OPT_ODDR && m_cs_n) ? 4'h8 : 4'h7;//i.e.7 - end - end - - always @(posedge i_clk) - if (m_ce) - begin - if (m_bitcount == 0) - begin - if (!OPT_ODDR && m_cs_n) - begin - m_dat <= {(4){m_this_word[7]}}; - m_byte <= m_this_word[7:0]; - end else begin - m_dat <= m_this_word[7:4]; - m_byte <= { m_this_word[3:0], 4'h0}; - if (!m_this_word[M_WAITBIT-1]) - begin - // Slow speed - m_dat[0] <= m_this_word[7]; - m_byte <= { m_this_word[6:0], 1'b0 }; - end - end - end else begin - m_dat <= m_byte[7:4]; - m_byte <= { m_byte[3:0], 4'h0 }; - if (!m_mod[1]) - begin - // Slow speed - m_dat[0] <= m_byte[7]; - m_byte <= { m_byte[6:0], 1'b0 }; - end else begin - m_byte <= { m_byte[3:0], 4'b00 }; - end - end - end - - if (OPT_ODDR) - begin - always @(*) - m_clk = !m_cs_n; - end else begin - - always @(posedge i_clk) - if (i_reset) - m_clk <= 1'b1; - else if (m_cs_n) - m_clk <= 1'b1; - else if ((!m_clk)&&(ckpos)) - m_clk <= 1'b1; - else if (m_midcount) - m_clk <= 1'b1; - else if (new_word && m_this_word[M_WAITBIT]) - m_clk <= 1'b1; - else if (ckneg) - m_clk <= 1'b0; - end - -`ifdef FORMAL - // {{{ - (* anyconst *) reg [M_LGADDR:0] f_const_addr; - - always @(*) - begin - assert((m_cmd_word[f_const_addr][M_WAITBIT]) - ||(m_cmd_word[f_const_addr][M_WAITBIT-1:M_WAITBIT-2] != 2'b01)); - if (m_cmd_word[f_const_addr][M_WAITBIT]) - assert(m_cmd_word[f_const_addr][M_WAITBIT-3:0] > 0); - end - always @(*) - begin - if (m_cmd_index != f_const_addr) - assume((m_cmd_word[m_cmd_index][M_WAITBIT])||(m_cmd_word[m_cmd_index][M_WAITBIT-1:M_WAITBIT-2] != 2'b01)); - if (m_cmd_word[m_cmd_index][M_WAITBIT]) - assume(m_cmd_word[m_cmd_index][M_WAITBIT-3:0]>0); - end - - always @(*) - begin - assert((m_this_word[M_WAITBIT]) - ||(m_this_word[M_WAITBIT-1:M_WAITBIT-2] != 2'b01)); - if (m_this_word[M_WAITBIT]) - assert(m_this_word[M_WAITBIT-3:0] > 0); - end - - // Setting the last two command words to IDLE with maximum - // counts is required by our implementation - always @(*) - assert(m_cmd_word[5'h1e] == 11'h7ff); - always @(*) - assert(m_cmd_word[5'h1f] == 11'h7ff); - - wire [M_LGADDR-1:0] last_index; - assign last_index = m_cmd_index - 1; - - always @(posedge i_clk) - if ((f_past_valid)&&(m_cmd_index != M_FIRSTIDX)) - assert(m_this_word == m_cmd_word[last_index]); - - always @(posedge i_clk) - assert(m_midcount == (m_counter != 0)); - - reg [20:0] f_mpipe; - initial f_mpipe = 0; - always @(posedge i_clk) - if (i_reset) - f_mpipe <= 0; - else - f_mpipe <= { f_mpipe[19:0], (m_cmd_index == 5'h15) }; - - always @(posedge i_clk) - begin - cover(!maintenance); - cover(f_mpipe[3]); - cover(f_mpipe[4]); - cover(f_mpipe[5]); - cover(f_mpipe[6]); - cover(f_mpipe[7]); - cover(f_mpipe[8]); - cover(f_mpipe[9]); - cover(f_mpipe[10]); - cover(f_mpipe[11]); - cover(m_cmd_index == 5'h0a); - cover(m_cmd_index == 5'h0b); - cover(m_cmd_index == 5'h0c); - cover(m_cmd_index == 5'h0d); - cover(m_cmd_index == 5'h0e); - cover(m_cmd_index == 5'h0f); - cover(m_cmd_index == 5'h10); - cover(m_cmd_index == 5'h11); - cover(m_cmd_index == 5'h12); - cover(m_cmd_index == 5'h13); - cover(m_cmd_index == 5'h14); - cover(m_cmd_index == 5'h15); - cover(m_cmd_index == 5'h16); // @ 470 - cover(m_cmd_index == 5'h17); // @482 - cover(m_cmd_index == 5'h18); // @ 494 - cover(m_cmd_index == 5'h19); // @ 506 - cover(m_cmd_index == 5'h1a); // @ 518 - cover(m_cmd_index == 5'h1b); // @ 530 - cover(m_cmd_index == 5'h1c); // @ 542 - cover(m_cmd_index == 5'h1d); // @ 554 - cover(m_cmd_index == 5'h1e); // @ 572 - cover(m_cmd_index == 5'h1f); // @ 590 - // 602 - end - // }}} -`endif - end else begin : NO_STARTUP_OPT - - always @(*) - begin - maintenance = 0; - m_mod = 2'b00; - m_cs_n = 1'b1; - m_clk = 1'b0; - m_dat = 4'h0; - end - - // verilator lint_off UNUSED - wire [8:0] unused_maintenance; - assign unused_maintenance = { maintenance, - m_mod, m_cs_n, m_clk, m_dat }; - // verilator lint_on UNUSED - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Data / access portion - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // data_pipe - // {{{ - initial data_pipe = 0; - always @(posedge i_clk) - begin - if (!bus_stall) - begin - // Set the high bits to zero initially - data_pipe <= 0; - - data_pipe[8+LGFLASHSZ-1:0] <= { - i_wb_addr, 2'b00, 4'ha, 4'h0 }; - - if (cfg_bus_stb) - // High speed configuration I/O - data_pipe[24+(OPT_ADDR32 ? 8:0) +: 8] <= i_cfg_data[7:0]; - - if ((i_cfg_stb)&&(!i_cfg_data[QSPEED_BIT])) - begin // Low speed configuration I/O - data_pipe[28+(OPT_ADDR32 ? 8:0)] <= i_cfg_data[7]; - data_pipe[24+(OPT_ADDR32 ? 8:0)] <= i_cfg_data[6]; - end - - if (i_cfg_stb) - begin // These can be set independent of speed - data_pipe[20+(OPT_ADDR32 ? 8:0)] <= i_cfg_data[5]; - data_pipe[16+(OPT_ADDR32 ? 8:0)] <= i_cfg_data[4]; - data_pipe[12+(OPT_ADDR32 ? 8:0)] <= i_cfg_data[3]; - data_pipe[ 8+(OPT_ADDR32 ? 8:0)] <= i_cfg_data[2]; - data_pipe[ 4+(OPT_ADDR32 ? 8:0)] <= i_cfg_data[1]; - data_pipe[ 0+(OPT_ADDR32 ? 8:0)] <= i_cfg_data[0]; - end - end else if (ckstb) - data_pipe <= { data_pipe[(32+(OPT_ADDR32 ? 8:0)+4*((OPT_ODDR ? 0:1)-1))-1:0], 4'h0 }; - - if (maintenance) - data_pipe[28+(OPT_ADDR32 ? 8:0)+4*(OPT_ODDR ? 0:1) +: 4] <= m_dat; - end - // }}} - - assign o_qspi_dat = data_pipe[28+(OPT_ADDR32 ? 8:0)+4*(OPT_ODDR ? 0:1) +: 4]; - - // pre_ack - // {{{ - // Since we can't abort any transaction once started, without - // risking losing XIP mode or any other mode we might be in, we'll - // keep track of whether this operation should be ack'd upon - // completion - always @(posedge i_clk) - if ((i_reset)||(!bus_cyc)) - pre_ack <= 1'b0; - else if ((bus_request)||(cfg_write)) - pre_ack <= 1'b1; - // }}} - - // pipe_req - // {{{ - generate if (OPT_PIPE) - begin : OPT_PIPE_BLOCK - reg r_pipe_req; - wire w_pipe_condition; - - reg [(AW-1):0] next_addr; - always @(posedge i_clk) - if (!bus_stall) - next_addr <= i_wb_addr + 1'b1; - - assign w_pipe_condition = (mem_bus_stb) - &&(!i_wb_we)&&(pre_ack) - &&(!maintenance) - &&(!cfg_mode) - &&(!o_qspi_cs_n) - &&(|clk_ctr[2:0]) - &&(next_addr == i_wb_addr); - - initial r_pipe_req = 1'b0; - always @(posedge i_clk) - if ((clk_ctr == 1)&&(ckstb)) - r_pipe_req <= 1'b0; - else - r_pipe_req <= w_pipe_condition; - - assign pipe_req = r_pipe_req; - end else begin - assign pipe_req = 1'b0; - end endgenerate - // }}} - - // clk_ctr - // {{{ - initial clk_ctr = 0; - always @(posedge i_clk) - if ((i_reset)||(maintenance)) - clk_ctr <= 0; - else if ((bus_request)&&(!pipe_req)) - // Notice that this is only for - // regular bus reads, and so the check for - // !pipe_req - clk_ctr <= 5'd14 + NDUMMY + (OPT_ADDR32 ? 2:0)+(OPT_ODDR ? 0:1); - else if (bus_request) // && pipe_req - // Otherwise, if this is a piped read, we'll - // reset the counter back to eight. - clk_ctr <= 5'd8; - else if (cfg_ls_write) - clk_ctr <= 5'd8 + ((OPT_ODDR) ? 0:1); - else if (cfg_write) - clk_ctr <= 5'd2 + ((OPT_ODDR) ? 0:1); - else if ((ckstb)&&(|clk_ctr)) - clk_ctr <= clk_ctr - 1'b1; - // }}} - - // o_qspi_sck - // {{{ - initial o_qspi_sck = (!OPT_ODDR); - always @(posedge i_clk) - if (i_reset) - o_qspi_sck <= (!OPT_ODDR); - else if (maintenance) - o_qspi_sck <= m_clk; - else if ((!OPT_ODDR)&&(bus_request)&&(pipe_req)) - o_qspi_sck <= 1'b0; - else if ((bus_request)||(cfg_write)) - o_qspi_sck <= 1'b1; - else if (OPT_ODDR) - begin - if ((cfg_mode)&&(clk_ctr <= 1)) - // Config mode has no pipe instructions - o_qspi_sck <= 1'b0; - else if (clk_ctr[4:0] > 5'd1) - o_qspi_sck <= 1'b1; - else - o_qspi_sck <= 1'b0; - end else if (((ckpos)&&(!o_qspi_sck))||(o_qspi_cs_n)) - begin - o_qspi_sck <= 1'b1; - end else if ((ckneg)&&(o_qspi_sck)) begin - - if ((cfg_mode)&&(clk_ctr <= 1)) - // Config mode has no pipe instructions - o_qspi_sck <= 1'b1; - else if (clk_ctr[4:0] > 5'd1) - o_qspi_sck <= 1'b0; - else - o_qspi_sck <= 1'b1; - end - // }}} - - // o_qspi_cs_n - // {{{ - initial o_qspi_cs_n = 1'b1; - always @(posedge i_clk) - if (i_reset) - o_qspi_cs_n <= 1'b1; - else if (maintenance) - o_qspi_cs_n <= m_cs_n; - else if ((cfg_stb)&&(i_cfg_we)) - o_qspi_cs_n <= (!i_cfg_data[CFG_MODE])||(i_cfg_data[USER_CS_n]); - else if ((OPT_CFG)&&(cfg_cs)) - o_qspi_cs_n <= 1'b0; - else if ((bus_request)||(cfg_write)) - o_qspi_cs_n <= 1'b0; - else if (ckstb) - o_qspi_cs_n <= (clk_ctr <= 1); - // }}} - - // o_qspi_mod - // {{{ - // Control the mode of the external pins - // NORMAL_SPI: i_miso is an input, o_mosi is an output - // QUAD_READ: i_miso is an input, o_mosi is an input - // QUAD_WRITE: i_miso is an output, o_mosi is an output - initial o_qspi_mod = NORMAL_SPI; - always @(posedge i_clk) - if (i_reset) - o_qspi_mod <= NORMAL_SPI; - else if (maintenance) - o_qspi_mod <= m_mod; - else if ((bus_request)&&(!pipe_req)) - o_qspi_mod <= QUAD_WRITE; - else if ((bus_request)||(cfg_hs_read)) - o_qspi_mod <= QUAD_READ; - else if (cfg_hs_write) - o_qspi_mod <= QUAD_WRITE; - else if ((cfg_ls_write)||((cfg_mode)&&(!cfg_speed))) - o_qspi_mod <= NORMAL_SPI; - else if ((ckstb)&&(clk_ctr <= 5'd9)&&((!cfg_mode)||(!cfg_dir))) - o_qspi_mod <= QUAD_READ; - // }}} - - // bus_stall - // {{{ - initial bus_stall = 1'b1; - always @(posedge i_clk) - if (i_reset) - bus_stall <= 1'b1; - else if (maintenance) - bus_stall <= 1'b1; - else if ((RDDELAY > 0)&&(bus_stb)&&(!bus_stall)) - bus_stall <= 1'b1; - else if ((RDDELAY == 0)&&((cfg_write)||(bus_request))) - bus_stall <= 1'b1; - else if (ckstb || clk_ctr == 0) - begin - if (ckpre && (mem_bus_stb)&&(pipe_req)&&(clk_ctr == 5'd2)) - bus_stall <= 1'b0; - else if ((clk_ctr > 1)||(xtra_stall)) - bus_stall <= 1'b1; - else - bus_stall <= 1'b0; - end else if (ckpre && (mem_bus_stb)&&(pipe_req)&&(clk_ctr == 5'd1)) - bus_stall <= 1'b0; - // }}} - - // dly_ack - // {{{ - initial dly_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - dly_ack <= 1'b0; - else if ((ckstb)&&(clk_ctr == 1)) - dly_ack <= (bus_cyc)&&(pre_ack); - else if ((!cfg_bus_stb && bus_stb)&&(!bus_stall)&&(!bus_request)) - dly_ack <= 1'b1; - else if (cfg_noop) - dly_ack <= 1'b1; - else - dly_ack <= 1'b0; - // }}} - - // actual_sck - // {{{ - generate if (OPT_ODDR) - begin : SCK_ACTUAL - - assign actual_sck = o_qspi_sck; - - end else if (OPT_CLKDIV == 1) - begin : SCK_ONE - reg r_actual_sck; - - initial r_actual_sck = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_actual_sck <= 1'b0; - else - r_actual_sck <= (!o_qspi_sck)&&(clk_ctr > 0); - - assign actual_sck = r_actual_sck; - - end else begin : SCK_ANY - reg r_actual_sck; - - initial r_actual_sck = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_actual_sck <= 1'b0; - else - r_actual_sck <= (o_qspi_sck)&&(ckpre)&&(clk_ctr > 0); - - assign actual_sck = r_actual_sck; - - end endgenerate - // }}} - -`ifdef FORMAL - wire [F_LGDEPTH-1:0] f_extra; -`endif - - // read_sck, bus_ack, xtra_stall - // {{{ - generate if (RDDELAY == 0) - begin : RDDELAY_NONE - - always @(*) - begin - read_sck = actual_sck; - bus_ack = dly_ack; - end - - assign xtra_stall = 1'b0; -`ifdef FORMAL - assign f_extra = 0; -`endif - - end else - begin : RDDELAY_NONZERO - - reg [RDDELAY-1:0] sck_pipe, ack_pipe, stall_pipe; - reg not_done; - - initial sck_pipe = 0; - initial ack_pipe = 0; - initial stall_pipe = -1; - if (RDDELAY > 1) - begin - always @(posedge i_clk) - if (i_reset) - sck_pipe <= 0; - else - sck_pipe <= { sck_pipe[RDDELAY-2:0], actual_sck }; - - always @(posedge i_clk) - if (i_reset || !bus_cyc) - ack_pipe <= 0; - else - ack_pipe <= { ack_pipe[RDDELAY-2:0], dly_ack }; - - always @(posedge i_clk) - if (i_reset) - stall_pipe <= -1; - else - stall_pipe <= { stall_pipe[RDDELAY-2:0], not_done }; - - - end else begin - always @(posedge i_clk) - if (i_reset) - sck_pipe <= 0; - else - sck_pipe <= actual_sck; - - always @(posedge i_clk) - if (i_reset || !bus_cyc) - ack_pipe <= 0; - else - ack_pipe <= dly_ack; - - always @(posedge i_clk) - if (i_reset) - stall_pipe <= -1; - else - stall_pipe <= not_done; - end - - always @(*) - begin - not_done = bus_stb && !bus_stall; - if (clk_ctr > 1) - not_done = 1'b1; - if ((clk_ctr == 1)&&(!ckstb)) - not_done = 1'b1; - end - - always @(*) - bus_ack = ack_pipe[RDDELAY-1]; - - always @(*) - read_sck = sck_pipe[RDDELAY-1]; - - assign xtra_stall = |stall_pipe; - -`ifdef FORMAL - reg [F_LGDEPTH-1:0] fr_extra; - integer k; - always @(*) - if (!bus_cyc) - fr_extra = 0; - else begin - fr_extra = 0; - for(k=0; k 0) - begin - always @(posedge i_clk) - assume(i_qspi_dat == $past(dly_idat,RDDELAY)); - end else begin - always @(posedge i_clk) - assume(i_qspi_dat == dly_idat); - end endgenerate - - // - //////////////////////////////////////////////////////////////////////// - // - // Maintenance mode assertions - // - - always @(*) - if (maintenance) - begin - assume((!i_wb_stb)&&(!i_cfg_stb)); - - assert(f_outstanding == 0); - - assert(bus_stall); - // - assert(clk_ctr == 0); - assert(cfg_mode == 1'b0); - end - - always @(*) - if (maintenance) - begin - assert(clk_ctr == 0); - assert(!bus_ack); - end - - //////////////////////////////////////////////////////////////////////// - // - // - // - always @(posedge i_clk) - if (dly_ack) - assert(clk_ctr[2:0] == 0); - - // Zero cycle requests - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(($past(cfg_noop)) - ||($past(mem_bus_stb && bus_we && !bus_stall)))) - assert((dly_ack)&&((!bus_cyc) - ||(f_outstanding == 1 + f_extra))); - - always @(posedge i_clk) - if ((f_outstanding > 0)&&(clk_ctr > 0)) - assert(pre_ack); - - always @(posedge i_clk) - if ((bus_cyc)&&(dly_ack)) - assert(f_outstanding >= 1 + f_extra); - - always @(posedge i_clk) - if ((f_past_valid)&&(clk_ctr == 0)&&(!dly_ack) - &&($past(!bus_stb || bus_stall)))) - assert(f_outstanding == f_extra); - - always @(*) - if ((bus_cyc)&&(pre_ack)&&(!o_qspi_cs_n)) - assert((f_outstanding >= 1 + f_extra)||((OPT_CFG)&&(cfg_mode))); - - always @(*) - if ((cfg_mode)&&(!dly_ack)&&(clk_ctr == 0)) - assert(f_outstanding == f_extra); - - always @(*) - if (cfg_mode) - assert(f_outstanding <= 1 + f_extra); - - ///////////////// - // - // Idle channel - // - ///////////////// - always @(*) - if (!maintenance) - begin - if (o_qspi_cs_n) - begin - assert(clk_ctr == 0); - assert(o_qspi_sck == !OPT_ODDR); - end else if (clk_ctr == 0) - assert(o_qspi_sck == !OPT_ODDR); - end - - always @(*) - assert(o_qspi_mod != 2'b01); - - always @(*) - if (clk_ctr > (5'h8 * (1+OPT_CLKDIV))) - begin - assert(!cfg_mode); - assert(!cfg_cs); - end - - - always @(posedge i_clk) - if ((OPT_CLKDIV==1)&&(!o_qspi_cs_n)&&(!$past(o_qspi_cs_n)) - &&(!$past(o_qspi_cs_n,2))&&(!cfg_mode)) - assert(o_qspi_sck != $past(o_qspi_sck)); - - ///////////////// - // - // Read requests - // - ///////////////// - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&($past(bus_request))) - begin - assert(!o_qspi_cs_n); - if ((OPT_ODDR)||(!$past(pipe_req))) - assert(o_qspi_sck == 1'b1); - else - assert(o_qspi_sck == 1'b0); - // - if (!$past(o_qspi_cs_n)) - begin - assert(clk_ctr == 5'd8); - assert(o_qspi_mod == QUAD_READ); - end else begin - assert(clk_ctr == 5'd14 + NDUMMY - + (OPT_ADDR32 ? 2:0) + (OPT_ODDR ? 0:1)); - assert(o_qspi_mod == QUAD_WRITE); - end - end - - always @(*) - assert(clk_ctr <= 5'd18 + NDUMMY + (OPT_ODDR ? 0:1)); - - always @(*) - if ((OPT_ODDR)&&(!o_qspi_cs_n)) - assert((o_qspi_sck)||(actual_sck)||(cfg_mode)||(maintenance)); - - always @(*) - if ((RDDELAY == 0)&&((dly_ack)&&(clk_ctr == 0))) - assert(!bus_stall); - - always @(*) - if (!maintenance) - begin - if (cfg_mode) - begin - if (!cfg_cs) - assert(o_qspi_cs_n); - else if (!cfg_speed) - assert(o_qspi_mod == NORMAL_SPI); - else if ((cfg_dir)&&(clk_ctr > 0)) - assert(o_qspi_mod == QUAD_WRITE); - end else if (clk_ctr > 5'd8) - assert(o_qspi_mod == QUAD_WRITE); - else if (clk_ctr > 0) - assert(o_qspi_mod == QUAD_READ); - end - - always @(posedge i_clk) - if (((!OPT_PIPE)&&(clk_ctr != 0))||(clk_ctr > 5'd1)) - assert(bus_stall); - - always @(posedge i_clk) - if ((OPT_CLKDIV>0)&&($past(o_qspi_cs_n))) - assert(o_qspi_sck); - - ///////////////// - // - // User mode - // - ///////////////// - always @(*) - if ((maintenance)||(!OPT_CFG)) - assert(!cfg_mode); - always @(*) - if ((OPT_CFG)&&(cfg_mode)) - assert(o_qspi_cs_n == !cfg_cs); - else - assert(!cfg_cs); - - // - // - // - // - always @(posedge i_clk) - if (bus_request) - begin - // Make sure all of the bits are set - fv_addr <= 0; - // Now set as many bits as we have address bits - fv_addr[AW-1:0] <= i_wb_addr; - end - - always @(posedge i_clk) - if (cfg_bus_stb && !bus_stall && bus_we) - fv_data <= i_cfg_data; - - // Memory reads - - initial f_memread = 0; - generate if (RDDELAY == 0) - begin - - always @(posedge i_clk) - if (i_reset) - f_memread <= 0; - else begin - if (ckstb) - f_memread <= { f_memread[F_MEMACK-1:0],1'b0}; - else if (!OPT_ODDR) - f_memread[F_MEMACK] <= 1'b0; - if ((bus_request)&&(o_qspi_cs_n)) - f_memread[0] <= 1'b1; - end - end else begin - - always @(posedge i_clk) - if (i_reset) - f_memread <= 0; - else begin - if (ckstb) - f_memread <= { f_memread[F_MEMACK-1:0],1'b0}; - else if (!OPT_ODDR) - f_memread[F_MEMACK:F_MEMDONE] - <= { f_memread[F_MEMACK-1:F_MEMDONE],1'b0}; - if ((bus_request)&&(o_qspi_cs_n)) - f_memread[0] <= 1'b1; - end - end endgenerate - - always @(posedge i_clk) - if ((OPT_ODDR)&&(|f_memread[F_MEMDONE-1:0])) - assert(o_qspi_sck); - - always @(posedge i_clk) - if (|f_memread[6+(OPT_ADDR32 ? 2:0)+(OPT_ODDR ? 0:1):0]) - assert(o_qspi_mod == QUAD_WRITE); - else if (|f_memread[(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0) +7 +: NDUMMY]) - // begin assert(1); end - begin end - else if (|f_memread) - assert(o_qspi_mod == QUAD_READ); - - generate if (RDDELAY > 0) - begin - always @(posedge i_clk) - if ($past(ckpos,RDDELAY)) - begin - if ($past(o_qspi_mod,RDDELAY) == NORMAL_SPI) - f_past_data <= { f_past_data[31:0], i_qspi_dat[1] }; - else if ($past(o_qspi_mod,RDDELAY) == QUAD_READ) - f_past_data <= { f_past_data[28:0], i_qspi_dat[3:0] }; - end - end else begin - always @(posedge i_clk) - if (ckpos) - begin - if (o_qspi_mod == NORMAL_SPI) - f_past_data <= { f_past_data[31:0], i_qspi_dat[1] }; - else if (o_qspi_mod == QUAD_READ) - f_past_data <= { f_past_data[28:0], i_qspi_dat[3:0] }; - end - end endgenerate - - - always @(posedge i_clk) - if (|f_memread[(OPT_ODDR ? 0:1) +: 7 + (OPT_ADDR32 ? 2:0)]) - begin - if (OPT_ADDR32) - begin - // Eight extra bits of address - if (f_memread[(OPT_ODDR ? 0:1)]) - assert(o_qspi_dat== fv_addr[29:26]); - if (f_memread[1 + (OPT_ODDR ? 0:1)]) - assert(o_qspi_dat== fv_addr[25:22]); - end - // 6 nibbles of address, one nibble of mode - if (f_memread[(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) - assert(o_qspi_dat== fv_addr[21:18]); - if (f_memread[1+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) - assert(o_qspi_dat== fv_addr[17:14]); - if (f_memread[2+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) - assert(o_qspi_dat== fv_addr[13:10]); - if (f_memread[3+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) - assert(o_qspi_dat== fv_addr[ 9: 6]); - if (f_memread[4+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) - assert(o_qspi_dat== fv_addr[ 5: 2]); - if (f_memread[5+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) - assert(o_qspi_dat=={ fv_addr[1:0],2'b00 }); - if (f_memread[6+(OPT_ODDR ? 0:1)+(OPT_ADDR32 ? 2:0)]) - assert(o_qspi_dat == 4'ha); - end - - always @(posedge i_clk) - if (OPT_ODDR) - begin - if (f_memread[F_MEMACK] && OPT_ENDIANSWAP) - begin - assert(o_wb_data[ 7: 4] == $past(i_qspi_dat,8)); - assert(o_wb_data[ 3: 0] == $past(i_qspi_dat,7)); - assert(o_wb_data[15:12] == $past(i_qspi_dat,6)); - assert(o_wb_data[11: 8] == $past(i_qspi_dat,5)); - assert(o_wb_data[23:20] == $past(i_qspi_dat,4)); - assert(o_wb_data[19:16] == $past(i_qspi_dat,3)); - assert(o_wb_data[31:28] == $past(i_qspi_dat,2)); - assert(o_wb_data[27:24] == $past(i_qspi_dat,1)); - end else if (f_memread[F_MEMACK]) - begin - assert(o_wb_data[31:28] == $past(i_qspi_dat,8)); - assert(o_wb_data[27:24] == $past(i_qspi_dat,7)); - assert(o_wb_data[23:20] == $past(i_qspi_dat,6)); - assert(o_wb_data[19:16] == $past(i_qspi_dat,5)); - assert(o_wb_data[15:12] == $past(i_qspi_dat,4)); - assert(o_wb_data[11: 8] == $past(i_qspi_dat,3)); - assert(o_wb_data[ 7: 4] == $past(i_qspi_dat,2)); - assert(o_wb_data[ 3: 0] == $past(i_qspi_dat,1)); - end else if (|f_memread) - begin - if (!OPT_PIPE) - assert(bus_stall); - else if (!f_memread[F_MEMDONE-1]) - assert(bus_stall); - assert(!bus_ack); - end - end else if (f_memread[F_MEMACK] && OPT_ENDIANSWAP) - assert((!o_wb_ack)||( - o_wb_data[ 7: 0] == f_past_data[31:24] - && o_wb_data[15: 8] == f_past_data[23:16] - && o_wb_data[23:16] == f_past_data[15: 8] - && o_wb_data[31:24] == f_past_data[ 7: 0])); - else if (f_memread[F_MEMACK]) // 25 - assert((!bus_ack)||(o_wb_data == f_past_data[31:0])); - else if (|f_memread) - begin - if ((!OPT_PIPE)||(!ckstb)) - assert(bus_stall); - else if (!f_memread[F_MEMDONE-1]) - assert(bus_stall); - assert(!bus_ack); - end - - always @(posedge i_clk) - if (f_memread[F_MEMDONE]) - assert((clk_ctr == 0)||((OPT_PIPE)&&(clk_ctr == F_PIPEDONE))); - - generate for(k=0; k 0) - begin - - always @(posedge i_clk) - if (|f_cfghswrite[F_CFGHSACK:F_CFGHSDONE]) - assert(!actual_sck); - - end endgenerate - - always @(posedge i_clk) - if (|f_cfghswrite) - begin - assert(!o_qspi_cs_n); - assert(o_qspi_mod == QUAD_WRITE); - end - - always @(posedge i_clk) - if (|f_cfghswrite[1:0]) - begin - assert(!dly_ack); - assert(bus_stall); - end - - always @(posedge i_clk) - if (f_cfghswrite[F_CFGHSACK]) - begin - assert((bus_ack)||(!$past(pre_ack))||(!$past(bus_cyc))); - assert(o_qspi_mod == QUAD_WRITE); - assert(!bus_stall); - end else if (|f_cfghswrite) - begin - assert(bus_stall); - assert(!bus_ack); - end - - //////////////////////////////////////////////////////////////////////// - // - // High speed config read - // - initial f_cfghsread = 0; - always @(posedge i_clk) - if (i_reset) - f_cfghsread <= 0; - else begin - if (ckstb) - f_cfghsread <= { f_cfghsread[F_CFGHSACK-1:0], 1'b0 }; - else if (!OPT_ODDR) - f_cfghsread[F_CFGHSACK:F_CFGHSDONE] - <={f_cfghsread[F_CFGHSACK:F_CFGHSDONE], 1'b0}; - if (cfg_hs_read) - f_cfghsread[0] <= 1'b1; - end - - always @(*) - if (OPT_ODDR) - begin - if (|f_cfghsread[1:0]) - assert(o_qspi_sck); - else if (|f_cfghsread) - assert(!o_qspi_sck); - end - - always @(posedge i_clk) - if (|f_cfghsread[F_CFGHSACK:F_CFGHSDONE]) - assert(o_qspi_sck == !OPT_ODDR); - - always @(*) - if ((!maintenance)&&(o_qspi_cs_n)) - assert(!actual_sck); - - always @(posedge i_clk) - if (|f_cfghsread[F_CFGHSDONE-1:F_CFGHSDONE-2]) - begin - assert(!dly_ack); - assert(!o_qspi_cs_n); - assert(o_qspi_mod == QUAD_READ); - assert(bus_stall); - end - - generate if (RDDELAY > 0) - begin - - always @(posedge i_clk) - if (|f_cfghswrite[F_CFGHSACK:F_CFGHSDONE]) - assert(!actual_sck); - - end endgenerate - - - always @(posedge i_clk) - if (f_cfghsread[F_CFGHSACK]) - begin - if (OPT_ODDR) - begin - assert(o_cfg_data[7:4] == $past(i_qspi_dat[3:0],2)); - assert(o_cfg_data[3:0] == $past(i_qspi_dat[3:0],1)); - end - assert(o_cfg_data[7:0] == f_past_data[7:0]); - assert((bus_ack)||(!$past(pre_ack))||(!$past(i_cfg_cyc))); - assert(o_qspi_mod == QUAD_READ); - assert(!bus_stall); - end else if (|f_cfghsread) - begin - assert(bus_stall); - assert(!bus_ack); - end - - //////////////////////////////////////////////////////////////////////// - // - // Crossover checks - // - wire f_qspi_not_done, f_qspi_not_ackd, f_qspi_active, f_qspi_ack; - assign f_qspi_not_done = - (|f_memread[F_MEMDONE-1:0]) - ||(|f_piperead[F_PIPEDONE-1:0]) - ||(|f_cfglswrite[F_CFGLSDONE-1:0]) - ||(|f_cfghswrite[F_CFGHSDONE-1:0]) - ||(|f_cfghsread[F_CFGHSDONE-1:0]); - assign f_qspi_active = (!maintenance)&&( - (|f_memread[F_MEMACK-1:0]) - ||(|f_piperead[F_PIPEACK-1:0]) - ||(|f_cfglswrite[F_CFGLSACK-1:0]) - ||(|f_cfghswrite[F_CFGHSACK-1:0]) - ||(|f_cfghsread[F_CFGHSACK-1:0])); - assign f_qspi_not_ackd = (!maintenance)&&(!f_qspi_not_done)&&( - (|f_memread[F_MEMACK-1:0]) - ||(|f_piperead[F_PIPEACK-1:0]) - ||(|f_cfglswrite[F_CFGLSACK-1:0]) - ||(|f_cfghswrite[F_CFGHSACK-1:0]) - ||(|f_cfghsread[F_CFGHSACK-1:0])); - assign f_qspi_ack = (!maintenance)&& - (|f_memread[F_MEMACK:0]) - ||(|f_piperead[F_PIPEACK:0]) - ||(|f_cfglswrite[F_CFGLSACK:0]) - ||(|f_cfghswrite[F_CFGHSACK:0]) - ||(|f_cfghsread[F_CFGHSACK:0]); - - always @(*) - begin - if ((|f_memread[F_MEMDONE:0])||(|f_piperead[F_PIPEDONE:0])) - begin - assert(f_cfglswrite == 0); - assert(f_cfghswrite == 0); - assert(f_cfghsread == 0); - end - - if (|f_cfglswrite[F_CFGLSDONE:0]) - begin - assert(f_cfghswrite[F_CFGHSDONE:0] == 0); - assert(f_cfghsread[F_CFGHSDONE:0] == 0); - end - - if (|f_cfghswrite[F_CFGHSDONE:0]) - assert(f_cfghsread[F_CFGHSDONE:0] == 0); - - if (maintenance) - begin - assert(f_memread == 0); - assert(f_piperead == 0); - assert(f_cfglswrite == 0); - assert(f_cfghswrite == 0); - assert(f_cfghsread == 0); - end - - assert(clk_ctr <= F_MEMDONE); - end - - always @(posedge i_clk) - if ((f_past_valid)&&(!f_qspi_ack)&&(!$past(i_reset)) - &&(!$past(maintenance))) - begin - assert($stable(o_wb_data[7:0])); - if (!cfg_mode && !$past(cfg_mode) - && !$past(i_cfg_stb && !o_wb_stall) - &&($past(f_past_valid)) - && !$past(i_cfg_stb && !o_wb_stall,2)) - assert($stable(o_wb_data)); - end - - always @(*) - if (!maintenance && actual_sck) - begin - assert(f_qspi_not_done); - end - - always @(*) - if (!maintenance && !o_qspi_cs_n && !cfg_mode) - begin - assert((|f_memread[F_MEMDONE:0]) - ||(|f_piperead[F_PIPEDONE:0])); - end else if (!maintenance && cfg_mode) - begin - if ((o_qspi_sck == OPT_ODDR)||(clk_ctr > 0)||(actual_sck)) - begin - assert( (|f_cfglswrite[F_CFGLSDONE-1:0]) - ||(|f_cfghswrite[F_CFGHSDONE-1:0]) - ||(|f_cfghsread[F_CFGHSDONE-1:0])); - end - end - - always @(posedge i_clk) - if (bus_ack && !$past(bus_stb && !bus_stall, 1+RDDELAY)) - begin - assert(f_memread[F_MEMACK] - || f_piperead[F_PIPEACK] - || f_cfglswrite[F_CFGLSACK] - || f_cfghswrite[F_CFGHSACK] - || f_cfghsread[F_CFGHSACK]); - end - - - //////////////////////////////////////////////////////////////////////// - // - // Cover Properties - // - //////////////////////////////////////////////////////////////////////// - // - // Due to the way the chip starts up, requiring 32k+ maintenance clocks, - // these cover statements are not likely to be hit - - generate if (!OPT_STARTUP) - begin - // Why is this generate only if !OPT_STARTUP? For performance - // reasons. The startup sequence can take a great many clocks. - // cover() would never be able to work through all of those - // clocks to find the following examples, and so it would fail. - // By only checking these cover() statements if !OPT_STARTUP, - // we give them an opportunity to succeed - always @(posedge i_clk) - cover(o_wb_ack && f_memread[ F_MEMACK]); - - if (OPT_CFG) - begin - always @(posedge i_clk) - begin - cover(cfg_ls_write); - cover(cfg_hs_write); - cover(cfg_hs_read); - - cover(|f_cfglswrite); - cover(|f_cfghsread); - cover(|f_cfghswrite); - - cover(o_cfg_ack && |f_cfglswrite); - cover(o_cfg_ack && |f_cfghsread); - cover(o_cfg_ack && |f_cfghswrite); - - cover(f_cfglswrite[0]); - cover(f_cfghsread[ 0]); - cover(f_cfghswrite[0]); - - cover(f_cfglswrite[F_CFGLSACK-2]); - cover(f_cfghsread[ F_CFGHSACK-2]); - cover(f_cfghswrite[F_CFGHSACK-2]); - - cover(f_cfglswrite[F_CFGLSACK-1]); - cover(f_cfghsread[ F_CFGHSACK-1]); - cover(f_cfghswrite[F_CFGHSACK-1]); - - cover(f_cfglswrite[F_CFGLSACK]); - cover(f_cfghsread[ F_CFGHSACK]); - cover(f_cfghswrite[F_CFGHSACK]); - - cover(o_cfg_ack && f_cfglswrite[F_CFGLSACK]); - cover(o_cfg_ack && f_cfghsread[ F_CFGHSACK]); - cover(o_cfg_ack && f_cfghswrite[F_CFGHSACK]); - end - end - - if (OPT_PIPE) - begin - always @(posedge i_clk) - cover(bus_ack && f_piperead[F_PIPEACK]); - end - // - // - // - always @(posedge i_clk) - cover((bus_ack)&&(!cfg_mode)); - always @(posedge i_clk) - cover((bus_ack)&&(!cfg_mode)&&(!$past(o_qspi_cs_n))); - always @(posedge i_clk) - // Cover a piped transaction - cover((bus_ack)&&(!cfg_mode)&&(!o_qspi_cs_n)); //! - always @(posedge i_clk) - cover((bus_ack)&&(cfg_mode)&&(cfg_speed)); - always @(posedge i_clk) - cover((bus_ack)&&(cfg_mode)&&(!cfg_speed)&&(cfg_dir)); - always @(posedge i_clk) - cover((bus_ack)&&(cfg_mode)&&(!cfg_speed)&&(!cfg_dir)); - end else begin - - always @(posedge i_clk) - cover(!maintenance); - - end endgenerate - -`endif -// }}} -endmodule diff --git a/delete_later/rtl/sdspi/llsdspi.v b/delete_later/rtl/sdspi/llsdspi.v deleted file mode 100644 index 1467ee7..0000000 --- a/delete_later/rtl/sdspi/llsdspi.v +++ /dev/null @@ -1,1243 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: llsdspi.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This file implements the "lower-level" interface to the -// SD-Card controller. Specifically, it turns byte-level -// interaction requests into SPI bit-wise interactions. Further, it -// handles the request and grant for the SPI wires (i.e., it requests -// the SPI port by pulling o_cs_n low, and then waits for i_bus_grant -// to be true before continuing.). Finally, the speed/clock rate of the -// communication is adjustable as a division of the current clock rate. -// -// i_speed -// This is the number of clocks (minus one) between SPI clock -// transitions. Hence a '0' (not tested, doesn't work) would -// result in a SPI clock that alternated on every input clock -// equivalently dividing the input clock by two, whereas a '1' -// would divide the input clock by four. -// -// In general, the SPI clock frequency will be given by the -// master clock frequency divided by twice this number plus one. -// In other words, -// -// SPIFREQ=(i_clk FREQ) / (2*(i_speed+1)) -// -// i_stb -// True if the master controller is requesting to send a byte. -// This will be ignored unless o_idle is false. -// -// i_byte -// The byte that the master controller wishes to send across the -// interface. -// -// (The external SPI interface) -// -// o_stb -// Only true for one clock--when a byte is valid coming in from the -// interface, this will be true for one clock (a strobe) indicating -// that a valid byte is ready to be read. -// -// o_byte -// The value of the byte coming in. -// -// o_idle -// True if this low-level device handler is ready to accept a -// byte from the incoming interface, false otherwise. -// -// i_bus_grant -// True if the SPI bus has been granted to this interface, false -// otherwise. This has been placed here so that the interface of -// the XuLA2 board may be shared between SPI-Flash and the SPI -// based SDCard. An external arbiter will determine which of the -// two gets to control the clock and mosi outputs given their -// cs_n requests. If control is not granted, i_bus_grant will -// remain low as will the actual cs_n going out of the FPGA. -// -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module llsdspi #( - // {{{ - parameter SPDBITS = 7, - // Minimum startup clocks - STARTUP_CLOCKS = 150, - // System clocks to wait before the startup - // clock sequence - POWERUP_IDLE = 1000, - // - // This core was originally developed for a shared SPI bus - // implementation on a XuLA2-LX25 board--one that shared flash - // with the SD-card. Few cards support such an implementation - // any more, since per protocol CS high (inactive) and clock - // and data pins toggling could well put the SD card into it's - // SD mode instead of SPI mode. - parameter [0:0] OPT_SPI_ARBITRATION = 1'b0, - // - // - localparam [0:0] CSN_ON_STARTUP = 1'b1, - // - // The MOSI INACTIVE VALUE *MUST* be 1'b1 to be compliant - localparam [0:0] MOSI_INACTIVE_VALUE = 1'b1, - // - // Normally, an SPI transaction shuts the clock down when - // finished. If OPT_CONTINUOUS_CLOCK is set, the clock will be - // continuous. This also means that any driving program must - // be ready when the SDSPI is idle. - parameter [0:0] OPT_CONTINUOUS_CLOCK = 1'b0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Parameters/setup - input wire [(SPDBITS-1):0] i_speed, - // The incoming interface - input wire i_cs, - input wire i_stb, - input wire [7:0] i_byte, - // The actual SPI interface - output reg o_cs_n, o_sclk, o_mosi, - input wire i_miso, - // The outgoing interface - output reg o_stb, - output reg [7:0] o_byte, - output reg o_idle, - // And whether or not we actually own the interface (yet) - input wire i_bus_grant - // }}} - ); - - // Signal / localparam declarations - // {{{ - localparam [3:0] LLSDSPI_IDLE = 4'h0, - LLSDSPI_HOTIDLE = 4'h1, - LLSDSPI_WAIT = 4'h2, - LLSDSPI_START = 4'h3, - LLSDSPI_END = 4'hb; - // - reg r_z_counter; - reg [(SPDBITS-1):0] r_clk_counter; - reg r_idle; - reg [3:0] r_state; - reg [7:0] r_byte, r_ireg; - wire byte_accepted; - reg restart_counter; - - wire bus_grant; - reg startup_hold, powerup_hold; -`ifdef FORMAL - reg f_past_valid; -`endif - // }}} - - assign bus_grant = (OPT_SPI_ARBITRATION ? i_bus_grant : 1'b1); - - // Wait for power up - // {{{ - generate if (POWERUP_IDLE > 0) - begin : WAIT_FOR_POWERUP - // {{{ - localparam POWERUP_BITS = $clog2(POWERUP_IDLE); - reg [POWERUP_BITS-1:0] powerup_counter; - - initial powerup_counter = POWERUP_IDLE[POWERUP_BITS-1:0]; - initial powerup_hold = 1; - always @(posedge i_clk) - if (i_reset) - begin - powerup_counter <= POWERUP_IDLE; - powerup_hold <= 1; - end else if (powerup_hold) - begin - if (|powerup_counter) - powerup_counter <= powerup_counter - 1; - powerup_hold <= (powerup_counter > 0); - end - -`ifdef FORMAL - always @(*) - if (!f_past_valid) - assume(powerup_counter > 2); - always @(*) - if (powerup_counter > 0) - assert(powerup_hold); -`endif - // }}} - end else begin - - always @(*) - powerup_hold = 0; - end endgenerate - // }}} - - // Send a minimum number of start up clocks after power up - // {{{ - generate if (STARTUP_CLOCKS > 0) - begin : WAIT_FOR_STARTUP - // {{{ - localparam STARTUP_BITS = $clog2(STARTUP_CLOCKS); - reg [STARTUP_BITS-1:0] startup_counter; - - initial startup_counter = STARTUP_CLOCKS[STARTUP_BITS-1:0]; - initial startup_hold = 1; - always @(posedge i_clk) - if (i_reset || powerup_hold) - begin - startup_counter <= STARTUP_CLOCKS; - startup_hold <= 1; - end else if (startup_hold && r_z_counter && !o_sclk) - begin - if (|startup_counter) - startup_counter <= startup_counter - 1; - startup_hold <= (startup_counter > 0); - end - -`ifdef FORMAL - always @(*) - if (!f_past_valid) - assume(startup_counter > 1); - always @(*) - if (startup_counter > 0) - assert(startup_hold); -`endif - // }}} - end else begin - - always @(*) - startup_hold = 0; - - end endgenerate - // }}} - - assign byte_accepted = (i_stb)&&(o_idle); - -`ifdef FORMAL - // {{{ - always @(*) - if (powerup_hold) - assert(startup_hold); - // }}} -`endif - //////////////////////////////////////////////////////////////////////// - // - // Clock divider and speed control - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial r_clk_counter = 0; - initial r_z_counter = 1'b1; - - // restart_counter - // {{{ - always @(*) - if (OPT_CONTINUOUS_CLOCK || powerup_hold) - restart_counter = !powerup_hold; - else begin - restart_counter = 1'b0; - - if (startup_hold || !i_cs) - restart_counter = 1'b1; - else if (!OPT_SPI_ARBITRATION && byte_accepted) - restart_counter = 1'b1; - else if (OPT_SPI_ARBITRATION && r_state == LLSDSPI_IDLE) - restart_counter = 1'b0; - else if (OPT_SPI_ARBITRATION && r_state == LLSDSPI_WAIT - && !bus_grant) - restart_counter = 1'b0; - else if (OPT_SPI_ARBITRATION && byte_accepted) - restart_counter = 1'b1; - else - restart_counter = !r_idle; - end - // }}} - - // r_clk_counter, r_z_counter - // {{{ - always @(posedge i_clk) - begin - if (!r_z_counter) - begin - r_clk_counter <= (r_clk_counter - 1); - r_z_counter <= (r_clk_counter == 1); - end else if (restart_counter) - begin - r_clk_counter <= i_speed; - r_z_counter <= (i_speed == 0); - end - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Control o_stb, o_cs_n, and o_mosi - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // o_cs_n, r_state - // {{{ - initial o_cs_n = CSN_ON_STARTUP; - initial r_state = LLSDSPI_IDLE; - always @(posedge i_clk) - if (i_reset || (!CSN_ON_STARTUP && startup_hold)) - begin - o_cs_n <= CSN_ON_STARTUP; - r_state <= LLSDSPI_IDLE; - end else if (r_z_counter) - begin - if (!i_cs) - begin - // No request for action. If anything, a request - // to close up/seal up the bus for the next transaction - // Expect to lose arbitration here. - r_state <= LLSDSPI_IDLE; - o_cs_n <= 1'b1; - end else if (r_state == LLSDSPI_IDLE) - begin - if (byte_accepted) - begin - o_cs_n <= 1'b0; - if (OPT_SPI_ARBITRATION) - // Wait for arbitration - r_state <= LLSDSPI_WAIT; - else - r_state <= LLSDSPI_START + (OPT_CONTINUOUS_CLOCK ? 1:0); - end - end else if (r_state == LLSDSPI_WAIT) - begin - if (bus_grant) - r_state <= LLSDSPI_START; - end else if (byte_accepted) - r_state <= LLSDSPI_START+1; - else if (o_sclk && r_state >= LLSDSPI_START) - begin - r_state <= r_state + 1; - if (r_state >= LLSDSPI_END) - r_state <= LLSDSPI_HOTIDLE; - end - - if (startup_hold) - o_cs_n <= 1; - end - // }}} - - // r_ireg - // {{{ - always @(posedge i_clk) - if (r_z_counter && !o_sclk) - r_ireg <= { r_ireg[6:0], i_miso }; - // }}} - - // o_byte - // {{{ - always @(posedge i_clk) - if (r_z_counter && o_sclk && r_state == LLSDSPI_END) - o_byte <= r_ireg; - // }}} - - // r_idle - // {{{ - initial r_idle = 0; - always @(posedge i_clk) - if (startup_hold || i_reset) - r_idle <= 0; - else if (r_z_counter) - begin - if (byte_accepted) - r_idle <= 1'b0; - else if ((r_state == LLSDSPI_END) - ||(r_state == LLSDSPI_HOTIDLE)) - r_idle <= 1'b1; - else if (r_state == LLSDSPI_IDLE) - r_idle <= 1'b1; - else - r_idle <= 1'b0; - end - // }}} - - // o_sclk - // {{{ - initial o_sclk = 1; - always @(posedge i_clk) - if (i_reset) - o_sclk <= 1; - else if (r_z_counter) - begin - if (OPT_CONTINUOUS_CLOCK) - o_sclk <= !o_sclk; - else if (restart_counter - && (startup_hold || (i_cs && !o_cs_n) || !o_sclk)) - o_sclk <= (r_state == LLSDSPI_WAIT) || !o_sclk; - end - // }}} - - // r_byte, o_mosi - // {{{ - initial r_byte = -1; - initial o_mosi = MOSI_INACTIVE_VALUE; - always @(posedge i_clk) - if (i_reset) - begin - r_byte <= {(8){MOSI_INACTIVE_VALUE}}; - o_mosi <= MOSI_INACTIVE_VALUE; - end else if (r_z_counter) - begin - if (byte_accepted) - begin - o_mosi <= MOSI_INACTIVE_VALUE; - if (o_cs_n && !OPT_CONTINUOUS_CLOCK) - r_byte <= i_byte[7:0]; - else begin - r_byte <= { i_byte[6:0], MOSI_INACTIVE_VALUE }; - o_mosi <= i_byte[7]; - end - end else if (o_sclk && (!OPT_SPI_ARBITRATION - || (bus_grant && r_state != LLSDSPI_WAIT))) - begin - r_byte <= { r_byte[6:0], MOSI_INACTIVE_VALUE }; - if (r_state >= LLSDSPI_START && r_state < LLSDSPI_END) - o_mosi <= r_byte[7]; - else if (!i_cs) - o_mosi <= MOSI_INACTIVE_VALUE; - end - end - // }}} - - // o_stb - // {{{ - initial o_stb = 1'b0; - always @(posedge i_clk) - if (i_reset || startup_hold || !i_cs || !r_z_counter || !o_sclk) - o_stb <= 1'b0; - else - o_stb <= (r_state >= LLSDSPI_END); - // }}} - - // o_idle - // {{{ - always @(*) - begin - if (OPT_CONTINUOUS_CLOCK) - o_idle = (r_idle)&&(r_z_counter)&&(o_sclk); - else - o_idle = (r_idle)&&(r_z_counter); - end - // }}} - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`ifdef LLSDSPI -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg [7:0] fv_byte; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - //////////////////////////////////////////////////////////////////////// - // - // Clock division logic (checks) - //////////////////////////////////////////////////////////////////////// - // - // - (* anyconst *) reg constant_speed; - - always @(posedge i_clk) - if (constant_speed) - begin - assume($stable(i_speed)); - assert(r_clk_counter <= i_speed); - end - - always @(posedge i_clk) - if (f_past_valid && $past(r_clk_counter != 0)) - assert(r_clk_counter == $past(r_clk_counter - 1)); - else if (f_past_valid) - assert((r_clk_counter == 0)||(r_clk_counter == $past(i_speed))); - - // - // And assumptions - // - always @(posedge i_clk) - if (f_past_valid && (i_cs || !r_z_counter)) - assume($stable(i_speed)); - - //////////////////////////////////////////////////////////////////////// - // - // Interface assumptions - // - always @(*) - if (i_stb) - `ASSUME(i_cs); - - always @(posedge i_clk) - if (f_past_valid && $past(i_stb && !o_idle)) - begin - if ($past(i_reset || !i_cs)) - `ASSUME(!i_stb); - // else - // `ASSUME(i_stb); - if ($past(f_past_valid)&&(!$past(o_idle,2))) - `ASSUME($stable(i_byte)); - end else if (f_past_valid && $past(i_cs && !o_idle && !i_reset)) - `ASSUME(i_cs); - // assume(i_cs); - - always @(posedge i_clk) - if (!f_past_valid) - assert(o_cs_n == CSN_ON_STARTUP); - else if ($past(bus_grant && !o_cs_n)) - `ASSUME(bus_grant); - else if ($past(!bus_grant && o_cs_n)) - `ASSUME(!bus_grant); - - always @(*) - if (r_state == LLSDSPI_IDLE) - assert(!CSN_ON_STARTUP || o_cs_n); - else - assert(!o_cs_n); - - - always @(posedge i_clk) - if (f_past_valid && CSN_ON_STARTUP && $past(r_state == LLSDSPI_IDLE) - && $past(!i_reset) - && r_state == LLSDSPI_IDLE) - assert(o_cs_n); - - always @(*) - if (r_state == LLSDSPI_WAIT) - assert(!o_cs_n && o_sclk); - else - assert(o_cs_n || bus_grant); - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && i_cs && !o_cs_n && !bus_grant)) - assert(!o_cs_n && o_sclk); - - always @(posedge i_clk) - if ($past(!o_cs_n && bus_grant) && (!o_cs_n && bus_grant)) - begin - if (!$fell(o_sclk)) - assume($stable(i_miso)); - - cover($changed(i_miso)); - end - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - `ASSUME(!i_stb); - `ASSUME(!i_cs); - end - - //////////////////////////////////////////////////////////////////////// - // - // Reset checks - // - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - assert(startup_hold); - assert(o_cs_n == CSN_ON_STARTUP); - assert(o_sclk); - end - - //////////////////////////////////////////////////////////////////////// - // - // Send byte sequences: from nothing, and from the last byte - // - //////////////////////////////////////////////////////////////////////// - // - // - reg [17:0] f_start_seq; - reg [16:0] f_next_seq; - - always @(*) - assert(r_z_counter == (r_clk_counter == 0)); - - always @(posedge i_clk) - if (byte_accepted) - fv_byte <= i_byte; - - always @(posedge i_clk) - assert(r_state <= LLSDSPI_END); - - initial f_start_seq = 0; - always @(posedge i_clk) - if (i_reset || !i_cs) - f_start_seq <= 0; - else if (f_start_seq == 0) - begin - if (OPT_SPI_ARBITRATION) - begin - if (r_state == LLSDSPI_IDLE && byte_accepted) - begin - // if (!o_cs_n && bus_grant) - // f_start_seq <= (f_next_seq == 0); - // //r_start_seq <= (!o_cs_n && bus_grant) ? 1:0; - end else if (r_state == LLSDSPI_WAIT && r_z_counter) - f_start_seq <= (bus_grant ? 1:0); - end else if (byte_accepted) - begin - if (OPT_CONTINUOUS_CLOCK) - f_start_seq <= (f_next_seq == 0) ? 2:0; - else - f_start_seq <= (f_next_seq == 0); - end - end else if (r_z_counter) - begin - f_start_seq <= f_start_seq << 1; - if (byte_accepted) - begin - f_start_seq[17] <= 0; - f_start_seq[16] <= 0; - end else if (f_start_seq[17]) - f_start_seq[17] <= 1; - end - - always @(*) - if (!OPT_SPI_ARBITRATION) - assert(r_state != LLSDSPI_WAIT); - - always @(*) - if (r_state == LLSDSPI_WAIT) - begin - // assert(o_mosi == fv_byte[7]); - assert(r_byte == fv_byte[7:0]); - assert(o_sclk); - assert(!o_stb); - assert(f_start_seq == 0); - assert(f_next_seq == 0); - assert(!r_idle); - assert(r_z_counter); - end - - always @(*) - if (|(f_start_seq & {(8){2'b01}})) - assert(o_sclk); - else if (|(f_start_seq & {(8){2'b10}})) - assert(!o_sclk); - - generate if (!OPT_CONTINUOUS_CLOCK) - begin - always @(*) - if (f_start_seq[17:0] == 18'h001) - cover(r_state == LLSDSPI_START); - end endgenerate - - always @(*) - case(f_start_seq[17:0]) - 18'h001: begin - assert(o_sclk); - assert(r_byte == fv_byte[7:0] ); - assert(r_state == LLSDSPI_START); - // assert(o_mosi == fv_byte[7]); - assert(!OPT_CONTINUOUS_CLOCK); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h002: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[6:0], {(1){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+1); - assert(o_mosi == fv_byte[7]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h004: begin - assert(o_sclk); - assert(r_byte == { fv_byte[6:0], {(1){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+1); - assert(o_mosi == fv_byte[7]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h008: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[5:0], {(2){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+2); - assert(o_mosi == fv_byte[6]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h010: begin - assert(o_sclk); - assert(r_byte == { fv_byte[5:0], {(2){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+2); - assert(o_mosi == fv_byte[6]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h020: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[4:0], {(3){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+3); - assert(o_mosi == fv_byte[5]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h040: begin - assert(o_sclk); - assert(r_byte == { fv_byte[4:0], {(3){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+3); - assert(o_mosi == fv_byte[5]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h080: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[3:0], {(4){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+4); - assert(o_mosi == fv_byte[4]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h100: begin - assert(o_sclk); - assert(r_byte == { fv_byte[3:0], {(4){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+4); - assert(o_mosi == fv_byte[4]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h00200: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[2:0], {(5){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+5); - assert(o_mosi == fv_byte[3]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h00400: begin - assert(o_sclk); - assert(r_byte == { fv_byte[2:0], {(5){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+5); - assert(o_mosi == fv_byte[3]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h00800: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[1:0], {(6){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+6); - assert(o_mosi == fv_byte[2]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h01000: begin - assert(o_sclk); - assert(r_byte == { fv_byte[1:0], {(6){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+6); - assert(o_mosi == fv_byte[2]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h02000: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[0], {(7){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+7); - assert(o_mosi == fv_byte[1]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h04000: begin - assert(o_sclk); - assert(r_byte == { fv_byte[0], {(7){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+7); - assert(o_mosi == fv_byte[1]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h08000: begin - assert(!o_sclk); - assert(r_byte == { {(8){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_END); - assert(o_mosi == fv_byte[0]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h10000: begin - assert(o_sclk); - assert(r_byte == { {(8){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_END); - assert(o_mosi == fv_byte[0]); - assert(!o_cs_n); - assert(r_idle); - end - 18'h20000: begin - assert(o_sclk); - assert(r_state == LLSDSPI_HOTIDLE); - assert(r_idle); - end - default: assert(f_start_seq == 0); - endcase - - always @(*) - if (|f_start_seq[16:1]) - begin - assert(!o_cs_n); - assert(bus_grant); - end - - initial f_next_seq = 0; - always @(posedge i_clk) - if (i_reset || !i_cs) - f_next_seq <= 0; - else if ((|f_start_seq[17:16]) && byte_accepted) - f_next_seq <= 1; - else if ((|f_next_seq[16:15]) && byte_accepted) - f_next_seq <= 1; - else if (r_z_counter) - begin - f_next_seq <= f_next_seq << 1; - // if (i_stb) - // f_next_seq[16] <= 0; - // else - if (f_next_seq[16]) - f_next_seq[16] <= 1; - end - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && !$fell(o_sclk) && !o_cs_n) - assert($stable(o_mosi)); - - always @(*) - if (|(f_next_seq & {(8){2'b10}})) - assert(o_sclk); - else if (|(f_next_seq & {(8){2'b01}})) - assert(!o_sclk); - - always @(*) - case(f_next_seq[16:0]) - 17'h001: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[6:0], {(1){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+1); - assert(o_mosi == fv_byte[7]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h002: begin - assert(o_sclk); - assert(r_byte == { fv_byte[6:0], {(1){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+1); - assert(o_mosi == fv_byte[7]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h004: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[5:0], {(2){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+2); - assert(o_mosi == fv_byte[6]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h008: begin - assert(o_sclk); - assert(r_byte == { fv_byte[5:0], {(2){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+2); - assert(o_mosi == fv_byte[6]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h010: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[4:0], {(3){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+3); - assert(o_mosi == fv_byte[5]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h020: begin - assert(o_sclk); - assert(r_byte == { fv_byte[4:0], {(3){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+3); - assert(o_mosi == fv_byte[5]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h040: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[3:0], {(4){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+4); - assert(o_mosi == fv_byte[4]); - assert(!o_cs_n); - assert(!r_idle); - end - 18'h080: begin - assert(o_sclk); - assert(r_byte == { fv_byte[3:0], {(4){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+4); - assert(o_mosi == fv_byte[4]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h100: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[2:0], {(5){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+5); - assert(o_mosi == fv_byte[3]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h200: begin - assert(o_sclk); - assert(r_byte == { fv_byte[2:0], {(5){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+5); - assert(o_mosi == fv_byte[3]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h400: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[1:0], {(6){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+6); - assert(o_mosi == fv_byte[2]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h0800: begin - assert(o_sclk); - assert(r_byte == { fv_byte[1:0], {(6){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+6); - assert(o_mosi == fv_byte[2]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h1000: begin - assert(!o_sclk); - assert(r_byte == { fv_byte[0], {(7){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+7); - assert(o_mosi == fv_byte[1]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h2000: begin - assert(o_sclk); - assert(r_byte == { fv_byte[0], {(7){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_START+7); - assert(o_mosi == fv_byte[1]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h4000: begin - assert(!o_sclk); - assert(r_byte == { {(8){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_END); - assert(o_mosi == fv_byte[0]); - assert(!o_cs_n); - assert(!r_idle); - end - 17'h8000: begin - assert(o_sclk); - assert(r_byte == { {(8){MOSI_INACTIVE_VALUE}} }); - assert(r_state == LLSDSPI_END); - assert(o_mosi == fv_byte[0]); - assert(!o_cs_n); - assert(r_idle); - end - 17'h10000: begin - assert(o_sclk); - assert(!o_cs_n); - assert(r_state == LLSDSPI_HOTIDLE); - assert(r_idle); - end - default: assert(f_next_seq == 0); - endcase - - always @(*) - if (f_next_seq != 0) - assert(f_start_seq == 0); - - always @(*) - if (r_state != LLSDSPI_IDLE) - assert(({ 1'b0, f_next_seq } | f_start_seq) - ||(OPT_SPI_ARBITRATION && r_state == LLSDSPI_WAIT)); - - always @(*) - if ((f_start_seq==0) && (f_next_seq == 0)) - assert((r_state == LLSDSPI_IDLE) - ||(OPT_SPI_ARBITRATION && r_state == LLSDSPI_WAIT)); - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && $changed({ o_sclk, o_mosi })) - begin - if ($past(i_cs)) - begin - assert(r_z_counter == $past(i_speed == 0)); - assert(r_clk_counter == $past(i_speed)); - end - end - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && !$past(r_z_counter)) - begin - assert($stable(o_cs_n)); - assert($stable(o_sclk)); - assert($stable(o_mosi)); - end - - //////////////////////////////////////////////////////////////////////// - // - // Verify the receiver - // - (* anyseq *) reg [7:0] f_rxdata; - - always @(posedge i_clk) - if (!$past(byte_accepted)) - assume($stable(f_rxdata)); - - always @(*) - case(f_start_seq[17:0] | { f_next_seq, 1'b0 }) - 18'h001: begin - end - 18'h002: begin - assume(i_miso == f_rxdata[7]); - end - 18'h004: begin - // assume(i_miso == f_rxdata[7]); - assert(r_ireg[0] == f_rxdata[7]); - end - 18'h008: begin - // assume(i_miso == f_rxdata[6]); - assert(r_ireg[0] == f_rxdata[7]); - end - 18'h010: begin - assume(i_miso == f_rxdata[6]); - assert(r_ireg[1:0] == f_rxdata[7:6]); - end - 18'h020: begin - assume(i_miso == f_rxdata[5]); - assert(r_ireg[1:0] == f_rxdata[7:6]); - end - 18'h040: begin - assume(i_miso == f_rxdata[5]); - assert(r_ireg[2:0] == f_rxdata[7:5]); - end - 18'h080: begin - assume(i_miso == f_rxdata[4]); - assert(r_ireg[2:0] == f_rxdata[7:5]); - end - 18'h100: begin - assume(i_miso == f_rxdata[4]); - assert(r_ireg[3:0] == f_rxdata[7:4]); - end - 18'h200: begin - assume(i_miso == f_rxdata[3]); - assert(r_ireg[3:0] == f_rxdata[7:4]); - end - 18'h400: begin - assume(i_miso == f_rxdata[3]); - assert(r_ireg[4:0] == f_rxdata[7:3]); - end - 18'h800: begin - assume(i_miso == f_rxdata[2]); - assert(r_ireg[4:0] == f_rxdata[7:3]); - end - 18'h1000: begin - assume(i_miso == f_rxdata[2]); - assert(r_ireg[5:0] == f_rxdata[7:2]); - end - 18'h2000: begin - assume(i_miso == f_rxdata[1]); - assert(r_ireg[5:0] == f_rxdata[7:2]); - end - 18'h4000: begin - assume(i_miso == f_rxdata[1]); - assert(r_ireg[6:0] == f_rxdata[7:1]); - end - 18'h8000: begin - assume(i_miso == f_rxdata[0]); - assert(r_ireg[6:0] == f_rxdata[7:1]); - end - 18'h10000: begin - assume(i_miso == f_rxdata[0]); - assert(r_ireg == f_rxdata); - end - 18'h20000: begin - assume(i_miso == f_rxdata[0]); - assert(r_ireg == f_rxdata); - assert(o_byte == f_rxdata); - end - endcase - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assert(!o_stb); - else if ($past(i_cs)) - begin - if ($fell(f_start_seq[16])) - assert(o_stb); - else if ($fell(f_next_seq[15])) - assert(o_stb); - else - assert(!o_stb); - end else - assert(!o_stb); - - always @(posedge i_clk) - if (o_cs_n || ((f_start_seq == 0) &&(f_next_seq == 0))) - assert(o_mosi == MOSI_INACTIVE_VALUE); - - always @(*) - if (!f_past_valid) - begin - if (STARTUP_CLOCKS > 0) - `ASSUME(startup_hold); - assert(r_z_counter); - assert(!r_idle); - assert(o_cs_n == CSN_ON_STARTUP); - assert(o_sclk); - end - - always @(*) - if (r_state == LLSDSPI_WAIT) - assert(o_sclk && !o_cs_n); - - always @(*) - if (!OPT_CONTINUOUS_CLOCK && o_cs_n && r_idle) - assert(o_sclk); - - always @(*) - if (startup_hold) - assert(o_cs_n == CSN_ON_STARTUP); - else if (!OPT_CONTINUOUS_CLOCK && o_cs_n) - assert(o_sclk); - - -`ifdef VERIFIC - always @(*) - assert($onehot0(f_next_seq)); - always @(*) - assert($onehot0(f_start_seq)); -`endif - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // -`ifdef LLSDSPI - (* anyconst *) reg nonzero_speed; - - reg [2:0] byte_count; - - always @(posedge i_clk) - if (i_reset || !i_cs) - byte_count <= 0; - else if (i_stb && !o_idle && (!(&byte_count))) - byte_count <= byte_count + 1; - - always @(posedge i_clk) - if (f_past_valid) - begin - cover(byte_count == 2 && !o_cs_n && nonzero_speed); - cover(byte_count == 2 && !o_cs_n && !nonzero_speed); - - /* - if (nonzero_speed) - begin - assume(i_speed > 0); - cover($rose(r_state == LLSDSPI_IDLE)&&($past(i_cs,2))); - cover($past(f_next_seq[16]) - && r_state == LLSDSPI_IDLE && (!i_cs)); - cover($past(f_next_seq[16]) && f_next_seq[0]); - end else begin - cover($rose(r_state == LLSDSPI_IDLE)&&($past(i_cs,2))); - cover($past(f_next_seq[16]) - && r_state == LLSDSPI_IDLE && (!i_cs)); - cover($past(f_next_seq[16]) && f_next_seq[0]); - end - */ - - cover(o_stb && o_byte == 8'haa && $changed(o_byte)); - cover(o_stb && o_byte == 8'h55 && $changed(o_byte)); - end - - generate if (OPT_CONTINUOUS_CLOCK) - begin - always @(*) - begin - cover(f_next_seq == 2); - cover(f_start_seq[3]); - cover(f_next_seq[15]); - // cover(f_next_seq[16]); // Won't happen anymore - end - end else begin - always @(*) - cover(f_next_seq == 1); - end endgenerate -`endif - //////////////////////////////////////////////////////////////////////// - // - // "Careless" constraining assumptions - // - always @(posedge i_clk) - if (f_past_valid) - begin - if ($past(i_stb && !i_reset)) - `ASSUME(i_cs); - end - - always @(*) - if (!CSN_ON_STARTUP && r_state == 0 && !o_cs_n) - assume(!i_cs); - - always @(posedge i_clk) - if (OPT_CONTINUOUS_CLOCK) - begin - // if ($past(i_cs && !i_stb)) - // assume(!i_stb); - assume(i_stb == i_cs); - - if (!o_sclk && r_state == LLSDSPI_IDLE) - assume(!i_stb); - end - -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/sdspi/sdckgen.v b/delete_later/rtl/sdspi/sdckgen.v deleted file mode 100644 index ccfb819..0000000 --- a/delete_later/rtl/sdspi/sdckgen.v +++ /dev/null @@ -1,257 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sdckgen.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Generate a digitally divided pre-serdes clock. The serdes this -// will feed is an 8:1 serdes. Hence, we generate 8 outputs per -// clock period. This allows us to generate a clock with a 90 degree -// offset, without needing to actually offset the clock by 90 degrees. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module sdckgen #( - // {{{ - // To hit 100kHz from a 100MHz clock, we'll need to divide by - // 4, and then by another 250. Hence, we'll need Lg(256)-2 - // bits. (The first three are special) - localparam LGMAXDIV = 8 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire i_cfg_clk90, - input wire [LGMAXDIV-1:0] i_cfg_ckspd, - input wire i_cfg_shutdown, - // - output reg o_ckstb, - output reg o_hlfck, - output reg [7:0] o_ckwide, - output reg [LGMAXDIV-1:0] o_ckspd - // }}} - ); - - // Local declarations - // {{{ - localparam NCTR = LGMAXDIV+2; - reg nxt_stb, nxt_clk; - reg [NCTR-1:0] nxt_counter, counter; - reg clk90; - reg [LGMAXDIV-1:0] ckspd; - wire w_clk90; - wire [LGMAXDIV-1:0] w_ckspd; - // }}} - - // nxt_stb, nxt_clk, nxt_counter - // {{{ - always @(*) - begin - nxt_stb = 1'b0; - nxt_clk = 1'b0; - nxt_counter = counter; - - { nxt_stb, nxt_counter[NCTR-3:0] } = counter[NCTR-3:0] - 1; - - if (nxt_stb) - begin - // Advance the top two bits - { nxt_clk, nxt_counter[NCTR-1:NCTR-2] } - = nxt_counter[NCTR-1:NCTR-2] +1; - - if (ckspd <= 1) - begin - nxt_clk = 1; - nxt_counter[NCTR-3:0] = 0; - end else if (ckspd == 2) - begin - nxt_clk = counter[NCTR-1]; - nxt_counter[NCTR-3:0] = 0; - end else - nxt_counter[NCTR-3:0] = ckspd-3; - end - - if (nxt_clk) - begin - if (i_cfg_ckspd <= 1) - nxt_counter = {2'b11, {(NCTR-2){1'b0}} }; - else if (i_cfg_ckspd == 2) - nxt_counter = { 2'b01, {(NCTR-2){1'b0}} }; - else - nxt_counter[NCTR-3:0] = i_cfg_ckspd-3; - end - end - - always @(posedge i_clk) - if (i_reset) - counter <= 0; - else if (nxt_clk && i_cfg_shutdown) - counter <= { 2'b11, {(NCTR-2){1'b0}} }; - else - counter <= nxt_counter; - // }}} - - // w_clk90, w_ckspd: Register the requested clock speed - // {{{ - always @(posedge i_clk) - if (i_reset) - clk90 <= 0; - else - clk90 <= w_clk90; - - always @(posedge i_clk) - if (i_reset) - ckspd <= 0; - else - ckspd <= w_ckspd; - - - assign w_clk90 = (nxt_clk) ? i_cfg_clk90 : clk90; - assign w_ckspd = (nxt_clk) ? i_cfg_ckspd : ckspd; - // }}} - - // o_ckstb, o_ckwide - // {{{ - initial o_ckstb = 1; - initial o_hlfck = 1; - initial o_ckwide = 0; - always @(posedge i_clk) - if (i_reset) - begin - o_ckstb <= 1; - o_hlfck <= 1; - o_ckwide <= 0; - end else if ((nxt_clk && i_cfg_shutdown) || (w_ckspd == 0)) - begin - o_ckstb <= 1'b1; // Or should this be !i_cfg_shutdown? - o_hlfck <= 1'b1; - o_ckwide <= (i_cfg_shutdown) ? 8'h00 - : (i_cfg_clk90) ? 8'h66 : 8'h33; - end else if (w_ckspd == 1) - begin - o_ckstb <= 1'b1; - o_hlfck <= 1'b1; - o_ckwide <= (w_clk90) ? 8'h3c : 8'h0f; - end else if (w_ckspd == 2) - begin - { o_ckstb, o_hlfck } <= (!nxt_counter[NCTR-1]) ? 2'b10 : 2'b01; - if (w_clk90) - o_ckwide <= (!nxt_counter[NCTR-1]) ? 8'h0f : 8'hf0; - else - o_ckwide <= (!nxt_counter[NCTR-1]) ? 8'h00 : 8'hff; - end else begin - o_ckstb <= nxt_clk; - o_hlfck <= (counter == {2'b01, {(NCTR-2){1'b0}} }); - if (w_clk90) - o_ckwide <= {(8){nxt_counter[NCTR-1] - ^ nxt_counter[NCTR-2]}}; - else - o_ckwide <= {(8){nxt_counter[NCTR-1]}}; - end - // }}} - - always @(posedge i_clk) - o_ckspd <= w_ckspd; -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - always @(*) - if (i_cfg_ckspd == 0) - assume(i_cfg_clk90); - - always @(posedge i_clk) - if (f_past_valid) - begin - if (ckspd == 0) - begin - assert(o_ckstb); - assert(counter == 0 - ||counter == {2'b11,{(NCTR-2){1'b0}} }); - end - if (ckspd == 1) - assert(counter == {2'b11,{(NCTR-2){1'b0}} }); - if (ckspd == 2) - assert(counter == 0 - || counter == {2'b01,{(NCTR-2){1'b0}} } - || counter == {2'b10,{(NCTR-2){1'b0}} } - || counter == {2'b11,{(NCTR-2){1'b0}} }); - if (ckspd >= 3) - assert(counter[NCTR-3:0] <= (ckspd-3)); - end - - always @(*) - if (!i_reset && o_ckstb && o_hlfck) - assert(ckspd <= 1 || (o_ckwide == 0 && nxt_clk)); - - always @(*) - if (!i_reset) - case(o_ckwide) - 8'h00: if (nxt_clk) - begin - assert(counter == {2'b11,{(NCTR-2){1'b0}} } || ckspd == 0); - end else if(!clk90) - begin - assert(counter[NCTR-1] == 1'b0); - end else if(clk90) - begin - assert(counter[NCTR-1:NCTR-2] == 2'b00 - ||counter[NCTR-1:NCTR-2] == 2'b11); - end - 8'h0f: assert((!clk90 && ckspd == 1 && o_ckstb && o_hlfck) - ||(clk90 && ckspd == 2 && o_ckstb)); - 8'hf0: assert(clk90 && ckspd == 2 && !o_ckstb && o_hlfck); - 8'hff: if(!clk90) assert(counter[NCTR-1] == 1'b1); - else - assert(counter[NCTR-1:NCTR-2] == 2'b01 - || counter[NCTR-1:NCTR-2] == 2'b10); - 8'h3c: assert( clk90 && ckspd == 1 && o_ckstb && o_hlfck); - 8'h33: assert(!clk90 && ckspd == 0 && o_ckstb && o_hlfck); - 8'h66: assert( clk90 && ckspd == 0 && o_ckstb && o_hlfck); - default: assert(0); - endcase -`endif // FORMAL -// }}} -endmodule - diff --git a/delete_later/rtl/sdspi/sdcmd.v b/delete_later/rtl/sdspi/sdcmd.v deleted file mode 100644 index 59d6382..0000000 --- a/delete_later/rtl/sdspi/sdcmd.v +++ /dev/null @@ -1,896 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sdcmd.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Bi-directional command line processor. This generates the -// command line inputs to the PHY, and receives its outputs. -// Commands are requested from the CPU, and responses gathered and -// returned to the register set. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module sdcmd #( - // {{{ - // parameter MW = 32, - parameter [0:0] OPT_DS = 1'b0, - // parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter LGTIMEOUT = 26, // 500ms expected - parameter LGLEN = 9, - parameter MW = 32 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Configuration bits - input wire i_cfg_ds, // Use ASYNC - input wire i_cfg_dbl, // 2Bits/Clk - input wire i_ckstb, - // Controller interface - // {{{ - input wire i_cmd_request, - input wire [1:0] i_cmd_type, - input wire [6:0] i_cmd, - input wire [31:0] i_arg, - - output wire o_busy, - output reg o_done, - output reg o_err, - output reg [1:0] o_ercode, - // }}} - // Send to the front end - // {{{ - output wire o_cmd_en, - // output wire o_pp_cmd, // From CFG reg - output wire [1:0] o_cmd_data, - // }}} - // Receive from the front end - // {{{ - input wire [1:0] i_cmd_strb, - input wire [1:0] i_cmd_data, - // input wire i_dat_busy, - - input wire S_ASYNC_VALID, - input wire [1:0] S_ASYNC_DATA, - // }}} - // Return the result - output reg o_cmd_response, - output reg [5:0] o_resp, - output reg [31:0] o_arg, - // Writes to memory - // {{{ - output reg o_mem_valid, - output wire [MW/8-1:0] o_mem_strb, - output wire [LGLEN-1:0] o_mem_addr, // Word address - output reg [MW-1:0] o_mem_data // Outgoing data - // }}} - // }}} - ); - - // Local declarations - // {{{ - localparam [1:0] R_NONE = 2'b00, - R_R1 = 2'b01, - R_R2 = 2'b10; - // R_R1b = 2'b11; - - localparam [1:0] ECODE_TIMEOUT = 2'b00, - ECODE_OKAY = 2'b01, - ECODE_BADCRC = 2'b10, - ECODE_FRAMEERR= 2'b11; - - localparam [6:0] CRC_POLYNOMIAL = 7'h09; - - reg active; - reg [5:0] srcount; - reg [47:0] tx_sreg; - - reg waiting_on_response, cfg_ds, cfg_dbl, r_frame_err; - reg [1:0] cmd_type; - reg [7:0] resp_count; - wire frame_err, w_done, crc_err, w_no_response; - reg [LGLEN+$clog2(MW/32)-1:0] mem_addr; - reg [39:0] rx_sreg; - - reg rx_timeout; - reg [LGTIMEOUT-1:0] rx_timeout_counter; - - reg [6:0] crc_fill; - reg r_busy, new_data; - - reg r_done; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Send 48b command to card - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial { active, srcount } = 0; - always @(posedge i_clk) - if (i_reset) - begin - active <= 0; - srcount <= 0; - end else if (i_cmd_request && !o_busy) - begin - srcount <= 48; - active <= 1; - // sreg <= { i_cmd, i_arg, CMDCRC({ i_cmd, i_arg }), 1'b1 }; - end else if (i_ckstb && srcount != 0) - begin - if (cfg_dbl) - begin - // sreg <= { sreg[45:0], 2'b11 }; - active <= (srcount > 2); - srcount <= srcount - 2; - end else begin - // sreg <= { sreg[46:0], 2'b1 }; - active <= (srcount > 1); - srcount <= srcount - 1; - end - end - - always @(posedge i_clk) - if (i_reset) - tx_sreg <= 48'hffff_ffff_ffff; - else if (i_cmd_request && !o_busy) - tx_sreg <= { 1'b0, i_cmd, i_arg, - CMDCRC({ 1'b0, i_cmd, i_arg }), 1'b1 }; - else if (i_ckstb) - begin - if (cfg_dbl) - tx_sreg <= { tx_sreg[45:0], 2'b11 }; - else - tx_sreg <= { tx_sreg[46:0], 1'b1 }; - end - - assign o_cmd_en = active; - assign o_cmd_data = tx_sreg[47:46]; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Receive response from card - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // waiting_on_response - // {{{ - initial waiting_on_response = 1'b0; - always @(posedge i_clk) - if (i_reset) - waiting_on_response <= 1'b0; - else if (i_cmd_request && !o_busy) - waiting_on_response <= (i_cmd_type != R_NONE); - else if (o_done) - waiting_on_response <= 1'b0; -/*; - begin - if (cmd_type[0] && resp_count >= 48) - waiting_on_response <= 1'b0; - if (resp_count >= 136) - waiting_on_response <= 1'b0; - if (rx_timeout) - waiting_on_response <= 1'b0; - end -*/ - // }}} - - // cfg_ds, cfg_dbl, cmd_type - // {{{ - always @(posedge i_clk) - if (i_reset) - { cfg_ds, cfg_dbl, cmd_type } <= 4'b0; - else if (i_cmd_request && !o_busy) - { cfg_ds, cfg_dbl, cmd_type } <= { (i_cfg_ds && OPT_DS), i_cfg_dbl, i_cmd_type }; - // }}} - - // new_data - // {{{ - always @(posedge i_clk) - if (i_reset || !waiting_on_response || active) - new_data <= 0; - else if (OPT_DS && cfg_ds) - new_data <= S_ASYNC_VALID; - else - new_data <= |i_cmd_strb; - // }}} - - // resp_count - // {{{ - always @(posedge i_clk) - if (i_reset || !waiting_on_response || active) - resp_count <= 0; - else if (resp_count < 192) - begin - if (OPT_DS && cfg_ds) - begin - if (S_ASYNC_VALID) - resp_count <= resp_count + 2; - end else - resp_count <= resp_count + (i_cmd_strb[1] ? 1:0) - + (i_cmd_strb[0] ? 1:0); - end - // }}} - - // rx_sreg - // {{{ - always @(posedge i_clk) - if (i_reset || !waiting_on_response || active) - rx_sreg <= 0; - else if (OPT_DS && cfg_ds) - begin - if (S_ASYNC_VALID) - rx_sreg <= { rx_sreg[37:0], S_ASYNC_DATA[1:0] }; - end else if (i_cmd_strb[1]) - begin - if (i_cmd_strb[0]) - rx_sreg <= { rx_sreg[37:0], i_cmd_data[1:0] }; - else - rx_sreg <= { rx_sreg[38:0], i_cmd_data[1] }; - end - // }}} - - assign w_done = waiting_on_response - &&((cmd_type == R_R2 && o_mem_valid && o_mem_addr >= 3) - || (cmd_type[0] && resp_count == 48)); - - assign w_no_response = (active && cmd_type == R_NONE && i_ckstb - // Verilator lint_off WIDTH - && (srcount == 1 + cfg_dbl)); - // Verilator lint_on WIDTH - - // o_cmd_response - // {{{ - initial o_cmd_response = 1'b0; - always @(posedge i_clk) - if (i_reset || !waiting_on_response || cmd_type == R_NONE || o_cmd_response) - o_cmd_response <= 1'b0; - else if (!cmd_type[1]) - o_cmd_response <= (resp_count == 48) && !r_done; - else // if (cmd_type == R_R2) - o_cmd_response <= (resp_count == 136) && !r_done; - // }}} - - // o_resp, o_arg - // {{{ - initial o_resp = 6'h0; - always @(posedge i_clk) - if (i_reset || !waiting_on_response) - o_resp <= 6'b0; - else if (resp_count == 8) - o_resp <= rx_sreg[5:0]; - - initial o_arg = 32'h0; - always @(posedge i_clk) - if (i_reset || !waiting_on_response) - o_arg <= 32'b0; - else if (cmd_type == R_R2) - begin - o_arg <= 32'h0; - end else - o_arg <= rx_sreg[8 +: 32]; - // }}} - - ////////// - // - // Writes to memory - // - - // o_mem_valid - // {{{ - initial o_mem_valid = 1'b0; - always @(posedge i_clk) - if (i_reset || cmd_type != R_R2 || !waiting_on_response - || rx_timeout || mem_addr >= 4) - o_mem_valid <= 1'b0; - else - o_mem_valid <= new_data - && (resp_count[4:0] == 8 && resp_count[7:5] != 0); - // }}} - - // o_mem_strb - // {{{ - generate if (MW==32) - begin : GEN_FULL_STRB - assign o_mem_strb = 4'hf; - end else begin : GEN_SUBSTRB - reg [MW/8-1:0] r_mem_strb; - - initial r_mem_strb = 0; - always @(posedge i_clk) - if (i_reset || cmd_type != R_R2 || !waiting_on_response) - r_mem_strb <= { 4'hf, {(MW/8-1){1'b0}} }; - else if (o_mem_valid) - r_mem_strb<= { r_mem_strb[3:0], r_mem_strb[MW/32-1:4] }; - - assign o_mem_strb = r_mem_strb; - end endgenerate - // }}} - - // o_mem_addr - // {{{ - initial mem_addr = 0; - always @(posedge i_clk) - if (i_reset || cmd_type != R_R2 || !waiting_on_response) - mem_addr <= 0; - else if (o_mem_valid) - mem_addr <= mem_addr + 1; - - assign o_mem_addr = mem_addr[LGLEN-1:$clog2(MW/32)]; - // }}} - - // o_mem_data - // {{{ - always @(posedge i_clk) - if (resp_count[4:0] == 8 && resp_count[7:5] != 0) - o_mem_data <= {(MW/32){rx_sreg[31:0]}}; - // }}} - - // Frame error detection - // {{{ - initial r_frame_err = 1'b0; - always @(posedge i_clk) - if (i_reset || !waiting_on_response) - r_frame_err <= 1'b0; - else if (i_cmd_request && !o_busy) - r_frame_err <= 1'b0; - else if (resp_count == 2 && rx_sreg[1:0] != 2'b00) - r_frame_err <= 1'b1; - - assign frame_err = r_frame_err || (waiting_on_response - &&((cmd_type[1] && !rx_sreg[0] && resp_count == 48) - ||((cmd_type==R_R2&& !rx_sreg[0] && resp_count == 136)))); - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // RX Timeout handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial rx_timeout = 0; - initial rx_timeout_counter = -1; - always @(posedge i_clk) - if (i_reset || !waiting_on_response || active || r_done) - begin - rx_timeout <= 0; - rx_timeout_counter <= -1; - end else if (!rx_timeout && ( - (OPT_DS && i_cfg_ds && S_ASYNC_VALID) - || ((!OPT_DS || !i_cfg_ds) && i_cmd_strb != 0))) - begin - // Recommended timeout is 500ms - rx_timeout <= 0; - rx_timeout_counter <= -1; - end else // if (i_ckstb) // Counter is in ms, not clock ticks - begin - if (rx_timeout_counter != 0) - rx_timeout_counter <= rx_timeout_counter - 1; - if (rx_timeout_counter <= 1) - rx_timeout <= 1; - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // CRC handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (i_reset || !waiting_on_response) - crc_fill <= 0; - else if (i_cmd_type[0] || resp_count > 7) - begin - if (OPT_DS && cfg_ds && S_ASYNC_VALID) - crc_fill <= STEPCRC(STEPCRC(crc_fill, - S_ASYNC_DATA[1]), S_ASYNC_DATA[0]); - else if ((!OPT_DS || !cfg_ds) && i_cmd_strb == 2'b11) - crc_fill <= STEPCRC(STEPCRC(crc_fill, - i_cmd_data[1]), i_cmd_data[0]); - else if ((!OPT_DS || !cfg_ds) && i_cmd_strb[1]) - crc_fill <= STEPCRC(crc_fill, i_cmd_data[1]); - end - - assign crc_err = w_done && (crc_fill != CRC_POLYNOMIAL); - - - function automatic [6:0] STEPCRC(input [6:0] fill, input i_bit); - // {{{ - begin - if (fill[6] ^ i_bit) - STEPCRC = { fill[5:0], 1'b0 } ^ CRC_POLYNOMIAL; - else - STEPCRC = { fill[5:0], 1'b0 }; - end endfunction - // }}} - - function automatic [6:0] CMDCRC(input [39:0] cmd); - // {{{ - reg [6:0] fill; - integer icrc; - begin - fill = 0; - - for(icrc=0; icrc<8+32; icrc=icrc+1) - fill = STEPCRC(fill, cmd[39-icrc]); - - CMDCRC = fill; - end endfunction - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // ERR handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial { o_err, o_ercode } = 3'h0; - always @(posedge i_clk) - if (i_reset || o_done || w_no_response) - o_err <= 1'b0; - else if (rx_timeout && !r_done) - o_err <= 1'b1; - else if (r_done && i_ckstb) - o_err <= (o_ercode != ECODE_OKAY); - - initial o_ercode = 2'h0; - always @(posedge i_clk) - if (i_reset || active || (i_cmd_request && !o_busy) || w_no_response - || o_done) - o_ercode <= 2'b00; - else if (!r_done) - begin - if (w_done) - begin - o_ercode <= ECODE_OKAY; - if (frame_err) - o_ercode <= ECODE_FRAMEERR; - if (crc_err) - o_ercode <= ECODE_BADCRC; - end else if (rx_timeout) - o_ercode <= ECODE_TIMEOUT; - end - // }}} - - initial r_done = 1'b0; - always @(posedge i_clk) - if (i_reset || w_no_response || o_done) - r_done <= 1'b0; - else if (w_done || rx_timeout) - r_done <= 1'b1; - // else // if (i_ckstb) - // r_done <= 1'b0; - - initial o_done = 1'b0; - always @(posedge i_clk) - if (i_reset || o_done) - o_done <= 1'b0; - else - o_done <= (rx_timeout || w_no_response - || (r_done && i_ckstb)); - - // r_busy is true if we are unable to accept a command - initial r_busy = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_busy <= 1'b0; - else if (i_cmd_request && !o_busy) - r_busy <= 1'b1; - else if (o_done) - r_busy <= 1'b0; - - assign o_busy = r_busy || !i_ckstb; - - // - // Make verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, R_R1 }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - (* anyconst *) reg f_nvr_request; - reg f_past_valid, f_busy; - reg [7:0] f_last_resp_count; - reg [47:0] f_tx_reg, f_tx_now; - wire [5:0] f_txshift; - - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - always @(*) - if (!i_reset && f_nvr_request) - begin - assume(!i_cmd_request); - assert(!active); - end - //////////////////////////////////////////////////////////////////////// - // - // Command requests - // {{{ - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assume(!i_cmd_request); - else if ($past(i_cmd_request && o_busy)) - begin - assume(i_cmd_request); - assume($stable(i_cmd)); - assume($stable(i_arg)); - assume($stable(i_cmd_type)); - end - - initial f_busy = 1'b0; - always @(posedge i_clk) - if (i_reset) - f_busy <= 1'b0; - else if (i_cmd_request && !o_busy) - f_busy <= 1'b1; - else if (o_done) - f_busy <= 1'b0; - - - always @(posedge i_clk) - if (!i_reset && f_busy) - begin - assume($stable(i_cfg_ds)); - assume($stable(i_cfg_dbl)); - end - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - assert(!f_busy); - assert(!r_busy); - assert(!o_done); - end else begin - if (!f_busy) - assert(!r_busy); - if (!r_busy) - assert(!active); - if ($past(o_done)) - begin - assert(!r_busy); - assert(!f_busy); - end - end - - always @(posedge i_clk) - if (!i_reset && r_busy && !r_done && cmd_type != R_R2) - assert(!o_err && o_ercode == 2'b00); - - always @(*) - if (!i_reset && o_err) - assert(o_done); - - always @(*) - if (!i_reset && !r_done) - assert(o_ercode == ECODE_TIMEOUT); - - always @(posedge i_clk) - if (!i_reset && $past(o_cmd_response)) - assert(!o_cmd_response); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // IO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && !$past(i_ckstb)) - begin - assert($stable(o_cmd_en)); - assert($stable(o_cmd_data)); - end - - always @(posedge i_clk) - if ($past(i_reset || o_cmd_en)) - assume(!S_ASYNC_VALID && i_cmd_strb == 0); - - always @(*) - if (!i_cmd_strb[1] || !cfg_dbl) - assume(!i_cmd_strb[0]); - - always @(*) - if (!i_reset && !OPT_DS) - assert(!cfg_ds); - - always @(*) - if (!i_reset && (!OPT_DS || !cfg_ds)) - assume(!S_ASYNC_VALID); - - always @(*) - if (r_busy && cfg_dbl) - assume(i_cmd_strb[1] == i_cmd_strb[0]); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (i_cmd_request && !o_busy) - f_tx_reg <= { 1'b0, i_cmd, i_arg, CMDCRC({ 1'b0, i_cmd, i_arg }), 1'b1 }; - - assign f_txshift = 48 - srcount; - - integer f_txcs; - always @(*) - begin - f_tx_now = f_tx_reg; - for(f_txcs=0; f_txcs<48; f_txcs=f_txcs+1) - if (f_txcs < f_txshift) - f_tx_now = { f_tx_now[46:0], 1'b1 }; - end - - always @(*) - if (f_past_valid) - begin - if (!active) - begin - assert(&tx_sreg); - assert(!o_cmd_en); - assert(o_cmd_data == 2'b11); - end else begin - assert(o_cmd_en); - assert(tx_sreg == f_tx_now); - end - end - - - // }}} - always @(posedge i_clk) - f_last_resp_count <= resp_count; - - always @(*) - if (!i_reset && (cfg_ds && OPT_DS)) - assert(!resp_count[0]); - - always @(*) - if (!i_reset && (!cfg_dbl || resp_count[0])) - assume(i_cmd_strb != 2'b11); - - always @(*) - if (!i_reset && active) - assert(waiting_on_response == (cmd_type != R_NONE)); - - always @(*) - if (!i_reset && (active || waiting_on_response)) - assert(r_busy); - - always @(*) - if (!i_reset) - begin - if (active || !waiting_on_response || cmd_type != R_R2) - assert(!o_mem_valid); - - if (active) - assert(resp_count == 0); - - if (resp_count < 8+32 || cmd_type != R_R2 || active) - begin - assert(mem_addr == 0); - end else if (r_done && !rx_timeout) - begin - assert(mem_addr == 4); - end else if (waiting_on_response && !rx_timeout) - begin - assert(mem_addr + o_mem_valid == ((f_last_resp_count-8)>>5)); - end - - if (cmd_type == R_NONE) - begin - assert(resp_count == 0); - end - - if (cmd_type[0] && resp_count == 48 && r_busy) - begin - assert(w_done || r_done); - end - - if (cmd_type[0] && resp_count > 48 && r_busy) - begin - assert(w_done || r_done); - end - - if (resp_count > 50 && !r_done && r_busy) - begin - assert(cmd_type == R_R2); - end - - if (!r_busy) - assert(!waiting_on_response); - if (!active && r_busy && !o_done) - assert(waiting_on_response); - - if (r_busy && (resp_count > (8+128))) - begin - assert(w_done || r_done); - end - - if (r_busy && !r_done) - begin - assert(o_mem_addr <= 3); - end - - end - - always @(*) - assert(srcount <= 48); - always @(*) - assert(active == (srcount != 0)); - always @(*) - if (active && !i_reset && cfg_dbl) - assert(srcount[0] == 1'b0); - - always @(*) - if (!i_reset && cmd_type == R_NONE) - assert(!waiting_on_response); - - always @(*) - assert(rx_timeout == (rx_timeout_counter == 0)); - - always @(*) - if (!i_reset && !r_busy) - assert(!rx_timeout); - - always @(*) - if (!i_reset && active) - assert(!o_err && o_ercode == 2'b00); - - always @(*) - if (!i_reset) - begin - if (!r_busy) - begin - assert(!r_done); - end - if (active) - begin - assert(!r_done); - end - - if (!rx_timeout) - begin - if (cmd_type[0] && resp_count < 48) - begin - assert(!r_done); - end - - if (cmd_type == R_R2 && resp_count < 136) - begin - assert(!r_done); - end - end - if (cmd_type == R_NONE) - begin - assert(!waiting_on_response); - end - end - - always @(*) - if (!i_reset) - begin - assert(r_busy == (active || waiting_on_response ||o_done)); - if (o_done) - assert(r_busy); - end - - always @(*) - if (!i_reset && !f_busy) - assert(!o_done); - - // always @(*) if (!i_reset && r_done) assert(!r_busy || o_done); - - always @(*) - if (!i_reset) - assert(f_busy == r_busy); - - always @(*) - if (!i_reset && o_err) - assert(o_ercode != ECODE_OKAY); - //////////////////////////////////////////////////////////////////////// - // - // Coverage - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - - always @(posedge i_clk) - if (!i_reset && o_done) - cover(i_cmd_type == R_NONE); - - always @(posedge i_clk) - if (!i_reset && o_done) - begin - cover(i_cmd_type == R_R1 && !o_err); - cover(i_cmd_type == R_R1 && o_err && o_ercode == ECODE_BADCRC); - cover(i_cmd_type == R_R1 && o_err && o_ercode== ECODE_FRAMEERR); - - // Caution! These will take at least 136+49+2 clocks! - cover(i_cmd_type == R_R2 && !o_err); - cover(i_cmd_type == R_R2 && o_err && o_ercode == ECODE_BADCRC); - cover(i_cmd_type == R_R2 && o_err && o_ercode== ECODE_FRAMEERR); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Careless assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} -`endif // FORMAL -// }}} -endmodule - diff --git a/delete_later/rtl/sdspi/sdfrontend.v b/delete_later/rtl/sdspi/sdfrontend.v deleted file mode 100644 index 4104c40..0000000 --- a/delete_later/rtl/sdspi/sdfrontend.v +++ /dev/null @@ -1,1008 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sdfrontend.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is the "front-end" for the SDIO controller. It's designed -// to support all modes up to HS400 if OPT_SERDES is enabled, -// or just the backwards compatibility modes (up to 50MHz) if not. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module sdfrontend #( - // {{{ - parameter [0:0] OPT_SERDES = 1'b0, - parameter [0:0] OPT_DDR = 1'b1, - parameter NUMIO = 8 - // }}} - ) ( - // {{{ - input wire i_clk, i_hsclk, - // Configuration - input wire i_reset, - input wire i_cfg_ddr, - input wire [4:0] i_sample_shift, - // Control signals - // Tx path - // {{{ - // MSB "first" incoming data. - input wire [7:0] i_sdclk, - // - input wire i_cmd_en, - input wire i_pp_cmd, // Push/pull cmd lines - input wire [1:0] i_cmd_data, - // - input wire i_data_en, i_rx_en, - input wire i_pp_data, // Push/pull data lines - input wire [31:0] i_tx_data, - input wire i_afifo_reset_n, - // }}} - output wire o_data_busy, - // Synchronous Rx path - // {{{ - output wire [1:0] o_cmd_strb, - output wire [1:0] o_cmd_data, - // - output wire [1:0] o_rx_strb, - output wire [15:0] o_rx_data, - // }}} - // Async Rx path - // {{{ - output wire MAC_VALID, - output wire [1:0] MAC_DATA, - output wire MAD_VALID, - output wire [31:0] MAD_DATA, - // output wire MAD_LAST, - // }}} - // I/O ports - // {{{ - output wire o_ck, - input wire i_ds, - // -`ifdef VERILATOR - output wire io_cmd_tristate, - output wire o_cmd, - input wire i_cmd, - // - output wire [NUMIO-1:0] io_dat_tristate, - output wire [NUMIO-1:0] o_dat, - input wire [NUMIO-1:0] i_dat, -`else - inout wire io_cmd, - inout wire [NUMIO-1:0] io_dat, -`endif - // }}} - output wire [31:0] o_debug - // }}} - ); - - // Local declarations - // {{{ - genvar gk; - reg dat0_busy, wait_for_busy; -`ifndef VERILATOR - wire io_cmd_tristate, i_cmd, o_cmd; - wire [NUMIO-1:0] io_dat_tristate, i_dat, o_dat; -`endif - // }}} - generate if (!OPT_SERDES && !OPT_DDR) - begin : GEN_NO_SERDES - // {{{ - // This is sort of the "No-PHY" option. Maximum speed, when - // using this option, is the incoming clock speed/2. Without - // SERDES support, there's no support for the DS (data strobe) - // pin either. Think of this as a compatibility mode. - // - // Fastest clock supported = incoming clock speed / 2 - // - wire next_pedge, next_dedge; - reg resp_started, io_started, last_ck; - reg r_cmd_data, r_cmd_strb, r_rx_strb; - reg [7:0] r_rx_data; - reg [1:0] ck_sreg, pck_sreg; - reg sample_ck, cmd_sample_ck; - - assign o_ck = i_sdclk[7]; - - assign io_cmd_tristate - = !(i_cmd_en && (i_pp_cmd || !i_cmd_data[1])); - assign o_cmd = i_cmd_data[1]; - - // assign io_cmd = (io_cmd_tristate) ? i_cmd : o_cmd; - - - assign o_dat = i_tx_data[24 +: NUMIO]; - - for(gk=0; gk> i_sample_shift[4:3]; - // Verilator lint_on WIDTH - // }}} - - // cmd_sample_ck: When do we sample the command line? - // {{{ - always @(posedge i_clk) - if (i_reset || i_cmd_en) - pck_sreg <= 0; - else - pck_sreg <= { pck_sreg[0], next_pedge }; - - always @(*) - if (i_cmd_en) - cmd_sample_ck = 0; - else - // Verilator lint_off WIDTH - cmd_sample_ck = { pck_sreg[1:0], next_pedge } >> i_sample_shift; - // Verilator lint_on WIDTH - // }}} - - always @(posedge i_clk) - if (i_reset || i_cmd_en) - resp_started <= 1'b0; - else if (!i_cmd && cmd_sample_ck) - resp_started <= 1'b1; - - always @(posedge i_clk) - if (i_reset || i_data_en || !i_rx_en) - io_started <= 1'b0; - else if (!i_dat[0] && sample_ck) - io_started <= 1'b1; - - // dat0_busy, wait_for_busy - // {{{ - initial { dat0_busy, wait_for_busy } = 2'b01; - always @(posedge i_clk) - if (i_reset || i_cmd_en || i_data_en) - begin - dat0_busy <= 1'b0; - wait_for_busy <= 1'b1; - end else if (wait_for_busy && !i_dat[0]) - begin - dat0_busy <= 1'b1; - wait_for_busy <= 1'b0; - end else if (!wait_for_busy && i_dat[0]) - dat0_busy <= 1'b0; - - assign o_data_busy = dat0_busy; - // }}} - - initial last_ck = 1'b0; - always @(posedge i_clk) - begin - last_ck <= i_sdclk[7]; - - if (i_cmd_en || !cmd_sample_ck) - r_cmd_strb <= 1'b0; - else if (!i_cmd || resp_started) - r_cmd_strb <= 1'b1; - else - r_cmd_strb <= 1'b0; - - if (i_data_en || !sample_ck || !i_rx_en) - r_rx_strb <= 1'b0; - else if (io_started || i_dat[0] == 0) - r_rx_strb <= 1'b1; - else - r_rx_strb <= 1'b0; - - if (cmd_sample_ck) - r_cmd_data <= i_cmd; - if (sample_ck) - begin - r_rx_data <= 0; - r_rx_data[NUMIO-1:0] <= i_dat; - end - end - - assign o_cmd_strb = { r_cmd_strb, 1'b0 }; - assign o_cmd_data = { r_cmd_data, 1'b0 }; - assign o_rx_strb = { r_rx_strb, 1'b0 }; - assign o_rx_data = { r_rx_data, 8'h0 }; - - // No asynchronous outputs w/o OPT_SERDES - assign MAC_VALID = 1'b0; - assign MAC_DATA = 2'h0; - assign MAD_VALID = 1'b0; - assign MAD_DATA = 32'h0; - - reg [7:0] w_out; - always @(*) - begin - w_out = 0; - w_out[NUMIO-1:0] = i_dat; - end - - assign o_debug = { - i_cmd_en || i_data_en, - 5'h0, - i_sdclk[7], 1'b0, - i_cmd_en, i_cmd_data[1], 1'b0, - (io_cmd_tristate) ? i_cmd : o_cmd, - r_cmd_strb, r_cmd_data, - i_data_en, r_rx_strb, r_rx_data, - // - ((i_data_en) ? i_tx_data[31:24] : w_out) - }; - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused_no_serdes; - assign unused_no_serdes = &{ 1'b0, i_afifo_reset_n, i_ds, - i_sdclk[6:0], i_tx_data[23:0], - i_cmd_data[0], i_hsclk,i_sample_shift - }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} - // }}} - end else if (!OPT_SERDES && OPT_DDR) - begin : GEN_IODDR_IO - // {{{ - // Notes: - // {{{ - // The idea is, if we only have DDR elements and no SERDES - // elements, can we do better than with just IOs? - // - // The answer is, Yes. Even though we aren't going to run at - // 2x the clock speed w/o OPT_SERDES, we can output a DDR clk, - // and we can also access sub-sample timing via IDDR elements. - // Even in DDR mode, however, there will be no possibility of - // two outputs per clock. - // - // Fastest clock supported = incoming clock speed - // Practically, you won't be likely to achieve this unless - // you get really lucky, but it is technically the fastest - // speed this version supports. - // A more realistic speed will be the incoming clock speed / 2, - // and done with more reliability than the non-DDR mode. - // }}} - - // Local declarations - // {{{ - wire [1:0] w_cmd; - wire pre_dat [15:0]; - reg [15:0] w_dat; - wire [1:0] next_pedge, next_dedge; - - reg [5:0] ck_sreg, pck_sreg; - reg [1:0] sample_ck, cmd_sample_ck; - reg resp_started, io_started, last_ck, - r_cmd_strb, r_cmd_data, r_rx_strb; - reg [7:0] r_rx_data; - // Verilator lint_off UNUSED - wire io_clk_tristate, ign_clk; - assign ign_clk = o_ck; - // Verilator lint_on UNUSED - // }}} - - // Clock - // {{{ - xsdddr #(.OPT_BIDIR(1'b0)) - u_clk_oddr( - .i_clk(i_clk), .i_en(1'b1), - .i_data({ i_sdclk[7], i_sdclk[3] }), - .io_pin_tristate(io_clk_tristate), - .o_pin(o_ck), - .i_pin(ign_clk), - // Verilator lint_off PINCONNECTEMPTY - .o_wide() - // Verilator lint_on PINCONNECTEMPTY - ); - // }}} - - // CMD - // {{{ - xsdddr #(.OPT_BIDIR(1'b1)) - u_cmd_ddr( - .i_clk(i_clk), - .i_en(i_reset || (i_cmd_en && (i_pp_cmd || !i_cmd_data[1]))), - .i_data({(2){ i_reset || i_cmd_data[1] }}), - .io_pin_tristate(io_cmd_tristate), - .o_pin(o_cmd), - .i_pin(i_cmd), - .o_wide(w_cmd) - ); - // }}} - - // DATA - // {{{ - for(gk=0; gk> i_sample_shift[4:2]; - // Verilator lint_on WIDTH - // }}} - - // cmd_sample_ck: When do we sample the command line? - // {{{ - always @(posedge i_clk) - if (i_cmd_en) - pck_sreg <= 0; - else - pck_sreg <= { pck_sreg[3:0], next_pedge }; - - always @(*) - if (i_cmd_en) - cmd_sample_ck = 0; - else - // Verilator lint_off WIDTH - cmd_sample_ck = { pck_sreg[5:0], next_pedge } >> i_sample_shift[4:2]; - // Verilator lint_on WIDTH - // }}} - - always @(posedge i_clk) - if (i_cmd_en) - resp_started <= 1'b0; - else if ((cmd_sample_ck != 0) && (cmd_sample_ck & w_cmd)==0) - resp_started <= 1'b1; - - always @(posedge i_clk) - if (i_data_en || !i_rx_en) - io_started <= 1'b0; - else if (sample_ck != 0 - && ((sample_ck & { w_dat[8], w_dat[0] }) == 0)) - io_started <= 1'b1; - - // dat0_busy, wait_for_busy - // {{{ - initial { dat0_busy, wait_for_busy } = 2'b01; - always @(posedge i_clk) - if (i_cmd_en || i_data_en) - begin - dat0_busy <= 1'b0; - wait_for_busy <= 1'b1; - end else if (wait_for_busy && (cmd_sample_ck != 0) - && (cmd_sample_ck & {w_dat[8],w_dat[0]})==2'b0) - begin - dat0_busy <= 1'b1; - wait_for_busy <= 1'b0; - end else if (!wait_for_busy && (cmd_sample_ck != 0) - && (cmd_sample_ck & {w_dat[8],w_dat[0]})!=2'b0) - dat0_busy <= 1'b0; - - assign o_data_busy = dat0_busy; - // }}} - - initial last_ck = 1'b0; - always @(posedge i_clk) - begin - last_ck <= i_sdclk[3]; - - // The command response - // {{{ - if (i_cmd_en || cmd_sample_ck == 0) - begin - r_cmd_strb <= 1'b0; - // r_cmd_data <= r_cmd_data; - end else if (resp_started) - begin - r_cmd_strb <= 1'b1; - r_cmd_data <= |(cmd_sample_ck & w_cmd); - end else if ((cmd_sample_ck[1] && !w_cmd[1]) - ||(cmd_sample_ck[0] && !w_cmd[0])) - begin - r_cmd_strb <= 1'b1; - r_cmd_data <= 1'b0; - end else - r_cmd_strb <= 1'b0; - // }}} - - // The data response - // {{{ - if (i_data_en || sample_ck == 0) - r_rx_strb <= 1'b0; - else if (io_started) - r_rx_strb <= 1'b1; - else - r_rx_strb <= 1'b0; - // }}} - - if (sample_ck[1]) - r_rx_data <= w_dat[15:8]; - else - r_rx_data <= w_dat[7:0]; - end - - assign o_cmd_strb = { r_cmd_strb, 1'b0 }; - assign o_cmd_data = { r_cmd_data, 1'b0 }; - assign o_rx_strb = { r_rx_strb, 1'b0 }; - assign o_rx_data = { r_rx_data, 8'h0 }; - - // No asynchronous outputs w/o OPT_SERDES - assign MAC_VALID = 1'b0; - assign MAC_DATA = 2'h0; - assign MAD_VALID = 1'b0; - assign MAD_DATA = 32'h0; - - reg [7:0] w_out; - always @(*) - begin - w_out = 0; - w_out[NUMIO-1:0] = w_dat[8 +: NUMIO]& w_dat[0 +: NUMIO]; - end - - assign o_debug = { - i_cmd_en || i_data_en, 2'h0, i_rx_en, - sample_ck, i_sdclk[7], i_sdclk[3], - i_cmd_en, i_cmd_data[1:0], - (&w_cmd), r_cmd_strb, r_cmd_data, - i_data_en, r_rx_strb, r_rx_data, - // - ((i_data_en) ? i_tx_data[31:24] : w_out) - }; - - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused_ddr; - assign unused_ddr = &{ 1'b0, i_hsclk, i_ds, i_tx_data[23:0], - i_sdclk[6:4], i_sdclk[2:0], i_afifo_reset_n, - i_sample_shift[1:0] }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} - // }}} - end else begin : GEN_WIDE_IO - // {{{ - // Generic PHY handler, designed to support up to HS400. - // Outputs 4 data periods per incoming clock, and 8 clock values - // per incoming clock--hence the outgoing clock may have a - // 90 degree shift from the data. When dealing with non-DS - // data, the clock edge is detected on output, and a sample - // controller decides when to sample it on input. When working - // with DS based outputs, an asynchronous FIFO is used to clock - // incoming data. Further, when using the asynchronous FIFO, - // the start of any incoming data is quietly stripped off, - // guaranteeing that all data will be aligned on the left/MSB - // sample. - // - // Fastest clock supported = incoming clock speed * 2 - - // Local declarations - // {{{ - reg af_started_p, af_started_n, acmd_started; - reg af_count_p, af_count_n, acmd_count; - wire [3:0] ign_afifo_full, afifo_empty; - wire [31:0] af_data; - wire [1:0] acmd_empty, ign_acmd_full; - reg [1:0] w_cmd_data; - wire [15:0] w_rx_data; - reg [15:0] r_rx_data; - reg last_ck; - wire [7:0] next_ck_sreg; - reg [23:0] ck_sreg; - wire [7:0] next_pedge, next_nedge, wide_cmd_data; - reg [7:0] sample_ck; - wire [1:0] af_cmd; - reg [1:0] r_cmd_data; - reg [1:0] busy_strb, busy_data; - reg [7:0] busy_ck; - wire raw_cmd; - wire [NUMIO-1:0] raw_iodat; - // }}} - - // Clock - // {{{ - // Verilator lint_off UNUSED - wire io_clk_tristate, ign_clk; - // Verilator lint_on UNUSED - - xsdserdes8x #(.OPT_BIDIR(1'b0)) - u_clk_oserdes( - .i_clk(i_clk), - .i_hsclk(i_hsclk), - .i_en(1'b1), - .i_data(i_sdclk), - .io_tristate(io_clk_tristate), - .o_pin(o_ck), - .i_pin(ign_clk), - // Verilator lint_off PINCONNECTEMPTY - .o_raw(), .o_wide() - // Verilator lint_on PINCONNECTEMPTY - ); - // }}} - - assign next_pedge = { ~{last_ck, i_sdclk[7:1] } & i_sdclk[7:0] }; - assign next_nedge = i_cfg_ddr ? { {last_ck, i_sdclk[7:1] } & ~i_sdclk[7:0] } : 8'h0; - - assign next_ck_sreg = (i_data_en) ? 8'h0 - : { next_pedge | next_nedge }; - - always @(posedge i_clk) - if (!i_afifo_reset_n || i_data_en) - { last_ck, ck_sreg } <= 0; - else begin - last_ck <= i_sdclk[0]; - ck_sreg <= { ck_sreg[15:0], next_ck_sreg }; - end - - initial sample_ck = 0; - always @(posedge i_clk) - if (i_data_en || i_afifo_reset_n) - sample_ck <= 0; - else - // Verilator lint_off WIDTH - sample_ck <= { ck_sreg[23:0], next_ck_sreg } >> i_sample_shift; - // Verilator lint_on WIDTH - - initial busy_ck = 1'b0; - always @(posedge i_clk) - if (i_data_en || i_cmd_en) - busy_ck <= 0; - else - // Verilator lint_off WIDTH - busy_ck <= { ck_sreg[23:0], next_ck_sreg } >> i_sample_shift; - // Verilator lint_on WIDTH - - - for(gk=0; gk> i_sample_shift; - // Verilator lint_on WIDTH - - - xsdserdes8x #( - .OPT_BIDIR(1'b1) - ) cmd_serdes( - .i_clk(i_clk), - .i_hsclk(i_hsclk), - .i_en(i_cmd_en && (i_pp_cmd || !i_cmd_data[1])), - .i_data({ {(4){i_cmd_data[1]}}, {(4){i_cmd_data[0]}} }), - .io_tristate(io_cmd_tristate), - .o_pin(o_cmd), - .i_pin(i_cmd), - .o_raw(raw_cmd), .o_wide(wide_cmd_data) - ); - - integer ikcmd; - - always @(*) - begin - w_cmd_data[1:0] = 0; - if (|sample_ck[7:4]) - begin - for(ikcmd=4; ikcmd<8; ikcmd=ikcmd+1) - if (cmd_sample_ck[ikcmd]) - w_cmd_data[1] = wide_cmd_data[ikcmd]; - end - - if (|sample_ck[3:0]) - begin - for(ikcmd=0; ikcmd<4; ikcmd=ikcmd+1) - if (cmd_sample_ck[ikcmd]) - w_cmd_data[gk] = wide_cmd_data[ikcmd]; - end - end - - always @(posedge i_clk) - if (sample_ck[7:4] == 0) - r_cmd_data <= { w_cmd_data[0], 1'b0 }; - else - r_cmd_data <= w_cmd_data; - - assign o_cmd_data = r_cmd_data; - - // }}} - //////////////////////////////////////////////////////////////// - // - // Data strobe based inputs - // {{{ - - // Async command port - // {{{ - // The rule here is that only the positive edges of the - // data strobe will qualify the CMD pin; - always @(posedge i_ds or posedge i_cmd_en) - if (i_cmd_en) - acmd_started <= 0; - else if (!raw_cmd) - acmd_started <= 1; - - always @(posedge i_ds or posedge i_cmd_en) - if (i_cmd_en) - acmd_count <= 0; - else if (acmd_started || raw_cmd) - acmd_count <= acmd_count + 1; - - afifo #( - .LGFIFO(4), .WIDTH(1), .WRITE_ON_POSEDGE(1'b1) - ) u_pcmd_fifo_0 ( - // {{{ - .i_wclk(i_ds), .i_wr_reset_n(i_cmd_en), - .i_wr((acmd_started || !raw_cmd)&& acmd_count == 1'b0), - .i_wr_data(raw_cmd), - .o_wr_full(ign_afifo_full[0]), - // - .i_rclk(i_clk), .i_rd_reset_n(i_cmd_en), - .i_rd(acmd_empty == 2'b0), .o_rd_data(af_cmd[1]), - .o_rd_empty(acmd_empty[0]) - // }}} - ); - - afifo #( - .LGFIFO(4), .WIDTH(1), .WRITE_ON_POSEDGE(1'b1) - ) u_pcmd_fifo_1 ( - // {{{ - .i_wclk(i_ds), .i_wr_reset_n(i_cmd_en), - .i_wr(acmd_count), .i_wr_data(raw_cmd), - .o_wr_full(ign_acmd_full[1]), - // - .i_rclk(i_clk), .i_rd_reset_n(i_cmd_en), - .i_rd(acmd_empty == 2'b0), .o_rd_data(af_cmd[0]), - .o_rd_empty(acmd_empty[1]) - // }}} - ); - - assign MAC_VALID = (acmd_empty == 2'h0); - assign MAC_DATA = af_cmd; - // }}} - - // af_started_*, af_count_* - // {{{ - always @(posedge i_ds or negedge i_afifo_reset_n) - if (!i_afifo_reset_n) - af_started_p <= 0; - else if (raw_iodat[0] == 0) - af_started_p <= 1; - - always @(posedge i_ds or negedge i_afifo_reset_n) - if (!i_afifo_reset_n) - af_count_p <= 0; - else if (af_started_p) - af_count_p <= af_count_p + 1; - - always @(negedge i_ds or negedge i_afifo_reset_n) - if (!i_afifo_reset_n) - af_started_n <= 0; - else if (af_started_p) - af_started_n <= 1; - - always @(negedge i_ds or negedge i_afifo_reset_n) - if (!i_afifo_reset_n) - af_count_n <= 0; - else if (af_started_n) - af_count_n <= af_count_n + 1; - // }}} - - - afifo #( - .LGFIFO(4), .WIDTH(8), .WRITE_ON_POSEDGE(1'b1) - ) u_pedge_fifo_0 ( - // {{{ - .i_wclk(i_ds), .i_wr_reset_n(i_afifo_reset_n), - .i_wr(af_started_p && af_count_p == 1'b0), - .i_wr_data(raw_iodat), - .o_wr_full(ign_afifo_full[0]), - // - .i_rclk(i_clk), .i_rd_reset_n(i_afifo_reset_n), - .i_rd(MAD_VALID), .o_rd_data(af_data[31:24]), - .o_rd_empty(afifo_empty[0]) - // }}} - ); - - afifo #( - .LGFIFO(4), .WIDTH(8), .WRITE_ON_POSEDGE(1'b0) - ) u_nedge_fifo_1 ( - // {{{ - .i_wclk(i_ds), .i_wr_reset_n(i_afifo_reset_n), - .i_wr(af_started_n && af_count_n == 1'b0), - .i_wr_data(raw_iodat), - .o_wr_full(ign_afifo_full[1]), - // - .i_rclk(i_clk), .i_rd_reset_n(i_afifo_reset_n), - .i_rd(MAD_VALID), .o_rd_data(af_data[23:16]), - .o_rd_empty(afifo_empty[1]) - // }}} - ); - - afifo #( - .LGFIFO(4), .WIDTH(8), .WRITE_ON_POSEDGE(1'b1) - ) u_pedge_fifo_2 ( - // {{{ - .i_wclk(i_ds), .i_wr_reset_n(i_afifo_reset_n), - .i_wr(af_count_p == 1'b1), - .i_wr_data(raw_iodat), - .o_wr_full(ign_afifo_full[2]), - // - .i_rclk(i_clk), .i_rd_reset_n(i_afifo_reset_n), - .i_rd(MAD_VALID), .o_rd_data(af_data[15:8]), - .o_rd_empty(afifo_empty[2]) - // }}} - ); - - afifo #( - .LGFIFO(4), .WIDTH(8), .WRITE_ON_POSEDGE(1'b0) - ) u_nedge_fifo_3 ( - // {{{ - .i_wclk(i_ds), .i_wr_reset_n(i_afifo_reset_n), - .i_wr(af_count_n == 1'b1), - .i_wr_data(raw_iodat), - .o_wr_full(ign_afifo_full[3]), - // - .i_rclk(i_clk), .i_rd_reset_n(i_afifo_reset_n), - .i_rd(MAD_VALID), .o_rd_data(af_data[ 7: 0]), - .o_rd_empty(afifo_empty[3]) - // }}} - ); - - /* - reg prior_af_return, af_flush; - - always @(posedge i_clk) - if (!i_afifo_reset_n) - prior_af_return <= 0; - else if (MAD_VALID) - prior_af_return <= 1; - - always @(posedge i_clk) - if (!i_afifo_reset_n || !prior_af_return) - af_flush <= 1'b0; - else if (afifo_empty == 4'h0) - af_flush <= 1'b0; - else - af_flush <= !afifo_empty[0]; - */ - - assign MAD_VALID = (afifo_empty == 4'h0); // af_flush && !afifo_empty[0] - assign MAD_DATA = af_data; - // assign MAD_LAST = af_flush && (afifo_empty != 4'h0); - // }}} - // }}} - // }}} - end endgenerate - - //////////////////////////////////////////////////////////////////////// - // - // IO buffers --- if not using Verilator - // {{{ -`ifndef VERILATOR - - IOBUF - u_cmdbuf( .T(io_cmd_tristate), .I(o_cmd), .IO(io_cmd), .O(i_cmd)); - - generate for(gk=0; gk= 8); - - always @(posedge i_clk) - if (i_reset || !i_rx_en || (i_cfg_ds && OPT_DS)) - s2_fill <= 0; - else - s2_fill <= sync_fill[4:3]; - - // Verilator lint_off WIDTH - always @(posedge i_clk) - if (OPT_LOWPOWER && (!i_rx_en || (i_cfg_ds && OPT_DS))) - s2_data <= 0; - else if (sync_fill[4]) - s2_data <= sync_sreg >> sync_fill[2:0]; - else if (sync_fill[3]) - s2_data <= {sync_sreg, 8'h0} >> sync_fill[2:0]; - // Verilator lint_on WIDTH - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Asynchronous (w/ DS) data path - // {{{ - - // Nothing really more needs to be done. The async path comes in at - // 4bytes at a times, all four valid (presently), and needs to be - // synchronized to a 4-byte stream w/ all four valid. Of course, this - // will only work as long as the DS strobe signals only ever arrive - // in pairs of pulses. - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Align, and write to (external) memory - // {{{ - // (Memory is just external to this module, not necessarily to the chip) - //////////////////////////////////////////////////////////////////////// - // - // - - // o_mem_valid - // {{{ - always @(posedge i_clk) - if (i_reset || !i_rx_en || mem_full || r_watchdog - || (mem_valid && (&mem_addr) && mem_strb[0])) - mem_valid <= 0; - else if (!i_cfg_ds || !OPT_DS) - begin - mem_valid <= s2_valid || rnxt_strb; - end else begin - mem_valid <= S_ASYNC_VALID && data_phase; - end - - always @(posedge i_clk) - if (i_reset || !i_rx_en) - mem_full <= 0; - else if (mem_valid && (&mem_addr) && mem_strb[0]) - mem_full <= 1; - - assign o_mem_valid = mem_valid; - // }}} - - // o_mem_addr - // {{{ - always @(posedge i_clk) - if (i_reset || !i_rx_en || mem_full - || (mem_valid && (&mem_addr) && mem_strb[0])) - next_subaddr <= 0; - else if (!i_cfg_ds || !OPT_DS) - next_subaddr <= next_subaddr + s2_fill; - // else if (S_ASYNC_VALID) - // next_subaddr <= next_subaddr + 4; - else - next_subaddr <= subaddr; - - always @(posedge i_clk) - if (i_reset || !i_rx_en) - { mem_addr, subaddr } <= 0; - else if (o_mem_valid) - begin - // Verilator lint_off WIDTH - { mem_addr, subaddr } <= { mem_addr, subaddr } + COUNTONES(o_mem_strb); - // Verilator lint_on WIDTH - end - - assign o_mem_addr = mem_addr; - // }}} - - // o_mem_data, o_mem_strb - // {{{ - always @(posedge i_clk) - if (i_reset || !i_rx_en || mem_full) - begin - mem_data <= 0; - mem_strb <= 0; - rnxt_data <= 0; - rnxt_strb <= 0; - end else if (!i_cfg_ds || !OPT_DS) - begin - - if (s2_fill[1]) - begin - { mem_data, rnxt_data } <= { rnxt_data, {(MW){1'b0}} } - |({ s2_data[15:0], {(MW-8){1'b0}} } >> (next_subaddr*8)); - { mem_strb, rnxt_strb } <= { rnxt_strb, {(MW/8){1'b0}} } - |({ 2'b11, {(MW/8-1){1'b0}} } >> (next_subaddr)); - end else if (s2_fill[0]) - begin - { mem_data, rnxt_data } <= {rnxt_data, {(MW){1'b0}} } - |({ s2_data[15:8], {(MW){1'b0}} } >> (next_subaddr*8)); - { mem_strb, rnxt_strb } <= { rnxt_strb, {(MW/8){1'b0}} } - |({ s2_fill[0],{(MW/8){1'b0}} }>> next_subaddr); - end else begin - { mem_data, rnxt_data } <= {rnxt_data,{(MW ){1'b0}} }; - { mem_strb, rnxt_strb } <= {rnxt_strb,{(MW/8){1'b0}} }; - end - end else begin - rnxt_data <= 0; - rnxt_strb <= 0; - mem_strb <= 0; - - if (S_ASYNC_VALID) - begin - mem_data <= { S_ASYNC_DATA, {(MW-32){1'b0}} } >> (next_subaddr*8); - mem_strb <= { 4'hf, {(MW/8-4){1'b0}} } >> (next_subaddr); - end - end - - generate if (OPT_LITTLE_ENDIAN) - begin : GEN_LIL_ENDIAN_SWAP - reg [MW/8-1:0] swap_strb; - reg [MW-1:0] swap_data; - integer ik; - - always @(*) - for(ik=0; ik 2); - load_crc <= 1'b0; - end else if (i_cfg_ddr) - begin - data_phase <= (rail_count > 16*2+2); - load_crc <= (rail_count <= 16*2+2)&&(rail_count > 2) && i_crc_en; - end else begin - data_phase <= (rail_count > 18); - load_crc <= (rail_count <= 18)&&(rail_count > 2) && i_crc_en; - end - - if (rail_count < 2) - rail_count <= 0; - // }}} - end else if (i_rx_strb[1]) - begin - // {{{ - rail_count <= rail_count - 1; - last_strb <= (rail_count == 2); - - if (!i_crc_en) - begin - data_phase <= (rail_count > 1); - load_crc <= 1'b0; - end else if (i_cfg_ddr) - begin - data_phase <= (rail_count > 16*2+1); - load_crc <= (rail_count <= 16*2+1)&&(rail_count > 1); - end else begin - data_phase <= (rail_count > 17); - load_crc <= (rail_count <= 17)&&(rail_count > 1); - end - - if (rail_count < 1) - rail_count <= 0; - // }}} - end - end else if (S_ASYNC_VALID) - begin - // {{{ - rail_count <= rail_count - 4; - last_strb <= 0; - - if (!i_crc_en) - begin - data_phase <= (rail_count > 4); - load_crc <= 1'b0; - end else if (i_cfg_ddr) - begin - data_phase <= (rail_count > 32+4); - load_crc <= (rail_count <= 32+4)&&(rail_count > 4); - end else begin - data_phase <= (rail_count > 16+4); - load_crc <= (rail_count <= 16+4)&&(rail_count > 4); - end - - if ((rail_count < 4)||(i_cfg_ddr && rail_count < 8)) - rail_count <= 0; - // }}} - end - - always @(posedge i_clk) - if (i_reset || o_done || !i_rx_en || !i_crc_en) - begin - pending_crc <= 1'b0; - end else if ((i_rx_en && !busy) || load_crc || data_phase) - pending_crc <= 1'b1; - else if (!load_crc) - pending_crc <= 1'b0; - - always @(*) - begin - w_done = !(data_phase || pending_crc || s2_valid - || sync_fill[4:3] != 2'b00 || mem_valid); - if (r_watchdog) - w_done = 1'b1; - if (!busy) - w_done = 1'b0; - end - - always @(posedge i_clk) - if (i_reset) - busy <= 0; - else if (!busy) - busy <= i_rx_en && i_length > 0 && !o_done; - else if (w_done) - busy <= 1'b0; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // CRC checking - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate for(gk=0; gk= 1 && i_cfg_width == WIDTH_1W) - || (gk >= 4 && i_cfg_width == WIDTH_4W)) - pedge_crc <= 0; - else if (!i_cfg_ds || !OPT_DS) - begin // CRC based upon synchronous inputs - // {{{ - if (i_rx_strb == 2'b11 && !i_cfg_ddr && !last_strb) - pedge_crc <= STEPCRC(STEPCRC(pedge_crc, - i_rx_data[8+gk]), - i_rx_data[ gk]); - else if (i_rx_strb[1] && (!i_cfg_ddr || !rail_count[0])) - pedge_crc <= STEPCRC(pedge_crc,i_rx_data[8+gk]); - else if (i_rx_strb[0] && rail_count[0] && i_cfg_ddr) - pedge_crc <= STEPCRC(pedge_crc,i_rx_data[0+gk]); - // }}} - end else if (S_ASYNC_VALID) - begin // Asynchronous CRC generation - // {{{ - // Note that in ASYNC mode, all rails are used - if (i_cfg_ddr) - begin - pedge_crc <= STEPCRC( STEPCRC(pedge_crc, - S_ASYNC_DATA[gk+24]), - S_ASYNC_DATA[gk+ 8]); - end else begin - pedge_crc <= STEPCRC( STEPCRC( - STEPCRC( STEPCRC(pedge_crc, - S_ASYNC_DATA[gk+24]), - S_ASYNC_DATA[gk+16]), - S_ASYNC_DATA[gk+ 8]), - S_ASYNC_DATA[gk ]); - end - // }}} - end - // }}} - - // nedge_crc: NEGEDGE Calculate the CRC for each rail - // {{{ - initial nedge_crc = 0; - always @(posedge i_clk) - if (i_reset || !i_rx_en || !i_crc_en || (!data_phase&&!load_crc) - || !i_cfg_ddr) - nedge_crc <= 0; - else if ((gk >= 1 && i_cfg_width == WIDTH_1W) - || (gk >= 4 && i_cfg_width == WIDTH_4W)) - // Zero out any unused rails - nedge_crc <= 0; - else if (!i_cfg_ds || !OPT_DS) - begin // CRC based upon synchronous inputs - // {{{ - if (i_rx_strb[1] && rail_count[0]) - nedge_crc <= STEPCRC(nedge_crc, i_rx_data[8+gk]); - else if (i_rx_strb[0] && !rail_count[0]) - nedge_crc <= STEPCRC(nedge_crc, i_rx_data[0+gk]); - // }}} - end else if (S_ASYNC_VALID) - begin // Asynchronous CRC generation - // {{{ - // Note that in ASYNC mode, all rails are used (IIRC) - nedge_crc <= STEPCRC( STEPCRC(nedge_crc, - S_ASYNC_DATA[gk+16]), - S_ASYNC_DATA[gk ]); - // }}} - end - // }}} - - always @(posedge i_clk) - if (i_reset || !i_rx_en || !i_crc_en || data_phase || load_crc) - begin - lcl_err <= 2'b00; - end else begin - lcl_err[0] <= (pedge_crc != 0); - - lcl_err[1] <= (nedge_crc != 0) && i_cfg_ddr; - end - - assign err[gk] = lcl_err[0]; - assign err[gk+NUMIO] = lcl_err[1]; - end endgenerate - - initial o_done = 0; - always @(posedge i_clk) - if (i_reset || !i_rx_en || o_done || !busy) - { o_done, o_err } <= 0; - else if (w_done) - begin - o_done <= 1'b1; - o_err <= |err; - end - - function automatic [NCRC-1:0] STEPCRC(reg[NCRC-1:0] prior, - input i_crc_data); - begin - if (prior[NCRC-1] ^ i_crc_data) - STEPCRC = { prior[NCRC-2:0], 1'b0 } ^ CRC_POLYNOMIAL; - else - STEPCRC = { prior[NCRC-2:0], 1'b0 }; - end endfunction - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Watchdog timeout - // {{{ - - always @(posedge i_clk) - if (i_reset || !i_rx_en || (!r_watchdog && - (((!OPT_DS || !i_cfg_ds) && i_rx_strb != 0) - || (OPT_DS && i_cfg_ds && S_ASYNC_VALID)))) - begin - r_watchdog <= 0; - r_timeout <= -1; - end else if (r_timeout != 0) - begin - r_watchdog <= (r_timeout <= 1); - r_timeout <= r_timeout - 1; - end - // }}} - - function automatic [$clog2(MW/8):0] COUNTONES(input [MW/8-1:0] set); - integer ik; - begin - COUNTONES=0; - for(ik=0; ik 0); - if (i_cfg_ds) - begin - assume(i_length[1:0] == 2'b00); - end else if (i_cfg_ddr && i_cfg_width >= WIDTH_8W) - assume(i_length[0] == 1'b0); - end - - always @(*) - if (i_cfg_ds) assume(i_cfg_width == WIDTH_8W && i_cfg_ddr); - - always @(*) - if (!i_reset) - begin - assume(i_cfg_width != 2'b11); - assume(i_length <= 16'h8000); - end - - always @(posedge i_clk) - if (i_reset) - f_state <= 1'b0; - else if (o_done) - f_state <= 1'b0; - else if (i_rx_en) - f_state <= 1'b1; - - always @(posedge i_clk) - if (!i_reset && !r_watchdog) - begin - if (busy || data_phase || load_crc || o_done - || s2_valid || o_mem_valid) - begin - assert(f_state); - end else begin - assert(!f_state || $past(o_mem_valid)); - end - - if (load_crc || data_phase) - assert(busy || r_watchdog); - end - - always @(posedge i_clk) - if (!i_reset && o_err) - assert(i_crc_en && o_done); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // PHY assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!i_reset && $past(!i_rx_en)) - begin - assume(i_rx_strb == 0); - assume(S_ASYNC_VALID == 0); - end - - always @(*) - if (!i_rx_strb[1]) - assume(!i_rx_strb[0]); - - always @(*) - if (!OPT_DS) - assume(!S_ASYNC_VALID); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Counting - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // f_count: count received bits - // {{{ - initial f_count = 0; - always @(posedge i_clk) - if (i_reset || !i_rx_en) - f_count <= 0; - else if (data_phase || load_crc) - begin - if (i_cfg_ds) - begin - if (S_ASYNC_VALID) - f_count <= f_count + 32; - end else case(i_cfg_width) - WIDTH_1W: f_count <= f_count + (i_rx_strb[1] ? 1:0) - + (i_rx_strb[0] ? 1:0); - WIDTH_4W: f_count <= f_count + (i_rx_strb[1] ? 4:0) - + (i_rx_strb[0] ? 4:0); - default: f_count <= f_count + (i_rx_strb[1] ? 8:0) - + (i_rx_strb[0] ? 8:0); - endcase - end - - always @(posedge i_clk) - if (!i_reset && i_rx_en) - begin - if (i_cfg_ds) - begin - assert(f_count[4:0] == 0); - end else case(i_cfg_width) - WIDTH_1W: begin end - WIDTH_4W: assert(f_count[1:0] == 2'b0); - WIDTH_8W: assert(f_count[2:0] == 3'b0); - endcase - - if (!i_cfg_ds && data_phase) - assert(f_count[2:0] == sync_fill[2:0]); - end - // }}} - - // fmem_count - // {{{ - always @(posedge i_clk) - if (!i_rx_en) - fmem_count <= 0; - else if (o_mem_valid) - fmem_count <= fmem_count + $countones(o_mem_strb); - // }}} - - always @(posedge i_clk) - if (!i_reset) - assert(s2_valid == (s2_fill != 0)); - - always @(posedge i_clk) - if (!i_reset && i_rx_en && (i_cfg_ds && OPT_DS)) - assert(!s2_valid); - - always @(posedge i_clk) - if (i_reset || !i_rx_en) - begin end - else if (!$past(i_rx_en)) - assert(sync_fill == 0); - else case(i_cfg_width) - WIDTH_1W: assert(sync_fill <= 5'd9); - WIDTH_4W: assert(sync_fill[1:0] == 2'b00 && sync_fill <= 5'd12); - WIDTH_8W: assert(sync_fill[2:0] == 3'b00 && sync_fill <= 5'd16); - default: assert(0); - endcase - - always @(*) - begin - // Relate the two counts together - // fmem_count - // + (o_mem_valid ? $countones(o_mem_strb) - // + (s2_valid ? s2_fill - // + sync_fill[4:3] - // ====================== - // f_count - - f_recount = fmem_count; - if (o_mem_valid) - f_recount = f_recount + $countones(o_mem_strb); - if (rnxt_strb) - f_recount = f_recount + 1; - if (!i_cfg_ds || !OPT_DS) - begin - if (s2_valid) - f_recount = f_recount + s2_fill; - f_recount = f_recount + sync_fill[4:3]; - end - end - - always @(posedge i_clk) - if (!i_reset && i_rx_en && data_phase && !r_watchdog) - begin - // reg [LGLEN:0] fmem_count, f_recount; - assert(f_count[LGLEN+3:3] == f_recount); - end - - always @(posedge i_clk) - if (!i_reset && i_rx_en && o_mem_valid) - begin - if (i_cfg_ds) - begin - assert($countones(o_mem_strb) == 4); - end else case(i_cfg_width) - WIDTH_1W: assert($countones(o_mem_strb) == 1); - WIDTH_4W: assert($countones(o_mem_strb) == 1); - WIDTH_8W: begin end // assert($countones(o_mem_strb) <= 2 + ($past(rnxt_strb) ? 1:0)); - default: assert(0); - endcase - end - - // Relate the rail_count to f_count - // {{{ - always @(posedge i_clk) - if (!i_reset && i_rx_en) - begin - case(i_cfg_width) - WIDTH_1W: if (!i_crc_en) - begin - assert(rail_count <= (i_length*8)); - end else if (i_cfg_ddr) - begin - assert(rail_count <= (i_length*8) + 32); - end else - assert(rail_count <= (i_length*8) + 16); - WIDTH_4W: if (!i_crc_en) - begin - assert(rail_count <= (i_length*2)); - end else if (i_cfg_ddr) - begin - assert(rail_count <= (i_length*2 + 32)); - end else - assert(rail_count <= (i_length*2 + 16)); - WIDTH_8W: if (!i_crc_en) - begin - assert(rail_count <= i_length); - end else if (i_cfg_ddr) - begin - assert(rail_count <= (i_length + 32)); - end else - assert(rail_count <= (i_length + 16)); - default: assert(0); - endcase - - if (!i_crc_en) - begin - assert(!load_crc); - assert(!pending_crc); - assert(data_phase == (rail_count > 0)); - end else if (i_cfg_ddr) - begin - assert(data_phase == (rail_count > 32)); - assert(load_crc == (rail_count <= 32 && rail_count>0)); - end else begin - assert(data_phase == (rail_count > 16)); - assert(load_crc == (rail_count <= 16 && rail_count>0)); - end - - if (i_crc_en && (load_crc || data_phase)) - assert(pending_crc); - assert(last_strb == (rail_count == 1)); - end - - always @(posedge i_clk) - if (!i_reset && i_rx_en && busy && (data_phase || load_crc)) - begin - casez({ i_crc_en, i_cfg_ddr, i_cfg_width }) - { 1'b0, 1'b?, WIDTH_1W }: begin - assert(rail_count + f_count == i_length*8); - assert(f_count <= i_length*8); - assert(rail_count <= i_length*8); - end - { 2'b10, WIDTH_1W }: begin - assert(rail_count + f_count == i_length*8+16); - assert(f_count <= i_length*8+16); - assert(rail_count <= i_length*8+16); - end - { 2'b11, WIDTH_1W }: begin - assert(rail_count + f_count == i_length*8+32); - assert(f_count <= i_length*8+32); - assert(rail_count <= i_length*8+32); - end - { 1'b0, 1'b?, WIDTH_4W }: begin - assert(rail_count + (f_count>>2) == i_length*2); - assert((f_count>>2) <= i_length*2); - assert(rail_count <= i_length*2); - end - { 2'b10, WIDTH_4W }: begin - assert(rail_count + (f_count>>2) == i_length*2+16); - assert((f_count>>2) <= i_length*2+16); - assert(rail_count <= i_length*2+16); - end - { 2'b11, WIDTH_4W }: begin - assert(rail_count + (f_count>>2) == i_length*2+32); - assert((f_count>>2) <= i_length*2+32); - assert(rail_count <= i_length*2+32); - end - { 1'b0, 1'b?, WIDTH_8W }: begin - assert(rail_count + (f_count>>3) == i_length); - assert((f_count>>3) <= i_length); - assert(rail_count <= i_length); - end - { 2'b10, WIDTH_8W }: begin - assert(rail_count + (f_count>>3) == i_length+16); - assert((f_count>>3) <= i_length+16); - assert(rail_count <= i_length+16); - end - { 2'b11, WIDTH_8W }: begin - assert(rail_count+(f_count>>3) == i_length+32); - assert((f_count>>3) <= i_length+32); - assert(rail_count <= i_length+32); - end - default: assert(0); - endcase - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Memory interface - // {{{ - - always @(posedge i_clk) - if (!i_reset && i_rx_en && fmem_count == 0) - assert(!mem_full); - - always @(*) - if (o_mem_valid) - f_next_subaddr = subaddr + $countones(o_mem_strb) - + (rnxt_strb ? 1:0); - else - f_next_subaddr = subaddr; - - always @(posedge i_clk) - if (i_reset) - begin end else - assert(f_next_subaddr == next_subaddr); - - always @(posedge i_clk) - if (!i_reset && rnxt_strb) - assert(o_mem_valid); - - always @(posedge i_clk) - if (!i_reset && i_rx_en && mem_full) - assert({ mem_addr, subaddr } == 0); - - always @(*) - if (!i_reset && i_rx_en) - assert({ mem_full, o_mem_addr, subaddr } == fmem_count); - - always @(posedge i_clk) - if (!i_reset && !i_rx_en) - assert(!o_mem_valid); - else if (!i_reset && o_mem_valid) - assert(o_mem_strb != 0); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract - // {{{ - - // Assume the known receive value - // {{{ - always @(posedge i_clk) - if (i_rx_en && f_count[LGLEN+3:5] == fc_posn[LGLEN:2] - && i_cfg_ds && S_ASYNC_VALID) - begin - case(fc_posn[1:0]) - 2'b00: assume(S_ASYNC_DATA[31:24] == fc_data); - 2'b01: assume(S_ASYNC_DATA[23:16] == fc_data); - 2'b10: assume(S_ASYNC_DATA[15: 8] == fc_data); - 2'b11: assume(S_ASYNC_DATA[ 7: 0] == fc_data); - endcase - end - - always @(posedge i_clk) - if (i_rx_en && !i_cfg_ds && i_cfg_width == WIDTH_1W) - begin - // {{{ - if (i_rx_strb[1] && f_count == { fc_posn, 3'd0 }) - assume(i_rx_data[8] == fc_data[7]); - if (i_rx_strb[1] && f_count == { fc_posn, 3'd1 }) - assume(i_rx_data[8] == fc_data[6]); - if (i_rx_strb[1] && f_count == { fc_posn, 3'd2 }) - assume(i_rx_data[8] == fc_data[5]); - if (i_rx_strb[1] && f_count == { fc_posn, 3'd3 }) - assume(i_rx_data[8] == fc_data[4]); - if (i_rx_strb[1] && f_count == { fc_posn, 3'd4 }) - assume(i_rx_data[8] == fc_data[3]); - if (i_rx_strb[1] && f_count == { fc_posn, 3'd5 }) - assume(i_rx_data[8] == fc_data[2]); - if (i_rx_strb[1] && f_count == { fc_posn, 3'd6 }) - assume(i_rx_data[8] == fc_data[1]); - if (i_rx_strb[1] && f_count == { fc_posn, 3'd7 }) - assume(i_rx_data[8] == fc_data[0]); - - if (i_rx_strb[0] && f_count + 1 == { fc_posn, 3'd0 }) - assume(i_rx_data[0] == fc_data[7]); - if (i_rx_strb[0] && f_count + 1 == { fc_posn, 3'd1 }) - assume(i_rx_data[0] == fc_data[6]); - if (i_rx_strb[0] && f_count + 1 == { fc_posn, 3'd2 }) - assume(i_rx_data[0] == fc_data[5]); - if (i_rx_strb[0] && f_count + 1 == { fc_posn, 3'd3 }) - assume(i_rx_data[0] == fc_data[4]); - if (i_rx_strb[0] && f_count + 1 == { fc_posn, 3'd4 }) - assume(i_rx_data[0] == fc_data[3]); - if (i_rx_strb[0] && f_count + 1 == { fc_posn, 3'd5 }) - assume(i_rx_data[0] == fc_data[2]); - if (i_rx_strb[0] && f_count + 1 == { fc_posn, 3'd6 }) - assume(i_rx_data[0] == fc_data[1]); - if (i_rx_strb[0] && f_count + 1 == { fc_posn, 3'd7 }) - assume(i_rx_data[0] == fc_data[0]); - // }}} - end - - always @(posedge i_clk) - if (i_rx_en && !i_cfg_ds && i_cfg_width == WIDTH_4W) - begin - // {{{ - if (f_count == { fc_posn, 3'd0 } && i_rx_strb[1]) - assume(i_rx_data[11:8] == fc_data[7:4]); - if (f_count == { fc_posn, 3'd4 } && i_rx_strb[1]) - assume(i_rx_data[11:8] == fc_data[3:0]); - - if (f_count +4 == { fc_posn, 3'd0 } && i_rx_strb[0]) - assume(i_rx_data[ 3: 0] == fc_data[7:4]); - if (f_count +4 == { fc_posn, 3'd4 } && i_rx_strb[0]) - assume(i_rx_data[ 3: 0] == fc_data[3:0]); - // }}} - end - - always @(posedge i_clk) - if (i_rx_en && !i_cfg_ds && i_cfg_width == WIDTH_8W) - begin - if (f_count == { fc_posn, 3'b0 } && i_rx_strb[1]) - assume(i_rx_data[15:8] == fc_data); - if (f_count + 8 == { fc_posn, 3'b0 } && i_rx_strb[0]) - assume(i_rx_data[ 7:0] == fc_data); - end - // }}} - - // Assert the value if it's in our pipeline, perhaps stalled somewhere - // {{{ - always @(*) - if (!i_reset && i_rx_en && !i_cfg_ds && sync_fill != 0 - && i_cfg_width == WIDTH_1W && f_count[LGLEN+3:3] == fc_posn) - begin - case(sync_fill[2:0]) - 3'd0: begin end // Nothing loaded, nothing to assert - 3'd1: assert(sync_sreg[0:0] == fc_data[7:7]); - 3'd2: assert(sync_sreg[1:0] == fc_data[7:6]); - 3'd3: assert(sync_sreg[2:0] == fc_data[7:5]); - 3'd4: assert(sync_sreg[3:0] == fc_data[7:4]); - 3'd5: assert(sync_sreg[4:0] == fc_data[7:3]); - 3'd6: assert(sync_sreg[5:0] == fc_data[7:2]); - 3'd7: assert(sync_sreg[6:0] == fc_data[7:1]); - endcase - end - - always @(*) - if (!i_reset && i_rx_en && !i_cfg_ds && sync_fill != 0 - && i_cfg_width == WIDTH_4W && f_count == { fc_posn, 3'd4 }) - begin - assert(sync_sreg[3:0] == fc_data[7:4]); - end - // }}} - - // Assert the known value out - // {{{ - always @(*) - begin - fmem_data = mem_data << (8*fc_posn[$clog2(MW/8)-1:0]); - fmem_strb = mem_strb << (fc_posn[$clog2(MW/8)-1:0]); - end - - always @(posedge i_clk) - if (!i_reset && i_rx_en && o_mem_valid) - begin - if ((o_mem_addr == fc_posn[LGLEN:$clog2(MW/8)]) - && mem_strb[(MW/8-1)-fc_posn[$clog2(MW/8)-1:0]]) - begin - // Assume big-endian ordering - assert(fmem_data[MW-1:MW-8] == fc_data); - assert(fmem_strb); - end - end - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - always @(posedge i_clk) - if (!i_reset && i_rx_en && o_done) - begin - case({ i_cfg_ds, i_cfg_ddr, i_cfg_width }) - 4'b0000: begin - cover(!i_crc_en); - cover(o_err); // !!! - cover(i_crc_en && !o_err); - end - 4'b0001: begin - cover(!i_crc_en); -cover(fc_posn == 0 && fc_data == 8'hff); -cover(fc_posn == 0 && fc_data == 8'ha5); -cover(fc_posn == 0 && fc_data == 8'h5a); -cover(fc_posn == 0 && fc_data == 8'h7e); - cover(o_err); // !!! - cover(i_crc_en && !o_err); - end - 4'b0010: begin - cover(!i_crc_en); - cover(o_err); // !!! - cover(i_crc_en && !o_err); - end - 4'b0100: begin - cover(!i_crc_en); - cover(o_err); // !!! - cover(i_crc_en && !o_err); - end - 4'b0101: begin - cover(!i_crc_en); - cover(o_err); // !!! - cover(i_crc_en && !o_err); - end - 4'b0110: begin - cover(!i_crc_en); - cover(o_err); // !!! - cover(i_crc_en && !o_err); - end - // 4'b1110: cover(1); - default: begin end - endcase - end - - generate if (OPT_DS) - begin : CVR_DATA_STROBE - always @(posedge i_clk) - if (!i_reset && i_rx_en && o_done) - begin - case({ i_cfg_ds, i_cfg_ddr, i_cfg_width }) - // 4'b0000: cover(1); - // 4'b0001: cover(1); - // 4'b0010: cover(1); - // 4'b0100: cover(1); - // 4'b0101: cover(1); - // 4'b0110: cover(1); - 4'b1110: begin - cover(!i_crc_en); - cover(o_err); - cover(i_crc_en && !o_err); - end - default: begin end - endcase - end - - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Careless assumptions - // {{{ - - // always @(*) assume(!r_watchdog); - // }}} -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/sdspi/sdspi.v b/delete_later/rtl/sdspi/sdspi.v deleted file mode 100644 index 8c8ff8b..0000000 --- a/delete_later/rtl/sdspi/sdspi.v +++ /dev/null @@ -1,1031 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sdspi.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: SD Card controller, using SPI interface with the card and -// WB interface with the rest of the system. This is the top -// level of the SPI based controller. -// -// See the specification for more information. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// License: GPL, v3, as defined and found on www.gnu.org, -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module sdspi #( - // {{{ - parameter [0:0] OPT_CARD_DETECT = 1'b1, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - // - // LGFIFOLN - // {{{ - // LGFIFOLN defines the size of the internal memory in words. - // An LGFIFOLN of 7 is appropriate for a 2^(7+2)=512 byte FIFO - parameter LGFIFOLN = 7, - // }}} - parameter POWERUP_IDLE = 1000, - // STARTUP_CLOCKS - // {{{ - // Many SD-Cards require a minimum number of SPI clocks to get - // them started. STARTUP_CLOCKS defines this number. Set this - // to zero if you don't want to use this initialization - // sequence. - parameter STARTUP_CLOCKS = 75, - // }}} - // CKDIV_BITS - // {{{ - // For my first design, using an 80MHz clock, 7 bits to the - // clock divider was plenty. Now that I'm starting to use - // faster and faster designs, it becomes important to - // parameterize the number of bits in the clock divider. More - // than 8, however, and the interface will need to change. - parameter CKDIV_BITS = 8, - // }}} - // INITIAL_CLKDIV - // {{{ - // The SPI frequency is given by the system clock frequency - // divided by a (clock_divider + 1). INITIAL_CLKDIV provides - // an initial value for this clock divider. - parameter [CKDIV_BITS-1:0] INITIAL_CLKDIV = 8'h7c, - // }}} - // OPT_SPI_ARBITRATION - // {{{ - // When I originally built this SDSPI controller, it was for an - // environment where the SPI was shared. Doing this requires - // feedback from an arbiter, to know when one SPI device has - // the bus or not. This feedback is provided in i_bus_grant. - // If you don't have an arbiter, just set i_bus_grant to the - // constant 1'b1 and set OPT_SPI_ARBITRATION to 1'b0 to remove - // this extra logic. - parameter [0:0] OPT_SPI_ARBITRATION = 1'b0, - // }}} - // - // - parameter [0:0] OPT_EXTRA_WB_CLOCK = 1'b0, - // - // - // - localparam AW = 2, DW = 32 - // }}} - ) ( - // {{{ - input wire i_clk, i_sd_reset, - // Wishbone interface - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [AW-1:0] i_wb_addr, - input wire [DW-1:0] i_wb_data, - input wire [DW/8-1:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [DW-1:0] o_wb_data, - // }}} - // SDCard interface - // {{{ - output wire o_cs_n, o_sck, o_mosi, - input wire i_miso, i_card_detect, - // }}} - // Our interrupt - output reg o_int, - // .. and whether or not we can use the SPI port - input wire i_bus_grant, - // And some wires for debugging it all - // - output reg [DW-1:0] o_debug - // }}} - ); - - // Signal / parameter declarations - // {{{ - localparam [1:0] SDSPI_CMD_ADDRESS = 2'b00, - SDSPI_DAT_ADDRESS = 2'b01, - SDSPI_FIFO_A_ADDR = 2'b10, - SDSPI_FIFO_B_ADDR = 2'b11; - - localparam BLKBASE = 16; - - // - // Command register bit definitions - // - localparam CARD_REMOVED_BIT= 18, - // CRCERR_BIT = 16, - ERR_BIT = 15, - FIFO_ID_BIT = 12, - USE_FIFO_BIT = 11, - FIFO_WRITE_BIT = 10; - // - // Some WB simplifications: - // - reg r_cmd_busy; - - reg dbg_trigger; - - wire wb_stb, write_stb, wb_cmd_stb, new_data; - wire [AW-1:0] wb_addr; - wire [DW-1:0] wb_data; - wire [3:0] wb_sel; - reg [1:0] pipe_addr; - reg dly_stb; - - reg [31:0] fifo_a [0:((1<= 3) - &&(r_data_reg[BLKBASE +: 4] <= max_lgblklen)) - r_lgblklen <= r_data_reg[BLKBASE +: 4]; - end - // if (r_lgblklen > max_lgblklen) - // r_lgblklen <= max_lgblklen; - - if (!card_present) - r_sdspi_clk <= INITIAL_CLKDIV; - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone return logic - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - pipe_addr <= wb_addr; - - always @(*) - card_status = { 8'h00, // 8b - 2'b0, r_watchdog_err, i_sd_reset, // 4b - !card_present, card_removed, 1'b0, 1'b0, - r_cmd_err, r_cmd_busy, 1'b0, r_fifo_id, // 4b - r_use_fifo, write_to_card, 2'b00, // 4b - r_last_r_one }; // 8b - - always @(posedge i_clk) - case(pipe_addr) - SDSPI_CMD_ADDRESS: - o_wb_data <= card_status; - SDSPI_DAT_ADDRESS: - o_wb_data <= r_data_reg; - SDSPI_FIFO_A_ADDR: - o_wb_data <= fifo_a_word; - SDSPI_FIFO_B_ADDR: - o_wb_data <= fifo_b_word; - endcase - - initial dly_stb = 0; - always @(posedge i_clk) - if (!i_wb_cyc) - dly_stb <= 0; - else - dly_stb <= wb_stb; - - initial o_wb_ack = 0; - always @(posedge i_clk) - if (!i_wb_cyc) - o_wb_ack <= 1'b0; - else - o_wb_ack <= dly_stb; - - assign o_wb_stall = 1'b0; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Interrupt generation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - initial last_busy = 0; - always @(posedge i_clk) - last_busy <= r_cmd_busy; - - initial o_int = 0; - always @(posedge i_clk) - o_int <= (!r_cmd_busy)&&(last_busy) - ||(!card_removed && !card_present); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Card detection logic --- is the card even present? - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Depends upon the i_card_detect signal. Set this signal to 1'b1 if - // you your device doesn't have it. - // - // - generate if (OPT_CARD_DETECT) - begin : GEN_CARD_DETECT - reg [2:0] raw_card_present; - reg [9:0] card_detect_counter; - reg r_card_removed, r_card_present; - - initial r_card_removed = 1'b1; - always @(posedge i_clk) - if (i_sd_reset) - r_card_removed <= 1'b1; - else if (!card_present) - r_card_removed <= 1'b1; - else if (wb_cmd_stb && wb_data[CARD_REMOVED_BIT]) - r_card_removed <= 1'b0; - - initial raw_card_present = 0; - always @(posedge i_clk) - raw_card_present <= { raw_card_present[1:0], i_card_detect }; - - initial card_detect_counter = 0; - always @(posedge i_clk) - if (i_sd_reset || !raw_card_present[2]) - card_detect_counter <= 0; - else if (!(&card_detect_counter)) - card_detect_counter <= card_detect_counter + 1; - - initial r_card_present = 1'b0; - always @(posedge i_clk) - if (i_sd_reset || !raw_card_present[2]) - r_card_present <= 1'b0; - else if (&card_detect_counter) - r_card_present <= 1'b1; - - assign card_present = r_card_present; - assign card_removed = r_card_removed; - - end else begin : NO_CARD_DETECT_SIGNAL - - assign card_present = 1'b1; - assign card_removed = 1'b0; - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Watchdog protection logic - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // Some watchdog logic for us. This way, if we are waiting for the - // card to respond, and something goes wrong, we can timeout the - // transaction and ... figure out what to do about it later. At least - // we'll have an error indication. - // - initial r_watchdog_err = 1'b0; - always @(posedge i_clk) - if (!r_cmd_busy) - r_watchdog_err <= 1'b0; - else if (r_watchdog == 0) - r_watchdog_err <= 1'b1; - - initial r_watchdog = 26'h3ffffff; - always @(posedge i_clk) - if (!r_cmd_busy) - r_watchdog <= 26'h3fffff; - else if (|r_watchdog) - r_watchdog <= r_watchdog - 26'h1; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Debug signals - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial dbg_trigger = 0; - always @(posedge i_clk) - dbg_trigger <= (cmd_valid)&&(cmd_response[38:33] != 0); - - always @(posedge i_clk) - o_debug <= { dbg_trigger, ll_cmd_stb, - (ll_cmd_stb & ll_idle), ll_out_stb, // 4'h - o_cs_n, o_sck, o_mosi, i_miso, // 4'h - 3'b000, i_sd_reset, // 4'h - 3'b000, r_cmd_busy, // 4'h - ll_cmd_dat, // 8'b - ll_out_dat }; // 8'b - // }}} - - // Make verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_wb_sel, cmd_sent, - spi_read_from_fifo }; - // verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal verification properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH = 3; - wire [F_LGDEPTH-1:0] f_nacks, f_nreqs, f_outstanding; - reg f_past_valid; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - //////////////////////////////////////////////////////////////////////// - // - // Wishbone Bus properties - // - //////////////////////////////////////////////////////////////////////// - // - // - fwb_slave #( - .AW(2), .DW(32), - .F_LGDEPTH(F_LGDEPTH), - .F_MAX_STALL(1), - .F_MAX_ACK_DELAY(2), - .F_OPT_DISCONTINUOUS(1), - .F_OPT_MINCLOCK_DELAY(1) - ) fwb( - .i_clk(i_clk), .i_reset(!f_past_valid), - .i_wb_cyc(i_wb_cyc), .i_wb_stb(i_wb_stb), .i_wb_we(i_wb_we), - .i_wb_addr(i_wb_addr),.i_wb_data(i_wb_data),.i_wb_sel(i_wb_sel), - .i_wb_stall(o_wb_stall), .i_wb_ack(o_wb_ack), - .i_wb_idata(o_wb_data), .i_wb_err(1'b0), - .f_nreqs(f_nreqs), .f_nacks(f_nacks), - .f_outstanding(f_outstanding) - ); - - always @(*) - if (i_wb_cyc) - assert(f_outstanding == (o_wb_ack ? 1:0) + (dly_stb ? 1:0) - + (OPT_EXTRA_WB_CLOCK ? wb_stb : 0)); - - //////////////////////////////////////////////////////////////////////// - // - // Contract checks - // - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - assert(!tx_busy || !rx_busy); - - always @(*) - assert(!tx_start || !rx_start); - - always @(*) - if (!r_use_fifo) - begin - assert(!tx_start && !rx_start); - assert(!tx_busy && !rx_busy); - if(!write_to_card) - assert(!rx_start && !rx_busy); - else - assert(!tx_start && !tx_busy); - end - - always @(*) - if (tx_busy || rx_busy || cmd_busy) - assert(r_cmd_busy); - - always @(*) - begin - assert(r_lgblklen >= 3); - assert(r_lgblklen <= 9); - end - - always @(*) - if (cmd_busy) - begin - assert(spi_read_addr[LGFIFOLN-1:0] <= 1); - assert(spi_write_addr[LGFIFOLN-1:0] <= 1); - end - - // - // Command sequence check - (* anyseq *) reg f_cmd_check_value; - reg [1:0] f_cmd_seq; - reg [7:0] f_cmd_byte; -`ifdef VERIFIC - always @(posedge i_clk) - if (f_cmd_check_value && f_cmd_seq == 0 && cmd_out_stb && !spicmdi.i_ll_busy) - f_cmd_byte <= cmd_out_byte; - - initial f_cmd_seq = 0; - always @(posedge i_clk) - if (i_sd_reset || r_watchdog_err) - f_cmd_seq <= 0; - else if (f_cmd_check_value && f_cmd_seq == 0 && cmd_out_stb && !spicmdi.i_ll_busy) - f_cmd_seq <= 1; - else if (!ll_cmd_stb || ll_idle) - f_cmd_seq <= f_cmd_seq << 1; - - always @(*) - if (!i_sd_reset && !r_watchdog_err) case(f_cmd_seq) - 0: begin end - 1: begin - assert(ll_cmd_stb); - assert(ll_cmd_dat == f_cmd_byte); - end - 2: begin - end - endcase -`endif - - //////////////////////////////////////////////////////////////////////// - // - // Abstract LLSDSPI properties - // - //////////////////////////////////////////////////////////////////////// - // - // -//`ifdef ABSTRACT_LLSDSPI -//`define LLSDSPI_ASSERT assume -//`else -//`define LLSDSPI_ASSERT assert -//`endif -// reg f_first_byte_accepted; -// -// always @(posedge i_clk) -// if (!f_past_valid) -// `LLSDSPI_ASSERT(!ll_out_stb); -// else if (!$past(r_cmd_busy)) -// `LLSDSPI_ASSERT(!ll_out_stb); -// else if ($past(ll_out_stb)) -// `LLSDSPI_ASSERT(!ll_out_stb); -// -// always @(posedge i_clk) -// if (!r_cmd_busy) -// f_first_byte_accepted <= 1'b0; -// else if (ll_cmd_stb && ll_idle) -// f_first_byte_accepted <= 1'b1; -// -// always @(posedge i_clk) -// if (f_past_valid && $past(f_past_valid)) -// begin -// if ($rose(r_cmd_busy)) -// begin -// assert($rose(ll_cmd_stb)); -// `LLSDSPI_ASSERT(!ll_out_stb); -// end else if (r_cmd_busy && f_first_byte_accepted && $past(f_first_byte_accepted)) -// `LLSDSPI_ASSERT(ll_out_stb == $past(ll_idle)); -// end -// -// always @(posedge i_clk) -// if (f_past_valid) -// begin -// if ($past(i_sd_reset || r_watchdog_err)) -// assert(!r_cmd_busy); -// else if ($past(r_cmd_busy && ll_out_stb && !ll_idle)) -// begin -// assert(ll_out_stb); -// assert($stable(ll_out_dat)); -// end -// end - - //////////////////////////////////////////////////////////////////////// - // - // Watchdog checks - // - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - if (f_past_valid && $past(r_watchdog_err)) - assert(!cmd_busy && !tx_busy && !rx_busy); - - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - begin - cover(cmd_sent && !r_cmd_busy); - cover(tx_busy && tx_start); - cover(rx_busy && rx_start); - end - - always @(posedge i_clk) - if (f_past_valid && !$past(i_sd_reset) && !$past(r_watchdog_err)) - begin - cover($fell(cmd_busy)); - cover($fell(tx_busy)); - cover($fell(rx_busy)); - cover($fell(r_cmd_busy)); - end - - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // - //////////////////////////////////////////////////////////////////////// - // - // - // always @(*) - // assume(!r_watchdog_err); -`endif -// }}} -endmodule diff --git a/delete_later/rtl/sdspi/sdtxframe.v b/delete_later/rtl/sdspi/sdtxframe.v deleted file mode 100644 index 78e352d..0000000 --- a/delete_later/rtl/sdspi/sdtxframe.v +++ /dev/null @@ -1,1489 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sdtxframe.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Given a frame of data from memory, formats it for sending to -// the front end. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module sdtxframe #( - parameter NCRC = 16, - parameter [0:0] OPT_SERDES = 1'b1, - parameter [NCRC-1:0] CRC_POLYNOMIAL = 16'h1021 - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire [7:0] i_cfg_spd, - input wire [1:0] i_cfg_width, - input wire i_cfg_ddr, - // - input wire i_en, i_ckstb, i_hlfck, - // - input wire S_VALID, - output wire S_READY, - input wire [31:0] S_DATA, - input wire S_LAST, - // - output wire tx_valid, - // input wire tx_ready, - output wire [31:0] tx_data - // }}} - ); - - // Local declarations - // {{{ - localparam [1:0] P_IDLE = 2'b00, - P_DATA = 2'b01, - P_CRC = 2'b10, - P_LAST = 2'b11; - - localparam [1:0] WIDTH_1W = 2'b00, - WIDTH_4W = 2'b01, - WIDTH_8W = 2'b10; - - localparam [1:0] P_1D = 2'b00, - P_2D = 2'b01, - P_4D = 2'b10; - - reg cfg_ddr; - reg [1:0] cfg_width, cfg_period; - - - wire start_packet; - reg pre_valid; - reg [1:0] pstate; - wire pre_ready; - reg [31:0] pre_data; - reg [3:0] pre_count; - - - integer ik, jk; - reg [NCRC- 1:0] crc_1w_reg; - reg [NCRC* 2-1:0] di_crc_2w, nxt_crc_2w, new_crc_2w, crc_2w_reg; - reg [NCRC* 4-1:0] di_crc_4w, nxt_crc_4w, new_crc_4w, crc_4w_reg; - reg [NCRC* 8-1:0] di_crc_8w, nxt_crc_8w, new_crc_8w, crc_8w_reg; - reg [NCRC*16-1:0] di_crc_8d, nxt_crc_8d, new_crc_8d, crc_8d_reg; - - reg ck_valid; - reg [4:0] ck_counts; - reg [31:0] ck_data, ck_sreg; - // }}} - // Steps: #1, Packetizer: breaks incoming signal into wires - // #2, add CRC - // #3, split across clocks - // - //////////////////////////////////////////////////////////////////////// - // - // Configuration - // {{{ - initial cfg_period = 2'b00; - always @(posedge i_clk) - if (i_reset || !OPT_SERDES) - cfg_period <= P_1D; - else if (pstate == P_IDLE) - begin - if (i_cfg_ddr && i_cfg_spd == 0) - cfg_period <= P_4D; // Four data periods / clk - else if ((i_cfg_ddr && i_cfg_spd == 1) - ||(!i_cfg_ddr && i_cfg_spd == 0)) - cfg_period <= P_2D; // Two data periods / clk - else - cfg_period <= P_1D; // One data period / clk - end - - always @(posedge i_clk) - if (i_reset) - cfg_width <= WIDTH_1W; - else if (pstate == P_IDLE) - cfg_width <= i_cfg_width; - - always @(posedge i_clk) - if (i_reset) - cfg_ddr <= 1'b0; - else if (pstate == P_IDLE) - cfg_ddr <= i_cfg_ddr; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Packetizer: Add CRC(s) to the packet - // {{{ - - assign start_packet = i_en && S_VALID && i_ckstb && !tx_valid && !ck_valid; - initial pstate = P_IDLE; - initial pre_valid = 1'b0; - initial pre_data = {(32){1'b1}}; - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - pstate <= P_IDLE; - pre_valid <= 1'b0; - pre_data <= {(32){1'b1}}; - // }}} - end else case(pstate) - P_IDLE: begin - // {{{ - pstate <= P_IDLE; - pre_valid <= 0; - pre_data <= (S_VALID) ? S_DATA : {(32){1'b1}}; - if (start_packet) - begin - pstate <= (S_LAST) ? P_CRC : P_DATA; - pre_valid <= 1; - end end - // }}} - P_DATA: if (S_VALID && S_READY) - // {{{ - begin - pstate <= P_DATA; - pre_valid <= 1; - pre_data <= S_DATA; - - if (S_LAST) - pstate <= P_CRC; - end - // }}} - P_CRC: if (pre_ready) - // {{{ - begin - pre_valid <= 1'b1; - if (pre_count == 0) - pstate <= P_LAST; - - case(cfg_width) - WIDTH_1W: if (cfg_ddr) - pre_data <= crc_2w_reg[NCRC*2-1:0]; - else - pre_data <= { crc_1w_reg[NCRC-1:0], 16'hffff }; - WIDTH_4W: if (cfg_ddr) - pre_data <= crc_8w_reg[8*NCRC-1:8*NCRC-32]; - else - pre_data <= crc_4w_reg[4*NCRC-1:4*NCRC-32]; - WIDTH_8W: if (cfg_ddr) - pre_data <= crc_8d_reg[16*NCRC-1:16*NCRC-32]; - else - pre_data <= crc_8w_reg[8*NCRC-1:8*NCRC-32]; - default: pre_data <= crc_8w_reg[8*NCRC-1:8*NCRC-32]; - endcase - end - // }}} - P_LAST: begin - if (pre_ready) - begin - pre_valid <= 0; - pre_data <= {(32){1'b1}}; - end - - if (!tx_valid) - pstate <= P_IDLE; - end - endcase - - initial pre_count = 0; - always @(posedge i_clk) - if (i_reset) - pre_count <= 0; - else if (pstate == P_DATA || pstate == P_IDLE) - begin - // pre_count = - // (SDR) 16bits / wire / 32 - // (DDR) 32bits / wire / 32 - case(cfg_width) - WIDTH_1W: pre_count <= 0; - WIDTH_4W: pre_count <= (cfg_ddr) ? 3 : 1; - default: // WIDTH_8W - pre_count <= (cfg_ddr) ? 7:3; - endcase - end else if (pre_ready && pre_count != 0) - pre_count <= pre_count - 1; - - assign S_READY = pre_ready && (pstate == P_DATA || pstate == P_IDLE); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // CRC calculation - // {{{ - - // di_crc*, new_crc*, next_crc*: Advance CRC calculations combinatorialy - // {{{ - always @(*) - begin - // Notes: - // {{{ - // Why the following monstrosity? So we can read data out - // directly into the shift register(s). However, the shift - // register(s) are not sorted by rail, hence all the work - // below to first sort them by rail, adjust the CRC, then - // sort them back, etc. - // - // The good news is that, inspite of all the tortured pain - // below, it's primarily just wire assignments and - // rearrangements. The logic itself is either a shift, or - // (for 1-4 bits per CRC per step), a XOR reduction of up - // to 20 incoming bits. - // }}} - - // Pre-load the CRC fills - // {{{ - for(ik=0; ik 0) - begin // Drain the shift registers - ck_counts <= ck_counts - 1; - case(cfg_period) - P_1D: begin // One clock period of data - // {{{ - case(cfg_width) - WIDTH_1W: begin - ck_sreg <= { ck_sreg[30: 0], 1'b1 }; - ck_data <= { (4){7'h7f, ck_sreg[31] }}; - end - WIDTH_4W: begin - ck_sreg <= { ck_sreg[27: 0], 4'hf }; - ck_data <= { (4){4'hf, ck_sreg[31:28] } }; - end - default: begin // WIDTH_8W - ck_sreg <= { ck_sreg[23: 0], 8'hff }; - ck_data <= { (4){ck_sreg[31:24] } }; - end - endcase end - // }}} - P_2D: begin // Two clock periods of data - // {{{ - case(cfg_width) - WIDTH_1W: begin - ck_sreg <= { ck_sreg[29: 0], 2'b11 }; - ck_data <= { {(2){7'h7f, ck_sreg[31] }}, - {(2){7'h7f, ck_sreg[30] }} }; - end - WIDTH_4W: begin - ck_sreg <= { ck_sreg[23: 0], 8'hff }; - ck_data <= { {(2){4'hf, ck_sreg[31:28] }}, - {(2){4'hf, ck_sreg[27:24] }} }; - end - default: begin // WIDTH_8W - ck_sreg <= { ck_sreg[15: 0], 16'hffff }; - ck_data <= { {(2){ck_sreg[31:24] }}, - {(2){ck_sreg[23:16]}} }; - end - endcase end - // }}} - default: begin // Four clock periods of data - // {{{ - case(cfg_width) - WIDTH_1W: begin - ck_sreg <= { ck_sreg[27: 0], 4'hf }; - ck_data <= { 7'h7f, ck_sreg[31], - 7'h7f, ck_sreg[30], - 7'h7f, ck_sreg[29], - 7'h7f, ck_sreg[28] }; - end - WIDTH_4W: begin - ck_sreg <= { ck_sreg[15: 0], 16'hffff }; - ck_data <= { 4'hf, ck_sreg[31:28], - 4'hf, ck_sreg[27:24], - 4'hf, ck_sreg[23:20], - 4'hf, ck_sreg[19:16] }; - end - default: begin // WIDTH_8W - ck_sreg <= {(32){1'b1}}; - ck_data <= ck_sreg; - end - endcase end - // }}} - endcase - end else if (i_ckstb && ck_counts == 0) - begin - // Fully idle - ck_data <= -1; - ck_sreg <= -1; - - ck_counts <= (start_packet && i_cfg_ddr && !i_hlfck) ? 1:0; - - if (start_packet) // Implies i_ckstb - case(cfg_period) - 2'b00: begin // One data period / clock - case(cfg_width) - WIDTH_1W: ck_data <= {(4){ 8'hfe }}; - WIDTH_4W: ck_data <= {(4){ 8'hf0 }}; - default: ck_data <= {(4){ 8'h00 }}; - endcase end - 2'b01: begin // Two data periods / clock - // {{{ - if (cfg_ddr) - begin - // One pedge, one negedge - case(cfg_width) - WIDTH_1W: ck_data <= {(4){ 8'hfe }}; - WIDTH_4W: ck_data <= {(4){ 8'hf0 }}; - default: ck_data <= {(4){ 8'h00 }}; - endcase - end else begin - // Two posedges, so only the second gets the - // start bits - case(cfg_width) - WIDTH_1W: ck_data <= { {(2){8'hff}}, {(2){8'hfe}} }; - WIDTH_4W: ck_data <= { {(2){8'hff}}, {(2){8'hf0}} }; - default: ck_data <= { {(2){8'hff}}, {(2){8'h00}} }; - endcase - end end - // }}} - default: begin // 4 data periods / clock, DDR - // pedge, nedge, pedge, nedge, so the last two - // get the start bit - case(cfg_width) - WIDTH_1W: ck_data <= { {(2){8'hff}}, {(2){8'hfe}} }; - WIDTH_4W: ck_data <= { {(2){8'hff}}, {(2){8'hf0}} }; - default: ck_data <= { {(2){8'hff}}, {(2){8'h00}} }; - endcase end - endcase - end - - assign pre_ready = (ck_counts == 0) && i_ckstb; // && tx_ready; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Final outputs - // {{{ - assign tx_valid = ck_valid; - // assign ck_ready = (i_ckstb || (i_hlfck && cfg_ddr)); // && tx_ready; - assign tx_data = ck_data; - // }}} - - // - // Make verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - // wire unused; - // assign unused = i_wb_cyc; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_ckstb, f_hlfck; - (* keep *) reg [9+5:0] fb_count, fd_offset, fd_count, - f_loaded_count; - (* keep *) reg [9:0] fs_count; - reg [10:0] fcrc_count; - (* keep *) reg fs_last; - wire f_step, fload_xtra; - - assign f_step = f_ckstb || (cfg_ddr && f_hlfck); - assign fload_xtra = tx_valid && f_step; // || fb_count == fd_offset); - - always @(*) - begin - if (fb_count < fd_offset) - f_loaded_count = 0; - else if (!tx_valid) - f_loaded_count = fb_count - fd_offset; - else case(cfg_period) - P_1D: case(cfg_width) - // {{{ - WIDTH_1W: f_loaded_count = fd_count + ck_counts + (fload_xtra ? 1:0); - WIDTH_4W: f_loaded_count = fd_count + (ck_counts*4) + (fload_xtra ? 4:0); - WIDTH_8W: f_loaded_count = fd_count + (ck_counts*8) + (fload_xtra ? 8:0); - endcase - // }}} - P_2D: case(cfg_width) - // {{{ - WIDTH_1W: f_loaded_count = fd_count + ck_counts*2 + (fload_xtra ? 2:0); - WIDTH_4W: f_loaded_count = fd_count + ck_counts*8 + (fload_xtra ? 8:0); - WIDTH_8W: f_loaded_count = fd_count + ck_counts*16 + (fload_xtra ? 16:0); - endcase - // }}} - P_4D: case(cfg_width) - // {{{ - WIDTH_1W: f_loaded_count = fd_count + ck_counts*4 + (fload_xtra ? 4:0); - WIDTH_4W: f_loaded_count = fd_count + ck_counts*16 + (fload_xtra ? 16:0); - WIDTH_8W: f_loaded_count = fd_count + ck_counts*32 + (fload_xtra ? 32:0); - endcase - // }}} - endcase - end - - always @(posedge i_clk) - if (i_reset) - { f_ckstb, f_hlfck } <= 2'b00; - else - { f_ckstb, f_hlfck } <= { i_ckstb, i_hlfck }; - - // fb_count -- count bits sent, including starting word - // {{{ - always @(posedge i_clk) - if (i_reset || !tx_valid) - fb_count <= 0; - else if (f_ckstb || (cfg_ddr && f_hlfck)) case(cfg_width) - WIDTH_1W: begin - case(cfg_period) - P_1D: fb_count <= fb_count + 1; - P_2D: fb_count <= fb_count + 2; - default: fb_count <= fb_count + 4; - endcase end - WIDTH_4W: begin - case(cfg_period) - P_1D: fb_count <= fb_count + 4; - P_2D: fb_count <= fb_count + 8; - default: fb_count <= fb_count + 16; - endcase end - default: begin - case(cfg_period) - P_1D: fb_count <= fb_count + 8; - P_2D: fb_count <= fb_count + 16; - default: fb_count <= fb_count + 32; - endcase end - endcase - // }}} - - initial fs_last = 0; - always @(posedge i_clk) - if (i_reset || !i_en || (pstate == P_LAST && !tx_valid)) - begin - fs_count <= 0; - fs_last <= 0; - fcrc_count <= 0; - end else if (S_VALID && S_READY) - begin - fs_count <= fs_count + 1; - fcrc_count <= fs_count + 1; - fs_last <= S_LAST; - end else if (pre_valid && pre_ready) - fcrc_count <= fcrc_count + 1; - - // fd_offset, fd_count: bit count, not including the starting word - // {{{ - always @(*) - begin - fd_offset = 1; - case(cfg_width) - WIDTH_1W: begin - case(cfg_period) - P_1D: fd_offset = (cfg_ddr ? 2:1); - P_2D: fd_offset = 2; - default: fd_offset = 4; - endcase end - WIDTH_4W: begin - case(cfg_period) - P_1D: fd_offset = (cfg_ddr ? 8: 4); - P_2D: fd_offset = 8; - default: fd_offset = 16; - endcase end - default: begin - case(cfg_period) - P_1D: fd_offset = (cfg_ddr ? 16: 8); - P_2D: fd_offset = 16; - default: fd_offset= 32; - endcase end - endcase - end - - always @(*) - if (fb_count > fd_offset) - fd_count = fb_count - fd_offset; - else - fd_count = 0; - // }}} - - reg f_past_valid, f_pending_half; - (* anyconst *) reg [9:0] fc_posn; - (* anyconst *) reg [31:0] fc_data; - wire [9:0] fp_count; - - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - //////////////////////////////////////////////////////////////////////// - // - // Configuraion interface - // {{{ - - always @(*) - if (!OPT_SERDES) - begin - assume(!i_cfg_ddr || i_cfg_spd > 1); - assume(i_cfg_spd > 0); - end - - always @(*) - if (!i_reset) - assume(i_cfg_width != 2'b11); - - //////// - - always @(*) - if (!i_reset) - assert(cfg_period <= P_4D); - - always @(posedge i_clk) - if (!i_reset && $past(tx_valid)) - assume(i_en); - - always @(posedge i_clk) - if (!i_reset && (i_en || $past(i_en))) - begin - assume($stable(i_cfg_ddr)); - assume($stable(i_cfg_spd)); - assume($stable(i_cfg_width)); - end - - always @(posedge i_clk) - if (!i_reset && i_en) - begin - assert(i_cfg_ddr == cfg_ddr); - assert(i_cfg_width == cfg_width); - end - - always @(*) - if (!i_reset) - assert(cfg_width != 2'b11); - - - always @(*) - if (!i_reset && pstate != P_IDLE) - begin - if (cfg_period == P_4D) - assert(cfg_ddr); - end - - always @(posedge i_clk) - if (!i_reset && i_en) - begin - if (i_cfg_ddr && i_cfg_spd == 0) - begin - assert(cfg_period == 2'b10); - end else if ((i_cfg_ddr && i_cfg_spd == 1) - ||(!i_cfg_ddr && i_cfg_spd == 0)) - begin - assert(cfg_period == 2'b01); - end else begin - assert(cfg_period == 2'b00); - end - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Clock interface - // {{{ - - always @(*) - if (!OPT_SERDES) - assume(!i_ckstb || !i_hlfck); - - initial f_pending_half = 1'b0; - always @(posedge i_clk) - if (i_reset) - f_pending_half <= 1'b0; - else if (i_ckstb) - f_pending_half <= !i_hlfck; - else if (i_hlfck) - f_pending_half <= 1'b0; - - always @(*) - if (i_en) case(i_cfg_spd) - 0: assume(i_ckstb && i_hlfck); - 1: assume(i_ckstb && i_hlfck); - 2: assume(i_ckstb ^ i_hlfck); - default: assume(!i_ckstb || !i_hlfck); - endcase - - always @(*) - if (i_en && i_cfg_spd == 2) - assume({ i_ckstb, i_hlfck } == (f_pending_half ? 2'b01:2'b10)); - - always @(*) - if (f_pending_half) - assume(!i_ckstb); - else if (i_hlfck) - assume(i_ckstb); - - always @(*) - if (!i_reset) - begin - if (cfg_period == P_1D) - begin - assume(!i_ckstb || (!cfg_ddr || !i_hlfck)); - end else - assume(i_ckstb && i_hlfck); // On every clock period - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // IO properties - // {{{ - - // Only change on a clock - // {{{ - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assert(!tx_valid); - else if (!$past(i_ckstb) && !$past(i_hlfck && cfg_ddr)) - begin - assert($stable(tx_valid)); - assert($stable(tx_data)); - end - // }}} - - // Unused bits to be set to 1'b1 - // {{{ - always @(*) - if (!i_reset) - begin - if (!tx_valid) - assert(&tx_data); - else case(cfg_width) - WIDTH_1W: begin - assert(tx_data[31:25] == 7'h7f); - assert(tx_data[23:17] == 7'h7f); - assert(tx_data[15: 9] == 7'h7f); - assert(tx_data[ 7: 1] == 7'h7f); - end - WIDTH_4W: begin - assert(tx_data[31:28] == 4'hf); - assert(tx_data[23:20] == 4'hf); - assert(tx_data[15:12] == 4'hf); - assert(tx_data[ 7: 4] == 4'hf); - end - default: begin end - endcase - end - // }}} - - // CFG_PERIOD requires repeated bits - // {{{ - always @(*) - if (!i_reset && tx_valid) - case(cfg_period) - P_1D: begin - assert(tx_data[31:24] == tx_data[ 7: 0]); - assert(tx_data[23:16] == tx_data[ 7: 0]); - assert(tx_data[15: 8] == tx_data[ 7: 0]); - end - P_2D: begin - assert(tx_data[31:24] == tx_data[23:16]); - assert(tx_data[15: 8] == tx_data[ 7: 0]); - end - default: begin end - endcase - // }}} - - always @(posedge i_clk) - if (!i_reset && pstate == P_CRC || pstate == P_DATA) - assert(tx_valid && pre_valid); - - always @(posedge i_clk) - if (!i_reset && pstate == P_IDLE) - assert(!tx_valid); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // AXI Stream inputs - // {{{ - - // Enable - // {{{ - always @(posedge i_clk) - if (!i_reset && (S_VALID || tx_valid))// || pstate != P_IDLE)) - assume(i_en); - - always @(*) - if (!i_en) - assume(!S_VALID); - - // always @(posedge i_clk) - // if (fs_last) - // assume(!i_en); - - always @(posedge i_clk) - if (!i_reset && pstate == P_IDLE) - assert(fs_count == 0); - - always @(*) - if (!i_reset) - begin - if (!fs_last) - begin - assert(fcrc_count == fs_count); - end else - assert(fcrc_count >= fs_count); - end - // }}} - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - assume(!S_VALID); - assume(!i_en); - end else if ($past(S_VALID && !S_READY)) - begin - assume(S_VALID); - assume($stable(S_DATA)); - assume($stable(S_LAST)); - end else if ($past(S_VALID && !S_LAST)) - assume(S_VALID); - - always @(*) - if (fs_last) - assume(!S_VALID); - - always @(*) - if (fs_count == 10'h3df) - assume(!S_VALID || S_LAST); - - always @(*) - if (!i_reset && fs_count >= 10'h3e0) - assert(fs_last); - - always @(*) - if (!i_reset && fs_count==0) - assert(!fs_last); - - always @(posedge i_clk) - if (!i_reset && (pstate == P_CRC || pstate == P_LAST)) - assert(fs_last); - - always @(posedge i_clk) - if (!i_reset && pstate == P_DATA) - assert(!fs_last && S_VALID && fs_count > 0); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract checking - // {{{ - - always @(*) - if (S_VALID && fs_count == fc_posn) - assume(fc_data == S_DATA); - - // Start bit checking - // {{{ - always @(*) - if (!i_reset && tx_valid && fb_count < fd_offset) - begin - if (!f_step) - begin - case({(cfg_ddr && !f_pending_half), cfg_width}) - {1'b0,WIDTH_1W}: assert(fb_count==1); - {1'b1,WIDTH_1W}: assert(fb_count==2); - {1'b0,WIDTH_4W}: assert(fb_count==4); - {1'b1,WIDTH_1W}: assert(fb_count==8); - {1'b0,WIDTH_8W}: assert(fb_count==8); - {1'b1,WIDTH_8W}: assert(fb_count==16); - default: assert(0); - endcase - end - assert(ck_counts == ((cfg_ddr && f_pending_half) ? 1:0)); - assert(fs_count <= 1); - assert(fd_count == 0); - assert(pstate == P_DATA || (pstate == P_CRC && fs_count == 1)); - case(cfg_period) - P_1D: case(cfg_width) - WIDTH_1W: assert((cfg_ddr && !f_pending_half) - || ({ tx_data[24], tx_data[16], tx_data[8], tx_data[0] } == 4'b0)); - WIDTH_4W: assert((cfg_ddr && !f_pending_half) - || ({ tx_data[27:24], tx_data[19:16], - tx_data[11:8], tx_data[3:0] } == 16'b0)); - WIDTH_8W: assert((cfg_ddr && !f_pending_half) - || tx_data == 32'h0); - default: begin end - endcase - P_2D: case(cfg_width) - WIDTH_1W: assert({ tx_data[24], tx_data[16], tx_data[8], tx_data[0] } - == (cfg_ddr) ? 4'b0000 : 4'b1100); - WIDTH_4W: assert({ tx_data[27:24], tx_data[19:16], - tx_data[11:8], tx_data[3:0] } - == (cfg_ddr) ? 16'h00 : 16'hff00); - WIDTH_8W: assert(tx_data == (cfg_ddr) ? 32'h00 : 32'hffff_0000); - default: begin end - endcase - P_4D: case(cfg_width) - WIDTH_1W: assert({ tx_data[24], tx_data[16], tx_data[8], tx_data[0] } == 4'b1100); - WIDTH_4W: assert({ tx_data[27:24], tx_data[19:16], - tx_data[11:8], tx_data[3:0] } == 16'hff00); - WIDTH_8W: assert(tx_data == 32'hffff_0000); - default: begin end - endcase - endcase - end - // }}} - - assign fp_count=((pstate == P_DATA && pre_valid) || (pstate == P_CRC)) - ? fs_count-1 : fs_count; - - always @(*) - if (pre_valid) - begin - assert(pstate != P_IDLE); - if (fp_count == fc_posn && pstate == P_DATA) - assert(pre_data == fc_data); - end else begin - assert(pstate == P_IDLE || pstate == P_LAST); - end - - // Verify pre_count - // {{{ - always @(*) - if (!i_reset) - assert(pre_count <= 7); - - always @(*) - if (!i_reset && pstate == P_DATA) - assert(pre_valid); - - always @(*) - if (!i_reset && pstate == P_DATA) - begin - case(cfg_width) - WIDTH_1W: assert(pre_count == 0); - WIDTH_4W: assert(pre_count == (cfg_ddr) ? 3 : 1); - default: // WIDTH_8W - assert(pre_count == (cfg_ddr) ? 7 : 3); - endcase - end else if (!i_reset && pstate == P_CRC) - begin - assert(pre_valid); - case(cfg_width) - WIDTH_1W: assert(pre_count == 0); - WIDTH_4W: assert(pre_count <= (cfg_ddr) ? 3 : 1); - default: // WIDTH_8W - assert(pre_count <= (cfg_ddr) ? 7 : 3); - endcase - end else if (!i_reset && pstate == P_LAST) - begin - assert(pre_count == 0); - end - // }}} - - always @(*) - if (!i_reset && pstate == P_DATA) - begin - if (fs_count < 2) - begin - assert(fd_count == 0); - end else begin - assert(fs_count == (pre_valid ? 1:0) + f_loaded_count[14:5]); - end - end - - always @(*) - if (!i_reset && pstate == P_CRC) - begin - assert(pre_valid); - assert(fcrc_count == 1 + f_loaded_count[14:5]); - - case(cfg_width) - WIDTH_1W: assert(fcrc_count == fs_count); - WIDTH_4W: assert(fcrc_count == fs_count + (((cfg_ddr) ? 3 : 1)-pre_count)); - WIDTH_8W: assert(fcrc_count == fs_count + (((cfg_ddr) ? 7 : 3)-pre_count)); - endcase - end - - always @(*) - if (!i_reset && pstate == P_LAST) - begin - case(cfg_width) - WIDTH_1W: assert(fcrc_count == fs_count + 1 + (pre_valid ? 0:1)); - WIDTH_4W: assert(fcrc_count == fs_count + 1 + (pre_valid ? 0:1) - + (((cfg_ddr) ? 3 : 1)-pre_count)); - WIDTH_8W: assert(fcrc_count == fs_count + 1 + (pre_valid ? 0:1) - + (((cfg_ddr) ? 7 : 3)-pre_count)); - endcase - end - - always @(*) - if (!i_reset && (pstate == P_IDLE || !tx_valid)) - assert(ck_counts == 0); - - always @(*) - if (!i_reset && fb_count >= fd_offset) - case(cfg_period) - P_1D: case(cfg_width) - // {{{ - WIDTH_1W: begin end - WIDTH_4W: begin - assert(ck_counts <= 7); - end - WIDTH_8W: begin - assert(ck_counts <= 3); - end - endcase - // }}} - P_2D: case(cfg_width) - // {{{ - WIDTH_1W: begin - assert(ck_counts <= 15); - end - WIDTH_4W: begin - assert(ck_counts <= 3); - end - WIDTH_8W: begin - assert(ck_counts <= 1); - end - endcase - // }}} - P_4D: case(cfg_width) - // {{{ - WIDTH_1W: begin - assert(ck_counts <= 7); - end - WIDTH_4W: begin - assert(ck_counts <= 1); - end - WIDTH_8W: begin - assert(ck_counts == 0); - if (pstate == P_DATA) begin - assert(fd_count + 32 == { fp_count, 5'h0 }); - if (fd_count == { fc_posn, 5'h0 }) - assert(ck_data == fc_data); - end end - endcase - // }}} - endcase - - // Verify fb_count modulo step is always zero - // {{{ - always @(*) - if (!i_reset) - begin - case(cfg_period) - P_1D: case(cfg_width) - // {{{ - WIDTH_1W: begin end - WIDTH_4W: assert(fb_count[1:0] == 2'b0); - WIDTH_8W: assert(fb_count[2:0] == 3'b0); - endcase - // }}} - P_2D: case(cfg_width) - // {{{ - WIDTH_1W: assert(fb_count[0] == 1'b0); - WIDTH_4W: assert(fb_count[2:0] == 3'b0); - WIDTH_8W: assert(fb_count[3:0] == 4'b0); - endcase - // }}} - P_4D: case(cfg_width) - // {{{ - WIDTH_1W: assert(fb_count[1:0] == 2'h0); - WIDTH_4W: assert(fb_count[3:0] == 4'h0); - WIDTH_8W: assert(fb_count[4:0] == 5'h0); - endcase - // }}} - endcase - end - // }}} - - // Verify f_loaded_count[4:0] - // {{{ - always @(*) - if (!i_reset) - begin - // assert(f_loaded_count[4:0] == 0); - if (pstate == P_DATA || pstate == P_CRC) case(cfg_period) - P_1D: case(cfg_width) - WIDTH_1W: assert(f_loaded_count[4:0] == 5'h00); - WIDTH_4W: assert(f_loaded_count[4:0] == 5'h00); - WIDTH_8W: assert(f_loaded_count[4:0] == 5'h00); - default: begin end - endcase - P_2D: case(cfg_width) - WIDTH_1W: assert(f_loaded_count[4:0] == (f_step ? 5'h00 : 5'h04)); - WIDTH_4W: assert(f_loaded_count[4:0] == (f_step ? 5'h00 : 5'h08)); - WIDTH_8W: assert(f_loaded_count[4:0] == 5'h0); - default: begin end - endcase - P_4D: case(cfg_width) - WIDTH_1W: assert(f_loaded_count[4:0] == (f_step ? 5'h00 : 5'h08)); - WIDTH_4W: assert(f_loaded_count[4:0] == (f_step ? 5'h00 : 5'h10)); - WIDTH_8W: assert(f_loaded_count[4:0] == 5'h0); - default: begin end - endcase - default: begin end - endcase - end - // }}} - - // Verify ck_count[LSB] for DDR - // {{{ - always @(*) - if (!i_reset && tx_valid && cfg_ddr && cfg_period == P_1D) - begin - assert(ck_counts[0] == f_pending_half - || (!pre_valid && pstate == P_LAST && ck_counts==0)); - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - - // Pre-contract cover check: Can we start a packet in each mode? - // {{{ - always @(posedge i_clk) - if (!i_reset && !$past(i_reset) && tx_valid) - begin - case(cfg_period) - P_1D: case(cfg_width) - // {{{ - WIDTH_1W: cover(1); - WIDTH_4W: cover(1); - WIDTH_8W: cover(1); - default: begin end - endcase - // }}} - P_2D: if(cfg_ddr) - // {{{ - begin - case(cfg_width) - WIDTH_1W: cover(1); - WIDTH_4W: cover(1); - WIDTH_8W: cover(1); - default: begin end - endcase - end else begin - case(cfg_width) - WIDTH_1W: cover(1); - WIDTH_4W: cover(1); - WIDTH_8W: cover(1); - default: begin end - endcase - end - // }}} - P_4D: case(cfg_width) - // {{{ - WIDTH_1W: cover(1); - WIDTH_4W: begin - cover(1); - cover(fs_count == 1); - cover(fs_count == 2); - cover(fs_count == 3); // !!! - cover(fs_count == 4); // !!! - cover(S_VALID && S_LAST); - cover(!S_VALID); - cover($fell(pre_valid)); - cover(pstate == P_CRC); - cover(pstate == P_LAST); // !!! - cover(!pre_valid); // !!! - end - WIDTH_8W: cover(1); - default: begin end - endcase - // }}} - endcase - end - // }}} - - // Contract covers: can we complete a packet in the first place? - // {{{ - always @(posedge i_clk) - if (!i_reset && !$past(i_reset) && $fell(tx_valid)) - begin - case(cfg_period) - P_1D: case(cfg_width) - // {{{ - WIDTH_1W: cover(1); // !!! - WIDTH_4W: cover(1); // !!! - WIDTH_8W: cover(1); // !!! - default: begin end - endcase - // }}} - P_2D: if(cfg_ddr) - // {{{ - begin - case(cfg_width) - WIDTH_1W: cover(1); // !!! - WIDTH_4W: cover(1); - WIDTH_8W: cover(1); - default: begin end - endcase - end else begin - case(cfg_width) - WIDTH_1W: cover(1); // !!! - WIDTH_4W: cover(1); - WIDTH_8W: cover(1); - default: begin end - endcase - end - // }}} - P_4D: case(cfg_width) - // {{{ - WIDTH_1W: cover(1); // !!! - WIDTH_4W: cover(1); // !!! - WIDTH_8W: cover(1); - default: begin end - endcase - // }}} - endcase - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - - // }}} -`endif // FORMAL -// }}} -endmodule - diff --git a/delete_later/rtl/sdspi/sdwb.v b/delete_later/rtl/sdspi/sdwb.v deleted file mode 100644 index 1f86240..0000000 --- a/delete_later/rtl/sdspi/sdwb.v +++ /dev/null @@ -1,1433 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sdwb.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Bus handler. Accepts and responds to Wishbone bus requests. -// Configures clock division, and IO speed and parameters. -// Issues commands to the command handler, TX and RX handlers. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module sdwb #( - // {{{ - parameter LGFIFO = 15, // FIFO size in bytes - parameter NUMIO=4, - parameter MW = 32, - // parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter [0:0] OPT_SERDES = 1'b0, - parameter [0:0] OPT_DDR = 1'b0, - parameter [0:0] OPT_CARD_DETECT = 1'b1, - localparam LGFIFOW=LGFIFO-$clog2(MW/8), - parameter [0:0] OPT_DMA = 1'b0, - parameter [0:0] OPT_1P8V= 1'b0 // 1.8V voltage switch capable? - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Wishbone interface - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [2:0] i_wb_addr, - input wire [32-1:0] i_wb_data, - input wire [32/8-1:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [32-1:0] o_wb_data, - // }}} - // Configuration options - // {{{ - output reg o_cfg_clk90, - output wire [7:0] o_cfg_ckspeed, - output reg o_cfg_shutdown, - output wire [1:0] o_cfg_width, - output reg o_cfg_ds, o_cfg_ddr, - output reg o_pp_cmd, o_pp_data, - output reg [4:0] o_cfg_sample_shift, - input wire [7:0] i_ckspd, - - output reg o_soft_reset, - // }}} - // CMD interface - // {{{ - output reg o_cmd_request, - output reg [1:0] o_cmd_type, - output wire [6:0] o_cmd_id, - output wire [31:0] o_arg, - // - input wire i_cmd_busy, i_cmd_done, - i_cmd_err, - input wire [1:0] i_cmd_ercode, - // - input wire i_cmd_response, - input wire [5:0] i_resp, - input wire [31:0] i_arg, - // - input wire i_cmd_mem_valid, - input wire [MW/8-1:0] i_cmd_mem_strb, - input wire [LGFIFOW-1:0] i_cmd_mem_addr, - input wire [MW-1:0] i_cmd_mem_data, - // }}} - // TX interface - // {{{ - output reg o_tx_en, - // - output reg o_tx_mem_valid, - input wire i_tx_mem_ready, - output reg [31:0] o_tx_mem_data, - output reg o_tx_mem_last, - input wire i_tx_busy, - // }}} - // RX interface - // {{{ - output reg o_rx_en, - output wire o_crc_en, - output wire [LGFIFO:0] o_length, - // - input wire i_rx_mem_valid, - input wire [MW/8-1:0] i_rx_mem_strb, - input wire [LGFIFOW-1:0] i_rx_mem_addr, - input wire [MW-1:0] i_rx_mem_data, - // - input wire i_rx_done, i_rx_err, - // }}} - input wire i_card_detect, - input wire i_card_busy, - output wire o_1p8v, - output reg o_int - // }}} - ); - - // Local declarations - // {{{ - localparam LGFIFO32 = LGFIFO - $clog2(32/8); - - localparam [2:0] ADDR_CMD = 0, - ADDR_ARG = 1, - ADDR_FIFOA = 2, - ADDR_FIFOB = 3, - ADDR_PHY = 4; - - localparam [1:0] CMD_PREFIX = 2'b01, - NUL_PREFIX = 2'b00; - localparam [1:0] RNO_REPLY = 2'b00, - R2_REPLY = 2'b10; - localparam CARD_REMOVED_BIT = 18, - // ERR_BIT = 15, - USE_DMA_BIT = 13, - FIFO_ID_BIT = 12, - USE_FIFO_BIT = 11, - FIFO_WRITE_BIT = 10; - - localparam [1:0] WIDTH_1W = 2'b00, - WIDTH_4W = 2'b01, - WIDTH_8W = 2'b10; - - wire wb_cmd_stb, wb_phy_stb; - reg [6:0] r_cmd; - reg r_tx_request, r_rx_request, r_tx_sent; - reg r_fifo, r_cmd_err; - reg [1:0] r_cmd_ecode; - reg [31:0] r_arg; - reg [3:0] lgblk; - reg [1:0] r_width; - reg [7:0] r_ckspeed; - reg [31:0] w_cmd_word, w_phy_ctrl; - reg [15:0] blk_words; - - integer ika, ikb; - localparam NFIFOW = (1< 0) ? ($clog2(MW/32)-1):0):0] tx_shift; - reg [LGFIFOW-1:0] fif_wraddr, fif_rdaddr; - reg [LGFIFOW-1:0] fif_a_rdaddr, fif_b_rdaddr; - reg [LGFIFO32-1:0] tx_mem_addr; - reg [MW-1:0] next_tx_mem; - reg tx_fifo_last, pre_tx_last, - tx_pipe_valid; - - wire card_present, card_removed; - - reg pre_ack; - reg [1:0] pre_sel; - reg [31:0] pre_data; - - reg [LGFIFOW-1:0] mem_wr_addr_a, mem_wr_addr_b; - reg [MW/8-1:0] mem_wr_strb_a, mem_wr_strb_b; - reg [MW-1:0] mem_wr_data_a, mem_wr_data_b; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Registers - // {{{ - reg cmd_busy, new_cmd_request, new_data_request, new_tx_request; - - // CMD/control register - // {{{ - assign wb_cmd_stb = i_wb_stb && i_wb_addr == ADDR_CMD && i_wb_we; - - // o_soft_reset - // {{{ - initial o_soft_reset = 1'b1; - always @(posedge i_clk) - if (i_reset || !card_present) - o_soft_reset <= 1'b1; - else - o_soft_reset <= (wb_cmd_stb)&&(&i_wb_sel[3:0]) - &&(i_wb_data==32'h52_00_00_00); - // }}} - - // o_cmd_request - // {{{ - always @(*) - begin - new_cmd_request = !cmd_busy && wb_cmd_stb && i_wb_sel[0] - && (i_wb_data[7:6] == CMD_PREFIX - || (i_wb_data[7:6] == NUL_PREFIX && i_wb_sel[1] - && !i_wb_data[USE_DMA_BIT] - && !i_wb_data[USE_FIFO_BIT] - && i_wb_data[9:8] == RNO_REPLY)); - - new_data_request = wb_cmd_stb && (&i_wb_sel[1:0]) - && ((!cmd_busy && i_wb_data[7:6] == CMD_PREFIX) - || i_wb_data[7:6] == NUL_PREFIX) - && ((i_wb_data[USE_DMA_BIT] && OPT_DMA) - || i_wb_data[USE_FIFO_BIT] - ||(!cmd_busy && i_wb_data[7:6] == CMD_PREFIX - && i_wb_data[9:8] == R2_REPLY)); - - // If the FIFO is already in use, then we can't accept any - // new command which would require the FIFO - // {{{ - if (o_tx_en || r_tx_request || o_rx_en || r_rx_request) - new_data_request = 1'b0; - if (cmd_busy && o_cmd_type == R2_REPLY) - new_data_request = 1'b0; - - // If we want an R2 reply, then the data channels need to be - // clear. - if ((o_tx_en || r_tx_request || o_rx_en || r_rx_request) - &&((i_wb_sel[1] && i_wb_data[9:8] == R2_REPLY) - ||(!i_wb_sel[1]&&o_cmd_type == R2_REPLY))) - new_cmd_request = 1'b0; - - // If we are requesting a new command, one that requires data - // transfer, and the data channels are still busy, then we - // must refuse the command. - if ((o_tx_en || r_tx_request || o_rx_en || r_rx_request) - &&((i_wb_data[USE_DMA_BIT] && OPT_DMA) - || i_wb_data[USE_FIFO_BIT])) - new_cmd_request = 1'b0; - // }}} - - if (i_reset || o_soft_reset) - { new_data_request, new_cmd_request } = 2'b0; - end - - initial o_cmd_request = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - o_cmd_request <= 1'b0; - else if (new_cmd_request) - begin - o_cmd_request <= 1'b1; - end else if (!i_cmd_busy) - o_cmd_request <= 1'b0; - // }}} - - // cmd_busy: Are we waiting on a command to complete? - // {{{ - initial cmd_busy = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - cmd_busy <= 1'b0; - else if (new_cmd_request) - cmd_busy <= 1'b1; - else if (i_cmd_done) - cmd_busy <= 1'b0; -`ifdef FORMAL - always @(*) - if (i_reset && o_cmd_request) - assert(cmd_busy); -`endif - // }}} - - // o_cmd_id: What command are we issuing? - // {{{ - initial r_cmd = 7'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - r_cmd <= 7'b0; - else if (new_cmd_request) - r_cmd <= i_wb_data[6:0]; - else if (i_cmd_response) - r_cmd <= { 1'b0, i_resp }; - - assign o_cmd_id = r_cmd[6:0]; - // }}} - - // o_cmd_type: What response to expect? None, R1, R2, or R1b - // {{{ - initial o_cmd_type = 2'b00; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - o_cmd_type <= 2'b00; - else if (new_cmd_request && i_wb_sel[1]) - o_cmd_type <= i_wb_data[9:8]; - // }}} - - // o_tx_en, r_tx_request, r_tx_sent - // {{{ - always @(*) - begin - new_tx_request = new_data_request && i_wb_data[FIFO_WRITE_BIT]; - if (i_wb_data[9:8] == R2_REPLY - && i_wb_data[7:6] == CMD_PREFIX) - new_tx_request = 1'b0; - if (i_reset || o_soft_reset) - new_tx_request = 1'b0; - end - - initial r_tx_request = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - r_tx_request <= 1'b0; - else if (new_tx_request) - r_tx_request <= 1'b1; - else if (!cmd_busy && !o_cmd_request && !o_tx_en && !i_card_busy) - r_tx_request <= 1'b0; - - initial r_tx_sent = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset || !o_tx_en) - r_tx_sent <= 1'b0; - else if (o_tx_mem_valid && i_tx_mem_ready && o_tx_mem_last) - r_tx_sent <= 1'b1; - - initial o_tx_en = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - o_tx_en <= 1'b0; - else if (o_tx_en && r_tx_sent && !i_tx_busy) - o_tx_en <= 1'b0; - else if (!cmd_busy && !o_cmd_request && !o_tx_en && !i_card_busy - && r_tx_request) - o_tx_en <= r_tx_request; -`ifdef FORMAL - always @(*) - if (!i_reset && !o_soft_reset) - assert(!r_tx_request || !o_tx_en); - - always @(posedge i_clk) - if (!i_reset && $past(!i_reset && !o_soft_reset && r_tx_request)) - assert(r_tx_request || o_tx_en); - - always @(posedge i_clk) - if (!i_reset && $past(!i_reset && !o_soft_reset && new_data_request)) - assert(r_tx_request || r_rx_request - ||(o_cmd_request && o_cmd_type == R2_REPLY)); -`endif - // }}} - - // o_rx_en, r_rx_request - // {{{ - initial r_rx_request = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - r_rx_request <= 1'b0; - else if (new_data_request && !i_wb_data[FIFO_WRITE_BIT] - && (i_wb_data[9:8] != R2_REPLY - || i_wb_data[7:6] == NUL_PREFIX)) - r_rx_request <= 1'b1; - else if (!cmd_busy && !o_cmd_request) - r_rx_request <= 1'b0; - - initial o_rx_en = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - o_rx_en <= 1'b0; - else if (o_rx_en && i_rx_done) - o_rx_en <= 1'b0; - else if (!cmd_busy && !o_cmd_request && r_rx_request) - o_rx_en <= 1'b1; -`ifdef FORMAL - always @(*) - if (!i_reset && !o_soft_reset) - assert(!r_rx_request || !o_rx_en); - always @(posedge i_clk) - if (!i_reset && $past(!i_reset && !o_soft_reset && r_rx_request)) - assert(r_rx_request || o_rx_en); -`endif - // }}} - - // r_fifo: Control which FIFO this command uses - // {{{ - initial r_fifo = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - r_fifo <= 1'b0; - else if (!cmd_busy && !o_tx_en && !o_rx_en - && !r_tx_request && !r_rx_request - && wb_cmd_stb && i_wb_sel[FIFO_ID_BIT/8]) - r_fifo <= i_wb_data[FIFO_ID_BIT]; - // }}} - - // always @(posedge i_clk) - // if (i_reset || !OPT_DMA) - // r_dma <= 1'b0; - // else if (!i_cmd_busy && i_wb_stb && i_wb_addr == 0 && i_wb_sel[1:0]) - // r_dma <= i_wb_data[USE_DMA_BIT]; - - // r_cmd_err - // {{{ - initial r_cmd_err = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - r_cmd_err <= 1'b0; - // else if (new_cmd_request) - else if (i_cmd_err || (o_rx_en && i_rx_err)) - r_cmd_err <= 1'b1; - else if (wb_cmd_stb && i_wb_sel[1] && i_wb_data[15]) - r_cmd_err <= 1'b0; - - initial r_cmd_ecode = 2'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - r_cmd_ecode <= 2'b0; - else if (new_cmd_request) - r_cmd_ecode <= 2'b0; - else if (!r_cmd_err) - begin - if (i_rx_err) - r_cmd_ecode <= 2'b10; - if (i_cmd_done) - r_cmd_ecode <= i_cmd_ercode; - end - // }}} - - always @(*) - begin - w_cmd_word = 32'h0; - - w_cmd_word[27] = o_tx_en; - w_cmd_word[26] = r_tx_request; - w_cmd_word[25] = o_rx_en; - w_cmd_word[24] = r_rx_request; - - w_cmd_word[21] = (fif_rdaddr == 0); - w_cmd_word[20] = i_card_busy; - w_cmd_word[19] = !card_present; - w_cmd_word[18] = card_removed; - w_cmd_word[17:16] = r_cmd_ecode; - w_cmd_word[15] = r_cmd_err; - w_cmd_word[14] = cmd_busy; - w_cmd_word[13] = 1'b0; // (== r_dma && OPT_DMA) - w_cmd_word[12] = r_fifo; - w_cmd_word[11] = (o_tx_en || r_tx_request - || o_rx_en || r_rx_request - ||(cmd_busy && o_cmd_type == 2'b10)); - w_cmd_word[10] = (o_tx_en || r_tx_request); - w_cmd_word[9:8] = o_cmd_type; - w_cmd_word[6:0] = r_cmd; - end - // }}} - - // Command argument register - // {{{ - initial r_arg = 32'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - r_arg <= 0; - // else if (o_cmd_request && !i_cmd_busy) - // r_arg <= 0; - else if (i_cmd_response) - r_arg <= i_arg; - else if (!cmd_busy && i_wb_stb && !o_wb_stall && i_wb_we && i_wb_addr == ADDR_ARG) - begin - if (i_wb_sel[0]) - r_arg[ 7: 0] <= i_wb_data[ 7: 0]; - if (i_wb_sel[1]) - r_arg[15: 8] <= i_wb_data[15: 8]; - if (i_wb_sel[2]) - r_arg[23:16] <= i_wb_data[23:16]; - if (i_wb_sel[3]) - r_arg[31:24] <= i_wb_data[31:24]; - end - - assign o_arg = r_arg; - // }}} - - // PHY control register - // {{{ - assign wb_phy_stb = i_wb_stb && !o_wb_stall && i_wb_addr == ADDR_PHY && i_wb_we; - - // o_length, lgblk - // {{{ - initial lgblk = 4'h9; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - lgblk <= 4'h9; - else if (!o_tx_en && !o_rx_en && !r_tx_request && !r_rx_request - && wb_phy_stb && i_wb_sel[3]) - begin - lgblk <= i_wb_data[27:24]; - if (i_wb_data[27:24] >= LGFIFO) - lgblk <= LGFIFO; - else if (i_wb_data[27:24] <= 2) - lgblk <= 2; - end - - assign o_length = 1<= 8) r_width <= WIDTH_8W; - 2'b11: if (NUMIO >= 8) r_width <= WIDTH_8W; - else if (NUMIO >= 4) r_width <= WIDTH_4W; - else r_width <= WIDTH_1W; - default: begin end - endcase - end - - assign o_cfg_width = r_width; - // }}} - - // o_cfg_ckspeed: Clock speed control - // {{{ - initial r_ckspeed = 252; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - r_ckspeed <= 252; - else if (wb_phy_stb && i_wb_sel[0]) - begin - r_ckspeed <= i_wb_data[7:0]; - if (!OPT_SERDES && !OPT_DDR && i_wb_data[7:0] < 2) - r_ckspeed <= 8'h2; - else if (!OPT_SERDES && i_wb_data[7:0] == 0) - r_ckspeed <= 8'h1; - end - - assign o_cfg_ckspeed = r_ckspeed; -`ifdef FORMAL - always @(*) - if (!i_reset && !OPT_SERDES && !OPT_DDR) - assert(o_cfg_ckspeed >= 2); - - always @(*) - if (!i_reset && !OPT_SERDES) - assert(o_cfg_ckspeed >= 1); -`endif - // }}} - - always @(*) - begin - w_phy_ctrl = 0; - w_phy_ctrl[31:28] = LGFIFO; // Can also set lgblk=15, & read MAX - w_phy_ctrl[27:24] = lgblk; - w_phy_ctrl[23] = OPT_1P8V; - w_phy_ctrl[22] = o_1p8v; - w_phy_ctrl[21] = OPT_SERDES; // Is this required? - w_phy_ctrl[20:16] = o_cfg_sample_shift; - w_phy_ctrl[15] = o_cfg_shutdown; - w_phy_ctrl[14] = o_cfg_clk90; - w_phy_ctrl[13] = o_pp_cmd; // Push-pull CMD line - w_phy_ctrl[12] = o_pp_data; // Push-pull DAT line(s) - w_phy_ctrl[11:10] = r_width; - w_phy_ctrl[9:8] = { o_cfg_ds, o_cfg_ddr }; - w_phy_ctrl[7:0] = i_ckspd; // r_ckspeed; - end - // }}} - - assign o_crc_en = 1'b1; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Card detection - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Depends upon the i_card_detect signal. Set this signal to 1'b1 if - // you your device doesn't have it. - // - // - generate if (OPT_CARD_DETECT) - begin : GEN_CARD_DETECT - reg [2:0] raw_card_present; - reg [9:0] card_detect_counter; - reg r_card_removed, r_card_present; - - // 3FF cross clock domains: i_card_detect->raw_card_present - // {{{ - initial raw_card_present = 0; - always @(posedge i_clk) - if (i_reset) - raw_card_present <= 0; - else - raw_card_present <= { raw_card_present[1:0], i_card_detect }; - // }}} - - // card_removed: If the card is ever not present, then it has - // {{{ - // been removed. Set the removed flag so the user can see the - // card has been removed, even if they come back to it later - // and there's a card present. - initial r_card_removed = 1'b1; - always @(posedge i_clk) - if (i_reset) - r_card_removed <= 1'b1; - else if (!card_present) - r_card_removed <= 1'b1; - else if (wb_cmd_stb && i_wb_data[CARD_REMOVED_BIT] - && i_wb_sel[CARD_REMOVED_BIT/8]) - r_card_removed <= 1'b0; - - assign card_removed = r_card_removed; - // }}} - - // card_present: Require a card to be inserted for a period - // {{{ - // of time before declaring it to be present. This helps - // to unbounce any card detection logic. - initial card_detect_counter = 0; - always @(posedge i_clk) - if (i_reset || !raw_card_present[2]) - card_detect_counter <= 0; - else if (!(&card_detect_counter)) - card_detect_counter <= card_detect_counter + 1; - - initial r_card_present = 1'b0; - always @(posedge i_clk) - if (i_reset || !raw_card_present[2]) - r_card_present <= 1'b0; - else if (&card_detect_counter) - r_card_present <= 1'b1; - - assign card_present = r_card_present; - // }}} - - end else begin : NO_CARD_DETECT_SIGNAL - - assign card_present = 1'b1; - assign card_removed = 1'b0; - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused_card_detect; - assign unused_card_detect = &{ 1'b0, i_card_detect }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Interrupt generation - // {{{ - - initial o_int = 0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - o_int <= 1'b0; - else begin - o_int <= 1'b0; - // 3 Types of interrupts: - // - // A) Command operation is complete, response is ready - if (i_cmd_done && cmd_busy) - o_int <= 1'b1; - // - // B) Transmit to card operation is complete, and is now ready - // for another command (if desired) - if (o_tx_en && r_tx_sent && !i_tx_busy) - o_int <= 1'b1; - // - // C) A block has been received. We are now ready to receive - // another block (if desired) - if (o_rx_en && i_rx_done) - o_int <= 1'b1; - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // FIFO / Memory handling - // {{{ - - // User write pointer - // {{{ - initial fif_wraddr = 0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - fif_wraddr <= 0; - else if (wb_cmd_stb && i_wb_sel[1] - && (i_wb_data[11] || i_wb_data[9:8] == 2'b10)) - fif_wraddr <= 0; - else if (i_wb_stb && !o_wb_stall && i_wb_we && i_wb_sel[0] - && (i_wb_addr == ADDR_FIFOA || i_wb_addr == ADDR_FIFOB)) - fif_wraddr <= fif_wraddr + 1; - // }}} - - // User read pointer - // {{{ - initial fif_rdaddr = 0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - fif_rdaddr <= 0; - else if (wb_cmd_stb && i_wb_sel[1] - && (i_wb_data[11] || i_wb_data[9:8] == 2'b10 - || r_fifo != i_wb_data[FIFO_ID_BIT])) - fif_rdaddr <= 0; - else if (i_wb_stb && !i_wb_we && i_wb_sel[0] - && (i_wb_addr == ADDR_FIFOA || i_wb_addr == ADDR_FIFOB)) - fif_rdaddr <= fif_rdaddr + 1; - // }}} - - // TX - - // o_tx_mem_valid - // {{{ - initial o_tx_mem_valid = 1'b0; - always @(posedge i_clk) - if (i_reset || o_soft_reset) - o_tx_mem_valid <= 0; - else if (!o_tx_en || r_tx_sent - || (o_tx_mem_valid && i_tx_mem_ready && o_tx_mem_last)) - { o_tx_mem_valid, tx_pipe_valid } <= 0; - else if (!o_tx_mem_valid || i_tx_mem_ready || !tx_pipe_valid) - { o_tx_mem_valid, tx_pipe_valid } <= { tx_pipe_valid, 1'b1 }; - // }}} - - // tx_mem_addr - // {{{ - always @(posedge i_clk) - if (i_reset || !o_tx_en || o_soft_reset) - tx_mem_addr <= 0; - else if (!o_tx_mem_valid || i_tx_mem_ready || !tx_pipe_valid) - tx_mem_addr <= tx_mem_addr + 1; - // }}} - - always @(*) - fif_a_rdaddr = (o_tx_en && !r_fifo) ? tx_mem_addr[LGFIFO32-1:$clog2(MW/32)] : fif_rdaddr; - - always @(*) - fif_b_rdaddr = (o_tx_en && r_fifo) ? tx_mem_addr[LGFIFO32-1:$clog2(MW/32)] : fif_rdaddr; - - always @(*) - blk_words = (1<<(lgblk-2))-1; - - // Verilator lint_off WIDTH - always @(*) - pre_tx_last = o_tx_en && (tx_mem_addr[LGFIFO32-1:$clog2(MW/32)] >= blk_words); - // Verilator lint_on WIDTH - - always @(posedge i_clk) - if (!o_tx_mem_valid || i_tx_mem_ready || r_fifo) - tx_fifo_a <= fifo_a[fif_a_rdaddr]; - - always @(posedge i_clk) - if (!o_tx_mem_valid || i_tx_mem_ready || !r_fifo) - tx_fifo_b <= fifo_b[fif_b_rdaddr]; - - always @(posedge i_clk) - if (!o_tx_mem_valid || i_tx_mem_ready) - tx_fifo_last <= pre_tx_last; - - // o_tx_mem_data - // {{{ - generate if (MW <= 32) - begin : NO_TX_SHIFT - assign tx_shift = 0; - end else begin : GEN_TX_SHIFT - reg [$clog2(MW/32)-1:0] r_tx_shift; - - always @(posedge i_clk) - if (!o_tx_mem_valid || i_tx_mem_ready) - r_tx_shift <= tx_mem_addr[$clog2(MW/32)-1:0]; - - assign tx_shift = r_tx_shift; - end endgenerate - - always @(*) - begin - next_tx_mem = (r_fifo) ? tx_fifo_b : tx_fifo_a; - next_tx_mem = next_tx_mem >> (32*tx_shift); - end - - always @(posedge i_clk) - if (!o_tx_mem_valid || i_tx_mem_ready) - o_tx_mem_data <= next_tx_mem[31:0]; - // }}} - - // o_tx_mem_last - // {{{ - always @(posedge i_clk) - if (!o_tx_mem_valid || i_tx_mem_ready) - o_tx_mem_last <= tx_fifo_last; - // }}} - - // Writing to memory - - // Take a clock to arbitrate writes - // {{{ - // WARNING: This isn't a proper arbiter. There is no ability to stall - // at present if multiple sources attempt to write to the FIFO at the - // same time. Hence always make sure to write to the FIFO that isn't - // currently in use. It is the software's responsibility to ping-pong. - // Failing to ping pong may result in corruption. - // - - // mem_wr_[strb|addr|data]_a: Arbitrate writes to FIFO A - // {{{ - initial mem_wr_strb_a = 0; - always @(posedge i_clk) - begin - mem_wr_strb_a <= 0; - - if (i_wb_stb && i_wb_we && i_wb_addr == ADDR_FIFOA - && (|i_wb_sel)) - begin - mem_wr_addr_a <= fif_wraddr; - mem_wr_strb_a <= i_wb_sel; - mem_wr_data_a <= i_wb_data; - end - - if (!r_fifo && i_cmd_mem_valid) - begin - mem_wr_addr_a <= i_cmd_mem_addr; - mem_wr_strb_a <= i_cmd_mem_strb; - mem_wr_data_a <= i_cmd_mem_data; - end - - if (!r_fifo && i_rx_mem_valid) - begin - mem_wr_addr_a <= i_rx_mem_addr; - mem_wr_strb_a <= i_rx_mem_strb; - mem_wr_data_a <= i_rx_mem_data; - end - - if (i_reset || o_soft_reset) - mem_wr_strb_a <= 0; - end - // }}} - - // mem_wr_[strb|addr|data]_b: Arbitrate writes to FIFO B - // {{{ - initial mem_wr_strb_b = 0; - always @(posedge i_clk) - begin - mem_wr_strb_b <= 0; - - if (i_wb_stb && i_wb_we && i_wb_addr == ADDR_FIFOB - && (|i_wb_sel)) - begin - mem_wr_addr_b <= fif_wraddr; - mem_wr_strb_b <= i_wb_sel; - mem_wr_data_b <= i_wb_data; - end - - if (r_fifo && i_cmd_mem_valid) - begin - mem_wr_addr_b <= i_cmd_mem_addr; - mem_wr_strb_b <= i_cmd_mem_strb; - mem_wr_data_b <= i_cmd_mem_data; - end - - if (r_fifo && i_rx_mem_valid) - begin - mem_wr_addr_b <= i_rx_mem_addr; - mem_wr_strb_b <= i_rx_mem_strb; - mem_wr_data_b <= i_rx_mem_data; - end - - if (i_reset || o_soft_reset) - mem_wr_strb_b <= 0; - end - // }}} - -`ifdef FORMAL - always @(*) - if (!i_reset) - assert(!i_cmd_mem_valid || !i_rx_mem_valid); -`endif - // }}} - - // Actually write to the memories - // {{{ - always @(posedge i_clk) - for(ika=0; ika= (1<<(lgblk-2))-1)); - end - - if (!tx_pipe_valid) - begin - assert(tx_mem_addr == 0); - end else if (!o_tx_mem_valid) - assert(tx_mem_addr == 1); - end - - always @(*) - if (!i_reset && o_tx_en && r_tx_sent) - assert(!tx_pipe_valid && !o_tx_mem_valid); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Register checking - // {{{ - - reg f_past_soft; - always @(posedge i_clk) - f_past_soft <= o_soft_reset; - - // PHY register - // {{{ - fwb_register #( - .AW(3), .DW(MW), .ADDR(ADDR_PHY), - .MASK(32'h0018_b100 - | (OPT_SERDES ? 32'h001f_0200 : 32'h00) - | (OPT_DDR ? 32'h001c_0000 : 32'h00)), - .FIXED_BIT_MASK(32'hf0e0_0000 - | (OPT_SERDES ? 32'h00: 32'h0003_0200) - | (OPT_DDR ? 32'h00: 32'h0004_0000)) - ) fwb_phy ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || o_soft_reset), - .i_wb_stb(i_wb_stb), .i_wb_we(i_wb_we), - .i_wb_addr(i_wb_addr), .i_wb_data(i_wb_data), - .i_wb_sel(i_wb_sel), - .i_wb_ack(pre_ack && !f_past_soft), - .i_wb_return(pre_data), - .i_register(w_phy_ctrl) - // }}} - ); - - always @(*) - if (!i_reset) - begin - assert(r_width != 2'b11); - if (NUMIO < 4) - assert(r_width == WIDTH_1W); - else if (NUMIO < 8) - assert(r_width == WIDTH_1W || r_width == WIDTH_4W); - end - - always @(*) - if (!i_reset && o_cfg_ds) - assert(o_cfg_ddr); - - always @(*) - if (!i_reset) - begin - assert(lgblk <= LGFIFO); - assert(lgblk >= 2); - end - - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Careless assumptions - // {{{ - - always @(*) - if (o_rx_en || o_tx_en) - assume(lgblk < 15); // Assume no overflow ... for now - - // Assume the user won't do something dumb, like write to the same FIFO - // we're reading from, or either read or write from the same FIFO we - // are writing to - // {{{ - always @(*) - if (o_tx_en || r_tx_request) - assume(!i_wb_stb || !i_wb_we - || i_wb_addr != ADDR_FIFOA + r_fifo); - - always @(*) - if (cmd_busy && o_cmd_type == R2_REPLY) - assume(!i_wb_stb || i_wb_addr != ADDR_FIFOA + r_fifo); - - always @(*) - if (o_rx_en || r_rx_request) - assume(!i_wb_stb || i_wb_addr != ADDR_FIFOA + r_fifo); - // }}} - // }}} -`endif // FORMAL -// }}} -endmodule - diff --git a/delete_later/rtl/sdspi/spicmd.v b/delete_later/rtl/sdspi/spicmd.v deleted file mode 100644 index a8bde3f..0000000 --- a/delete_later/rtl/sdspi/spicmd.v +++ /dev/null @@ -1,508 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: spicmd.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Issues commands and collects responses from the lower level -// SPI processor. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module spicmd ( - // {{{ - input wire i_clk, i_reset, - // - input wire i_cmd_stb, - input wire [1:0] i_cmd_type, - input wire [5:0] i_cmd, - input wire [31:0] i_cmd_data, - output reg o_busy, - // - output wire o_ll_stb, - output wire [7:0] o_ll_byte, - input wire i_ll_busy, - // - input wire i_ll_stb, - input wire [7:0] i_ll_byte, - // - output reg o_cmd_sent, - output reg o_rxvalid, - output reg [39:0] o_response - // }}} - ); - - // Signal declarations - // {{{ - reg almost_sent; - reg [4:0] crc_valid_sreg; - reg crc_busy; - reg [4:0] crc_bit_counter; - reg [39:0] crc_shift_reg, shift_data; - reg [7:0] crc_byte; - reg rx_r1_byte, rx_check_busy, rxvalid; - reg [2:0] rx_counter; - localparam CRC_POLYNOMIAL = 7'h09; // Was 8'h12 - reg [6:0] next_crc_byte; - // }}} - - // o_busy - // {{{ - initial o_busy = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_busy <= 1'b0; - else if (!o_busy && i_cmd_stb) - o_busy <= 1'b1; - // else if (o_rxvalid) - else if (rxvalid && !rx_check_busy) - o_busy <= 1'b0; - // }}} - - // shift_data - // {{{ - initial shift_data = -1; - always @(posedge i_clk) - if (!o_busy && i_cmd_stb) - shift_data <= { 2'b01, i_cmd, i_cmd_data }; - else if (!i_ll_busy) - begin - shift_data <= { shift_data[31:0], 8'hff }; - if (crc_valid_sreg[0]) - shift_data[39:32] <= crc_byte; - end - // }}} - - assign o_ll_stb = o_busy; - assign o_ll_byte = shift_data[39:32]; - - // o_cmd_sent - // {{{ - initial o_cmd_sent = 1'b0; - always @(posedge i_clk) - if (i_reset || !o_busy) - { o_cmd_sent, almost_sent } <= 2'b00; - else if (!o_cmd_sent && !i_ll_busy) - { o_cmd_sent, almost_sent } <= { almost_sent, crc_valid_sreg[0] }; - // }}} - - // crc_valid_sreg - // {{{ - initial crc_valid_sreg = 5'b10000; - always @(posedge i_clk) - if (!o_busy) - crc_valid_sreg <= 5'b10000; - else if (!i_ll_busy) - crc_valid_sreg <= crc_valid_sreg >> 1; - // }}} - - // crc_busy, crc_bit_counter - // {{{ - initial crc_busy = 1'b0; - initial crc_bit_counter = 20; - always @(posedge i_clk) - if (!o_busy) - begin - crc_bit_counter <= 20; - crc_busy <= (i_cmd_stb); - end else if (crc_busy) - begin - crc_bit_counter <= crc_bit_counter - 1; - crc_busy <= (crc_bit_counter > 1); - end - // }}} - - // crc_shift_reg - // {{{ - always @(posedge i_clk) - if (!o_busy) - crc_shift_reg <= { 2'b01, i_cmd, i_cmd_data }; - else if (crc_busy) - crc_shift_reg <= crc_shift_reg << 2; - // }}} - - // next_crc_byte - // {{{ - always @(*) - begin - next_crc_byte = { crc_byte[6:1], 1'b0 }; - if (crc_byte[7] ^ crc_shift_reg[39]) - next_crc_byte = next_crc_byte ^ CRC_POLYNOMIAL; - if (next_crc_byte[6] ^ crc_shift_reg[38]) - next_crc_byte = (next_crc_byte<<1) ^ CRC_POLYNOMIAL; - else - next_crc_byte = (next_crc_byte<<1); - end - // }}} - - // crc_byte - // {{{ - initial crc_byte = 0; - always @(posedge i_clk) - if (!o_busy) - crc_byte <= 1; - else if (crc_busy) - crc_byte <= { next_crc_byte, 1'b1 }; - // }}} - - // rx_r1_byte, rx_counter, rxvalid, rx_check_busy - // {{{ - initial rxvalid = 1'b0; - initial rx_counter = 1; - always @(posedge i_clk) - if (!o_busy) - begin - rx_r1_byte <= 1'b0; - rx_counter <= (i_cmd_type[1]) ? 5 : 1; - rx_check_busy <= (i_cmd_type == 2'b01); - rxvalid <= 1'b0; - end else if (o_cmd_sent && i_ll_stb) - begin - if (!rx_r1_byte) - rx_r1_byte <= (!i_ll_byte[7]); - - if ((rx_r1_byte || !i_ll_byte[7]) && !rxvalid) - begin - rx_counter <= rx_counter - 1; - rxvalid <= (rx_counter <= 1); - end - - if (rx_r1_byte && i_ll_byte != 0) - rx_check_busy <= 1'b0; - end - // }}} - - // o_rxvalid - // {{{ - initial o_rxvalid = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - o_rxvalid <= 0; - else if (rxvalid && !rx_check_busy) - o_rxvalid <= 1; - // }}} - - // o_response - // {{{ - initial o_response = -1; - always @(posedge i_clk) - if (!o_busy) - o_response <= -1; - else if (i_ll_stb) - begin - if (!rx_r1_byte) - o_response[39:32] <= i_ll_byte; - else - o_response[31:0] <= { o_response[23:0], i_ll_byte }; - end - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`ifdef SPICMD -`define ASSUME assume -`else -`define ASSUME assert -`endif - reg f_past_valid; - reg [2:0] f_send_seq; - reg [3:0] f_rcv_seq; - reg [5:0] f_cmd; - reg [31:0] f_data; - reg [1:0] f_type; - reg [39:0] f_rcv_data; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!o_cmd_sent) - begin - assert(!o_rxvalid); - assert(!rxvalid || !o_busy); - end else - assert(&shift_data); - - always @(*) - if (!rxvalid) - assert(!o_rxvalid); - - initial f_send_seq = 0; - always @(posedge i_clk) - if (i_reset || (o_busy && rxvalid && !rx_check_busy)) - f_send_seq <= 0; - else if (!o_busy) - f_send_seq <= (i_cmd_stb) ? 1:0; - else if (o_busy && !o_cmd_sent && (f_send_seq < 7)) - f_send_seq <= f_send_seq + (i_ll_busy ? 0:1); - - always @(posedge i_clk) - if (!o_busy) - { f_cmd, f_data, f_type } <= { i_cmd, i_cmd_data, i_cmd_type }; - - always @(*) - if (i_reset || !o_busy) - begin - if (!o_busy) - assert(f_send_seq == 0); - end else case(f_send_seq) - 1: begin - assert(shift_data == { 2'b01, f_cmd, f_data }); - assert(o_busy); - assert({ o_cmd_sent, almost_sent } == 2'b00); - assert(crc_valid_sreg == 5'b1_0000); - end - 2: begin - assert(shift_data == { f_data, 8'hff }); - assert(o_busy); - assert({ o_cmd_sent, almost_sent } == 2'b00); - assert(crc_valid_sreg == 5'b1000); - end - 3: begin - assert(shift_data == { f_data[23:0], 16'hffff }); - assert(o_busy); - assert({ o_cmd_sent, almost_sent } == 2'b00); - assert(crc_valid_sreg == 5'b100); - end - 4: begin - assert(shift_data == { f_data[15:0], 24'hffffff }); - assert(o_busy); - assert({ o_cmd_sent, almost_sent } == 2'b00); - assert(crc_valid_sreg == 5'b10); - end - 5: begin - assert(shift_data == { f_data[7:0], 32'hffffffff }); - assert(o_busy); - assert({ o_cmd_sent, almost_sent } == 2'b00); - assert(crc_valid_sreg == 5'b1); - end - 6: begin - assert(shift_data == { crc_byte, 32'hffffffff }); - assert(o_busy); - assert({ o_cmd_sent, almost_sent } == 2'b01); - assert(crc_valid_sreg == 5'b0); - end - 7: begin - assert(shift_data == 40'hff_ffff_ffff); - assert(crc_valid_sreg == 5'b0); - assert(o_cmd_sent); - end - endcase - - always @(*) - if (o_busy) - begin - assert(f_send_seq != 0); - assert(f_rcv_seq != 0); - end - - always @(*) - assert(crc_bit_counter <= 20); - - always @(*) - if (o_busy) - assert(crc_busy == (crc_bit_counter > 0)); - - // Got to give the CRC enough time to work - always @(*) - if (!o_cmd_sent) - begin - // if (crc_bit_counter > 4) - // `ASSUME(f_send_seq < 3); - if (crc_bit_counter > 2) - `ASSUME(f_send_seq < 4); - if (crc_bit_counter > 0) - `ASSUME(f_send_seq < 5); - end - - always @(*) - if (o_busy && !o_cmd_sent) - assume(i_ll_byte == 8'hff); - - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - if (o_busy && !o_cmd_sent) - begin - assert(f_rcv_seq == 1); - assert(&o_response); - end - - initial f_rcv_seq = 0; - always @(posedge i_clk) - if (i_reset) - f_rcv_seq <= 0; - else if (!o_busy) - f_rcv_seq <= (i_cmd_stb) ? 1 : 0; - else if (o_cmd_sent && i_ll_stb) - begin - assert(f_rcv_seq != 0); - if (!rx_r1_byte) - begin - if (!i_ll_byte[7]) casez(f_type) - 2'b00: f_rcv_seq <= 3; // R1 response - 2'b01: f_rcv_seq <= 2; // R1b response - 2'b1?: f_rcv_seq <= 4; // R3/R7 response - endcase - end else case(f_rcv_seq) - 1: begin assert(0); end // Should never be here - 2: begin - if (i_ll_byte != 0) - f_rcv_seq <= 3; - end - 3: begin end // We'll stop here with R1b - 4: f_rcv_seq <= f_rcv_seq + 1; - 5: f_rcv_seq <= f_rcv_seq + 1; - 6: f_rcv_seq <= f_rcv_seq + 1; - 7: f_rcv_seq <= f_rcv_seq + 1; - default: begin end - endcase - end - - always @(posedge i_clk) - if (i_ll_stb) - begin - if (!rx_r1_byte) - f_rcv_data[39:32] <= i_ll_byte; - else - f_rcv_data[31:0] <= { f_rcv_data[23:0], i_ll_byte }; - end - - always @(*) - if (!i_reset && o_busy && f_rcv_seq > 0) - case(f_rcv_seq) - 1: begin - assert(!rx_r1_byte); - assert(rx_counter == ((f_type[1]) ? 5 : 1)); - assert(rx_check_busy == (f_type == 2'b01)); - assert(!rxvalid); - assert(f_send_seq != 0); - assert(&o_response[31:0]); - end - 2: begin - assert(o_cmd_sent); - assert(rx_r1_byte); - assert(rx_counter == 0); - assert(rx_check_busy); - assert(rxvalid); - assert(o_response[39:32] == f_rcv_data[39:32]); - // assert(&o_response[31:0]); - end - 3: begin - assert(o_cmd_sent); - assert(rx_r1_byte); - assert(rx_counter == 0); - assert(!rx_check_busy); - assert(rxvalid); - assert(o_response[39:32] == f_rcv_data[39:32]); - // assert(&o_response[31:8]); - end - 4: begin - assert(rx_r1_byte); - assert(rx_counter == 4); - assert(!rx_check_busy); - assert(!rxvalid); - assert(o_response[39:32] == f_rcv_data[39:32]); - assert(&o_response[31:0]); - end - 5: begin - assert(rx_r1_byte); - assert(rx_counter == 3); - assert(!rx_check_busy); - assert(!rxvalid); - assert(o_response[39:32] == f_rcv_data[39:32]); - assert(o_response[7:0] == f_rcv_data[7:0]); - assert(&o_response[31:8]); - end - 6: begin - assert(rx_r1_byte); - assert(rx_counter == 2); - assert(!rx_check_busy); - assert(!rxvalid); - assert(o_response[39:32] == f_rcv_data[39:32]); - assert(o_response[15:0] == f_rcv_data[15:0]); - assert(&o_response[31:16]); - end - 7: begin - assert(rx_r1_byte); - assert(rx_counter == 1); - assert(!rx_check_busy); - assert(!rxvalid); - assert(o_response[39:32] == f_rcv_data[39:32]); - assert(o_response[23:0] == f_rcv_data[23:0]); - assert(&o_response[31:24]); - end - 8: begin - assert(rx_r1_byte); - assert(rx_counter == 0); - assert(!rx_check_busy); - assert(rxvalid); - assert(o_response[39:32] == f_rcv_data[39:32]); - end - default: assert(f_rcv_seq <= 8); - endcase - - always @(*) - assert(rxvalid == (rx_counter == 0)); - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - begin - cover(o_cmd_sent); - cover(f_rcv_seq == 1); - cover(f_rcv_seq == 2); - cover(f_rcv_seq == 3); - cover(f_rcv_seq == 4); - cover(f_rcv_seq == 5); - cover(f_rcv_seq == 6); - cover(f_rcv_seq == 7); - cover(f_rcv_seq == 8); - end - - always @(posedge i_clk) - cover(o_rxvalid && f_cmd == 0 && f_data == 0); - - always @(posedge i_clk) - cover(o_rxvalid && f_cmd == 0 && f_data == 0 - && crc_byte == 8'h95); -`endif -// }}} -endmodule diff --git a/delete_later/rtl/sdspi/spirxdata.v b/delete_later/rtl/sdspi/spirxdata.v deleted file mode 100644 index ff875af..0000000 --- a/delete_later/rtl/sdspi/spirxdata.v +++ /dev/null @@ -1,691 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: spirxdata.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: To handle all of the processing associated with receiving data -// from an SD card via the lower-level SPI processor, and then -// issuing write commands to our internal memory store (external to this -// module). -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module spirxdata #( - // {{{ - parameter DW = 32, AW = 8, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - localparam CRC_POLYNOMIAL = 16'h1021 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire i_start, - input wire [3:0] i_lgblksz, - input wire i_fifo, - output reg o_busy, - // - input wire i_ll_stb, - input wire [7:0] i_ll_byte, - // - output reg o_write, - output reg [AW-1:0] o_addr, - output reg [DW-1:0] o_data, - // - output reg o_rxvalid, - output reg [7:0] o_response - // }}} - ); - - // Signal declarations - // {{{ - reg error_token, start_token, token, received_token, done, - lastaddr; - reg all_mem_written, lastdata; - - reg [1:0] crc_byte; - reg [2:0] r_lgblksz_m3; - reg new_data_byte; - reg [3:0] crc_fill; - reg [7:0] crc_gearbox; - reg [15:0] next_crc_data; - reg [15:0] crc_data; - reg crc_err, crc_active; - reg [2:0] fill; - reg [23:0] gearbox; - reg [15:0] first_crc_data; - // }}} - - // error_token - // {{{ - always @(*) - begin - error_token = 0; - - if (i_ll_byte[7:4] == 0) - error_token = 1; - if (!i_ll_stb || received_token) - error_token = 0; - end - // }}} - - // start_token - // {{{ - always @(*) - begin - start_token = 0; - - if (!i_ll_byte[0]) - start_token = 1; - if (!i_ll_stb || received_token) - start_token = 0; - end - // }}} - - // token - // {{{ - always @(*) - token = (start_token || error_token); - // }}} - - // done - // {{{ - always @(*) - done = (i_ll_stb && (crc_byte>1)); - // }}} - - // received_token - // {{{ - initial received_token = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - received_token <= 0; - else if (token) - received_token <= 1; - // }}} - - // o_busy - // {{{ - initial o_busy = 0; - always @(posedge i_clk) - if (i_reset) - o_busy <= 0; - else if (!o_busy) - o_busy <= i_start; - else if (error_token || done) - o_busy <= 0; - // }}} - - // o_rxvalid - // {{{ - initial o_rxvalid = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - o_rxvalid <= 0; - else if (error_token || done) - o_rxvalid <= 1; - // }}} - - // o_response - // {{{ - initial o_response = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - o_response <= 0; - else if (error_token) - o_response <= i_ll_byte; - else if (done) - o_response <= (crc_err || (crc_data[7:0] != i_ll_byte)) ? 8'h10 : 0; - // }}} - - // o_write - // {{{ - initial o_write = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - o_write <= 0; - else if (received_token && !all_mem_written) - o_write <= (&fill) && i_ll_stb; - else - o_write <= 0; - // }}} - - // o_data - // {{{ - initial o_data = 0; - always @(posedge i_clk) - if (received_token && !all_mem_written) - begin - if (OPT_LITTLE_ENDIAN) - o_data <= { i_ll_byte, gearbox }; - else - o_data <= { gearbox, i_ll_byte }; - end - // }}} - - // o_addr - // {{{ - always @(posedge i_clk) - if (!o_busy) - o_addr <= { i_fifo, {(AW-1){1'b0}} }; - else if (o_write && !lastaddr) - o_addr <= o_addr + 1; - // }}} - - // fill - // {{{ - initial fill = 0; - always @(posedge i_clk) - begin - if (i_ll_stb) - begin - if (OPT_LITTLE_ENDIAN) - gearbox <= { i_ll_byte, gearbox[23:8] }; - else - gearbox <= { gearbox[15:0], i_ll_byte }; - end - - if (!o_busy || !received_token) - fill <= 0; - else if ((&fill) && i_ll_stb) - fill <= 0; - else if (i_ll_stb) - fill <= { fill[1:0], 1'b1 }; - end - // }}} - - // lastdata - // {{{ - always @(posedge i_clk) - if (!o_busy) - lastdata <= 0; - else if (!lastdata) - lastdata <= (lastaddr && (&fill)); - // }}} - - // all_mem_written - // {{{ - initial all_mem_written = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - all_mem_written <= 0; - else if (o_write && lastaddr) - all_mem_written <= 1; - // }}} - - // crc_byte - // {{{ - initial crc_byte = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - crc_byte <= 0; - else if (i_ll_stb && lastaddr && lastdata) - crc_byte <= crc_byte + 1; - // }}} - - // lastaddr, r_lgblksz_m3 - // {{{ - initial r_lgblksz_m3 = 0; - initial lastaddr = 0; - always @(posedge i_clk) - if (!o_busy) - begin - lastaddr <= (i_lgblksz < 4); - // Verilator lint_off WIDTH - r_lgblksz_m3 <= i_lgblksz-3; - // Verilator lint_on WIDTH - end else if (o_write && !lastaddr) - begin - case(r_lgblksz_m3) - 0: lastaddr <= 1; // 8 bytes - 1: lastaddr <= (&o_addr[1:1]); // 16 bytes - 2: lastaddr <= (&o_addr[2:1]); // 32 bytes - 3: lastaddr <= (&o_addr[3:1]); // 64 bytes - 4: lastaddr <= (&o_addr[4:1]); // 128 bytes - 5: lastaddr <= (&o_addr[5:1]); // 256 bytes - default: lastaddr <= (&o_addr[6:1]); // 512 bytes - endcase - end - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // CRC calculation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // new_data_byte - // {{{ - always @(*) - new_data_byte = (i_ll_stb && !all_mem_written); - // }}} - - // crc_fill, crc_active - // {{{ - initial crc_fill = 0; - initial crc_active = 0; - always @(posedge i_clk) - if (i_reset || !o_busy || !received_token) - begin - crc_fill <= 0; - crc_active <= 0; - end else if (crc_active || new_data_byte) - begin - // Verilator lint_off WIDTH - crc_fill <= crc_fill - (crc_active ? 1:0) - + (new_data_byte ? 4:0); - // Verilator lint_on WIDTH - if (new_data_byte) - crc_active <= 1; - else - crc_active <= (crc_fill > 1); - end - // }}} - - // crc_gearbox - // {{{ - always @(posedge i_clk) - if (!crc_active) - crc_gearbox <= i_ll_byte; - else - crc_gearbox <= { crc_gearbox[8-3:0], 2'b00 }; - // }}} - - - // first_crc_data, next_crc_data - // {{{ - always @(*) - begin - first_crc_data = crc_data << 1;; - - if (crc_data[15] ^ crc_gearbox[7]) - first_crc_data = first_crc_data ^ CRC_POLYNOMIAL; - - if (first_crc_data[15] ^ crc_gearbox[6]) - next_crc_data = (first_crc_data << 1) ^ CRC_POLYNOMIAL; - else - next_crc_data = (first_crc_data << 1); - end - // }}} - - // crc_data - // {{{ - initial crc_data = 0; - always @(posedge i_clk) - if (!o_busy) - crc_data <= 0; - else if (crc_active) - crc_data <= next_crc_data; - // }}} - - // crc_err - // {{{ - initial crc_err = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - crc_err <= 0; - else if (i_ll_stb && (crc_byte == 1)) - crc_err <= (crc_data[15:8] != i_ll_byte); - // else if (i_ll_stb && (crc_byte == 2) - // crc_err <= (crc_data[7:0] != i_ll_byte); - // }}} - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`ifdef SPIRXDATA -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - reg [3:0] f_lgblksz; - wire [3:0] f_lgblksz_m3; - reg f_fifo; - - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - // Reset check(s) - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - assert(!o_busy); - assert(o_write == 0); - end - - always @(posedge i_clk) - if (!f_past_valid || !$past(o_busy)) - begin - assert(!o_rxvalid); - assert(crc_fill == 0); - end - - always @(*) - if (!o_busy) - assert(!o_write); - - //////////////////////////////////////////////////////////////////////// - // - // Data assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg [6:0] f_last_read; - - initial f_last_read = 0; - always @(posedge i_clk) - begin - f_last_read <= f_last_read << 1; - if (i_ll_stb) - f_last_read[0] <= 1; - end - -`ifdef VERIFIC - always @(*) - `ASSUME($onehot0({f_last_read, i_ll_stb})); -`else - always @(*) - case({f_last_read, i_ll_stb}) - 8'h00: begin end - 8'h01: begin end - 8'h02: begin end - 8'h04: begin end - 8'h08: begin end - 8'h10: begin end - 8'h20: begin end - 8'h40: begin end - 8'h80: begin end - default: `ASSUME(0); - endcase -`endif - - always @(*) - if (!o_busy && i_start) - begin - `ASSUME(i_lgblksz <= 9); - `ASSUME(i_lgblksz >= 3); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Induction assertions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (o_busy) - assert(crc_active == (crc_fill > 0)); - - always @(*) - if (o_write) - assert(fill == 0); - - always @(*) - if (o_busy && crc_byte > 0) - begin - assert(lastaddr); - assert(all_mem_written || o_write); - assert(lastdata); - end - - always @(*) - if (o_busy && all_mem_written) - begin - assert(lastaddr); - assert(lastdata); - end - - always @(*) - if (o_busy && lastdata) - begin - assert(lastaddr); - assert((&fill) || o_write || all_mem_written); - end - - always @(posedge i_clk) - if (!o_busy) - begin - f_lgblksz <= i_lgblksz; - f_fifo <= i_fifo; - end - - assign f_lgblksz_m3 = f_lgblksz - 3; - - always @(*) - if (o_busy) - begin - assert(f_lgblksz >= 3); - assert(f_lgblksz <= 9); - - assert(o_addr[AW-1] == f_fifo); - - if (!received_token) - begin - assert((f_lgblksz == 3) || !lastaddr); - assert(o_addr[AW-2:0] == 0); - assert(fill == 0); - end - end - - always @(*) - if (o_busy) - assert(f_lgblksz_m3[2:0] == r_lgblksz_m3); - - always @(*) - if (o_busy) - case(r_lgblksz_m3) - 3'h0: assert(lastaddr); // 8 bytes - 3'h1: assert(lastaddr == (&o_addr[1:0])); // 16 bytes - 3'h2: assert(lastaddr == (&o_addr[2:0])); // 32 bytes - 3'h3: assert(lastaddr == (&o_addr[3:0])); // 64 bytes - 3'h4: assert(lastaddr == (&o_addr[4:0])); // 128 bytes - 3'h5: assert(lastaddr == (&o_addr[5:0])); // 256 bytes - default: assert(lastaddr == (&o_addr[AW-2:0])); - endcase - - always @(*) - if (o_busy) - case(r_lgblksz_m3) - 3'h0: assert(o_addr[AW-2:1] == 0); // 8 bytes - 3'h1: assert(o_addr[AW-2:2] == 0); // 16 bytes - 3'h2: assert(o_addr[AW-2:3] == 0); // 32 bytes - 3'h3: assert(o_addr[AW-2:4] == 0); // 64 bytes - 3'h4: assert(o_addr[AW-2:5] == 0); // 128 bytes - 3'h5: assert(o_addr[AW-2:6] == 0); // 256 bytes - default: begin end // assert(lastaddr == (&o_addr[AW-2:0])); - endcase - - always @(*) - if (fill != 0) - begin - assert(fill[0]); - if (!fill[1]) - assert(fill[2] == 0); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // CRC checks and properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - assert(crc_fill <= 4); - - always @(*) - if (o_busy && !received_token) - begin - assert(!crc_active); - assert(crc_fill == 0); - assert(crc_data == 0); - end - - always @(*) - if (crc_active) - begin - if (crc_data == 0 && crc_gearbox[7:6] == 0) - assert(next_crc_data == 0); - - if ((crc_data[15] ^ crc_gearbox[7]) - &&((crc_data[14] ^ crc_gearbox[6])==0)) - assert(next_crc_data == ({ crc_data[13:0], 2'b00 } ^ { CRC_POLYNOMIAL[14:0], 1'b0 })); - - if (((crc_data[15] ^ crc_gearbox[7])==0) - &&(crc_data[14] ^ crc_gearbox[6])) - assert(next_crc_data == ({ crc_data[13:0], 2'b00 } ^ CRC_POLYNOMIAL[14:0])); - end - - -/* - reg [5:0] f_read_seq; - (* anyseq *) reg f_read_check; - reg [DW-1:0] f_read_data; - - always @(posedge i_clk) - if (rdvalid[RDDELAY-1]) - f_read_data <= i_data; - - always @(*) - if (f_read_seq != 0) - assume(!f_read_check); - - initial f_read_seq = 0; - always @(posedge i_clk) - if (!o_busy) - f_read_seq <= 0; - else if (f_read_check && o_read) - f_read_seq <= 1; - else if (rdvalid != 0) - begin - if (rdvalid[RDDELAY-1]) - f_read_seq <= 2; - end else if (!i_ll_busy) - f_read_seq <= (f_read_seq << 1); - - always @(*) - if (i_reset || !o_busy || (f_read_seq == 0)) - begin end - else case(f_read_seq) - 6'h01: begin - assert(rdvalid != 0); - assert(fill == 5'h10); - end - 6'h02: begin - assert(rdvalid == 0); - assert(fill == 5'h1f); - assert(gearbox[DW-1:0] == f_read_data); - end - 6'h04: begin - assert(rdvalid == 0); - assert(fill == 5'h1e); - assert(gearbox[8+DW-1:8] == f_read_data); - end - 6'h08: begin - assert(rdvalid == 0); - assert(fill == 5'h1c); - assert(gearbox[8+DW-1:16] == f_read_data[23:0]); - end - 6'h10: begin - assert(rdvalid == 0); - assert(fill == 5'h18); - assert(gearbox[8+DW-1:24] == f_read_data[15:0]); - end - 6'h20: begin - assert(fill[4]); - assert(gearbox[8+DW-1:DW] == f_read_data[7:0]); - end - default: assert($onehot0(f_read_seq)); - endcase -*/ - // }}} -`ifdef SPIRXDATA - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // - reg cvr_packet_received; - - always @(*) - if (!received_token) - begin - cover(error_token); - cover(start_token); - end - - initial cvr_packet_received = 0; - always @(posedge i_clk) - if (i_reset || error_token) - cvr_packet_received <= 0; - else if (o_rxvalid) - cvr_packet_received <= 1; - - always @(posedge i_clk) - begin - cover(o_rxvalid); - cover(o_rxvalid && all_mem_written); - cover(o_rxvalid && f_lgblksz == 4 && all_mem_written); - cover(o_rxvalid && f_lgblksz == 4 && o_response == 0); - cover(o_rxvalid && f_lgblksz == 4 && o_response == 0 && all_mem_written); - - cover(o_busy && f_lgblksz == 4 && o_addr == 8'h01); - cover(o_busy && f_lgblksz == 4 && o_addr == 8'h02); - cover(o_busy && f_lgblksz == 4 && o_addr == 8'h03); - cover(o_busy && crc_byte == 0); - cover(o_busy && crc_byte == 1); - cover(o_busy && crc_byte == 2); - cover(o_busy && crc_byte == 1 && i_ll_stb); - cover(o_busy && crc_byte == 2 && i_ll_stb); - - cover(cvr_packet_received && !o_busy); - end - // }}} -`endif // SPIRXDATA -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/sdspi/spitxdata.v b/delete_later/rtl/sdspi/spitxdata.v deleted file mode 100644 index 8017144..0000000 --- a/delete_later/rtl/sdspi/spitxdata.v +++ /dev/null @@ -1,725 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: spitxdata.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: To handle all of the processing associated with sending data -// from a memory to our lower-level SPI processor. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module spitxdata #( - // {{{ - parameter DW = 32, AW = 8, RDDELAY = 2, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - localparam CRC_POLYNOMIAL = 16'h1021 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire i_start, - input wire [3:0] i_lgblksz, - input wire i_fifo, - output reg o_busy, - // - output reg o_read, - output reg [AW-1:0] o_addr, - input wire [DW-1:0] i_data, - // - input wire i_ll_busy, - output reg o_ll_stb, - output wire [7:0] o_ll_byte, - // - input wire i_ll_stb, - input wire [7:0] i_ll_byte, - // - output reg o_rxvalid, - output reg [7:0] o_response - // }}} - ); - - // Signal declarations - // {{{ - reg [RDDELAY-1:0] rdvalid; - reg [8+DW-1:0] gearbox; - reg [1+(DW/8)-1:0] fill; - reg crc_flag, crc_stb, data_read, - all_mem_read; - - reg lastaddr, data_sent, received_token, - all_idle; - reg crc_active; - reg [$clog2(1+DW/2)-1:0] crc_fill; - (* keep *) reg [DW-1:0] crc_gearbox; - reg [15:0] crc_data; - - reg token; - reg [2:0] r_lgblksz_m3; - reg [15:0] next_crc_data; - // }}} - - // token - // {{{ - always @(*) - token = (data_sent && i_ll_stb && i_ll_byte[0] &&!i_ll_byte[4]); - // }}} - - // o_busy - // {{{ - initial o_busy = 0; - always @(posedge i_clk) - if (i_reset) - o_busy <= 0; - else if (!o_busy) - o_busy <= i_start; - else if (all_idle && i_ll_stb && (&i_ll_byte)) - o_busy <= 0; - // }}} - - // o_rxvalid, received_token - // {{{ - initial o_rxvalid = 0; - initial received_token = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - { received_token, o_rxvalid } <= 0; - else if (token && !received_token) - { received_token, o_rxvalid } <= 2'b11; - else - o_rxvalid <= 0; - // }}} - - // all_idle - // {{{ - initial all_idle = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - all_idle <= 0; - else if (received_token && i_ll_stb && (&i_ll_byte)) - all_idle <= 1'b1; - // }}} - - // o_response - // {{{ - always @(posedge i_clk) - if (token) - o_response <= i_ll_byte; - // }}} - - // o_read & o_addr - // 0: arbited read request - // 1: read data - // 2: muxed read data - - // rdvalid - // {{{ - initial rdvalid = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - rdvalid <= 0; - else - rdvalid <= { rdvalid[RDDELAY-2:0], o_read }; - // }}} - - // o_ll_stb - // {{{ - initial o_ll_stb = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - o_ll_stb <= 0; - else if (rdvalid[RDDELAY-1]) - o_ll_stb <= 1; - else if (data_read && !fill[4]) - o_ll_stb <= 0; - // }}} - - // fill - // {{{ - initial fill = 0; - always @(posedge i_clk) - begin - if (!o_ll_stb && rdvalid[RDDELAY-1]) - begin - if (OPT_LITTLE_ENDIAN) - gearbox <= { i_data, 8'hfe }; - else - gearbox <= { 8'hfe, i_data }; - fill <= 5'h1f; - end else if (rdvalid[RDDELAY-1]) - begin - if (OPT_LITTLE_ENDIAN) - gearbox <= { i_data, gearbox[7:0] }; - else - gearbox <= { gearbox[DW+8-1:DW], i_data }; - fill <= 5'h1f; - end else if (crc_stb) - begin - if (OPT_LITTLE_ENDIAN) - gearbox <= { 16'hff, crc_data[7:0], crc_data[15:8], gearbox[7:0] }; - else - gearbox <= { gearbox[DW+8-1:DW], crc_data, 16'hff }; - fill[3:0] <= 4'hc; - end else if (o_ll_stb && !i_ll_busy) - begin - if (OPT_LITTLE_ENDIAN) - gearbox <= { 8'hff, gearbox[DW+8-1:8] }; - else - gearbox <= { gearbox[DW-1:0], 8'hff }; - fill <= fill << 1; - end - - if (!o_busy) - begin - if (OPT_LITTLE_ENDIAN) - gearbox[7:0] <= 8'hfe; // Start token - else - gearbox[39:32] <= 8'hfe; // Start token - end - - if (i_reset) - fill <= 0; - else if (!o_busy) - fill <= (i_start) ? 5'h10 : 0; - end - // }}} - - generate if (OPT_LITTLE_ENDIAN) - begin - assign o_ll_byte = gearbox[7:0]; - end else begin : GEN_BIG_ENDIAN - assign o_ll_byte = gearbox[39:32]; - end endgenerate - - // crc_stb, o_read - // {{{ - initial { crc_stb, o_read } = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - { crc_stb, o_read } <= 0; - else if (!fill[3] || (!fill[2] && (!o_ll_stb || !i_ll_busy))) - begin - { crc_stb, o_read } <= 0; - if (!o_read && rdvalid == 0 && !data_read) - begin - if (!all_mem_read) - o_read <= 1; - else - crc_stb <= (!crc_flag)&&(!crc_stb); - end - end else - { crc_stb, o_read } <= 0; - // }}} - - // o_addr - // {{{ - always @(posedge i_clk) - if (!o_busy) - o_addr <= { i_fifo, {(AW-1){1'b0}} }; - else if (o_read && !lastaddr) - o_addr[AW-2:0] <= o_addr[AW-2:0] + 1; - // }}} - - // all_mem_read - // {{{ - initial all_mem_read = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - all_mem_read <= 0; - else if (o_read && lastaddr) - all_mem_read <= 1; - // }}} - - // crc_flag - // {{{ - initial crc_flag = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - crc_flag <= 0; - else if (crc_stb) - crc_flag <= 1; - // }}} - - // data_read - // {{{ - always @(*) - data_read = crc_flag; - // }}} - - // data_sent - // {{{ - initial data_sent = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - data_sent <= 1'b0; - else if (data_read && !fill[3] && o_ll_stb && !i_ll_busy) - data_sent <= 1'b1; - // }}} - - // r_lgblksz_m3, lastaddr - // {{{ - initial r_lgblksz_m3 = 0; - initial lastaddr = 0; - always @(posedge i_clk) - if (!o_busy) - begin - lastaddr <= (i_lgblksz < 4); - // Verilator lint_off WIDTH - r_lgblksz_m3 <= i_lgblksz-3; - // Verilator lint_on WIDTH - end else if (o_read && !lastaddr) - begin - case(r_lgblksz_m3) - 0: begin end // assert(lastaddr); // 8 bytes - 1: lastaddr <= (&o_addr[1:1]); // 16 bytes - 2: lastaddr <= (&o_addr[2:1]); // 32 bytes - 3: lastaddr <= (&o_addr[3:1]); // 64 bytes - 4: lastaddr <= (&o_addr[4:1]); // 128 bytes - 5: lastaddr <= (&o_addr[5:1]); // 256 bytes - default: lastaddr <= (&o_addr[6:1]); // 512 bytes - endcase - end - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // CRC calculation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // crc_fill - // {{{ - initial crc_fill = 0; - always @(posedge i_clk) - if (i_reset || !o_busy) - begin - crc_fill <= 0; - crc_active <= 0; - end else if (crc_active || rdvalid[RDDELAY-1]) - begin - // Verilator lint_off WIDTH - crc_fill <= crc_fill - (crc_active ? 1:0) - + (rdvalid[RDDELAY-1] ? (DW/2):0); - // Verilator lint_on WIDTH - if (rdvalid[RDDELAY-1]) - crc_active <= 1; - else - crc_active <= (crc_fill > 1); - end - // }}} - - // crc_gearbox - // {{{ - always @(posedge i_clk) - if (!crc_active) - begin - if (OPT_LITTLE_ENDIAN) - crc_gearbox <= { i_data[7:0], i_data[15:8], i_data[23:16], i_data[31:24] }; - else - crc_gearbox <= i_data; - end else - crc_gearbox <= { crc_gearbox[DW-3:0], 2'b00 }; - // }}} - - // next_crc_data - // {{{ - always @(*) - begin - next_crc_data = crc_data << 1;; - - if (crc_data[15] ^ crc_gearbox[31]) - next_crc_data = next_crc_data ^ CRC_POLYNOMIAL; - - if (next_crc_data[15] ^ crc_gearbox[30]) - next_crc_data = (next_crc_data << 1) ^ CRC_POLYNOMIAL; - else - next_crc_data = (next_crc_data << 1); - end - // }}} - - // crc_data - // {{{ - always @(posedge i_clk) - if (!o_busy) - crc_data <= 0; - else if (crc_active) - crc_data <= next_crc_data; - // }}} - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`ifdef SPITXDATA -`define ASSUME assume -`else -`define ASSUME assert -`endif - - reg f_past_valid; - reg [3:0] f_lgblksz; - wire [3:0] f_lgblksz_m3; - - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - // Reset check(s) - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - assert(!o_ll_stb); - assert(!o_busy); - assert(rdvalid == 0); - assert(!o_rxvalid); - end - - always @(posedge i_clk) - if (!f_past_valid || !$past(o_busy)) - begin - assert(rdvalid == 0); - assert(!o_rxvalid); - if (!f_past_valid || $past(i_reset)) - assert(fill == 0); - else if ($past(i_start)) - assert(fill == 5'h10); - else - assert(fill == 0); - assert(crc_fill == 0); - end - - //////////////////////////////////////////////////////////////////////// - // - // Data assumptions - // - reg [6:0] f_last_read; - - initial f_last_read = 0; - always @(posedge i_clk) - begin - f_last_read <= f_last_read << 1; - if (o_ll_stb && !i_ll_busy) - f_last_read[0] <= 1; - end - -`ifdef VERIFIC - always @(*) - `ASSUME($onehot0({f_last_read, (o_ll_stb && !i_ll_busy)})); -`else - always @(*) - case({f_last_read, (o_ll_stb && !i_ll_busy)}) - 8'h00: begin end - 8'h01: begin end - 8'h02: begin end - 8'h04: begin end - 8'h08: begin end - 8'h10: begin end - 8'h20: begin end - 8'h40: begin end - 8'h80: begin end - default: `ASSUME(0); - endcase -`endif - - - always @(*) - if (i_start) - begin - `ASSUME(i_lgblksz <= 9); - `ASSUME(i_lgblksz > 2); - end - - always @(*) - if (crc_fill > 1) - begin - assert(o_ll_stb); - assert(!crc_stb); - end - - always @(*) - if (o_read || rdvalid != 0) - assert(!o_ll_stb || i_ll_busy); - - //////////////////////////////////////////////////////////////////////// - // - // Induction assertions - // - - always @(*) - if (rdvalid != 0) - assert(crc_fill <= 1); - - always @(*) - if (o_busy) - assert(crc_active == (crc_fill > 0)); - - always @(*) - if (o_read) - assert(rdvalid == 0); - else -`ifdef VERIFIC - assert($onehot0(rdvalid)); -`else - begin - assert((rdvalid == 0) - ||(rdvalid == 1) - ||(rdvalid == 2) - ||(rdvalid == 4)); - end -`endif - - always @(*) - if (o_busy && all_idle) - assert(received_token); - - always @(*) - if (o_busy && received_token) - assert(data_sent); - - always @(*) - if (o_busy && data_sent) - begin - assert(data_read); - assert(!crc_stb); - assert(!crc_active); - end - - always @(*) - if (crc_fill > 5'h0c) - assert(&fill[4:1]); - else if (crc_fill > 4) - assert(&fill[4:2]); - else if (crc_fill > 0) - assert(&fill[4:3]); - - always @(*) - assert(crc_fill <= 5'h10); - always @(*) - if (o_busy && data_read) - begin - assert(crc_flag); - assert(!crc_stb); - assert(!crc_active); - end - - always @(*) - if (o_busy && crc_flag) - begin - assert(!crc_stb); - assert(all_mem_read); - assert(!crc_active); - end - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && $past(o_busy)) - assert($rose(crc_flag) == $past(crc_stb)); - - always @(*) - if (o_busy && all_mem_read) - assert(lastaddr); - - always @(*) - if (o_busy && !lastaddr) - assert(!all_mem_read); - - always @(posedge i_clk) - if (!o_busy) - f_lgblksz <= i_lgblksz; - - assign f_lgblksz_m3 = f_lgblksz - 3; - - always @(*) - if(o_busy) - assert(f_lgblksz >= 3); - - always @(*) - if (o_busy) - assert(f_lgblksz_m3[2:0] == r_lgblksz_m3); - - always @(*) - if (o_busy) - case(r_lgblksz_m3) - 3'h0: assert(lastaddr); // 8 bytes - 3'h1: assert(lastaddr == (&o_addr[1:0])); // 16 bytes - 3'h2: assert(lastaddr == (&o_addr[2:0])); // 32 bytes - 3'h3: assert(lastaddr == (&o_addr[3:0])); // 64 bytes - 3'h4: assert(lastaddr == (&o_addr[4:0])); // 128 bytes - 3'h5: assert(lastaddr == (&o_addr[5:0])); // 256 bytes - default: assert(lastaddr == (&o_addr[AW-2:0])); - endcase - - always @(*) - if (o_ll_stb && !data_sent) - assert(fill[4]); - - always @(*) - if (fill != 0) - assert(fill[DW/8]); - - genvar k; - - generate for(k=DW/8; k>0; k=k-1) - begin - always @(*) - if ((fill != 0) && !fill[k]) - assert(fill[k-1:0]==0); - end endgenerate - - always @(posedge i_clk) - if (f_past_valid && $past(crc_stb)) - assert(!crc_stb); - -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal property section -// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef SPITXDATA - reg [5:0] f_read_seq; - (* anyseq *) reg f_read_check; - reg [DW-1:0] f_read_data; - - always @(posedge i_clk) - if (rdvalid[RDDELAY-1]) - f_read_data <= i_data; - - always @(*) - if (f_read_seq != 0) - assume(!f_read_check); - - initial f_read_seq = 0; - always @(posedge i_clk) - if (!o_busy) - f_read_seq <= 0; - else if (f_read_check && o_read) - f_read_seq <= 1; - else if (rdvalid != 0) - begin - if (rdvalid[RDDELAY-1]) - f_read_seq <= 2; - end else if (!i_ll_busy) - f_read_seq <= (f_read_seq << 1); - - always @(*) - if (i_reset || !o_busy || (f_read_seq == 0)) - begin end - else case(f_read_seq) - 6'h01: begin - assert(rdvalid != 0); - assert(fill == 5'h10); - end - 6'h02: begin - assert(o_ll_stb); - assert(rdvalid == 0); - assert(fill == 5'h1f); - if (OPT_LITTLE_ENDIAN) - assert(gearbox[DW+8-1:8] == f_read_data); - else - assert(gearbox[DW-1:0] == f_read_data); - end - 6'h04: begin - assert(o_ll_stb); - assert(rdvalid == 0); - assert(fill == 5'h1e); - if (OPT_LITTLE_ENDIAN) - assert(gearbox[DW-1:0] == f_read_data); - else - assert(gearbox[8+DW-1:8] == f_read_data); - end - 6'h08: begin - assert(o_ll_stb); - assert(rdvalid == 0); - assert(fill == 5'h1c); - if (OPT_LITTLE_ENDIAN) - assert(gearbox[DW-8-1:0] == f_read_data[31:8]); - else - assert(gearbox[8+DW-1:16] == f_read_data[23:0]); - end - 6'h10: begin - assert(o_ll_stb); - assert(rdvalid == 0); - assert(fill == 5'h18); - if (OPT_LITTLE_ENDIAN) - assert(gearbox[DW-16-1:0] == f_read_data[31:16]); - else - assert(gearbox[8+DW-1:24] == f_read_data[15:0]); - end - 6'h20: begin - assert(o_ll_stb); - assert(fill[4]); - if (OPT_LITTLE_ENDIAN) - assert(gearbox[DW-24-1:0] == f_read_data[31:24]); - else - assert(gearbox[8+DW-1:DW] == f_read_data[7:0]); - end - default: -`ifdef VERIFIC - assert($onehot0(f_read_seq)); -`else - if (f_read_seq) - assert(0); -`endif - endcase -`endif - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // - always @(posedge i_clk) - begin - cover(f_lgblksz == 4 && o_rxvalid); - cover(o_busy && f_lgblksz == 4 && o_addr == 8'h00); - cover(o_busy && f_lgblksz == 4 && o_addr == 8'h01); - cover(o_busy && f_lgblksz == 4 && o_addr == 8'h02); - cover(o_busy && f_lgblksz == 4 && o_addr == 8'h03); - cover(o_busy && f_lgblksz == 4 && lastaddr); - cover(o_busy && f_lgblksz == 4 && crc_stb); - cover(o_busy && f_lgblksz == 4 && all_mem_read); - cover(o_busy && f_lgblksz == 4 && crc_flag); - cover(o_busy && f_lgblksz == 4 && data_read); - cover(o_busy && f_lgblksz == 4 && data_sent); - cover(o_busy && f_lgblksz == 4 && received_token); - cover(o_busy && f_lgblksz == 4 && all_idle); - cover(!o_busy && f_lgblksz == 4 && all_idle); - end -`endif -// }}} -endmodule diff --git a/delete_later/rtl/sdspi/xsdddr.v b/delete_later/rtl/sdspi/xsdddr.v deleted file mode 100644 index 7390742..0000000 --- a/delete_later/rtl/sdspi/xsdddr.v +++ /dev/null @@ -1,147 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: xsdddr.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: An 2:1 OSERDES followed by an (optional) 1:2 ISERDES implemented -// via the Xilinx ODDR and IDDR elements. That simple, nothing -// more. This implementation is specific to Xilinx FPGAs. It's designed, -// however, so that there may be a minimum number of components that -// need replacing when switching hardware platforms. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -`ifdef VERILATOR -`define OPENSIM -`endif -`ifdef IVERILOG -`define OPENSIM -`endif -// }}} -module xsdddr #( - parameter [0:0] OPT_BIDIR = 1'b1 - ) ( - // {{{ - input wire i_clk, - // - input wire i_en, - input wire [1:0] i_data, - output wire io_pin_tristate, - input wire i_pin, - output wire o_pin, - output wire [1:0] o_wide - // }}} - ); - - wire w_in, w_out; - reg high_z; - - initial high_z = OPT_BIDIR; - always @(posedge i_clk) - high_z <= !i_en && OPT_BIDIR; - -`ifdef OPENSIM - // {{{ - reg [1:0] r_out; - - always @(posedge i_clk) - r_out <= i_data; - - assign w_out = (i_clk) ? r_out[1] : r_out[0]; - assign io_pin_tristate = high_z; - assign o_pin = w_out; - - assign w_in = (high_z) ? i_pin : w_out; - // }}} -`else - ODDR #( - // {{{ - .DDR_CLK_EDGE("SAME_EDGE"), - .INIT(1'b1), - .SRTYPE("SYNC") - // }}} - ) u_oddr ( - // {{{ - .CE(1'b1), .R(1'b0), .S(1'b0), - // - .C(i_clk), - .Q(w_out), .D1(i_data[1]), .D2(i_data[0]) - // }}} - ); - - assign io_pin_tristate = high_z; - assign o_pin = w_out; - assign w_in = i_pin; -`endif - - generate if (OPT_BIDIR) - begin : GEN_BIDIRECTIONAL - // {{{ -`ifdef OPENSIM - reg r_p, r_n; - reg [1:0] r_in; - - always @(posedge i_clk) - r_p <= w_in; - always @(negedge i_clk) - r_n <= w_in; - always @(posedge i_clk) - r_in <= { r_p, r_n }; - - assign o_wide = r_in; -`else - IDDR #( - .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"), - .INIT_Q1(1'b1), - .INIT_Q2(1'b1), - .SRTYPE("SYNC") - ) u_iddr ( - .Q1(o_wide[1]), .Q2(o_wide[0]), - .C(i_clk), .CE(1'b1), .D(i_pin), - .R(1'b0), .S(1'b0) - ); -`endif - // }}} - end else begin : GEN_OUTPUT - - assign o_wide = 2'b11; - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, -`ifdef VERILATOR - i_pin, -`endif - w_in }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} - end endgenerate -endmodule diff --git a/delete_later/rtl/sdspi/xsdserdes8x.v b/delete_later/rtl/sdspi/xsdserdes8x.v deleted file mode 100644 index c505041..0000000 --- a/delete_later/rtl/sdspi/xsdserdes8x.v +++ /dev/null @@ -1,143 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: xsdserdes8x.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: An 8:1 OSERDES followed by an (optional) 1:8 ISERDES. That -// simple, nothing more. This implementation is specific to -// Xilinx FPGAs. It's designed, however, so that it may be the only -// component needing replacing when switching hardware platforms. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module xsdserdes8x #( - parameter [0:0] OPT_BIDIR = 1'b1 - ) ( - // {{{ - input wire i_clk, i_hsclk, - // input wire i_reset, - // - input wire i_en, - input wire [7:0] i_data, - // - output wire io_tristate, - output wire o_pin, - input wire i_pin, - // - output wire o_raw, - output wire [7:0] o_wide - // }}} - ); - -`ifdef VERILATOR - assign io_tristate = 1'b1; - assign o_pin = 1'b1; - assign o_wide = 8'h0; - assign o_raw = i_pin; - - // Verilator lint_off UNUSED - wire unused; - assign unused = i_pin; - // Verilator lint_on UNUSED -`else - wire w_pin, w_in, w_reset, high_z, fabric_return; - assign w_reset = 1'b0; // Active high reset - - OSERDESE2 #( - // {{{ - .DATA_RATE_OQ("DDR"), - .DATA_RATE_TQ("SDR"), - .DATA_WIDTH(8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1) - // }}} - ) u_oserdes ( - // {{{ - // Verilator lint_off PINCONNECTEMPTY - .OCE(1'b1), .TCE(1'b1), .TFB(), .TQ(high_z), - .CLK(i_hsclk), .CLKDIV(i_clk), .OQ(w_pin), .OFB(fabric_return), - .D1(i_data[7]), .D2(i_data[6]), - .D3(i_data[5]), .D4(i_data[4]), - .D5(i_data[3]), .D6(i_data[2]), - .D7(i_data[1]), .D8(i_data[0]), - .RST(w_reset), .TBYTEIN(1'b0), // .TBYTEOUT(), - .T1(!i_en && OPT_BIDIR), .T2(1'b0), .T3(1'b0), .T4(1'b0) - // .SHIFTIN1(), .SHIFTIN2(), .SHIFTOUT1(), .SHIFTOUT2() - // Verilator lint_on PINCONNECTEMPTY - // }}} - ); - - // Actual buffers are held externally - assign io_tristate = high_z; - assign o_pin = w_pin; - assign w_in = i_pin; - - generate if (OPT_BIDIR) - begin : GEN_BIDIRECTIONAL - - ISERDESE2 #( - // {{{ - .SERDES_MODE("MASTER"), - .DATA_RATE("DDR"), - .DATA_WIDTH(8), - .INTERFACE_TYPE("NETWORKING"), - .NUM_CE(1), - .INIT_Q1(1'b0), .INIT_Q2(1'b0), - .INIT_Q3(1'b0), .INIT_Q4(1'b0), - .SRVAL_Q1(1'b0), .SRVAL_Q2(1'b0), - .SRVAL_Q3(1'b0), .SRVAL_Q4(1'b0), - .SYN_CLKDIV_INV_EN("FALSE"), - .DYN_CLK_INV_EN("FALSE"), - .OFB_USED("FALSE") - // }}} - ) u_iserdes ( - // {{{ - .BITSLIP(1'b0), .CE(1'b1), // .CE2(), - .CLK(i_hsclk), .CLKB(!i_hsclk), .CLKDIV(i_clk), .CLKDIVP(1'b0), - .D(w_in), .DYNCLKDIVSEL(1'b0), .DYNCLKSEL(1'b0), // .DDLY() - .OCLK(1'b0), .OCLKB(1'b0), .O(o_raw), // .OFB(), - .Q1(o_wide[0]), .Q2(o_wide[1]), - .Q3(o_wide[2]), .Q4(o_wide[3]), - .Q5(o_wide[4]), .Q6(o_wide[5]), - .Q7(o_wide[6]), .Q8(o_wide[7]), - .RST(w_reset) - // .SHIFTIN1(), .SHIFTIN2(), .SHIFTOUT1(), .SHIFTOUT2() - // }}} - ); - end else begin : GEN_OUTPUT - - assign o_wide = 8'h0; - assign o_raw = fabric_return; - - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, w_in }; - // Verilator lint_on UNUSED - end endgenerate -`endif // VERILATOR -endmodule diff --git a/delete_later/rtl/sfifo.v b/delete_later/rtl/sfifo.v deleted file mode 100644 index d1dc7ea..0000000 --- a/delete_later/rtl/sfifo.v +++ /dev/null @@ -1,484 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sfifo.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A synchronous data FIFO. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// -// Written and distributed by Gisselquist Technology, LLC -// }}} -// This design is hereby granted to the public domain. -// {{{ -// This program is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or -// FITNESS FOR A PARTICULAR PURPOSE. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module sfifo #( - // {{{ - parameter BW=8, // Byte/data width - parameter LGFLEN=4, - parameter [0:0] OPT_ASYNC_READ = 1'b1, - parameter [0:0] OPT_WRITE_ON_FULL = 1'b0, - parameter [0:0] OPT_READ_ON_EMPTY = 1'b0 - // }}} - ) ( - // {{{ - input wire i_clk, - input wire i_reset, - // - // Write interface - input wire i_wr, - input wire [(BW-1):0] i_data, - output wire o_full, - output reg [LGFLEN:0] o_fill, - // - // Read interface - input wire i_rd, - output reg [(BW-1):0] o_data, - output wire o_empty // True if FIFO is empty -`ifdef FORMAL -`ifdef F_PEEK - , output wire [LGFLEN:0] f_first_addr, - output wire [LGFLEN:0] f_second_addr, - output reg [BW-1:0] f_first_data, f_second_data, - - output reg f_first_in_fifo, - f_second_in_fifo, - output reg [LGFLEN:0] f_distance_to_first, - f_distance_to_second, - output wire [LGFLEN:0] f_wraddr, - f_rdaddr -`endif -`endif - // }}} - ); - - // Register/net declarations - // {{{ - localparam FLEN=(1<1) - begin - assert(!r_empty); - end else if ($past(!i_rd && f_fill > 0)) - assert(!r_empty); - end - - always @(*) - if (!r_empty) - begin - // This also applies for the registered read case - assert(mem[rd_addr[LGFLEN-1:0]] == o_data); - end else if (OPT_READ_ON_EMPTY) - assert(o_data == i_data); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Formal contract: (Twin write test) - // {{{ - // If you write two values in succession, you should be able to read - // those same two values in succession some time later. - // - //////////////////////////////////////////////////////////////////////// - // - // - - // Verilator lint_off UNDRIVEN - (* anyconst *) reg [LGFLEN:0] fw_first_addr; - // Verilator lint_on UNDRIVEN -`ifndef F_PEEK - wire [LGFLEN:0] f_first_addr; - wire [LGFLEN:0] f_second_addr; - reg [BW-1:0] f_first_data, f_second_data; - - reg f_first_in_fifo, f_second_in_fifo; - reg [LGFLEN:0] f_distance_to_first, f_distance_to_second; -`endif - reg f_first_addr_in_fifo, f_second_addr_in_fifo; - - assign f_first_addr = fw_first_addr; - assign f_second_addr = f_first_addr + 1; - - always @(*) - begin - f_distance_to_first = (f_first_addr - rd_addr); - f_first_addr_in_fifo = 0; - if ((f_fill != 0) && (f_distance_to_first < f_fill)) - f_first_addr_in_fifo = 1; - end - - always @(*) - begin - f_distance_to_second = (f_second_addr - rd_addr); - f_second_addr_in_fifo = 0; - if ((f_fill != 0) && (f_distance_to_second < f_fill)) - f_second_addr_in_fifo = 1; - end - - always @(posedge i_clk) - if (w_wr && wr_addr == f_first_addr) - f_first_data <= i_data; - - always @(posedge i_clk) - if (w_wr && wr_addr == f_second_addr) - f_second_data <= i_data; - - always @(*) - if (f_first_addr_in_fifo) - assert(mem[f_first_addr[LGFLEN-1:0]] == f_first_data); - always @(*) - f_first_in_fifo = (f_first_addr_in_fifo && (mem[f_first_addr[LGFLEN-1:0]] == f_first_data)); - - always @(*) - if (f_second_addr_in_fifo) - assert(mem[f_second_addr[LGFLEN-1:0]] == f_second_data); - - always @(*) - f_second_in_fifo = (f_second_addr_in_fifo && (mem[f_second_addr[LGFLEN-1:0]] == f_second_data)); - - always @(*) - if (f_first_in_fifo && (o_fill == 1 || f_distance_to_first == 0)) - assert(o_data == f_first_data); - - always @(*) - if (f_second_in_fifo && (o_fill == 1 || f_distance_to_second == 0)) - assert(o_data == f_second_data); - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset)) - begin - case({$past(f_first_in_fifo), $past(f_second_in_fifo)}) - 2'b00: begin - if ($past(w_wr && (!w_rd || !r_empty)) - &&($past(wr_addr == f_first_addr))) - begin - assert(f_first_in_fifo); - end else begin - assert(!f_first_in_fifo); - end - // - // The second could be in the FIFO, since - // one might write other data than f_first_data - // - // assert(!f_second_in_fifo); - end - 2'b01: begin - assert(!f_first_in_fifo); - if ($past(w_rd && (rd_addr==f_second_addr))) - begin - assert((o_empty&&!OPT_ASYNC_READ)||!f_second_in_fifo); - end else begin - assert(f_second_in_fifo); - end - end - 2'b10: begin - if ($past(w_wr) - &&($past(wr_addr == f_second_addr))) - begin - assert(f_second_in_fifo); - end else begin - assert(!f_second_in_fifo); - end - if ($past(!w_rd ||(rd_addr != f_first_addr))) - assert(f_first_in_fifo); - end - 2'b11: begin - assert(f_second_in_fifo); - if ($past(!w_rd ||(rd_addr != f_first_addr))) - begin - assert(f_first_in_fifo); - if (rd_addr == f_first_addr) - assert(o_data == f_first_data); - end else begin - assert(!f_first_in_fifo); - assert(o_data == f_second_data); - end - end - endcase - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // -`ifdef SFIFO - reg f_was_full; - initial f_was_full = 0; - always @(posedge i_clk) - if (o_full) - f_was_full <= 1; - - always @(posedge i_clk) - cover($fell(f_empty)); - - always @(posedge i_clk) - cover($fell(o_empty)); - - always @(posedge i_clk) - cover(f_was_full && f_empty); - - always @(posedge i_clk) - cover($past(o_full,2)&&(!$past(o_full))&&(o_full)); - - always @(posedge i_clk) - if (f_past_valid) - cover($past(o_empty,2)&&(!$past(o_empty))&& o_empty); -`endif - // }}} - - // Make Verilator happy - // Verilator lint_off UNUSED - wire unused_formal; - assign unused_formal = &{ 1'b0, f_next[LGFLEN], f_empty }; - // Verilator lint_on UNUSED -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/smi/smi.v b/delete_later/rtl/smi/smi.v deleted file mode 100644 index fb5d5ff..0000000 --- a/delete_later/rtl/smi/smi.v +++ /dev/null @@ -1,265 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: smi.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Generates a sort of serial port out of the SMI interface, for -// interfacing with the CM4. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module smi #( - parameter [0:0] OPT_ASYNC = 1'b0, - parameter LGFIFO = 8 - ) ( - // {{{ - input wire i_clk, - input wire i_reset, - // (Asynchronous) SMI interface - // {{{ - input wire i_smi_oen, i_smi_wen, - input wire [5:0] i_smi_sa, - input wire [17:0] i_smi_data, - output wire [17:0] o_smi_data, - output wire o_smi_oen, - // }}} - // AXI stream interfaces to/from FPGA - // {{{ - input wire S_TX_VALID, - output wire S_TX_READY, - input wire [7:0] S_TX_DATA, - // - output wire M_RX_VALID, - input wire M_RX_READY, - output wire [7:0] M_RX_DATA, - - output wire [31:0] o_debug - // }}} - // }}} - ); - - generate if (OPT_ASYNC) - begin : GEN_ASYNC - // {{{ - // This should work nicely for writing to the FPGA. It will - // fail on reading, however, since transitions will take place - // as soon as the positive edge of OEN takes place, whereas the - // protocol requires it hold a bit longer. - // - - // Local declarations - // {{{ - wire ifif_full, ifif_empty, ofif_full, ofif_empty; - wire [7:0] ofif_data; - reg rerr, werr; - wire ifif_err; - // }}} - - afifo #( - .LGFIFO(LGFIFO), .WIDTH(8), .WRITE_ON_POSEDGE(1'b1), - .OPT_REGISTER_READS(1'b0) - ) u_from_pi ( - // {{{ - .i_wclk(i_smi_wen), .i_wr_reset_n(!i_reset), - .i_wr(i_smi_sa == 6'h0), .i_wr_data(i_smi_data[7:0]), - .o_wr_full(ifif_full), - .i_rclk(i_clk), .i_rd_reset_n(!i_reset), - .i_rd(M_RX_VALID && M_RX_READY), - .o_rd_data(M_RX_DATA), - .o_rd_empty(ifif_empty) - // }}} - ); - - assign M_RX_VALID = !ifif_empty; - - afifo #( - .LGFIFO(LGFIFO), .WIDTH(8), .WRITE_ON_POSEDGE(1'b1), - .OPT_REGISTER_READS(1'b0) - ) u_to_pi ( - // {{{ - .i_wclk(i_clk), .i_wr_reset_n(!i_reset), - .i_wr(S_TX_VALID && S_TX_READY), - .i_wr_data(S_TX_DATA), - .o_wr_full(ofif_full), - .i_rclk(i_smi_oen), .i_rd_reset_n(!i_reset), - .i_rd(i_smi_sa == 6'h0), - .o_rd_data(ofif_data), - .o_rd_empty(ofif_empty) - // }}} - ); - - // FIFO overflow error -- cleared on any read - // {{{ - always @(posedge i_smi_wen or posedge i_reset) - if (i_reset) - werr <= 1'b0; - else if (ifif_full) - werr <= !rerr; - - always @(posedge i_smi_oen or posedge i_reset) - if (i_reset) - rerr <= 1'b0; - else - rerr <= werr; - - assign ifif_err = werr ^ rerr; - // }}} - - assign S_TX_READY = !ofif_full; - assign o_smi_data = { {(18-11){1'b0}}, ifif_err, - ifif_full, ofif_empty, - ((ofif_empty) ? 8'hff : ofif_data) }; - assign o_smi_oen = i_smi_oen; - // }}} - end else begin : GEN_SYNCHRONOUS - // {{{ - // Local declarations - // {{{ - reg last_oen, last_wen, r_active; - reg ck_oen, ck_wen; - reg [1:0] pipe_oen, pipe_wen; - - reg [11:0] pipe_addr; - reg [5:0] r_smi_sa; - - reg [15:0] pipe_data; - reg [7:0] r_smi_data, r_data; - - wire ifif_empty, ifif_full, ofif_empty, ofif_full; - wire [7:0] ofif_data; - - wire [LGFIFO:0] ign_ifif_fill, ign_ofif_fill; - reg fif_err; - // }}} - - // Clock domain transfer(s) - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - { last_oen, ck_oen, pipe_oen } <= -1; - { last_wen, ck_wen, pipe_wen } <= -1; - end else begin - { last_oen, ck_oen, pipe_oen } - <= { ck_oen, pipe_oen, i_smi_oen }; - { last_wen, ck_wen, pipe_wen } - <= { ck_wen, pipe_wen, i_smi_wen }; - end - - always @(posedge i_clk) - { r_smi_sa, pipe_addr } <= { pipe_addr, i_smi_sa }; - - always @(posedge i_clk) - { r_smi_data, pipe_data } <= { pipe_data, i_smi_data[7:0] }; - // }}} - - // r_active: Latch the address when it's not changing - // {{{ - always @(posedge i_clk) - if ((!ck_oen && !last_oen)||(!ck_wen && !last_wen)) - r_active <= (r_smi_sa == 6'h0); - // }}} - - // r_data: Latch the data when it's not changing - // {{{ - always @(posedge i_clk) - if (!ck_wen && !last_wen) - r_data <= r_smi_data; - // }}} - - sfifo #( - .BW(8), .LGFLEN(LGFIFO), .OPT_ASYNC_READ(1'b1) - ) u_from_pi ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wr(ck_wen && !last_wen && r_active), - .i_data(r_data), - .o_full(ifif_full), .o_fill(ign_ifif_fill), - .i_rd(M_RX_VALID && M_RX_READY), - .o_data(M_RX_DATA), - .o_empty(ifif_empty) - // }}} - ); - - assign M_RX_VALID = !ifif_empty; - - // - sfifo #( - .BW(8), .LGFLEN(LGFIFO), .OPT_ASYNC_READ(1'b1) - ) u_to_pi ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wr(S_TX_VALID && S_TX_READY), - .i_data(S_TX_DATA), - .o_full(ofif_full), .o_fill(ign_ofif_fill), - .i_rd(ck_oen && !last_oen && r_active), - .o_data(ofif_data), .o_empty(ofif_empty) - // }}} - ); - - assign S_TX_READY = !ofif_full; - - always @(posedge i_clk) - if (i_reset) - fif_err <= 1'b0; - else if (ck_wen && !last_wen && r_active && ifif_full) - fif_err <= 1'b1; - else if (ck_oen && !last_oen && r_active) - fif_err <= 1'b0; - - assign o_smi_data = { {(18-11){1'b0}}, - fif_err, ifif_full, ofif_empty, ofif_data }; - - assign o_smi_oen = &{ last_oen, ck_oen, pipe_oen, i_smi_oen }; - - assign o_debug = { - ((last_oen && !ck_oen)||(last_wen && !ck_wen)), - o_smi_oen, last_wen && last_oen, ck_oen, ck_wen, - fif_err, ifif_full, ofif_empty, i_smi_sa, - (o_smi_oen) ? i_smi_data : o_smi_data - }; - - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, ign_ifif_fill, ign_ofif_fill }; - // Verilator lint_on UNUSED - // }}} - // }}} - end endgenerate - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_smi_data[17:8] }; - // Verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/smi/smitest.v b/delete_later/rtl/smi/smitest.v deleted file mode 100644 index 6617317..0000000 --- a/delete_later/rtl/smi/smitest.v +++ /dev/null @@ -1,128 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: smitest.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -`default_nettype none -// }}} -module smitest ( - input wire i_clk_200mhz_p, i_clk_200mhz_n, - input wire i_wbu_uart_rx, - output wire o_wbu_uart_tx, - output wire o_wbu_uart_cts_n, - input wire i_smi_wen, i_smi_oen, - input wire [5:0] i_smi_sa, - inout wire [17:0] io_smi_sd - ); - - localparam real CLOCK_FREQUENCY_MHZ = 200.0, - BAUD_RATE_KHZ = 19.200; - localparam CLOCKS_PER_BAUD = $rtoi(CLOCK_FREQUENCY_MHZ * 1000.0 - / BAUD_RATE_KHZ), - TIMING_BITS = $clog2(CLOCKS_PER_BAUD+1); - - wire ck_prebuf, s_clk; - wire rx_valid, rx_ready, tx_valid, tx_ready, tx_busy; - wire [7:0] rx_data, tx_data; - wire [17:0] o_smi_data; - wire o_smi_oen; - reg s_reset; - reg [1:0] reset_pipe; - - IBUFDS - clk_ibuf ( - .I(i_clk_200mhz_p), .IB(i_clk_200mhz_n), - .O(ck_prebuf) - ); - - BUFG clk_bfg ( .I(ck_prebuf), .O(s_clk) ); - - initial { s_reset, reset_pipe } = -1; - always @(posedge s_clk) - { s_reset, reset_pipe } <= { reset_pipe, 1'b0 }; - - txuartlite #( - .TIMING_BITS(TIMING_BITS[4:0]), - .CLOCKS_PER_BAUD(CLOCKS_PER_BAUD[TIMING_BITS-1:0]) - ) u_txuart ( - .i_clk(s_clk), .i_wr(tx_valid && !tx_busy), - .i_data(tx_data), - .o_uart_tx(o_wbu_uart_tx), .o_busy(tx_busy) - ); - - assign tx_ready = !tx_busy; - - rxuartlite #( - .TIMER_BITS(TIMING_BITS[4:0]), - .CLOCKS_PER_BAUD(CLOCKS_PER_BAUD[TIMING_BITS-1:0]) - ) u_rxuart ( - .i_clk(s_clk), .i_uart_rx(i_wbu_uart_rx), - .o_wr(rx_valid), .o_data(rx_data) - ); - - assign o_wbu_uart_cts_n = o_smi_data[8]; - - smi #( - .OPT_ASYNC(1'b0) - ) u_smi ( - .i_clk(s_clk), .i_reset(s_reset), - .i_smi_oen(i_smi_oen), .i_smi_wen(i_smi_wen), - .i_smi_sa(i_smi_sa), - .i_smi_data(io_smi_sd), .o_smi_data(o_smi_data), - .o_smi_oen(o_smi_oen), - .S_TX_VALID(rx_valid), .S_TX_READY(rx_ready), - .S_TX_DATA(rx_data), - .M_RX_VALID(tx_valid), .M_RX_READY(tx_ready), - .M_RX_DATA(tx_data) - ); - - assign io_smi_sd = (o_smi_oen) ? 18'hz : o_smi_data; - - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, rx_ready }; - // Verilator lint_on UNUSED -endmodule - -`ifdef VERILATOR -// {{{ -// Verilator lint_off DECLFILENAME -module IBUFDS ( input wire I, input wire IB, output wire O ); - assign O = I; - // Verilator lint_off UNUSED - wire unused = IB; - // Verilator lint_on UNUSED -endmodule - -module BUFG ( input wire I, output wire O ); - assign O = I; -endmodule -// Verilator lint_on DECLFILENAME -// }}} -`endif // VERILATOR diff --git a/delete_later/rtl/spio.v b/delete_later/rtl/spio.v deleted file mode 100644 index b5d7f20..0000000 --- a/delete_later/rtl/spio.v +++ /dev/null @@ -1,239 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: spio.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module spio #( - // {{{ - parameter NLEDS=8, NBTN=8, NSW=8, NFF=2 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output wire [31:0] o_wb_data, - // - input wire [(NSW-1):0] i_sw, - input wire [(NBTN-1):0] i_btn, - output reg [(NLEDS-1):0] o_led, - output reg o_int - // }}} - ); - - // Local declarations - // {{{ - reg led_demo; - reg [(8-1):0] r_led; - wire [(8-1):0] w_btn; - wire [(NLEDS-1):0] bounced; - wire [(8-1):0] r_sw; - reg sw_int; - wire btn_int; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // LED handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // r_led - // {{{ - initial r_led = 0; - always @(posedge i_clk) - if (i_reset) - r_led <= 0; - else if (i_wb_stb && i_wb_we && i_wb_sel[0]) - begin - if (!i_wb_sel[1]) - r_led[NLEDS-1:0] <= i_wb_data[(NLEDS-1):0]; - else - r_led[NLEDS-1:0] <= (r_led[NLEDS-1:0]&(~i_wb_data[(8+NLEDS-1):8])) - |(i_wb_data[(NLEDS-1):0]&i_wb_data[(8+NLEDS-1):8]); - end - // }}} - - initial led_demo = 1'b1; - always @(posedge i_clk) - if (i_reset) - led_demo <= 1'b1; - else if (i_wb_stb && i_wb_we && i_wb_sel[3]) - led_demo <= i_wb_data[24]; - - ledbouncer #(NLEDS, 25) - knightrider(i_clk, bounced); - - always @(posedge i_clk) - if (led_demo) - o_led <= bounced; - else - o_led <= r_led[NLEDS-1:0]; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Buttons - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Let's make buttons sticky: once any button is pressed, the bit - // will get set and then stay high until acknowledged. - - generate if (NBTN > 0) - begin : GEN_BUTTON - // {{{ - reg [NBTN-1:0] next_btn, s_btn, r_btn; - (* ASYNC_REG *) reg [NFF*NBTN-1:0] btn_pipe; - reg r_btn_int, next_int; - - always @(posedge i_clk) - if (i_reset) - { s_btn, btn_pipe } <= 0; - else - { s_btn, btn_pipe } <= { btn_pipe, i_btn }; - - // r_btn rises on i_btn, and falls on a write - - // next_btn - // {{{ - always @(*) - begin - next_btn = r_btn; - - if (i_wb_stb && i_wb_we && i_wb_sel[2]) - next_btn = next_btn & (~i_wb_data[16 +: NBTN]); - - next_btn = next_btn | s_btn; - next_int = |next_btn; - end - // }}} - - // r_btn - // {{{ - always @(posedge i_clk) - if (i_reset) - r_btn <= 0; - else - r_btn <= next_btn; - // }}} - - always @(posedge i_clk) - if (i_reset) - r_btn_int <= 1'b0; - else - r_btn_int <= next_int; - - assign btn_int = r_btn_int; - assign w_btn[NBTN-1:0] = r_btn; - // }}} - end else begin : NO_BUTTONS - - assign btn_int = 1'b0; - - end endgenerate - - generate if (NBTN < 8) - begin : GEN_UNUSED_BUTTONS - assign w_btn[7:NBTN] = 0; - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Switches - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // 2FF synchronizer for our switches - generate if (NSW > 0) - begin : GEN_SWITCHES - (* ASYNC_REG *) reg [NFF*NSW-1:0] sw_pipe; - reg [NSW-1:0] rr_sw; - - initial rr_sw = 0; - initial sw_pipe = 0; - always @(posedge i_clk) - begin - rr_sw <= 0; - { rr_sw[NSW-1:0], sw_pipe } <= { sw_pipe, i_sw }; - - sw_int <= (rr_sw != sw_pipe[(NFF-1)*NSW-1 +: NSW]); - end - - assign r_sw = { {(8-NSW){1'b0}}, rr_sw }; - - end else begin : NO_SWITCHES - - assign r_sw = 0; - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign o_wb_data = { 7'h0, led_demo, w_btn, r_sw, r_led }; - - always @(posedge i_clk) - if (i_reset) - o_int <= 0; - else - o_int <= sw_int || btn_int; - - assign o_wb_stall = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_ack <= 1'b0; - else - o_wb_ack <= (i_wb_stb); - // }}} - - // Make Verilator happy - // {{{ - // verilator lint_on UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_wb_data, i_wb_sel[2] }; - // verilator lint_off UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/toplevel.v b/delete_later/rtl/toplevel.v deleted file mode 100644 index ae2fd3c..0000000 --- a/delete_later/rtl/toplevel.v +++ /dev/null @@ -1,622 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: ./toplevel.v -// {{{ -// Project: 10Gb Ethernet switch -// -// DO NOT EDIT THIS FILE! -// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT. -// DO NOT EDIT THIS FILE! -// -// CmdLine: autofpga autofpga -I .: -d -o . allclocks.txt global.txt wbdown.txt icape.txt version.txt gpio.txt spio.txt wbuconsole.txt zipmaster.txt bkram.txt ddr3.txt sdio.txt emmc.txt sdioscope.txt emmcscope.txt mem_bkram_only.txt mem_flash_bkram.txt i2ccpu.txt fan.txt sirefclk.txt i2cscope.txt -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// }}} -`default_nettype none - - -// -// Here we declare our toplevel.v (toplevel) design module. -// All design logic must take place beneath this top level. -// -// The port declarations just copy data from the @TOP.PORTLIST -// key, or equivalently from the @MAIN.PORTLIST key if -// @TOP.PORTLIST is absent. For those peripherals that don't need -// any top level logic, the @MAIN.PORTLIST should be sufficent, -// so the @TOP.PORTLIST key may be left undefined. -// -// The only exception is that any clocks with CLOCK.TOP tags will -// also appear in this list -// -module toplevel( - // DDR3 I/O port wires - o_ddr3_reset_n, o_ddr3_cke, o_ddr3_clk_p, o_ddr3_clk_n, - o_ddr3_s_n, o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n, - o_ddr3_ba, o_ddr3_a, - o_ddr3_odt, o_ddr3_dm, - io_ddr3_dqs_p, io_ddr3_dqs_n, io_ddr3_dq, - o_siref_clk_p, o_siref_clk_n, - io_temp_sda, io_temp_scl, - o_fan_pwm, o_fan_sys, i_fan_tach, - // eMMC Card - // o_emmc_clk, - io_emmc_cmd, io_emmc_dat, i_emmc_ds, - io_i2c_sda, io_i2c_scl, - o_i2c_mxrst_n, - // SDIO SD Card - o_sdcard_clk, io_sdcard_cmd, io_sdcard_dat, i_sdcard_cd_n, - i_clk_200mhz_p, i_clk_200mhz_n, - // UART/host to wishbone interface - i_wbu_uart_rx, o_wbu_uart_tx, - o_wbu_uart_cts_n, - // GPIO ports - i_pi_reset_n, i_soft_reset, i_hdmitx_hpd_n, - o_tp, o_si5324_rst, i_si5324_int, - o_hdmirx_hpd_n, - // SPIO interface - i_sw, i_nbtn_u, i_nbtn_l, i_nbtn_c, i_nbtn_r, i_nbtn_d, o_led); - // - // Declaring any top level parameters. - // - // These declarations just copy data from the @TOP.PARAM key, - // or from the @MAIN.PARAM key if @TOP.PARAM is absent. For - // those peripherals that don't do anything at the top level, - // the @MAIN.PARAM key should be sufficient, so the @TOP.PARAM - // key may be left undefined. - // - localparam real DDR3_CONTROLLERCONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module - DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device - localparam DDR3_CONTROLLERROW_BITS = 14, // width of row address - DDR3_CONTROLLERCOL_BITS = 10, // width of column address - DDR3_CONTROLLERBA_BITS = 3, // width of bank address - DDR3_CONTROLLERDQ_BITS = 8, // Size of one octet - DDR3_CONTROLLERLANES = 8, //8 lanes of DQ - DDR3_CONTROLLERAUX_WIDTH = 1, - DDR3_CONTROLLERSERDES_RATIO = $rtoi(DDR3_CONTROLLERCONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD), - //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits - DDR3_CONTROLLERCMD_LEN = 4 + 3 + DDR3_CONTROLLERBA_BITS + DDR3_CONTROLLERROW_BITS; - - - //////////////////////////////////////////////////////////////////////// - // - // Variables/definitions/parameters used by the ZipCPU bus master - // {{{ - // - // A 32-bit address indicating where the ZipCPU should start running - // from -`ifdef BKROM_ACCESS - localparam RESET_ADDRESS = @$(/bkrom.BASE); -`else -`ifdef FLASH_ACCESS - localparam RESET_ADDRESS = @$RESET_ADDRESS; -`else - localparam RESET_ADDRESS = 67108864; -`endif // FLASH_ACCESS -`endif // BKROM_ACCESS - // - // The number of valid bits on the bus - localparam ZIP_ADDRESS_WIDTH = 22; // Zip-CPU address width - // - // Number of ZipCPU interrupts - localparam ZIP_INTS = 16; - // - // ZIP_START_HALTED - // - // A boolean, indicating whether or not the ZipCPU be halted on startup? -`ifdef BKROM_ACCESS - localparam ZIP_START_HALTED=1'b0; -`else - localparam ZIP_START_HALTED=1'b1; -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // WBUBUS parameters - // {{{ - // Baudrate : 1000000 - // Clock : 100000000 - localparam [23:0] BUSUART = 24'h64; // 1000000 baud - localparam DBGBUSBITS = $clog2(BUSUART); - // - // Maximum command is 6 bytes, where each byte takes 10 baud clocks - // and each baud clock requires DBGBUSBITS to represent. Here, - // we'll add one more for good measure. - localparam DBGBUSWATCHDOG_RAW = DBGBUSBITS + 9; - localparam DBGBUSWATCHDOG = (DBGBUSWATCHDOG_RAW > 19) - ? DBGBUSWATCHDOG_RAW : 19; - // }}} - localparam ICAPE_LGDIV=3; - // - // Declaring our input and output ports. We listed these above, - // now we are declaring them here. - // - // These declarations just copy data from the @TOP.IODECLS key, - // or from the @MAIN.IODECL key if @TOP.IODECL is absent. For - // those peripherals that don't do anything at the top level, - // the @MAIN.IODECL key should be sufficient, so the @TOP.IODECL - // key may be left undefined. - // - // We start with any @CLOCK.TOP keys - // - // I/O declarations for the DDR3 SDRAM - // {{{ - output wire o_ddr3_reset_n; - output wire [1:0] o_ddr3_cke; - output wire [0:0] o_ddr3_clk_p, o_ddr3_clk_n; - output wire [1:0] o_ddr3_s_n; // o_ddr3_s_n[1] is set to 0 since controller only support single rank - output wire [0:0] o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n; - output wire [DDR3_CONTROLLERBA_BITS-1:0] o_ddr3_ba; - output wire [15:0] o_ddr3_a; //set to max of 16 bits, but only ROW_BITS bits are relevant - output wire [1:0] o_ddr3_odt; - output wire [DDR3_CONTROLLERLANES-1:0] o_ddr3_dm; - inout wire [(DDR3_CONTROLLERDQ_BITS*DDR3_CONTROLLERLANES)/8-1:0] io_ddr3_dqs_p, io_ddr3_dqs_n; - inout wire [(DDR3_CONTROLLERDQ_BITS*DDR3_CONTROLLERLANES)-1:0] io_ddr3_dq; - // }}} - - - output wire o_siref_clk_p, o_siref_clk_n; - inout wire io_temp_sda, io_temp_scl; - output wire o_fan_pwm, o_fan_sys; - input wire i_fan_tach; - // eMMC Card - // {{{ - // output wire o_emmc_clk; - inout wire io_emmc_cmd; - inout wire [8-1:0] io_emmc_dat; - input wire i_emmc_ds; - // }}} - inout wire io_i2c_sda, io_i2c_scl; - output wire o_i2c_mxrst_n; - // SDIO SD Card - // {{{ - output wire o_sdcard_clk; - inout wire io_sdcard_cmd; - inout wire [4-1:0] io_sdcard_dat; - input wire i_sdcard_cd_n; - // }}} - input wire i_clk_200mhz_p, i_clk_200mhz_n; - input wire i_wbu_uart_rx; - output wire o_wbu_uart_tx; - // input wire i_wbu_uart_rts_n; // FT*'s perspective - output wire o_wbu_uart_cts_n; - // GPIO wires - input wire i_pi_reset_n, i_soft_reset, i_hdmitx_hpd_n; - output wire [3:0] o_tp; - output wire o_si5324_rst, o_hdmirx_hpd_n; - input wire i_si5324_int; - // SPIO interface - input wire [8-1:0] i_sw; - input wire i_nbtn_c, i_nbtn_d, i_nbtn_l, i_nbtn_r, i_nbtn_u; - output wire [8-1:0] o_led; - - - // - // Declaring component data, internal wires and registers - // - // These declarations just copy data from the @TOP.DEFNS key - // within the component data files. - // - // Wires connected to PHY interface of DDR3 controller - // {{{ - genvar ddr3_controllergen_index; - - wire [DDR3_CONTROLLERDQ_BITS*DDR3_CONTROLLERLANES*8-1:0] ddr3_controller_iserdes_data; - wire [DDR3_CONTROLLERLANES*8-1:0] ddr3_controller_iserdes_dqs; - wire [DDR3_CONTROLLERLANES*8-1:0] ddr3_controller_iserdes_bitslip_reference; - wire ddr3_controller_idelayctrl_rdy; - wire [DDR3_CONTROLLERCMD_LEN*DDR3_CONTROLLERSERDES_RATIO-1:0] ddr3_controller_cmd; - wire ddr3_controller_dqs_tri_control, ddr3_controller_dq_tri_control; - wire ddr3_controller_toggle_dqs; - wire [512-1:0] ddr3_controller_data; - wire [512/8-1:0] ddr3_controller_dm; - wire [4:0] ddr3_controller_odelay_data_cntvaluein, ddr3_controller_odelay_dqs_cntvaluein; - wire [4:0] ddr3_controller_idelay_data_cntvaluein, ddr3_controller_idelay_dqs_cntvaluein; - wire [DDR3_CONTROLLERLANES-1:0] ddr3_controller_odelay_data_ld, ddr3_controller_odelay_dqs_ld; - wire [DDR3_CONTROLLERLANES-1:0] ddr3_controller_idelay_data_ld, ddr3_controller_idelay_dqs_ld; - wire [DDR3_CONTROLLERLANES-1:0] ddr3_controller_bitslip; - // }}} - // Definitions for the clock generation circuit - wire s_sirefclk_clk, w_sirefclk_pll_locked, - w_sirefclk_ce; - wire s_clk4x; // s_clk4x_unbuffered, - // s_clksync, s_clksync_unbuffered; - wire [7:0] w_sirefclk_word; - // FAN definitions - // {{{ - wire i_fan_sda, i_fan_scl, - o_fan_sda, o_fan_scl; - // }}} - // eMMC Card definitions - // {{{ - wire i_emmc_cd_n; - wire o_emmc_clk; - // }}} - // I2CCPU definitions - // {{{ - wire i_i2c_sda, i_i2c_scl, - o_i2c_sda, o_i2c_scl; - reg r_i2c_mxrst_n; - reg [2:0] r_i2c_mxrst_dly; - // }}} - // SDIO SD Card definitions - // {{{ - wire i_sdcard_ds; - // }}} - // Verilator lint_off UNUSED - wire ign_cpu_stall, ign_cpu_ack; - wire [31:0] ign_cpu_idata; - // Verilator lint_on UNUSED - wire s_clk200; - wire s_clk, s_reset, sysclk_locked, s_clk_nobuf, - clk_feedback, clk_feedback_bufd, - s_lcl_pixclk_nobuf, s_clk4x_unbuffered, s_clk300; - reg [2:0] pipe_reset; - reg [6:0] refdly_reset_ctr; - wire refdly_ready; - // GPIO declarations. The two wire busses are just virtual lists of - // input (or output) ports. - wire [16-1:0] i_gpio; - wire [8-1:0] o_gpio; - wire [8-1:0] w_led; - wire [5-1:0] w_btn; - - - // - // Time to call the main module within main.v. Remember, the purpose - // of the main.v module is to contain all of our portable logic. - // Things that are Xilinx (or even Altera) specific, or for that - // matter anything that requires something other than on-off logic, - // such as the high impedence states required by many wires, is - // kept in this (toplevel.v) module. Everything else goes in - // main.v. - // - // We automatically place s_clk, and s_reset here. You may need - // to define those above. (You did, didn't you?) Other - // component descriptions come from the keys @TOP.MAIN (if it - // exists), or @MAIN.PORTLIST if it does not. - // - - main thedesign(s_clk, s_reset, - // DDR3 Controller-PHY Interface - ddr3_controller_iserdes_data, ddr3_controller_iserdes_dqs, - ddr3_controller_iserdes_bitslip_reference, - ddr3_controller_idelayctrl_rdy, - ddr3_controller_cmd, - ddr3_controller_dqs_tri_control, ddr3_controller_dq_tri_control, - ddr3_controller_toggle_dqs, ddr3_controller_data, ddr3_controller_dm, - ddr3_controller_odelay_data_cntvaluein, ddr3_controller_odelay_dqs_cntvaluein, - ddr3_controller_idelay_data_cntvaluein, ddr3_controller_idelay_dqs_cntvaluein, - ddr3_controller_odelay_data_ld, ddr3_controller_odelay_dqs_ld, - ddr3_controller_idelay_data_ld, ddr3_controller_idelay_dqs_ld, - ddr3_controller_bitslip, - // Clock Generator ports - w_sirefclk_word, w_sirefclk_ce, - // FAN/fan - i_fan_sda, i_fan_scl, - o_fan_sda, o_fan_scl, - o_fan_pwm, o_fan_sys, i_fan_tach, - // eMMC Card - o_emmc_clk, i_emmc_ds, - io_emmc_cmd, io_emmc_dat, - !i_emmc_cd_n, - // I2CCPU - i_i2c_sda, i_i2c_scl, - o_i2c_sda, o_i2c_scl, - // SDIO SD Card - o_sdcard_clk, i_sdcard_ds, - io_sdcard_cmd, io_sdcard_dat, - !i_sdcard_cd_n, - // Reset wire for the ZipCPU - 1'b0, 1'b0, 1'b0, 7'h0, 32'h0, - ign_cpu_stall, ign_cpu_ack, ign_cpu_idata, s_reset, - s_clk200, - // UART/host to wishbone interface - i_wbu_uart_rx, o_wbu_uart_tx, - o_wbu_uart_cts_n, - // GPIO wires - i_gpio, o_gpio, - i_sw, w_btn, w_led); - - - // - // Our final section to the toplevel is used to provide all of - // that special logic that couldnt fit in main. This logic is - // given by the @TOP.INSERT tag in our data files. - // - - - // DDR3 PHY Instantiation - ddr3_phy #( - .ROW_BITS(DDR3_CONTROLLERROW_BITS), //width of row address - .BA_BITS(DDR3_CONTROLLERBA_BITS), //width of bank address - .DQ_BITS(DDR3_CONTROLLERDQ_BITS), //width of DQ - .LANES(DDR3_CONTROLLERLANES), //8 lanes of DQ - .CONTROLLER_CLK_PERIOD(DDR3_CONTROLLERCONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module - .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD) //ns, period of clock input to DDR3 RAM device - ) ddr3_phy_inst ( - // clock and reset - .i_controller_clk(s_clk), - .i_ddr3_clk(s_clk4x), - .i_ref_clk(s_clk200), - .i_rst_n(!s_reset), - // Controller Interface - .i_controller_cmd(ddr3_controller_cmd), - .i_controller_dqs_tri_control(ddr3_controller_dqs_tri_control), - .i_controller_dq_tri_control(ddr3_controller_dq_tri_control), - .i_controller_toggle_dqs(ddr3_controller_toggle_dqs), - .i_controller_data(ddr3_controller_data), - .i_controller_dm(ddr3_controller_dm), - .i_controller_odelay_data_cntvaluein(ddr3_controller_odelay_data_cntvaluein), - .i_controller_odelay_dqs_cntvaluein(ddr3_controller_odelay_dqs_cntvaluein), - .i_controller_idelay_data_cntvaluein(ddr3_controller_idelay_data_cntvaluein), - .i_controller_idelay_dqs_cntvaluein(ddr3_controller_idelay_dqs_cntvaluein), - .i_controller_odelay_data_ld(ddr3_controller_odelay_data_ld), - .i_controller_odelay_dqs_ld(ddr3_controller_odelay_dqs_ld), - .i_controller_idelay_data_ld(ddr3_controller_idelay_data_ld), - .i_controller_idelay_dqs_ld(ddr3_controller_idelay_dqs_ld), - .i_controller_bitslip(ddr3_controller_bitslip), - .o_controller_iserdes_data(ddr3_controller_iserdes_data), - .o_controller_iserdes_dqs(ddr3_controller_iserdes_dqs), - .o_controller_iserdes_bitslip_reference(ddr3_controller_iserdes_bitslip_reference), - .o_controller_idelayctrl_rdy(ddr3_controller_idelayctrl_rdy), - // DDR3 I/O Interface - .o_ddr3_clk_p(o_ddr3_clk_p), - .o_ddr3_clk_n(o_ddr3_clk_n), - .o_ddr3_reset_n(o_ddr3_reset_n), - .o_ddr3_cke(o_ddr3_cke[0]), // CKE - .o_ddr3_cs_n(o_ddr3_s_n[0]), // chip select signal (controls rank 1 only) - .o_ddr3_ras_n(o_ddr3_ras_n), // RAS# - .o_ddr3_cas_n(o_ddr3_cas_n), // CAS# - .o_ddr3_we_n(o_ddr3_we_n), // WE# - .o_ddr3_addr(o_ddr3_a[DDR3_CONTROLLERROW_BITS-1:0]), - .o_ddr3_ba_addr(o_ddr3_ba), - .io_ddr3_dq(io_ddr3_dq), - .io_ddr3_dqs(io_ddr3_dqs_p), - .io_ddr3_dqs_n(io_ddr3_dqs_n), - .o_ddr3_dm(o_ddr3_dm), - .o_ddr3_odt(o_ddr3_odt[0]) // on-die termination - ); - - assign o_ddr3_s_n[1] = 1; // set to 1 (disabled) since controller only supports single rank - assign o_ddr3_cke[1] = 0; // set to 0 (disabled) since controller only supports single rank - assign o_ddr3_odt[1] = 0; // set to 0 (disabled) since controller only supports single rank - generate for(ddr3_controllergen_index = DDR3_CONTROLLERROW_BITS; - ddr3_controllergen_index < 16; - ddr3_controllergen_index = ddr3_controllergen_index + 1) - begin : GEN_UNUSED_DDR3_CONTROLLER_ASSIGN - assign o_ddr3_a[ddr3_controllergen_index] = 0; - end endgenerate - - - //////////////////////////////////////////////////////////////////////// - // - // Clock generator for the Si5324 - // {{{ -/* - PLLE2_BASE #( - // {{{ - .CLKFBOUT_MULT(8), - .CLKFBOUT_PHASE(0.0), - .CLKIN1_PERIOD(10), - .CLKOUT0_DIVIDE(4), - .CLKOUT1_DIVIDE(2) - // }}} - ) gen_sysclk( - // {{{ - .CLKIN1(i_clk), - .CLKOUT0(s_clk_200mhz_unbuffered), - .CLKOUT1(s_clk4x_unbuffered), - .PWRDWN(1'b0), .RST(1'b0), - .CLKFBOUT(sysclk_feedback), - .CLKFBIN(sysclk_feedback), - .LOCKED(sysclk_locked) - // }}} - ); -*/ - // BUFG clksync_buf(.I(s_clksync_unbuffered), .O(s_clk)); - BUFG clk4x_buf(.I(s_clk4x_unbuffered), .O(s_clk4x)); - - xgenclk - u_xsirefclk( - // {{{ - .i_clk(s_clk), .i_hsclk(s_clk4x), - .i_ce(w_sirefclk_ce), - .i_word(w_sirefclk_word), - .o_pin({ o_siref_clk_p, o_siref_clk_n }), - .o_clk(s_sirefclk_clk) - // }}} - ); - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // FAN IO buffers - // {{{ - - // We need these in order to (properly) ensure the high impedance - // states (pull ups) of the I2C I/O lines. Our goals are: - // - // o_fan_X io_fan_X Derived:T - // 1'b0 1'b0 1'b0 - // 1'b1 1'bz 1'b1 - // - IOBUF fansclp( - // {{{ - .I(1'b0), - .T(o_fan_scl), - .O(i_fan_scl), - .IO(io_temp_scl) - // }}} - ); - - IOBUF fansdap( - // {{{ - .I(1'b0), - .T(o_fan_sda), - .O(i_fan_sda), - .IO(io_temp_sda) - // }}} - ); - // }}} - - assign i_emmc_cd_n = 1'b0; - - //////////////////////////////////////////////////////////////////////// - // - // I2C IO buffers - // {{{ - - // We need these in order to (properly) ensure the high impedance - // states (pull ups) of the I2C I/O lines. Our goals are: - // - // o_i2c_X io_i2c_X Derived:T - // 1'b0 1'b0 1'b0 - // 1'b1 1'bz 1'b1 - // - IOBUF i2csclp( - // {{{ - .I(1'b0), - .T(o_i2c_scl), - .O(i_i2c_scl), - .IO(io_i2c_scl) - // }}} - ); - - IOBUF i2csdap( - // {{{ - .I(1'b0), - .T(o_i2c_sda), - .O(i_i2c_sda), - .IO(io_i2c_sda) - // }}} - ); - - initial { r_i2c_mxrst_n, r_i2c_mxrst_dly } = 0; - always @(posedge s_clk or negedge sysclk_locked) - if (!sysclk_locked) - { r_i2c_mxrst_n, r_i2c_mxrst_dly } <= 0; - else - { r_i2c_mxrst_n, r_i2c_mxrst_dly } <= { r_i2c_mxrst_dly, 1'b1 }; - - assign o_i2c_mxrst_n = r_i2c_mxrst_n; - // }}} - - assign i_sdcard_ds = 1'b0; - - //////////////////////////////////////////////////////////////////////// - // - // 200MHz clock ingestion - // {{{ - IBUFDS - ibuf_ck200 ( - .I(i_clk_200mhz_p), .IB(i_clk_200mhz_n), - .O(s_clk200) - ); - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // Default clock setup - // {{{ - // assign s_clk=s_clk200; - // assign sysclk_locked = 1'b1; - - initial pipe_reset = -1; - always @(posedge s_clk or negedge sysclk_locked) - if (!sysclk_locked) - pipe_reset <= -1; - else - pipe_reset <= { pipe_reset[1:0], 1'b0 }; - - assign s_reset = pipe_reset[2]; - - PLLE2_BASE #( - .CLKFBOUT_MULT(6), // 200MHz*6 => 1200MHz - .CLKFBOUT_PHASE(0.0), - .CLKIN1_PERIOD(5), - .CLKOUT0_DIVIDE(12), // Divide by 2x - .CLKOUT1_DIVIDE(3), // Multiply by 2x - .CLKOUT2_DIVIDE(30), // Divide by 5x - .CLKOUT3_DIVIDE(4) // Multiply by 3/2 - ) u_syspll ( - .CLKOUT0(s_clk_nobuf), // 100MHz - .CLKOUT1(s_clk4x_unbuffered), // 400MHz - .CLKOUT2(s_lcl_pixclk_nobuf), // 40MHz - .CLKOUT3(s_clk300), // 300MHz - // - .CLKFBOUT(clk_feedback), - .LOCKED(sysclk_locked), - .CLKIN1(s_clk200), // 200MHz - .PWRDWN(1'b0), - .CLKFBIN(clk_feedback_bufd) - ); - - BUFG feedback_buffer(.I(clk_feedback), .O(clk_feedback_bufd)); - BUFG sysclk_buffer(.I(s_clk_nobuf), .O(s_clk)); - // BUFG sysclk_buffer(.I(s_lcl_pixclk_nobuf), .O(s_lcl_pixclk)); - - // IDELAYCTRL - // {{{ - // Min reset width of 52ns, or 9 clocks at 150MHz - always @(posedge s_clk300 or negedge sysclk_locked) - if (!sysclk_locked) - refdly_reset_ctr <= 0; - else if (!refdly_reset_ctr[5]) - refdly_reset_ctr <= refdly_reset_ctr + 1; - - IDELAYCTRL - u_dlyctrl (.REFCLK(s_clk300), .RST(refdly_reset_ctr[5]), - .RDY(refdly_ready)); - // }}} - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // GPIO adjustments - // {{{ - // Set to '1' when there's something to say. Hence, the reset - // inputs will be '1' when the reset is active, the HDMI detect - // will be '1' when an HDMI is detected, the PLL lock signals - // will be '1' when not locked, etc. - assign i_gpio = { 11'h0, - 1'b0, // Was pxrx_locked - !i_hdmitx_hpd_n, - i_si5324_int,!sysclk_locked,!i_pi_reset_n,i_soft_reset }; - assign o_tp = o_gpio[3:0]; - assign o_si5324_rst = o_gpio[4]; - assign o_hdmirx_hpd_n = o_gpio[5]; - // o_trace = o_gpio[6]; // But this is for simulation only, so ignore - // o_error = o_gpio[7]; // SIM ONLY: Internal error detection - // }}} - - assign o_led = { w_led[8-1:2], (w_led[1] || !sysclk_locked), - w_led[0] | s_reset }; - - assign w_btn = ~{ i_nbtn_u, i_nbtn_l, i_nbtn_c, i_nbtn_r, i_nbtn_d }; - - - -endmodule // end of toplevel.v module definition diff --git a/delete_later/rtl/wb2axip/addrdecode.v b/delete_later/rtl/wb2axip/addrdecode.v deleted file mode 100644 index 83d436f..0000000 --- a/delete_later/rtl/wb2axip/addrdecode.v +++ /dev/null @@ -1,431 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sim/rtl/addrdecode.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module addrdecode #( - // {{{ - parameter NS=8, - parameter AW = 32, DW=32+32/8+1+1, - // - // SLAVE_ADDR contains address assignments for each of the - // various slaves we are adjudicating between. - parameter [NS*AW-1:0] SLAVE_ADDR = { - { 3'b111, {(AW-3){1'b0}} }, - { 3'b110, {(AW-3){1'b0}} }, - { 3'b101, {(AW-3){1'b0}} }, - { 3'b100, {(AW-3){1'b0}} }, - { 3'b011, {(AW-3){1'b0}} }, - { 3'b010, {(AW-3){1'b0}} }, - { 4'b0010, {(AW-4){1'b0}} }, - { 4'b0000, {(AW-4){1'b0}} }}, - // - // SLAVE_MASK contains a mask of those address bits in - // SLAVE_ADDR which are relevant. It shall be true that if - // !SLAVE_MASK[k] then !SLAVE_ADDR[k], for any bits of k - parameter [NS*AW-1:0] SLAVE_MASK = (NS <= 1) ? 0 - : { {(NS-2){ 3'b111, {(AW-3){1'b0}} }}, - {(2){ 4'b1111, {(AW-4){1'b0}} }} }, - // - // ACCESS_ALLOWED is a bit-wise mask indicating which slaves - // may get access to the bus. If ACCESS_ALLOWED[slave] is true, - // then a master can connect to the slave via this method. This - // parameter is primarily here to support AXI (or other similar - // buses) which may have separate accesses for both read and - // write. By using this, a read-only slave can be connected, - // which would also naturally create an error on any attempt to - // write to it. - parameter [NS-1:0] ACCESS_ALLOWED = -1, - // - // If OPT_REGISTERED is set, address decoding will take an extra - // clock, and will register the results of the decoding - // operation. - parameter [0:0] OPT_REGISTERED = 0, - // - // If OPT_LOWPOWER is set, then whenever the output is not - // valid, any respective data linse will also be forced to zero - // in an effort to minimize power. - parameter [0:0] OPT_LOWPOWER = 0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire i_valid, - output reg o_stall, - input wire [AW-1:0] i_addr, - input wire [DW-1:0] i_data, - // - output reg o_valid, - input wire i_stall, - output reg [NS:0] o_decode, - output reg [AW-1:0] o_addr, - output reg [DW-1:0] o_data - // }}} - ); - - // Local declarations - // {{{ - // - // OPT_NONESEL controls whether or not the address lines are fully - // proscribed, or whether or not a "no-slave identified" slave should - // be created. To avoid a "no-slave selected" output, slave zero must - // have no mask bits set (and therefore no address bits set), and it - // must also allow access. - localparam [0:0] OPT_NONESEL = (!ACCESS_ALLOWED[0]) - || (SLAVE_MASK[AW-1:0] != 0); - // - wire [NS:0] request; - reg [NS-1:0] prerequest; - integer iM; - // }}} - - // prerequest - // {{{ - always @(*) - for(iM=0; iM 1 && |prerequest[NS-1:1])) - r_request[0] = 1'b0; - end - - assign request[NS-1:0] = r_request; - // }}} - end else if (NS == 1) - begin : SINGLE_SLAVE - // {{{ - assign request[0] = i_valid; - // }}} - end else begin : LCL_NOSEL - // {{{ - reg [NS-1:0] r_request; - - always @(*) - begin - for(iM=0; iM 1 && |prerequest[NS-1:1])) - r_request[0] = 1'b0; - end - - assign request[NS-1:0] = r_request; - // }}} - end endgenerate - // }}} - - // request[NS] - // {{{ - generate if (OPT_NONESEL) - begin : OPT_NONESEL_REQUEST - reg r_request_NS, r_none_sel; - - always @(*) - begin - // Let's assume nothing's been selected, and then check - // to prove ourselves wrong. - // - // Note that none_sel will be considered an error - // condition in the follow-on processing. Therefore - // it's important to clear it if no request is pending. - r_none_sel = i_valid && (prerequest == 0); - // - // request[NS] indicates a request for a non-existent - // slave. A request that should (eventually) return a - // bus error - // - r_request_NS = r_none_sel; - end - - assign request[NS] = r_request_NS; - end else begin : NO_NONESEL_REQUEST - assign request[NS] = 1'b0; - end endgenerate - // }}} - - // o_valid, o_addr, o_data, o_decode, o_stall - // {{{ - generate if (OPT_REGISTERED) - begin : GEN_REGISTERED_OUTS - - // o_valid - // {{{ - initial o_valid = 0; - always @(posedge i_clk) - if (i_reset) - o_valid <= 0; - else if (!o_stall) - o_valid <= i_valid; - // }}} - - // o_addr, o_data - // {{{ - initial o_addr = 0; - initial o_data = 0; - always @(posedge i_clk) - if (i_reset && OPT_LOWPOWER) - begin - o_addr <= 0; - o_data <= 0; - end else if ((!o_valid || !i_stall) - && (i_valid || !OPT_LOWPOWER)) - begin - o_addr <= i_addr; - o_data <= i_data; - end else if (OPT_LOWPOWER && !i_stall) - begin - o_addr <= 0; - o_data <= 0; - end - // }}} - - // o_decode - // {{{ - initial o_decode = 0; - always @(posedge i_clk) - if (i_reset) - o_decode <= 0; - else if ((!o_valid || !i_stall) - && (i_valid || !OPT_LOWPOWER)) - o_decode <= request; - else if (OPT_LOWPOWER && !i_stall) - o_decode <= 0; - // }}} - - // o_stall - // {{{ - always @(*) - o_stall = (o_valid && i_stall); - // }}} - end else begin : COMB_OUTPUTS - - always @(*) - begin - o_valid = i_valid; - o_stall = i_stall; - o_addr = i_addr; - o_data = i_data; - - o_decode = request; - end - - // Make Verilator happy - // {{{ - // verilator coverage_off - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, -`ifdef VERILATOR - // Can't declare the clock as unused for formal, - // lest it not be recognized as *the* clock - i_clk, -`endif - i_reset }; - // verilator lint_on UNUSED - // verilator coverage_on - // }}} - end endgenerate - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - reg [AW+DW-1:0] f_idata; - always @(*) - f_idata = { i_addr, i_data }; - -`ifdef ADDRDECODE - always @(posedge i_clk) - if (!f_past_valid) - assume(i_reset); -`else - always @(posedge i_clk) - if (!f_past_valid) - assert(i_reset); - -`endif // ADDRDECODE - always @(posedge i_clk) - if (OPT_REGISTERED && (!f_past_valid || $past(i_reset))) - begin - assert(!o_valid); - assert(o_decode == 0); - end else if ($past(o_valid && i_stall) && OPT_REGISTERED) - begin - assert($stable(o_addr)); - assert($stable(o_decode)); - assert($stable(o_data)); - end - - // If the output is ever valid, there must be at least one - // decoded output - always @(*) - assert(o_valid == (o_decode != 0)); - - always @(*) - for(iM=0; iM !i_valid; - endproperty - - property IDATA_HELD_WHEN_NOT_READY; - @(posedge i_clk) disable iff (i_reset) - i_valid && !o_ready |=> i_valid && $stable(i_data); - endproperty - -`ifdef SKIDBUFFER - assume property (IDATA_HELD_WHEN_NOT_READY); -`else - assert property (IDATA_HELD_WHEN_NOT_READY); -`endif -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Outgoing stream properties / assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - generate if (!OPT_PASSTHROUGH) - begin - - always @(posedge i_clk) - if (!f_past_valid) // || $past(i_reset)) - begin - // Following any reset, valid must be deasserted - assert(!o_valid || !OPT_INITIAL); - end else if ($past(o_valid && !i_ready && !i_reset) && !i_reset) - // Following any stall, valid must remain high and - // data must be preserved - assert(o_valid && $stable(o_data)); - - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Other properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - generate if (!OPT_PASSTHROUGH) - begin - // Rule #1: - // If registered, then following any reset we should be - // ready for a new request - // {{{ - always @(posedge i_clk) - if (f_past_valid && $past(OPT_OUTREG && i_reset)) - assert(o_ready); - // }}} - - // Rule #2: - // All incoming data must either go directly to the - // output port, or into the skid buffer - // {{{ -`ifndef VERIFIC - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && $past(i_valid && o_ready - && (!OPT_OUTREG || o_valid) && !i_ready)) - assert(!o_ready && w_data == $past(i_data)); -`else - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_valid && o_ready - && (!OPT_OUTREG || o_valid) && !i_ready) - |=> (!o_ready && w_data == $past(i_data))); -`endif - // }}} - - // Rule #3: - // After the last transaction, o_valid should become idle - // {{{ - if (!OPT_OUTREG) - begin - // {{{ - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && !i_reset - && $past(i_ready)) - begin - assert(o_valid == i_valid); - assert(!i_valid || (o_data == i_data)); - end - // }}} - end else begin - // {{{ - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset)) - begin - if ($past(i_valid && o_ready)) - assert(o_valid); - - if ($past(!i_valid && o_ready && i_ready)) - assert(!o_valid); - end - // }}} - end - // }}} - - // Rule #4 - // Same thing, but this time for o_ready - // {{{ - always @(posedge i_clk) - if (f_past_valid && $past(!o_ready && i_ready)) - assert(o_ready); - // }}} - - // If OPT_LOWPOWER is set, o_data and w_data both need to be - // zero any time !o_valid or !r_valid respectively - // {{{ - if (OPT_LOWPOWER) - begin - always @(*) - if ((OPT_OUTREG || !i_reset) && !o_valid) - assert(o_data == 0); - - always @(*) - if (o_ready) - assert(w_data == 0); - - end - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // -`ifdef SKIDBUFFER - generate if (!OPT_PASSTHROUGH) - begin - reg f_changed_data; - - initial f_changed_data = 0; - always @(posedge i_clk) - if (i_reset) - f_changed_data <= 1; - else if (i_valid && $past(!i_valid || o_ready)) - begin - if (i_data != $past(i_data + 1)) - f_changed_data <= 0; - end else if (!i_valid && i_data != 0) - f_changed_data <= 0; - - -`ifndef VERIFIC - reg [3:0] cvr_steps, cvr_hold; - - always @(posedge i_clk) - if (i_reset) - begin - cvr_steps <= 0; - cvr_hold <= 0; - end else begin - cvr_steps <= cvr_steps + 1; - cvr_hold <= cvr_hold + 1; - case(cvr_steps) - 0: if (o_valid || i_valid) - cvr_steps <= 0; - 1: if (!i_valid || !i_ready) - cvr_steps <= 0; - 2: if (!i_valid || !i_ready) - cvr_steps <= 0; - 3: if (!i_valid || !i_ready) - cvr_steps <= 0; - 4: if (!i_valid || i_ready) - cvr_steps <= 0; - 5: if (!i_valid || !i_ready) - cvr_steps <= 0; - 6: if (!i_valid || !i_ready) - cvr_steps <= 0; - 7: if (!i_valid || i_ready) - cvr_steps <= 0; - 8: if (!i_valid || i_ready) - cvr_steps <= 0; - 9: if (!i_valid || !i_ready) - cvr_steps <= 0; - 10: if (!i_valid || !i_ready) - cvr_steps <= 0; - 11: if (!i_valid || !i_ready) - cvr_steps <= 0; - 12: begin - cvr_steps <= cvr_steps; - cover(!o_valid && !i_valid && f_changed_data); - if (!o_valid || !i_ready) - cvr_steps <= 0; - else - cvr_hold <= cvr_hold + 1; - end - default: assert(0); - endcase - end - -`else - // Cover test - cover property (@(posedge i_clk) - disable iff (i_reset) - (!o_valid && !i_valid) - ##1 i_valid && i_ready [*3] - ##1 i_valid && !i_ready - ##1 i_valid && i_ready [*2] - ##1 i_valid && !i_ready [*2] - ##1 i_valid && i_ready [*3] - // Wait for the design to clear - ##1 o_valid && i_ready [*0:5] - ##1 (!o_valid && !i_valid && f_changed_data)); -`endif - end endgenerate -`endif // SKIDBUFFER - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wb2axip/wbdown.v b/delete_later/rtl/wb2axip/wbdown.v deleted file mode 100644 index b2818a9..0000000 --- a/delete_later/rtl/wb2axip/wbdown.v +++ /dev/null @@ -1,1150 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbdown.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Downconvert a Wishbone bus from a wider width to a smaller one. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbdown #( - // {{{ - parameter ADDRESS_WIDTH = 28, // Byte address width - parameter WIDE_DW = 64, - parameter SMALL_DW = 32, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter [0:0] OPT_LOWPOWER = 1'b0, - parameter [0:0] OPT_LOWLOGIC = 1'b0, - localparam WIDE_AW = ADDRESS_WIDTH-$clog2(WIDE_DW/8), - localparam SMALL_AW = ADDRESS_WIDTH-$clog2(SMALL_DW/8) - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Incoming wide port - // {{{ - input wire i_wcyc, i_wstb, i_wwe, - input wire [WIDE_AW-1:0] i_waddr, - input wire [WIDE_DW-1:0] i_wdata, - input wire [WIDE_DW/8-1:0] i_wsel, - output wire o_wstall, - output wire o_wack, - output wire [WIDE_DW-1:0] o_wdata, - output wire o_werr, - // }}} - // Outgoing, small bus size, port - // {{{ - output wire o_scyc, o_sstb, o_swe, - output wire [SMALL_AW-1:0] o_saddr, - output wire [SMALL_DW-1:0] o_sdata, - output wire [SMALL_DW/8-1:0] o_ssel, - input wire i_sstall, - input wire i_sack, - input wire [SMALL_DW-1:0] i_sdata, - input wire i_serr - // }}} - // }}} - ); - - // Verilator lint_off UNUSED - localparam WBLSB = $clog2(WIDE_DW/SMALL_DW); - // Verilator lint_on UNUSED - generate if (WIDE_DW == SMALL_DW) - begin : NO_ADJUSTMENT - // {{{ - assign o_scyc = i_wcyc; - assign o_sstb = i_wstb; - assign o_swe = i_wwe; - assign o_saddr = i_waddr; - assign o_sdata = i_wdata; - assign o_ssel = i_wsel; - - assign o_wstall = i_sstall; - assign o_wack = i_sack; - assign o_wdata = i_sdata; - assign o_werr = i_serr; - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_clk, i_reset }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} - // }}} - end else if (OPT_LOWLOGIC) - begin : CHEAP_DOWNSIZER - // {{{ - // Local declarations - // {{{ - localparam LGFIFO = 5; - reg r_cyc, r_stb, r_we, r_ack, r_err; - reg [SMALL_AW-1:0] r_addr; - reg [WIDE_DW-1:0] s_data, r_data; - reg [WIDE_DW/8-1:0] s_sel; - reg [WBLSB:0] s_count; - wire fifo_full, ign_fifo_empty, fifo_ack; - wire [LGFIFO:0] ign_fifo_fill; -`ifdef FORMAL - wire [LGFIFO:0] f_first_addr, f_second_addr; - wire f_first_data, f_second_data; - wire f_first_in_fifo, f_second_in_fifo; - wire [LGFIFO:0] f_distance_to_first, - f_distance_to_second; -`endif - // }}} - - // r_cyc - // {{{ - initial r_cyc = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wcyc ||(o_scyc && i_serr) || o_werr) - r_cyc <= 1'b0; - else if (i_wcyc && i_wstb) - r_cyc <= 1'b1; - // }}} - - initial r_stb = 1'b0; - initial r_we = 1'b0; - initial r_addr = 0; - initial s_data = 0; - initial s_sel = 0; - initial s_count = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || o_werr || (o_scyc && i_serr)) - begin - // {{{ - r_stb <= 1'b0; - r_we <= 1'b0; - r_addr <= 0; - s_data <= 0; - s_sel <= 0; - s_count <= 0; - // }}} - end else if (i_wstb && !o_wstall) // New request - begin - // {{{ - r_stb <= 1'b1; - r_we <= i_wwe; - r_addr <= { i_waddr, - {($clog2(WIDE_DW/SMALL_DW)){1'b0}} }; - s_data <= i_wdata; - s_sel <= i_wsel; - // Verilator lint_off WIDTH - s_count <= (WIDE_DW/SMALL_DW); - // Verilator lint_on WIDTH - // }}} - end else if (o_sstb && !i_sstall) - begin - // {{{ - s_count <= s_count - 1; - r_stb <= (s_count > 1); - r_addr[$clog2(WIDE_DW/SMALL_DW)-1:0] - <= r_addr[$clog2(WIDE_DW/SMALL_DW)-1:0] + 1; - if (OPT_LITTLE_ENDIAN) - begin - // Verilator coverage_off - s_data <= s_data >> SMALL_DW; - s_sel <= s_sel >> (SMALL_DW/8); - // Verilator coverage_on - end else begin - s_data <= s_data << SMALL_DW; - s_sel <= s_sel << (SMALL_DW/8); - end - // }}} - end - - assign o_scyc = r_cyc; - assign o_sstb = r_stb && !fifo_full; - assign o_swe = r_we; - assign o_saddr= r_addr; - - if (OPT_LITTLE_ENDIAN) - begin : OPT_LILEND_DATA - // Verilator coverage_off - assign o_sdata = s_data[SMALL_DW-1:0]; - assign o_ssel = s_sel[SMALL_DW/8-1:0]; - // Verilator coverage_on - end else begin : OPT_BIGEND_DATA - assign o_sdata=s_data[WIDE_DW-1:WIDE_DW-SMALL_DW]; - assign o_ssel =s_sel[WIDE_DW/8-1:(WIDE_DW-SMALL_DW)/8]; - end - - sfifo #( - .BW(1), .LGFLEN(LGFIFO), - .OPT_WRITE_ON_FULL(1'b1), .OPT_READ_ON_EMPTY(1'b1) - ) u_fifo ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || !i_wcyc), - .i_wr(o_sstb && !i_sstall), - .i_data({ (s_count == 1) ? 1'b1 : 1'b0 }), - .o_full(fifo_full), .o_fill(ign_fifo_fill), - .i_rd(i_sack), .o_data(fifo_ack), - .o_empty(ign_fifo_empty) -`ifdef FORMAL - , .f_first_addr(f_first_addr), - .f_second_addr(f_second_addr), - .f_first_data(f_first_data), - .f_second_data(f_second_data), - .f_first_in_fifo(f_first_in_fifo), - .f_second_in_fifo(f_second_in_fifo), - .f_distance_to_first(f_distance_to_first), - .f_distance_to_second(f_distance_to_second) -`endif - // }}} - ); - - // r_data - // {{{ - initial r_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (!i_wcyc || !o_scyc || i_serr)) - r_data <= 0; - else if (i_sack) - begin - if (OPT_LITTLE_ENDIAN) - r_data<= { i_sdata, r_data[WIDE_DW-1:SMALL_DW] }; - else - r_data<={r_data[WIDE_DW-SMALL_DW-1:0], i_sdata }; - end - // }}} - - // r_ack - // {{{ - initial r_ack = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || !o_scyc) - r_ack <= 1'b0; - else - r_ack <= i_sack && fifo_ack; - // }}} - - // r_err - // {{{ - initial r_err = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || !o_scyc) - r_err <= 1'b0; - else - r_err <= i_serr; - // }}} - - assign o_wdata = r_data; - assign o_wack = r_ack; - assign o_werr = r_err; - assign o_wstall = (r_stb && (fifo_full || i_sstall)) - || (s_count > 1); - - // Keep Verilator happy - // {{{ - // Verilator coverage_off - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, ign_fifo_fill, ign_fifo_empty }; - // Verilator lint_on UNUSED - // Verilator coverage_on - // }}} - //////////////////////////////////////////////////////////////// - //////////////////////////////////////////////////////////////// - //////////////////////////////////////////////////////////////// - // - // Formal properties - // {{{ - //////////////////////////////////////////////////////////////// - //////////////////////////////////////////////////////////////// - //////////////////////////////////////////////////////////////// -`ifdef FORMAL - parameter F_LGDEPTH = LGFIFO+1; - reg f_past_valid; - wire [F_LGDEPTH-1:0] fslv_nreqs, fslv_nacks,fslv_outstanding; - wire [F_LGDEPTH-1:0] fmst_nreqs, fmst_nacks,fmst_outstanding; - wire f_first_ack, f_second_ack; - reg [LGFIFO:0] f_acks_in_fifo; - reg [WBLSB-1:0] f_first_subaddr, f_second_subaddr, - f_this_subaddr; - reg [WIDE_DW/8-1:0] f_mask; - reg f_subsequent; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - fwb_slave #( - .AW(WIDE_AW), .DW(WIDE_DW), - ) fslv ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_wb_cyc(i_wcyc), .i_wb_stb(i_wstb), .i_wb_we(i_wwe), - .i_wb_addr(i_waddr), .i_wb_data(i_wdata), - .i_wb_sel(i_wsel), - .i_wb_stall(o_wstall), .i_wb_ack(o_wack), - .i_wb_idata(o_wdata), .i_wb_err(o_werr), - // - .f_nreqs(fslv_nreqs), .f_nacks(fslv_nacks), - .f_outstanding(fslv_outstanding) - // }}} - ); - - fwb_master #( - .AW(SMALL_AW), .DW(SMALL_DW), - ) fmst ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_wb_cyc(o_scyc), .i_wb_stb(o_sstb), .i_wb_we(o_swe), - .i_wb_addr(o_saddr), .i_wb_data(o_sdata), - .i_wb_sel(o_ssel), - .i_wb_stall(i_sstall), .i_wb_ack(i_sack), - .i_wb_idata(i_sdata), .i_wb_err(i_serr), - // - .f_nreqs(fmst_nreqs), .f_nacks(fmst_nacks), - .f_outstanding(fmst_outstanding) - // }}} - ); - - always @(*) - if (r_stb) - begin - assert(s_count > 0); - end else begin - assert(s_count == 0); - end - - always @(*) - if (!i_reset && o_scyc && i_wcyc) - assert(ign_fifo_fill == fmst_outstanding); - - always @(*) - if (!i_reset && !o_scyc && i_wcyc && !o_werr) - assert(ign_fifo_fill == 0); - - always @(*) - if (!o_scyc) - assert(!r_stb); - - always @(*) - if ((r_stb || fslv_outstanding > 0) && i_wcyc && o_scyc) - assert(o_swe == i_wwe); - - always @(*) - if (i_wcyc && fslv_outstanding > 0 && !o_werr) - assert(o_scyc); - - initial f_acks_in_fifo = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc) - f_acks_in_fifo <= 0; - else case({ o_sstb && !i_sstall && (s_count == 1), - (i_sack && fifo_ack) }) - 2'b01: f_acks_in_fifo <= f_acks_in_fifo - 1; - 2'b10: f_acks_in_fifo <= f_acks_in_fifo + 1; - endcase - - always @(*) - if (!i_reset && i_wcyc && o_scyc) - begin - assert(f_acks_in_fifo + (s_count > 0 ? 1:0) - + (o_wack ? 1:0) == fslv_outstanding); - - if (s_count == 0 && fslv_outstanding > (o_wack ? 1:0)) - assert(f_acks_in_fifo > 0); - end - - assign f_first_ack = f_first_data; - assign f_second_ack = f_second_data; - - always @(*) - begin - // f_first_subaddr = f_first_data[WBLSB-1:0]; - // f_second_subaddr = f_second_data[WBLSB-1:0]; - - f_first_subaddr = (r_stb ? o_saddr[WBLSB-1:0] : {(WBLSB){1'b0}}) - - ign_fifo_fill[WBLSB-1:0] - + f_distance_to_first[WBLSB-1:0]; - - f_second_subaddr = (r_stb ? o_saddr[WBLSB-1:0] : {(WBLSB){1'b0}}) - - ign_fifo_fill[WBLSB-1:0] - + f_distance_to_second[WBLSB-1:0]; - - f_this_subaddr = (r_stb ? o_saddr[WBLSB-1:0] : {(WBLSB){1'b0}}) - - ign_fifo_fill[WBLSB-1:0]; - end - - always @(*) - begin - if (!i_reset && o_scyc && i_wcyc && f_first_in_fifo) - begin - assert(f_first_ack == (&f_first_subaddr[WBLSB-1:0])); - end - if (!i_reset && o_scyc && i_wcyc && f_second_in_fifo) - begin - assert(f_second_ack == (&f_second_subaddr[WBLSB-1:0])); - end - assert(f_acks_in_fifo <= ign_fifo_fill); - assert(!ign_fifo_empty || f_acks_in_fifo == 0); - assert(f_acks_in_fifo >= - ((f_first_in_fifo && f_first_ack) ? 1:0) - + ((f_second_in_fifo && f_second_ack) ? 1:0)); - assert(ign_fifo_fill - f_acks_in_fifo >= - ((f_first_in_fifo && !f_first_ack) ? 1:0) - + ((f_second_in_fifo && !f_second_ack) ? 1:0)); - - if (o_scyc && f_first_in_fifo && f_distance_to_first == ign_fifo_fill - 1) - assert(f_first_ack || s_count > 0); - if (o_scyc && f_second_in_fifo && f_distance_to_second == ign_fifo_fill - 1) - assert(f_second_ack || s_count > 0); - if (!i_reset && i_wcyc && o_scyc - && ign_fifo_fill > 0 && s_count == 0) - assert(f_acks_in_fifo > 0); - - if (o_scyc&& i_wcyc && f_first_in_fifo && s_count == 0 && !o_werr - && f_distance_to_first + 1 < ign_fifo_fill) - assert(f_acks_in_fifo > (f_first_ack ? 1:0)); - - if (o_scyc && i_wcyc && f_second_in_fifo && s_count == 0 && !o_werr - && f_distance_to_second + 1 < ign_fifo_fill) - assert(f_acks_in_fifo > - ((f_first_in_fifo && f_first_ack) ? 1:0) - + (f_second_ack ? 1:0)); - end - - always @(*) - begin - if (f_second_in_fifo) - f_subsequent = (f_distance_to_second + 1 < ign_fifo_fill); - else if (f_first_in_fifo) - f_subsequent = (f_distance_to_first + 1 < ign_fifo_fill); - else - f_subsequent = (f_acks_in_fifo > 0 && s_count == 0); - end - - always @(*) - if ((!f_first_in_fifo || f_distance_to_first > 0) - &&(!f_second_in_fifo || f_distance_to_second > 0) - && !ign_fifo_empty) - begin - assume(!fifo_ack || (f_acks_in_fifo > - ((f_subsequent) ? 1:0) - + ((f_first_in_fifo && f_first_ack) ? 1:0) - + ((f_second_in_fifo && f_second_ack) ? 1:0))); - assume(fifo_ack || (ign_fifo_fill - f_acks_in_fifo > - ((f_first_in_fifo && !f_first_ack) ? 1:0) - + ((f_second_in_fifo && !f_second_ack) ? 1:0))); - if (f_acks_in_fifo == 1 && s_count == 0 && ign_fifo_fill > 1) - assume(!fifo_ack); - - assume(fifo_ack == (&f_this_subaddr)); - end - - always @(*) - if (!i_reset && o_scyc && i_wcyc) - begin - if (f_first_in_fifo && f_second_in_fifo) - begin - assert(f_second_subaddr > f_first_subaddr - || f_first_ack); - end else if (f_first_in_fifo && !f_first_ack) - begin - assert(s_count > 0 - && o_saddr[WBLSB-1:0] > f_first_subaddr); - end - end - - always @(*) - if (!i_reset && o_scyc && i_wcyc) - begin - assert(s_count <= (1< f_first_subaddr - || f_first_ack); - end - - always @(*) - if (OPT_LITTLE_ENDIAN) - // Verilator coverage_off - f_mask = {(WIDE_DW/8){1'b1}} >> (o_saddr[WBLSB-1:0] * SMALL_DW/8); - // Verilator coverage_on - else - f_mask = {(WIDE_DW/8){1'b1}} << (o_saddr[WBLSB-1:0] * SMALL_DW/8); - - always @(*) - if (s_count > 0) - begin - assert((s_sel & (~f_mask)) == 0); - end -`endif - // }}} - // }}} - end else begin : DOWNSIZE - // {{{ - // Notes: - // {{{ - // A "full" and "proper" downsizer would only issue requests - // for memory requested in o_wb_sel. It would skip the first - // address (or two) if necessary to do so, and stop early - // if necessary--as soon as the full access had been completed. - // Only one clock cycle would be spent (assuming !i_sstall) - // for each request. - // 1st clock cycle: - // o_sstb <= (i_wsel != 0) - // o_saddr[WBLSB-1:0] matches first i_wsel!=0 - // o_sdata, o_ssel, also matches first i_wsel != 0 - // nth clock cycle: - // Drops o_sstb once all remaining ssel == 0 - // s_count == 0 (already, was 1 on cycle prior) - // - // However ... this full and "proper" downsizer isn't meeting - // timing. So ... let's make some adjustments here for timing. - // Our new goals: - // 1st clock cycle: - // Activates o_sstb if (and only if) either - // i_wstb[SMALL-1:0] != 0 or - // i_wstb[] == 0 (an empty request) - // Sets o_saddr[WBLSB-1:0] = 0 - // Sets o_sdata = i_wdata[SMALL-1:0] - // Sets o_ssel = i_wsel[SMALL/8-1:0] - // - // 2nd clock cycle: - // Activates o_sstb (if i_wsel[WIDE-1:SMALL] != 0) - // Sets o_saddr, o_sdata, and o_ssel appropriately - // so that it matches the first active - // word of the transfer. - // nth clock cyle: - // Drops o_sstb once remaining wsel == 0. - // - // }}} - - // Local declarations - // {{{ - localparam LGFIFO = 5; - - reg r_cyc, r_stb, r_we, r_ack, r_err, - r_first; - reg [SMALL_AW-1:0] r_addr; - reg s_null, s_last; - reg [WIDE_DW-1:0] s_data, r_data, nxt_data; - reg [WIDE_DW/8-1:0] s_sel, nxt_sel; - reg [WBLSB-1:0] r_shift; - wire [WBLSB-1:0] fifo_addr, i_subaddr; - wire fifo_full, fifo_empty, fifo_ack; - wire [LGFIFO:0] ign_fifo_fill; -`ifdef FORMAL - wire [LGFIFO:0] f_first_addr, f_second_addr; - wire [WBLSB:0] f_first_data, f_second_data; - wire f_first_in_fifo, f_second_in_fifo; - wire [LGFIFO:0] f_distance_to_first, - f_distance_to_second; -`endif - // }}} - - // r_cyc - // {{{ - initial r_cyc = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wcyc ||(o_scyc && i_serr) || o_werr) - r_cyc <= 1'b0; - else if (i_wcyc && i_wstb) - r_cyc <= 1'b1; - // }}} - - // i_subaddr - assign i_subaddr = subaddr_fn(i_wsel); - - initial r_stb = 1'b0; - initial r_we = 1'b0; - initial r_first = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || o_werr || (o_scyc && i_serr)) - begin - // {{{ - r_stb <= 1'b0; - r_we <= 1'b0; - r_first <= 1'b0; - // }}} - end else if (i_wstb && !o_wstall) // New request - begin - // {{{ - r_we <= i_wwe; - if (OPT_LITTLE_ENDIAN) - begin - r_stb <=(i_wsel[SMALL_DW/8-1:0] != 0); - r_first<=(i_wsel[WIDE_DW/8-1:SMALL_DW/8] != 0); - end else begin - r_stb<=(i_wsel[WIDE_DW/8-1:WIDE_DW/8-SMALL_DW/8]!= 0); - r_first<=(i_wsel[WIDE_DW/8-SMALL_DW/8-1:0] != 0); - end - - // Assuming i_subaddr == 0 - // }}} - end else if ((r_first && !o_sstb) || (o_sstb && !i_sstall)) - begin - // {{{ - r_first <= 1'b0; - if (OPT_LITTLE_ENDIAN) - begin - // Verilator coverage_off - r_stb <= (s_sel[WIDE_DW/8-1:SMALL_DW/8] != 0); - // Verilator coverage_on - end else begin - r_stb <= (s_sel[WIDE_DW/8-SMALL_DW/8-1:0]!=0); - end - // }}} - end - - // s_null - // {{{ - initial s_null = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || o_werr || (o_scyc && i_serr)) - s_null <= 0; - else if (!o_wstall) // New request - s_null <= i_wstb && (i_wsel == 0); - else if (!r_first && (!o_sstb || !i_sstall) && s_last - && fifo_empty) - s_null <= 0; - // }}} - - // s_last - // {{{ - initial s_last = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || o_werr || (o_scyc && i_serr)) - begin - s_last <= 1'b1; - end else if (!o_wstall) - begin - // {{{ - if (OPT_LITTLE_ENDIAN) - begin - s_last<=(i_wsel[WIDE_DW/8-1:SMALL_DW/8]==0); - end else begin - s_last<=(i_wsel[WIDE_DW/8-SMALL_DW/8-1:0]==0); - end - - if (!i_wstb) - s_last <= 1'b1; - // }}} - end else if (!o_sstb || !i_sstall) - begin - // {{{ - if (OPT_LITTLE_ENDIAN) - begin - // Verilator coverage_off - s_last<=(nxt_sel[WIDE_DW/8-1:SMALL_DW/8]==0); - // Verilator coverage_on - end else begin - s_last<=(nxt_sel[WIDE_DW/8-SMALL_DW/8-1:0]==0); - end - // }}} - end - // }}} - - // r_addr - // {{{ - initial r_addr = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (i_reset || !i_wcyc || o_werr - || (o_scyc && i_serr))) - r_addr <= 0; - else if (!o_wstall) - begin - // Treat the subaddress as zero--even if it isn't - r_addr <= { i_waddr, {(WBLSB){1'b0}} }; - if (OPT_LOWPOWER && !i_wstb) - r_addr <= 0; - end else if ((!r_stb && r_first) || (r_stb && !i_sstall)) - r_addr[WBLSB-1:0] <= r_addr[WBLSB-1:0] + r_shift; - // }}} - - // r_shift, s_data, s_sel - // {{{ - if (OPT_LITTLE_ENDIAN) - begin : DNSHIFT_NXTSEL - always @(*) - nxt_sel = s_sel >> (r_shift * SMALL_DW/8); - end else begin : UPSHIFT_NXTSEL - always @(*) - nxt_sel = s_sel << (r_shift * SMALL_DW/8); - end - - initial s_data = 0; - initial s_sel = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (i_reset || !i_wcyc || o_werr - || (o_scyc && i_serr))) - begin - r_shift <= 0; - s_data <= 0; - s_sel <= 0; - end else if (!o_wstall) - begin - // {{{ - if (OPT_LITTLE_ENDIAN) - begin - r_shift<= (i_wsel[SMALL_DW/8-1:0] != 0) ? 1 - : i_subaddr; - end else begin - r_shift<= (i_wsel[WIDE_DW/8-1:WIDE_DW/8-SMALL_DW]!= 0) - ? 1 : i_subaddr; - end - - s_data <= i_wdata; - s_sel <= (i_wstb) ? i_wsel : {(WIDE_DW/8){1'b0}}; - - if (OPT_LOWPOWER && !i_wstb) - { r_shift, s_data } <= 0; - // }}} - end else if (!o_sstb || !i_sstall) // && !s_last - begin - // {{{ - r_shift <= 1; - if (OPT_LITTLE_ENDIAN) - begin - // Verilator coverage_off - s_data <= s_data >> (r_shift * SMALL_DW); - // Verilator coverage_on - end else begin - s_data <= s_data << (r_shift * SMALL_DW); - end - s_sel <= nxt_sel; - // }}} - end - // }}} - - assign o_scyc = r_cyc; - assign o_sstb = r_stb && !fifo_full; - assign o_swe = r_we; - assign o_saddr= r_addr; - - if (OPT_LITTLE_ENDIAN) - begin : OPT_LILODATA - assign o_sdata = s_data[SMALL_DW-1:0]; - assign o_ssel = s_sel[SMALL_DW/8-1:0]; - end else begin : OPT_BIGODATA - assign o_sdata =s_data[WIDE_DW-1:WIDE_DW-SMALL_DW]; - assign o_ssel =s_sel[WIDE_DW/8-1:(WIDE_DW-SMALL_DW)/8]; - end - - sfifo #( - .BW(1+WBLSB), .LGFLEN(LGFIFO), - .OPT_WRITE_ON_FULL(1'b1), .OPT_READ_ON_EMPTY(1'b1) - ) u_fifo ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || !i_wcyc), - .i_wr(o_sstb && !i_sstall), - .i_data({ {(s_last) ? 1'b1 : 1'b0 }, - o_saddr[WBLSB-1:0] }), - .o_full(fifo_full), .o_fill(ign_fifo_fill), - .i_rd(i_sack), - .o_data({ fifo_ack, fifo_addr }), - .o_empty(fifo_empty) -`ifdef FORMAL - , .f_first_addr(f_first_addr), - .f_second_addr(f_second_addr), - .f_first_data(f_first_data), - .f_second_data(f_second_data), - .f_first_in_fifo(f_first_in_fifo), - .f_second_in_fifo(f_second_in_fifo), - .f_distance_to_first(f_distance_to_first), - .f_distance_to_second(f_distance_to_second) -`endif - // }}} - ); - - // nxt_data, r_data - // {{{ - always @(*) - begin - nxt_data = r_data; - if (o_wack) - nxt_data = 0; - if (i_sack) - begin - if (OPT_LITTLE_ENDIAN) - begin - // Verilator coverage_off - nxt_data = nxt_data - | ({ {(WIDE_DW-SMALL_DW){1'b0}}, i_sdata } << (fifo_addr * SMALL_DW)); - // Verilator coverage_on - end else begin - nxt_data = nxt_data - | ({ i_sdata, {(WIDE_DW-SMALL_DW){1'b0}} } >> (fifo_addr * SMALL_DW)); - end - end - end - - initial r_data = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || !o_scyc || i_serr) - r_data <= 0; - else - r_data <= nxt_data; - // }}} - - // r_ack - // {{{ - initial r_ack = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || !o_scyc) - r_ack <= 1'b0; - else if (!fifo_empty) - r_ack <= fifo_ack && i_sack; - else - r_ack <= s_null; - // }}} - - // r_err - // {{{ - initial r_err = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc || !o_scyc) - r_err <= 0; - else - r_err <= i_serr; - // }}} - - assign o_wdata = r_data; - assign o_wack = r_ack; - assign o_werr = r_err; - assign o_wstall= r_first || (r_stb && (fifo_full || i_sstall)) - || (s_null && !fifo_empty) - || (!s_last); - - function [WBLSB-1:0] subaddr_fn(input [WIDE_DW/8-1:0] sel); - // {{{ - integer fnk, fm; - begin - subaddr_fn = 0; - for(fnk=0; fnk 0); - assert(o_ssel != 0); - if (r_first) - assert(o_saddr[WBLSB-1:0] == 0); - end else if (r_first) - begin - assert(o_saddr[WBLSB-1:0] == 0); - if (OPT_LITTLE_ENDIAN) - begin - assert(s_sel[SMALL_DW/8-1:0] == 0); - // assert(s_count == 0); - end else begin - assert(s_sel[WIDE_DW/8-1:SMALL_DW/8] == 0); - end - end else begin - assert(s_sel == 0); - assert(s_count == 0); - end - - always @(posedge i_clk) - if (i_wstb && !o_wstall) - begin - f_we <= i_wwe; - f_addr <= i_waddr; - f_data <= i_wdata; - f_sel <= i_wsel; - end - - always @(*) - assert(!r_stb || !s_null); - - always @(*) - if (r_stb) - begin - assert(o_ssel != 0); - - if (OPT_LITTLE_ENDIAN) - begin - assert((s_count == 1) == (s_sel[WIDE_DW/8-1:SMALL_DW/8] == 0)); - end else begin - assert((s_count == 1) == (s_sel[WIDE_DW/8-SMALL_DW/8-1:0] == 0)); - end - end - - always @(*) - if (!i_reset && o_scyc && i_wcyc) - assert(ign_fifo_fill == fmst_outstanding); - - always @(*) - if (!i_reset && !o_scyc && i_wcyc && !o_werr) - assert(ign_fifo_fill == 0); - - always @(*) - if (!o_scyc) - assert(!r_stb); - - always @(*) - if ((r_stb || fslv_outstanding > 0) && i_wcyc && o_scyc) - assert(o_swe == i_wwe); - - always @(*) - if (i_wcyc && fslv_outstanding > 0 && !o_werr) - assert(o_scyc); - - always @(*) - if (i_wcyc && !o_wack && fmst_outstanding == 0 && s_count == 0) - assert(r_data == 0); - - initial f_acks_in_fifo = 0; - always @(posedge i_clk) - if (i_reset || !i_wcyc) - f_acks_in_fifo <= 0; - else case({ o_sstb && !i_sstall && (s_count == 1), - (i_sack && fifo_ack) }) - 2'b01: f_acks_in_fifo <= f_acks_in_fifo - 1; - 2'b10: f_acks_in_fifo <= f_acks_in_fifo + 1; - endcase - - always @(*) - if (!i_reset && i_wcyc && o_scyc) - begin - assert(f_acks_in_fifo + (s_count > 0 ? 1:0) - + (s_null ? 1:0) - + (o_wack ? 1:0) == fslv_outstanding); - - if (s_count == 0 && fslv_outstanding > (s_null ? 1:0) + (o_wack ? 1:0)) - assert(f_acks_in_fifo > 0); - end - - assign f_first_ack = f_first_data[WBLSB]; - assign f_second_ack = f_second_data[WBLSB]; - - assign f_first_subaddr = f_first_data[WBLSB-1:0]; - assign f_second_subaddr = f_second_data[WBLSB-1:0]; - - always @(*) - begin - assert(f_acks_in_fifo <= ign_fifo_fill); - assert(!fifo_empty || f_acks_in_fifo == 0); - assert(f_acks_in_fifo >= - ((f_first_in_fifo && f_first_ack) ? 1:0) - + ((f_second_in_fifo && f_second_ack) ? 1:0)); - assert(ign_fifo_fill - f_acks_in_fifo >= - ((f_first_in_fifo && !f_first_ack) ? 1:0) - + ((f_second_in_fifo && !f_second_ack) ? 1:0)); - - if (o_scyc && f_first_in_fifo && f_distance_to_first == ign_fifo_fill - 1) - assert(f_first_ack || s_count > 0); - if (o_scyc && f_second_in_fifo && f_distance_to_second == ign_fifo_fill - 1) - assert(f_second_ack || s_count > 0); - if (!i_reset && i_wcyc && o_scyc - && ign_fifo_fill > 0 && s_count == 0) - assert(f_acks_in_fifo > 0); - - if (o_scyc&& i_wcyc && f_first_in_fifo && s_count == 0 && !o_werr - && f_distance_to_first + 1 < ign_fifo_fill) - assert(f_acks_in_fifo > (f_first_ack ? 1:0)); - - if (o_scyc && i_wcyc && f_second_in_fifo && s_count == 0 && !o_werr - && f_distance_to_second + 1 < ign_fifo_fill) - assert(f_acks_in_fifo > - ((f_first_in_fifo && f_first_ack) ? 1:0) - + (f_second_ack ? 1:0)); - end - - always @(*) - begin - if (f_second_in_fifo) - f_subsequent = (f_distance_to_second + 1 < ign_fifo_fill); - else if (f_first_in_fifo) - f_subsequent = (f_distance_to_first + 1 < ign_fifo_fill); - else - f_subsequent = (f_acks_in_fifo > 0 && s_count == 0); - end - - always @(*) - if ((!f_first_in_fifo || f_distance_to_first > 0) - &&(!f_second_in_fifo || f_distance_to_second > 0) - && !fifo_empty) - begin - assume(!fifo_ack || (f_acks_in_fifo > - ((f_subsequent) ? 1:0) - + ((f_first_in_fifo && f_first_ack) ? 1:0) - + ((f_second_in_fifo && f_second_ack) ? 1:0))); - assume(fifo_ack || (ign_fifo_fill - f_acks_in_fifo > - ((f_first_in_fifo && !f_first_ack) ? 1:0) - + ((f_second_in_fifo && !f_second_ack) ? 1:0))); - if (f_acks_in_fifo == 1 && s_count == 0 && ign_fifo_fill > 1) - assume(!fifo_ack); - end - - always @(*) - if (!i_reset && o_scyc && i_wcyc) - begin - if (f_first_in_fifo && f_second_in_fifo) - begin - assert(f_second_subaddr > f_first_subaddr - || f_first_ack); - end else if (f_first_in_fifo && !f_first_ack) - begin - assert(s_count > 0 - && o_saddr[WBLSB-1:0] > f_first_subaddr); - end - end - - always @(*) - if (!i_reset && o_scyc && i_wcyc) - begin - assert(s_count <= (1< 1) - assert(s_count + o_saddr[WBLSB-1:0]==(1< f_first_subaddr - || f_first_ack); - end - - always @(*) - if (OPT_LITTLE_ENDIAN) - f_mask = {(WIDE_DW/8){1'b1}} >> (o_saddr[WBLSB-1:0] * SMALL_DW/8); - else - f_mask = {(WIDE_DW/8){1'b1}} << (o_saddr[WBLSB-1:0] * SMALL_DW/8); - - always @(*) - if (s_count > 0) - begin - assert((s_sel & (~f_mask)) == 0); - end -`endif - // }}} - // }}} - end endgenerate - -endmodule diff --git a/delete_later/rtl/wb2axip/wbupsz.v b/delete_later/rtl/wb2axip/wbupsz.v deleted file mode 100644 index e701db1..0000000 --- a/delete_later/rtl/wb2axip/wbupsz.v +++ /dev/null @@ -1,233 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbupsz.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Bridge a Wishbone bus from a smaller data width to a wider one. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbupsz #( - // {{{ - parameter ADDRESS_WIDTH = 28, // Byte address width - parameter WIDE_DW = 512, - parameter SMALL_DW = 32, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter [0:0] OPT_LOWPOWER = 1'b0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Incoming small port - // {{{ - input wire i_scyc, i_sstb, i_swe, - input wire [ADDRESS_WIDTH-$clog2(SMALL_DW/8)-1:0] i_saddr, - input wire [SMALL_DW-1:0] i_sdata, - input wire [SMALL_DW/8-1:0] i_ssel, - output wire o_sstall, - output wire o_sack, - output wire [SMALL_DW-1:0] o_sdata, - output wire o_serr, - // }}} - // Outgoing, small bus size, port - // {{{ - output wire o_wcyc, o_wstb, o_wwe, - output wire [ADDRESS_WIDTH-$clog2(WIDE_DW/8)-1:0] o_waddr, - output wire [WIDE_DW-1:0] o_wdata, - output wire [WIDE_DW/8-1:0] o_wsel, - input wire i_wstall, - input wire i_wack, - input wire [WIDE_DW-1:0] i_wdata, - input wire i_werr - // }}} - // }}} - ); - - generate if (WIDE_DW == SMALL_DW) - begin : NO_ADJUSTMENT - // {{{ - assign o_wcyc = i_scyc; - assign o_wstb = i_sstb; - assign o_wwe = i_swe; - assign o_waddr = i_saddr; - assign o_wdata = i_sdata; - assign o_wsel = i_ssel; - - assign o_sstall = i_wstall; - assign o_sack = i_wack; - assign o_sdata = i_wdata; - assign o_serr = i_werr; - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_clk, i_reset }; - // Verilator lint_on UNUSED - // }}} - // }}} - end else begin : UPSIZE - localparam LGFIFO = 5; - reg r_cyc, r_stb, r_we, r_ack, r_err; - reg [ADDRESS_WIDTH-$clog2(WIDE_DW/8)-1:0] r_addr; - reg [WIDE_DW-1:0] r_data, rtn_data; - reg [WIDE_DW/8-1:0] r_sel; - reg [$clog2(WIDE_DW/SMALL_DW)-1:0] r_shift; - wire fifo_full, ign_fifo_empty; - wire [LGFIFO:0] ign_fifo_fill; - - wire [$clog2(WIDE_DW/SMALL_DW)-1:0] w_shift, fifo_shift; - wire [WIDE_DW-1:0] w_data; - wire [WIDE_DW/8-1:0] w_sel; - - if (OPT_LITTLE_ENDIAN) - begin : GEN_LILEND - assign w_data= {{(WIDE_DW-SMALL_DW){1'b0}}, i_sdata }; - assign w_sel ={{((WIDE_DW-SMALL_DW)/8){1'b0}},i_ssel }; - end else begin : GEN_BIGEND - assign w_data= {i_sdata, {(WIDE_DW-SMALL_DW){1'b0}} }; - assign w_sel ={i_ssel,{((WIDE_DW-SMALL_DW)/8){1'b0}} }; - end - - assign w_shift = i_saddr[$clog2(WIDE_DW/SMALL_DW)-1:0]; - - initial r_cyc = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_scyc ||(o_wcyc && i_werr) || o_serr) - r_cyc <= 1'b0; - else if (i_scyc && i_sstb) - r_cyc <= 1'b1; - - initial r_stb = 1'b0; - initial r_we = 1'b0; - initial r_addr = 0; - initial r_data = 0; - initial r_sel = 0; - always @(posedge i_clk) - if (i_reset || !i_scyc || o_serr || (o_wcyc && i_werr)) - begin - // {{{ - r_stb <= 1'b0; - r_we <= 1'b0; - r_addr <= 0; - r_data <= 0; - r_sel <= 0; - r_shift <= 0; - // }}} - end else if (i_sstb && !o_sstall) // New request - begin - // {{{ - r_stb <= 1'b1; - r_we <= i_swe; - r_addr <= i_saddr[ADDRESS_WIDTH-$clog2(SMALL_DW/8)-1:$clog2(WIDE_DW/SMALL_DW)]; - if (OPT_LITTLE_ENDIAN) - begin - r_data <= w_data << (SMALL_DW * w_shift); - r_sel <= w_sel << ((SMALL_DW/8) * w_shift); - end else begin - r_data <= w_data >> (SMALL_DW * w_shift); - r_sel <= w_sel >> ((SMALL_DW/8) * w_shift); - end - r_shift <= w_shift; - // }}} - end else if (!i_wstall) - r_stb <= 1'b0; - - assign o_wcyc = r_cyc; - assign o_wstb = r_stb && !fifo_full; - assign o_wwe = r_we; - assign o_waddr = r_addr; - assign o_wdata = r_data; - assign o_wsel = r_sel; - - sfifo #( - .BW($clog2(WIDE_DW/SMALL_DW)), .LGFLEN(LGFIFO) - ) u_fifo ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || !i_scyc), - .i_wr(o_wstb && !i_wstall), - .i_data(r_shift), - .o_full(fifo_full), .o_fill(ign_fifo_fill), - .i_rd(i_wack), .o_data(fifo_shift), - .o_empty(ign_fifo_empty) - // }}} - ); - - // o_sdata&rtn_data, the return (shifted) data in the WIDE space - // {{{ - initial r_data = 0; - always @(posedge i_clk) - if (OPT_LOWPOWER && (!i_scyc || !o_wcyc || i_werr)) - rtn_data <= 0; - else if (i_wack) - begin - if (OPT_LITTLE_ENDIAN) - rtn_data <= i_wdata >> (SMALL_DW * fifo_shift); - else - rtn_data <= i_wdata << (SMALL_DW * fifo_shift); - end - - if (OPT_LITTLE_ENDIAN) - begin : GEN_LILEND - assign o_sdata = rtn_data[SMALL_DW-1:0]; - end else begin : GEN_BIGEND - assign o_sdata = rtn_data[WIDE_DW-1:WIDE_DW-SMALL_DW]; - end - // }}} - - // o_sack, r_ack - // {{{ - initial r_ack = 0; - always @(posedge i_clk) - r_ack <= !i_reset && i_scyc && o_wcyc && i_wack; - - assign o_sack = r_ack; - // }}} - - // o_serr, r_err - // {{{ - initial r_err = 0; - always @(posedge i_clk) - r_err <= !i_reset && i_scyc && o_wcyc && i_werr; - - assign o_serr = r_err; - // }}} - - assign o_sstall= r_stb && (fifo_full || i_wstall); - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, ign_fifo_fill, ign_fifo_empty, - rtn_data }; - // Verilator lint_on UNUSED - // }}} - end endgenerate - -endmodule diff --git a/delete_later/rtl/wb2axip/wbxbar.v b/delete_later/rtl/wb2axip/wbxbar.v deleted file mode 100644 index 02efe28..0000000 --- a/delete_later/rtl/wb2axip/wbxbar.v +++ /dev/null @@ -1,1791 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: sim/rtl/wbxbar.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A Configurable wishbone cross-bar interconnect, conforming -// to the WB-B4 pipeline specification, as described on the -// ZipCPU blog. -// -// Performance: -// Throughput: One transaction per clock -// Latency: One clock to get access to an unused channel, another to -// place the results on the slave bus, and another to return, or a minimum -// of three clocks. -// -// Usage: To use, you'll need to set NM and NS to the number of masters -// (input ports) and the number of slaves respectively. You'll then -// want to set the addresses for the slaves in the SLAVE_ADDR array, -// together with the SLAVE_MASK array indicating which SLAVE_ADDRs -// are valid. Address and data widths should be adjusted at the same -// time. -// -// Voila, you are now set up! -// -// Now let's fine tune this: -// -// LGMAXBURST can be set to control the maximum number of outstanding -// transactions. An LGMAXBURST of 6 will allow 63 outstanding -// transactions. -// -// OPT_TIMEOUT, if set to a non-zero value, is a number of clock periods -// to wait for a slave to respond. Should the timeout expire and the -// slave not respond, a bus error will be returned and the slave will -// be issued a bus abort signal (CYC will be dropped). -// -// OPT_STARVATION_TIMEOUT, if set, applies the OPT_TIMEOUT counter to -// how long a particular master waits for arbitration. If the master is -// "starved", a bus error will be returned. -// -// OPT_DBLBUFFER is used to increase clock speed by registering all -// outputs. -// -// OPT_LOWPOWER is an experimental feature that, if set, will cause any -// unused FFs to be set to zero rather than flopping in the electronic -// wind, in an effort to minimize transitions over bus wires. This will -// cost some extra logic, for ... an uncertain power savings. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbxbar #( - // i_sstall, i_sack, i_sdata, i_serr); - // {{{ - parameter NM = 4, NS=8, - parameter AW = 32, DW=32, - parameter [NS*AW-1:0] SLAVE_ADDR = { - { 3'b111, {(AW-3){1'b0}} }, - { 3'b110, {(AW-3){1'b0}} }, - { 3'b101, {(AW-3){1'b0}} }, - { 3'b100, {(AW-3){1'b0}} }, - { 3'b011, {(AW-3){1'b0}} }, - { 3'b010, {(AW-3){1'b0}} }, - { 4'b0010, {(AW-4){1'b0}} }, - { 4'b0000, {(AW-4){1'b0}} } }, - parameter [NS*AW-1:0] SLAVE_MASK = (NS <= 1) ? 0 - : { {(NS-2){ 3'b111, {(AW-3){1'b0}} }}, - {(2){ 4'b1111, {(AW-4){1'b0}} }} }, - // - // LGMAXBURST is the log_2 of the length of the longest burst - // that might be seen. It's used to set the size of the - // internal counters that are used to make certain that the - // cross bar doesn't switch while still waiting on a response. - parameter LGMAXBURST=6, - // - // OPT_TIMEOUT is used to help recover from a misbehaving slave. - // If set, this value will determine the number of clock cycles - // to wait for a misbehaving slave before returning a bus error. - // Alternatively, if set to zero, this functionality will be - // removed. - parameter OPT_TIMEOUT = 0, // 1023; - // - // If OPT_TIMEOUT is set, then OPT_STARVATION_TIMEOUT may also - // be set. The starvation timeout adds to the bus error timeout - // generation the possibility that a master will wait - // OPT_TIMEOUT counts without receiving the bus. This may be - // the case, for example, if one bus master is consuming a - // peripheral to such an extent that there's no time/room for - // another bus master to use it. In that case, when the timeout - // runs out, the waiting bus master will be given a bus error. - parameter [0:0] OPT_STARVATION_TIMEOUT = 1'b0 - && (OPT_TIMEOUT > 0), - // - // OPT_DBLBUFFER is used to register all of the outputs, and - // thus avoid adding additional combinational latency through - // the core that might require a slower clock speed. - parameter [0:0] OPT_DBLBUFFER = 1'b0, - // - // OPT_LOWPOWER adds logic to try to force unused values to - // zero, rather than to allow a variety of logic optimizations - // that could be used to reduce the logic count of the device. - // Hence, OPT_LOWPOWER will use more logic, but it won't drive - // bus wires unless there's a value to drive onto them. - parameter [0:0] OPT_LOWPOWER = 1'b1 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - // Here are the bus inputs from each of the WB bus masters - input wire [NM-1:0] i_mcyc, i_mstb, i_mwe, - input wire [NM*AW-1:0] i_maddr, - input wire [NM*DW-1:0] i_mdata, - input wire [NM*DW/8-1:0] i_msel, - // - // .... and their return data - output wire [NM-1:0] o_mstall, - output wire [NM-1:0] o_mack, - output reg [NM*DW-1:0] o_mdata, - output wire [NM-1:0] o_merr, - // - // - // Here are the output ports, used to control each of the - // various slave ports that we are connected to - output reg [NS-1:0] o_scyc, o_sstb, o_swe, - output reg [NS*AW-1:0] o_saddr, - output reg [NS*DW-1:0] o_sdata, - output reg [NS*DW/8-1:0] o_ssel, - // - // ... and their return data back to us. - input wire [NS-1:0] i_sstall, i_sack, - input wire [NS*DW-1:0] i_sdata, - input wire [NS-1:0] i_serr - // }}} - ); - // - // - //////////////////////////////////////////////////////////////////////// - // - // Register declarations - // {{{ - // - // TIMEOUT_WIDTH is the number of bits in counter used to check - // on a timeout. - localparam TIMEOUT_WIDTH = $clog2(OPT_TIMEOUT); - // - // LGNM is the log (base two) of the number of bus masters - // connecting to this crossbar - localparam LGNM = (NM>1) ? $clog2(NM) : 1; - // - // LGNS is the log (base two) of the number of slaves plus one - // come out of the system. The extra "plus one" is used for a - // pseudo slave representing the case where the given address - // doesn't connect to any of the slaves. This address will - // generate a bus error. - localparam LGNS = $clog2(NS+1); - // At one time I used o_macc and o_sacc to put into the outgoing - // trace file, just enough logic to tell me if a transaction was - // taking place on the given clock. - // - // assign o_macc = (i_mstb & ~o_mstall); - // assign o_sacc = (o_sstb & ~i_sstall); - // - // These definitions work with Veri1ator, just not with Yosys - // reg [NM-1:0][NS:0] request; - // reg [NM-1:0][NS-1:0] requested; - // reg [NM-1:0][NS:0] grant; - // - // These definitions work with both - wire [NS:0] request [0:NM-1]; - reg [NS-1:0] requested [0:NM-1]; - reg [NS:0] grant [0:NM-1]; - reg [NM-1:0] mgrant; - reg [NS-1:0] sgrant; - - // Verilator lint_off UNUSED - wire [LGMAXBURST-1:0] w_mpending [0:NM-1]; - // Verilator lint_on UNUSED - reg [NM-1:0] mfull, mnearfull, mempty; - wire [NM-1:0] timed_out; - - localparam NMFULL = (NM > 1) ? (1< 0) - begin : CHECK_TIMEOUT - // {{{ - for(N=0; N 0) - begin - deadlock_timer <= deadlock_timer - 1; - r_timed_out <= (deadlock_timer <= 1); - end - - assign timed_out[N] = r_timed_out; - end - // }}} - end else begin : NO_TIMEOUT - // {{{ - assign timed_out = 0; - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Parameter consistency check - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial begin : PARAMETER_CONSISTENCY_CHECK - // {{{ - if (NM == 0) - begin - $display("ERROR: At least one master must be defined"); - $stop; - end - - if (NS == 0) - begin - $display("ERROR: At least one slave must be defined"); - $stop; - end - - if (OPT_STARVATION_TIMEOUT != 0 && OPT_TIMEOUT == 0) - begin - $display("ERROR: The starvation timeout is implemented as part of the regular timeout"); - $display(" Without a timeout, the starvation timeout will not work"); - $stop; - end - // }}} - end - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties used to verify the core -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Register declarations - // {{{ - localparam F_MAX_DELAY = 4; - localparam F_LGDEPTH = LGMAXBURST; - // - reg f_past_valid; - // - // Our bus checker keeps track of the number of requests, - // acknowledgments, and the number of outstanding transactions on - // every channel, both the masters driving us - wire [F_LGDEPTH-1:0] f_mreqs [0:NM-1]; - wire [F_LGDEPTH-1:0] f_macks [0:NM-1]; - wire [F_LGDEPTH-1:0] f_moutstanding [0:NM-1]; - // - // as well as the slaves that we drive ourselves - wire [F_LGDEPTH-1:0] f_sreqs [0:NS-1]; - wire [F_LGDEPTH-1:0] f_sacks [0:NS-1]; - wire [F_LGDEPTH-1:0] f_soutstanding [0:NS-1]; - // }}} - - initial assert(!OPT_STARVATION_TIMEOUT || OPT_TIMEOUT > 0); - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid = 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - generate for(N=0; N= - ((OPT_BUFFER_DECODER && dcd_stb[N]) ? 1:0) - + (o_mack[N] && OPT_DBLBUFFER) ? 1:0); - - always @(*) - n_outstanding = f_moutstanding[N] - - ((OPT_BUFFER_DECODER && dcd_stb[N]) ? 1:0) - - ((o_mack[N] && OPT_DBLBUFFER) ? 1:0); - - always @(posedge i_clk) - if (i_mcyc[N] && !mgrant[N] && !o_merr[N]) - assert(f_moutstanding[N] - == ((OPT_BUFFER_DECODER & dcd_stb[N]) ? 1:0)); - - else if (i_mcyc[N] && mgrant[N] && !i_reset) - for(iM=0; iM 0) - assert(i_mwe[N] == o_swe[iM]); - if (o_sstb[iM]) - assert(i_mwe[N] == o_swe[iM]); - if (o_mack[N]) - assert(i_mwe[N] == o_swe[iM]); - if (o_scyc[iM] && i_sack[iM]) - assert(i_mwe[N] == o_swe[iM]); - if (o_merr[N] && !timed_out[N]) - assert(i_mwe[N] == o_swe[iM]); - if (o_scyc[iM] && i_serr[iM]) - assert(i_mwe[N] == o_swe[iM]); - end - end - - always @(*) - if (!i_reset && OPT_BUFFER_DECODER && i_mcyc[N]) - begin - if (dcd_stb[N]) - assert(i_mwe[N] == m_we[N]); - end - // }}} - end endgenerate - - generate for(M=0; M 1) - begin : DOUBLE_ADDRESS_CHECK - // {{{ - // - // Check that no slave address has been assigned twice. - // This check only needs to be done once at the beginning - // of the run, during the BMC section. - reg address_found; - - always @(*) - if (!f_past_valid) - begin - address_found = 0; - for(iM=0; iM 1) - begin - - always @(posedge i_clk) - cover(!f_cvr_aborted && (&f_m_ackd[1:0])); - - end endgenerate - - initial f_s_ackd = 0; - generate for (M=0; M 1) - begin - - always @(posedge i_clk) - cover(!f_cvr_aborted && (&f_s_ackd[NS-1:0])); - - end endgenerate - // }}} -`endif -// }}} -endmodule -`ifndef YOSYS -`default_nettype wire -`endif diff --git a/delete_later/rtl/wbfan.v b/delete_later/rtl/wbfan.v deleted file mode 100644 index 9e93227..0000000 --- a/delete_later/rtl/wbfan.v +++ /dev/null @@ -1,405 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbfan -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Controls the FPGA and case fan speeds. -// -// Registers: -// 0: Current FPGA fan PWM -// 1: Current System fan PWM -// 2: Measured FAN speed -// 3: Measured temperature, twos-complement, in quarter degrees -// centigrade. Multiply by 36/5 and add 128 to get -// Fahrenheit. -// 4: Temperature I2C control, bypass to temp I2CCPU -// 5: Temperature I2C Override -// 6: Temperature I2C address -- only points to local (fixed) mem -// 7: Temperature I2C ckcount -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbfan ( - // {{{ - input wire i_clk, i_reset, - // - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [2:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // - input wire i_temp_sda, i_temp_scl, - output wire o_temp_sda, o_temp_scl, - // - output reg o_fpga_pwm, - output reg o_sys_pwm, - input wire i_fan_tach, - // - output wire [31:0] temp_debug - // }}} - ); - - // Local declarations - // {{{ - localparam CK_PER_SECOND = 100_000_000, - CK_PER_MS = (CK_PER_SECOND / 1000), - PWM_HZ = 20_000; - localparam MAX_PWM = (CK_PER_SECOND / PWM_HZ)-1; - localparam LGPWM = $clog2(MAX_PWM+1); - reg [LGPWM-1:0] pwm_counter; - reg [LGPWM-1:0] ctl_fpga, ctl_sys; - - reg ck_tach, last_tach; - reg [1:0] pipe_tach; - reg tach_reset; - reg [$clog2(CK_PER_SECOND)-1:0] tach_count, tach_counter, - tach_timer; - - wire i2c_wb_stall, i2c_wb_ack; - wire [31:0] i2c_wb_data; - - wire ign_mem_cyc, mem_stb, ign_mem_we, ign_mem_sel; - wire [4:0] mem_addr; - wire [7:0] ign_mem_data; - reg [7:0] mem_data; - reg mem_ack; - - wire i2cd_valid, i2cd_last, ign_i2cd_id; - wire [7:0] i2cd_data; - - reg pp_ms; - reg [$clog2(CK_PER_MS)-1:0] trigger_counter; - - reg [23:0] temp_tmp; - reg [31:0] temp_data; - - reg pre_ack; - reg [31:0] pre_data; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Fan control itself - // {{{ - - // ctl_fpga, ctl_sys - // {{{ - initial ctl_fpga = MAX_PWM[LGPWM-1:0]; - initial ctl_sys = MAX_PWM[LGPWM-1:0]; - always @(posedge i_clk) - if (i_reset) - begin - ctl_fpga <= MAX_PWM[LGPWM-1:0]; - ctl_sys <= MAX_PWM[LGPWM-1:0]; - end else if (i_wb_stb && i_wb_we && i_wb_addr[2] == 1'b0) - begin - case(i_wb_addr[1:0]) - 2'b00: begin - if (i_wb_sel[0]) ctl_fpga[ 7: 0] <= i_wb_data[ 7: 0]; - if (i_wb_sel[1]) ctl_fpga[LGPWM-1: 8] <= i_wb_data[LGPWM-1: 8]; - // if (i_wb_sel[2]) ctl_fpga[23:16] <= i_wb_data[23:16]; - // if (i_wb_sel[3]) ctl_fpga[31:24] <= i_wb_data[31:24]; - end - 2'b01: begin - if (i_wb_sel[0]) ctl_sys[ 7: 0] <= i_wb_data[ 7: 0]; - if (i_wb_sel[1]) ctl_sys[LGPWM-1: 8] <= i_wb_data[LGPWM-1: 8]; - // if (i_wb_sel[2]) ctl_sys[23:16] <= i_wb_data[23:16]; - // if (i_wb_sel[3]) ctl_sys[31:24] <= i_wb_data[31:24]; - end - default: begin end - endcase - end else begin - if (ctl_fpga >= MAX_PWM[LGPWM-1:0]) - ctl_fpga <= MAX_PWM[LGPWM-1:0]; - if (ctl_sys >= MAX_PWM[LGPWM-1:0]) - ctl_sys <= MAX_PWM[LGPWM-1:0]; - end - // }}} - - // pwm_counter - // {{{ - always @(posedge i_clk) - if (pwm_counter >= MAX_PWM[LGPWM-1:0]) - pwm_counter <= 0; - else - pwm_counter <= pwm_counter + 1; - - // }}} - - // o_*_pwm - // {{{ - // Need a 20kHz proper PWM signal, with an adjustable duty cycle - always @(posedge i_clk) - o_fpga_pwm <=(ctl_fpga >= pwm_counter)||(ctl_fpga >= MAX_PWM[LGPWM-1:0]); - always @(posedge i_clk) - o_sys_pwm <= (ctl_sys >= pwm_counter)|| (ctl_sys >= MAX_PWM[LGPWM-1:0]); - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Tachometer counter - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - - always @(posedge i_clk) - { last_tach, ck_tach, pipe_tach } - <= { ck_tach, pipe_tach, i_fan_tach }; - - always @(posedge i_clk) - if (i_reset) - begin - tach_reset <= 1; - tach_counter <= 0; - tach_count <= 0; - tach_timer <= 0; - end else if (tach_reset) - begin - tach_reset <= 1'b0; - tach_timer <= CK_PER_SECOND[$clog2(CK_PER_SECOND)-1:0]-1; - tach_count <= tach_counter; - tach_counter <= (ck_tach && !last_tach) ? 1 : 0; - end else begin - tach_counter <= tach_counter + ((ck_tach && !last_tach) ? 1:0); - - tach_timer <= tach_timer - 1; - tach_reset <= (tach_timer <= 1); - end - - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // I2C Temperature reader: Address 7'b1001_000 and/or 7'b1001_001 - // {{{ - //////////////////////////////////////////////////////////////////////// - // - - always @(posedge i_clk) - if (i_reset) - begin - pp_ms <= 1'b0; - trigger_counter <= CK_PER_MS[$clog2(CK_PER_MS)-1:0]-1; - end else if (trigger_counter == 0) - begin - pp_ms <= 1'b0; - trigger_counter <= CK_PER_MS[$clog2(CK_PER_MS)-1:0]-1; - end else begin - pp_ms <= (trigger_counter <= 1); - trigger_counter <= trigger_counter - 1; - end - - // Our script - // {{{ - // TARGET: - // CHANNEL 0 - // ABORT - // WAIT - // START // @ 4.1 - // SEND 0x48,WR - // SEND 0x00 // Temperature address - // START - // SEND 0x48,RD - // RXK // Read two bytes of temperature - // RXN - // STOP // @B.1 - // START // @C.0 - // SEND 0x49,WR - // SEND 0x00 // Temperature address - // START - // SEND 0x49,RD - // RXK // Read two bytes of temperature - // RXLN - // STOP - // JUMP - // Second start, if only TEMP1 is available - // TARGET: - // ABORT - // WAIT - // START // @C.0 - // SEND 0x49,WR - // SEND 0x00 // Temperature address - // START - // SEND 0x49,RD - // RXK // Read two bytes of temperature - // RXLN - // STOP - // JUMP - // HALT - // }}} - - wbi2ccpu #( - // {{{ - .ADDRESS_WIDTH(5), - .DATA_WIDTH(8), - .AXIS_ID_WIDTH(0), - .OPT_START_HALTED(1'b0), - .DEF_CKCOUNT(200) - // }}} - ) u_i2ccpu ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_wb_cyc(i_wb_cyc), .i_wb_stb(i_wb_stb && i_wb_addr[2]), - .i_wb_we(i_wb_we), .i_wb_addr(i_wb_addr[1:0]), - .i_wb_data(i_wb_data), .i_wb_sel(i_wb_sel), - .o_wb_stall(i2c_wb_stall), .o_wb_ack(i2c_wb_ack), - .o_wb_data(i2c_wb_data), - // - .o_pf_cyc(ign_mem_cyc), .o_pf_stb(mem_stb), - .o_pf_we(ign_mem_we), .o_pf_addr(mem_addr), - .o_pf_data(ign_mem_data), .o_pf_sel(ign_mem_sel), - .i_pf_stall(1'b0), .i_pf_ack(mem_ack), .i_pf_err(1'b0), - .i_pf_data(mem_data), - // - .i_i2c_sda(i_temp_sda), .i_i2c_scl(i_temp_scl), - .o_i2c_sda(o_temp_sda), .o_i2c_scl(o_temp_scl), - // - .M_AXIS_TVALID(i2cd_valid), - .M_AXIS_TREADY(1'b1), - .M_AXIS_TDATA(i2cd_data), - .M_AXIS_TID(ign_i2cd_id), - .M_AXIS_TLAST(i2cd_last), - // - .i_sync_signal(pp_ms), - .o_debug(temp_debug) - // }}} - ); - - always @(posedge i_clk) - mem_ack <= !i_reset && mem_stb; - - // mem_addr - // {{{ - always @(posedge i_clk) - if (mem_stb) - case(mem_addr) - 5'h00: mem_data <= 8'hb0; // TARGET - 5'h01: mem_data <= 8'hd0; // CHANNEL - 5'h02: mem_data <= 8'h00; // #0 - 5'h03: mem_data <= 8'ha0; // ABORT - 5'h04: mem_data <= 8'h81; // WAIT | START - 5'h05: mem_data <= 8'h30; // SEND - 5'h06: mem_data <= 8'h90; // #90 - 5'h07: mem_data <= 8'h30; // SEND - 5'd08: mem_data <= 8'h00; // #00 - 5'h09: mem_data <= 8'h13; // START | SEND - 5'h0a: mem_data <= 8'h91; // #91 - 5'h0b: mem_data <= 8'h45; // RXK | RXN - 5'h0c: mem_data <= 8'h21; // STOP | START - 5'h0d: mem_data <= 8'h30; // SEND - 5'h0e: mem_data <= 8'h92; // #92 - 5'h0f: mem_data <= 8'h30; // SEND - 5'h10: mem_data <= 8'h00; // #00 - 5'h11: mem_data <= 8'h13; // START | SEND - 5'h12: mem_data <= 8'h93; // #93 - 5'h13: mem_data <= 8'h47; // RXK | RXLN - 5'h14: mem_data <= 8'h2c; // STOP | JUMP - // Sensor #1 only (skip sensor #0) - 5'h15: mem_data <= 8'hb0; // TARGET - 5'h16: mem_data <= 8'ha0; // ABORT - 5'h17: mem_data <= 8'h81; // WAIT | START - 5'h18: mem_data <= 8'h30; // SEND 0x49,WR - 5'h19: mem_data <= 8'h92; // #92 - 5'h1a: mem_data <= 8'h30; // SEND 0x00 - 5'h1b: mem_data <= 8'h00; // - 5'h1c: mem_data <= 8'h13; // START | SEND 0x49,RD - 5'h1d: mem_data <= 8'h93; // #93 - 5'h1e: mem_data <= 8'h47; // RXK | RXLN - 5'h1f: mem_data <= 8'h2c; // STOP | JUMP - // default: mem_data <= 8'h99; - endcase - // }}} - - always @(posedge i_clk) - if (i2cd_valid) - temp_tmp <= { temp_tmp[15:0], i2cd_data }; - - always @(posedge i_clk) - if (i2cd_valid && i2cd_last) - temp_data <= { temp_tmp, i2cd_data }; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // WB returns - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial pre_ack = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wb_cyc) - pre_ack <= 1'b0; - else - pre_ack <= i_wb_stb && !o_wb_stall; - - always @(posedge i_clk) - if (i_reset || !i_wb_stb || i_wb_addr[2]) - pre_data <= 0; - else begin - pre_data <= 0; - case(i_wb_addr[1:0]) - 2'b00: pre_data[LGPWM-1:0] <= ctl_fpga; - 2'b01: pre_data[LGPWM-1:0] <= ctl_sys; - 2'b10: pre_data[$clog2(CK_PER_SECOND)-1:0] <= tach_count; - 2'b11: pre_data <= temp_data; - default: pre_data <= 32'h0; - endcase - end - - assign o_wb_stall = i2c_wb_stall; - - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - if (i_reset || !i_wb_cyc) - o_wb_ack <= 1'b0; - else - o_wb_ack <= pre_ack; - - always @(posedge i_clk) - if (i_reset || !i_wb_cyc) - o_wb_data <= 0; - else if (i2c_wb_ack) - o_wb_data <= i2c_wb_data; - else - o_wb_data <= pre_data; - // }}} - - // Keep Verilator happy - // {{{ - wire unused; - assign unused = &{ 1'b0, ign_mem_cyc, ign_mem_we, ign_mem_data, - ign_mem_sel, ign_i2cd_id }; - // }}} -endmodule diff --git a/delete_later/rtl/wbgpio.v b/delete_later/rtl/wbgpio.v deleted file mode 100644 index ae946e7..0000000 --- a/delete_later/rtl/wbgpio.v +++ /dev/null @@ -1,136 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbgpio.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This extremely simple GPIO controller, although minimally -// featured, is designed to control up to sixteen general purpose -// input and sixteen general purpose output lines of a module from a -// single address on a 32-bit wishbone bus. -// -// Input GPIO values are contained in the top 16-bits. Any change in -// input values will generate an interrupt. -// -// Output GPIO values are contained in the bottom 16-bits. To change an -// output GPIO value, writes to this port must also set a bit in the -// upper sixteen bits. Hence, to set GPIO output zero, one would write -// a 0x010001 to the port, whereas a 0x010000 would clear the bit. This -// interface makes it possible to change only the bit of interest, without -// needing to capture and maintain the prior bit values--something that -// might be difficult from a interrupt context within a CPU. -// -// Unlike other controllers, this controller offers no capability to -// change input/output direction, or to implement pull-up or pull-down -// resistors. It simply changes and adjusts the values going out the -// output pins, while allowing a user to read the values on the input -// pins. -// -// Any change of an input pin value will result in the generation of an -// interrupt signal. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbgpio #( - // {{{ - parameter NIN=16, NOUT=16, - parameter [(NOUT-1):0] DEFAULT=0 - // }}} - ) ( - // {{{ - input wire i_clk, - // - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [31:0] i_wb_data, - input wire [32/8-1:0] i_wb_sel, - // - output wire o_wb_stall, - output wire o_wb_ack, - output wire [31:0] o_wb_data, - // - input wire [(NIN-1):0] i_gpio, - output reg [(NOUT-1):0] o_gpio, - // - output reg o_int - // }}} - ); - - // Local declarations - // {{{ - reg [(NIN-1):0] r_gpio; - (* ASYNC_REG *) reg [(NIN-1):0] x_gpio, q_gpio; - wire [15:0] hi_bits, low_bits; - // }}} - - assign o_wb_ack = i_wb_stb; - assign o_wb_stall = 1'b0; - - // o_gpio - // {{{ - // 9LUT's, 16 FF's - initial o_gpio = DEFAULT; - always @(posedge i_clk) - if (i_wb_stb && i_wb_we && (&i_wb_sel)) - o_gpio <= ((o_gpio)&(~i_wb_data[(NOUT+16-1):16])) - |((i_wb_data[(NOUT-1):0])&(i_wb_data[(NOUT+16-1):16])); - // }}} - - // 3 LUTs, 33 FF's - // {{{ - always @(posedge i_clk) - begin - { r_gpio, q_gpio, x_gpio } <= { q_gpio, x_gpio, i_gpio }; - o_int <= (q_gpio != r_gpio); - end - // }}} - - // o_wb_data - // {{{ - assign hi_bits[ (NIN -1):0] = r_gpio; - assign low_bits[(NOUT-1):0] = o_gpio; - - generate - if (NIN < 16) - begin : GEN_HIBITS - assign hi_bits[ 15: NIN] = 0; - end - if (NOUT < 16) - begin : GEN_LOBITS - assign low_bits[15:NOUT] = 0; - end endgenerate - - assign o_wb_data = { hi_bits, low_bits }; - // }}} - - // Make Verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_wb_data[31:0], i_wb_sel }; - // verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/wbi2c/axisi2c.v b/delete_later/rtl/wbi2c/axisi2c.v deleted file mode 100644 index 47c2d3d..0000000 --- a/delete_later/rtl/wbi2c/axisi2c.v +++ /dev/null @@ -1,1084 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: axisi2c.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is a lower level I2C driver for a master I2C byte-wise -// interface. It accepts commands via AXI-Stream, and reports -// results via AXI Stream. -// -// Commands: -// {{{ -// 3'h0,8'hxx NOP -// 3'h1,8'hxx START -// 3'h2,8'hxx STOP (Ignored if we are already busy) -// 3'h3,8'hdata SEND -// 3'h4,8'hxx RXK -// 3'h5,8'hxx RXN -// 3'h6,8'hxx RXLK -// 3'h7,8'hxx RXLN -// (4'h8) WAIT (for external interrupt. Handled externally) -// (4'h9) HALT -// (4'ha) ABORT (Return here following an unexpected NAK) -// (4'hb) TARGET (Return here on any jump) -// (4'hc) JUMP (Useful for repeats, handled externally) -// (4'hd) CHANNEL (Sets the outgoing AXI stream channel ID) -// }}} -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module axisi2c #( - parameter OPT_WATCHDOG = 0, - parameter [0:0] OPT_LOWPOWER = 1'b0 - ) ( - // {{{ - input wire S_AXI_ACLK, S_AXI_ARESETN, - // - // Incoming instruction stream - // {{{ - input wire S_AXIS_TVALID, - output wire S_AXIS_TREADY, - input wire [8+3-1:0] S_AXIS_TDATA, - // input wire S_AXIS_TLAST, (unused) - // }}} - // Outgoing received data stream - // {{{ - output reg M_AXIS_TVALID, - input wire M_AXIS_TREADY, - output reg [8-1:0] M_AXIS_TDATA, - output reg M_AXIS_TLAST, - // }}} - // - input wire i_ckedge, - output wire o_stretch, - input wire i_scl, i_sda, - output reg o_scl, o_sda, // 1 = tristate, 0 = ground - - output reg o_abort - // }}} - ); - - // Local declarations - // {{{ - - // Parameter, enumerations, and state declarations - // {{{ - localparam [3:0] IDLE_STOPPED = 4'h0, - START = 4'h1, - IDLE_ACTIVE = 4'h2, - STOP = 4'h3, - DATA = 4'h4, - CLOCK = 4'h5, - ACK = 4'h6, - CKACKLO = 4'h7, - CKACKHI = 4'h8, - RXNAK = 4'h9, - ABORT = 4'ha, - REPEAT_START = 4'hb, - REPEAT_START2= 4'hc; - // INIT = 4'hd; // Wait for SDA && SCL? - - localparam D_RD = 1'b0, D_WR = 1'b1; - - localparam [2:0] CMD_NOOP = 3'h0, - CMD_START = 3'h1, - CMD_STOP = 3'h2, - CMD_SEND = 3'h3, - CMD_RXK = 3'h4, - CMD_RXN = 3'h5, - CMD_RXLK = 3'h6, - CMD_RXLN = 3'h7; - - localparam [0:0] OPT_ABORT_REQUEST = 1'b0; - // }}} - - reg last_byte, dir, will_ack; reg [3:0] state; - reg [2:0] nbits; - reg [7:0] sreg; - - reg q_scl, q_sda, ck_scl, ck_sda, lst_scl, lst_sda; - reg stop_bit, channel_busy; - wire watchdog_timeout; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Synchronize the asynchronous inputs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial { lst_scl, ck_scl, q_scl } = 3'b111; - initial { lst_sda, ck_sda, q_sda } = 3'b111; - -`ifndef FORMAL - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - begin - { lst_scl, ck_scl, q_scl } <= 3'b111; - { lst_sda, ck_sda, q_sda } <= 3'b111; - end else begin - { lst_scl, ck_scl, q_scl } <= { ck_scl, q_scl, i_scl }; - { lst_sda, ck_sda, q_sda } <= { ck_sda, q_sda, i_sda }; - end -`else - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - begin - lst_scl <= 1'b1; - lst_sda <= 1'b1; - end else begin - lst_scl <= ck_scl; - lst_sda <= ck_sda; - end - - always @(*) - { ck_scl, q_scl } = {(2){i_scl}}; - always @(*) - { ck_sda, q_sda } = {(2){i_sda}}; -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Channel busy, and watchdog - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial stop_bit = 1'b0; - initial channel_busy = 1'b0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - begin - stop_bit <= 1'b0; - channel_busy <= 1'b0; - end else begin - stop_bit <= (ck_scl)&&(lst_scl)&&( ck_sda)&&(!lst_sda); - - if (!ck_scl || !ck_sda) - channel_busy <= 1'b1; - else if (stop_bit) - channel_busy <= 1'b0; - end - - generate if (OPT_WATCHDOG > 0) - begin : GEN_WATCHDOG - // {{{ - reg [OPT_WATCHDOG:0] r_watchdog_counter; - reg r_watchdog_timeout; - - initial r_watchdog_counter = 0; - initial r_watchdog_timeout = 0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - begin - r_watchdog_counter <= 0; - r_watchdog_timeout <= 0; - end else begin - if (!channel_busy) - r_watchdog_counter <= 0; - else if (!r_watchdog_counter[OPT_WATCHDOG]) - r_watchdog_counter <= r_watchdog_counter + 1'b1; - - r_watchdog_timeout <= r_watchdog_counter[OPT_WATCHDOG]; - end - - assign watchdog_timeout = r_watchdog_timeout; - // }}} - end else begin : NO_WATCHDOG - assign watchdog_timeout = 1'b0; - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Master state machine - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial state = IDLE_STOPPED; - initial nbits = 3'h0; - initial sreg = 8'hff; - initial o_scl = 1'b1; - initial o_sda = 1'b1; - always @(posedge S_AXI_ACLK) - begin - if (i_ckedge) case(state) - IDLE_STOPPED: begin - // {{{ - nbits <= 0; - will_ack <= 1'b1; - last_byte <= 1'b0; - - sreg <= (OPT_LOWPOWER) ? 8'h0 : S_AXIS_TDATA[7:0]; - dir <= D_RD; - if (S_AXIS_TVALID && S_AXIS_TREADY) - begin - // NOTE: We aren't detecting collisions here. - // Perhaps we should be, but we can't force - // the driver to seize if something is wrong. - // Hence, if i_ckedge is true, S_AXIS_TREADY - // must also be true. - case(S_AXIS_TDATA[10:8]) - CMD_NOOP: begin end - CMD_START: begin - // {{{ - o_sda <= 1'b0; - o_scl <= 1'b1; - state <= START; - end - // }}} - CMD_STOP: begin - // {{{ - // We are already stopped. Therefore - // do nothing. - end - // }}} - CMD_RXK: begin - // {{{ - o_sda <= 1'b0; - o_scl <= 1'b1; - state <= START; - - nbits <= 3'h7; - end - // }}} - CMD_RXN: begin - // {{{ - will_ack <= 1'b0; - nbits <= 3'h7; - - o_sda <= 1'b0; - o_scl <= 1'b1; - state <= START; - end - // }}} - CMD_RXLK: begin - // {{{ - o_sda <= 1'b0; - o_scl <= 1'b1; - state <= START; - - last_byte <= 1'b1; - nbits <= 3'h7; - end - // }}} - CMD_RXLN: begin - // {{{ - o_sda <= 1'b0; - o_scl <= 1'b1; - state <= START; - - last_byte <= 1'b1; - will_ack <= 1'b0; - nbits <= 3'h7; - end - // }}} - CMD_SEND: begin - // {{{ - o_sda <= 1'b0; - o_scl <= 1'b1; - state <= START; - - dir <= D_WR; - nbits <= 3'h7; - sreg <= S_AXIS_TDATA[7:0]; - end - // }}} - endcase - - if (OPT_ABORT_REQUEST && (!ck_scl || !ck_sda || channel_busy)) - begin - state <= ABORT; - nbits <= 0; - { o_scl, o_sda } <= 2'b11; - end - end end - // }}} - START: begin - // {{{ - if (nbits[2]) - state <= DATA; - else - state <= IDLE_ACTIVE; - o_scl <= 1'b0; - o_sda <= 1'b0; - end - // }}} - IDLE_ACTIVE: begin - // {{{ - nbits <= 0; - will_ack <= 1'b1; - last_byte <= 1'b0; - - sreg <= (OPT_LOWPOWER) ? 8'h0 : S_AXIS_TDATA[7:0]; - dir <= D_RD; - o_sda <= 1'b0; - o_scl <= 1'b0; - if (S_AXIS_TVALID && S_AXIS_TREADY) - begin - case(S_AXIS_TDATA[10:8]) - CMD_NOOP: begin end - CMD_START: begin - // {{{ - o_scl <= 1'b0; - o_sda <= 1'b1; - state <= REPEAT_START; - end - // }}} - CMD_STOP: begin - // {{{ - o_scl <= 1'b1; - o_sda <= 1'b0; - state <= STOP; - end - // }}} - CMD_RXK: begin - // {{{ - nbits <= 3'h7; - o_sda <= 1'b0; - o_scl <= 1'b0; - state <= DATA; - end - // }}} - CMD_RXN: begin - // {{{ - will_ack <= 1'b0; - nbits <= 3'h7; - - o_sda <= 1'b0; - o_scl <= 1'b0; - state <= DATA; - end - // }}} - CMD_RXLK: begin - // {{{ - last_byte <= 1'b1; - nbits <= 3'h7; - o_sda <= 1'b0; - o_scl <= 1'b0; - state <= DATA; - end - // }}} - CMD_RXLN: begin - // {{{ - last_byte <= 1'b1; - will_ack <= 1'b0; - nbits <= 3'h7; - o_sda <= 1'b0; - o_scl <= 1'b0; - state <= DATA; - end - // }}} - CMD_SEND: begin - // {{{ - dir <= D_WR; - nbits <= 3'h7; - o_sda <= 1'b0; - o_scl <= 1'b0; - state <= DATA; - sreg <= S_AXIS_TDATA[7:0]; - end - // }}} - endcase - end end - // }}} - STOP: begin - // {{{ - o_scl <= 1'b1; - if (ck_scl) begin - // o_scl == 1 on entry - // o_sda == 0 - state <= IDLE_STOPPED; - o_sda <= 1'b1; - end end - // }}} - REPEAT_START: if (!o_stretch) begin - // {{{ - // SDA && !SCL on entry - o_scl <= 1'b1; - o_sda <= 1'b1; - state <= REPEAT_START2; - - if (o_sda != ck_sda) - begin - { o_scl, o_sda } <= 2'b11; - state <= ABORT; - end - end - // }}} - REPEAT_START2: if (!o_stretch) begin - // {{{ - // SDA && SCL on entry - o_scl <= 1'b1; - o_sda <= 1'b0; - state <= START; - - if (!ck_sda || !ck_scl) - begin - { o_scl, o_sda } <= 2'b11; - state <= ABORT; - end - end - // }}} - // - DATA: begin - // {{{ - o_scl <= 1'b0; - o_sda <= sreg[7] || (dir == D_RD); - if (o_sda == (sreg[7] || (dir == D_RD))) - state <= CLOCK; - - if (ck_scl) - state <= DATA; - end - // }}} - CLOCK: begin - // {{{ - if (ck_scl) - begin - o_scl <= 1'b0; - sreg <= { sreg[6:0], ck_sda }; - if (nbits > 0) - nbits <= nbits - 1; - - if (dir == D_WR && ck_sda != sreg[7]) - begin - state <= ABORT; - { o_scl, o_sda } <= 2'b11; - end else if (nbits == 0) - state <= ACK; - else - state <= DATA; - end else - o_scl <= 1'b1; - end - // }}} - ACK: begin - // {{{ - o_scl <= 1'b0; - o_sda <= (dir == D_WR) || !will_ack; - - // Clock stretch - if (!ck_scl) case(dir) - D_RD: if (o_sda != will_ack) - state <= CKACKLO; - D_WR: state <= CKACKLO; - endcase - - if (ck_scl) - state <= ACK; - end - // }}} - CKACKLO: begin - // {{{ - // !o_scl on entry - o_scl <= 1'b1; - o_sda <= (dir == D_WR) || !will_ack; - state <= CKACKHI; - end - // }}} - CKACKHI: begin - // {{{ - o_scl <= 1'b1; - if (ck_scl) // Check for clock stretching - begin - o_scl <= 1'b0; - o_sda <= 1'b0; - - if (dir == D_WR && ck_sda) - state <= RXNAK; - else - state <= IDLE_ACTIVE; - end end - // }}} - RXNAK: begin - // {{{ - // We received a NAK. Protocol failure! - // Send a STOP bit and return to idle - o_scl <= 1'b0; - o_sda <= 1'b0; - if (!ck_scl && !ck_sda) - begin - o_scl <= 1'b1; - state <= STOP; - end end - // }}} - ABORT: begin - // {{{ - // COLLISION!!! - o_scl <= 1'b1; - o_sda <= 1'b1; - if (!channel_busy && ck_scl && ck_sda) - state <= IDLE_STOPPED; - else if (watchdog_timeout) - begin - o_scl <= 1'b1; - o_sda <= 1'b0; - state <= STOP; - end end - // }}} - default: begin - // {{{ - o_scl <= 1'b1; - o_sda <= 1'b1; - if (!channel_busy) - state <= IDLE_STOPPED; - else if (watchdog_timeout) - begin - o_sda <= 1'b0; - state <= STOP; - end end - // }}} - endcase - - if (!S_AXI_ARESETN) - begin - o_scl <= 1'b1; - o_sda <= 1'b1; - state <= IDLE_STOPPED; - end - end - - assign S_AXIS_TREADY = i_ckedge && (state == IDLE_STOPPED - || state == IDLE_ACTIVE); - - // o_abort - // {{{ - initial o_abort = 1'b0; - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - o_abort <= 1'b0; - else if (!i_ckedge || (o_stretch && !S_AXIS_TREADY)) - o_abort <= 1'b0; - else begin - o_abort <= 1'b0; - - // RXNAK - if (ck_scl && dir == D_WR && state == CKACKHI && ck_sda) - o_abort <= 1'b1; - - // COLLISION ABORT!! - if (ck_scl && dir == D_WR && state == CLOCK && ck_sda != sreg[7]) - o_abort <= 1; - - // COLLISION ABORT ON REQUEST!! - if (state == REPEAT_START && (o_sda != ck_sda)) - o_abort <= 1; - if (state == REPEAT_START2 && (!ck_scl || !ck_sda)) - o_abort <= 1; - - if (OPT_ABORT_REQUEST && state == IDLE_STOPPED - && (!ck_scl || !ck_sda || channel_busy)&& S_AXIS_TVALID) - o_abort <= 1; - end - // }}} - - // Stretch the idle clock, so we're always ready to accept once idle - // is over. - assign o_stretch = (o_scl && !ck_scl) - ||(!S_AXIS_TVALID && (state == IDLE_STOPPED || state == IDLE_ACTIVE)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Outgoing AXI Stream - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // M_AXIS_TVALID - // {{{ - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN) - M_AXIS_TVALID <= 1'b0; - else if (i_ckedge && !o_stretch && state == CKACKHI && dir == D_RD) - M_AXIS_TVALID <= 1'b1; - else if (M_AXIS_TREADY) - M_AXIS_TVALID <= 1'b0; - // }}} - - // M_AXIS_TDATA, M_AXIS_TLAST - // {{{ - always @(posedge S_AXI_ACLK) - if (OPT_LOWPOWER && !S_AXI_ARESETN) - begin - M_AXIS_TDATA <= 0; - M_AXIS_TLAST <= 0; - end else if (!M_AXIS_TVALID || M_AXIS_TREADY) - begin - M_AXIS_TDATA <= sreg; - M_AXIS_TLAST <= last_byte; - - if (OPT_LOWPOWER && (!i_ckedge || o_stretch - || state != CKACKHI || dir != D_RD || ck_sda)) - begin - M_AXIS_TDATA <= 0; - M_AXIS_TLAST <= 0; - end - end - // }}} - - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL -`ifdef I2CCPU -`define ASSUME assert -`else -`define ASSUME assume -`endif - // Local declarations - // {{{ - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge S_AXI_ACLK) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - `ASSUME(!S_AXI_ARESETN); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Input properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) if (!f_past_valid) assume({ i_scl, i_sda } == 2'b11); - always @(*) if (!o_scl) assume(!i_scl); - always @(*) if (!o_sda) assume(!i_sda); - - always @(posedge S_AXI_ACLK) - if (f_past_valid && $past(S_AXI_ARESETN && i_ckedge && o_stretch)) - `ASSUME(i_ckedge); - - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN || !$past(S_AXI_ARESETN)) - begin - if (S_AXI_ARESETN && !$past(S_AXI_ARESETN)) - `ASSUME(!i_ckedge); - end else case({ lst_scl, ck_scl, q_scl, i_scl }) - 4'b0000: begin end - 4'b0001: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b0011: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b0111: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b1111: begin end - 4'b1110: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b1100: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b1000: assume($past(i_ckedge && o_stretch) || !i_ckedge); - default: assume(0); - endcase - - always @(posedge S_AXI_ACLK) - case({ lst_sda, ck_sda, q_sda, i_sda }) - 4'b0000: begin end - 4'b0001: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b0011: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b0111: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b1111: begin end - 4'b1110: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b1100: assume($past(i_ckedge && o_stretch) || !i_ckedge); - 4'b1000: assume($past(i_ckedge && o_stretch) || !i_ckedge); - default: assume(0); - endcase - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge S_AXI_ACLK) - if (!f_past_valid) - begin - end else if (!$past(S_AXI_ARESETN)) - begin - `ASSUME(!S_AXIS_TVALID); - - assert(!M_AXIS_TVALID); - - if (OPT_LOWPOWER) - begin - assert(M_AXIS_TDATA == 0); - assert(M_AXIS_TLAST == 0); - end - end else begin - if ($past(o_abort)) - `ASSUME(!S_AXIS_TVALID); - else if ($past(S_AXIS_TVALID && !S_AXIS_TREADY)) - begin - `ASSUME(S_AXIS_TVALID); - `ASSUME($stable(S_AXIS_TDATA)); - end - - if ($past(M_AXIS_TVALID && !M_AXIS_TREADY)) - begin - assert(M_AXIS_TVALID); - assert($stable(M_AXIS_TDATA)); - assert($stable(M_AXIS_TLAST)); - end - - if (OPT_LOWPOWER && !M_AXIS_TVALID) - begin - assert(M_AXIS_TDATA == 0); - assert(M_AXIS_TLAST == 0); - end - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Internal consistency checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (S_AXI_ARESETN && (state != IDLE_STOPPED) && (state != IDLE_ACTIVE)) - assert(!S_AXIS_TREADY); - - always @(*) - if (S_AXI_ARESETN) case(state) - IDLE_STOPPED: begin - // {{{ - assert(o_scl); - assert(o_sda); - end - // }}} - START: begin - // {{{ - assert( o_scl); - assert(!o_sda); - assert(nbits == 7 || nbits == 0); - end - // }}} - IDLE_ACTIVE: begin - // {{{ - assert(!o_sda); - assert(!o_scl); - assert(nbits == 0); - end - // }}} - STOP: begin - // {{{ - // o_sda == 0 - // o_scl == 1 on entry - assert( o_scl); - assert(!o_sda); - end - // }}} - REPEAT_START: begin - // {{{ - assert(!o_scl); - assert( o_sda); - assert(nbits == 7 || nbits == 0); - end - // }}} - REPEAT_START2: begin - // {{{ - assert(o_sda && o_scl); - assert(nbits == 7 || nbits == 0); - end - // }}} - // - DATA: begin - // {{{ - assert(!o_scl); - if (dir == D_RD) - assert(o_sda || nbits == 7); - end - // }}} - CLOCK: begin - // {{{ - if (dir == D_RD) - assert(o_sda); - else - assert(o_sda == sreg[7]); - end - // }}} - ACK: begin - // {{{ - assert(!o_scl); - assert(nbits == 0); - end - // }}} - CKACKLO: begin - // {{{ - assert(!o_scl); - assert(o_sda == ((dir == D_WR) || !will_ack)); - assert(nbits == 0); - end - // }}} - CKACKHI: begin - // {{{ - assert(o_scl); - assert(o_sda == ((dir == D_WR) || !will_ack)); - assert(nbits == 0); - end - // }}} - RXNAK: begin - // {{{ - assert(!o_scl && !o_sda); - assert(nbits == 0); - end - // }}} - ABORT: begin - // {{{ - // COLLISION!!! - assert(o_scl); - assert(o_sda); - end - // }}} - default: begin - // {{{ - assert(0); - end - // }}} - endcase - - always @(posedge S_AXI_ACLK) - if (S_AXI_ARESETN && $past(S_AXI_ARESETN) && $past(o_scl)) - begin - if ($past(!ck_scl) && !$past(S_AXIS_TREADY) - && ($past(ck_sda == o_sda))) - begin - // HALT - assert($stable(o_scl)); - if ($past(watchdog_timeout && state == ABORT && o_sda && i_ckedge)) - begin - assert(state == STOP && !o_sda); - end else begin - assert($stable(state) || state == ABORT); - assert($stable(o_sda)); - end - end - end - - always @(*) - if (S_AXI_ARESETN && o_abort) - assert(state == RXNAK || state == ABORT); - - always @(posedge S_AXI_ACLK) - if (S_AXI_ARESETN && $past(S_AXI_ARESETN)) - begin - if ($rose(state == ABORT)) - begin - assert(o_abort); // Collision - end else if ($rose(state == RXNAK)) - begin - assert(o_abort); // Failed NAK - end else - assert(!o_abort); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - reg [3:0] cvr_state, cvr_send; - (* anyconst *) reg nvr_abort; - - always @(*) - if (nvr_abort) - assume(!o_abort && state != ABORT && state != RXNAK); - - // *LONG* Cover sequence - // {{{ - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN || state == ABORT || o_abort) - cvr_state <= 0; - else if (S_AXIS_TVALID && S_AXIS_TREADY) - begin - case(cvr_state) - 4'h0: cvr_state = (S_AXIS_TDATA[10:8] == CMD_START) ? 4'h1 : 0; - 4'h1: cvr_state = (S_AXIS_TDATA=={CMD_SEND, 8'h8a })? 4'h2 : 0; - 4'h2: cvr_state = (S_AXIS_TDATA=={CMD_SEND, 8'hd1 })? 4'h3 : 0; - 4'h3: cvr_state = (S_AXIS_TDATA[10:8] == CMD_START) ? 4'h4 : 0; - 4'h4: cvr_state = (S_AXIS_TDATA[10:8] == CMD_SEND) ? 4'h5 : 0; - 4'h5: cvr_state = (S_AXIS_TDATA[10:8] == CMD_STOP) ? 4'h6 : 0; - endcase - end - - always @(*) - if (S_AXI_ARESETN && !o_abort) - begin - case(cvr_state) - 4'h0: begin - cover(S_AXIS_TREADY); // Step 1 - end - 4'h1: begin - cover(S_AXIS_TREADY); // Step 5 - assert(nbits == 0); - end - 4'h2: begin - // Measure 5-6 cycles per clock - cover(S_AXIS_TREADY); // Step 57 - end - 4'h3: begin - // Measure 5-6 cycles per clock - cover(S_AXIS_TREADY); // Step 101 - end - 4'h4: begin - cover(S_AXIS_TREADY && nvr_abort); // Step 115 - end - 4'h5: cover(S_AXIS_TREADY); // Step 161 - 4'h6: cover(S_AXIS_TREADY); - default: assert(0); - endcase - end - // }}} - - // Read check - // {{{ - always @(*) - if (S_AXI_ARESETN && !o_abort) - begin - if (M_AXIS_TVALID && state == IDLE_STOPPED) - begin - cover( M_AXIS_TLAST && M_AXIS_TDATA == 8'h9f); // S 54 - cover(!M_AXIS_TLAST && M_AXIS_TDATA == 8'ha5); // S 54 - end - end - // }}} - - // cvr_send - // {{{ - always @(posedge S_AXI_ACLK) - if (!S_AXI_ARESETN || o_abort || state == ABORT) - cvr_send <= 0; - else case(cvr_send) - 4'h0: if (S_AXIS_TVALID && S_AXIS_TREADY - && S_AXIS_TDATA[10:8] == CMD_SEND) - begin - cvr_send <= 1; - end else if (S_AXIS_TVALID && S_AXIS_TREADY - && S_AXIS_TDATA[10:8] == CMD_START) - begin - cvr_send <= 4'h8; - end - 4'h1: if (state == DATA) - begin - cvr_send <= 2; - end - 4'h2: if (state == IDLE_ACTIVE) - begin - cvr_send <= 3; - end - 4'h3: if (state == IDLE_STOPPED) - begin - cvr_send <= 4'h4; - end - 4'h8: if (state == IDLE_ACTIVE) - begin - cvr_send <= 4'h9; - end - 4'h9: if (state == STOP) - begin - cvr_send <= 4'ha; - end else if (state == REPEAT_START) - begin - cvr_send <= 4'hc; - end - 4'ha: if (state == IDLE_STOPPED) - begin - cvr_send <= 4'hb; - end - 4'hc: if (state == IDLE_STOPPED) - begin - cvr_send <= 4'hd; - end - default: begin end - endcase - - always @(*) - if (S_AXI_ARESETN) - begin - cover(cvr_send == 4'h1); // Step 3 - cover(cvr_send == 4'h2); // Step 5 - cover(cvr_send == 4'h3); // Step 50 - cover(cvr_send == 4'h4); // Step 54 - // - cover(cvr_send == 4'h8); // Step 3 - cover(cvr_send == 4'h9); // Step 5 - cover(cvr_send == 4'ha); // Step 7 - cover(cvr_send == 4'hb); // Step 9 - - cover(cvr_send == 4'hc); // Step 7 - cover(cvr_send == 4'hd); // Step 17 - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Assume no collisions - // {{{ - always @(*) - if ((dir == D_WR && state == CLOCK)||(dir == D_RD && state == CKACKHI)) - assume(i_sda == o_sda); - else if (state == REPEAT_START || state == REPEAT_START2 || state == START) - assume((i_scl == o_scl)&&(i_sda == o_sda)); - // }}} - - // No one else adjusts our clock - // {{{ - always @(posedge S_AXI_ACLK) - if ($past(o_scl && i_scl) && o_scl) - assume(i_scl); - // }}} - - // No bit adjustments mid clock cycle? What about start & stop? - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wbi2c/lli2cm.v b/delete_later/rtl/wbi2c/lli2cm.v deleted file mode 100644 index 2d39998..0000000 --- a/delete_later/rtl/wbi2c/lli2cm.v +++ /dev/null @@ -1,352 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: lli2cm.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is a lower level I2C driver for a master I2C byte-wise -// interface. This particular interface is designed to handle -// all byte level ineraction with the actual port. The external interface -// to this module is something akin to wishbone, although without the -// address register. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module lli2cm #( - // {{{ - parameter [5:0] TICKBITS = 20, - parameter [(TICKBITS-1):0] CLOCKS_PER_TICK = 20'd1000, - parameter [0:0] PROGRAMMABLE_RATE= 1'b1 - // }}} - ) ( - // {{{ - input wire i_clk, - // - input wire [(TICKBITS-1):0] i_clocks, - // - input wire i_cyc, i_stb, i_we, - input wire [7:0] i_data, - output reg o_ack, o_busy, o_err, - output reg [7:0] o_data, - input wire i_scl, i_sda, - output reg o_scl, o_sda, - output wire [31:0] o_dbg - // }}} - ); - - // Local declarations - // {{{ - localparam [3:0] I2CMIDLE = 4'h0, - I2CMSTART = 4'h1, - I2CMBIT_SET = 4'h2, - I2CMBIT_POSEDGE = 4'h3, - I2CMBIT_NEGEDGE = 4'h4, - I2CMBIT_CLR = 4'h5, - I2CMACK_SET = 4'h6, - I2CMACK_POSEDGE = 4'h7, - I2CMACK_NEGEDGE = 4'h8, - I2CMACK_CLR = 4'h9, - I2CMRESTART = 4'ha, - I2CMRESTART_POSEDGE= 4'hb, - I2CMRESTART_NEGEDGE= 4'hc, - I2CMSTOP = 4'hd, - I2CMSTOPPD = 4'he, - I2CMFINAL = 4'hf; - - reg [(TICKBITS-1):0] clocks_per_tick; - - reg [3:0] state; - reg [(TICKBITS-1):0] clock; - reg zclk, r_cyc, r_err, r_we; - reg [2:0] nbits; - reg [7:0] r_data; - - reg q_scl, q_sda, ck_scl, ck_sda, lst_scl, lst_sda; - - reg start_bit, stop_bit, channel_busy; - reg watchdog_timeout; - reg [27:0] watchdog; - - always @(posedge i_clk) - clocks_per_tick <= (PROGRAMMABLE_RATE) ? i_clocks - : CLOCKS_PER_TICK; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Synchronize any asynchronous inputs - // {{{ - initial q_scl = 1'b1; - initial q_sda = 1'b1; - initial ck_scl = 1'b1; - initial ck_sda = 1'b1; - initial lst_scl = 1'b1; - initial lst_sda = 1'b1; - always @(posedge i_clk) - begin - q_scl <= i_scl; - ck_scl <= q_scl; - lst_scl <= ck_scl; - - q_sda <= i_sda; - ck_sda <= q_sda; - lst_sda <= ck_sda; - end - // }}} - - // start_bit, stop_bit, channel_busy - // {{{ - initial start_bit = 1'b0; - initial stop_bit = 1'b0; - initial channel_busy = 1'b0; - always @(posedge i_clk) - begin - start_bit <= (ck_scl)&&(lst_scl)&&(!ck_sda)&&( lst_sda); - stop_bit <= (ck_scl)&&(lst_scl)&&( ck_sda)&&(!lst_sda); - if ((!ck_scl)||(!ck_sda)) - channel_busy <= 1'b1; - else if (stop_bit) - channel_busy <= 1'b0; - end - // }}} - - // Watchdog, and watchdog_timeout - // {{{ - always @(posedge i_clk) - begin - if (!channel_busy) - watchdog <= 0; - else if (!(&watchdog)) - watchdog <= watchdog + 1'b1; - watchdog_timeout <= (&watchdog); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Generate a clock we can use - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial clock = CLOCKS_PER_TICK; - initial zclk = 1'b1; - always @(posedge i_clk) - if (state == I2CMIDLE) - begin - if (watchdog_timeout) - begin - clock <= 0; - zclk <= 1'b1; - end else if (((i_stb)&&(!o_busy))||(channel_busy)) - begin - clock <= clocks_per_tick; - zclk <= 1'b0; - end else begin - clock <= 0; - zclk <= 1'b1; - end - end else if ((clock == 0)||((o_scl)&&(!ck_scl))) - begin - clock <= clocks_per_tick; - zclk <= 1'b0; - end else begin - clock <= clock - 1'b1; - zclk <= (clock == 1); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Massive state machine - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial state = I2CMIDLE; - initial o_ack = 1'b0; - initial o_busy = 1'b0; - initial r_cyc = 1'b1; - initial nbits = 3'h0; - initial r_we = 1'b0; - initial r_data = 8'h0; - initial o_scl = 1'b1; - initial o_sda = 1'b1; - always @(posedge i_clk) - begin - o_ack <= 1'b0; - o_err <= 1'b0; - o_busy <= 1'b1; - r_cyc <= (r_cyc) && (i_cyc); - if (zclk) case(state) - I2CMIDLE: begin - r_err <= 1'b0; - nbits <= 3'h0; - r_cyc <= i_cyc; - o_sda <= 1'b1; - o_scl <= 1'b1; - if ((i_stb)&&(!o_busy)) begin - r_data <= i_data; - r_we <= i_we; - nbits <= 0; - state <= I2CMSTART; - o_sda <= 1'b0; - end else if (watchdog_timeout) - begin - o_sda <= 1'b0; - o_scl <= 1'b0; - state <= I2CMSTOP; - end else - o_busy <= 1'b0; - end - I2CMSTART: begin - state <= I2CMBIT_SET; - o_sda <= 1'b0; - o_scl <= 1'b0; - end - I2CMBIT_SET: begin - o_sda <= (r_we)?r_data[7] : 1'b1; - if (r_we) - r_data <= { r_data[6:0], ck_sda }; - nbits <= nbits - 1'b1; - state <= I2CMBIT_POSEDGE; - end - I2CMBIT_POSEDGE: begin - if (!r_we) - r_data <= { r_data[6:0], ck_sda }; - o_scl <= 1'b1; - r_err <= (r_err)||((r_we)&&(o_sda != ck_sda)); - state <= I2CMBIT_NEGEDGE; - end - I2CMBIT_NEGEDGE: begin - if (ck_scl) - begin - o_scl <= 1'b0; - state <= I2CMBIT_CLR; - end - end - I2CMBIT_CLR: begin - if (nbits != 3'h0) - state <= I2CMBIT_SET; - else if ((!r_we)&&((!i_stb)||(!r_cyc))) - state <= I2CMSTOP; - else - state <= I2CMACK_SET; - end - I2CMACK_SET: begin - o_sda <= (r_we) ? 1'b1 : 1'b0; - state <= I2CMACK_POSEDGE; - end - I2CMACK_POSEDGE: begin - o_scl <= 1'b1; - state <= I2CMACK_NEGEDGE; - end - I2CMACK_NEGEDGE: begin - if (ck_scl) - begin - o_scl <= 1'b0; - r_err <= (r_err)||((r_we)&&(ck_sda)); - state <= I2CMACK_CLR; - end - end - I2CMACK_CLR: begin - o_err <= r_err; - o_data <= r_data; - o_ack <= 1'b1; - o_sda <= 1'b0; - o_scl <= 1'b0; - if (r_err) - state <= I2CMSTOP; - else if ((i_stb)&&(r_cyc)&&(i_cyc)) - begin - o_busy <= 1'b0; - r_we <= i_we; - r_data <= i_data; - // if (r_we != i_we) - // state <= I2CMRESTART; - // else - state <= I2CMSTART; - nbits <= 0; - end else if ((i_cyc)&&(i_stb)&&(!r_cyc)) - state <= I2CMRESTART; - else // if (!i_cyc) - state <= I2CMSTOP; - end - I2CMRESTART: begin - o_sda <= 1'b1; - state <= I2CMRESTART_POSEDGE; - end - I2CMRESTART_POSEDGE: begin - o_sda <= 1'b1; - o_scl <= 1'b1; - state <= I2CMRESTART_NEGEDGE; - end - I2CMRESTART_NEGEDGE: begin - o_sda <= 1'b1; - o_scl <= 1'b1; - if (ck_scl) - begin - state <= I2CMSTART; - o_sda <= 1'b0; - end - end - I2CMSTOP: begin - o_scl <= 1'b0; - o_sda <= 1'b0; - if ((ck_scl == 1'b0)&&(ck_sda == 1'b0)) - begin - o_scl <= 1'b1; - o_sda <= 1'b0; // (No change) - state <= I2CMSTOPPD; - end - end - I2CMSTOPPD: begin - o_scl <= 1'b1; - o_sda <= 1'b0; - if ((ck_scl)&&(!ck_sda)) - begin - o_sda <= 1'b1; - state <= I2CMFINAL; - end - end - default: begin - o_scl <= 1'b1; - o_sda <= 1'b1; - if (!channel_busy) - state <= I2CMIDLE; - else if (watchdog_timeout) - state <= I2CMSTOP; - end - endcase - end - // }}} - - assign o_dbg = { i_cyc, i_cyc, i_stb, 13'h00, - 1'b0, watchdog_timeout, o_ack, o_busy, - o_err, stop_bit, start_bit, channel_busy, - state, - ck_scl, ck_sda, o_scl, o_sda }; - -endmodule diff --git a/delete_later/rtl/wbi2c/wbi2ccpu.v b/delete_later/rtl/wbi2c/wbi2ccpu.v deleted file mode 100644 index c452c12..0000000 --- a/delete_later/rtl/wbi2c/wbi2ccpu.v +++ /dev/null @@ -1,1079 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbi2ccpu.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: -// -// Registers -// {{{ -// 0. Stop control -// [31:28]: half_insn. If the half_valid flag is true, there -// is another half to this instruction contained in these -// bits. -// [27:24]: Unused/Reserved -// [23]: r_wait - True if the controller is waiting on a -// synchronization signal before issuing its next command -// [22]: Soft halt request (halt on STOP or o.w. inactive) -// Writes that set the soft halt bit will cause the I2C -// port to halt once the current command is complete. -// [21]: r_aborted - a user instruction was aborted. Further -// user (bus) instructions will be ignored until this -// bit is cleared by writing to it. -// [20]: Err bit -// True if an instruction read has returned a bus error. -// The error may be cleared by writing a '1' to this bit, -// or by writing to the address register. -// [19]: Hard halt request (halt in any state) -// Writes that set this bit will cause the controller -// to immediately halt in whatever state the controller -// is in. Any currently issued command will run to -// completion. -// Reads return 1'b1 if the controller is not running a -// script from memory. This is almost the same as if it -// were halted, but not quite, since this bit will not -// clear following an override request. -// [18]: insn_valid - An instruction has been read and queued that -// hasn't been issued. An attempt to write to the override -// register might override this instruction -// [17]: half_valid - a half instruction is waiting to be issued. -// [16]: imm_cycle - the next word the controller receives will -// be an immediate byte -// [15:14]: Currently output/commanded SCL, SDA respectivvely -// [13:12]: Input/incoming SCL, SDA respectively -// [11: 0]: Returns the currently running instruction. -// 1. Override -// Writes instructions to bits [7:0] of this port -// bit [9] will be true on read if a valid byte can be read -// This bit will be cleared on any write to ADR_OVERRIDE -// bit [8] will be true on read if TLAST is set on a valid request -// bit [7:0] on read will return the last data read from the device -// 2. Address control -// Writes set the address, unstop the CPU, and cause a jump to that -// address. Writes will also set the abort address and -// the jump target, so that on either an abort abort or a -// the command restarts right where the CPU set it up to -// start. -// Reads return the current address -// 3. Clock control -// (May not be required) -// }}} -// -// Instruction set: -// {{{ -// 4'h,4'h Two instructions per byte -// -// 4'h0 NOP -// 4'h1 START -// 4'h2 STOP -// 4'h3 SEND -// 4'h4 RXK -// 4'h5 RXN // RX byte, NAK result -// 4'h6 RXLK // Cn't include STOP, bc we might want rptd strt -// 4'h7 RXLN // ditto -// 4'h8 WAIT -// 4'h9 HALT -// 4'ha ABORT -// 4'hb TARGET -// 4'hc JUMP -// 4'hd CHANNEL -// 4'he (Undef/Illegal Insn) -// 4'hf (Undef/Illegal Insn) -// }}} -// -// Dependencies: -// dblfetch.v From the ZipCPU repo, zipcore branch, rtl/core directory -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbi2ccpu #( - // {{{ - parameter ADDRESS_WIDTH = 29, - parameter DATA_WIDTH = 32, - parameter I2C_WIDTH = 8, - parameter AXIS_ID_WIDTH = 2, - parameter [((AXIS_ID_WIDTH>0)?AXIS_ID_WIDTH:1)-1:0] DEF_CHANNEL = 0, - localparam AW = ADDRESS_WIDTH, - localparam DW = DATA_WIDTH, - localparam RW = I2C_WIDTH, - localparam BAW = AW + $clog2(DATA_WIDTH/8), // Byte addr w - parameter [BAW-1:0] RESET_ADDRESS = 0, - parameter [0:0] OPT_START_HALTED = (RESET_ADDRESS == 0), - // If OPT_MANUAL is set, the override register may be used - // to take direct and manual control over the I2C ports, and - // so to directly control the wires without any logic in the - // way. - parameter [0:0] OPT_MANUAL = 1'b1, - parameter OPT_WATCHDOG = 0, -`ifdef FORMAL - parameter [11:0] DEF_CKCOUNT = 2, -`else - parameter [11:0] DEF_CKCOUNT = -1, -`endif - parameter [0:0] OPT_LOWPOWER = 1'b0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Bus slave interface - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [1:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output wire [31:0] o_wb_data, - // }}} - // Bus master interface - // {{{ - output wire o_pf_cyc, o_pf_stb, o_pf_we, - output wire [AW-1:0] o_pf_addr, - output wire [DW-1:0] o_pf_data, - output wire [DW/8-1:0] o_pf_sel, - input wire i_pf_stall, - input wire i_pf_ack, - input wire i_pf_err, - input wire [DW-1:0] i_pf_data, - // }}} - // I2C interfacce - // {{{ - input wire i_i2c_sda, i_i2c_scl, - output wire o_i2c_sda, o_i2c_scl, - // }}} - // Outgoing stream interface - // {{{ - output wire M_AXIS_TVALID, - input wire M_AXIS_TREADY, - output wire [RW-1:0] M_AXIS_TDATA, - output wire M_AXIS_TLAST, - output wire [((AXIS_ID_WIDTH > 0) ? (AXIS_ID_WIDTH-1):0):0] - M_AXIS_TID, - // OPT output wire M_AXIS_TABORT, - // }}} - input wire i_sync_signal, - output wire [31:0] o_debug - // }}} - ); - - // Local declarations - // {{{ - // Addresses - // {{{ - localparam [1:0] ADR_CONTROL = 2'b00, - ADR_OVERRIDE= 2'b01, - ADR_ADDRESS = 2'b10, - ADR_CKCOUNT = 2'b11; - // }}} - - // Command register bit enumeration(s) - // {{{ - localparam // IMMCYCLE_BIT = 16, - // HALFVLD_BIT = 17, - // INSNVLD_BIT = 18, - HALT_BIT = 19, - ERR_BIT = 20, - ABORT_BIT = 21, - SOFTHALT_BIT = 22; - // WAIT_BIT = 23; - // }}} - localparam OVW_VALID = 9; - localparam MANUAL_BIT = 11; - - // Instruction set / Commands - // {{{ - localparam [3:0] CMD_NOOP = 4'h0, - // CMD_START = 4'h1, - CMD_STOP = 4'h2, - CMD_SEND = 4'h3, - CMD_RXK = 4'h4, - CMD_RXN = 4'h5, - CMD_RXLK = 4'h6, - CMD_RXLN = 4'h7, - CMD_WAIT = 4'h8, - CMD_HALT = 4'h9, - CMD_ABORT = 4'ha, - CMD_TARGET= 4'hb, - CMD_JUMP = 4'hc, - CMD_CHANNEL = 4'hd; - // }}} - - wire cpu_reset, cpu_clear_cache; - reg cpu_new_pc; - reg [BAW-1:0] pf_jump_addr; - wire pf_valid; - wire pf_ready; - wire [7:0] pf_insn; - wire [BAW-1:0] pf_insn_addr; - wire pf_illegal; - - reg half_valid, imm_cycle; - - reg next_valid; - reg [7:0] next_insn; - - wire insn_ready, half_ready, i2c_abort; - reg insn_valid; - reg [11:0] insn; - reg [3:0] half_insn; - reg i2c_ckedge; - wire i2c_stretch; - reg [11:0] i2c_ckcount, ckcount; - reg [BAW-1:0] abort_address, jump_target; - reg r_wait, soft_halt_request, r_halted, r_err, - r_aborted; - wire r_manual, r_sda, r_scl; - wire w_stopped, w_sda, w_scl; - - wire bus_read, bus_write, bus_override, bus_manual, - ovw_ready, bus_jump; - wire [1:0] bus_write_addr, bus_read_addr; - wire [31:0] bus_write_data; - wire [3:0] bus_write_strb; - reg [31:0] bus_read_data; - - wire s_tvalid, s_tready; - reg [9:0] ovw_data; - wire [31:0] w_control; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus (read) handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign bus_write = i_wb_stb && i_wb_we && !o_wb_stall; - assign bus_write_addr = i_wb_addr; - assign bus_write_data = i_wb_data; - assign bus_write_strb = i_wb_sel; - - assign bus_read = i_wb_stb && !i_wb_we && !o_wb_stall; - assign bus_read_addr = i_wb_addr; - - assign o_wb_stall = 1'b0; // (i_wb_we && i_wb_addr == BUS_OVERRIDE && !ovw_ready) - - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_ack <= 1'b0; - else - o_wb_ack <= i_wb_stb && !o_wb_stall; - - // Read handling - // {{{ - assign w_control = { - half_insn, 3'h0, r_manual, - // - r_wait, soft_halt_request, - r_aborted, r_err, r_halted, - insn_valid, half_valid, imm_cycle, - // - o_i2c_scl, o_i2c_sda, - i_i2c_scl, i_i2c_sda, - // - insn // 12 bits - }; - - always @(posedge i_clk) - if (OPT_LOWPOWER && i_reset) - bus_read_data <= 0; - else if (bus_read) - begin - bus_read_data <= 0; - case(bus_read_addr) - ADR_CONTROL: bus_read_data <= w_control; - ADR_OVERRIDE: bus_read_data[15:0] <= { - r_scl, r_sda, i_i2c_scl, i_i2c_sda, - r_manual, r_aborted, ovw_data }; - ADR_ADDRESS: bus_read_data[BAW-1:0] <= pf_insn_addr; - ADR_CKCOUNT: bus_read_data[11:0] <= ckcount; - // default: bus_read_data <= 0; - endcase - - // if(OPT_LOWPOWER && !bus_read) - // bus_read_data <= 0; - end else if (OPT_LOWPOWER) - bus_read_data <= 0; - - assign o_wb_data = bus_read_data; - // }}} - - assign bus_override = r_halted && !r_aborted && bus_write - && bus_write_addr == ADR_OVERRIDE && bus_write_strb[0]; - assign bus_manual = OPT_MANUAL && bus_write - && bus_write_addr == ADR_OVERRIDE - && bus_write_data[MANUAL_BIT] - && bus_write_strb[MANUAL_BIT/8]; - assign bus_jump = bus_write && bus_write_addr == ADR_ADDRESS - && (&bus_write_strb) && r_halted && !r_aborted; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Instruction fetch - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign cpu_reset = r_halted; - assign cpu_clear_cache = 1'b0; - assign o_pf_sel = -1; - -`ifndef FORMAL - dblfetch #( - // {{{ - .ADDRESS_WIDTH(BAW), - .DATA_WIDTH(DW), - .INSN_WIDTH(8), - .OPT_LITTLE_ENDIAN(1'b0) - // }}} - ) u_fetch ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || cpu_reset), - // - .i_new_pc(cpu_new_pc), .i_clear_cache(cpu_clear_cache), - .i_ready(pf_ready), .i_pc(pf_jump_addr), - .o_valid(pf_valid), .o_illegal(pf_illegal), - .o_insn(pf_insn), .o_pc(pf_insn_addr), - // - .o_wb_cyc(o_pf_cyc), .o_wb_stb(o_pf_stb), .o_wb_we(o_pf_we), - .o_wb_addr(o_pf_addr), .o_wb_data(o_pf_data), - .i_wb_stall(i_pf_stall), .i_wb_ack(i_pf_ack), - .i_wb_err(i_pf_err), .i_wb_data(i_pf_data) - // }}} - ); -`endif - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Decode pipeline, and non-i2c handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // next_valid, next_insn - // {{{ - always @(*) - begin - if (r_halted) - begin - next_valid = bus_override && ovw_ready; - if (bus_manual) - next_valid = 1'b0; - next_insn = bus_write_data[7:0]; - end else begin - next_valid = pf_valid && pf_ready; - if (insn_valid && insn[11:8] == CMD_HALT) - next_valid = 1'b0; - next_insn = pf_insn; - end - - if (!imm_cycle && next_insn[7:4] == CMD_NOOP) - next_insn = { next_insn[3:0], CMD_NOOP }; - - if (bus_jump) - next_valid = 1'b0; - end -`ifdef FORMAL - always @(*) - if (insn_valid && !s_tready) - begin - assert(!next_valid); - assert(!pf_ready); - assert(!ovw_ready); - end - - always @(*) - if (!i_reset && !insn_valid && !r_manual) - begin - assert(pf_ready == (!r_halted && !r_wait && !cpu_new_pc && !r_manual)); - assert(ovw_ready); - end -`endif - // }}} - - // half_valid - // {{{ - initial half_valid = 1'b0; - always @(posedge i_clk) - if (i_reset || i2c_abort || r_manual || bus_manual) - half_valid <= 1'b0; - else if (!imm_cycle && next_valid) - begin - half_valid <= 1'b0; - - if (next_insn[7:4] != CMD_SEND - && next_insn[7:4] != CMD_CHANNEL - && next_insn[3:0] != CMD_NOOP - && next_insn[7:4] != CMD_HALT) - half_valid <= 1'b1; - end else if (half_ready) - half_valid <= 1'b0; -`ifdef FORMAL - always @(posedge i_clk) - if (!i_reset && $past(!i_reset && !i2c_abort && next_valid && !imm_cycle)) - begin - if (half_insn[3:0] == CMD_NOOP) - assert(!half_valid); - end -`endif - // }}} - - // imm_cycle - // {{{ - initial imm_cycle = 1'b0; - always @(posedge i_clk) - if (i_reset || cpu_new_pc || cpu_clear_cache || i2c_abort) - imm_cycle <= 1'b0; - else if (!imm_cycle && ( - (next_valid && (next_insn[7:4]== CMD_SEND - || next_insn[7:4]== CMD_CHANNEL)) - ||(half_valid && half_ready && (half_insn[3:0] == CMD_SEND - ||half_insn[3:0] == CMD_CHANNEL)))) - imm_cycle <= 1'b1; - else begin - if (bus_jump) - imm_cycle <= 1'b0; - if ((pf_valid && pf_ready) || (bus_override && ovw_ready)) - imm_cycle <= 1'b0; - end -`ifdef FORMAL - always @(*) - if (!i_reset && imm_cycle) - assert(insn[11:8] == CMD_SEND || insn[11:8] == CMD_CHANNEL); -`endif - // }}} - - // cpu_new_pc, pf_jump_addr - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - cpu_new_pc <= !OPT_START_HALTED; - pf_jump_addr <= RESET_ADDRESS; - end else begin - - cpu_new_pc <= 1'b0; - if (cpu_new_pc || (pf_valid && pf_ready)) - pf_jump_addr <= pf_jump_addr + 1; - - // Jump instruction - // {{{ - if ((pf_valid && pf_ready && !imm_cycle - && pf_insn[7:4] == CMD_JUMP) - ||(half_valid && half_ready - && half_insn[3:0] == CMD_JUMP)) - begin - cpu_new_pc <= 1'b1; - pf_jump_addr <= jump_target; - end - // }}} - - // Abort an I2C command - // {{{ - if (i2c_abort) - begin - cpu_new_pc <= 1'b1; - pf_jump_addr <= abort_address; - end - // }}} - - // CPU commanded jump - // {{{ - if (bus_jump) - begin - cpu_new_pc <= 1'b1; - pf_jump_addr <= bus_write_data[BAW-1:0]; - end - // }}} - end - // }}} - - assign pf_ready = !w_stopped && !half_valid - && (!insn_valid || s_tready) && !cpu_new_pc; - assign half_ready = s_tready; - - assign ovw_ready = !half_valid && (!insn_valid || s_tready); - - // insn_valid - // {{{ - initial insn_valid = 1'b0; - always @(posedge i_clk) - if (i_reset || i2c_abort) - insn_valid <= 1'b0; - else if (OPT_MANUAL && (r_manual || bus_manual)) - insn_valid <= 1'b0; - else if (next_valid) - insn_valid <= imm_cycle || (next_insn[7:4] != CMD_SEND - && next_insn[7:4] != CMD_CHANNEL); - else if ((!half_valid || half_insn == CMD_SEND || half_insn == CMD_CHANNEL) && s_tready) - insn_valid <= 1'b0; - -`ifdef FORMAL - always @(posedge i_clk) - if (!i_reset && half_valid) - begin - assert(insn_valid); - assert(insn[11:8] != CMD_HALT && insn[11:8] != CMD_SEND - && insn[11:8] != CMD_CHANNEL); - assert(!imm_cycle); - end -`endif - // }}} - - // insn - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - half_insn <= CMD_NOOP; - insn <= 0; - // }}} - end else if (next_valid) - begin - // {{{ - if (imm_cycle) - begin - insn[7:0] <= next_insn; - half_insn <= CMD_NOOP; - end else - { insn[11:8], half_insn } <= next_insn; - // }}} - end else if (!imm_cycle && s_tready) - { insn[11:8], half_insn } <= { half_insn, CMD_NOOP }; - -`ifdef FORMAL - always @(*) - if (!i_reset && imm_cycle) - assert(!half_valid); -`endif - // }}} - - // ckcount - // {{{ - always @(posedge i_clk) - if (i_reset) - ckcount <= DEF_CKCOUNT; - else if (bus_write && bus_write_addr == ADR_CKCOUNT && (&bus_write_strb)) - ckcount <= bus_write_data[11:0]; - // }}} - - // i2c_ckedge - // {{{ - always @(posedge i_clk) - if (i_reset) - begin - i2c_ckedge <= 0; - i2c_ckcount <= DEF_CKCOUNT; - end else if (!i2c_ckedge || !i2c_stretch) - begin - if (i2c_ckcount > 0) - i2c_ckcount <= i2c_ckcount - 1; - else - i2c_ckcount <= ckcount; - - if (i2c_ckedge) - begin - i2c_ckedge <= (ckcount == 0); - end else - i2c_ckedge <= (i2c_ckcount <= 1); - end -`ifdef FORMAL - always @(*) - if (!i_reset) - assert(i2c_ckedge == (i2c_ckcount == 0)); - -`ifdef COVER - (* anyconst *) reg f_cvrspeed; - reg cvr_active; - - initial cvr_active <= 0; - always @(posedge i_clk) - if (insn_valid) - cvr_active <= 1; - - always @(*) - assume(f_cvrspeed); - - always @(posedge i_clk) - if (cvr_active && f_cvrspeed) - assume(ckcount == 1); -`endif -`endif - // }}} - - // abort_address - // {{{ - always @(posedge i_clk) - if (i_reset) - abort_address <= RESET_ADDRESS; - else if (bus_jump) - abort_address <= bus_write_data[BAW-1:0]; - else if (pf_valid && pf_ready && !imm_cycle && pf_insn[7:4]== CMD_ABORT) - // || pf_insn == { CMD_START, CMD_SEND }) - abort_address <= pf_insn_addr + 1; - // }}} - - // jump_target - // {{{ - always @(posedge i_clk) - if (i_reset) - jump_target <= RESET_ADDRESS; - else if (bus_jump) - jump_target <= bus_write_data[BAW-1:0]; - else if (pf_valid && pf_ready && !imm_cycle - && pf_insn[7:4] == CMD_TARGET) - jump_target <= pf_insn_addr + 1; - // }}} - - // r_wait - // {{{ - always @(posedge i_clk) - if (i_reset) - r_wait <= 1'b0; - else if (r_halted || i_sync_signal) - r_wait <= 1'b0; - else begin - if (insn_valid && insn[11:8] == CMD_WAIT) - r_wait <= 1'b1; - if (bus_jump) - r_wait <= 1'b0; - end - // }}} - - // soft_halt_request - // {{{ - always @(posedge i_clk) - if (i_reset || r_halted) - soft_halt_request <= 1'b0; - else if (bus_write && bus_write_addr == ADR_CONTROL - && bus_write_data[SOFTHALT_BIT] - && bus_write_strb[SOFTHALT_BIT/8]) - soft_halt_request <= 1'b1; - // }}} - - // r_halted - // {{{ - always @(posedge i_clk) - if (i_reset) - r_halted <= OPT_START_HALTED; - else begin - if (insn_valid && s_tready && insn[11:8] == CMD_STOP - && soft_halt_request) - r_halted <= 1'b1; - if (soft_halt_request && i2c_abort) - r_halted <= 1'b1; - if (pf_valid && pf_ready && pf_illegal) - r_halted <= 1'b1; - if (insn_valid && s_tready && insn[11:8] == CMD_HALT) - r_halted <= 1'b1; - - if (bus_write) - begin - if (bus_write_addr == ADR_CONTROL - && bus_write_data[HALT_BIT] - && bus_write_strb[HALT_BIT/8]) - r_halted <= 1'b1; - if (bus_manual) - r_halted <= 1'b1; - if (bus_jump && r_halted) - r_halted <= 1'b0; - end - end - // }}} - - // r_aborted - // {{{ - always @(posedge i_clk) - if (i_reset) - r_aborted <= 1'b0; - else begin - if (i2c_abort && !r_halted) - r_aborted <= 1'b1; - - if (bus_write) - begin - if (bus_write_addr == ADR_CONTROL - && bus_write_data[ABORT_BIT] - && bus_write_strb[ABORT_BIT/8]) - r_aborted <= 1'b0; - if (bus_jump && r_halted) - r_aborted <= 1'b0; - end - end - // }}} - - // r_err - // {{{ - always @(posedge i_clk) - if (i_reset) - r_err <= 1'b0; - else begin - if (pf_valid && pf_ready && pf_illegal) - r_err <= 1'b1; - - if (bus_write) - begin - if (bus_write_addr == ADR_CONTROL && bus_write_data[ERR_BIT] - && bus_write_strb[ERR_BIT/8]) - r_err <= 1'b0; - if (bus_jump && r_halted) - r_err <= 1'b0; - end - end - // }}} - - // ovw_data - // {{{ - always @(posedge i_clk) - if (i_reset) - ovw_data <= 10'h00; - else if (!r_halted) - ovw_data[OVW_VALID] <= 1'b0; - else begin - if (M_AXIS_TVALID) - ovw_data <= { 1'b1, M_AXIS_TLAST, M_AXIS_TDATA }; - if (bus_jump) - ovw_data[OVW_VALID] <= 1'b0; - end -`ifdef FORMAL - always @(*) - if (!i_reset && !r_halted) - assert(ovw_data[OVW_VALID] == 1'b0); -`endif - // }}} - - // r_manual override, and r_scl, r_sda, manual override values - // {{{ - generate if (OPT_MANUAL) - begin : GEN_MANUAL - // {{{ - reg manual, scl, sda, o_scl, o_sda; - - initial { manual, scl, sda } = 3'b011; - always @(posedge i_clk) - if (i_reset) - begin - { manual, scl, sda } <= 3'b011; - end else if (bus_write && bus_write_addr == ADR_OVERRIDE - && bus_write_strb[MANUAL_BIT/8]) - begin - manual <= bus_write_data[MANUAL_BIT]; - if (!bus_write_data[MANUAL_BIT]) - { scl, sda } <= 2'b11; - else - { scl, sda } <= bus_write_data[15:14]; - end else if (bus_jump) - { manual, scl, sda } <= 3'b011; - - // o_i2c_[sda|scl], muxed based upon r_manual - // {{{ - initial { o_scl, o_sda } = 2'b11; - always @(posedge i_clk) - if (i_reset) - { o_scl, o_sda } <= 2'b11; - else if (r_manual) - { o_scl, o_sda } <= { r_scl, r_sda }; - else - { o_scl, o_sda } <= { w_scl, w_sda }; - - assign { o_i2c_scl, o_i2c_sda } = { o_scl, o_sda }; - // }}} - - assign { r_manual, r_scl, r_sda } = { manual, scl, sda }; - // }}} - end else begin : NO_MANUAL - // {{{ - assign { o_i2c_scl, o_i2c_sda } = { w_scl, w_sda }; - assign { r_manual, r_scl, r_sda } = { 1'b0, w_scl, w_sda }; - // }}} - end endgenerate - // }}} - - assign w_stopped = r_wait || r_halted; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // I2C Sub-module - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign s_tvalid = insn_valid && !insn[11] && !r_wait; - assign s_tready =((insn_ready || insn[11]) && !r_wait) || r_manual; - -`ifndef FORMAL - axisi2c #( - // {{{ - .OPT_WATCHDOG(OPT_WATCHDOG), - .OPT_LOWPOWER(OPT_LOWPOWER) - // }}} - ) u_axisi2c ( - // {{{ - .S_AXI_ACLK(i_clk), .S_AXI_ARESETN(!i_reset && !r_manual), - // - // Incoming instruction stream - // {{{ - .S_AXIS_TVALID(s_tvalid), .S_AXIS_TREADY(insn_ready), - .S_AXIS_TDATA(insn[10:0]), - // }}} - // Outgoing received data stream - // {{{ - .M_AXIS_TVALID(M_AXIS_TVALID), .M_AXIS_TREADY(M_AXIS_TREADY), - .M_AXIS_TDATA(M_AXIS_TDATA), - .M_AXIS_TLAST(M_AXIS_TLAST), - // }}} - // Control interface - // {{{ - .i_ckedge(i2c_ckedge), - .o_stretch(i2c_stretch), - .o_abort(i2c_abort), - // }}} - .i_scl(i_i2c_scl), .i_sda(i_i2c_sda), - .o_scl(w_scl), .o_sda(w_sda) - // }}} - ); -`endif - - // mid_axis_pkt, r_channel - // {{{ - generate if (AXIS_ID_WIDTH > 0) - begin : GEN_TID - reg mid_axis_pkt; - reg [AXIS_ID_WIDTH-1:0] r_channel, axis_tid; - - always @(posedge i_clk) - if (i_reset || r_halted) - mid_axis_pkt <= 0; - else if (s_tvalid && insn_ready - && (insn[10:8] == CMD_RXK[2:0] - ||insn[10:8] == CMD_RXN[2:0] - ||insn[10:8] == CMD_RXLK[2:0] - ||insn[10:8] == CMD_RXLN[2:0])) - mid_axis_pkt <= 1; - else if (M_AXIS_TVALID && M_AXIS_TREADY) - mid_axis_pkt <= !M_AXIS_TLAST; - - always @(posedge i_clk) - if (i_reset || r_halted) - r_channel <= DEF_CHANNEL; - else if (insn_valid && insn[11:8] == CMD_CHANNEL && s_tready) - r_channel <= insn[AXIS_ID_WIDTH-1:0]; - - initial axis_tid = 0; - always @(posedge i_clk) - if (i_reset) - axis_tid <= 0; - else if (!M_AXIS_TVALID || M_AXIS_TREADY) - begin - if (insn_valid && insn[11:8] == CMD_CHANNEL - && s_tready && !mid_axis_pkt) - axis_tid <= insn[AXIS_ID_WIDTH-1:0]; - else if (M_AXIS_TVALID && M_AXIS_TREADY && M_AXIS_TLAST) - axis_tid <= r_channel; - else if (!mid_axis_pkt) - axis_tid <= r_channel; - end - - assign M_AXIS_TID = axis_tid; - end else begin : NO_TID - assign M_AXIS_TID = 1'b0; - end endgenerate - // }}} - - assign o_debug = { - r_aborted, // !r_halted || insn_valid, - ovw_data[OVW_VALID], - i2c_abort, i2c_stretch, half_insn, - r_wait, soft_halt_request, - w_control[21:0] }; - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc }; - // Verilator lint_off UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - wire [1:0] fwb_nreqs, fwb_nacks, fwb_outstanding; - wire [7:0] f_const_insn; - wire f_const_illegal; - wire [AW-1:0] f_address, f_const_addr; - - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - //////////////////////////////////////////////////////////////////////// - // - // Assert bus compliance - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - fwb_slave #( - // {{{ - .AW(2), .DW(32), .F_MAX_STALL(2), .F_MAX_ACK_DELAY(2), - .F_LGDEPTH(2) - // }}} - ) slv ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_wb_cyc(i_wb_cyc), .i_wb_stb(i_wb_stb), .i_wb_addr(i_wb_addr), - .i_wb_data(i_wb_data), .i_wb_sel(i_wb_sel), .i_wb_ack(o_wb_ack), - .i_wb_stall(o_wb_stall), .i_wb_idata(o_wb_data), - .i_wb_err(1'b0), - // - .f_nreqs(fwb_nreqs), - .f_nacks(fwb_nacks), - .f_outstanding(fwb_outstanding) - // }}} - ); - - always @(*) - if (f_past_valid && i_wb_cyc) - assert(fwb_outstanding == (o_wb_ack ? 1:0)); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Fetch interface compliance - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - ffetch #( - // {{{ - .ADDRESS_WIDTH(AW), - .INSN_WIDTH(8) - // }}} - ) f_fetch ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset || cpu_reset), - .cpu_new_pc(cpu_new_pc), .cpu_clear_cache(cpu_clear_cache), - .cpu_pc(pf_jump_addr), .pf_valid(pf_valid),.cpu_ready(pf_ready), - .pf_pc(pf_insn_addr),.pf_insn(pf_insn), .pf_illegal(pf_illegal), - .fc_illegal(f_const_illegal), .fc_insn(f_const_insn), - .fc_pc(f_const_addr), .f_address(f_address) - // }}} - ); - - /* - wire [AW-1:0] f_next_addr; - assign f_next_addr = f_address + 1; - always @(*) - if (!i_reset && !cpu_reset && !cpu_new_pc && !cpu_clear_cache) - assert(pf_jump_addr == f_next_addr); - */ - // }}} - - // Follow commands - - // First, the prefetch and decoding - - always @(*) - if (f_past_valid) - assert(!imm_cycle || !half_valid); - - //////////////////////////////////////////////////////////////////////// - // - // Model the (missing) I2C controller - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - (* anyseq *) wire m_tvalid, m_tlast; - (* anyseq *) wire [7:0] m_tdata; - - always @(posedge i_clk) - if (!f_past_valid) - begin - assert(!insn_valid); - end else if ($past(i_reset || i2c_abort || (OPT_MANUAL && r_manual) - ||bus_manual)) - begin - assert(!insn_valid); - assert(!half_valid); - end else if ($past(s_tvalid && !insn_ready)) - begin - assert(s_tvalid); - assert($stable(insn[10:0])); - end - - always @(posedge i_clk) - if (!f_past_valid) - begin - assume(!m_tvalid); - end else if ($past(i_reset)) - begin - assume(!m_tvalid); - end else if ($past(m_tvalid && !M_AXIS_TREADY)) - begin - assume(m_tvalid); - assume($stable(m_tdata)); - assume($stable(m_tlast)); - end - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - end else if ($past(m_tvalid && !M_AXIS_TREADY)) - assert($stable(M_AXIS_TID)); - - assign M_AXIS_TVALID = m_tvalid; - assign M_AXIS_TDATA = m_tdata; - assign M_AXIS_TLAST = m_tlast; - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wbi2c/wbi2cdma.v b/delete_later/rtl/wbi2c/wbi2cdma.v deleted file mode 100644 index 5a8eeeb..0000000 --- a/delete_later/rtl/wbi2c/wbi2cdma.v +++ /dev/null @@ -1,597 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbi2cdma.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is a basic stream to memory DMA. It's designed to work -// with the I2C controller, where memory accesses are on a byte by -// byte basis and rare. Therefore there's no buffering, and stream data -// is immediately written to memory as soon as its received. Similarly, -// since this is designed to write bytes, all bytes will be aligned by -// nature. If the stream width is increased beyond 8bits (a non-I2C -// application), the address will need to remain aligned. -// -// The design is activated as soon as a non-zero length is allotted to it. -// -// On receiving a stream LAST, the current address will return to the -// base address. -// -// Registers: -// 0: Control/Status -// 1: Active. Data has been received without receiving a -// last. -// 0: (Bus) Error. The design is deactivated on an error. -// Write a new base address or length to clear this bit. -// 1: (Current address) -// Almost. The actual current address will return to the base -// address once a LAST is received. This address will increment -// up to and including the LAST item. Hence, if nothing has been -// received, this will reflect the base address. If LAST has been -// received, then the difference between this and the base address -// will be the length of data received. -// 2: Base address (No alignment required) -// 3: Allocated length (Byte alignment) -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbi2cdma #( - // {{{ - parameter AW = 28, - parameter DW = 32, - parameter SW = 8, - parameter [0:0] OPT_LITTLE_ENDIAN = 1'b0, - parameter [0:0] OPT_LOWPOWER = 1'b0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Control port - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [1:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // }}} - // Stream port - // {{{ - input wire S_VALID, - output wire S_READY, - input wire [SW-1:0] S_DATA, - input wire S_LAST, - // }}} - // DMA master port - // {{{ - output reg o_dma_cyc, o_dma_stb, - output wire o_dma_we, - output reg [AW-1:0] o_dma_addr, - output reg [DW-1:0] o_dma_data, - output reg [DW/8-1:0] o_dma_sel, - input wire i_dma_stall, - input wire i_dma_ack, - input wire [DW-1:0] i_dma_data, - input wire i_dma_err - // }}} - // }}} - ); - - // Local declarations - // {{{ - localparam SUBLSB = $clog2(SW/8); - localparam WBLSB = $clog2(DW/SW); - localparam ADDRESS_WIDTH = AW + WBLSB; - - reg [ADDRESS_WIDTH-1:0] r_baseaddr, r_memlen; - reg [WBLSB-1:0] subaddr; - reg [ADDRESS_WIDTH-1:0] current_addr; - reg [31:0] next_baseaddr, next_memlen; - reg wb_last, bus_err, r_reset, r_overflow; - - wire skd_valid, skd_ready, skd_last; - wire [SW-1:0] skd_data; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Control - // {{{ - //////////////////////////////////////////////////////////////////////// - - always @(posedge i_clk) - if (i_reset) - bus_err <= 1'b0; - else if (o_dma_cyc && i_dma_err) - bus_err <= 1'b1; - else if (i_wb_stb && !o_wb_stall && i_wb_we) - case(i_wb_addr) - 2'b00: begin end // Control - 2'b01: begin end // Current address - 2'b10: bus_err <= bus_err && (i_wb_sel == 0); - 2'b11: bus_err <= bus_err && (i_wb_sel == 0); - endcase - - always @(*) - begin - next_baseaddr = 0; - next_baseaddr[ADDRESS_WIDTH-1:0] = r_baseaddr; - next_baseaddr = next_baseaddr << SUBLSB; - next_baseaddr = apply_strb(next_baseaddr, i_wb_sel, i_wb_data); - next_baseaddr = next_baseaddr >> SUBLSB; - - next_memlen = 0; - next_memlen[ADDRESS_WIDTH-1:0] = r_memlen; - next_memlen = next_memlen << SUBLSB; - next_memlen = apply_strb(next_memlen, i_wb_sel, i_wb_data); - next_memlen = next_memlen >> SUBLSB; - end - - initial r_baseaddr = 0; - initial r_memlen = 0; - initial r_reset = 1; - always @(posedge i_clk) - if (i_reset) - begin - r_baseaddr <= 0; - r_memlen <= 0; - r_reset <= 1; - end else if (i_wb_stb && !o_wb_stall && i_wb_we) - case(i_wb_addr) - 2'b00: begin end // Control - 2'b01: begin end // Current address - 2'b10: begin - r_baseaddr <= next_baseaddr[ADDRESS_WIDTH-1:0]; - r_reset <= 1; - end - 2'b11: begin - r_memlen <= next_memlen[ADDRESS_WIDTH-1:0]; - r_reset <= 1; - end - endcase else if (!i_wb_cyc) - begin - r_reset <= (r_memlen == 0) || bus_err - || (r_baseaddr + r_memlen >= (1<<(AW+WBLSB))); - end - - assign o_wb_stall = 1'b0; - - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_wb_ack <= 1'b0; - else - o_wb_ack <= i_wb_stb && !o_wb_stall; - - initial o_wb_data = 0; - always @(posedge i_clk) - begin - o_wb_data <= 32'h0; - - case(i_wb_addr) - 2'b00: begin - o_wb_data[1] <= !wb_last - && (current_addr != r_baseaddr); - o_wb_data[0] <= bus_err; - end - 2'b01: o_wb_data[ADDRESS_WIDTH-1:0] <= current_addr; - 2'b10: o_wb_data[ADDRESS_WIDTH-1:0] <= r_baseaddr; - 2'b11: o_wb_data[ADDRESS_WIDTH-1:0] <= r_memlen; - endcase - - if (OPT_LOWPOWER && (i_reset || !i_wb_stb - || !i_wb_we || i_wb_sel == 0)) - o_wb_data <= 0; - end - - - function automatic [31:0] apply_strb(input [31:0] old, - input [ 3:0] strb, - input [31:0] nxt); - begin - apply_strb[31:24] = (strb[3]) ? nxt[31:24] : old[31:24]; - apply_strb[23:16] = (strb[2]) ? nxt[23:16] : old[23:16]; - apply_strb[15: 8] = (strb[1]) ? nxt[15: 8] : old[15: 8]; - apply_strb[ 7: 0] = (strb[0]) ? nxt[ 7: 0] : old[ 7: 0]; - end endfunction - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Stream processing - // {{{ - //////////////////////////////////////////////////////////////////////// - - skidbuffer #( - .DW(1+SW), .OPT_LOWPOWER(OPT_LOWPOWER) - ) sskd ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_valid(S_VALID), .o_ready(S_READY), - .i_data({ S_LAST, S_DATA }), - // - .o_valid(skd_valid), .i_ready(skd_ready), - .o_data({ skd_last, skd_data }) - // }}} - ); - - assign skd_ready = r_reset || bus_err || !o_dma_cyc; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // DMA - // {{{ - //////////////////////////////////////////////////////////////////////// - - assign o_dma_we = 1'b1; - - initial { o_dma_cyc, o_dma_stb } = 2'b00; - always @(posedge i_clk) - if (i_reset || r_reset || bus_err || (o_dma_cyc && i_dma_err)) - { o_dma_cyc, o_dma_stb } <= 2'b00; - else if (o_dma_cyc) - begin - if (!i_dma_stall) - o_dma_stb <= 1'b0; - if (i_dma_ack) - o_dma_cyc <= 1'b0; - end else if (skd_valid) - begin - if (r_overflow && !wb_last) - { o_dma_cyc, o_dma_stb } <= 2'b00; - else - { o_dma_cyc, o_dma_stb } <= 2'b11; - end - - - always @(posedge i_clk) - if (r_reset) - wb_last <= 1'b1; - else if (skd_valid && skd_ready) - wb_last <= skd_last; - - // o_dma_addr, subaddr - // {{{ - always @(posedge i_clk) - if (r_reset || bus_err) - { o_dma_addr, subaddr } <= r_baseaddr; - else if ((!o_dma_stb || !i_dma_stall) && (wb_last || r_overflow)) - { o_dma_addr, subaddr } <= r_baseaddr; - else if (skd_valid && skd_ready && !r_overflow) - { o_dma_addr, subaddr } <= { o_dma_addr, subaddr } + 1; - // }}} - - // r_overflow - // {{{ - always @(posedge i_clk) - if (r_reset) - r_overflow <= 0; - else if ((!o_dma_stb || !i_dma_stall) && wb_last) - r_overflow <= 0; - else if (skd_valid && skd_ready && skd_last) - r_overflow <= 1'b0; - else if (!r_overflow) - r_overflow <= ({ o_dma_addr, subaddr } + 1 - r_baseaddr - >= r_memlen); - // }}} - - // o_dma_sel - // {{{ - generate if (OPT_LITTLE_ENDIAN) - begin : GEN_LILSEL - always @(posedge i_clk) - if (r_reset || bus_err) - o_dma_sel <= { {(DW/8-1){1'b0}},1'b1 } << r_baseaddr[WBLSB-1:0]; - else if ((!o_dma_stb || !i_dma_stall) &&(wb_last || r_overflow)) - o_dma_sel <= { {(DW/8-1){1'b0}},1'b1 } << r_baseaddr[WBLSB-1:0]; - else if (skd_valid && skd_ready) - o_dma_sel <= { o_dma_sel[(DW-SW)/8-1:0], o_dma_sel[DW/8-1: (DW-SW)/8] }; - end else begin : GEN_BIGSEL - always @(posedge i_clk) - if (r_reset || bus_err) - o_dma_sel <= { 1'b1, {(DW/8-1){1'b0}} } >> r_baseaddr[WBLSB-1:0]; - else if ((!o_dma_stb || !i_dma_stall) && (wb_last || r_overflow)) - o_dma_sel <= { 1'b1, {(DW/8-1){1'b0}} } >> r_baseaddr[WBLSB-1:0]; - else if (skd_valid && skd_ready) - o_dma_sel <= { o_dma_sel[SW/8-1:0], o_dma_sel[DW/8-1:SW/8] }; - end endgenerate - // }}} - - // o_dma_data - // {{{ - generate if (!OPT_LOWPOWER) - begin : GEN_DATABLAST - always @(posedge i_clk) - if (skd_ready) - o_dma_data <= {(DW/SW){skd_data }}; - - end else if (OPT_LITTLE_ENDIAN) - begin : GEN_LILDATA - // {{{ - always @(posedge i_clk) - if (r_reset || bus_err) - o_dma_data <= 0; - else if (skd_valid && skd_ready) - begin - if (wb_last) - o_dma_data <= { {(DW-1){1'b0}},skd_data } << r_baseaddr[WBLSB-1:0]*SW; - else - o_dma_data <= { {(DW-1){1'b0}},skd_data } << subaddr*SW; - end - // }}} - end else begin : GEN_BIGDATA - always @(posedge i_clk) - if (r_reset || bus_err) - o_dma_data <= 0; - else if (skd_valid && skd_ready) - begin - if (wb_last) - o_dma_data <= { skd_data, {(DW-1){1'b0}} } >> r_baseaddr[WBLSB-1:0]; - else - o_dma_data <= { skd_data, {(DW-1){1'b0}} } >> subaddr; - end - end endgenerate - // }}} - - always @(posedge i_clk) - if (r_reset) - current_addr <= r_baseaddr; - else if (o_dma_stb && !i_dma_stall) - current_addr <= { o_dma_addr, subaddr } + 1; - // }}} - - // Keep Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_dma_data }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH=4, F_LGCOUNT=12; - reg f_past_valid; - wire [AW+WBLSB-1:0] fdma_addr; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - assign fdma_addr = { o_dma_addr, subaddr }; - - //////////////////////////////////////////////////////////////////////// - // - // Control port (WB slave) properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wire [1:0] fwb_nreqs, fwb_nacks, fwb_noutstanding; - - fwb_slave #( - .AW(2), .DW(32), .F_MAX_STALL(1), .F_MAX_ACK_DELAY(2), - .F_LGDEPTH(2) - ) fslv ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_wb_cyc(i_wb_cyc), .i_wb_stb(i_wb_stb), .i_wb_we(i_wb_we), - .i_wb_addr(i_wb_addr), - .i_wb_data(i_wb_data), .i_wb_sel(i_wb_sel), - .i_wb_stall(o_wb_stall), - .i_wb_idata(o_wb_data), - .i_wb_ack(o_wb_ack), - .i_wb_err(1'b0), - .f_nreqs(fwb_nreqs), - .f_nacks(fwb_nacks), - .f_outstanding(fwb_noutstanding) - // }}} - ); - - always @(*) - if (!i_reset && i_wb_cyc) - begin - assert(fwb_noutstanding == (o_wb_ack ? 1:0)); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Incoming stream assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg [F_LGCOUNT-1:0] s_count; - - always @(posedge i_clk) - if (!f_past_valid) - assume(!S_VALID); - else if ($past(i_reset)) - assume(!S_VALID); - else if ($past(S_VALID && !S_READY)) - begin - assume(S_VALID); - assume($stable(S_DATA)); - assume($stable(S_LAST)); - end - - always @(posedge i_clk) - if (i_reset || r_reset) - s_count <= 0; - else if (skd_valid && skd_ready) - s_count <= (skd_last) ? 0 : (s_count + 1); - - always @(*) - assume(!(&s_count)); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // DMA (WB master) properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wire [F_LGDEPTH-1:0] fdma_nreqs, fdma_nacks, fdma_noutstanding; - - fwb_master #( - .AW(AW), .DW(DW), .F_LGDEPTH(F_LGDEPTH) - ) fdma ( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_wb_cyc(o_dma_cyc), .i_wb_stb(o_dma_stb), .i_wb_we(o_dma_we), - .i_wb_addr(o_dma_addr), - .i_wb_data(o_dma_data), .i_wb_sel(o_dma_sel), - .i_wb_stall(i_dma_stall), - .i_wb_idata(i_dma_data), - .i_wb_ack(i_dma_ack), - .i_wb_err(1'b0), - .f_nreqs(fdma_nreqs), - .f_nacks(fdma_nacks), - .f_outstanding(fdma_noutstanding) - // }}} - ); - - always @(posedge i_clk) - if (o_dma_cyc) - begin - assert(fdma_nreqs == (o_dma_stb ? 0 : 1)); - assert(fdma_nacks == 0); - end - - always @(posedge i_clk) - if (!i_reset && !r_reset) - begin - assert($countones(o_dma_sel)==1); - - assert(wb_last == (s_count == 0)); - if (!bus_err && s_count != 0 && !r_overflow) - assert(fdma_addr ==r_baseaddr + s_count-1); - - if (!r_overflow) - begin - assert(fdma_addr >= r_baseaddr); - assert(fdma_addr < r_baseaddr + r_memlen); - end - end - - generate if (OPT_LITTLE_ENDIAN) - begin : GEN_LITTLE_ENDIAN_SELCHECK - always @(posedge i_clk) - if (!i_reset && !r_reset && !bus_err) - assert(o_dma_sel == ({{((DW-SW)/8){1'b0}}, - {(SW/8){1'b1}} } >> subaddr)); - end else begin : GEN_BIG_ENDIAN_SELCHECK - always @(posedge i_clk) - if (!i_reset && !r_reset && !bus_err) - assert(o_dma_sel == ({{(SW/8){1'b1}}, - {((DW-SW)/8){1'b0}} } >> subaddr)); - end endgenerate - - always @(*) - if (!i_reset && !r_reset) - begin - assert(r_memlen != 0); - assert(r_memlen + r_baseaddr < (1<<(AW+WBLSB))); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - (* anyconst *) reg [F_LGCOUNT-1:0] fc_count; - (* anyconst *) reg [SW-1:0] fc_data; - reg [DW-1:0] f_shifted; - - always @(*) - if (s_count == fc_count) - assume(skd_data == fc_data); - - generate if (OPT_LITTLE_ENDIAN) - begin : GEN_LITTLE_ENDIAN_CONTRACT - always @(*) - f_shifted = o_dma_data >> subaddr * SW; - - always @(posedge i_clk) - if (o_dma_stb && s_count == fc_count+1) - assert(f_shifted[SW-1:0] == fc_data); - end else begin : GEN_BIG_ENDIAN_CONTRACT - always @(*) - f_shifted = o_dma_data << subaddr*SW; - - always @(posedge i_clk) - if (o_dma_stb && s_count == fc_count+1) - assert(f_shifted[DW-1:DW-SW] == fc_data); - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - (* anyconst *) reg fcvr; - always @(*) - if (fcvr) - assume(skd_last == (s_count == 7)); - - always @(*) - cover(o_dma_stb && wb_last && fcvr); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Careless assumptions - // {{{ - - // always @(*) assume(i_reset || r_reset || !r_overflow); - // }}} -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/wbi2c/wbi2cslave.v b/delete_later/rtl/wbi2c/wbi2cslave.v deleted file mode 100644 index 46a4aee..0000000 --- a/delete_later/rtl/wbi2c/wbi2cslave.v +++ /dev/null @@ -1,590 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbi2cslave.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: To create an I2C Slave that can be accessed via a wishbone bus. -// -// This core works by creating a dual-port 128-byte memory, that can be -// written to via either the wishbone bus it is connected to, or the I2C -// bus which it acts as a slave upon. -// Via either bus, the 128 bytes of slave memory may be referenced, read, -// and written to. -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2017-2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbi2cslave #( - // {{{ - // Verilator lint_off UNUSED - parameter INITIAL_MEM = "", - // Verilator lint_on UNUSED - parameter [0:0] WB_READ_ONLY = 1'b0, - parameter [0:0] I2C_READ_ONLY = 1'b0, - parameter [6:0] SLAVE_ADDRESS = 7'h50, - parameter MEM_ADDR_BITS = 8, - localparam [0:0] READ_ONLY = (WB_READ_ONLY)&&(I2C_READ_ONLY) - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Bus access - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [(MEM_ADDR_BITS-3):0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // }}} - // AXI Stream access, for data from I2C - // {{{ - input wire s_valid, - output wire s_ready, - input wire [7:0] s_data, - input wire s_last, - // }}} - // Actual I2C interaction - // {{{ - input wire i_i2c_scl, i_i2c_sda, - output reg o_i2c_scl, o_i2c_sda, - // }}} - output wire [31:0] o_dbg - // }}} - ); - - // Local declarations - // {{{ - localparam [2:0] I2CIDLE = 3'h0, - I2CSTART = 3'h1, - I2CADDR = 3'h2, - I2CSACK = 3'h3,// Slave ack's (that's us), - I2CRX = 3'h4,// Slave receive's (that's us) - I2CMACK = 3'h5,// Master acks's - I2CTX = 3'h6,// Slave transmits - I2CILLEGAL= 3'h7; - - localparam [1:0] BUS_IDLE = 2'b00, - BUS_READ = 2'b01, - BUS_SEND = 2'b10; - localparam PL=2; - - reg [31:0] mem [0:((1<<(MEM_ADDR_BITS-2))-1)]; - reg [4:0] wr_stb; - reg [7:0] i2c_addr; - wire [7:0] wr_data; - - reg [3:0] r_we; - reg [31:0] r_data; - reg [(MEM_ADDR_BITS-3):0] r_addr; - - reg [(2*PL-1):0] i2c_pipe; - reg last_scl, last_sda; - // Current values are at the edge of the synchronizer - wire this_scl = i2c_pipe[(2*PL-1)]; - wire this_sda = i2c_pipe[(2*PL-2)]; - - // This allows us to notice edges - wire i2c_posedge= (!last_scl)&&( this_scl); - wire i2c_negedge= ( last_scl)&&(!this_scl); - wire i2c_start = ( last_scl)&&( this_scl)&&( last_sda)&&(!this_sda); - wire i2c_stop = ( last_scl)&&( this_scl)&&(!last_sda)&&( this_sda); - - reg [2:0] i2c_state; - reg [7:0] dreg, oreg, rd_val, i2c_rx_byte; - wire [7:0] i2c_tx_byte; - reg [2:0] dbits; - reg slave_tx_rx_n, i2c_slave_ack, i2c_rx_stb, i2c_tx_stb; - - reg [1:0] bus_state; - reg go_bus_idle, wr_complete, - bus_rd_stb, bus_wr_stb; - reg [2:0] wr_pipe; - reg [31:0] pipe_mem; - reg [1:0] pipe_sel; - reg r_trigger; - - reg [MEM_ADDR_BITS-1:0] axis_addr; - // - -`ifndef VERILATOR - initial begin - if (INITIAL_MEM != "") - $readmemh(INITIAL_MEM, mem); - end -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone interactions: Read/write set memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // r_data, r_addr, r_we - // {{{ - initial r_we = 4'h0; - always @(posedge i_clk) - begin - if (!READ_ONLY) - begin - if ((!I2C_READ_ONLY)&&(wr_stb[4])) - begin - r_we <= wr_stb[3:0]; - r_addr <= i2c_addr[MEM_ADDR_BITS-1:2]; - r_data <= {(4){wr_data}}; - end else if (s_valid) - begin - case(axis_addr[1:0]) - 2'b00: r_we <= 4'b1000; - 2'b01: r_we <= 4'b0100; - 2'b10: r_we <= 4'b0010; - 2'b11: r_we <= 4'b0001; - endcase - r_addr <= axis_addr[MEM_ADDR_BITS-1:2]; - r_data <= {(4){s_data}}; - end else if ((!WB_READ_ONLY)&&(i_wb_stb)&&(i_wb_we)) - begin - r_we <= i_wb_sel; - r_addr <= i_wb_addr; - r_data <= i_wb_data; - end - end else - r_we <= 4'h0; - - if (i_reset) - r_we <= 4'h0; - end - // }}} - - // o_wb_data: Read from memory - // {{{ - always @(posedge i_clk) - o_wb_data <= mem[ i_wb_addr[(MEM_ADDR_BITS-3):0] ]; - // }}} - - // o_wb_ack, o_wb_stall - // {{{ - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - o_wb_ack <= (i_wb_stb)&&(!o_wb_stall); - - assign o_wb_stall = (!READ_ONLY && wr_stb[4]) || s_valid; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // AXI Stream incoming data - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial axis_addr = 0; - always @(posedge i_clk) - if (i_reset) - axis_addr <= 0; - else if (s_valid && s_ready) - begin - if (s_last) - axis_addr <= 0; - else - axis_addr <= axis_addr + 1; - end - - assign s_ready = (I2C_READ_ONLY || !wr_stb[4]); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Write to memory - // {{{ - always @(posedge i_clk) - if (!READ_ONLY) - begin - if (r_we[3]) - mem[r_addr][31:24] <= r_data[31:24]; - if (r_we[2]) - mem[r_addr][23:16] <= r_data[23:16]; - if (r_we[1]) - mem[r_addr][15: 8] <= r_data[15: 8]; - if (r_we[0]) - mem[r_addr][ 7: 0] <= r_data[ 7: 0]; - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // I2C Controller - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - - // - // - // Okay, that builds our memory, and gives us access to the bus. - // Now ... let's build the I2C slave portion to interact over that bus - // - // - - // 2FF Synchronizer - always @(posedge i_clk) - i2c_pipe <= { i2c_pipe[(2*PL-3):0], i_i2c_scl, i_i2c_sda }; - - // Capture the last values - always @(posedge i_clk) - begin - last_scl <= i2c_pipe[(2*PL-1)]; - last_sda <= i2c_pipe[(2*PL-2)]; - end - - // i2c_state, o_i2c_scl, o_i2c_sda, i2c_slave_ack, i2c_*x_stb,dreg,oreg - // {{{ - initial i2c_state = I2CIDLE; - initial o_i2c_scl = 1'b1; - initial o_i2c_sda = 1'b1; - initial i2c_slave_ack = 1'b1; - always @(posedge i_clk) - begin - // Default is to do nothing with the output ports. A 1'b1 does - // that. - o_i2c_scl <= 1'b1; - o_i2c_sda <= 1'b1; - i2c_tx_stb <= 1'b0; - i2c_rx_stb <= 1'b0; - if (i2c_posedge) - dreg <= { dreg[6:0], this_sda }; - if (i2c_negedge) - oreg <= { oreg[6:0], oreg[0] }; - case(i2c_state) - I2CIDLE: begin - // {{{ - dbits <= 0; - if (i2c_start) - i2c_state <= I2CSTART; - end - // }}} - I2CSTART: begin - // {{{ - dbits <= 0; - if (i2c_negedge) - i2c_state <= I2CADDR; - end - // }}} - I2CADDR: begin - // {{{ - if (i2c_negedge) - dbits <= dbits + 1'b1; - if ((i2c_negedge)&&(dbits == 3'h7)) - begin - slave_tx_rx_n <= dreg[0]; - if (dreg[7:1] == SLAVE_ADDRESS) - begin - i2c_state <= I2CSACK; - i2c_slave_ack <= 1'b0; - end else begin - // Ignore this, its not for - // me. - i2c_state <= I2CILLEGAL; - i2c_slave_ack <= 1'b1; - end - end - end - // }}} - I2CSACK: begin - // {{{ - dbits <= 3'h0; - // NACK anything outside of our address range - o_i2c_sda <= i2c_slave_ack; - oreg <= rd_val; - if (i2c_negedge) - begin - i2c_state <= (slave_tx_rx_n)? I2CTX:I2CRX; - oreg <= i2c_tx_byte; - end - end - // }}} - I2CRX: begin // Slave reads from the bus - // {{{ - // - // First byte received is always the memory - // address. - // - if (i2c_negedge) - dbits <= dbits + 1'b1; - if ((i2c_negedge)&&(dbits == 3'h7)) - begin - i2c_rx_byte <= dreg; - i2c_rx_stb <= 1'b1; - i2c_state <= I2CSACK; - end - end - // }}} - I2CTX: begin // Slave transmits - // {{{ - // Read from the slave (that's us) - if (i2c_negedge) - dbits <= dbits + 1'b1; - if ((i2c_negedge)&&(dbits == 3'h7)) - begin - i2c_tx_stb <= 1'b1; - i2c_state <= I2CMACK; - end - o_i2c_sda <= oreg[7]; - end - // }}} - I2CMACK: begin - // {{{ - dbits <= 3'h0; - if (i2c_negedge) - begin - i2c_state <= I2CTX; - oreg <= i2c_tx_byte; - end - oreg <= rd_val; - end - // }}} - I2CILLEGAL: dbits <= 3'h0; - // default: dbits <= 3'h0; - endcase - if (i2c_stop) - i2c_state <= I2CIDLE; - else if (i2c_start) - i2c_state <= I2CSTART; - end - // }}} - - // bus_*_stb, wr_complete, go_bus_idle, bus_state - // {{{ - initial wr_complete = 1'b0; - initial bus_rd_stb = 1'b0; - initial bus_wr_stb = 1'b0; - initial bus_state = BUS_IDLE; - initial go_bus_idle = 1'b0; - always @(posedge i_clk) - begin - go_bus_idle <= ((i2c_state == I2CIDLE) - ||(i2c_state == I2CSTART) - ||(i2c_state == I2CILLEGAL)); - bus_rd_stb <= 1'b0; - bus_wr_stb <= 1'b0; - if (go_bus_idle) - bus_state <= BUS_IDLE; - else case(bus_state) - BUS_IDLE: begin - // {{{ - if (i2c_rx_stb) - begin - i2c_addr <= i2c_rx_byte; - bus_state <= BUS_READ; - bus_rd_stb <= 1'b1; - end else if (i2c_tx_stb) - begin - bus_state <= BUS_SEND; - i2c_addr <= i2c_addr + 1'b1; - bus_rd_stb <= 1'b1; - end end - // }}} - BUS_READ: if (i2c_rx_stb) - // {{{ - begin - // Reading from the bus means we are - // writing to memory - bus_wr_stb <= (!I2C_READ_ONLY); - end - // Increment the address once a write completes - // }}} - BUS_SEND: if (i2c_tx_stb) - // {{{ - begin - // Once we've finished transmitting, - // increment the address to read the - // next item - i2c_addr <= i2c_addr + 1'b1; - bus_rd_stb <= 1'b1; - end - // }}} - default: begin end - endcase - - if (wr_complete) - begin - i2c_addr <= i2c_addr + 1'b1; - bus_rd_stb <= 1'b1; - end - end - // }}} - - // wr_pipe, wr_complete - // {{{ - initial wr_pipe = 3'h0; - initial wr_complete = 1'b0; - always @(posedge i_clk) - wr_pipe <= { wr_pipe[1:0], bus_wr_stb }; - always @(posedge i_clk) - wr_complete <= wr_pipe[2]; - // }}} - - // wr_stb - // {{{ - initial wr_stb = 5'b0; - always @(posedge i_clk) - if (!I2C_READ_ONLY) - begin - wr_stb[4] <= bus_wr_stb; - wr_stb[3] <= (bus_wr_stb)&&(i2c_addr[1:0]==2'b00); - wr_stb[2] <= (bus_wr_stb)&&(i2c_addr[1:0]==2'b01); - wr_stb[1] <= (bus_wr_stb)&&(i2c_addr[1:0]==2'b10); - wr_stb[0] <= (bus_wr_stb)&&(i2c_addr[1:0]==2'b11); - end - // }}} - - assign wr_data = i2c_rx_byte; - - - // Read from memory - // {{{ - always @(posedge i_clk) - if(bus_rd_stb) - pipe_mem <= mem[i2c_addr[(MEM_ADDR_BITS-1):2]]; - // }}} - - // pipe_sel - // {{{ - always @(posedge i_clk) - if (bus_rd_stb) - pipe_sel <= i2c_addr[1:0]; - // }}} - - // rd_val - // {{{ - always @(posedge i_clk) - case(pipe_sel) - 2'b00: rd_val <= pipe_mem[31:24]; - 2'b01: rd_val <= pipe_mem[23:16]; - 2'b10: rd_val <= pipe_mem[15: 8]; - 2'b11: rd_val <= pipe_mem[ 7: 0]; - endcase - // }}} - - assign i2c_tx_byte = rd_val; - // }}} - // Debug port - // {{{ - initial r_trigger = 1'b0; - always @(posedge i_clk) - r_trigger <= i2c_start; - - assign o_dbg = { r_trigger, 3'h0, - i_wb_stb, i_wb_we && i_wb_stb, o_wb_stall, - o_wb_ack, i_wb_addr[5:0],2'b00, // 12b - s_valid, s_ready, s_last, 1'b0, s_data, // 12b - i_i2c_scl, i_i2c_sda, o_i2c_scl, o_i2c_sda // 4b - }; - // }}} - - // Make verilator happy - // {{{ - // verilator lint_off UNUSED - wire [1:0] unused; - assign unused = { i_wb_cyc, i_reset }; - // verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH = 4; - reg [F_LGDEPTH-1:0] f_nreqs, f_nacks, f_outstanding; - - fwb_slave #(.AW(MEM_ADDR_BITS-2),.DW(DW), - .F_MAX_STALL(3),.F_MAX_ACK_DELAY(1), - .F_LGDEPTH(F_LGDEPTH)) - fwb(i_clk, i_reset, - i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel, - o_wb_ack, o_wb_stall, o_wb_data, 1'b0, - f_nreqs, f_nacks, f_outstanding); - - always @(*) - if (o_wb_ack) - assert(f_outstanding == 1); - else - assert(f_outstanding == 0); - - always @(*) - if (!o_i2c_scl) - assume(!i_i2c_scl); - - always @(*) - if (!o_i2c_sda) - assume(!i_i2c_sda); - - sequence INPUTBIT(BIT) - (!this_scl)&&(this_sda == BIT) [1:$] - ##1 (this_scl)&&(this_sda == BIT) [1:$] - ##1 (!this_scl)&&(this_sda == BIT) [1:$] - endsequence - - sequence OUTPUTBIT(BIT) - (!this_scl)&&(this_sda == BIT) [1:$] - ##1 (this_scl)&&(this_sda == BIT) [1:$] - ##1 (!this_scl) [1:$] - endsequence - - sequence STOPBIT(BIT) - (this_scl) throughout - ((!this_sda) [1:$] ##1 (this_sda)) - endsequence - - sequence STARTBIT(BIT) - (this_scl) throughout - ((this_sda) [1:$] ##1 (!this_sda)) - endsequence - - wire i2c_stop = ( last_scl)&&( this_scl)&&(!last_sda)&&( this_sda); - - sequence PREAMBLE - (i2c_start) - ##1 (this_scl)&&(!this_sda) [1:$] - ##1 (!this_scl)&&(!this_sda) [1:$] - ##1 ADDRBIT(SLAVE_ADDRESS[6]) - ##1 ADDRBIT(SLAVE_ADDRESS[5]) - ##1 ADDRBIT(SLAVE_ADDRESS[4]) - ##1 ADDRBIT(SLAVE_ADDRESS[3]) - ##1 ADDRBIT(SLAVE_ADDRESS[2]) - ##1 ADDRBIT(SLAVE_ADDRESS[1]) - ##1 ADDRBIT(SLAVE_ADDRESS[0]) - endsequence -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wbicapetwo.v b/delete_later/rtl/wbicapetwo.v deleted file mode 100644 index 7565dae..0000000 --- a/delete_later/rtl/wbicapetwo.v +++ /dev/null @@ -1,801 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbicapetwo.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This routine maps the configuration registers of a 7-series -// Xilinx part onto register addresses on a wishbone bus interface -// via the ICAPE2 access port to those parts. The big thing this -// captures is the timing and handshaking required to read and -// write registers from the configuration interface. -// -// As an example of what can be done, writing a 32'h00f to -// local address 5'h4 sends the IPROG command to the FPGA, causing -// it to immediately reconfigure itself. -// -// As another example, the warm boot start address is located -// in register 5'h10. Writing to this address, followed by -// issuing the IPROG command just mentioned will cause the -// FPGA to configure from that warm boot start address. -// -// For more details on the configuration interface, the registers -// in question, their meanings and what they do, please see -// User's Guide 470, the "7 Series FPGAs Configuration" User -// Guide. -// -// Notes: This module supports both reads and writes from the ICAPE2 -// interface. These follow the following pattern. -// -// For writes: -// (Idle) 0xffffffff (Dummy) -// (CS/W) 0x20000000 NOOP -// (CS/W) 0xaa995566 SYNC WORD -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x20000000 NOOP -// (CS/W) ... Write command -// (CS/W) ... Write value, from Wishbone bus -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x30008001 Write to CMD register (address 4) -// (CS/W) 0x0000000d DESYNC command -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x20000000 NOOP -// (Idle) -// -// and for reads: -// (Idle) 0xffffffff (Dummy) -// (CS/W) 0x20000000 NOOP -// (CS/W) 0xaa995566 SYNC WORD -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x20000000 NOOP -// (CS/W) ... Read command -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x20000000 NOOP -// (Idle) 0x20000000 (Idle the interface again, so we can rd) -// (CS/R) 0x20000000 (Wait) -// (CS/R) 0x20000000 (Wait) -// (CS/R) 0x20000000 (Wait) -// (CS/R) 0x20000000 (Wait) -// (Idle) 0x20000000 (Idle the interface before writing) -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x30008001 Write to CMD register (address 4) -// (CS/W) 0x0000000d DESYNC command -// (CS/W) 0x20000000 NOOP -// (CS/W) 0x20000000 NOOP -// (Idle) -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -`default_nettype none -// }}} -module wbicapetwo #( - parameter LGDIV = 3 /// Log of the clock divide - ) ( - // {{{ - input wire i_clk, - // Wishbone inputs - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [4:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - // Wishbone outputs - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // - output wire [31:0] o_dbg - // }}} - ); - - //////////////////////////////////////////////////////////////////////// - // - // Local declarations - // {{{ - localparam [4:0] MBOOT_IDLE = 5'h00, - MBOOT_START = 5'h01, - MBOOT_END_OF_SYNC = 5'h05, - MBOOT_READ = 5'h06, - MBOOT_END_OF_READ = 5'h0e, - MBOOT_WRITE = 5'h0f, - MBOOT_END_OF_WRITE = 5'h10, - MBOOT_DESYNC = 5'h11, - MBOOT_END = 5'h17; - localparam [31:0] NOOP = 32'h2000_0000; - - // ICAPE2 interface signals - // These are kept internal to this block ... - - genvar k; - reg wb_req, r_we, pre_stall; - reg [31:0] r_data; - reg [4:0] r_addr; - - reg [31:0] cfg_in; - reg cfg_cs_n, cfg_rdwrn; - wire [31:0] cfg_out; - reg [4:0] state; - - wire [31:0] bit_swapped_cfg_in; - wire [31:0] bit_swapped_cfg_out; - - reg clk_stb; - wire slow_clk; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Internal "Clock" generation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - generate - if (LGDIV <= 1) - begin : DDRCK - // {{{ - reg r_slow_clk; - always @(posedge i_clk) - begin - r_slow_clk <= (slow_clk + 1'b1); - // We'll move on the positive edge of the clock, - // so therefore clk_stb must be true one clock before - // that, so we test for it one clock before that. - clk_stb <= (slow_clk == 1'b1); - end - - assign slow_clk = r_slow_clk; - // }}} - end else begin : CLOCKGEN - // {{{ - reg [(LGDIV-1):0] slow_clk_counter; - localparam [LGDIV-1:0] MINUS_TWO = -2; - - initial slow_clk_counter = 0; - always @(posedge i_clk) - begin - slow_clk_counter <= slow_clk_counter + 1'b1; - // We'll move on the negative edge of the clock, so - // therefore clk_stb must be true one clock before - // that, so we test for it one clock before that. - clk_stb <= (slow_clk_counter==MINUS_TWO); - end - - assign slow_clk = slow_clk_counter[(LGDIV-1)]; - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Giant state machine - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial state = MBOOT_IDLE; - initial cfg_cs_n = 1'b1; - initial cfg_rdwrn = 1'b1; - initial o_wb_ack = 1'b0; - always @(posedge i_clk) - begin - // In general, o_wb_ack is always zero. The exceptions to this - // will be handled individually below. - o_wb_ack <= 1'b0; - // We can simplify our logic a touch by always setting - // o_wb_data. It will only be examined if o_wb_ack - // is also true, so this is okay. - o_wb_data <= cfg_out; - - // Turn any request "off", so that it will not be ack'd, if - // the wb_cyc line is ever lowered. - wb_req <= wb_req && i_wb_cyc; - - pre_stall <= (state != MBOOT_IDLE); - if (clk_stb) - begin - state <= state + 5'h01; - case(state) - MBOOT_IDLE: begin - // {{{ - cfg_cs_n <= 1'b1; - cfg_rdwrn <= 1'b1; - cfg_in <= 32'hffffffff; // Dummy word - - state <= MBOOT_IDLE; - pre_stall <= 1'b0; - - o_wb_ack <= 1'b0; - - r_addr <= i_wb_addr; - r_data <= i_wb_data; - r_we <= i_wb_we; - if(i_wb_stb) // &&(!o_wb_stall) - begin - if (&i_wb_sel) - begin - state <= MBOOT_START; - wb_req <= 1'b1; - pre_stall <= 1'b1; - end else - o_wb_ack <= 1'b1; - end end - // }}} - MBOOT_START: begin - // {{{ - cfg_in <= 32'hffffffff; // NOOP - cfg_cs_n <= 1'b1; - end - // }}} - 5'h02: begin - // {{{ - cfg_cs_n <= 1'b0; // Activate interface - cfg_rdwrn <= 1'b0; - cfg_in <= 32'h20000000; // NOOP - end - // }}} - 5'h03: begin // Sync word - // {{{ - cfg_in <= 32'haa995566; // Sync word - cfg_cs_n <= 1'b0; - end - // }}} - 5'h04: begin // NOOP - // {{{ - cfg_in <= 32'h20000000; // NOOP - cfg_cs_n <= 1'b0; - end - // }}} - 5'h05: begin // NOOP - // {{{ - // Opening/sync sequence is complete. Continue - // now with either the read or write sequence - cfg_in <= 32'h20000000; // NOOP - state <= (r_we) ? MBOOT_WRITE : MBOOT_READ; - cfg_cs_n <= 1'b0; - end - // }}} - MBOOT_READ: begin - // {{{ - cfg_cs_n <= 1'b0; - cfg_in <= { 8'h28, 6'h0, r_addr, 13'h001 }; - end - // }}} - 5'h07: begin // (Read, NOOP) - // {{{ - cfg_cs_n <= 1'b0; - cfg_in <= 32'h20000000; // NOOP - end - // }}} - 5'h08: begin // (Read, NOOP) - // {{{ - cfg_cs_n <= 1'b0; - cfg_in <= 32'h20000000; // NOOP - end - // }}} - 5'h09: begin // Idle the interface before the read cycle - // {{{ - cfg_cs_n <= 1'b1; - cfg_rdwrn <= 1'b1; - cfg_in <= 32'h20000000; // NOOP - end - // }}} - 5'h0a: begin // Re-activate the interface, wait 3 cycles - // {{{ - cfg_cs_n <= 1'b0; - cfg_rdwrn <= 1'b1; - cfg_in <= 32'h20000000; // NOOP - end - // }}} - 5'h0b: begin // NOOP ... still waiting, cycle two - // {{{ - cfg_in <= 32'h20000000; // NOOP - cfg_cs_n <= 1'b0; - end - // }}} - 5'h0c: begin // NOOP ... still waiting, cycle three - // {{{ - cfg_in <= 32'h20000000; // NOOP - cfg_cs_n <= 1'b0; - end - // }}} - 5'h0d: begin // NOOP ... still waiting, cycle four - // {{{ - cfg_in <= 32'h20000000; // NOOP - cfg_cs_n <= 1'b0; - end - // }}} - MBOOT_END_OF_READ: begin // and now our answer is there - // {{{ - cfg_cs_n <= 1'b1; - cfg_rdwrn <= 1'b1; - cfg_in <= 32'h20000000; // NOOP - // - // Wishbone return - o_wb_ack <= i_wb_cyc && wb_req; - // o_wb_data <= cfg_out; // Independent of state - wb_req <= 1'b0; - // - state <= MBOOT_DESYNC; - end - // }}} - MBOOT_WRITE: begin // Issue write cmd to the given addr - // {{{ - cfg_in <= { 8'h30, 6'h0, r_addr, 13'h001 }; - cfg_cs_n <= 1'b0; - end - // }}} - MBOOT_END_OF_WRITE: begin - // {{{ - cfg_in <= r_data; // Write the value - cfg_cs_n <= 1'b0; - end - // }}} - MBOOT_DESYNC: begin - // {{{ - cfg_cs_n <= 1'b0; - cfg_rdwrn <= 1'b0; - cfg_in <= 32'h20000000; // 1st NOOP - end - // }}} - 5'h12: begin - // {{{ - cfg_cs_n <= 1'b0; - cfg_in <= 32'h20000000; // 2nd NOOP - end - // }}} - 5'h13: begin - // {{{ - cfg_cs_n <= 1'b0; - cfg_in <= 32'h30008001; // Write to CMD register - end - // }}} - 5'h14: begin - // {{{ - cfg_cs_n <= 1'b0; - cfg_in <= 32'h0000000d; // DESYNC command - end - // }}} - 5'h15: begin - // {{{ - cfg_cs_n <= 1'b0; - cfg_in <= 32'h20000000; // NOOP - end - // }}} - 5'h16: begin - // {{{ - cfg_cs_n <= 1'b0; - cfg_in <= 32'h20000000; // NOOP - end - // }}} - MBOOT_END: begin // Acknowledge the bus transaction, - // {{{ - // it is now complete - o_wb_ack <= i_wb_cyc && wb_req; - wb_req <= 1'b0; - // - cfg_cs_n <= 1'b1; - cfg_rdwrn <= 1'b0; - cfg_in <= 32'hffffffff; // DUMMY - // - state <= MBOOT_IDLE; - pre_stall <= 1'b0; - end - // }}} - default: begin - // {{{ - wb_req <= 1'b0; - cfg_cs_n <= 1'b1; - cfg_rdwrn <= 1'b0; - state <= MBOOT_IDLE; - pre_stall <= 1'b0; - cfg_in <= 32'hffffffff; // DUMMY WORD - end - // }}} - endcase - end - end - - assign o_wb_stall = pre_stall || !clk_stb; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bit-swap in and out registers - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // - // The data registers to the ICAPE2 interface are bit swapped within - // each byte. Thus, in order to read from or write to the interface, - // we need to bit swap the bits in each byte. These next lines - // accomplish that for both the input and output ports. - // - generate for(k=0; k<8; k=k+1) - begin : GEN_BITSWAP - assign bit_swapped_cfg_in[ k] = cfg_in[ 7-k]; - assign bit_swapped_cfg_in[ 8+k] = cfg_in[ 8+7-k]; - assign bit_swapped_cfg_in[16+k] = cfg_in[16+7-k]; - assign bit_swapped_cfg_in[24+k] = cfg_in[24+7-k]; - end endgenerate - - generate for(k=0; k<8; k=k+1) - begin : GEN_CFGOUT - assign cfg_out[ k] = bit_swapped_cfg_out[ 7-k]; - assign cfg_out[ 8+k] = bit_swapped_cfg_out[ 8+7-k]; - assign cfg_out[16+k] = bit_swapped_cfg_out[16+7-k]; - assign cfg_out[24+k] = bit_swapped_cfg_out[24+7-k]; - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Instantiate ICAPE2 - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // -`ifdef VERILATOR - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, slow_clk, cfg_cs_n, cfg_rdwrn }; - assign bit_swapped_cfg_out = bit_swapped_cfg_in; - // Verilator lint_on UNUSED -`else -`ifndef FORMAL - ICAPE2 #( - .ICAP_WIDTH("X32") - ) reconfig( - .CLK(slow_clk), .CSIB(cfg_cs_n), .RDWRB(cfg_rdwrn), - .I(bit_swapped_cfg_in), .O(bit_swapped_cfg_out) - ); -`else - (* anyseq *) wire [31:0] f_icape_return; - - assign bit_swapped_cfg_out = f_icape_return; -`endif -`endif - // }}} - - assign o_dbg = { (i_wb_stb && !o_wb_stall), // TRIGGER - clk_stb, slow_clk, 1'b0, // 3b - i_wb_stb, o_wb_ack, cfg_cs_n, cfg_rdwrn, // 4b - o_wb_stall, 2'h0, state, // 8b - (cfg_rdwrn) ? - (clk_stb ? cfg_out[15:0]:cfg_out[31:16]) - : (clk_stb ? cfg_in[15:0] : cfg_in[31:16]) }; // 16b -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // This is only a partial formal proof - localparam F_LGDEPTH = 4; - reg f_past_valid; - wire [F_LGDEPTH-1:0] fwb_nreqs, fwb_nacks, fwb_outstanding; - reg fwb_we; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - //////////////////////////////////////////////////////////////////////// - // - // Bus properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - fwb_slave #( - // {{{ - .AW(5), .F_MAX_STALL(0), .F_MAX_ACK_DELAY(0), - .F_LGDEPTH(F_LGDEPTH) - // }}} - ) fwb ( - // {{{ - .i_clk(i_clk), .i_reset(!f_past_valid), - // - // Wishbone inputs - .i_wb_cyc(i_wb_cyc), - .i_wb_stb(i_wb_stb), - .i_wb_we(i_wb_we), - .i_wb_addr(i_wb_addr), - .i_wb_data(i_wb_data), - .i_wb_sel(i_wb_sel), - .i_wb_ack(o_wb_ack), - .i_wb_err(1'b0), - .i_wb_stall(o_wb_stall), - .f_nreqs(fwb_nreqs), - .f_nacks(fwb_nacks), - .f_outstanding(fwb_outstanding) - // }}} - ); - - always @(*) - assert(fwb_outstanding <= 1); - - always @(*) - if (i_wb_cyc) - assert(fwb_outstanding == ((o_wb_ack || wb_req) ? 1:0)); - - always @(*) - if (!clk_stb || state != MBOOT_IDLE) - assert(o_wb_stall); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // {{{ - always @(posedge i_clk) - if (i_wb_stb && !o_wb_stall) - fwb_we <= i_wb_we; - - always @(*) - if (state >= MBOOT_WRITE && state < MBOOT_DESYNC) - assert(fwb_we); - - always @(*) - if (state < MBOOT_WRITE && state >= MBOOT_READ) - assert(!fwb_we); - - always @(posedge i_clk) - if (f_past_valid) - begin - if (state == MBOOT_IDLE) - assert(!wb_req); - - case(state) - MBOOT_IDLE: assert($stable(state) || $past(state) == MBOOT_END); - MBOOT_READ: assert($stable(state) - || $past(state) == MBOOT_END_OF_SYNC); - MBOOT_WRITE:assert($stable(state) - || $past(state) == MBOOT_END_OF_SYNC); - MBOOT_DESYNC:assert($stable(state) - || $past(state) == MBOOT_END_OF_WRITE - || $past(state) == MBOOT_END_OF_READ); - default: - assert($stable(state) || state == $past(state)+1); - endcase - end - - always @(*) - assert(state <= 5'h17); - - always @(*) - case(state) - MBOOT_IDLE: begin - // {{{ - if (f_past_valid) - begin - assert(cfg_cs_n); - // assert(cfg_rdwrn); - // cfg_cs_n <= 1'b1; - // cfg_rdwrn <= 1'b1; - // cfg_in <= 32'hffffffff; // Dummy word - end end - // }}} - MBOOT_START: begin - // {{{ - // cfg_in <= 32'hffffffff; // NOOP - // cfg_cs_n <= 1'b1; - assert(cfg_cs_n); - assert(cfg_rdwrn); - end - // }}} - 5'h02: begin - // {{{ - assert(cfg_cs_n); - assert(cfg_rdwrn); - assert(&cfg_in); - end - // }}} - 5'h03: begin - // {{{ - assert(!cfg_cs_n); // Activate interface - assert(!cfg_rdwrn); - assert(cfg_in == 32'h20000000); // NOOP - end - // }}} - 5'h04: begin - // {{{ - assert(!cfg_cs_n); - assert(!cfg_rdwrn); - assert(cfg_in == 32'haa995566); // NOOP - end - // }}} - 5'h05: begin - // {{{ - assert(!cfg_cs_n); - assert(!cfg_rdwrn); - assert(cfg_in == 32'h2000_0000); // NOOP - end - // }}} - MBOOT_READ: begin - // {{{ - assert(!cfg_cs_n); // Activate interface - assert(!cfg_rdwrn); - assert(cfg_in == 32'h2000_0000); // NOOP - end - // }}} - 5'h07: begin - // {{{ - assert(!cfg_cs_n); - // cfg_in <= { 8'h28, 6'h0, r_addr, 13'h001 }; - end - // }}} - 5'h08: begin - // {{{ - assert(!cfg_cs_n); // Activate interface - assert(!cfg_rdwrn); - assert(cfg_in == NOOP); // NOOP - end - // }}} - 5'h09: begin // Idle the interface before the read cycle - // {{{ - // cfg_cs_n <= 1'b1; - // cfg_rdwrn <= 1'b1; - // cfg_in <= 32'h20000000; // NOOP - end - // }}} - 5'h0a: begin // Re-activate the interface and wait 3 cycles - // {{{ - assert(cfg_cs_n); - assert(cfg_rdwrn); - assert(cfg_in == NOOP); // NOOP - end - // }}} - 5'h0b: begin // ... still waiting, cycle two - // {{{ - assert(!cfg_cs_n); - assert(cfg_rdwrn); - assert(cfg_in == NOOP); // NOOP - end - // }}} - 5'h0c: begin // ... still waiting, cycle three - // {{{ - assert(!cfg_cs_n); - assert(cfg_rdwrn); - assert(cfg_in == NOOP); // NOOP - end - // }}} - 5'h0d: begin // ... still waiting, cycle four - // {{{ - assert(!cfg_cs_n); - assert(cfg_rdwrn); - assert(cfg_in == NOOP); // NOOP - end - // }}} - MBOOT_END_OF_READ: begin // and now our answer is there - // {{{ - // cfg_in <= 32'h20000000; // NOOP - // cfg_cs_n <= 1'b0; - // cfg_cs_n <= 1'b1; - end - // }}} - MBOOT_WRITE: begin - // {{{ - // Issue a write command to the given address - // cfg_in <= { 8'h30, 6'h0, r_addr, 13'h001 }; - // cfg_cs_n <= 1'b0; - end - // }}} - MBOOT_END_OF_WRITE: begin - // {{{ - // cfg_in <= r_data; // Write the value - // cfg_cs_n <= 1'b0; - end - // }}} - MBOOT_DESYNC: begin - // {{{ - // cfg_cs_n <= 1'b0; - // cfg_rdwrn <= 1'b0; - // cfg_in <= 32'h20000000; // 1st NOOP - end - // }}} - 5'h12: begin - // {{{ - assert(!cfg_cs_n); - assert(!cfg_rdwrn); - assert(cfg_in == NOOP); - end - // }}} - 5'h13: begin - // {{{ - // cfg_cs_n <= 1'b0; - // cfg_in <= 32'h30008001; // Write to CMD register - assert(!cfg_cs_n); - assert(!cfg_rdwrn); - assert(cfg_in == NOOP); - end - // }}} - 5'h14: begin - // {{{ - assert(!cfg_cs_n); - assert(!cfg_rdwrn); - assert(cfg_in == 32'h30008001); - // cfg_in <= 32'h0000000d; // DESYNC command - end - // }}} - 5'h15: begin - // {{{ - assert(!cfg_cs_n); - assert(!cfg_rdwrn); - assert(cfg_in == 32'h0d); - // cfg_in <= 32'h0000000d; // DESYNC command - end - // }}} - 5'h16: begin - // {{{ - assert(!cfg_cs_n); - assert(!cfg_rdwrn); - assert(cfg_in == NOOP); - end - // }}} - MBOOT_END: begin - // {{{ - assert(!cfg_cs_n); - assert(!cfg_rdwrn); - assert(cfg_in == NOOP); - end - // }}} - default: assert(0); - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg cvr_write, cvr_read; - - always @(*) - if (f_past_valid) - cover(o_wb_ack); - - initial cvr_write = 1'b0; - always @(posedge i_clk) - if (i_wb_cyc && o_wb_ack && fwb_we) - cvr_write <= 1'b1; - - initial cvr_read = 1'b0; - always @(posedge i_clk) - if (i_wb_cyc && o_wb_ack && !fwb_we) - cvr_read <= 1'b1; - - always @(*) - if (!o_wb_stall && cvr_write && !i_wb_cyc) - cover(cvr_write); - - always @(*) - if (!o_wb_stall && cvr_write && !i_wb_cyc) - cover(cvr_read); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wbmarbiter.v b/delete_later/rtl/wbmarbiter.v deleted file mode 100644 index 7160151..0000000 --- a/delete_later/rtl/wbmarbiter.v +++ /dev/null @@ -1,651 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbmarbiter.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A *HIGH* speed N:1 WB arbiter. This works like an N:1 AXI -// arbiter: Wishbone requests are potentially interleaved between -// multiple (incoming) slave connections. Hence, an outgoing connection -// might include requests from slave 1, 2, 4, 3, etc, and the arbiter -// will be responsible for returning ACKs in the order they were received: -// 1, 2, 4, 3, etc. There are some unfortunate consequences to this, -// however, that break some key features of Wishbone. -// -// 1. If two slaves have outstanding requests and a bus error is returned, -// the bus error will be returned to *both* slaves, not just one, -// *EVEN IF* only one slave created an illegal access. -// 2. Read-Modify-Write accesses are now broken, because there is no longer -// any guarantee, when using this arbiter, that no other bus master -// (incoming slave) will not have modified a given address. -// 3. The property that bus requests will only ever be a string of reads, -// or a string of writes, is also broken. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbmarbiter #( - // {{{ - parameter DW = 64, - parameter AW = 31-$clog2(DW/8), - parameter NIN = 4, - parameter LGFIFO = 5, - parameter [0:0] OPT_LOWPOWER = 0 - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // - input wire [NIN-1:0] s_cyc, s_stb, s_we, - input wire [NIN*AW-1:0] s_addr, - input wire [NIN*DW-1:0] s_data, - input wire [NIN*DW/8-1:0] s_sel, - output wire [NIN-1:0] s_stall, s_ack, - output wire [NIN*DW-1:0] s_idata, - output wire [NIN-1:0] s_err, - // - output reg m_cyc, m_stb, m_we, - output reg [AW-1:0] m_addr, - output reg [DW-1:0] m_data, - output reg [DW/8-1:0] m_sel, - input wire m_stall, m_ack, - input wire [DW-1:0] m_idata, - input wire m_err - // }}} - ); - - // Register/net declarations - // {{{ - genvar gk; - integer ik; - - wire arb_stall; - wire [NIN-1:0] grant; - reg [NIN-1:0] ack, err; - reg [DW-1:0] data; - - wire fifo_reset; - wire ack_wr, ack_rd; - reg [LGFIFO:0] fif_wraddr, fif_rdaddr; - wire [LGFIFO:0] ack_fill; - wire ack_empty, ack_full; - wire [NIN-1:0] ack_fifo_data; - - reg [NIN-1:0] flushing; - - reg nxt_stb, nxt_we; - reg [AW-1:0] nxt_addr; - reg [DW-1:0] nxt_data; - reg [DW/8-1:0] nxt_sel; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Arbitrate among sources - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - pktarbiter #( - .W(NIN) - ) u_arb ( - .i_clk(i_clk), .i_reset_n(!i_reset), - .i_req(s_stb & ~flushing), .i_stall(arb_stall), - .o_grant(grant) - ); - - assign arb_stall = m_stb && m_stall; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Log STBs, to know where to deliver ACKs - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign fifo_reset = i_reset || (m_cyc && m_err); - assign ack_wr =|(s_stb & ~s_stall); - assign ack_rd = m_ack; - -`ifdef FORMAL - // {{{ - wire [LGFIFO:0] f_first_addr, f_second_addr, - f_distance_to_first, f_distance_to_second; - wire f_first_in_fifo, f_second_in_fifo; - wire [NIN-1:0] f_first_data, f_second_data; - wire [LGFIFO:0] f_wraddr, f_rdaddr; - wire [NIN-1:0] f_ch_empty; - wire [NIN*(LGFIFO+1)-1:0] f_ch_last_addr; - // }}} -`endif - - sfifo #( - .BW(NIN), - .LGFLEN(LGFIFO) - ) u_ack_fifo ( - // {{{ - .i_clk(i_clk), .i_reset(fifo_reset), - .i_wr(ack_wr), .i_data(grant), - .o_full(ack_full), .o_fill(ack_fill), - .i_rd(ack_rd), .o_data(ack_fifo_data), - .o_empty(ack_empty) -`ifdef FORMAL - // {{{ - , .f_first_addr(f_first_addr), - .f_second_addr(f_second_addr), - .f_first_data(f_first_data), - .f_second_data(f_second_data), - .f_first_in_fifo(f_first_in_fifo), - .f_second_in_fifo(f_second_in_fifo), - .f_distance_to_first(f_distance_to_first), - .f_distance_to_second(f_distance_to_second), - .f_wraddr(f_wraddr), .f_rdaddr(f_rdaddr) - // }}} -`endif - // }}} - ); - - always @(posedge i_clk) - if (fifo_reset) - fif_wraddr <= 0; - else if (ack_wr && !ack_full) - fif_wraddr <= fif_wraddr + 1; - - always @(posedge i_clk) - if (fifo_reset) - fif_rdaddr <= 0; - else if (ack_rd && !ack_empty) - fif_rdaddr <= fif_rdaddr + 1; - -`ifdef FORMAL - always @(*) - if (!fifo_reset) - assert(fif_wraddr == f_wraddr); - - always @(*) - if (!fifo_reset) - assert(fif_rdaddr == f_rdaddr); -`endif - - // Need to do some extra work, just to deal with potential bus errors - // and dropped CYC lines - initial ack = 0; - initial err = 0; - generate for(gk=0; gk> (fc_checkid * (LGFIFO+1)); - assign fc_last_distance = fc_last_addr - f_rdaddr; - - assign f_known_data = (f_first_in_fifo && f_distance_to_first == 0) - || (f_second_in_fifo && f_distance_to_second == 0); - - assign f_known_checkid = - ((f_first_in_fifo && (f_first_data & (1<= f_distance_to_second) // *** - assert(fwbs_outstanding <= fc_last_distance+1 - - f_known_noncheckid + fc_ack); - end - - if (fc_last_addr == f_wraddr) - assert(ack_empty); - - // f_known_checkid+fc_ack<= fwbs_outstanding <= ack_fill+fc_ack - assert(fwbs_outstanding >= f_known_checkid + fc_ack); - assert(fwbs_outstanding <= ack_fill+fc_ack-f_known_noncheckid); - assert(fc_last_distance <= ack_fill); - assert(fwbs_outstanding <= fc_last_distance - + fc_ack + (ack_empty ? 0 :1)); - assert(fwbm_outstanding + (m_stb ? 1:0) + (fc_ack ? 1:0) - >= fwbs_outstanding); // *** - assert(ack_fill == fwbm_outstanding + (m_stb ? 1:0)); - if (fc_empty) - begin - assert(fwbs_outstanding == (fc_ack ? 1:0)); - assert(fc_last_distance == 0); - assert(ack_empty - || ((ack_fifo_data & (1< 0) - begin : GEN_SYNCHRONOUS - assign dw_reset = bw_reset_request; - assign dw_manual_trigger = bw_manual_trigger; - assign dw_disable_trigger = bw_disable_trigger; - assign bw_reset_complete = bw_reset_request; - end else begin : GEN_ASYNC_FLAGS - reg r_reset_complete; - (* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags; - reg [2:0] r_iflags; - - // Resets are synchronous to the bus clock, not the data clock - // so do a clock transfer here - initial { q_iflags, r_iflags } = 6'h0; - initial r_reset_complete = 1'b0; - always @(posedge i_data_clk) - begin - q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger }; - r_iflags <= q_iflags; - r_reset_complete <= (dw_reset); - end - - assign dw_reset = r_iflags[2]; - assign dw_manual_trigger = r_iflags[1]; - assign dw_disable_trigger = r_iflags[0]; - - (* ASYNC_REG = "TRUE" *) reg q_reset_complete, - qq_reset_complete; - // Pass an acknowledgement back from the data clock to the bus - // clock that the reset has been accomplished - initial q_reset_complete = 1'b0; - initial qq_reset_complete = 1'b0; - always @(posedge bus_clock) - begin - q_reset_complete <= r_reset_complete; - qq_reset_complete <= q_reset_complete; - end - - assign bw_reset_complete = qq_reset_complete; - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Set up the trigger - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // dw_trigger -- trigger wire, defined on the data clock - // {{{ - // Write with the i_clk, or input clock. All outputs read with the - // bus clock, or i_wb_clk as we've called it here. - assign dw_trigger = (dr_primed)&&( - ((i_trigger)&&(!dw_disable_trigger)) - ||(dw_manual_trigger)); - // }}} - - // dr_triggered - // {{{ - initial dr_triggered = 1'b0; - always @(posedge i_data_clk) - if (dw_reset) - dr_triggered <= 1'b0; - else if ((i_ce)&&(dw_trigger)) - dr_triggered <= 1'b1; - // }}} - - // - // Determine when memory is full and capture is complete - // - // Writes take place on the data clock - - // holdoff_counter - // {{{ - // The counter is unsigned - initial holdoff_counter = 0; - always @(posedge i_data_clk) - if (dw_reset) - holdoff_counter <= 0; - else if ((i_ce)&&(dr_triggered)&&(!dr_stopped)) - holdoff_counter <= holdoff_counter + 1'b1; - // }}} - - // dr_stopped - // {{{ - initial dr_stopped = 1'b0; - always @(posedge i_data_clk) - if ((!dr_triggered)||(dw_reset)) - dr_stopped <= 1'b0; - else if ((i_ce)&&(!dr_stopped)) - begin - if (HOLDOFFBITS > 1) // if (i_ce) - dr_stopped <= (holdoff_counter >= br_holdoff); - else if (HOLDOFFBITS <= 1) - dr_stopped <= ((i_ce)&&(dw_trigger)); - end - // }}} - - always @(posedge i_data_clk) - if (dw_reset) - dr_stop_pipe <= 0; - else if (i_ce) - dr_stop_pipe <= { dr_stop_pipe[(DLYSTOP-2):0], dr_stopped }; - - assign dw_final_stop = dr_stop_pipe[(DLYSTOP-1)]; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Write to memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // A big part of this scope is the run length of any particular - // data value. Hence, when the address line (i.e. data[31]) - // is high on decompression, the run length field will record an - // address difference. - // - // To implement this, we set our run length to zero any time the - // data changes, but increment it on all other clocks. Should the - // address difference get to our maximum value, we let it saturate - // rather than overflow. - - // dr_force_write, dr_force_inhibit - // {{{ - // - // The "dr_force_write" logic here is designed to make sure we write - // at least every MAX_STEP samples, and that we stop as soon as - // we are able. Hence, if an interface is slow - // and idle, we'll at least prime the scope, and even if the interface - // doesn't have enough transitions to fill our buffer, we'll at least - // fill the buffer with repeats. - // - initial ck_addr = 0; - initial dr_force_write = 1'b0; - always @(posedge i_data_clk) - if (dw_reset) - begin - dr_force_write <= 1'b1; - dr_force_inhibit <= 1'b0; - end else if (i_ce) - begin - dr_force_inhibit <= (dr_force_write); - if ((dr_run_timeout)&&(!dr_force_write)&&(!dr_force_inhibit)) - dr_force_write <= 1'b1; - else if (((dw_trigger)&&(!dr_triggered))||(!dr_primed)) - dr_force_write <= 1'b1; - else - dr_force_write <= 1'b0; - end - // }}} - - // ck_addr: Keep track of how long it has been since the last write - // {{{ - always @(posedge i_data_clk) - if (dw_reset) - ck_addr <= 0; - else if (i_ce) - begin - if ((dr_force_write)||(new_data)||(dr_stopped)) - ck_addr <= 0; - else - ck_addr <= ck_addr + 1'b1; - end - // }}} - - // dr_run_timeout - // {{{ - always @(posedge i_data_clk) - if (dw_reset) - dr_run_timeout <= 1'b1; - else if (i_ce) - dr_run_timeout <= (ck_addr >= MAX_STEP-1'b1); - // }}} - - // new_data - // {{{ - always @(posedge i_data_clk) - if (dw_reset) - new_data <= 1'b1; - else if (i_ce) - new_data <= (i_data != qd_data); - // }}} - - // qd_data - // {{{ - always @(posedge i_data_clk) - if (i_ce) - qd_data <= i_data; - // }}} - - // w_data - // {{{ - generate if (NELM == BUSW-1) - begin : GEN_WDATA - assign w_data = qd_data; - end else begin : GEN_DATA_FILL - assign w_data = { {(BUSW-NELM-1){1'b0}}, qd_data }; - end endgenerate - // }}} - - // imm_val, imm_adr, lst_val, lst_adr - // {{{ - // To do our RLE compression, we keep track of two registers: the most - // recent data to the device (imm_ prefix) and the data from one - // clock ago. This allows us to suppress writes to the scope which - // would otherwise be two address writes in a row. - initial lst_adr = 1'b1; - initial imm_adr = 1'b1; - always @(posedge i_data_clk) - if (dw_reset) - begin - imm_val <= 31'h0; - imm_adr <= 1'b1; - lst_val <= 31'h0; - lst_adr <= 1'b1; - end else if (i_ce) - begin - if ((new_data)||(dr_force_write)||(dr_stopped)) - begin - imm_val <= w_data; - imm_adr <= 1'b0; // Last thing we wrote was data - lst_val <= imm_val; - lst_adr <= imm_adr; - end else begin - imm_val <= ck_addr; // Minimum value here is '1' - imm_adr <= 1'b1; // This (imm) is an address - lst_val <= imm_val; - lst_adr <= imm_adr; - end - end - // }}} - - // record_ce - // {{{ - // Here's where we suppress writing pairs of address words to the - // scope at once. - // - initial record_ce = 1'b0; - always @(posedge i_data_clk) - record_ce <= (i_ce)&&((!lst_adr)||(!imm_adr))&&(!dr_stop_pipe[2]); - // }}} - - // r_data - // {{{ - always @(posedge i_data_clk) - r_data <= ((!lst_adr)||(!imm_adr)) - ? { lst_adr, lst_val } - : { {(32 - NELM){1'b0}}, qd_data }; - // }}} - - // - // Actually do our writes to memory. Record, via 'primed' when - // the memory is full. - // - // The 'waddr' address that we are using really crosses two clock - // domains. While writing and changing, it's in the data clock - // domain. Once stopped, it becomes part of the bus clock domain. - // The clock transfer on the stopped line handles the clock - // transfer for these signals. - // - - // waddr, dr_primed - // {{{ - initial waddr = {(LGMEM){1'b0}}; - initial dr_primed = 1'b0; - always @(posedge i_data_clk) - if (dw_reset) // For simulation purposes, supply a valid value - begin - waddr <= 0; // upon reset. - dr_primed <= 1'b0; - end else if (record_ce) - begin - // mem[waddr] <= i_data; - waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1}; - dr_primed <= (dr_primed)||(&waddr); - end - // }}} - - // mem[] <= r_data - // {{{ - always @(posedge i_data_clk) - if (record_ce) - mem[waddr] <= r_data; - // }}} - - - // - // - // - // Bus response - // - // - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Move the status signals back to the bus clock - // {{{ - //////////////////////////////////////////////////////////////////////// - // - generate if (SYNCHRONOUS > 0) - begin : SYNCHRONOUS_RETURN - assign bw_stopped = dw_final_stop; - assign bw_triggered = dr_triggered; - assign bw_primed = dr_primed; - end else begin : ASYNC_STATUS - // {{{ - // These aren't a problem, since none of these are strobe - // signals. They goes from low to high, and then stays high - // for many clocks. Swapping is thus easy--two flip flops to - // protect against meta-stability and we're done. - // - (* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags; - reg [2:0] r_oflags; - initial q_oflags = 3'h0; - initial r_oflags = 3'h0; - always @(posedge bus_clock) - if (bw_reset_request) - begin - q_oflags <= 3'h0; - r_oflags <= 3'h0; - end else begin - q_oflags <= { dw_final_stop, dr_triggered, dr_primed }; - r_oflags <= q_oflags; - end - - assign bw_stopped = r_oflags[2]; - assign bw_triggered = r_oflags[1]; - assign bw_primed = r_oflags[0]; - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Read from the memory, using the bus clock. Otherwise respond to bus - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Reads use the bus clock - assign bw_cyc_stb = (i_wb_stb); - - initial br_pre_wb_ack = 1'b0; - initial br_wb_ack = 1'b0; - always @(posedge bus_clock) - begin - if ((bw_reset_request)||(write_to_control)) - raddr <= 0; - else if ((read_from_data)&&(bw_stopped)) - raddr <= raddr + 1'b1; // Data read, when stopped - - br_pre_wb_ack <= bw_cyc_stb; - br_wb_ack <= (br_pre_wb_ack)&&(i_wb_cyc); - end - - assign o_wb_ack = br_wb_ack; - - always @(posedge bus_clock) - if (read_from_data) - this_addr <= raddr + waddr + 1'b1; - else - this_addr <= raddr + waddr; - - always @(posedge bus_clock) - nxt_mem <= mem[this_addr]; - - // holdoff sub-register - // {{{ - assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff; - generate if (HOLDOFFBITS < 20) - begin : GEN_FULL_HOLDOFF - assign full_holdoff[19:(HOLDOFFBITS)] = 0; - end endgenerate - // }}} - - assign bw_lgmem = LGMEM; - - // Bus read - // {{{ - always @(posedge bus_clock) - begin - if (!read_address) // Control register read - o_bus_data <= { bw_reset_request, - bw_stopped, - bw_triggered, - bw_primed, - bw_manual_trigger, - bw_disable_trigger, - (raddr == {(LGMEM){1'b0}}), - bw_lgmem, - full_holdoff }; - else if (!bw_stopped) // read, prior to stopping - // - // *WARNING*: THIS READ IS NOT PROTECTED FROM - // ASYNCHRONOUS COHERENCE ISSUES! - // - o_bus_data <= {1'b0, w_data };// Violates clk tfr rules - else // if (i_wb_addr) // Read from FIFO memory - o_bus_data <= nxt_mem; // mem[raddr+waddr]; - end - // }}} - - assign o_wb_data = o_bus_data; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Interrupt generation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial br_level_interrupt = 1'b0; - always @(posedge bus_clock) - if ((bw_reset_complete)||(bw_reset_request)) - br_level_interrupt<= 1'b0; - else - br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger); - - assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger) - &&(!br_level_interrupt); - // }}} - - // Make verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_bus_data[30:28], i_bus_data[25:HOLDOFFBITS], - i_wb_sel }; - // verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/wbscope/wbscope.v b/delete_later/rtl/wbscope/wbscope.v deleted file mode 100644 index 5381402..0000000 --- a/delete_later/rtl/wbscope/wbscope.v +++ /dev/null @@ -1,590 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbscope.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is a generic/library routine for providing a bus accessed -// 'scope' or (perhaps more appropriately) a bus accessed logic analyzer. -// The general operation is such that this 'scope' can record and report -// on any 32 bit value transiting through the FPGA. Once started and -// reset, the scope records a copy of the input data every time the clock -// ticks with the circuit enabled. That is, it records these values up -// until the trigger. Once the trigger goes high, the scope will record -// for br_holdoff more counts before stopping. Values may then be read -// from the buffer, oldest to most recent. After reading, the scope may -// then be reset for another run. -// -// In general, therefore, operation happens in this fashion: -// 1. A reset is issued. -// 2. Recording starts, in a circular buffer, and continues until -// 3. The trigger line is asserted. -// The scope registers the asserted trigger by setting -// the 'o_triggered' output flag. -// 4. A counter then ticks until the last value is written -// The scope registers that it has stopped recording by -// setting the 'o_stopped' output flag. -// 5. The scope recording is then paused until the next reset. -// 6. While stopped, the CPU can read the data from the scope -// 7. -- oldest to most recent -// 8. -- one value per i_rd&i_data_clk -// 9. Writes to the data register reset the address to the -// beginning of the buffer -// -// Although the data width DW is parameterized, it is not very changable, -// since the width is tied to the width of the data bus, as is the -// control word. Therefore changing the data width would require changing -// the interface. It's doable, but it would be a change to the interface. -// -// The SYNCHRONOUS parameter turns on and off meta-stability -// synchronization. Ideally a wishbone scope able to handle one or two -// clocks would have a changing number of ports as this SYNCHRONOUS -// parameter changed. Other than running another script to modify -// this, I don't know how to do that so ... we'll just leave it running -// off of two clocks or not. -// -// -// Internal to this routine, registers and wires are named with one of the -// following prefixes: -// -// i_ An input port to the routine -// o_ An output port of the routine -// br_ A register, controlled by the bus clock -// dr_ A register, controlled by the data clock -// bw_ A wire/net, controlled by the bus clock -// dw_ A wire/net, controlled by the data clock -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbscope #( - // {{{ - parameter [4:0] LGMEM = 5'd10, - parameter BUSW = 32, - parameter [0:0] SYNCHRONOUS=1, - parameter HOLDOFFBITS = 20, - parameter [(HOLDOFFBITS-1):0] DEFAULT_HOLDOFF = ((1<<(LGMEM-1))-4) - // }}} - ) ( - // {{{ - // The input signals that we wish to record - input wire i_data_clk, i_ce, i_trigger, - input wire [(BUSW-1):0] i_data, - // The WISHBONE bus for reading and configuring this scope - // {{{ - input wire i_wb_clk, i_wb_cyc, - i_wb_stb, i_wb_we, - input wire i_wb_addr, // One address line only - input wire [(BUSW-1):0] i_wb_data, - input wire [(BUSW/8-1):0] i_wb_sel, - output wire o_wb_stall, o_wb_ack, - output wire [(BUSW-1):0] o_wb_data, - // }}} - // And, finally, for a final flair --- offer to interrupt the - // CPU after our trigger has gone off. This line is equivalent - // to the scope being stopped. It is not maskable here. - output wire o_interrupt - // }}} - ); - - // Signal declarations - // {{{ - wire bus_clock; - wire read_from_data; - wire write_stb; - wire write_to_control; - reg read_address; - wire [31:0] i_bus_data; - reg [(LGMEM-1):0] raddr; - reg [(BUSW-1):0] mem[0:((1< 0) - begin : GEN_SYNCHRONOUS - assign dw_reset = bw_reset_request; - assign dw_manual_trigger = bw_manual_trigger; - assign dw_disable_trigger = bw_disable_trigger; - assign bw_reset_complete = bw_reset_request; - end else begin : GEN_ASYNC - reg r_reset_complete; - (* ASYNC_REG = "TRUE" *) reg [2:0] q_iflags; - reg [2:0] r_iflags; - - // Resets are synchronous to the bus clock, not the data clock - // so do a clock transfer here - initial { q_iflags, r_iflags } = 6'h0; - initial r_reset_complete = 1'b0; - always @(posedge i_data_clk) - begin - q_iflags <= { bw_reset_request, bw_manual_trigger, bw_disable_trigger }; - r_iflags <= q_iflags; - r_reset_complete <= (dw_reset); - end - - assign dw_reset = r_iflags[2]; - assign dw_manual_trigger = r_iflags[1]; - assign dw_disable_trigger = r_iflags[0]; - - (* ASYNC_REG = "TRUE" *) reg q_reset_complete, - qq_reset_complete; - // Pass an acknowledgement back from the data clock to the bus - // clock that the reset has been accomplished - initial q_reset_complete = 1'b0; - initial qq_reset_complete = 1'b0; - always @(posedge bus_clock) - begin - q_reset_complete <= r_reset_complete; - qq_reset_complete <= q_reset_complete; - end - - assign bw_reset_complete = qq_reset_complete; - -`ifdef FORMAL - always @(posedge gbl_clk) - if (f_past_valid_data) - begin - if ($rose(r_reset_complete)) - assert(bw_reset_request); - end - - always @(*) - case({ bw_reset_request, q_iflags[2], dw_reset, q_reset_complete, qq_reset_complete }) - 5'h00: begin end - 5'h10: begin end - 5'h18: begin end - 5'h1c: begin end - 5'h1e: begin end - 5'h1f: begin end - 5'h0f: begin end - 5'h07: begin end - 5'h03: begin end - 5'h01: begin end - default: assert(0); - endcase -`endif - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Set up the trigger - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // dw_trigger -- trigger wire, defined on the data clock - // {{{ - // Write with the i_clk, or input clock. All outputs read with the - // bus clock, or i_wb_clk as we've called it here. - assign dw_trigger = (dr_primed)&&( - ((i_trigger)&&(!dw_disable_trigger)) - ||(dw_manual_trigger)); - // }}} - - // dr_triggered - // {{{ - initial dr_triggered = 1'b0; - always @(posedge i_data_clk) - if (dw_reset) - dr_triggered <= 1'b0; - else if ((i_ce)&&(dw_trigger)) - dr_triggered <= 1'b1; - // }}} - - // - // Determine when memory is full and capture is complete - // - // Writes take place on the data clock - - // counter - // {{{ - // The counter is unsigned - initial counter = 0; - always @(posedge i_data_clk) - if (dw_reset) - counter <= 0; - else if ((i_ce)&&(dr_triggered)&&(!dr_stopped)) - counter <= counter + 1'b1; -`ifdef FORMAL - always @(*) - if (!dw_reset && !bw_reset_request) - assert(counter <= br_holdoff+1'b1); - always @(posedge i_data_clk) - assume(!(&br_holdoff)); - always @(posedge i_data_clk) - if (!dr_triggered) - assert(counter == 0); -`endif - // }}} - - // dr_stopped - // {{{ - initial dr_stopped = 1'b0; - always @(posedge i_data_clk) - if ((!dr_triggered)||(dw_reset)) - dr_stopped <= 1'b0; - else if (!dr_stopped) - begin - if (HOLDOFFBITS > 1) // if (i_ce) - dr_stopped <= (counter >= br_holdoff); - else if (HOLDOFFBITS <= 1) - dr_stopped <= ((i_ce)&&(dw_trigger)); - end - // }}} - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Write to memory - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - - // - // Actually do our writes to memory. Record, via 'primed' when - // the memory is full. - // - // The 'waddr' address that we are using really crosses two clock - // domains. While writing and changing, it's in the data clock - // domain. Once stopped, it becomes part of the bus clock domain. - // The clock transfer on the stopped line handles the clock - // transfer for these signals. - // - - // waddr, dr_primed - // {{{ - initial waddr = {(LGMEM){1'b0}}; - initial dr_primed = 1'b0; - always @(posedge i_data_clk) - if (dw_reset) // For simulation purposes, supply a valid value - begin - waddr <= 0; // upon reset. - dr_primed <= 1'b0; - end else if (i_ce && !dr_stopped) - begin - // mem[waddr] <= i_data; - waddr <= waddr + {{(LGMEM-1){1'b0}},1'b1}; - if (!dr_primed) - dr_primed <= (&waddr); - end - // }}} - - // wr_piped_data -- delay data to match the trigger - // {{{ - // Delay the incoming data so that we can get our trigger - // logic to line up with the data. The goal is to have a - // hold off of zero place the trigger in the last memory - // address. - generate - if (STOPDELAY == 0) - begin : NO_STOPDLY - // No delay ... just assign the wires to our input lines - assign wr_piped_data = i_data; - end else if (STOPDELAY == 1) - begin : GEN_ONE_STOPDLY - // - // Delay by one means just register this once - reg [(BUSW-1):0] data_pipe; - always @(posedge i_data_clk) - if (i_ce) - data_pipe <= i_data; - - assign wr_piped_data = data_pipe; - end else begin : GEN_STOPDELAY - // Arbitrary delay ... use a longer pipe - reg [(STOPDELAY*BUSW-1):0] data_pipe; - - always @(posedge i_data_clk) - if (i_ce) - data_pipe <= { data_pipe[((STOPDELAY-1)*BUSW-1):0], i_data }; - assign wr_piped_data = { data_pipe[(STOPDELAY*BUSW-1):((STOPDELAY-1)*BUSW)] }; - end endgenerate - // }}} - - // mem[] <= wr_piped_data - // {{{ - always @(posedge i_data_clk) - if ((i_ce)&&(!dr_stopped)) - mem[waddr] <= wr_piped_data; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Move the status signals back to the bus clock - // {{{ - //////////////////////////////////////////////////////////////////////// - // - generate if (SYNCHRONOUS > 0) - begin : SYNCHRONOUS_RETURN - assign bw_stopped = dr_stopped; - assign bw_triggered = dr_triggered; - assign bw_primed = dr_primed; - end else begin : ASYNC_STATUS - // {{{ - // These aren't a problem, since none of these are strobe - // signals. They goes from low to high, and then stays high - // for many clocks. Swapping is thus easy--two flip flops to - // protect against meta-stability and we're done. - // - (* ASYNC_REG = "TRUE" *) reg [2:0] q_oflags; - reg [2:0] r_oflags; - initial q_oflags = 3'h0; - initial r_oflags = 3'h0; - always @(posedge bus_clock) - if (bw_reset_request) - begin - q_oflags <= 3'h0; - r_oflags <= 3'h0; - end else begin - q_oflags <= { dr_stopped, dr_triggered, dr_primed }; - r_oflags <= q_oflags; - end - - assign bw_stopped = r_oflags[2]; - assign bw_triggered = r_oflags[1]; - assign bw_primed = r_oflags[0]; - // }}} -`ifdef FORMAL - always @(*) - if (!bw_reset_request) - begin - if (bw_primed) - assert(q_oflags[0] && dr_primed); - else if (q_oflags[0]) - assert(dr_primed); - - if (bw_triggered) - assert(q_oflags[1] && dr_triggered); - else if (q_oflags[1]) - assert(dr_triggered); - - if (bw_stopped) - assert(q_oflags[2] && dr_stopped); - else if (q_oflags[2]) - assert(dr_stopped); - end - -`endif - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Read from the memory, using the bus clock. Otherwise respond to bus - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Reads use the bus clock - assign bw_cyc_stb = (i_wb_stb); - - initial br_pre_wb_ack = 1'b0; - initial br_wb_ack = 1'b0; - always @(posedge bus_clock) - begin - if ((bw_reset_request)||(write_to_control)) - raddr <= 0; - else if ((read_from_data)&&(bw_stopped)) - raddr <= raddr + 1'b1; // Data read, when stopped - - br_pre_wb_ack <= bw_cyc_stb; - br_wb_ack <= (br_pre_wb_ack)&&(i_wb_cyc); - end - - assign o_wb_ack = (i_wb_cyc)&&(br_wb_ack); - - always @(posedge bus_clock) - if (read_from_data) - this_addr <= raddr + waddr + 1'b1; - else - this_addr <= raddr + waddr; - - always @(posedge bus_clock) - nxt_mem <= mem[this_addr]; - - // holdoff sub-register - // {{{ - assign full_holdoff[(HOLDOFFBITS-1):0] = br_holdoff; - generate if (HOLDOFFBITS < 20) - begin : GEN_FULL_HOLDOFF - assign full_holdoff[19:(HOLDOFFBITS)] = 0; - end endgenerate - // }}} - - assign bw_lgmem = LGMEM; - - // Bus read - // {{{ - always @(posedge bus_clock) - begin - if (!read_address) // Control register read - o_bus_data <= { bw_reset_request, - bw_stopped, - bw_triggered, - bw_primed, - bw_manual_trigger, - bw_disable_trigger, - (raddr == {(LGMEM){1'b0}}), - bw_lgmem, - full_holdoff }; - else if (!bw_stopped) // read, prior to stopping - // - // *WARNING*: THIS READ IS NOT PROTECTED FROM - // ASYNCHRONOUS COHERENCE ISSUES! - // - o_bus_data <= i_data; - else // if (i_wb_addr) // Read from FIFO memory - o_bus_data <= nxt_mem; // mem[raddr+waddr]; - end - // }}} - - assign o_wb_data = o_bus_data; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Interrupt generation - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial br_level_interrupt = 1'b0; - always @(posedge bus_clock) - if ((bw_reset_complete)||(bw_reset_request)) - br_level_interrupt<= 1'b0; - else - br_level_interrupt<= (bw_stopped)&&(!bw_disable_trigger); - - assign o_interrupt = (bw_stopped)&&(!bw_disable_trigger) - &&(!br_level_interrupt); - // }}} - - // Make verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_bus_data[30:28], i_bus_data[25:0], - i_wb_sel }; - // verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/wbuart/rxuart.v b/delete_later/rtl/wbuart/rxuart.v deleted file mode 100644 index 7cf67c9..0000000 --- a/delete_later/rtl/wbuart/rxuart.v +++ /dev/null @@ -1,509 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: rxuart.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Receive and decode inputs from a single UART line. -// -// -// To interface with this module, connect it to your system clock, -// pass it the 32 bit setup register (defined below) and the UART -// input. When data becomes available, the o_wr line will be asserted -// for one clock cycle. On parity or frame errors, the o_parity_err -// or o_frame_err lines will be asserted. Likewise, on a break -// condition, o_break will be asserted. These lines are self clearing. -// -// There is a synchronous reset line, logic high. -// -// Now for the setup register. The register is 32 bits, so that this -// UART may be set up over a 32-bit bus. -// -// i_setup[30] True if we are not using hardware flow control. This bit -// is ignored within this module, as any receive hardware flow -// control will need to be implemented elsewhere. -// -// i_setup[29:28] Indicates the number of data bits per word. This will -// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 -// for a six bit word, or 2'b11 for a five bit word. -// -// i_setup[27] Indicates whether or not to use one or two stop bits. -// Set this to one to expect two stop bits, zero for one. -// -// i_setup[26] Indicates whether or not a parity bit exists. Set this -// to 1'b1 to include parity. -// -// i_setup[25] Indicates whether or not the parity bit is fixed. Set -// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the -// parity to be set based upon data. (Both assume the parity -// enable value is set.) -// -// i_setup[24] This bit is ignored if parity is not used. Otherwise, -// in the case of a fixed parity bit, this bit indicates whether -// mark (1'b1) or space (1'b0) parity is used. Likewise if the -// parity is not fixed, a 1'b1 selects even parity, and 1'b0 -// selects odd. -// -// i_setup[23:0] Indicates the speed of the UART in terms of clocks. -// So, for example, if you have a 200 MHz clock and wish to -// run your UART at 9600 baud, you would take 200 MHz and divide -// by 9600 to set this value to 24'd20834. Likewise if you wished -// to run this serial port at 115200 baud from a 200 MHz clock, -// you would set the value to 24'd1736 -// -// Thus, to set the UART for the common setting of an 8-bit word, -// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you -// would want to set the setup value to: -// -// 32'h0006c8 // For 115,200 baud, 8 bit, no parity -// 32'h005161 // For 9600 baud, 8 bit, no parity -// -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module rxuart #( - // {{{ - // 8 data bits, no parity, (at least 1) stop bit - parameter [30:0] INITIAL_SETUP = 31'd868, - // States: (@ baud counter == 0) - // 0 First bit arrives - // ..7 Bits arrive - // 8 Stop bit (x1) - // 9 Stop bit (x2) - // c break condition - // d Waiting for the channel to go high - // e Waiting for the reset to complete - // f Idle state - localparam [3:0] RXU_BIT_ZERO = 4'h0, - RXU_BIT_ONE = 4'h1, - RXU_BIT_TWO = 4'h2, - RXU_BIT_THREE = 4'h3, - // RXU_BIT_FOUR = 4'h4, // UNUSED - // RXU_BIT_FIVE = 4'h5, // UNUSED - // RXU_BIT_SIX = 4'h6, // UNUSED - RXU_BIT_SEVEN = 4'h7, - RXU_PARITY = 4'h8, - RXU_STOP = 4'h9, - RXU_SECOND_STOP = 4'ha, - // Unused 4'hb - // Unused 4'hc - RXU_BREAK = 4'hd, - RXU_RESET_IDLE = 4'he, - RXU_IDLE = 4'hf - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - /* verilator lint_off UNUSED */ - input wire [30:0] i_setup, - /* verilator lint_on UNUSED */ - input wire i_uart_rx, - output reg o_wr, - output reg [7:0] o_data, - output reg o_break, - output reg o_parity_err, o_frame_err, - output wire o_ck_uart - // }}} - ); - - // Signal declarations - // {{{ - wire [27:0] clocks_per_baud, break_condition, half_baud; - wire [1:0] data_bits; - wire use_parity, parity_even, dblstop, fixd_parity; - reg [29:0] r_setup; - reg [3:0] state; - - reg [27:0] baud_counter; - reg zero_baud_counter; - reg q_uart, qq_uart, ck_uart; - reg [27:0] chg_counter; - reg line_synch; - reg half_baud_time; - reg [7:0] data_reg; - reg calc_parity; - reg pre_wr; - - assign clocks_per_baud = { 4'h0, r_setup[23:0] }; - // assign hw_flow_control = !r_setup[30]; - assign data_bits = r_setup[29:28]; - assign dblstop = r_setup[27]; - assign use_parity = r_setup[26]; - assign fixd_parity = r_setup[25]; - assign parity_even = r_setup[24]; - assign break_condition = { r_setup[23:0], 4'h0 }; - assign half_baud = { 5'h00, r_setup[23:1] }-28'h1; - - // }}} - - // ck_uart - // {{{ - // Since this is an asynchronous receiver, we need to register our - // input a couple of clocks over to avoid any problems with - // metastability. We do that here, and then ignore all but the - // ck_uart wire. - initial q_uart = 1'b0; - initial qq_uart = 1'b0; - initial ck_uart = 1'b0; - always @(posedge i_clk) - begin - q_uart <= i_uart_rx; - qq_uart <= q_uart; - ck_uart <= qq_uart; - end - // }}} - - // o_ck_uart - // {{{ - // In case anyone else wants this clocked, stabilized value, we - // offer it on our output. - assign o_ck_uart = ck_uart; - // }}} - - // chg_counter - // {{{ - // Keep track of the number of clocks since the last change. - // - // This is used to determine if we are in either a break or an idle - // condition, as discussed further below. - initial chg_counter = 28'h00; - always @(posedge i_clk) - if (i_reset) - chg_counter <= 28'h00; - else if (qq_uart != ck_uart) - chg_counter <= 28'h00; - else if (chg_counter < break_condition) - chg_counter <= chg_counter + 1; - // }}} - - // o_break - // {{{ - // Are we in a break condition? - // - // A break condition exists if the line is held low for longer than - // a data word. Hence, we keep track of when the last change occurred. - // If it was more than break_condition clocks ago, and the current input - // value is a 0, then we're in a break--and nothing can be read until - // the line idles again. - initial o_break = 1'b0; - always @(posedge i_clk) - o_break <= ((chg_counter >= break_condition)&&(~ck_uart))? 1'b1:1'b0; - // }}} - - // line_synch - // {{{ - // Are we between characters? - // - // The opposite of a break condition is where the line is held high - // for more clocks than would be in a character. When this happens, - // we know we have synchronization--otherwise, we might be sampling - // from within a data word. - // - // This logic is used later to hold the RXUART in a reset condition - // until we know we are between data words. At that point, we should - // be able to hold on to our synchronization. - initial line_synch = 1'b0; - always @(posedge i_clk) - line_synch <= ((chg_counter >= break_condition)&&(ck_uart)); - // }}} - - // half_baud_time - // {{{ - // Are we in the middle of a baud iterval? Specifically, are we - // in the middle of a start bit? Set this to high if so. We'll use - // this within our state machine to transition out of the IDLE - // state. - initial half_baud_time = 0; - always @(posedge i_clk) - half_baud_time <= (~ck_uart)&&(chg_counter >= half_baud); - // }}} - - // r_setup - // {{{ - // Allow our controlling processor to change our setup at any time - // outside of receiving/processing a character. - initial r_setup = INITIAL_SETUP[29:0]; - always @(posedge i_clk) - if (state >= RXU_RESET_IDLE) - r_setup <= i_setup[29:0]; - // }}} - - // state -- the monster state machine - // {{{ - // Our monster state machine. YIKES! - // - // Yeah, this may be more complicated than it needs to be. The basic - // progression is: - // RESET -> RESET_IDLE -> (when line is idle) -> IDLE - // IDLE -> bit 0 -> bit 1 -> bit_{ndatabits} -> - // (optional) PARITY -> STOP -> (optional) SECOND_STOP - // -> IDLE - // ANY -> (on break) BREAK -> IDLE - // - // There are 16 states, although all are not used. These are listed - // at the top of this file. - // - // Logic inputs (12): (I've tried to minimize this number) - // state (4) - // i_reset - // line_synch - // o_break - // ckuart - // half_baud_time - // zero_baud_counter - // use_parity - // dblstop - // Logic outputs (4): - // state - // - initial state = RXU_RESET_IDLE; - always @(posedge i_clk) - if (i_reset) - state <= RXU_RESET_IDLE; - else if (state == RXU_RESET_IDLE) - begin - // {{{ - if (line_synch) - // Goto idle state from a reset - state <= RXU_IDLE; - else // Otherwise, stay in this condition 'til reset - state <= RXU_RESET_IDLE; - // }}} - end else if (o_break) - begin // We are in a break condition - state <= RXU_BREAK; - end else if (state == RXU_BREAK) - begin // Goto idle state following return ck_uart going high - // {{{ - if (ck_uart) - state <= RXU_IDLE; - else - state <= RXU_BREAK; - // }}} - end else if (state == RXU_IDLE) - begin // Idle state, independent of baud counter - // {{{ - if ((~ck_uart)&&(half_baud_time)) - begin - // We are in the center of a valid start bit - case (data_bits) - 2'b00: state <= RXU_BIT_ZERO; - 2'b01: state <= RXU_BIT_ONE; - 2'b10: state <= RXU_BIT_TWO; - 2'b11: state <= RXU_BIT_THREE; - endcase - end else // Otherwise, just stay here in idle - state <= RXU_IDLE; - // }}} - end else if (zero_baud_counter) - begin - // {{{ - if (state < RXU_BIT_SEVEN) - // Data arrives least significant bit first. - // By the time this is clocked in, it's what - // you'll have. - state <= state + 1; - else if (state == RXU_BIT_SEVEN) - state <= (use_parity) ? RXU_PARITY:RXU_STOP; - else if (state == RXU_PARITY) - state <= RXU_STOP; - else if (state == RXU_STOP) - begin // Stop (or parity) bit(s) - if (~ck_uart) // On frame error, wait 4 ch idle - state <= RXU_RESET_IDLE; - else if (dblstop) - state <= RXU_SECOND_STOP; - else - state <= RXU_IDLE; - end else // state must equal RX_SECOND_STOP - begin - if (~ck_uart) // On frame error, wait 4 ch idle - state <= RXU_RESET_IDLE; - else - state <= RXU_IDLE; - end - // }}} - end - // }}} - - // data_reg -- Data bit capture logic. - // {{{ - // This is drastically simplified from the state machine above, based - // upon: 1) it doesn't matter what it is until the end of a captured - // byte, and 2) the data register will flush itself of any invalid - // data in all other cases. Hence, let's keep it real simple. - // The only trick, though, is that if we have parity, then the data - // register needs to be held through that state without getting - // updated. - always @(posedge i_clk) - if ((zero_baud_counter)&&(state != RXU_PARITY)) - data_reg <= { ck_uart, data_reg[7:1] }; - // }}} - - // calc_parity - // {{{ - // Parity calculation logic - // - // As with the data capture logic, all that must be known about this - // bit is that it is the exclusive-OR of all bits prior. The first - // of those will follow idle, so we set ourselves to zero on idle. - // Then, as we walk through the states of a bit, all will adjust this - // value up until the parity bit, where the value will be read. Setting - // it then or after will be irrelevant, so ... this should be good - // and simplified. Note--we don't need to adjust this on reset either, - // since the reset state will lead to the idle state where we'll be - // reset before any transmission takes place. - always @(posedge i_clk) - if (state == RXU_IDLE) - calc_parity <= 0; - else if (zero_baud_counter) - calc_parity <= calc_parity ^ ck_uart; - // }}} - - // o_parity_err -- Parity error logic - // {{{ - // Set during the parity bit interval, read during the last stop bit - // interval, cleared on BREAK, RESET_IDLE, or IDLE states. - initial o_parity_err = 1'b0; - always @(posedge i_clk) - if ((zero_baud_counter)&&(state == RXU_PARITY)) - begin - if (fixd_parity) - // Fixed parity bit--independent of any dat - // value. - o_parity_err <= (ck_uart ^ parity_even); - else if (parity_even) - // Parity even: The XOR of all bits including - // the parity bit must be zero. - o_parity_err <= (calc_parity != ck_uart); - else - // Parity odd: the parity bit must equal the - // XOR of all the data bits. - o_parity_err <= (calc_parity == ck_uart); - end else if (state >= RXU_BREAK) - o_parity_err <= 1'b0; - // }}} - - // o_frame_err -- Frame error determination - // {{{ - // For the purpose of this controller, a frame error is defined as a - // stop bit (or second stop bit, if so enabled) not being high midway - // through the stop baud interval. The frame error value is - // immediately read, so we can clear it under all other circumstances. - // Specifically, we want it clear in RXU_BREAK, RXU_RESET_IDLE, and - // most importantly in RXU_IDLE. - initial o_frame_err = 1'b0; - always @(posedge i_clk) - if ((zero_baud_counter)&&((state == RXU_STOP) - ||(state == RXU_SECOND_STOP))) - o_frame_err <= (o_frame_err)||(~ck_uart); - else if ((zero_baud_counter)||(state >= RXU_BREAK)) - o_frame_err <= 1'b0; - // }}} - - // pre_wr, o_data - // {{{ - // Our data bit logic doesn't need nearly the complexity of all that - // work above. Indeed, we only need to know if we are at the end of - // a stop bit, in which case we copy the data_reg into our output - // data register, o_data. - // - // We would also set o_wr to be true when this is the case, but ... we - // won't know if there is a frame error on the second stop bit for - // another baud interval yet. So, instead, we set up the logic so that - // we know on the next zero baud counter that we can write out. That's - // the purpose of pre_wr. - initial o_data = 8'h00; - initial pre_wr = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - pre_wr <= 1'b0; - o_data <= 8'h00; - end else if ((zero_baud_counter)&&(state == RXU_STOP)) - begin - pre_wr <= 1'b1; - case (data_bits) - 2'b00: o_data <= data_reg; - 2'b01: o_data <= { 1'b0, data_reg[7:1] }; - 2'b10: o_data <= { 2'b0, data_reg[7:2] }; - 2'b11: o_data <= { 3'b0, data_reg[7:3] }; - endcase - end else if ((zero_baud_counter)||(state == RXU_IDLE)) - pre_wr <= 1'b0; - // }}} - - // o_wr - // {{{ - // Create an output strobe, true for one clock only, once we know - // all we need to know. o_data will be set on the last baud interval, - // o_parity_err on the last parity baud interval (if it existed, - // cleared otherwise, so ... we should be good to go here.) - initial o_wr = 1'b0; - always @(posedge i_clk) - if ((zero_baud_counter)||(state == RXU_IDLE)) - o_wr <= (pre_wr)&&(!i_reset); - else - o_wr <= 1'b0; - // }}} - - // The baud counter - // {{{ - // This is used as a "clock divider" if you will, but the clock needs - // to be reset before any byte can be decoded. In all other respects, - // we set ourselves up for clocks_per_baud counts between baud - // intervals. - always @(posedge i_clk) - if (i_reset) - baud_counter <= clocks_per_baud-28'h01; - else if (zero_baud_counter) - baud_counter <= clocks_per_baud-28'h01; - else case(state) - RXU_RESET_IDLE:baud_counter <= clocks_per_baud-28'h01; - RXU_BREAK: baud_counter <= clocks_per_baud-28'h01; - RXU_IDLE: baud_counter <= clocks_per_baud-28'h01; - default: baud_counter <= baud_counter-28'h01; - endcase - // }}} - - // zero_baud_counter - // {{{ - // Rather than testing whether or not (baud_counter == 0) within our - // (already too complicated) state transition tables, we use - // zero_baud_counter to pre-charge that test on the clock - // before--cleaning up some otherwise difficult timing dependencies. - initial zero_baud_counter = 1'b0; - always @(posedge i_clk) - if (state == RXU_IDLE) - zero_baud_counter <= 1'b0; - else - zero_baud_counter <= (baud_counter == 28'h01); - // }}} -endmodule - - diff --git a/delete_later/rtl/wbuart/rxuartlite.v b/delete_later/rtl/wbuart/rxuartlite.v deleted file mode 100644 index 51bd40c..0000000 --- a/delete_later/rtl/wbuart/rxuartlite.v +++ /dev/null @@ -1,744 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: rxuartlite.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Receive and decode inputs from a single UART line. -// -// -// To interface with this module, connect it to your system clock, -// and a UART input. Set the parameter to the number of clocks per -// baud. When data becomes available, the o_wr line will be asserted -// for one clock cycle. -// -// This interface only handles 8N1 serial port communications. It does -// not handle the break, parity, or frame error conditions. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module rxuartlite #( - // {{{ - parameter TIMER_BITS = 10, -`ifdef FORMAL - parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof -`else - parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 868, // 115200 Baud at 100MHz -`endif - localparam TB = TIMER_BITS, - // - localparam [3:0] RXUL_BIT_ZERO = 4'h0, - // Verilator lint_off UNUSED - // These are used by the formal solver - localparam [3:0] RXUL_BIT_ONE = 4'h1, - localparam [3:0] RXUL_BIT_TWO = 4'h2, - localparam [3:0] RXUL_BIT_THREE = 4'h3, - localparam [3:0] RXUL_BIT_FOUR = 4'h4, - localparam [3:0] RXUL_BIT_FIVE = 4'h5, - localparam [3:0] RXUL_BIT_SIX = 4'h6, - localparam [3:0] RXUL_BIT_SEVEN = 4'h7, - // Verilator lint_on UNUSED - localparam [3:0] RXUL_STOP = 4'h8, - localparam [3:0] RXUL_WAIT = 4'h9, - localparam [3:0] RXUL_IDLE = 4'hf - // }}} - ) ( - // {{{ - input wire i_clk, - input wire i_uart_rx, - output reg o_wr, - output reg [7:0] o_data - // }}} - ); - - // Signal/register declarations - // {{{ - wire [(TB-1):0] half_baud; - reg [3:0] state; - - assign half_baud = { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] }; - reg [(TB-1):0] baud_counter; - reg zero_baud_counter; - - reg q_uart, qq_uart, ck_uart; - reg [(TB-1):0] chg_counter; - reg half_baud_time; - reg [7:0] data_reg; - // }}} - - // ck_uart - // {{{ - // Since this is an asynchronous receiver, we need to register our - // input a couple of clocks over to avoid any problems with - // metastability. We do that here, and then ignore all but the - // ck_uart wire. - initial q_uart = 1'b1; - initial qq_uart = 1'b1; - initial ck_uart = 1'b1; - always @(posedge i_clk) - { ck_uart, qq_uart, q_uart } <= { qq_uart, q_uart, i_uart_rx }; - // }}} - - // chg_counter - // {{{ - // Keep track of the number of clocks since the last change. - // - // This is used to determine if we are in either a break or an idle - // condition, as discussed further below. - initial chg_counter = {(TB){1'b1}}; - always @(posedge i_clk) - if (qq_uart != ck_uart) - chg_counter <= 0; - else if (chg_counter != { (TB){1'b1} }) - chg_counter <= chg_counter + 1; - // }}} - - // half_baud_time - // {{{ - // Are we in the middle of a baud iterval? Specifically, are we - // in the middle of a start bit? Set this to high if so. We'll use - // this within our state machine to transition out of the IDLE - // state. - initial half_baud_time = 0; - always @(posedge i_clk) - half_baud_time <= (!ck_uart)&&(chg_counter >= half_baud-1'b1-1'b1); - // }}} - - // state - // {{{ - initial state = RXUL_IDLE; - always @(posedge i_clk) - if (state == RXUL_IDLE) - begin // Idle state, independent of baud counter - // {{{ - // By default, just stay in the IDLE state - state <= RXUL_IDLE; - if ((!ck_uart)&&(half_baud_time)) - // UNLESS: We are in the center of a valid - // start bit - state <= RXUL_BIT_ZERO; - // }}} - end else if ((state >= RXUL_WAIT)&&(ck_uart)) - state <= RXUL_IDLE; - else if (zero_baud_counter) - begin - // {{{ - if (state <= RXUL_STOP) - // Data arrives least significant bit first. - // By the time this is clocked in, it's what - // you'll have. - state <= state + 1; - // }}} - end - // }}} - - // data_reg - // {{{ - // Data bit capture logic. - // - // This is drastically simplified from the state machine above, based - // upon: 1) it doesn't matter what it is until the end of a captured - // byte, and 2) the data register will flush itself of any invalid - // data in all other cases. Hence, let's keep it real simple. - always @(posedge i_clk) - if ((zero_baud_counter)&&(state != RXUL_STOP)) - data_reg <= { qq_uart, data_reg[7:1] }; - // }}} - - // o_wr, o_data - // {{{ - // Our data bit logic doesn't need nearly the complexity of all that - // work above. Indeed, we only need to know if we are at the end of - // a stop bit, in which case we copy the data_reg into our output - // data register, o_data, and tell others (for one clock) that data is - // available. - // - initial o_wr = 1'b0; - initial o_data = 8'h00; - always @(posedge i_clk) - if ((zero_baud_counter)&&(state == RXUL_STOP)&&(ck_uart)) - begin - o_wr <= 1'b1; - o_data <= data_reg; - end else - o_wr <= 1'b0; - // }}} - - // baud_counter -- The baud counter - // {{{ - // This is used as a "clock divider" if you will, but the clock needs - // to be reset before any byte can be decoded. In all other respects, - // we set ourselves up for CLOCKS_PER_BAUD counts between baud - // intervals. - initial baud_counter = 0; - always @(posedge i_clk) - if (((state==RXUL_IDLE))&&(!ck_uart)&&(half_baud_time)) - baud_counter <= CLOCKS_PER_BAUD-1'b1; - else if (state == RXUL_WAIT) - baud_counter <= 0; - else if ((zero_baud_counter)&&(state < RXUL_STOP)) - baud_counter <= CLOCKS_PER_BAUD-1'b1; - else if (!zero_baud_counter) - baud_counter <= baud_counter-1'b1; - // }}} - - // zero_baud_counter - // {{{ - // Rather than testing whether or not (baud_counter == 0) within our - // (already too complicated) state transition tables, we use - // zero_baud_counter to pre-charge that test on the clock - // before--cleaning up some otherwise difficult timing dependencies. - initial zero_baud_counter = 1'b1; - always @(posedge i_clk) - if ((state == RXUL_IDLE)&&(!ck_uart)&&(half_baud_time)) - zero_baud_counter <= 1'b0; - else if (state == RXUL_WAIT) - zero_baud_counter <= 1'b1; - else if ((zero_baud_counter)&&(state < RXUL_STOP)) - zero_baud_counter <= 1'b0; - else if (baud_counter == 1) - zero_baud_counter <= 1'b1; - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// - // Declarations - // {{{ -`ifdef FORMAL -`define FORMAL_VERILATOR -`else -`ifdef VERILATOR -`define FORMAL_VERILATOR -`endif -`endif - -`ifdef FORMAL - localparam F_CKRES = 10; - - (* anyseq *) wire f_tx_start; - (* anyconst *) wire [(F_CKRES-1):0] f_tx_step; - (* gclk *) wire gbl_clk; - reg f_tx_zclk; - reg [(TB-1):0] f_tx_timer; - wire [7:0] f_rx_newdata; - reg [TB-1:0] f_tx_baud; - wire f_tx_zbaud; - - wire [(TB-1):0] f_max_baud_difference; - reg [(TB-1):0] f_baud_difference; - reg [(TB+3):0] f_tx_count, f_rx_count; - (* anyseq *) wire [7:0] f_tx_data; - - wire f_txclk; - reg [1:0] f_rx_clock; - reg [(F_CKRES-1):0] f_tx_clock; - reg f_past_valid, f_past_valid_tx; - - reg [9:0] f_tx_reg; - reg f_tx_busy; - - // }}} - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - initial f_rx_clock = 3'h0; - always @(posedge gbl_clk) - f_rx_clock <= f_rx_clock + 1'b1; - - always @(*) - assume(i_clk == f_rx_clock[1]); - - - //////////////////////////////////////////////////////////////////////// - // - // Assume a transmitted signal - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // First, calculate the transmit clock - localparam [(F_CKRES-1):0] F_MIDSTEP = { 2'b01, {(F_CKRES-2){1'b0}} }; - // - // Need to allow us to slip by half a baud clock over 10 baud intervals - // - // (F_STEP / (2^F_CKRES)) * (CLOCKS_PER_BAUD)*10 < CLOCKS_PER_BAUD/2 - // F_STEP * 2 * 10 < 2^F_CKRES - localparam [(F_CKRES-1):0] F_HALFSTEP= F_MIDSTEP/32; - localparam [(F_CKRES-1):0] F_MINSTEP = F_MIDSTEP - F_HALFSTEP + 1; - localparam [(F_CKRES-1):0] F_MAXSTEP = F_MIDSTEP + F_HALFSTEP - 1; - - initial assert(F_MINSTEP <= F_MIDSTEP); - initial assert(F_MIDSTEP <= F_MAXSTEP); - - // assume((f_tx_step >= F_MINSTEP)&&(f_tx_step <= F_MAXSTEP)); - // - // - always @(*) assume((f_tx_step == F_MINSTEP) - ||(f_tx_step == F_MIDSTEP) - ||(f_tx_step == F_MAXSTEP)); - - always @(posedge gbl_clk) - f_tx_clock <= f_tx_clock + f_tx_step; - - assign f_txclk = f_tx_clock[F_CKRES-1]; - // - initial f_past_valid_tx = 1'b0; - always @(posedge f_txclk) - f_past_valid_tx <= 1'b1; - - initial assume(i_uart_rx); - - //////////////////////////////////////////////////////////////////////// - // - // The simulated timing generator - - always @(*) - if (f_tx_busy) - assume(!f_tx_start); - - initial f_tx_baud = 0; - always @(posedge f_txclk) - if (f_tx_zbaud && (f_tx_busy || f_tx_start)) - f_tx_baud <= CLOCKS_PER_BAUD-1; - else if (!f_tx_zbaud) - f_tx_baud <= f_tx_baud - 1; - - always @(*) - assert(f_tx_baud < CLOCKS_PER_BAUD); - - always @(*) - if (!f_tx_busy) - assert(f_tx_baud == 0); - - assign f_tx_zbaud = (f_tx_baud == 0); - - // But only if we aren't busy - initial assume(f_tx_data == 0); - always @(posedge f_txclk) - if ((!f_tx_zbaud)||(f_tx_busy)||(!f_tx_start)) - assume(f_tx_data == $past(f_tx_data)); - - // Force the data to change on a clock only - always @(posedge gbl_clk) - if ((f_past_valid)&&(!$rose(f_txclk))) - assume($stable(f_tx_data)); - else if (f_tx_busy) - assume($stable(f_tx_data)); - - // - always @(posedge gbl_clk) - if ((!f_past_valid)||(!$rose(f_txclk))) - begin - assume($stable(f_tx_start)); - assume($stable(f_tx_data)); - end - - // - // - // - - // Here's the transmitter itself (roughly) - initial f_tx_busy = 1'b0; - initial f_tx_reg = 0; - always @(posedge f_txclk) - if (!f_tx_zbaud) - begin - assert(f_tx_busy); - end else begin - f_tx_reg <= { 1'b0, f_tx_reg[9:1] }; - if (f_tx_start) - f_tx_reg <= { 1'b1, f_tx_data, 1'b0 }; - end - - // Create a busy flag that we'll use - always @(*) - if (!f_tx_zbaud) - f_tx_busy <= 1'b1; - else if (|f_tx_reg) - f_tx_busy <= 1'b1; - else - f_tx_busy <= 1'b0; - - // - // Tie the TX register to the TX data - always @(posedge f_txclk) - if (f_tx_reg[9]) - begin - assert(f_tx_reg[8:0] == { f_tx_data, 1'b0 }); - end else if (f_tx_reg[8]) - begin - assert(f_tx_reg[7:0] == f_tx_data[7:0] ); - end else if (f_tx_reg[7]) - begin - assert(f_tx_reg[6:0] == f_tx_data[7:1] ); - end else if (f_tx_reg[6]) - begin - assert(f_tx_reg[5:0] == f_tx_data[7:2] ); - end else if (f_tx_reg[5]) - begin - assert(f_tx_reg[4:0] == f_tx_data[7:3] ); - end else if (f_tx_reg[4]) - begin - assert(f_tx_reg[3:0] == f_tx_data[7:4] ); - end else if (f_tx_reg[3]) - begin - assert(f_tx_reg[2:0] == f_tx_data[7:5] ); - end else if (f_tx_reg[2]) - begin - assert(f_tx_reg[1:0] == f_tx_data[7:6] ); - end else if (f_tx_reg[1]) - begin - assert(f_tx_reg[0] == f_tx_data[7]); - end - - // Our counter since we start - initial f_tx_count = 0; - always @(posedge f_txclk) - if (!f_tx_busy) - f_tx_count <= 0; - else - f_tx_count <= f_tx_count + 1'b1; - - always @(*) - if (f_tx_reg == 10'h0) - assume(i_uart_rx); - else - assume(i_uart_rx == f_tx_reg[0]); - - // - // Make sure the absolute transmit clock timer matches our state - // - always @(posedge f_txclk) - if (!f_tx_busy) - begin - if ((!f_past_valid_tx)||(!$past(f_tx_busy))) - assert(f_tx_count == 0); - end else if (f_tx_reg[9]) - begin - assert(f_tx_count == - CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[8]) - begin - assert(f_tx_count == - 2 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[7]) - begin - assert(f_tx_count == - 3 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[6]) - begin - assert(f_tx_count == - 4 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[5]) - begin - assert(f_tx_count == - 5 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[4]) - begin - assert(f_tx_count == - 6 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[3]) - begin - assert(f_tx_count == - 7 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[2]) - begin - assert(f_tx_count == - 8 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[1]) - begin - assert(f_tx_count == - 9 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else if (f_tx_reg[0]) - begin - assert(f_tx_count == - 10 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end else begin - assert(f_tx_count == - 11 * CLOCKS_PER_BAUD -1 -f_tx_baud); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Receiver - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - // Count RX clocks since the start of the first stop bit, measured in - // rx clocks - initial f_rx_count = 0; - always @(posedge i_clk) - if (state == RXUL_IDLE) - f_rx_count = (!ck_uart) ? (chg_counter+2) : 0; - else - f_rx_count <= f_rx_count + 1'b1; - - always @(posedge i_clk) - case(state) - 0: assert(f_rx_count == half_baud + (CLOCKS_PER_BAUD-baud_counter)); - 1: assert(f_rx_count == half_baud + 2 * CLOCKS_PER_BAUD - - baud_counter); - 2: assert(f_rx_count == half_baud + 3 * CLOCKS_PER_BAUD - - baud_counter); - 3: assert(f_rx_count == half_baud + 4 * CLOCKS_PER_BAUD - - baud_counter); - 4: assert(f_rx_count == half_baud + 5 * CLOCKS_PER_BAUD - - baud_counter); - 5: assert(f_rx_count == half_baud + 6 * CLOCKS_PER_BAUD - - baud_counter); - 6: assert(f_rx_count == half_baud + 7 * CLOCKS_PER_BAUD - - baud_counter); - 7: assert(f_rx_count == half_baud + 8 * CLOCKS_PER_BAUD - - baud_counter); - 8: assert((f_rx_count == half_baud + 9 * CLOCKS_PER_BAUD - - baud_counter) - ||(f_rx_count == half_baud + 10 * CLOCKS_PER_BAUD - - baud_counter)); - 9: begin end - 4'hf: begin end - default: - assert(1'b0); - endcase - - always @(*) - assert( ((!zero_baud_counter) - &&(state == RXUL_IDLE) - &&(baud_counter == 0)) - ||((zero_baud_counter)&&(baud_counter == 0)) - ||((!zero_baud_counter)&&(baud_counter != 0))); - - always @(posedge i_clk) - if (!f_past_valid) - assert((state == RXUL_IDLE)&&(baud_counter == 0) - &&(zero_baud_counter)); - - always @(*) - begin - assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h2); - assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h4); - assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h5); - assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h6); - assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'h9); - assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'ha); - assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hb); - assert({ ck_uart,qq_uart,q_uart,i_uart_rx } != 4'hd); - end - - always @(posedge i_clk) - if ((f_past_valid)&&($past(state) >= RXUL_WAIT)&&($past(ck_uart))) - assert(state == RXUL_IDLE); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(state) >= RXUL_WAIT) - &&(($past(state) != RXUL_IDLE)||(state == RXUL_IDLE))) - assert(zero_baud_counter); - - // Calculate an absolute value of the difference between the two baud - // clocks - always @(posedge i_clk) - if ((f_past_valid)&&($past(state)==RXUL_IDLE)&&(state == RXUL_IDLE)) - begin - assert(($past(ck_uart)) - ||(chg_counter <= - { 1'b0, CLOCKS_PER_BAUD[(TB-1):1] })); - end - - always @(posedge f_txclk) - if (!f_past_valid_tx) - assert((state == RXUL_IDLE)&&(baud_counter == 0) - &&(zero_baud_counter)&&(!f_tx_busy)); - - wire [(TB+3):0] f_tx_count_two_clocks_ago; - assign f_tx_count_two_clocks_ago = f_tx_count - 2; - always @(*) - if (f_tx_count >= f_rx_count + 2) - f_baud_difference = f_tx_count_two_clocks_ago - f_rx_count; - else - f_baud_difference = f_rx_count - f_tx_count_two_clocks_ago; - - localparam F_SYNC_DLY = 8; - - reg [(TB+4+F_CKRES-1):0] f_sub_baud_difference; - reg [F_CKRES-1:0] ck_tx_clock; - reg [((F_SYNC_DLY-1)*F_CKRES)-1:0] q_tx_clock; - reg [TB+3:0] ck_tx_count; - reg [(F_SYNC_DLY-1)*(TB+4)-1:0] q_tx_count; - initial q_tx_count = 0; - initial ck_tx_count = 0; - initial q_tx_clock = 0; - initial ck_tx_clock = 0; - always @(posedge gbl_clk) - { ck_tx_clock, q_tx_clock } <= { q_tx_clock, f_tx_clock }; - always @(posedge gbl_clk) - { ck_tx_count, q_tx_count } <= { q_tx_count, f_tx_count }; - - - reg [TB+4+F_CKRES-1:0] f_ck_tx_time, f_rx_time; - always @(*) - f_ck_tx_time = { ck_tx_count, !ck_tx_clock[F_CKRES-1], - ck_tx_clock[F_CKRES-2:0] }; - always @(*) - f_rx_time = { f_rx_count, !f_rx_clock[1], f_rx_clock[0], - {(F_CKRES-2){1'b0}} }; - - reg [TB+4+F_CKRES-1:0] f_signed_difference; - always @(*) - f_signed_difference = f_ck_tx_time - f_rx_time; - - always @(*) - if (f_signed_difference[TB+4+F_CKRES-1]) - f_sub_baud_difference = -f_signed_difference; - else - f_sub_baud_difference = f_signed_difference; - - always @(posedge gbl_clk) - if (state == RXUL_WAIT) - assert((!f_tx_busy)||(f_tx_reg[9:1] == 0)); - - always @(posedge gbl_clk) - if (state == RXUL_IDLE) - begin - assert((!f_tx_busy)||(f_tx_reg[9])||(f_tx_reg[9:1]==0)); - if (ck_uart) - assert((f_tx_reg[9:1]==0)||(f_tx_count < (3 + CLOCKS_PER_BAUD/2))); - end else if (state == 0) - begin - assert(f_sub_baud_difference - <= 2 * ((CLOCKS_PER_BAUD< 6)) - // assert(i_uart_rx == ck_uart); - - // Make sure the data register matches - always @(posedge i_clk) - case(state) - 4'h0: assert(!data_reg[7]); - 4'h1: assert((data_reg[7] == $past(f_tx_data[0]))&&(!data_reg[6])); - 4'h2: assert(data_reg[7:6] == $past(f_tx_data[1:0])); - 4'h3: assert(data_reg[7:5] == $past(f_tx_data[2:0])); - 4'h4: assert(data_reg[7:4] == $past(f_tx_data[3:0])); - 4'h5: assert(data_reg[7:3] == $past(f_tx_data[4:0])); - 4'h6: assert(data_reg[7:2] == $past(f_tx_data[5:0])); - 4'h7: assert(data_reg[7:1] == $past(f_tx_data[6:0])); - 4'h8: assert(data_reg[7:0] == $past(f_tx_data[7:0])); - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - always @(posedge i_clk) - cover(o_wr); // Step 626, takes about 20mins - - always @(posedge i_clk) - begin - cover(!ck_uart); - cover((f_past_valid)&&($rose(ck_uart))); // 82 - cover((zero_baud_counter)&&(state == RXUL_BIT_ZERO)); // 110 - cover((zero_baud_counter)&&(state == RXUL_BIT_ONE)); // 174 - cover((zero_baud_counter)&&(state == RXUL_BIT_TWO)); // 238 - cover((zero_baud_counter)&&(state == RXUL_BIT_THREE));// 302 - cover((zero_baud_counter)&&(state == RXUL_BIT_FOUR)); // 366 - cover((zero_baud_counter)&&(state == RXUL_BIT_FIVE)); // 430 - cover((zero_baud_counter)&&(state == RXUL_BIT_SIX)); // 494 - cover((zero_baud_counter)&&(state == RXUL_BIT_SEVEN));// 558 - cover((zero_baud_counter)&&(state == RXUL_STOP)); // 622 - cover((zero_baud_counter)&&(state == RXUL_WAIT)); // 626 - end -`endif - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Properties to test via Verilator *and* formal - // {{{ - //////////////////////////////////////////////////////////////////////// - // -`ifdef FORMAL_VERILATOR - // FORMAL properties which can be tested via Verilator as well as - // Yosys FORMAL - always @(*) - assert((state == 4'hf)||(state <= RXUL_WAIT)); - always @(*) - assert(zero_baud_counter == (baud_counter == 0)? 1'b1:1'b0); - always @(*) - assert(baud_counter <= CLOCKS_PER_BAUD-1'b1); - // }}} -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wbuart/txuart.v b/delete_later/rtl/wbuart/txuart.v deleted file mode 100644 index ab8c7c2..0000000 --- a/delete_later/rtl/wbuart/txuart.v +++ /dev/null @@ -1,1207 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: txuart.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Transmit outputs over a single UART line. -// -// To interface with this module, connect it to your system clock, -// pass it the 32 bit setup register (defined below) and the byte -// of data you wish to transmit. Strobe the i_wr line high for one -// clock cycle, and your data will be off. Wait until the 'o_busy' -// line is low before strobing the i_wr line again--this implementation -// has NO BUFFER, so strobing i_wr while the core is busy will just -// cause your data to be lost. The output will be placed on the o_txuart -// output line. If you wish to set/send a break condition, assert the -// i_break line otherwise leave it low. -// -// There is a synchronous reset line, logic high. -// -// Now for the setup register. The register is 32 bits, so that this -// UART may be set up over a 32-bit bus. -// -// i_setup[30] Set this to zero to use hardware flow control, and to -// one to ignore hardware flow control. Only works if the hardware -// flow control has been properly wired. -// -// If you don't want hardware flow control, fix the i_rts bit to -// 1'b1, and let the synthesys tools optimize out the logic. -// -// i_setup[29:28] Indicates the number of data bits per word. This will -// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 -// for a six bit word, or 2'b11 for a five bit word. -// -// i_setup[27] Indicates whether or not to use one or two stop bits. -// Set this to one to expect two stop bits, zero for one. -// -// i_setup[26] Indicates whether or not a parity bit exists. Set this -// to 1'b1 to include parity. -// -// i_setup[25] Indicates whether or not the parity bit is fixed. Set -// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the -// parity to be set based upon data. (Both assume the parity -// enable value is set.) -// -// i_setup[24] This bit is ignored if parity is not used. Otherwise, -// in the case of a fixed parity bit, this bit indicates whether -// mark (1'b1) or space (1'b0) parity is used. Likewise if the -// parity is not fixed, a 1'b1 selects even parity, and 1'b0 -// selects odd. -// -// i_setup[23:0] Indicates the speed of the UART in terms of clocks. -// So, for example, if you have a 200 MHz clock and wish to -// run your UART at 9600 baud, you would take 200 MHz and divide -// by 9600 to set this value to 24'd20834. Likewise if you wished -// to run this serial port at 115200 baud from a 200 MHz clock, -// you would set the value to 24'd1736 -// -// Thus, to set the UART for the common setting of an 8-bit word, -// one stop bit, no parity, and 115200 baud over a 200 MHz clock, you -// would want to set the setup value to: -// -// 32'h0006c8 // For 115,200 baud, 8 bit, no parity -// 32'h005161 // For 9600 baud, 8 bit, no parity -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module txuart #( - // {{{ - parameter [30:0] INITIAL_SETUP = 31'd868, - // - localparam [3:0] TXU_BIT_ZERO = 4'h0, - localparam [3:0] TXU_BIT_ONE = 4'h1, - localparam [3:0] TXU_BIT_TWO = 4'h2, - localparam [3:0] TXU_BIT_THREE = 4'h3, - // localparam [3:0] TXU_BIT_FOUR = 4'h4, - // localparam [3:0] TXU_BIT_FIVE = 4'h5, - // localparam [3:0] TXU_BIT_SIX = 4'h6, - localparam [3:0] TXU_BIT_SEVEN = 4'h7, - localparam [3:0] TXU_PARITY = 4'h8, - localparam [3:0] TXU_STOP = 4'h9, - localparam [3:0] TXU_SECOND_STOP = 4'ha, - // - localparam [3:0] TXU_BREAK = 4'he, - localparam [3:0] TXU_IDLE = 4'hf - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - input wire [30:0] i_setup, - input wire i_break, - input wire i_wr, - input wire [7:0] i_data, - // Hardware flow control Ready-To-Send bit. Set this to one to - // use the core without flow control. (A more appropriate name - // would be the Ready-To-Receive bit ...) - input wire i_cts_n, - // And the UART input line itself - output reg o_uart_tx, - // A line to tell others when we are ready to accept data. If - // (i_wr)&&(!o_busy) is ever true, then the core has accepted a - // byte for transmission. - output wire o_busy - // }}} - ); - - // Signal declarations - // {{{ - wire [27:0] clocks_per_baud, break_condition; - wire [1:0] i_data_bits, data_bits; - wire use_parity, parity_odd, dblstop, fixd_parity, - fixdp_value, hw_flow_control, i_parity_odd; - reg [30:0] r_setup; - assign clocks_per_baud = { 4'h0, r_setup[23:0] }; - assign break_condition = { r_setup[23:0], 4'h0 }; - assign hw_flow_control = !r_setup[30]; - assign i_data_bits = i_setup[29:28]; - assign data_bits = r_setup[29:28]; - assign dblstop = r_setup[27]; - assign use_parity = r_setup[26]; - assign fixd_parity = r_setup[25]; - assign i_parity_odd = i_setup[24]; - assign parity_odd = r_setup[24]; - assign fixdp_value = r_setup[24]; - - reg [27:0] baud_counter; - reg [3:0] state; - reg [7:0] lcl_data; - reg calc_parity, r_busy, zero_baud_counter, last_state; - reg q_cts_n, qq_cts_n, ck_cts; - // }}} - - // CTS: ck_cts - // {{{ - // First step ... handle any hardware flow control, if so enabled. - // - // Clock in the flow control data, two clocks to avoid metastability - // Default to using hardware flow control (uart_setup[30]==0 to use it). - // Set this high order bit off if you do not wish to use it. - // - // While we might wish to give initial values to q_rts and ck_cts, - // 1) it's not required since the transmitter starts in a long wait - // state, and 2) doing so will prevent the synthesizer from optimizing - // this pin in the case it is hard set to 1'b1 external to this - // peripheral. - // - // initial q_cts_n = 1'b1; - // initial qq_cts_n = 1'b1; - // initial ck_cts = 1'b0; - always @(posedge i_clk) - { qq_cts_n, q_cts_n } <= { q_cts_n, i_cts_n }; - always @(posedge i_clk) - ck_cts <= (!qq_cts_n)||(!hw_flow_control); - // }}} - - // r_busy, state - // {{{ - initial r_busy = 1'b1; - initial state = TXU_IDLE; - always @(posedge i_clk) - if (i_reset) - begin - r_busy <= 1'b1; - state <= TXU_IDLE; - end else if (i_break) - begin - state <= TXU_BREAK; - r_busy <= 1'b1; - end else if (!zero_baud_counter) - begin // r_busy needs to be set coming into here - r_busy <= 1'b1; - end else if (state == TXU_BREAK) - begin - state <= TXU_IDLE; - r_busy <= !ck_cts; - end else if (state == TXU_IDLE) // STATE_IDLE - begin - if ((i_wr)&&(!r_busy)) - begin // Immediately start us off with a start bit - r_busy <= 1'b1; - case(i_data_bits) - 2'b00: state <= TXU_BIT_ZERO; - 2'b01: state <= TXU_BIT_ONE; - 2'b10: state <= TXU_BIT_TWO; - 2'b11: state <= TXU_BIT_THREE; - endcase - end else begin // Stay in idle - r_busy <= !ck_cts; - end - end else begin - // One clock tick in each of these states ... - // baud_counter <= clocks_per_baud - 28'h01; - r_busy <= 1'b1; - if (state[3] == 0) // First 8 bits - begin - if (state == TXU_BIT_SEVEN) - state <= (use_parity)? TXU_PARITY:TXU_STOP; - else - state <= state + 1; - end else if (state == TXU_PARITY) - begin - state <= TXU_STOP; - end else if (state == TXU_STOP) - begin // two stop bit(s) - if (dblstop) - state <= TXU_SECOND_STOP; - else - state <= TXU_IDLE; - end else // `TXU_SECOND_STOP and default: - begin - state <= TXU_IDLE; // Go back to idle - // Still r_busy, since we need to wait - // for the baud clock to finish counting - // out this last bit. - end - end - // }}} - - // o_busy - // {{{ - // This is a wire, designed to be true is we are ever busy above. - // originally, this was going to be true if we were ever not in the - // idle state. The logic has since become more complex, hence we have - // a register dedicated to this and just copy out that registers value. - assign o_busy = (r_busy); - // }}} - - // r_setup - // {{{ - // Our setup register. Accept changes between any pair of transmitted - // words. The register itself has many fields to it. These are - // broken out up top, and indicate what 1) our baud rate is, 2) our - // number of stop bits, 3) what type of parity we are using, and 4) - // the size of our data word. - initial r_setup = INITIAL_SETUP; - always @(posedge i_clk) - if (!o_busy) - r_setup <= i_setup; - // }}} - - // lcl_data - // {{{ - // This is our working copy of the i_data register which we use - // when transmitting. It is only of interest during transmit, and is - // allowed to be whatever at any other time. Hence, if r_busy isn't - // true, we can always set it. On the one clock where r_busy isn't - // true and i_wr is, we set it and r_busy is true thereafter. - // Then, on any zero_baud_counter (i.e. change between baud intervals) - // we simple logically shift the register right to grab the next bit. - initial lcl_data = 8'hff; - always @(posedge i_clk) - if (!r_busy) - lcl_data <= i_data; - else if (zero_baud_counter) - lcl_data <= { 1'b0, lcl_data[7:1] }; - // }}} - - // o_uart_tx - // {{{ - // This is the final result/output desired of this core. It's all - // centered about o_uart_tx. This is what finally needs to follow - // the UART protocol. - // - // Ok, that said, our rules are: - // 1'b0 on any break condition - // 1'b0 on a start bit (IDLE, write, and not busy) - // lcl_data[0] during any data transfer, but only at the baud - // change - // PARITY -- During the parity bit. This depends upon whether or - // not the parity bit is fixed, then what it's fixed to, - // or changing, and hence what it's calculated value is. - // 1'b1 at all other times (stop bits, idle, etc) - - initial o_uart_tx = 1'b1; - always @(posedge i_clk) - if (i_reset) - o_uart_tx <= 1'b1; - else if ((i_break)||((i_wr)&&(!r_busy))) - o_uart_tx <= 1'b0; - else if (zero_baud_counter) - casez(state) - 4'b0???: o_uart_tx <= lcl_data[0]; - TXU_PARITY: o_uart_tx <= calc_parity; - default: o_uart_tx <= 1'b1; - endcase - // }}} - - // calc_parity - // {{{ - // Calculate the parity to be placed into the parity bit. If the - // parity is fixed, then the parity bit is given by the fixed parity - // value (r_setup[24]). Otherwise the parity is given by the GF2 - // sum of all the data bits (plus one for even parity). - initial calc_parity = 1'b0; - always @(posedge i_clk) - if (!o_busy) - calc_parity <= i_setup[24]; - else if (fixd_parity) - calc_parity <= fixdp_value; - else if (zero_baud_counter) - begin - if (state[3] == 0) // First 8 bits of msg - calc_parity <= calc_parity ^ lcl_data[0]; - else if (state == TXU_IDLE) - calc_parity <= parity_odd; - end else if (!r_busy) - calc_parity <= parity_odd; - // }}} - - // baud_counter, zero_baud_counter - // {{{ - // All of the above logic is driven by the baud counter. Bits must last - // {{{ - // clocks_per_baud in length, and this baud counter is what we use to - // make certain of that. - // - // The basic logic is this: at the beginning of a bit interval, start - // the baud counter and set it to count clocks_per_baud. When it gets - // to zero, restart it. - // - // However, comparing a 28'bit number to zero can be rather complex-- - // especially if we wish to do anything else on that same clock. For - // that reason, we create "zero_baud_counter". zero_baud_counter is - // nothing more than a flag that is true anytime baud_counter is zero. - // It's true when the logic (above) needs to step to the next bit. - // Simple enough? - // - // I wish we could stop there, but there are some other (ugly) - // conditions to deal with that offer exceptions to this basic logic. - // - // 1. When the user has commanded a BREAK across the line, we need to - // wait several baud intervals following the break before we start - // transmitting, to give any receiver a chance to recognize that we are - // out of the break condition, and to know that the next bit will be - // a stop bit. - // - // 2. A reset is similar to a break condition--on both we wait several - // baud intervals before allowing a start bit. - // - // 3. In the idle state, we stop our counter--so that upon a request - // to transmit when idle we can start transmitting immediately, rather - // than waiting for the end of the next (fictitious and arbitrary) baud - // interval. - // - // When (i_wr)&&(!r_busy)&&(state == TXU_IDLE) then we're not only in - // the idle state, but we also just accepted a command to start writing - // the next word. At this point, the baud counter needs to be reset - // to the number of clocks per baud, and zero_baud_counter set to zero. - // - // The logic is a bit twisted here, in that it will only check for the - // above condition when zero_baud_counter is false--so as to make - // certain the STOP bit is complete. - // }}} - initial zero_baud_counter = 1'b0; - initial baud_counter = 28'h05; - always @(posedge i_clk) - begin - zero_baud_counter <= (baud_counter == 28'h01); - if ((i_reset)||(i_break)) - begin - // Give ourselves 16 bauds before being ready - baud_counter <= break_condition; - zero_baud_counter <= 1'b0; - end else if (!zero_baud_counter) - baud_counter <= baud_counter - 28'h01; - else if (state == TXU_BREAK) - begin - baud_counter <= 0; - zero_baud_counter <= 1'b1; - end else if (state == TXU_IDLE) - begin - baud_counter <= 28'h0; - zero_baud_counter <= 1'b1; - if ((i_wr)&&(!r_busy)) - begin - baud_counter <= { 4'h0, i_setup[23:0]} - 28'h01; - zero_baud_counter <= 1'b0; - end - end else if (last_state) - baud_counter <= clocks_per_baud - 28'h02; - else - baud_counter <= clocks_per_baud - 28'h01; - end - // }}} - - // last_state - // {{{ - initial last_state = 1'b0; - always @(posedge i_clk) - if (dblstop) - last_state <= (state == TXU_SECOND_STOP); - else - last_state <= (state == TXU_STOP); - // }}} - - // Make Verilator happy - // {{{ - // Verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_parity_odd, data_bits }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations - // {{{ - reg fsv_parity; - reg [30:0] fsv_setup; - reg [7:0] fsv_data; - reg f_past_valid; - // - // Our various sequence data declarations - reg [5:0] f_five_seq; - reg [6:0] f_six_seq; - reg [7:0] f_seven_seq; - reg [8:0] f_eight_seq; - reg [2:0] f_stop_seq; // parity bit, stop bit, double stop bit - // }}} - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(posedge i_clk) - if ((i_wr)&&(!o_busy)) - fsv_data <= i_data; - - initial fsv_setup = INITIAL_SETUP; - always @(posedge i_clk) - if (!o_busy) - fsv_setup <= i_setup; - - always @(*) - assert(r_setup == fsv_setup); - - - always @(posedge i_clk) - assert(zero_baud_counter == (baud_counter == 0)); - - always @(*) - if (!o_busy) - assert(zero_baud_counter); - - /* - * - * Will only pass if !i_break && !i_reset, otherwise the setup can - * change in the middle of this operation - * - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(i_reset))&&(!$past(i_break)) - &&(($past(o_busy))||($past(i_wr)))) - assert(baud_counter <= { fsv_setup[23:0], 4'h0 }); - */ - - // A single baud interval - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(zero_baud_counter)) - &&(!$past(i_reset))&&(!$past(i_break))) - begin - assert($stable(o_uart_tx)); - assert($stable(state)); - assert($stable(lcl_data)); - if ((state != TXU_IDLE)&&(state != TXU_BREAK)) - assert($stable(calc_parity)); - assert(baud_counter == $past(baud_counter)-1'b1); - end - - - // - // One byte transmitted - // - // DATA = the byte that is sent - // CKS = the number of clocks per bit - // - //////////////////////////////////////////////////////////////////////// - // - // Five bit data - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial f_five_seq = 0; - always @(posedge i_clk) - if ((i_reset)||(i_break)) - f_five_seq = 0; - else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy) - &&(i_data_bits == 2'b11)) // five data bits - f_five_seq <= 1; - else if (zero_baud_counter) - f_five_seq <= f_five_seq << 1; - - always @(*) - if (|f_five_seq) - begin - assert(fsv_setup[29:28] == data_bits); - assert(data_bits == 2'b11); - assert(baud_counter < fsv_setup[23:0]); - - assert(1'b0 == |f_six_seq); - assert(1'b0 == |f_seven_seq); - assert(1'b0 == |f_eight_seq); - assert(r_busy); - assert(state > 4'h2); - end - - always @(*) - case(f_five_seq) - 6'h00: begin assert(1); end - 6'h01: begin - assert(state == 4'h3); - assert(o_uart_tx == 1'b0); - assert(lcl_data[4:0] == fsv_data[4:0]); - if (!fixd_parity) - assert(calc_parity == parity_odd); - end - 6'h02: begin - assert(state == 4'h4); - assert(o_uart_tx == fsv_data[0]); - assert(lcl_data[3:0] == fsv_data[4:1]); - if (!fixd_parity) - assert(calc_parity == fsv_data[0] ^ parity_odd); - end - 6'h04: begin - assert(state == 4'h5); - assert(o_uart_tx == fsv_data[1]); - assert(lcl_data[2:0] == fsv_data[4:2]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd); - end - 6'h08: begin - assert(state == 4'h6); - assert(o_uart_tx == fsv_data[2]); - assert(lcl_data[1:0] == fsv_data[4:3]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd); - end - 6'h10: begin - assert(state == 4'h7); - assert(o_uart_tx == fsv_data[3]); - assert(lcl_data[0] == fsv_data[4]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd); - end - 6'h20: begin - if (use_parity) - assert(state == 4'h8); - else - assert(state == 4'h9); - assert(o_uart_tx == fsv_data[4]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[4:0]) ^ parity_odd); - end - default: begin assert(0); end - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Six bit data - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial f_six_seq = 0; - always @(posedge i_clk) - if ((i_reset)||(i_break)) - f_six_seq = 0; - else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy) - &&(i_data_bits == 2'b10)) // six data bits - f_six_seq <= 1; - else if (zero_baud_counter) - f_six_seq <= f_six_seq << 1; - - always @(*) - if (|f_six_seq) - begin - assert(fsv_setup[29:28] == 2'b10); - assert(fsv_setup[29:28] == data_bits); - assert(baud_counter < fsv_setup[23:0]); - - assert(1'b0 == |f_five_seq); - assert(1'b0 == |f_seven_seq); - assert(1'b0 == |f_eight_seq); - assert(r_busy); - assert(state > 4'h1); - end - - always @(*) - case(f_six_seq) - 7'h00: begin assert(1); end - 7'h01: begin - assert(state == 4'h2); - assert(o_uart_tx == 1'b0); - assert(lcl_data[5:0] == fsv_data[5:0]); - if (!fixd_parity) - assert(calc_parity == parity_odd); - end - 7'h02: begin - assert(state == 4'h3); - assert(o_uart_tx == fsv_data[0]); - assert(lcl_data[4:0] == fsv_data[5:1]); - if (!fixd_parity) - assert(calc_parity == fsv_data[0] ^ parity_odd); - end - 7'h04: begin - assert(state == 4'h4); - assert(o_uart_tx == fsv_data[1]); - assert(lcl_data[3:0] == fsv_data[5:2]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd); - end - 7'h08: begin - assert(state == 4'h5); - assert(o_uart_tx == fsv_data[2]); - assert(lcl_data[2:0] == fsv_data[5:3]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd); - end - 7'h10: begin - assert(state == 4'h6); - assert(o_uart_tx == fsv_data[3]); - assert(lcl_data[1:0] == fsv_data[5:4]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd); - end - 7'h20: begin - assert(state == 4'h7); - assert(lcl_data[0] == fsv_data[5]); - assert(o_uart_tx == fsv_data[4]); - if (!fixd_parity) - assert(calc_parity == ((^fsv_data[4:0]) ^ parity_odd)); - end - 7'h40: begin - if (use_parity) - assert(state == 4'h8); - else - assert(state == 4'h9); - assert(o_uart_tx == fsv_data[5]); - if (!fixd_parity) - assert(calc_parity == ((^fsv_data[5:0]) ^ parity_odd)); - end - default: begin if (f_past_valid) assert(0); end - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Seven bit data - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial f_seven_seq = 0; - always @(posedge i_clk) - if ((i_reset)||(i_break)) - f_seven_seq = 0; - else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy) - &&(i_data_bits == 2'b01)) // seven data bits - f_seven_seq <= 1; - else if (zero_baud_counter) - f_seven_seq <= f_seven_seq << 1; - - always @(*) - if (|f_seven_seq) - begin - assert(fsv_setup[29:28] == 2'b01); - assert(fsv_setup[29:28] == data_bits); - assert(baud_counter < fsv_setup[23:0]); - - assert(1'b0 == |f_five_seq); - assert(1'b0 == |f_six_seq); - assert(1'b0 == |f_eight_seq); - assert(r_busy); - assert(state != 4'h0); - end - - always @(*) - case(f_seven_seq) - 8'h00: begin assert(1); end - 8'h01: begin - assert(state == 4'h1); - assert(o_uart_tx == 1'b0); - assert(lcl_data[6:0] == fsv_data[6:0]); - if (!fixd_parity) - assert(calc_parity == parity_odd); - end - 8'h02: begin - assert(state == 4'h2); - assert(o_uart_tx == fsv_data[0]); - assert(lcl_data[5:0] == fsv_data[6:1]); - if (!fixd_parity) - assert(calc_parity == fsv_data[0] ^ parity_odd); - end - 8'h04: begin - assert(state == 4'h3); - assert(o_uart_tx == fsv_data[1]); - assert(lcl_data[4:0] == fsv_data[6:2]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd); - end - 8'h08: begin - assert(state == 4'h4); - assert(o_uart_tx == fsv_data[2]); - assert(lcl_data[3:0] == fsv_data[6:3]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd); - end - 8'h10: begin - assert(state == 4'h5); - assert(o_uart_tx == fsv_data[3]); - assert(lcl_data[2:0] == fsv_data[6:4]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd); - end - 8'h20: begin - assert(state == 4'h6); - assert(o_uart_tx == fsv_data[4]); - assert(lcl_data[1:0] == fsv_data[6:5]); - if (!fixd_parity) - assert(calc_parity == ((^fsv_data[4:0]) ^ parity_odd)); - end - 8'h40: begin - assert(state == 4'h7); - assert(lcl_data[0] == fsv_data[6]); - assert(o_uart_tx == fsv_data[5]); - if (!fixd_parity) - assert(calc_parity == ((^fsv_data[5:0]) ^ parity_odd)); - end - 8'h80: begin - if (use_parity) - assert(state == 4'h8); - else - assert(state == 4'h9); - assert(o_uart_tx == fsv_data[6]); - if (!fixd_parity) - assert(calc_parity == ((^fsv_data[6:0]) ^ parity_odd)); - end - default: begin if (f_past_valid) assert(0); end - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Eight bit data - // {{{ - //////////////////////////////////////////////////////////////////////// - initial f_eight_seq = 0; - always @(posedge i_clk) - if ((i_reset)||(i_break)) - f_eight_seq = 0; - else if ((state == TXU_IDLE)&&(i_wr)&&(!o_busy) - &&(i_data_bits == 2'b00)) // Eight data bits - f_eight_seq <= 1; - else if (zero_baud_counter) - f_eight_seq <= f_eight_seq << 1; - - always @(*) - if (|f_eight_seq) - begin - assert(fsv_setup[29:28] == 2'b00); - assert(fsv_setup[29:28] == data_bits); - assert(baud_counter < { 6'h0, fsv_setup[23:0]}); - - assert(1'b0 == |f_five_seq); - assert(1'b0 == |f_six_seq); - assert(1'b0 == |f_seven_seq); - assert(r_busy); - end - - always @(*) - case(f_eight_seq) - 9'h000: begin assert(1); end - 9'h001: begin - assert(state == 4'h0); - assert(o_uart_tx == 1'b0); - assert(lcl_data[7:0] == fsv_data[7:0]); - if (!fixd_parity) - assert(calc_parity == parity_odd); - end - 9'h002: begin - assert(state == 4'h1); - assert(o_uart_tx == fsv_data[0]); - assert(lcl_data[6:0] == fsv_data[7:1]); - if (!fixd_parity) - assert(calc_parity == fsv_data[0] ^ parity_odd); - end - 9'h004: begin - assert(state == 4'h2); - assert(o_uart_tx == fsv_data[1]); - assert(lcl_data[5:0] == fsv_data[7:2]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[1:0]) ^ parity_odd); - end - 9'h008: begin - assert(state == 4'h3); - assert(o_uart_tx == fsv_data[2]); - assert(lcl_data[4:0] == fsv_data[7:3]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[2:0]) ^ parity_odd); - end - 9'h010: begin - assert(state == 4'h4); - assert(o_uart_tx == fsv_data[3]); - assert(lcl_data[3:0] == fsv_data[7:4]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[3:0]) ^ parity_odd); - end - 9'h020: begin - assert(state == 4'h5); - assert(o_uart_tx == fsv_data[4]); - assert(lcl_data[2:0] == fsv_data[7:5]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[4:0]) ^ parity_odd); - end - 9'h040: begin - assert(state == 4'h6); - assert(o_uart_tx == fsv_data[5]); - assert(lcl_data[1:0] == fsv_data[7:6]); - if (!fixd_parity) - assert(calc_parity == (^fsv_data[5:0]) ^ parity_odd); - end - 9'h080: begin - assert(state == 4'h7); - assert(o_uart_tx == fsv_data[6]); - assert(lcl_data[0] == fsv_data[7]); - if (!fixd_parity) - assert(calc_parity == ((^fsv_data[6:0]) ^ parity_odd)); - end - 9'h100: begin - if (use_parity) - assert(state == 4'h8); - else - assert(state == 4'h9); - assert(o_uart_tx == fsv_data[7]); - if (!fixd_parity) - assert(calc_parity == ((^fsv_data[7:0]) ^ parity_odd)); - end - default: begin if (f_past_valid) assert(0); end - endcase - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Combined properties for all of the data sequences - // {{{ - //////////////////////////////////////////////////////////////////////// - // - always @(posedge i_clk) - if (((|f_five_seq[5:0]) || (|f_six_seq[6:0]) || (|f_seven_seq[7:0]) - || (|f_eight_seq[8:0])) - && ($past(zero_baud_counter))) - assert(baud_counter == { 4'h0, fsv_setup[23:0] }-1); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The stop sequence - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // This consists of any parity bit, as well as one or two stop bits - // - initial f_stop_seq = 1'b0; - always @(posedge i_clk) - if ((i_reset)||(i_break)) - f_stop_seq <= 0; - else if (zero_baud_counter) - begin - f_stop_seq <= 0; - if (f_stop_seq[0]) // Coming from a parity bit - begin - if (dblstop) - f_stop_seq[1] <= 1'b1; - else - f_stop_seq[2] <= 1'b1; - end - - if (f_stop_seq[1]) - f_stop_seq[2] <= 1'b1; - - if (f_eight_seq[8] | f_seven_seq[7] | f_six_seq[6] - | f_five_seq[5]) - begin - if (use_parity) - f_stop_seq[0] <= 1'b1; - else if (dblstop) - f_stop_seq[1] <= 1'b1; - else - f_stop_seq[2] <= 1'b1; - end - end - - always @(*) - if (|f_stop_seq) - begin - assert(1'b0 == |f_five_seq[4:0]); - assert(1'b0 == |f_six_seq[5:0]); - assert(1'b0 == |f_seven_seq[6:0]); - assert(1'b0 == |f_eight_seq[7:0]); - - assert(r_busy); - end - - always @(*) - if (f_stop_seq[0]) - begin - // 9 if dblstop and use_parity - if (dblstop) - assert(state == TXU_STOP); - else - assert(state == TXU_STOP); - assert(use_parity); - assert(o_uart_tx == fsv_parity); - end - - always @(*) - if (f_stop_seq[1]) - begin - // if (!use_parity) - assert(state == TXU_SECOND_STOP); - assert(dblstop); - assert(o_uart_tx); - end - - always @(*) - if (f_stop_seq[2]) - begin - assert(state == 4'hf); - assert(o_uart_tx); - assert(baud_counter < fsv_setup[23:0]-1'b1); - end - - - always @(*) - if (fsv_setup[25]) - fsv_parity <= fsv_setup[24]; - else - case(fsv_setup[29:28]) - 2'b00: fsv_parity = (^fsv_data[7:0]) ^ fsv_setup[24]; - 2'b01: fsv_parity = (^fsv_data[6:0]) ^ fsv_setup[24]; - 2'b10: fsv_parity = (^fsv_data[5:0]) ^ fsv_setup[24]; - 2'b11: fsv_parity = (^fsv_data[4:0]) ^ fsv_setup[24]; - endcase - // }}} - ////////////////////////////////////////////////////////////////////// - // - // The break sequence - // {{{ - ////////////////////////////////////////////////////////////////////// - reg [1:0] f_break_seq; - - initial f_break_seq = 2'b00; - always @(posedge i_clk) - if (i_reset) - f_break_seq <= 2'b00; - else if (i_break) - f_break_seq <= 2'b01; - else if (!zero_baud_counter) - f_break_seq <= { |f_break_seq, 1'b0 }; - else - f_break_seq <= 0; - - always @(posedge i_clk) - if (f_break_seq[0]) - assert(baud_counter == { $past(fsv_setup[23:0]), 4'h0 }); - always @(posedge i_clk) - if ((f_past_valid)&&($past(f_break_seq[1]))&&(state != TXU_BREAK)) - begin - assert(state == TXU_IDLE); - assert(o_uart_tx == 1'b1); - end - - always @(*) - if (|f_break_seq) - begin - assert(state == TXU_BREAK); - assert(r_busy); - assert(o_uart_tx == 1'b0); - end - // }}} - ////////////////////////////////////////////////////////////////////// - // - // Properties for use during induction if we are made a submodule of - // the rxuart - // {{{ - ////////////////////////////////////////////////////////////////////// - // - // Need enough bits for reset (24+4) plus enough bits for all of the - // various characters, 24+4, so 24+5 is a minimum of this counter - // -`ifndef TXUART - reg [28:0] f_counter; - initial f_counter = 0; - always @(posedge i_clk) - if (!o_busy) - f_counter <= 1'b0; - else - f_counter <= f_counter + 1'b1; - - always @(*) - if (f_five_seq[0]|f_six_seq[0]|f_seven_seq[0]|f_eight_seq[0]) - // {{{ - assert(f_counter == (fsv_setup[23:0] - baud_counter - 1)); - // }}} - else if (f_five_seq[1]|f_six_seq[1]|f_seven_seq[1]|f_eight_seq[1]) - // {{{ - assert(f_counter == ({4'h0, fsv_setup[23:0], 1'b0} - baud_counter - 1)); - // }}} - else if (f_five_seq[2]|f_six_seq[2]|f_seven_seq[2]|f_eight_seq[2]) - // {{{ - assert(f_counter == ({4'h0, fsv_setup[23:0], 1'b0} - +{5'h0, fsv_setup[23:0]} - - baud_counter - 1)); - // }}} - else if (f_five_seq[3]|f_six_seq[3]|f_seven_seq[3]|f_eight_seq[3]) - // {{{ - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} - - baud_counter - 1)); - // }}} - else if (f_five_seq[4]|f_six_seq[4]|f_seven_seq[4]|f_eight_seq[4]) - // {{{ - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} - +{5'h0, fsv_setup[23:0]} - - baud_counter - 1)); - // }}} - else if (f_five_seq[5]|f_six_seq[5]|f_seven_seq[5]|f_eight_seq[5]) - // {{{ - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} - +{4'h0, fsv_setup[23:0], 1'b0} - - baud_counter - 1)); - // }}} - else if (f_six_seq[6]|f_seven_seq[6]|f_eight_seq[6]) - // {{{ - assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} - +{5'h0, fsv_setup[23:0]} - +{4'h0, fsv_setup[23:0], 1'b0} - - baud_counter - 1)); - // }}} - else if (f_seven_seq[7]|f_eight_seq[7]) - // {{{ - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} // 8 - - baud_counter - 1)); - // }}} - else if (f_eight_seq[8]) - // {{{ - assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} // 9 - +{5'h0, fsv_setup[23:0]} - - baud_counter - 1)); - // }}} - else if (f_stop_seq[0] || (!use_parity && f_stop_seq[1])) - begin - // {{{ - // Parity bit, or first of two stop bits - case(data_bits) - 2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{4'h0, fsv_setup[23:0], 1'b0} // 10 - - baud_counter - 1)); - 2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{5'h0, fsv_setup[23:0]} // 9 - - baud_counter - 1)); - 2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - - baud_counter - 1)); // 8 - 2'b11: assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} - +{5'h0, fsv_setup[23:0]} // 7 - +{4'h0, fsv_setup[23:0], 1'b0} - - baud_counter - 1)); - endcase - // }}} - end else if (!use_parity && !dblstop && f_stop_seq[2]) - begin - // {{{ - // No parity, single stop bit - // Different from the one above, since the last counter is has - // one fewer items within it - case(data_bits) - 2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{4'h0, fsv_setup[23:0], 1'b0} // 10 - - baud_counter - 2)); - 2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{5'h0, fsv_setup[23:0]} // 9 - - baud_counter - 2)); - 2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - - baud_counter - 2)); // 8 - 2'b11: assert(f_counter == ({3'h0, fsv_setup[23:0], 2'b0} - +{5'h0, fsv_setup[23:0]} // 7 - +{4'h0, fsv_setup[23:0], 1'b0} - - baud_counter - 2)); - endcase - // }}} - end else if (f_stop_seq[1]) - begin - // {{{ - // Parity and the first of two stop bits - assert(dblstop && use_parity); - case(data_bits) - 2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{5'h0, fsv_setup[23:0]} // 11 - +{4'h0, fsv_setup[23:0], 1'b0} - - baud_counter - 1)); - 2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{4'h0, fsv_setup[23:0], 1'b0} // 10 - - baud_counter - 1)); - 2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{5'h0, fsv_setup[23:0]} // 9 - - baud_counter - 1)); - 2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - - baud_counter - 1)); // 8 - endcase - // }}} - end else if ((dblstop ^ use_parity) && f_stop_seq[2]) - begin - // {{{ - // Parity and one stop bit - // assert(!dblstop && use_parity); - case(data_bits) - 2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{5'h0, fsv_setup[23:0]} // 11 - +{4'h0, fsv_setup[23:0], 1'b0} - - baud_counter - 2)); - 2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{4'h0, fsv_setup[23:0], 1'b0} // 10 - - baud_counter - 2)); - 2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{5'h0, fsv_setup[23:0]} // 9 - - baud_counter - 2)); - 2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - - baud_counter - 2)); // 8 - endcase - // }}} - end else if (f_stop_seq[2]) - begin - // {{{ - assert(dblstop); - assert(use_parity); - // Parity and two stop bits - case(data_bits) - 2'b00: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{3'h0, fsv_setup[23:0], 2'b00} // 12 - - baud_counter - 2)); - 2'b01: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{5'h0, fsv_setup[23:0]} // 11 - +{4'h0, fsv_setup[23:0], 1'b0} - - baud_counter - 2)); - 2'b10: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{4'h0, fsv_setup[23:0], 1'b0} // 10 - - baud_counter - 2)); - 2'b11: assert(f_counter == ({2'h0, fsv_setup[23:0], 3'b0} - +{5'h0, fsv_setup[23:0]} // 9 - - baud_counter - 2)); - endcase - // }}} - end -`endif - // }}} - ////////////////////////////////////////////////////////////////////// - // - // Other properties, not necessarily associated with any sequences - // - ////////////////////////////////////////////////////////////////////// - always @(*) - assert((state < 4'hb)||(state >= 4'he)); - ////////////////////////////////////////////////////////////////////// - // - // Careless/limiting assumption section - // - ////////////////////////////////////////////////////////////////////// - always @(*) - assume(i_setup[23:0] > 2); - always @(*) - assert(fsv_setup[23:0] > 2); - -`endif // FORMAL -// }}} -endmodule - diff --git a/delete_later/rtl/wbuart/txuartlite.v b/delete_later/rtl/wbuart/txuartlite.v deleted file mode 100644 index 3817d65..0000000 --- a/delete_later/rtl/wbuart/txuartlite.v +++ /dev/null @@ -1,455 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: txuartlite.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Transmit outputs over a single UART line. This particular UART -// implementation has been extremely simplified: it does not handle -// generating break conditions, nor does it handle anything other than the -// 8N1 (8 data bits, no parity, 1 stop bit) UART sub-protocol. -// -// To interface with this module, connect it to your system clock, and -// pass it the byte of data you wish to transmit. Strobe the i_wr line -// high for one cycle, and your data will be off. Wait until the 'o_busy' -// line is low before strobing the i_wr line again--this implementation -// has NO BUFFER, so strobing i_wr while the core is busy will just -// get ignored. The output will be placed on the o_txuart output line. -// -// (I often set both data and strobe on the same clock, and then just leave -// them set until the busy line is low. Then I move on to the next piece -// of data.) -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module txuartlite #( - // {{{ - // TIMING_BITS -- the number of bits required to represent - // the number of clocks per baud. 24 should be sufficient for - // most baud rates, but you can trim it down to save logic if - // you would like. TB is just an abbreviation for TIMING_BITS. - parameter [4:0] TIMING_BITS = 5'd24, - localparam TB = TIMING_BITS, - // CLOCKS_PER_BAUD -- the number of system clocks per baud - // interval. - parameter [(TB-1):0] CLOCKS_PER_BAUD = 8 // 24'd868 - // }}} - ) ( - // {{{ - input wire i_clk, - input wire i_wr, - input wire [7:0] i_data, - // And the UART input line itself - output reg o_uart_tx, - // A line to tell others when we are ready to accept data. If - // (i_wr)&&(!o_busy) is ever true, then the core has accepted - // a byte for transmission. - output wire o_busy - // }}} - ); - - // Register/net declarations - // {{{ - localparam [3:0] TXUL_BIT_ZERO = 4'h0, - // TXUL_BIT_ONE = 4'h1, - // TXUL_BIT_TWO = 4'h2, - // TXUL_BIT_THREE = 4'h3, - // TXUL_BIT_FOUR = 4'h4, - // TXUL_BIT_FIVE = 4'h5, - // TXUL_BIT_SIX = 4'h6, - // TXUL_BIT_SEVEN = 4'h7, - TXUL_STOP = 4'h8, - TXUL_IDLE = 4'hf; - - reg [(TB-1):0] baud_counter; - reg [3:0] state; - reg [7:0] lcl_data; - reg r_busy, zero_baud_counter; - // }}} - - // Big state machine controlling: r_busy, state - // {{{ - // - initial r_busy = 1'b1; - initial state = TXUL_IDLE; - always @(posedge i_clk) - begin - if (!zero_baud_counter) - // r_busy needs to be set coming into here - r_busy <= 1'b1; - else if (state > TXUL_STOP) // STATE_IDLE - begin - state <= TXUL_IDLE; - r_busy <= 1'b0; - if ((i_wr)&&(!r_busy)) - begin // Immediately start us off with a start bit - r_busy <= 1'b1; - state <= TXUL_BIT_ZERO; - end - end else begin - // One clock tick in each of these states ... - r_busy <= 1'b1; - if (state <=TXUL_STOP) // start bit, 8-d bits, stop-b - state <= state + 1'b1; - else - state <= TXUL_IDLE; - end - end - // }}} - - // o_busy - // {{{ - // - // This is a wire, designed to be true is we are ever busy above. - // originally, this was going to be true if we were ever not in the - // idle state. The logic has since become more complex, hence we have - // a register dedicated to this and just copy out that registers value. - assign o_busy = (r_busy); - // }}} - - // lcl_data - // {{{ - // - // This is our working copy of the i_data register which we use - // when transmitting. It is only of interest during transmit, and is - // allowed to be whatever at any other time. Hence, if r_busy isn't - // true, we can always set it. On the one clock where r_busy isn't - // true and i_wr is, we set it and r_busy is true thereafter. - // Then, on any zero_baud_counter (i.e. change between baud intervals) - // we simple logically shift the register right to grab the next bit. - initial lcl_data = 8'hff; - always @(posedge i_clk) - if ((i_wr)&&(!r_busy)) - lcl_data <= i_data; - else if (zero_baud_counter) - lcl_data <= { 1'b1, lcl_data[7:1] }; - // }}} - - // o_uart_tx - // {{{ - // - // This is the final result/output desired of this core. It's all - // centered about o_uart_tx. This is what finally needs to follow - // the UART protocol. - // - initial o_uart_tx = 1'b1; - always @(posedge i_clk) - if ((i_wr)&&(!r_busy)) - o_uart_tx <= 1'b0; // Set the start bit on writes - else if (zero_baud_counter) // Set the data bit. - o_uart_tx <= lcl_data[0]; - // }}} - - // Baud counter - // {{{ - // All of the above logic is driven by the baud counter. Bits must last - // CLOCKS_PER_BAUD in length, and this baud counter is what we use to - // make certain of that. - // - // The basic logic is this: at the beginning of a bit interval, start - // the baud counter and set it to count CLOCKS_PER_BAUD. When it gets - // to zero, restart it. - // - // However, comparing a 28'bit number to zero can be rather complex-- - // especially if we wish to do anything else on that same clock. For - // that reason, we create "zero_baud_counter". zero_baud_counter is - // nothing more than a flag that is true anytime baud_counter is zero. - // It's true when the logic (above) needs to step to the next bit. - // Simple enough? - // - // I wish we could stop there, but there are some other (ugly) - // conditions to deal with that offer exceptions to this basic logic. - // - // 1. When the user has commanded a BREAK across the line, we need to - // wait several baud intervals following the break before we start - // transmitting, to give any receiver a chance to recognize that we are - // out of the break condition, and to know that the next bit will be - // a stop bit. - // - // 2. A reset is similar to a break condition--on both we wait several - // baud intervals before allowing a start bit. - // - // 3. In the idle state, we stop our counter--so that upon a request - // to transmit when idle we can start transmitting immediately, rather - // than waiting for the end of the next (fictitious and arbitrary) baud - // interval. - // - // When (i_wr)&&(!r_busy)&&(state == TXUL_IDLE) then we're not only in - // the idle state, but we also just accepted a command to start writing - // the next word. At this point, the baud counter needs to be reset - // to the number of CLOCKS_PER_BAUD, and zero_baud_counter set to zero. - // - // The logic is a bit twisted here, in that it will only check for the - // above condition when zero_baud_counter is false--so as to make - // certain the STOP bit is complete. - initial zero_baud_counter = 1'b1; - initial baud_counter = 0; - always @(posedge i_clk) - begin - zero_baud_counter <= (baud_counter == 1); - if (state == TXUL_IDLE) - begin - baud_counter <= 0; - zero_baud_counter <= 1'b1; - if ((i_wr)&&(!r_busy)) - begin - baud_counter <= CLOCKS_PER_BAUD - 1'b1; - zero_baud_counter <= 1'b0; - end - end else if (!zero_baud_counter) - baud_counter <= baud_counter - 1'b1; - else if (state > TXUL_STOP) - begin - baud_counter <= 0; - zero_baud_counter <= 1'b1; - end else if (state == TXUL_STOP) - // Need to complete this state one clock early, so - // we can release busy one clock before the stop bit - // is complete, so we can start on the next byte - // exactly 10*CLOCKS_PER_BAUD clocks after we started - // the last one - baud_counter <= CLOCKS_PER_BAUD - 2; - else // All other states - baud_counter <= CLOCKS_PER_BAUD - 1'b1; - end - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// FORMAL METHODS -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - // Declarations -`ifdef TXUARTLITE -`define ASSUME assume -`else -`define ASSUME assert -`endif - reg f_past_valid, f_last_clk; - reg [(TB-1):0] f_baud_count; - reg [9:0] f_txbits; - reg [3:0] f_bitcount; - reg [7:0] f_request_tx_data; - wire [3:0] subcount; - - // Setup - // {{{ - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - initial `ASSUME(!i_wr); - always @(posedge i_clk) - if ((f_past_valid)&&($past(i_wr))&&($past(o_busy))) - begin - `ASSUME(i_wr == $past(i_wr)); - `ASSUME(i_data == $past(i_data)); - end - // }}} - - // Check the baud counter - // {{{ - always @(posedge i_clk) - assert(zero_baud_counter == (baud_counter == 0)); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(baud_counter != 0))&&($past(state != TXUL_IDLE))) - assert(baud_counter == $past(baud_counter - 1'b1)); - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(zero_baud_counter))&&($past(state != TXUL_IDLE))) - assert($stable(o_uart_tx)); - - initial f_baud_count = 1'b0; - always @(posedge i_clk) - if (zero_baud_counter) - f_baud_count <= 0; - else - f_baud_count <= f_baud_count + 1'b1; - - always @(posedge i_clk) - assert(f_baud_count < CLOCKS_PER_BAUD); - - always @(posedge i_clk) - if (baud_counter != 0) - assert(o_busy); - // }}} - - // {{{ - initial f_txbits = 0; - always @(posedge i_clk) - if (zero_baud_counter) - f_txbits <= { o_uart_tx, f_txbits[9:1] }; - - always @(posedge i_clk) - if ((f_past_valid)&&(!$past(zero_baud_counter)) - &&(!$past(state==TXUL_IDLE))) - assert(state == $past(state)); - - initial f_bitcount = 0; - always @(posedge i_clk) - if ((!f_past_valid)||(!$past(f_past_valid))) - f_bitcount <= 0; - else if ((state == TXUL_IDLE)&&(zero_baud_counter)) - f_bitcount <= 0; - else if (zero_baud_counter) - f_bitcount <= f_bitcount + 1'b1; - - always @(posedge i_clk) - assert(f_bitcount <= 4'ha); - - always @(*) - if (!o_busy) - assert(zero_baud_counter); - - always @(posedge i_clk) - if ((i_wr)&&(!o_busy)) - f_request_tx_data <= i_data; - - assign subcount = 10-f_bitcount; - always @(posedge i_clk) - if (f_bitcount > 0) - assert(!f_txbits[subcount]); - - always @(posedge i_clk) - if (f_bitcount == 4'ha) - begin - assert(f_txbits[8:1] == f_request_tx_data); - assert( f_txbits[9]); - end - - always @(posedge i_clk) - assert((state <= TXUL_STOP + 1'b1)||(state == TXUL_IDLE)); - - always @(posedge i_clk) - if ((f_past_valid)&&($past(f_past_valid))&&($past(o_busy))) - cover(!o_busy); - // }}} - -`endif // FORMAL -`ifdef VERIFIC_SVA - reg [7:0] fsv_data; - - // - // Grab a copy of the data any time we are sent a new byte to transmit - // We'll use this in a moment to compare the item transmitted against - // what is supposed to be transmitted - // - always @(posedge i_clk) - if ((i_wr)&&(!o_busy)) - fsv_data <= i_data; - - // - // One baud interval - // {{{ - // - // 1. The UART output is constant at DAT - // 2. The internal state remains constant at ST - // 3. CKS = the number of clocks per bit. - // - // Everything stays constant during the CKS clocks with the exception - // of (zero_baud_counter), which is *only* raised on the last clock - // interval - sequence BAUD_INTERVAL(CKS, DAT, SR, ST); - ((o_uart_tx == DAT)&&(state == ST) - &&(lcl_data == SR) - &&(!zero_baud_counter))[*(CKS-1)] - ##1 (o_uart_tx == DAT)&&(state == ST) - &&(lcl_data == SR) - &&(zero_baud_counter); - endsequence - // }}} - - // - // One byte transmitted - // {{{ - // - // DATA = the byte that is sent - // CKS = the number of clocks per bit - // - sequence SEND(CKS, DATA); - BAUD_INTERVAL(CKS, 1'b0, DATA, 4'h0) - ##1 BAUD_INTERVAL(CKS, DATA[0], {{(1){1'b1}},DATA[7:1]}, 4'h1) - ##1 BAUD_INTERVAL(CKS, DATA[1], {{(2){1'b1}},DATA[7:2]}, 4'h2) - ##1 BAUD_INTERVAL(CKS, DATA[2], {{(3){1'b1}},DATA[7:3]}, 4'h3) - ##1 BAUD_INTERVAL(CKS, DATA[3], {{(4){1'b1}},DATA[7:4]}, 4'h4) - ##1 BAUD_INTERVAL(CKS, DATA[4], {{(5){1'b1}},DATA[7:5]}, 4'h5) - ##1 BAUD_INTERVAL(CKS, DATA[5], {{(6){1'b1}},DATA[7:6]}, 4'h6) - ##1 BAUD_INTERVAL(CKS, DATA[6], {{(7){1'b1}},DATA[7:7]}, 4'h7) - ##1 BAUD_INTERVAL(CKS, DATA[7], 8'hff, 4'h8) - ##1 BAUD_INTERVAL(CKS-1, 1'b1, 8'hff, 4'h9); - endsequence - // }}} - - // - // Transmit one byte - // {{{ - // Once the byte is transmitted, make certain we return to - // idle - // - assert property ( - @(posedge i_clk) - (i_wr)&&(!o_busy) - |=> ((o_busy) throughout SEND(CLOCKS_PER_BAUD,fsv_data)) - ##1 (!o_busy)&&(o_uart_tx)&&(zero_baud_counter)); - // }}} - - // {{{ - assume property ( - @(posedge i_clk) - (i_wr)&&(o_busy) |=> - (i_wr)&&($stable(i_data))); - - // - // Make certain that o_busy is true any time zero_baud_counter is - // non-zero - // - always @(*) - assert((o_busy)||(zero_baud_counter) ); - - // If and only if zero_baud_counter is true, baud_counter must be zero - // Insist on that relationship here. - always @(*) - assert(zero_baud_counter == (baud_counter == 0)); - - // To make certain baud_counter stays below CLOCKS_PER_BAUD - always @(*) - assert(baud_counter < CLOCKS_PER_BAUD); - - // - // Insist that we are only ever in a valid state - always @(*) - assert((state <= TXUL_STOP+1'b1)||(state == TXUL_IDLE)); - // }}} - -`endif // Verific SVA -// }}} -endmodule diff --git a/delete_later/rtl/wbuart/ufifo.v b/delete_later/rtl/wbuart/ufifo.v deleted file mode 100644 index 35fb19e..0000000 --- a/delete_later/rtl/wbuart/ufifo.v +++ /dev/null @@ -1,472 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: ufifo.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: A synchronous data FIFO, designed for supporting the Wishbone -// UART. Particular features include the ability to read and -// write on the same clock, while maintaining the correct output FIFO -// parameters. Two versions of the FIFO exist within this file, separated -// by the RXFIFO parameter's value. One, where RXFIFO = 1, produces status -// values appropriate for reading and checking a read FIFO from logic, -// whereas the RXFIFO = 0 applies to writing to the FIFO from bus logic -// and reading it automatically any time the transmit UART is idle. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module ufifo #( - // {{{ - parameter BW=8, // Byte/data width - parameter [3:0] LGFLEN=4, - parameter [0:0] RXFIFO=1'b1, - localparam FLEN=(1< 4'ha)? 4'ha - : ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN) - // }}} - ) ( - // {{{ - input wire i_clk, i_reset, - // Wishbone inputs - input wire i_wb_cyc, - input wire i_wb_stb, i_wb_we, - input wire [1:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // - input wire i_uart_rx, - output wire o_uart_tx, - input wire i_cts_n, - output reg o_rts_n, - output wire o_uart_rx_int, o_uart_tx_int, - o_uart_rxfifo_int, o_uart_txfifo_int - // }}} - ); - - localparam [1:0] UART_SETUP = 2'b00, - UART_FIFO = 2'b01, - UART_RXREG = 2'b10, - UART_TXREG = 2'b11; - - // Register and signal declarations - // {{{ - wire tx_busy; - reg [30:0] uart_setup; - // Receiver - wire rx_stb, rx_break, rx_perr, rx_ferr, ck_uart; - wire [7:0] rx_uart_data; - reg rx_uart_reset; - // Receive FIFO - wire rx_empty_n, rx_fifo_err; - wire [7:0] rxf_wb_data; - wire [15:0] rxf_status; - reg rxf_wb_read; - // - wire [(LCLLGFLEN-1):0] check_cutoff; - reg r_rx_perr, r_rx_ferr; - wire [31:0] wb_rx_data; - // The transmitter - wire tx_empty_n, txf_err, tx_break; - wire [7:0] tx_data; - wire [15:0] txf_status; - reg txf_wb_write, tx_uart_reset; - reg [7:0] txf_wb_data; - // - wire [31:0] wb_tx_data; - wire [31:0] wb_fifo_data; - reg [1:0] r_wb_addr; - reg r_wb_ack; - // }}} - - // uart_setup - // {{{ - // The UART setup parameters: bits per byte, stop bits, parity, and - // baud rate are all captured within this uart_setup register. - // - initial uart_setup = INITIAL_SETUP - | ((HARDWARE_FLOW_CONTROL_PRESENT==1'b0)? 31'h40000000 : 0); - always @(posedge i_clk) - // Under wishbone rules, a write takes place any time i_wb_stb - // is high. If that's the case, and if the write was to the - // setup address, then set us up for the new parameters. - if ((i_wb_stb)&&(i_wb_addr == UART_SETUP)&&(i_wb_we)) - begin - if (i_wb_sel[0]) - uart_setup[7:0] <= i_wb_data[7:0]; - if (i_wb_sel[1]) - uart_setup[15:8] <= i_wb_data[15:8]; - if (i_wb_sel[2]) - uart_setup[23:16] <= i_wb_data[23:16]; - if (i_wb_sel[3]) - uart_setup[30:24] <= { (i_wb_data[30]) - ||(!HARDWARE_FLOW_CONTROL_PRESENT), - i_wb_data[29:24] }; - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The UART receiver - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // The receiver itself - // {{{ - // Here's our UART receiver. Basically, it accepts our setup wires, - // the UART input, a clock, and a reset line, and produces outputs: - // a stb (true when new data is ready), and an 8-bit data out value - // valid when stb is high. -`ifdef USE_LITE_UART - // {{{ - rxuartlite #(.CLOCKS_PER_BAUD(INITIAL_SETUP[23:0])) - rx(i_clk, i_uart_rx, rx_stb, rx_uart_data); - assign rx_break = 1'b0; - assign rx_perr = 1'b0; - assign rx_ferr = 1'b0; - assign ck_uart = 1'b0; - // }}} -`else - // {{{ - // The full receiver also produces a break value (true during a break - // cond.), and parity/framing error flags--also valid when stb is true. - rxuart #(.INITIAL_SETUP(INITIAL_SETUP)) rx(i_clk, (i_reset)||(rx_uart_reset), - uart_setup, i_uart_rx, - rx_stb, rx_uart_data, rx_break, - rx_perr, rx_ferr, ck_uart); - // The real trick is ... now that we have this extra data, what do we do - // with it? - // }}} -`endif - // }}} - - // The receive FIFO - // {{{ - // We place new arriving data into a receiver FIFO. - // - // And here's the FIFO proper. - // - // Note that the FIFO will be cleared upon any reset: either if there's - // a UART break condition on the line, the receiver is in reset, or an - // external reset is issued. - // - // The FIFO accepts strobe and data from the receiver. - // We issue another wire to it (rxf_wb_read), true when we wish to read - // from the FIFO, and we get our data in rxf_wb_data. The FIFO outputs - // four status-type values: 1) is it non-empty, 2) is the FIFO over half - // full, 3) a 16-bit status register, containing info regarding how full - // the FIFO truly is, and 4) an error indicator. - ufifo #( - // {{{ - .LGFLEN(LCLLGFLEN), .RXFIFO(1) - // }}} - ) rxfifo( - // {{{ - .i_clk(i_clk), .i_reset((i_reset)||(rx_break)||(rx_uart_reset)), - .i_wr(rx_stb), .i_data(rx_uart_data), - .o_empty_n(rx_empty_n), - .i_rd(rxf_wb_read), .o_data(rxf_wb_data), - .o_status(rxf_status), .o_err(rx_fifo_err) - // }}} - ); - // }}} - - assign o_uart_rxfifo_int = rxf_status[1]; - - // We produce four interrupts. One of the receive interrupts indicates - // whether or not the receive FIFO is non-empty. This should wake up - // the CPU. - assign o_uart_rx_int = rxf_status[0]; - - // o_rts_n - // {{{ - // The clear to send line, which may be ignored, but which we set here - // to be true any time the FIFO has fewer than N-2 items in it. - // Why not N-1? Because at N-1 we are totally full, but already so full - // that if the transmit end starts sending we won't have a location to - // receive it. (Transmit might've started on the next character by the - // time we set this--thus we need to set it to one, one character before - // necessary). - assign check_cutoff = -3; - always @(posedge i_clk) - o_rts_n <= ((HARDWARE_FLOW_CONTROL_PRESENT) - &&(!uart_setup[30]) - &&(rxf_status[(LCLLGFLEN+1):2] > check_cutoff)); - // }}} - - // rxf_wb_read - // {{{ - // If the bus requests that we read from the receive FIFO, we need to - // tell this to the receive FIFO. Note that because we are using a - // clock here, the output from the receive FIFO will necessarily be - // delayed by an extra clock. - initial rxf_wb_read = 1'b0; - always @(posedge i_clk) - rxf_wb_read <= (i_wb_stb)&&(i_wb_addr[1:0]== UART_RXREG) - &&(!i_wb_we); - // }}} - - // r_rx_perr, r_rx_ferr -- parity and framing errors - // {{{ - // Now, let's deal with those RX UART errors: both the parity and frame - // errors. As you may recall, these are valid only when rx_stb is - // valid, so we need to hold on to them until the user reads them via - // a UART read request.. - initial r_rx_perr = 1'b0; - initial r_rx_ferr = 1'b0; - always @(posedge i_clk) - if ((rx_uart_reset)||(rx_break)) - begin - // Clear the error - r_rx_perr <= 1'b0; - r_rx_ferr <= 1'b0; - end else if ((i_wb_stb) - &&(i_wb_addr[1:0]== UART_RXREG)&&(i_wb_we)) - begin - // Reset the error lines if a '1' is ever written to - // them, otherwise leave them alone. - // - if (i_wb_sel[1]) - begin - r_rx_perr <= (r_rx_perr)&&(~i_wb_data[9]); - r_rx_ferr <= (r_rx_ferr)&&(~i_wb_data[10]); - end - end else if (rx_stb) - begin - // On an rx_stb, capture any parity or framing error - // indications. These aren't kept with the data rcvd, - // but rather kept external to the FIFO. As a result, - // if you get a parity or framing error, you will never - // know which data byte it was associated with. - // For now ... that'll work. - r_rx_perr <= (r_rx_perr)||(rx_perr); - r_rx_ferr <= (r_rx_ferr)||(rx_ferr); - end - // }}} - - // rx_uart_reset - // {{{ - initial rx_uart_reset = 1'b1; - always @(posedge i_clk) - if ((i_reset)||((i_wb_stb)&&(i_wb_addr[1:0]== UART_SETUP)&&(i_wb_we))) - // The receiver reset, always set on a master reset - // request. - rx_uart_reset <= 1'b1; - else if ((i_wb_stb)&&(i_wb_addr[1:0]== UART_RXREG)&&(i_wb_we)&&i_wb_sel[1]) - // Writes to the receive register will command a receive - // reset anytime bit[12] is set. - rx_uart_reset <= i_wb_data[12]; - else - rx_uart_reset <= 1'b0; - // }}} - - // wb_rx_data - // {{{ - // Finally, we'll construct a 32-bit value from these various wires, - // to be returned over the bus on any read. These include the data - // that would be read from the FIFO, an error indicator set upon - // reading from an empty FIFO, a break indicator, and the frame and - // parity error signals. - assign wb_rx_data = { 16'h00, - 3'h0, rx_fifo_err, - rx_break, rx_ferr, r_rx_perr, !rx_empty_n, - rxf_wb_data}; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The UART transmitter - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // txf_wb_write, txf_wb_data - // {{{ - // Unlike the receiver which goes from RXUART -> UFIFO -> WB, the - // transmitter basically goes WB -> UFIFO -> TXUART. Hence, to build - // support for the transmitter, we start with the command to write data - // into the FIFO. In this case, we use the act of writing to the - // UART_TXREG address as our indication that we wish to write to the - // FIFO. Here, we create a write command line, and latch the data for - // the extra clock that it'll take so that the command and data can be - // both true on the same clock. - initial txf_wb_write = 1'b0; - always @(posedge i_clk) - begin - txf_wb_write <= (i_wb_stb)&&(i_wb_addr == UART_TXREG) - &&(i_wb_we)&&(i_wb_sel[0]); - txf_wb_data <= i_wb_data[7:0]; - end - // }}} - - // Transmit FIFO - // {{{ - // Most of this is just wire management. The TX FIFO is identical in - // implementation to the RX FIFO (theyre both UFIFOs), but the TX - // FIFO is fed from the WB and read by the transmitter. Some key - // differences to note: we reset the transmitter on any request for a - // break. We read from the FIFO any time the UART transmitter is idle. - // and ... we just set the values (above) for controlling writing into - // this. - ufifo #( - // {{{ - .LGFLEN(LGFLEN), .RXFIFO(0) - // }}} - ) txfifo( - // {{{ - .i_clk(i_clk), .i_reset((tx_break)||(tx_uart_reset)), - .i_wr(txf_wb_write), .i_data(txf_wb_data), - .o_empty_n(tx_empty_n), - .i_rd((!tx_busy)&&(tx_empty_n)), .o_data(tx_data), - .o_status(txf_status), .o_err(txf_err) - // }}} - ); - // }}} - - // Transmit interrupts - // {{{ - // Let's create two transmit based interrupts from the FIFO for the CPU. - // The first will be true any time the FIFO has at least one open - // position within it. - assign o_uart_tx_int = txf_status[0]; - // The second will be true any time the FIFO is less than half - // full, allowing us a change to always keep it (near) fully - // charged. - assign o_uart_txfifo_int = txf_status[1]; - // }}} - - // Break logic -`ifndef USE_LITE_UART - // {{{ - // A break in a UART controller is any time the UART holds the line - // low for an extended period of time. Here, we capture the wb_data[9] - // wire, on writes, as an indication we wish to break. As long as you - // write unsigned characters to the interface, this will never be true - // unless you wish it to be true. Be aware, though, writing a valid - // value to the interface will bring it out of the break condition. - reg r_tx_break; - initial r_tx_break = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_tx_break <= 1'b0; - else if ((i_wb_stb)&&(i_wb_addr[1:0]== UART_TXREG)&&(i_wb_we) - &&(i_wb_sel[1])) - r_tx_break <= i_wb_data[9]; - - assign tx_break = r_tx_break; - // }}} -`else - // {{{ - assign tx_break = 1'b0; - // }}} -`endif - - // TX-Reset logic - // {{{ - // This is nearly identical to the RX reset logic above. Basically, - // any time someone writes to bit [12] the transmitter will go through - // a reset cycle. Keep bit [12] low, and everything will proceed as - // normal. - initial tx_uart_reset = 1'b1; - always @(posedge i_clk) - if((i_reset)||((i_wb_stb)&&(i_wb_addr == UART_SETUP)&&(i_wb_we))) - tx_uart_reset <= 1'b1; - else if ((i_wb_stb)&&(i_wb_addr[1:0]== UART_TXREG)&&(i_wb_we) && i_wb_sel[1]) - tx_uart_reset <= i_wb_data[12]; - else - tx_uart_reset <= 1'b0; - // }}} - - // The actuall transmitter itself -`ifdef USE_LITE_UART - // {{{ - txuartlite #(.CLOCKS_PER_BAUD(INITIAL_SETUP[23:0])) tx(i_clk, (tx_empty_n), tx_data, - o_uart_tx, tx_busy); - // }}} -`else - // cts_n - // {{{ - wire cts_n; - assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT)&&(i_cts_n); - // }}} - - // The *full* transmitter impleemntation - // {{{ - // Finally, the UART transmitter module itself. Note that we haven't - // connected the reset wire. Transmitting is as simple as setting - // the stb value (here set to tx_empty_n) and the data. When these - // are both set on the same clock that tx_busy is low, the transmitter - // will move on to the next data byte. Really, the only thing magical - // here is that tx_empty_n wire--thus, if there's anything in the FIFO, - // we read it here. (You might notice above, we register a read any - // time (tx_empty_n) and (!tx_busy) are both true---the condition for - // starting to transmit a new byte.) - txuart #(.INITIAL_SETUP(INITIAL_SETUP)) tx(i_clk, 1'b0, uart_setup, - r_tx_break, (tx_empty_n), tx_data, - cts_n, o_uart_tx, tx_busy); - // }}} -`endif - - // wb_tx_data - // {{{ - // Now that we are done with the chain, pick some wires for the user - // to read on any read of the transmit port. - // - // This port is different from reading from the receive port, since - // there are no side effects. (Reading from the receive port advances - // the receive FIFO, here only writing to the transmit port advances the - // transmit FIFO--hence the read values are free for ... whatever.) - // We choose here to provide information about the transmit FIFO - // (txf_err, txf_half_full, txf_full_n), information about the current - // voltage on the line (o_uart_tx)--and even the voltage on the receive - // line (ck_uart), as well as our current setting of the break and - // whether or not we are actively transmitting. - assign wb_tx_data = { 16'h00, - i_cts_n, txf_status[1:0], txf_err, - ck_uart, o_uart_tx, tx_break, (tx_busy|txf_status[0]), - (tx_busy|txf_status[0])?txf_wb_data:8'b00}; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus / register handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - - // wb_fifo_data - // {{{ - // Each of the FIFO's returns a 16 bit status value. This value tells - // us both how big the FIFO is, as well as how much of the FIFO is in - // use. Let's merge those two status words together into a word we - // can use when reading about the FIFO. - assign wb_fifo_data = { txf_status, rxf_status }; - // }}} - - // r_wb_addr - // {{{ - // You may recall from above that reads take two clocks. Hence, we - // need to delay the address decoding for a clock until the data is - // ready. We do that here. - always @(posedge i_clk) - r_wb_addr <= i_wb_addr; - // }}} - - // r_wb_ack - // {{{ - initial r_wb_ack = 1'b0; - always @(posedge i_clk) // We'll ACK in two clocks - r_wb_ack <= (!i_reset)&&(i_wb_stb); - // }}} - - // o_wb_ack - // {{{ - initial o_wb_ack = 1'b0; - always @(posedge i_clk) // Okay, time to set the ACK - o_wb_ack <= (!i_reset)&&(r_wb_ack)&&(i_wb_cyc); - // }}} - - // o_wb_data - // {{{ - // Finally, set the return data. This data must be valid on the same - // clock o_wb_ack is high. On all other clocks, it is irrelelant--since - // no one cares, no one is reading it, it gets lost in the mux in the - // interconnect, etc. For this reason, we can just simplify our logic. - always @(posedge i_clk) - casez(r_wb_addr) - UART_SETUP: o_wb_data <= { 1'b0, uart_setup }; - UART_FIFO: o_wb_data <= wb_fifo_data; - UART_RXREG: o_wb_data <= wb_rx_data; - UART_TXREG: o_wb_data <= wb_tx_data; - endcase - // }}} - - // o_wb_stall - // {{{ - // This device never stalls. Sure, it takes two clocks, but they are - // pipelined, and nothing stalls that pipeline. (Creates FIFO errors, - // perhaps, but doesn't stall the pipeline.) Hence, we can just - // set this value to zero. - assign o_wb_stall = 1'b0; - // }}} - // }}} - - // Make verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_data[31] }; - // verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/wbubus/wbconsole.v b/delete_later/rtl/wbubus/wbconsole.v deleted file mode 100644 index c005f4b..0000000 --- a/delete_later/rtl/wbubus/wbconsole.v +++ /dev/null @@ -1,374 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbconsole.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Unlilke wbuart-insert.v, this is a full blown wishbone core -// with integrated FIFO support to support the UART transmitter -// and receiver found within here. As a result, it's usage may be -// heavier on the bus than the insert, but it may also be more useful. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbconsole #( - parameter [3:0] LGFLEN = 4 - ) ( - // {{{ - input wire i_clk, i_reset, - // Wishbone inputs - // {{{ - input wire i_wb_cyc, i_wb_stb, i_wb_we, - input wire [1:0] i_wb_addr, - input wire [31:0] i_wb_data, - input wire [3:0] i_wb_sel, - output wire o_wb_stall, - output reg o_wb_ack, - output reg [31:0] o_wb_data, - // }}} - // TX - // {{{ - output wire o_uart_stb, - output wire [6:0] o_uart_data, - input wire i_uart_busy, - // }}} - // RX - // {{{ - input wire i_uart_stb, - input wire [6:0] i_uart_data, - // }}} - // Interrupts - output wire o_uart_rx_int, o_uart_tx_int, - o_uart_rxfifo_int, o_uart_txfifo_int, - // - output reg [31:0] o_debug - // }}} - ); - - // Local declarations - // {{{ - // parameter [0:0] HARDWARE_FLOW_CONTROL_PRESENT = 1'b1; - // Perform a simple/quick bounds check on the log FIFO length, to make - // sure its within the bounds we can support with our current - // interface. - localparam [3:0] LCLLGFLEN = (LGFLEN > 4'ha)? 4'ha - : ((LGFLEN < 4'h2) ? 4'h2 : LGFLEN); - // - // - localparam [1:0] UART_SETUP = 2'b00, - UART_FIFO = 2'b01, - UART_RXREG = 2'b10, - UART_TXREG = 2'b11; - - reg rx_uart_reset; - wire rx_empty_n, rx_fifo_err; - wire [6:0] rxf_wb_data; - wire [15:0] rxf_status; - reg rxf_wb_read; - - wire [31:0] wb_rx_data; - - wire tx_empty_n, txf_err; - wire [15:0] txf_status; - reg txf_wb_write, tx_uart_reset; - reg [6:0] txf_wb_data; - - wire [31:0] wb_tx_data; - wire [31:0] wb_fifo_data; - reg [1:0] r_wb_addr; - reg r_wb_ack; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // First, the receiver - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // We place it into a receiver FIFO. - - // And here's the FIFO proper. - // - // Note that the FIFO will be cleared upon any reset: either if there's - // a UART break condition on the line, the receiver is in reset, or an - // external reset is issued. - // - // The FIFO accepts strobe and data from the receiver. - // We issue another wire to it (rxf_wb_read), true when we wish to read - // from the FIFO, and we get our data in rxf_wb_data. The FIFO outputs - // four status-type values: 1) is it non-empty, 2) is the FIFO over half - // full, 3) a 16-bit status register, containing info regarding how full - // the FIFO truly is, and 4) an error indicator. - ufifo #( - .LGFLEN(LCLLGFLEN), .BW(7), .RXFIFO(1) - ) rxfifo( - // {{{ - i_clk, (i_reset)||(rx_uart_reset), - i_uart_stb, i_uart_data, - rx_empty_n, - rxf_wb_read, rxf_wb_data, - rxf_status, rx_fifo_err - // }}} - ); - - assign o_uart_rxfifo_int = rxf_status[1]; - - // We produce four interrupts. One of the receive interrupts indicates - // whether or not the receive FIFO is non-empty. This should wake up - // the CPU. - assign o_uart_rx_int = rxf_status[0]; - - // If the bus requests that we read from the receive FIFO, we need to - // tell this to the receive FIFO. Note that because we are using a - // clock here, the output from the receive FIFO will necessarily be - // delayed by an extra clock. - initial rxf_wb_read = 1'b0; - always @(posedge i_clk) - rxf_wb_read <= (i_wb_stb)&&(i_wb_addr[1:0]==UART_RXREG) - && !i_wb_we && i_wb_sel[0]; - - initial rx_uart_reset = 1'b1; - always @(posedge i_clk) - if (i_reset) - rx_uart_reset <= 1'b1; - else begin - rx_uart_reset <= 1'b0; - - if (i_wb_stb && i_wb_we) - begin - if (i_wb_addr[1:0]==UART_SETUP && i_wb_sel[0]) - // The receiver reset, always set on a master - // reset request. - rx_uart_reset <= 1'b1; - - if (i_wb_addr[1:0]==UART_RXREG && i_wb_sel[1] - && i_wb_data[12]) - // Writes to the receive register will command - // a receive reset anytime bit[12] is set. - rx_uart_reset <= 1'b1; - end - end - - // Finally, we'll construct a 32-bit value from these various wires, - // to be returned over the bus on any read. These include the data - // that would be read from the FIFO, an error indicator set upon - // reading from an empty FIFO, a break indicator, and the frame and - // parity error signals. - assign wb_rx_data = { 16'h00, - 3'h0, rx_fifo_err, - 1'b0, 1'b0, 1'b0, !rx_empty_n, - 1'b0, rxf_wb_data}; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Then the UART transmitter - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Unlike the receiver which goes from RXUART -> UFIFO -> WB, the - // transmitter basically goes WB -> UFIFO -> TXUART. Hence, to build - // support for the transmitter, we start with the command to write data - // into the FIFO. In this case, we use the act of writing to the - // UART_TXREG address as our indication that we wish to write to the - // FIFO. Here, we create a write command line, and latch the data for - // the extra clock that it'll take so that the command and data can be - // both true on the same clock. - initial txf_wb_write = 1'b0; - always @(posedge i_clk) - begin - txf_wb_write <= (i_wb_stb)&&(i_wb_addr == UART_TXREG) - && i_wb_we && i_wb_sel[0]; - txf_wb_data <= i_wb_data[6:0]; - end - - // Transmit FIFO - // {{{ - // Most of this is just wire management. The TX FIFO is identical in - // implementation to the RX FIFO (theyre both UFIFOs), but the TX - // FIFO is fed from the WB and read by the transmitter. Some key - // differences to note: we reset the transmitter on any request for a - // break. We read from the FIFO any time the UART transmitter is idle. - // and ... we just set the values (above) for controlling writing into - // this. - ufifo #( - .LGFLEN(LGFLEN), .BW(7), .RXFIFO(0) - ) txfifo( - // {{{ - i_clk, (tx_uart_reset), - txf_wb_write, txf_wb_data, - tx_empty_n, - (!i_uart_busy)&&(tx_empty_n), o_uart_data, - txf_status, txf_err - // }}} - ); - // }}} - - assign o_uart_stb = tx_empty_n; - - // Let's create two transmit based interrupts from the FIFO for the CPU. - // The first will be true any time the FIFO has at least one open - // position within it. - assign o_uart_tx_int = txf_status[0]; - // The second will be true any time the FIFO is less than half - // full, allowing us a change to always keep it (near) fully - // charged. - assign o_uart_txfifo_int = txf_status[1]; - - // TX-Reset logic - // {{{ - // This is nearly identical to the RX reset logic above. Basically, - // any time someone writes to bit [12] the transmitter will go through - // a reset cycle. Keep bit [12] low, and everything will proceed as - // normal. - initial tx_uart_reset = 1'b1; - always @(posedge i_clk) - if((i_reset)||((i_wb_stb)&&(i_wb_addr == UART_SETUP && i_wb_sel[0])&&(i_wb_we))) - tx_uart_reset <= 1'b1; - else if ((i_wb_stb)&&(i_wb_addr[1:0]==UART_TXREG)&&(i_wb_we)) - tx_uart_reset <= i_wb_data[12] && i_wb_sel[1]; - else - tx_uart_reset <= 1'b0; - // }}} - - // Now that we are done with the chain, pick some wires for the user - // to read on any read of the transmit port. - // - // This port is different from reading from the receive port, since - // there are no side effects. (Reading from the receive port advances - // the receive FIFO, here only writing to the transmit port advances the - // transmit FIFO--hence the read values are free for ... whatever.) - // We choose here to provide information about the transmit FIFO - // (txf_err, txf_half_full, txf_full_n), information about the current - // voltage on the line (o_uart_tx)--and even the voltage on the receive - // line (ck_uart), as well as our current setting of the break and - // whether or not we are actively transmitting. - assign wb_tx_data = { 16'h00, - 1'b0, txf_status[1:0], txf_err, - 1'b0, o_uart_stb, 1'b0, - (i_uart_busy|tx_empty_n), - 1'b0,(i_uart_busy|tx_empty_n)?txf_wb_data:7'h0}; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Bus return handling - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Each of the FIFO's returns a 16 bit status value. This value tells - // us both how big the FIFO is, as well as how much of the FIFO is in - // use. Let's merge those two status words together into a word we - // can use when reading about the FIFO. - assign wb_fifo_data = { txf_status, rxf_status }; - - // You may recall from above that reads take two clocks. Hence, we - // need to delay the address decoding for a clock until the data is - // ready. We do that here. - always @(posedge i_clk) - r_wb_addr <= i_wb_addr; - - // o_wb_ack - // {{{ - // Likewise, the acknowledgement is delayed by one clock. - always @(posedge i_clk) // We'll ACK in two clocks - if (i_reset || !i_wb_cyc) - r_wb_ack <= 1'b0; - else - r_wb_ack <= i_wb_stb; - - always @(posedge i_clk) // Okay, time to set the ACK - if (i_reset || !i_wb_cyc) - o_wb_ack <= 1'b0; - else - o_wb_ack <= r_wb_ack; - // }}} - - // o_wb_data - // {{{ - // Finally, set the return data. This data must be valid on the same - // clock o_wb_ack is high. On all other clocks, it is irrelelant--since - // no one cares, no one is reading it, it gets lost in the mux in the - // interconnect, etc. For this reason, we can just simplify our logic. - always @(posedge i_clk) - casez(r_wb_addr) - UART_SETUP: o_wb_data <= 32'h0; - UART_FIFO: o_wb_data <= wb_fifo_data; - UART_RXREG: o_wb_data <= wb_rx_data; - UART_TXREG: o_wb_data <= wb_tx_data; - endcase - // }}} - - // This device never stalls. Sure, it takes two clocks, but they are - // pipelined, and nothing stalls that pipeline. (Creates FIFO errors, - // perhaps, but doesn't stall the pipeline.) Hence, we can just - // set this value to zero. - assign o_wb_stall = 1'b0; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // A debug return - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - begin - o_debug[31:16] <= { txf_status[11:0], rxf_status[3:0] }; - - // - // Transmit byte - o_debug[15] <= tx_empty_n; - if ((i_wb_stb)&&(i_wb_addr[1:0]==UART_TXREG)&&(i_wb_we && i_wb_sel[0])) - o_debug[14:8] <= i_wb_data[6:0]; - else if (o_uart_stb) - o_debug[14:8] <= o_uart_data; - else - o_debug[14:8] <= 0; - // - // Received - o_debug[7] <= i_uart_stb; - if (i_uart_stb) - o_debug[6:0] <= i_uart_data; - else - o_debug[6:0] <= rxf_wb_data; - end - // }}} - - // Make verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, i_wb_cyc, i_wb_data[31:13], i_wb_data[11:7], - i_wb_sel }; - // verilator lint_on UNUSED - // }}} -endmodule diff --git a/delete_later/rtl/wbubus/wbubus.v b/delete_later/rtl/wbubus/wbubus.v deleted file mode 100644 index 8482fd9..0000000 --- a/delete_later/rtl/wbubus/wbubus.v +++ /dev/null @@ -1,329 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbubus.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is the top level file for the entire JTAG-USB to Wishbone -// bus conversion. (It's also the place to start debugging, should -// things not go as planned.) Bytes come into this routine, bytes go out, -// and the wishbone bus (external to this routine) is commanded in between. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbubus #( - // {{{ - parameter LGWATCHDOG=19, - LGINPUT_FIFO=6, - LGOUTPUT_FIFO=10, - parameter [0:0] CMD_PORT_OFF_UNTIL_ACCESSED = 1'b1, - parameter AW = 30 - // }}} - ) ( - // {{{ - input wire i_clk, - input wire i_reset, - // RX - // {{{ - input wire i_rx_stb, - input wire [7:0] i_rx_data, - // }}} - // Wishbone master - // {{{ - output wire o_wb_cyc, o_wb_stb, o_wb_we, - output wire [AW-1:0] o_wb_addr, - output wire [31:0] o_wb_data, - input wire i_wb_stall, i_wb_ack, - input wire [31:0] i_wb_data, - input wire i_wb_err, - // }}} - input wire i_interrupt, - // TX - // {{{ - output wire o_tx_stb, - output wire [7:0] o_tx_data, - input wire i_tx_busy - // }}} - // , output wire o_dbg; - // }}} - ); - - // Local declarations - // {{{ - wire soft_reset; - reg r_wdt_reset; - wire cmd_port_active, w_tx_stb; - - // RX byte - wire rx_valid; - wire [7:0] rx_data; - - // Incoming code word, once processed - wire in_stb, in_active; - wire [35:0] in_word; - - // Input FIFO - wire ififo_valid; - wire [35:0] ififo_codword; - - // Code word outputs from running the bus - wire exec_stb; - wire [35:0] exec_word; - - // Output FIFO - wire ofifo_rd; - wire [35:0] ofifo_codword; - wire ofifo_err, ofifo_empty_n; - - wire w_bus_busy, w_bus_reset; - reg [(LGWATCHDOG-1):0] r_wdt_timer; - wire ign_input_busy; - wire output_busy, out_active; - - // wire [30:0] out_dbg; - // }}} - - // cmd_port_active - // {{{ - generate if (CMD_PORT_OFF_UNTIL_ACCESSED) - begin : GEN_DEACTIVATEPORT - - reg r_cmd_port_active; - - initial r_cmd_port_active = 1'b0; - always @(posedge i_clk) - if (i_rx_stb && i_rx_data[7]) - r_cmd_port_active <= 1'b1; - - assign cmd_port_active = r_cmd_port_active; - - end else begin : GEN_ALWAYSON - - assign cmd_port_active = 1'b1; - - end endgenerate - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // Decode ASCII input requests into WB bus cycle requests - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign rx_valid = i_rx_stb; - assign rx_data = i_rx_data; - - wbuinput - getinput( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_stb(rx_valid), .o_busy(ign_input_busy), - .i_byte(rx_data), - .o_soft_reset(soft_reset), - .o_stb(in_stb), .i_busy(1'b0), .o_codword(in_word), - .o_active(in_active) - // }}} - ); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The input FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - generate if (LGINPUT_FIFO < 2) - begin : NO_INPUT_FIFO - - assign ififo_valid = in_stb; - assign ififo_codword = in_word; - assign w_bus_reset = soft_reset; - - end else begin : INPUT_FIFO - - wire ififo_empty_n, ififo_err, ififo_rd; - - assign ififo_rd = (!w_bus_busy)&&(ififo_empty_n); - assign ififo_valid = (ififo_empty_n); - assign w_bus_reset = r_wdt_reset; - - wbufifo #( - // {{{ - .BW(36),.LGFLEN(LGINPUT_FIFO) - // }}} - ) padififo( - // {{{ - .i_clk(i_clk), .i_reset(w_bus_reset), - .i_wr(in_stb), .i_data(in_word), - .i_rd(ififo_rd), .o_data(ififo_codword), - .o_empty_n(ififo_empty_n), .o_err(ififo_err) - // }}} - ); - - // verilator lint_off UNUSED - wire gen_unused; - assign gen_unused = &{ 1'b0, ififo_err }; - // verilator lint_on UNUSED - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Run the bus - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Take requests in, Run the bus, send results out - // This only works if no requests come in while requests - // are pending. - wbuexec #( - // .LGFIFO(LGOUTPUT_FIFO) - .AW(AW) - ) runwb( - // {{{ - .i_clk(i_clk), .i_reset(r_wdt_reset), - // - .i_valid(ififo_valid), .i_codword(ififo_codword), - .o_busy(w_bus_busy), - // - .o_wb_cyc(o_wb_cyc), .o_wb_stb(o_wb_stb), .o_wb_we(o_wb_we), - .o_wb_addr(o_wb_addr), .o_wb_data(o_wb_data), - .i_wb_stall(i_wb_stall), .i_wb_ack(i_wb_ack), - .i_wb_data(i_wb_data), .i_wb_err(i_wb_err), - // - .o_stb(exec_stb), .o_codword(exec_word), .i_fifo_rd(ofifo_rd) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Output FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (LGOUTPUT_FIFO < 2) - begin : NO_OUTBOUND_FIFO - - assign ofifo_rd = exec_stb; - assign ofifo_codword = exec_word; - assign ofifo_err = 1'b0; - assign ofifo_empty_n = exec_stb; - - end else begin : GEN_OUTBOUND_FIFO - - assign ofifo_rd = ofifo_empty_n && !output_busy; - wbufifo #( - .BW(36), .LGFLEN(LGOUTPUT_FIFO) - ) busoutfifo ( - // {{{ - .i_clk(i_clk), .i_reset(r_wdt_reset), - .i_wr(exec_stb), .i_data(exec_word), - .i_rd(ofifo_rd), .o_data(ofifo_codword), - .o_empty_n(ofifo_empty_n), - .o_err(ofifo_err) - // }}} - ); - - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Encode bus outputs into a serial data stream - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wbuoutput - wroutput( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), .i_soft_reset(w_bus_reset), - .i_stb(ofifo_rd), .i_codword(ofifo_codword), - .o_busy(output_busy), - // - .i_wb_cyc(o_wb_cyc), .i_int(i_interrupt), - .i_bus_busy(exec_stb || ofifo_empty_n), - .o_stb(w_tx_stb), .o_char(o_tx_data), .i_tx_busy(i_tx_busy), - .o_active(out_active) - // }}} - ); - - assign o_tx_stb = w_tx_stb && cmd_port_active; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Watchdog timer - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Add in a watchdog timer to the bus - initial r_wdt_reset = 1'b1; - initial r_wdt_timer = 0; - always @(posedge i_clk) - if (i_reset || soft_reset) - begin - r_wdt_timer <= 0; - r_wdt_reset <= 1'b1; - end else if ((!o_wb_cyc)||(i_wb_ack)) - begin - // We're inactive, or the bus has responded: reset the timer - // {{{ - r_wdt_timer <= 0; - r_wdt_reset <= 1'b0; - // }}} - end else if (&r_wdt_timer) - begin // TIMEOUT!!! - // {{{ - r_wdt_reset <= 1'b1; - r_wdt_timer <= 0; - // }}} - end else begin // Tick-tock ... - r_wdt_timer <= r_wdt_timer+{{(LGWATCHDOG-1){1'b0}},1'b1}; - r_wdt_reset <= 1'b0; - end - // }}} - - // Make Verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, ofifo_err, ign_input_busy, - out_active, in_active }; - // verilator lint_on UNUSED - // }}} -endmodule - diff --git a/delete_later/rtl/wbubus/wbucompactlines.v b/delete_later/rtl/wbubus/wbucompactlines.v deleted file mode 100644 index 169d03d..0000000 --- a/delete_later/rtl/wbubus/wbucompactlines.v +++ /dev/null @@ -1,352 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbucompactlines.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Removes 'end of line' characters placed at the end of every -// deworded word, unless we're idle or the line is too long. -// This helps to format the output nicely to fit in an 80-character -// display, should you need to do so for debugging. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -// -// When to apply a new line? -// When no prior new line exists -// or when prior line length exceeds (72) -// Between codewords (need inserted newline) -// When bus has become idle (~wb_cyc)&&(~busys) -// -// So, if every codeword ends in a newline, what we -// really need to do is to remove newlines. Thus, if -// i_stb goes high while i_tx_busy, we skip the newline -// unless the line is empty. ... But i_stb will always -// go high while i_tx_busy. How about if the line -// length exceeds 72, we do nothing, but record the -// last word. If the last word was a -// -`default_nettype none -// }}} -module wbucompactlines ( - // {{{ - input wire i_clk, i_reset, i_stb, - input wire [6:0] i_nl_hexbits, - output reg o_stb, - output reg [6:0] o_nl_hexbits, - input wire i_bus_busy, - input wire i_tx_busy, - output wire o_busy, - output wire o_active - // }}} - ); - - // Local declarations - // {{{ - localparam [6:0] MAX_LINE_LENGTH = 79; - localparam [6:0] TRIGGER_LENGTH = (MAX_LINE_LENGTH-6); - reg last_out_nl, last_in_nl, full_line, r_busy; - reg [6:0] linelen; - // }}} - - // last_out_nl - // {{{ - initial last_out_nl = 1'b1; - always @(posedge i_clk) - if (i_reset) - last_out_nl <= 1'b1; - else if (!i_tx_busy && o_stb) - last_out_nl <= o_nl_hexbits[6]; - // }}} - - // last_in_nl - // {{{ - initial last_in_nl = 1'b1; - always @(posedge i_clk) - if (i_reset) - last_in_nl <= 1'b1; - else if (i_stb && !o_busy) - last_in_nl <= i_nl_hexbits[6]; - // }}} - - // linelen - // {{{ - // Now, let's count how long our lines are - initial linelen = 7'h00; - always @(posedge i_clk) - if (i_reset) - linelen <= 0; - else if (!i_tx_busy && o_stb) - begin - if (o_nl_hexbits[6]) - linelen <= 0; - else - linelen <= linelen + 7'h1; - end - // }}} - - // full_line - // {{{ - initial full_line = 1'b0; - always @(posedge i_clk) - if (i_reset) - full_line <= 0; - else if (!i_tx_busy && o_stb) - begin - if (o_nl_hexbits[6]) - full_line <= 0; - else - full_line <= (linelen >= TRIGGER_LENGTH); - end - // }}} - - - // o_stb, o_nl_hexbits - // {{{ - // Now that we know whether or not the last character was a newline, - // and indeed how many characters we have in any given line, we can - // selectively remove newlines from our output stream. - initial o_stb = 1'b0; - always @(posedge i_clk) - begin - if (i_stb && !o_busy) - begin - // Only accept incoming newline requests if our line is - // already full, otherwise quietly suppress them - o_stb <= (full_line)||(!i_nl_hexbits[6]); - o_nl_hexbits <= i_nl_hexbits; - end else if (!o_busy) - begin // Send an EOL if we are idle - - // Without a request, we'll add a newline, but only if - // 1. There's nothing coming down the channel - // (!bus_busy) - // 2. What we last sent wasn't a new-line - // 3. The last thing that came in was a newline - // In otherwords, we can resurrect one of the newlines - // we squashed above - o_stb <= (!i_tx_busy)&&(!i_bus_busy)&&(!last_out_nl)&&(last_in_nl); - o_nl_hexbits <= 7'h40; - end else if (!i_tx_busy) - o_stb <= 1'b0; - - if (i_reset) - o_stb <= 1'b0; - end - // }}} - - // o_busy - // {{{ - initial r_busy = 1'b0; - always @(posedge i_clk) - if (i_reset) - r_busy <= 1'b0; - else - r_busy <= o_stb && i_tx_busy; - - assign o_busy = (r_busy)||(o_stb); - // }}} - - assign o_active = i_stb || (i_tx_busy && !last_out_nl && last_in_nl); - /* - output wire [27:0] o_dbg; - assign o_dbg = { o_stb, o_nl_hexbits, o_busy, r_busy, full_line, - i_bus_busy, linelen, i_tx_busy, i_stb, i_nl_hexbits }; - */ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_MAX_WORD_LENGTH = 6; - reg f_past_valid; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - //////////////////////////////////////////////////////////////////////// - // - // Assumptions - // - //////////////////////////////////////////////////////////////////////// - // - // - reg [2:0] f_nonnl_count; - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - assume(!i_stb); - end else if (f_past_valid && $past(i_stb && o_busy)) - begin - assume(i_stb); - - // Our protocol actually allows i_nl_hexbits to change - // while i_stb is true - end - - always @(*) - if (i_stb && i_nl_hexbits[6]) - assume(i_nl_hexbits[5:0] == 0); - - initial f_nonnl_count = 0; - always @(posedge i_clk) - if (i_stb && !o_busy) - begin - if (i_nl_hexbits[6]) - f_nonnl_count <= 0; - else - f_nonnl_count <= f_nonnl_count + 1;; - end - - always @(*) - assume(f_nonnl_count <= F_MAX_WORD_LENGTH); - - //////////////////////////////////////////////////////////////////////// - // - // The contract - // - All incoming data must go out - // (if incoming[6], incoming == 7'h40) - // - save that newlines may be suppressed - // - Prove that the output will always be less than 80 characters - // - //////////////////////////////////////////////////////////////////////// - // - // - reg f_pending_nl; - - - always @(*) - assert(linelen <= MAX_LINE_LENGTH); - - // The outgoing channel doesn't change unless/until it has been - // accepted - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && o_stb && i_tx_busy)) - assert(o_stb && $stable(o_nl_hexbits)); - - // Requested (non-newline) incoming data always goes to the outgoing - // channel unmolested - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && i_stb - && !o_busy && !i_nl_hexbits[6])) - assert(o_stb && (o_nl_hexbits == $past(i_nl_hexbits))); - - always @(*) - assert(full_line == (linelen > TRIGGER_LENGTH)); - - always @(*) - if (o_stb && !o_nl_hexbits[6]) - assert(linelen + 1 <= MAX_LINE_LENGTH); - - always @(*) - if (!o_stb || !o_nl_hexbits[6]) - assert((F_MAX_WORD_LENGTH - f_nonnl_count) + linelen - + ((o_busy&&!o_nl_hexbits[6]) ? 1:0) <=MAX_LINE_LENGTH); - - always @(*) - if (o_stb && o_nl_hexbits[6]) - assert(o_nl_hexbits[5:0] == 0); - - initial f_pending_nl = 0; - always @(posedge i_clk) - if (i_reset) - f_pending_nl <= 0; - else if (i_stb && !o_busy) - f_pending_nl <= (i_nl_hexbits[6]) && !last_out_nl; - else if (o_stb && o_nl_hexbits[6]) - f_pending_nl <= 0; - - always @(*) - if (!last_in_nl) - assert(!o_stb || !o_nl_hexbits[6]); - - always @(*) - if (last_in_nl && !last_out_nl) - assert(f_pending_nl || (o_stb && o_nl_hexbits[6])); - else if (!o_stb || !o_nl_hexbits[6]) - assert(f_pending_nl == 1'b0); - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && $past(!o_stb || !i_tx_busy)) - begin - if (o_stb && o_nl_hexbits[6]) - assert(f_pending_nl); - end - - always @(*) - if (last_in_nl) - assert(!o_stb || o_nl_hexbits[6]); - - always @(*) - if (last_out_nl) - assert(last_in_nl || (o_stb && !o_nl_hexbits[6])); - - always @(*) - if (last_out_nl) - begin - assert(linelen == 0); - assert(!o_stb || !o_nl_hexbits[6]); - end - - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // - //////////////////////////////////////////////////////////////////////// - // - // - reg f_cvr_valid; - reg [5:0] f_cvr_counter; - - initial f_cvr_counter = 0; - always @(posedge i_clk) - if (i_reset) - f_cvr_counter <= 0; - else if (i_stb && !o_busy && !i_nl_hexbits[6]) - f_cvr_counter <= f_cvr_counter + 1; - - initial f_cvr_valid = 1; - always @(posedge i_clk) - if (i_reset) - f_cvr_valid <= 0; - else if (i_stb && !i_nl_hexbits[6] - && (i_nl_hexbits[5:0] != f_cvr_counter)) - f_cvr_valid <= 0; - - always @(*) - cover(f_cvr_valid && (linelen == MAX_LINE_LENGTH)); - always @(*) - cover(f_cvr_valid && o_stb && !i_tx_busy && o_nl_hexbits[6]); -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wbubus/wbucompress.v b/delete_later/rtl/wbubus/wbucompress.v deleted file mode 100644 index a45e296..0000000 --- a/delete_later/rtl/wbubus/wbucompress.v +++ /dev/null @@ -1,780 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbucompress.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: When reading many words that are identical, it makes no sense -// to spend the time transmitting the same thing over and over -// again, especially on a slow channel. Hence this routine uses a table -// lookup to see if the word to be transmitted was one from the recent -// past. If so, the word is replaced with an address of the recently -// transmitted word. Mind you, the table lookup takes one clock per table -// entry, so even if a word is in the table it might not be found in time. -// If the word is not in the table, or if it isn't found due to a lack of -// time, the word is placed into the table while incrementing every other -// table address. -// -// Oh, and on a new address--the table is reset and starts over. This way, -// any time the host software changes, the host software will always start -// by issuing a new address--hence the table is reset for every new piece -// of software that may wish to communicate. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// -// All input words are valid codewords. If we can, we make them -// better here. -// }}} -module wbucompress #( - parameter DW=32, CW=36, TBITS=10 - ) ( - // {{{ - input wire i_clk, i_reset, i_stb, - input wire [(CW-1):0] i_codword, - input wire i_busy, - output reg o_stb, - output wire [(CW-1):0] o_cword, - output wire o_busy, - output wire o_active - // }}} - ); - - // Local declarations - // {{{ - // First stage is to compress the address. - // This stage requires one clock. - // - // ISTB,ICODWORD - // ISTB2,IWRD2 ASTB,AWORD - // ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1) - // ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1) - // ISTB3,IWRD3 ASTB2,AWRD2 I_BUSY(1) - // ISTB3,IWRD3 ASTB2,AWRD2 - // ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2) - // ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2) - // ISTB4,IWRD4 ASTB3,AWRD3 I_BUSY(2) - reg aword_valid; - reg [35:0] a_addrword; - wire [31:0] w_addr; - wire [3:0] addr_zcheck; - wire tbl_busy; - - wire w_accepted; - reg [35:0] r_word; - reg [(TBITS-1):0] tbl_addr; - reg tbl_filled; - reg [31:0] compression_tbl [0:((1< 1); - end else if (o_cword[35:34] == 2'b01) - begin - assert(compression_tbl[f_match_addr] == { r_word[32:31], r_word[29:0] }); - assert(r_cword[33:31] == f_adr_dbld[8:6]); - assert(r_cword[30] == r_word[30]); - assert(r_cword[29:24] == f_adr_dbld[5:0]); - assert(f_matchaddr >= 10); - assert(f_matchaddr -10 <= 10'h1ff); - end else - assert(o_cword == r_word); - end - - always @(posedge i_clk) - if ((f_past_valid)&&($past(!i_reset && o_stb && i_busy))) - begin - assert(o_stb); - - // Once a match has taken place, or similarly if this codeword - // isn't a matchable one, then it should be stable - if ($past(o_cword[35:33]) != 3'b111) - assert($stable(o_cword)); - end - -`ifdef VERIFIC - reg [4:0] r_seq_counter; - always @(posedge i_clk) - r_seq_counter <= r_seq_counter + 1; - - assert property (@(posedge i_clk) - // This complicated sequence makes sure we abort the test - // if i_busy drops too early - disable iff (i_reset - || (r_seq_counter > 1)&&(r_seq_counter < 7)&&(!i_busy)) - // - // Two setup clocks - // - (o_stb && !i_busy && o_cword[35:33] == 3'b111) - &&(r_seq_counter == 0) - ##1 o_stb && $stable(o_cword) && i_busy - |-> (rd_addr == $past(tbl_addr)) - ##1 (cword == $past({ r_word[32:31], r_word[29:0] })) - ##1 dmatch && w_match - ##1 o_stb && o_cword[35:31] == 5'h3); - - assert property (@(posedge i_clk) - disable iff (i_reset - || (r_seq_counter > 2)&&(r_seq_counter < 7)&&(!i_busy)) - // - // Accept two words - (o_stb && !i_busy && o_cword[35:33] == 3'b111) - &&(r_seq_counter == 0) - ##1 (o_stb && !i_busy && $changed({o_cword[32:31], o_cword[29:0]}) - && (o_cword[35:33] == 3'b111)) - // Receive a third, identical to the first - ##1 (o_stb && o_cword == $past(o_cword,2))&&(i_busy) - |=> ##1 (cword == $past({ r_word[32:31], r_word[29:0] },2)) - &&(r_seq_counter == 4) - ##1 dmatch && w_match && hmatch - ##1 o_stb && (o_cword[35:34] == 2'b10) - && (o_cword[33:31] == 3'b000)); -`endif - - //////////////////////////////////////////////////////////////////////// - // - // Induction assertions - // - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - if (aword_valid) - begin - assert(a_addrword[35:31] != 5'h3); - assert(a_addrword[35:34] != 2'b01); - assert(a_addrword[35:34] != 2'b10); - end - - always @(posedge i_clk) - if (!matched && !w_match) - f_matchaddr <= maddr; - - always @(*) - f_rd_diff = tbl_addr - rd_addr; - - always @(*) - if (o_stb) - assert(f_rd_diff == dffaddr); - - - always @(posedge i_clk) - f_caddr <= rd_addr; - always @(posedge i_clk) - f_daddr <= f_caddr; - - always @(*) - f_match_addr = tbl_addr - f_matchaddr; - - always @(*) - if (matched) - begin - assert(adr_dbld == f_adr_dbld); - assert(adr_hlfd == f_adr_hlfd); - end - - always @(*) - if (o_stb && dmatch) - begin - assert(compression_tbl[f_daddr] == { r_word[32:31], r_word[29:0] }); - // assert(maddr == tbl_addr - f_daddr); - end - - always @(*) - if (o_stb && matched) - begin - assert(compression_tbl[f_match_addr] == { r_word[32:31], r_word[29:0] }); - end - - always @(*) - if (matched) - begin - assert({ 1'b0, f_match_addr } < { tbl_filled, tbl_addr }); - assert(f_match_addr != tbl_addr ); - assert(compression_tbl[f_match_addr] - == { r_word[32:31], r_word[29:0] }); - end - - always @(*) - if (r_word[35:33] != 3'b111) - assert(!matched); - - //////////////////////////////////////////////////////////////////////// - // - // Cover checks - // - //////////////////////////////////////////////////////////////////////// - // - // - - reg [1:0] f_cvr_repeat_values, f_cvr_half_codewords, f_cvr_full_codewords; - reg [35:0] f_last_codeword; - reg f_set_last; - reg [4:0] f_time_since_last; - - - initial { f_cvr_repeat_values, f_cvr_half_codewords, f_cvr_full_codewords } = 0; - always @(posedge i_clk) - if (i_reset) - { f_cvr_repeat_values, f_cvr_half_codewords, f_cvr_full_codewords } <= 0; - else if (o_stb && !i_busy) - begin - if ((o_cword[35:31] == 5'h3)&&(!(&f_cvr_repeat_values))) - f_cvr_repeat_values <= f_cvr_repeat_values + 1; - if ((o_cword[35:34] == 2'b10)&&(!(&f_cvr_half_codewords))) - f_cvr_half_codewords <= f_cvr_half_codewords + 1; - if ((o_cword[35:34] == 2'b01)&&(!(&f_cvr_full_codewords))) - f_cvr_full_codewords <= f_cvr_full_codewords + 1; - end - - always @(*) - cover(o_stb && !i_busy); - - always @(*) - cover(cword == { r_word[32:31], r_word[29:0] }); - - always @(*) - cover(cword == { r_word[32:31], r_word[29:0] } && pmatch); - - always @(posedge i_clk) - cover(cword == { r_word[32:31], r_word[29:0] } && pmatch); - - always @(*) - cover((cword == { r_word[32:31], r_word[29:0] }) && pmatch - && (tbl_addr == 1) && (rd_addr == 10'h3ff)); - - always @(*) - cover((cword == { r_word[32:31], r_word[29:0] }) && pmatch - && (tbl_addr == 1)); - - always @(posedge i_clk) - cover((tbl_addr == 1) && o_stb &&i_busy); - - always @(*) - cover(cword == { r_word[32:31], r_word[29:0] } && pmatch && vaddr); - - always @(*) - cover(dmatch); - - always @(*) - cover(w_match); - - always @(*) - cover(!matched && w_match); - - always @(*) - cover(o_stb && !i_busy && o_cword[35:31] == 5'h3); - - initial f_set_last = 0; - always @(posedge i_clk) - if (i_reset) - f_set_last <= 0; - else if (o_stb && !i_busy && o_cword[35:33] == 3'b111) - f_set_last <= 1; - - initial f_time_since_last = 0; - always @(posedge i_clk) - if (!o_stb || !i_busy) - f_time_since_last <= 0; - else if (f_set_last && !(&(f_time_since_last))) - f_time_since_last <= f_time_since_last + 1; - - always @(posedge i_clk) - if (o_stb && !i_busy && o_cword[35:33] == 3'b111) - f_last_codeword <= o_cword; - - always @(*) - cover(o_stb && !i_busy && f_set_last); - - always @(*) - cover(o_stb && !i_busy && f_set_last && f_time_since_last > 4 - &&(r_word == f_last_codeword)); - - - always @(*) - begin - cover(f_cvr_full_codewords != 0); - cover(f_cvr_half_codewords != 0); - cover(f_cvr_repeat_values != 0); - // - cover(f_cvr_full_codewords == 0); - cover(f_cvr_full_codewords == 1); - cover(f_cvr_full_codewords == 2); - // - cover(&f_cvr_full_codewords); - cover(&f_cvr_half_codewords); - cover(&f_cvr_repeat_values); - // - cover((&f_cvr_repeat_values) && (&f_cvr_half_codewords)); - cover((&f_cvr_repeat_values) && (&f_cvr_full_codewords)); - // - cover((&f_cvr_repeat_values) && (&f_cvr_half_codewords) - &&(&f_cvr_full_codewords)); - end - - -`endif -// }}} -endmodule - diff --git a/delete_later/rtl/wbubus/wbuconsole.v b/delete_later/rtl/wbubus/wbuconsole.v deleted file mode 100644 index bbaf441..0000000 --- a/delete_later/rtl/wbubus/wbuconsole.v +++ /dev/null @@ -1,394 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbuconsole.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is the top level file for the entire JTAG-USB to Wishbone -// bus conversion. (It's also the place to start debugging, should -// things not go as planned.) Bytes come into this routine, bytes go out, -// and the wishbone bus (external to this routine) is commanded in between. -// -// You may find some strong similarities between this module and the -// wbubus module. They two are essentially the same, with the exception -// that this version will also multiplex a serial port together with -// the JTAG-USB->wishbone conversion. Graphically: -// -// devbus -> TCP/IP \ / -> WB master -// MUXED over USB -> UART -// console -> TCP/IP / \ -> wbuconsole -// -// Doing this, however, also entails stripping the 8th bit from the UART -// port, so the serial port so contrived can only handle 7-bit data. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbuconsole #( - // {{{ - parameter LGWATCHDOG=19, - LGINPUT_FIFO=6, - LGOUTPUT_FIFO=10, - parameter [0:0] CMD_PORT_OFF_UNTIL_ACCESSED = 1'b0, - parameter AW = 30 - // }}} - ) ( - // {{{ - input wire i_clk, - input wire i_reset, - // RX - // {{{ - input wire i_rx_stb, - input wire [7:0] i_rx_data, - // }}} - // Wishbone master - // {{{ - output wire o_wb_cyc, o_wb_stb, o_wb_we, - output wire [AW-1:0] o_wb_addr, - output wire [31:0] o_wb_data, - input wire i_wb_stall, i_wb_ack, - input wire [31:0] i_wb_data, - input wire i_wb_err, - // }}} - input wire i_interrupt, - // TX - // {{{ - output wire o_tx_stb, - output wire [7:0] o_tx_data, - input wire i_tx_busy, - // }}} - // CONSOLE - // {{{ - input wire i_console_stb, - input wire [6:0] i_console_data, - output wire o_console_busy, - // - output reg o_console_stb, - output reg [6:0] o_console_data, - // }}} - output wire o_dbg - // }}} - ); - - // Local declarations - // {{{ - wire soft_reset; - reg r_wdt_reset; - wire cmd_port_active; - - // RX byte - wire rx_valid; - wire [7:0] rx_data; - - // Incoming code word, once processed - wire in_stb, in_active; - wire [35:0] in_word; - - reg ps_full; - reg [7:0] ps_data; - wire wbu_tx_stb; - wire [7:0] wbu_tx_data; - - // Input FIFO - wire ififo_valid; - wire [35:0] ififo_codword; - - // Code word outputs from running the bus - wire exec_stb; - wire [35:0] exec_word; - - // Output FIFO - wire ofifo_rd; - wire [35:0] ofifo_codword; - wire ofifo_err, ofifo_empty_n; - - wire w_bus_busy, w_bus_reset; - reg [(LGWATCHDOG-1):0] r_wdt_timer; - wire ign_input_busy; - wire output_busy, out_active; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Forward console inputs to the console - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - initial o_console_stb = 1'b0; - always @(posedge i_clk) - o_console_stb <= (i_rx_stb)&&(i_rx_data[7] == 1'b0); - - always @(posedge i_clk) - o_console_data <= i_rx_data[6:0]; - // }}} - - // cmd_port_active - // {{{ - generate if (CMD_PORT_OFF_UNTIL_ACCESSED) - begin : GEN_DEACTIVATEPORT - - reg r_cmd_port_active; - - initial r_cmd_port_active = 1'b0; - always @(posedge i_clk) - if (i_rx_stb && i_rx_data[7]) - r_cmd_port_active <= 1'b1; - - assign cmd_port_active = r_cmd_port_active; - - end else begin : GEN_ALWAYSON - - assign cmd_port_active = 1'b1; - - end endgenerate - // }}} - - //////////////////////////////////////////////////////////////////////// - // - // Decode ASCII input requests into WB bus cycle requests - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - assign rx_valid = i_rx_stb && i_rx_data[7]; - assign rx_data = { 1'b0, i_rx_data[6:0] }; - - wbuinput - getinput( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_stb(rx_valid), .o_busy(ign_input_busy), - .i_byte(rx_data), - .o_soft_reset(soft_reset), - .o_stb(in_stb), .i_busy(1'b0), .o_codword(in_word), - .o_active(in_active) - // }}} - ); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The input FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - generate if (LGINPUT_FIFO < 2) - begin : NO_INPUT_FIFO - - assign ififo_valid = in_stb; - assign ififo_codword = in_word; - assign w_bus_reset = soft_reset; - - end else begin : INPUT_FIFO - - wire ififo_empty_n, ififo_err, ififo_rd; - - assign ififo_rd = (!w_bus_busy)&&(ififo_empty_n); - assign ififo_valid = (ififo_empty_n); - assign w_bus_reset = r_wdt_reset; - - wbufifo #( - // {{{ - .BW(36),.LGFLEN(LGINPUT_FIFO) - // }}} - ) padififo( - // {{{ - .i_clk(i_clk), .i_reset(w_bus_reset), - .i_wr(in_stb), .i_data(in_word), - .i_rd(ififo_rd), .o_data(ififo_codword), - .o_empty_n(ififo_empty_n), .o_err(ififo_err) - // }}} - ); - - // verilator lint_off UNUSED - wire gen_unused; - assign gen_unused = &{ 1'b0, ififo_err }; - // verilator lint_on UNUSED - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Run the bus - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Take requests in, Run the bus, send results out - // This only works if no requests come in while requests - // are pending. - wbuexec #( - // .LGFIFO(LGOUTPUT_FIFO) - .AW(AW) - ) runwb( - // {{{ - .i_clk(i_clk), .i_reset(r_wdt_reset), - // - .i_valid(ififo_valid), .i_codword(ififo_codword), - .o_busy(w_bus_busy), - // - .o_wb_cyc(o_wb_cyc), .o_wb_stb(o_wb_stb), .o_wb_we(o_wb_we), - .o_wb_addr(o_wb_addr), .o_wb_data(o_wb_data), - .i_wb_stall(i_wb_stall), .i_wb_ack(i_wb_ack), - .i_wb_data(i_wb_data), .i_wb_err(i_wb_err), - // - .o_stb(exec_stb), .o_codword(exec_word), .i_fifo_rd(ofifo_rd) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Output FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (LGOUTPUT_FIFO < 2) - begin : NO_OUTBOUND_FIFO - - assign ofifo_rd = exec_stb; - assign ofifo_codword = exec_word; - assign ofifo_err = 1'b0; - assign ofifo_empty_n = exec_stb; - - end else begin : GEN_OUTBOUND_FIFO - - assign ofifo_rd = ofifo_empty_n && !output_busy; - wbufifo #( - .BW(36), .LGFLEN(LGOUTPUT_FIFO) - ) busoutfifo ( - // {{{ - .i_clk(i_clk), .i_reset(r_wdt_reset), - .i_wr(exec_stb), .i_data(exec_word), - .i_rd(ofifo_rd), .o_data(ofifo_codword), - .o_empty_n(ofifo_empty_n), - .o_err(ofifo_err) - // }}} - ); - - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Encode bus outputs into a serial data stream - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wbuoutput - wroutput( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), .i_soft_reset(w_bus_reset), - .i_stb(ofifo_rd), .i_codword(ofifo_codword), - .o_busy(output_busy), - // - .i_wb_cyc(o_wb_cyc), .i_int(i_interrupt), - .i_bus_busy(exec_stb || ofifo_empty_n), - .o_stb(wbu_tx_stb), .o_char(wbu_tx_data), .i_tx_busy(ps_full), - .o_active(out_active) - // }}} - ); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Arbitrate between the two outputs, console and dbg bus - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - initial ps_full = 1'b0; - always @(posedge i_clk) - if (!ps_full) - begin - if (cmd_port_active && wbu_tx_stb) - begin - ps_full <= 1'b1; - ps_data <= { 1'b1, wbu_tx_data[6:0] }; - end else if (i_console_stb) - begin - ps_full <= 1'b1; - ps_data <= { 1'b0, i_console_data[6:0] }; - end - end else if (!i_tx_busy) - ps_full <= 1'b0; - - assign o_tx_stb = ps_full; - assign o_tx_data = ps_data; - assign o_console_busy = (wbu_tx_stb && cmd_port_active)||(ps_full); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Watchdog timer - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // Add in a watchdog timer to the bus - initial r_wdt_reset = 1'b1; - initial r_wdt_timer = 0; - always @(posedge i_clk) - if (i_reset || soft_reset) - begin - r_wdt_timer <= 0; - r_wdt_reset <= 1'b1; - end else if ((!o_wb_cyc)||(i_wb_ack)) - begin - // We're inactive, or the bus has responded: reset the timer - // {{{ - r_wdt_timer <= 0; - r_wdt_reset <= 1'b0; - // }}} - end else if (&r_wdt_timer) - begin // TIMEOUT!!! - // {{{ - r_wdt_reset <= 1'b1; - r_wdt_timer <= 0; - // }}} - end else begin // Tick-tock ... - r_wdt_timer <= r_wdt_timer+{{(LGWATCHDOG-1){1'b0}},1'b1}; - r_wdt_reset <= 1'b0; - end - // }}} - - assign o_dbg = w_bus_reset; - - // Make Verilator happy - // {{{ - // verilator lint_off UNUSED - wire unused; - assign unused = &{ 1'b0, ofifo_err, ign_input_busy, wbu_tx_data[7], - out_active, in_active }; - // verilator lint_on UNUSED - // }}} -endmodule - diff --git a/delete_later/rtl/wbubus/wbudecompress.v b/delete_later/rtl/wbubus/wbudecompress.v deleted file mode 100644 index 5cdb9f2..0000000 --- a/delete_later/rtl/wbubus/wbudecompress.v +++ /dev/null @@ -1,401 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbudecompress.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Compression via this interface is simply a lookup table. -// When writing, if requested, rather than writing a new 36-bit -// word, we may be asked to repeat a word that's been written recently. -// That's the goal of this routine: if given a word's (relative) address -// in the write stream, we use that address, else we expect a full 32-bit -// word to come in to be written. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbudecompress ( - // {{{ - input wire i_clk, i_reset, i_stb, - output wire o_busy, - input wire [35:0] i_word, - output reg o_stb, - input wire i_busy, - output reg [35:0] o_word, - output wire o_active - // }}} - ); - - // Local declarations - // {{{ - reg [7:0] wr_addr; - reg [31:0] compression_tbl [0:255]; - reg [35:0] r_word; - reg [7:0] cmd_addr; - reg [24:0] r_addr; - wire [31:0] w_addr; - reg [9:0] rd_len; - reg [31:0] cword; - reg [2:0] r_stb; - wire cmd_write_not_compressed; - - assign o_busy = (o_stb && i_busy) || (|r_stb); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Clock zero - // { o_stb, r_stb } = 0 - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - assign cmd_write_not_compressed = (i_word[35:33] == 3'h3); - - - // Clock one: { o_stb, r_stb } = 4'h1 when done - - // wr_addr - // {{{ - initial wr_addr = 8'h0; - always @(posedge i_clk) - if (i_reset) - wr_addr <= 8'h0; - else if ((i_stb && !o_busy)&&(cmd_write_not_compressed)) - wr_addr <= wr_addr + 8'h1; - // }}} - - // Write to compression_tbl - // {{{ - always @(posedge i_clk) - if (i_stb && !o_busy) - compression_tbl[wr_addr] <= { i_word[32:31], i_word[29:0] }; - // }}} - - // r_word - // {{{ - always @(posedge i_clk) - if (i_stb && !o_busy) - r_word <= i_word; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Clock two, calculate the table address ... 1 is the smallest address - // { o_stb, r_stb } = 4'h2 when done - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // cmd_addr - // {{{ - always @(posedge i_clk) - if (i_stb && !o_busy) - cmd_addr <= wr_addr - { i_word[32:31], i_word[29:24] }; - // }}} - - // r_addr - // {{{ - // Let's also calculate the address, in case this is a compressed - // address word - always @(posedge i_clk) - if (i_stb && !o_busy) - case(i_word[32:30]) - 3'b000: r_addr <= { 19'h0, i_word[29:24] }; - 3'b010: r_addr <= { 13'h0, i_word[29:18] }; - 3'b100: r_addr <= { 7'h0, i_word[29:12] }; - 3'b110: r_addr <= { 1'h0, i_word[29: 6] }; - 3'b001: r_addr <= { {(19){ i_word[29]}}, i_word[29:24] }; - 3'b011: r_addr <= { {(13){ i_word[29]}}, i_word[29:18] }; - 3'b101: r_addr <= { {( 7){ i_word[29]}}, i_word[29:12] }; - 3'b111: r_addr <= { {( 1){ i_word[29]}}, i_word[29: 6] }; - endcase - - assign w_addr = { {(7){r_addr[24]}}, r_addr }; - // }}} - - // rd_len - // {{{ - always @(posedge i_clk) - if (i_stb && !o_busy) - begin - if (!i_word[34]) - rd_len <= 10'h01 + { 6'h00, i_word[33:31] }; - else - rd_len <= 10'h09 + { 1'b0,i_word[33:31],i_word[29:24] }; - end - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Clock three, read the table value - // { o_stb, r_stb } = 4'h4 when done - // Maintaining ... - // r_word (clock 1) - // r_addr, rd_len (clock 2) - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - always @(posedge i_clk) - cword <= compression_tbl[cmd_addr]; - - // r_stb - // {{{ - // Pipeline the strobe signal to create an output strobe, 3 clocks later - initial r_stb = 0; - always @(posedge i_clk) - if (i_reset) - r_stb <= 0; - else - r_stb <= { r_stb[1:0], i_stb && !o_busy }; - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Clock four, now that the table value is valid, let's set our output - // word. - // { o_stb, r_stb } = 4'h8 when done - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // o_stb - // {{{ - initial o_stb = 0; - always @(posedge i_clk) - if (i_reset) - o_stb <= 0; - else if (!o_stb || !i_busy) - o_stb <= r_stb[2]; - // }}} - - // o_word - // {{{ - // Maintaining ... - // r_word (clock 1) - // r_addr, rd_len (clock 2) - // cword (clock 3) - // Any/all of these can be pipelined for faster operation - // However, speed is really limited by the speed of the I/O port. At - // it's fastest, it's 1 bit per clock, 48 clocks per codeword therefore, - // thus ... things will hold still for much longer than just 5 clocks. - always @(posedge i_clk) - if (!o_stb || !i_busy) - begin - if (r_word[35:30] == 6'b101110) - o_word <= r_word; - else casez(r_word[35:30]) - // Set address from something compressed ... unsigned - 6'b001??0: o_word <= { 4'h0, w_addr[31:0] }; - // Set a new address as a signed offset from the last (set) one - // (The last address is kept further down the chain, - // we just mark here that the address is to be set - // relative to it, and by how much.) - 6'b001??1: o_word <= { 3'h1, w_addr[31:30], 1'b1, w_addr[29:0]}; - // Write a value to the bus, with the value given from our - // codeword table - 6'b010???: o_word <= - { 3'h3, cword[31:30], r_word[30], cword[29:0] }; - // Read, highly compressed length (1 word) - 6'b1?????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len }; - // Read, two word (3+9 bits) length ... same encoding - // 6'b1?????: o_word <= { 5'b11000, r_word[30], 20'h00, rd_len }; - default: o_word <= r_word; - endcase - end - // }}} - - assign o_active = o_stb || (|r_stb); - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - // always @(*) - // if (!f_past_valid) - // assume(i_reset); - - always @(*) - if (|r_stb) - assert(!o_stb); - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assume(!i_stb); - else if ($past(i_stb && o_busy)) - begin - assume(i_stb); - assume($stable(i_word)); - end - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assert(!o_stb); - else if ($past(o_stb && i_busy)) - begin - assert(o_stb); - assert($stable(o_word)); - end - -`ifdef VERIFIC - assert property (@(posedge i_clk) - disable iff (i_reset) - i_stb && !o_busy |=> r_stb[0] ##1 r_stb[1] ##1 r_stb[2] ##1 o_stb); - - // - // Without changing things, I would note that any time o_stb is valid, - // the codeword has been known for a full clock. Hence, we could - // trim a clock off of the whole calculation. - assert property (@(posedge i_clk) - disable iff (i_reset) - o_stb |-> $stable(o_word)); - - // Uncompressed - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b101110) - |=> (!o_stb) [*3] - ##1 (o_stb) && $stable(o_word) && o_word == $past(i_word, 4)); - - // Address (compressed) - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b001000) - |=> ##3 (o_stb)&&(o_word == { 4'h0, 26'h0, $past(i_word[29:24], 4)})); - - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b001010) - |=> ##3 (o_stb)&&(o_word == { 4'h0, 20'h0, $past(i_word[29:18], 4)})); - - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b001100) - |=> ##3 (o_stb)&&(o_word == { 4'h0, 12'h0, $past(i_word[29:12], 4)})); - - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b001110) - |=> ##3 (o_stb)&&(o_word == { 4'h0, 6'h0, $past(i_word[29:6], 4)})); - - // Address (compressed, offset) - // initial $warn("Addresses not checked\n") - // 6'b001??1: o_word <= { 3'h1, w_addr[31:30], 1'b1, w_addr[29:0]}; - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b001001) - |=> ##3 (o_stb)&&(o_word == { 3'h1, - $past({ - {(2){i_word[29]}}, 1'b1, - {(24){i_word[29]}}, i_word[29:24]}, 4)})); - - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b001011) - |=> ##3 (o_stb)&&(o_word == { 3'h1, - $past({ - {(2){i_word[29]}}, 1'b1, - {(18){i_word[29]}}, i_word[29:18]}, 4)})); - - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b001101) - |=> ##3 (o_stb)&&(o_word == { 3'h1, - $past({ - {(2){i_word[29]}}, 1'b1, - {(12){i_word[29]}}, i_word[29:12]}, 4)})); - - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:30] == 6'b001111) - |=> ##3 (o_stb)&&(o_word == { 3'h1, - $past({ - {(2){i_word[29]}}, 1'b1, - {(6){i_word[29]}}, i_word[29:6]}, 4)})); - - - // Write from codeword table - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:33] == 3'b010) - |=> ##3 - (cword == compression_tbl[cmd_addr]) - && (o_word == { 3'h3, cword[31:30], r_word[30], cword[29:0] })); - - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:33] == 3'b010) - |=> !o_stb - ##1 !o_stb && (cmd_addr == (wr_addr - $past({i_word[32:31], i_word[29:24]},2))) - ##1 (!o_stb) && (cmd_addr == (wr_addr - $past({i_word[32:31], i_word[29:24]}, 3))) - && $stable(wr_addr)); - - // - // 1-word compressed reads - // - // Read, highly compressed length (1 word) - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && (i_word[35:34] == 2'b10) && (i_word[35:30] != 6'h2e)) - |=> ##3 (o_word[35:31] == 5'b11000) - &&(o_word[30] == $past(i_word[30],4)) - &&(o_word[29:0] == $past(i_word[33:31],4)+1)); - - // - // 2-word compressed reads - // - // Read, highly compressed length (1 word) - assert property (@(posedge i_clk) - disable iff (i_reset) - (i_stb && !o_busy && i_word[35:34] == 2'b11) - |=> ##3 (o_word[35:31] == 5'b11000) - &&(o_word[30] == $past(i_word[30],4)) - &&(o_word[29:0] == $past({i_word[33:31], i_word[29:24]},4)+9)); -`else - initial begin - // This design *requires* verific to verify - $stop(); - end - -`endif -`endif -// }}} -endmodule - diff --git a/delete_later/rtl/wbubus/wbudeword.v b/delete_later/rtl/wbubus/wbudeword.v deleted file mode 100644 index dc6739c..0000000 --- a/delete_later/rtl/wbubus/wbudeword.v +++ /dev/null @@ -1,413 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbudeword.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Once a word has come from the bus, undergone compression, had -// idle cycles and interrupts placed in it, this routine converts -// that word form a 36-bit single word into a series of 6-bit words -// that can head to the output routine. Hence, it 'deword's the value: -// unencoding the 36-bit word encoding. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbudeword ( - // {{{ - input wire i_clk, i_reset, i_stb, - input wire [35:0] i_word, - input wire i_tx_busy, - output reg o_stb, - output reg [6:0] o_nl_hexbits, - output wire o_busy, - output wire o_active - // }}} - ); - - // Local declarations - // {{{ - wire [2:0] w_len; - reg [2:0] r_len; - reg [29:0] r_word; - // }}} - - // r_word, o_nl_hexbits - // {{{ - initial o_nl_hexbits = 7'h40; - always @(posedge i_clk) - if (i_stb && !o_busy) // Only accept when not busy - begin - r_word <= i_word[29:0]; - o_nl_hexbits <= { 1'b0, i_word[35:30] }; // No newline ... yet - end else if (!i_tx_busy) - begin - if (r_len > 1) - begin - o_nl_hexbits <= { 1'b0, r_word[29:24] }; - r_word[29:6] <= r_word[23:0]; - end else if (!o_nl_hexbits[6]) - begin - // Place a 7'h40 between every pair of words - o_nl_hexbits <= 7'h40; - end - end - // }}} - - // o_stb - // {{{ - initial o_stb = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_stb <= 1'b0; - else if (i_stb && !o_busy) - o_stb <= 1'b1; - else if (r_len == 0 && !i_tx_busy) - o_stb <= 1'b0; - // }}} - - // r_len - // {{{ - assign w_len = (i_word[35:33]==3'b000)? 3'b001 - : (i_word[35:32]==4'h2)? 3'b110 - : (i_word[35:32]==4'h3)? (3'b010+{1'b0,i_word[31:30]}) - : (i_word[35:34]==2'b01)? 3'b010 - : (i_word[35:34]==2'b10)? 3'b001 - : 3'b110; - - initial r_len = 0; - always @(posedge i_clk) - if (i_reset) - r_len <= 0; - else if (i_stb && !o_busy) - r_len <= w_len; - else if (!i_tx_busy && (r_len > 0)) - r_len <= r_len - 1; - // }}} - - assign o_busy = o_stb; - assign o_active = i_stb || o_stb; -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg [35:0] fvword; - reg [6:0] six_seq; - reg [5:0] five_seq; - reg [4:0] four_seq; - reg [3:0] three_seq; - reg [2:0] two_seq; - reg [1:0] one_seq; - - always @(*) - assert(o_busy == o_stb); - always @(posedge i_clk) - if (!o_busy) - fvword <= i_word; - - initial six_seq = 0; - always @(posedge i_clk) - if (i_reset) - six_seq <= 0; - else if (i_stb && !o_busy && w_len == 3'b110) - six_seq <= 1; - else if (!i_tx_busy) - six_seq <= six_seq << 1; - - always @(*) - case(six_seq) - 0: begin end // This is the idle state, no assertions required - 7'b000_0001: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[35:30] }); - assert(r_len == 3'b110); - assert(r_word == fvword[29:0]); - assert(o_busy); - end - 7'b000_0010: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[29:24] }); - assert(r_len == 3'b101); - assert(r_word == { fvword[23:0], fvword[5:0] }); - assert(o_busy); - end - 7'b000_0100: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[23:18] }); - assert(r_len == 3'b100); - assert(r_word == { fvword[17:0], {(2){fvword[5:0]}} }); - assert(o_busy); - end - 7'b000_1000: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[17:12] }); - assert(r_len == 3'b011); - assert(r_word == { fvword[11:0], {(3){fvword[5:0]}} }); - assert(o_busy); - end - 7'b001_0000: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[11:6] }); - assert(r_len == 3'b010); - assert(r_word == { fvword[5:0], {(4){fvword[5:0]}} }); - assert(o_busy); - end - 7'b010_0000: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[5:0] }); - assert(r_len == 3'b001); - assert(o_busy); - end - 7'b100_0000: begin - assert(o_stb); - assert(o_nl_hexbits == 7'h40); - assert(r_len == 3'b000); - assert(o_busy); - end - default: assert(0); - endcase - - //////////////////////////////////////////////////////////////////////// - - initial five_seq = 0; - always @(posedge i_clk) - if (i_reset) - five_seq <= 0; - else if (i_stb && !o_busy && w_len == 3'b101) - five_seq <= 1; - else if (!i_tx_busy) - five_seq <= five_seq << 1; - - always @(*) - case(five_seq) - 0: begin end // This is the idle state, no assertions required - 6'b00_0001: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[35:30] }); - assert(r_len == 3'b101); - assert(r_word == fvword[29:0]); - assert(o_busy); - end - 6'b00_0010: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[29:24] }); - assert(r_len == 3'b100); - assert(r_word == { fvword[23:0], fvword[5:0] }); - assert(o_busy); - end - 6'b00_0100: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[23:18] }); - assert(r_len == 3'b011); - assert(r_word == { fvword[17:0], {(2){fvword[5:0]}} }); - assert(o_busy); - end - 6'b00_1000: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[17:12] }); - assert(r_len == 3'b010); - assert(r_word == { fvword[11:0], {(3){fvword[5:0]}} }); - assert(o_busy); - end - 6'b01_0000: begin - assert(o_stb); - assert(o_nl_hexbits == { 1'b0, fvword[11:6] }); - assert(r_len == 3'b001); - assert(r_word == { fvword[5:0], {(4){fvword[5:0]}} }); - assert(o_busy); - end - 6'b10_0000: begin - assert(o_stb); - assert(o_nl_hexbits == 7'h40); - assert(r_len == 3'b000); - assert(o_busy); - end - default: assert(0); - endcase - - //////////////////////////////////////////////////////////////////////// - - initial four_seq = 0; - always @(posedge i_clk) - if (i_reset) - four_seq <= 0; - else if (i_stb && !o_busy && w_len == 3'b100) - four_seq <= 1; - else if (!i_tx_busy) - four_seq <= four_seq << 1; - - always @(*) - case(four_seq) - 0: begin end // This is the idle state, no assertions required - 5'b0_0001: begin - assert(o_nl_hexbits == { 1'b0, fvword[35:30] }); - assert(r_len == 3'b100); - assert(r_word == fvword[29:0]); - assert(o_busy && o_stb); - end - 5'b0_0010: begin - assert(o_nl_hexbits == { 1'b0, fvword[29:24] }); - assert(r_len == 3'b011); - assert(r_word == { fvword[23:0], fvword[5:0] }); - assert(o_busy && o_stb); - end - 5'b0_0100: begin - assert(o_nl_hexbits == { 1'b0, fvword[23:18] }); - assert(r_len == 3'b010); - assert(r_word == { fvword[17:0], {(2){fvword[5:0]}} }); - assert(o_busy && o_stb); - end - 5'b0_1000: begin - assert(o_nl_hexbits == { 1'b0, fvword[17:12] }); - assert(r_len == 3'b001); - assert(r_word == { fvword[11:0], {(3){fvword[5:0]}} }); - assert(o_busy && o_stb); - end - 5'b1_0000: begin - assert(o_nl_hexbits == 7'h40); - assert(r_len == 3'b000); - assert(o_busy && o_stb); - end - default: assert(0); - endcase - - //////////////////////////////////////////////////////////////////////// - - initial three_seq = 0; - always @(posedge i_clk) - if (i_reset) - three_seq <= 0; - else if (i_stb && !o_busy && w_len == 3'b011) - three_seq <= 1; - else if (!i_tx_busy) - three_seq <= three_seq << 1; - - always @(*) - case(three_seq) - 0: begin end // This is the idle state, no assertions required - 4'b0001: begin - assert(o_nl_hexbits == { 1'b0, fvword[35:30] }); - assert(r_len == 3'b011); - assert(r_word == fvword[29:0]); - assert(o_busy && o_stb); - end - 4'b0010: begin - assert(o_nl_hexbits == { 1'b0, fvword[29:24] }); - assert(r_len == 3'b010); - assert(r_word == { fvword[23:0], fvword[5:0] }); - assert(o_busy && o_stb); - end - 4'b0100: begin - assert(o_nl_hexbits == { 1'b0, fvword[23:18] }); - assert(r_len == 3'b001); - assert(r_word == { fvword[17:0], {(2){fvword[5:0]}} }); - assert(o_busy && o_stb); - end - 4'b1000: begin - assert(o_nl_hexbits == 7'h40); - assert(r_len == 3'b000); - assert(o_busy && o_stb); - end - default: assert(0); - endcase - - //////////////////////////////////////////////////////////////////////// - - initial two_seq = 0; - always @(posedge i_clk) - if (i_reset) - two_seq <= 0; - else if (i_stb && !o_busy && w_len == 3'b010) - two_seq <= 1; - else if (!i_tx_busy) - two_seq <= two_seq << 1; - - always @(*) - case(two_seq) - 0: begin end // This is the idle state, no assertions required - 3'b001: begin - assert(o_nl_hexbits == { 1'b0, fvword[35:30] }); - assert(r_len == 3'b010); - assert(r_word == fvword[29:0]); - assert(o_busy && o_stb); - end - 3'b010: begin - assert(o_nl_hexbits == { 1'b0, fvword[29:24] }); - assert(r_len == 3'b001); - assert(r_word == { fvword[23:0], fvword[5:0] }); - assert(o_busy && o_stb); - end - 3'b100: begin - assert(o_nl_hexbits == 7'h40); - assert(r_len == 3'b000); - assert(o_busy && o_stb); - end - default: assert(0); - endcase - - - //////////////////////////////////////////////////////////////////////// - - initial one_seq = 0; - always @(posedge i_clk) - if (i_reset) - one_seq <= 0; - else if (i_stb && !o_busy && w_len == 3'b001) - one_seq <= 1; - else if (!i_tx_busy) - one_seq <= one_seq << 1; - - always @(*) - case(one_seq) - 2'b00: begin end // This is the idle state, no assertions required - 2'b01: begin - assert(o_nl_hexbits == { 1'b0, fvword[35:30] }); - assert(r_len == 3'b001); - assert(o_busy && o_stb); - end - 2'b10: begin - assert(o_nl_hexbits == 7'h40); - assert(r_len == 3'b000); - assert(o_busy && o_stb); - end - default: assert(0); - endcase - - //////////////////////////////////////////////////////////////////////// - always @(*) - assert(o_busy == (|{ six_seq, five_seq, four_seq, three_seq, two_seq, one_seq })); - -`endif -// }}} -endmodule - diff --git a/delete_later/rtl/wbubus/wbuexec.v b/delete_later/rtl/wbubus/wbuexec.v deleted file mode 100644 index 29ad8ae..0000000 --- a/delete_later/rtl/wbubus/wbuexec.v +++ /dev/null @@ -1,1048 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbuexec.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This is the part of the USB-JTAG to wishbone conversion that -// actually conducts a wishbone transaction. Transactions are -// requested via codewords that come in, and the results recorded on -// codewords that are sent out. Compression and/or decompression, coding -// etc. all take place external to this routine. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbuexec #( - parameter [0:0] OPT_COUNT_FIFO = 1'b0, - parameter LGFIFO = 4, - parameter AW = 32, DW = 32 - ) ( - // {{{ - input wire i_clk, i_reset, - // The command inputs - // {{{ - input wire i_valid, - input wire [35:0] i_codword, - output wire o_busy, - // }}} - // Wishbone outputs - // {{{ - output reg o_wb_cyc, - output reg o_wb_stb, - output reg o_wb_we, - output wire [AW-1:0] o_wb_addr, - output reg [DW-1:0] o_wb_data, - // }}} - // Wishbone inputs - // {{{ - input wire i_wb_stall, i_wb_ack, - input wire [DW-1:0] i_wb_data, - input wire i_wb_err, - // }}} - // And our codeword outputs - // {{{ - output reg o_stb, - output reg [35:0] o_codword, - // }}} - input wire i_fifo_rd - // }}} - ); - - // Local declarations - // {{{ - // localparam [5:0] END_OF_WRITE = 6'h2e; - localparam [1:0] WB_IDLE = 2'b00, - WB_READ_REQUEST = 2'b01, - WB_WRITE_REQUEST = 2'b10, - // WB_WAIT_ON_NEXT_WRITE = 3'b011, - WB_FLUSH_WRITE_REQUESTS = 2'b11; - localparam [1:0] WRITE_PREFIX = 2'b01; - - wire [31:0] w_cod_data; - -// wire w_accept, w_eow, w_newwr, w_new_err; -// // wire w_newad, w_newrd; -// assign w_accept = (i_valid)&&(!o_busy); -// // assign w_newad = (w_accept)&&(i_codword[35:34] == 2'b00); -// assign w_newwr = (w_accept)&&(i_codword[35:34] == WRITE_PREFIX); -// assign w_eow = (w_accept)&&(i_codword[35:30] == END_OF_WRITE); -// // assign w_newrd = (w_accept)&&(i_codword[35:34] == 2'b11); -// assign w_new_err = ((w_accept) -// &&(i_codword[35:33] != 3'h3) -// &&(i_codword[35:30] != END_OF_WRITE)); - - reg [1:0] wb_state; - reg [9:0] r_acks_needed, r_len; - reg r_inc, r_new_addr, last_read_request, last_ack, - zero_acks, r_busy; - reg [31:0] wide_addr; - - assign w_cod_data={ i_codword[32:31], i_codword[29:0] }; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Count the number of items in the FIFO - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wire [LGFIFO:0] fifo_space_available; - wire space_available; - - generate if (OPT_COUNT_FIFO) - begin : GEN_FIFO_SPACE - // {{{ - reg [LGFIFO:0] r_fifo_space_available; - reg r_space_available; - wire [LGFIFO:0] wb_space_needed, idl_space_needed; - - initial r_fifo_space_available = (1< 1) ? 1:0); - // Verilator lint_on WIDTH - - assign idl_space_needed = (i_valid ? 1:0) + (r_new_addr ? 1:0) - + (o_stb ? 1:0); - - initial r_space_available = 1'b1; - always @(posedge i_clk) - if (i_reset) - r_space_available <= 1'b1; - else if (o_wb_cyc) - r_space_available <= (r_fifo_space_available - > wb_space_needed); - else - r_space_available <= (r_fifo_space_available > idl_space_needed); - - assign fifo_space_available = r_fifo_space_available; - assign space_available = r_space_available; - - // Verilator lint_off UNUSED - wire unused_count; - assign unused_count = &{ 1'b0, i_fifo_rd, fifo_space_available }; - // Verilator lint_on UNUSED - // }}} - end else begin : NO_FIFO - // {{{ - assign fifo_space_available = 0; - assign space_available = 1'b1; - - // Verilator lint_off UNUSED - wire unused_count; - assign unused_count = &{ 1'b0, i_fifo_rd, fifo_space_available }; - // Verilator lint_on UNUSED - // }}} - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Issue bus requests - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // CYC, STB, wb_state and o_busy - // {{{ - initial wb_state = WB_IDLE; - initial o_wb_cyc = 1'b0; - initial o_wb_stb = 1'b0; - initial r_busy = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - // {{{ - wb_state <= WB_IDLE; - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - r_busy <= 1'b0; - // }}} - end else case(wb_state) - WB_IDLE: begin - // {{{ - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - r_busy <= 1'b0; - - // The new instruction. The following - // don't matter if we're not running, - // so set them any time in this state, - // and if we move then they'll still be - // set right. - // - // - // The output data is a don't care, unless we are - // starting a write. Hence, let's always set it as - // though we were about to start a write. - // - // o_wb_data <= w_cod_data; - // - if (i_valid && !o_busy) - begin - // Default is not to send any codewords - // Do we need to broadcast a new address? - // - casez(i_codword[35:32]) - 4'b0000: begin end // Set a new (arbitrary) address - 4'b001?: begin end // Set a new relative address - 4'b01??: begin // Start a write transaction, - // {{{ - // address must be already set - wb_state <= WB_WRITE_REQUEST; - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - r_busy <= 1'b1; - end - // }}} - 4'b11??: begin // Start a vector read - // {{{ - wb_state <= WB_READ_REQUEST; - o_wb_cyc <= 1'b1; - o_wb_stb <= 1'b1; - r_busy <= 1'b1; - end - // }}} - default: begin end - endcase - end end - // }}} - WB_READ_REQUEST: begin - // {{{ - o_wb_cyc <= 1'b1; - // o_wb_stb <= 1'b1; - - // if ((r_inc)&&(!i_wb_stall)) - // o_wb_addr <= o_wb_addr + 32'h001; - - - if (!o_wb_stb || !i_wb_stall) // Deal with the strobe line - begin // Strobe was accepted, busy should be '1' here - o_wb_stb <= space_available && !last_read_request; - end - - if (i_wb_ack && last_ack) - begin - wb_state <= WB_IDLE; - o_wb_cyc <= 1'b0; - r_busy <= 1'b0; - end - - if (i_wb_err) - begin - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - wb_state <= WB_IDLE; - r_busy <= 1'b0; - end end - // }}} - WB_WRITE_REQUEST: begin - // {{{ - o_wb_cyc <= 1'b1; - r_busy <= 1'b1; - - if (!i_wb_stall) - o_wb_stb <= 1'b0; - - if (!o_wb_stb || !i_wb_stall) - begin - if (i_valid && i_codword[35:34] == WRITE_PREFIX) - begin - if (!o_busy) - begin - o_wb_stb <= 1'b1; - r_busy <= 1'b1; - end else - r_busy <= 1'b0; - end else if ((!o_wb_stb && zero_acks) - || (i_wb_ack && last_ack)) - begin - o_wb_cyc <= 1'b0; - r_busy <= 1'b0; - wb_state <= WB_IDLE; - end - end - - if (i_wb_err) // Bus returns an error - begin - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - wb_state <= WB_FLUSH_WRITE_REQUESTS; - r_busy <= 1'b1; - end end - // }}} - WB_FLUSH_WRITE_REQUESTS: begin - // {{{ - // We come in here after an error within a write - // We need to wait until the command cycle finishes - // issuing all its write commands before we can go back - // to idle. - // - // In the off chance that we are in here in error, or - // out of sync, we'll transition to WB_IDLE and just - // issue a second error token. - - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - - r_busy <= 1'b1; - if (i_valid && i_codword[35:34] != WRITE_PREFIX) - begin - wb_state <= WB_IDLE; - r_busy <= 1'b0; - end end - // }}} - default: begin - // {{{ - wb_state <= WB_IDLE; - o_wb_cyc <= 1'b0; - o_wb_stb <= 1'b0; - r_busy <= 1'b0; - end - // }}} - endcase - - assign o_busy = r_busy || !space_available; - // }}} - - always @(posedge i_clk) - if (!o_busy) - o_wb_data <= w_cod_data; - - always @(posedge i_clk) - if (wb_state == WB_IDLE) - // Will this be a write? - o_wb_we <= !i_codword[35]; - - // o_wb_addr - // {{{ - always @(posedge i_clk) - if (i_valid && !o_busy && i_codword[35:32] == 4'h0) - // Set a new absolute address - wide_addr <= i_codword[31:0]; //w_cod_data - else if (i_valid && !o_busy && i_codword[35:33] == 3'h1) - // Set a new relative address - wide_addr <= wide_addr // + w_cod_data; - + { i_codword[32:31], i_codword[29:0] }; - else if (o_wb_stb && !i_wb_stall && r_inc) - // Increment - wide_addr <= wide_addr + 1; - - assign o_wb_addr = wide_addr[AW-1:0]; - // }}} - - // r_new_addr - // {{{ - initial r_new_addr = 1'b1; - always @(posedge i_clk) - if (i_reset) - r_new_addr <= 1'b1; - else if (!o_wb_cyc && i_valid && !o_busy && i_codword[35:34] != 2'b10) - // && i_codword[35:33] == 3'b001) - r_new_addr <= (i_codword[35:32] == 4'h0) - || (i_codword[35:33] == 3'b001); - // }}} - - // r_acks_needed - // {{{ - initial r_acks_needed = 0; - always @(posedge i_clk) - if (i_reset || !o_wb_cyc || i_wb_err) - r_acks_needed <= 10'h00; // (i_codword[35])?i_codword[9:0]:10'h00; - else case ({o_wb_stb && !i_wb_stall, i_wb_ack }) - 2'b10: r_acks_needed <= r_acks_needed + 10'h01; - 2'b01: r_acks_needed <= r_acks_needed - 10'h01; - default: begin end - endcase - // }}} - - always @(posedge i_clk) - if (wb_state == WB_IDLE) - // Increment addresses? - r_inc <= i_codword[30]; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Receive and process bus returns - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // last_ack - // {{{ -// last_ack was ... -// always @(posedge i_clk) -// last_ack <= (!o_wb_stb)&&(r_acks_needed == 10'h01) -// ||(o_wb_stb)&&(r_acks_needed == 10'h00); - - always @(posedge i_clk) - if (!o_wb_cyc) - begin - last_ack <= 1; - if (i_valid && i_codword[35:34] == 2'b11) - last_ack <= (i_codword[9:0] <= 1); - end else if (o_wb_we) - last_ack <= ((o_wb_stb ? 1:0) + r_acks_needed - + ((i_valid && !o_busy && i_codword[35:34] == WRITE_PREFIX) ? 1:0) - <= 1 + (i_wb_ack ? 1:0)); - else - last_ack <= (r_len + r_acks_needed <= 1 + (i_wb_ack ? 1:0)); - // }}} - - // zero_acks - // {{{ - initial zero_acks = 1; - always @(posedge i_clk) - if (i_reset || !o_wb_cyc || i_wb_err) - zero_acks <= 1; - else case({ o_wb_stb && !i_wb_stall, i_wb_ack }) - 2'b10: zero_acks <= 1'b0; - 2'b01: zero_acks <= (r_acks_needed == 10'h01); - default: begin end - endcase - // }}} - - // r_len - // {{{ - initial r_len = 0; - always @(posedge i_clk) - if (i_reset) - r_len <= 0; - else if (!o_wb_cyc) - begin - r_len <= 0; - if (i_valid && !o_busy && i_codword[35:34] == 2'b11) - r_len <= i_codword[9:0]; - end else if (o_wb_cyc && i_wb_err) - r_len <= 0; - else if (o_wb_stb && !i_wb_stall &&(|r_len)) - r_len <= r_len - 10'h01; - // }}} - - // last_read_request - // {{{ - initial last_read_request = 1; - always @(posedge i_clk) - if (i_reset) - last_read_request <= 1; - else if (!o_wb_cyc) - last_read_request <= !i_valid || o_busy - || i_codword[35:34] != 2'b11 - || (i_codword[9:0] <= 10'h01); - // When there is one read request left, it will be the last one - // will be the last one - else if (i_wb_err) - last_read_request <= 1; - else if (o_wb_stb && !i_wb_stall && space_available) - last_read_request <= (r_len <= 2); - else if (o_wb_stb && i_wb_stall) - last_read_request <= (r_len <= 1); - else if (!o_wb_stb && !space_available) - last_read_request <= (r_len == 0); - else - last_read_request <= (r_len <= 1); -`ifdef FORMAL - always @(*) - if (!i_reset) - begin - if (r_len == 0) - assert(last_read_request); - else if (o_wb_stb) - assert(last_read_request == (r_len == 1)); - else - assert(last_read_request == (r_len == 0)); - end -`endif - // }}} - // }}} - //////////////////////////////////////////////////////////////////////// - // - // The outgoing codeword stream - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // o_stb, o_codword - initial o_stb = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - // Send a bus reset indication - o_stb <= 1'b1; - o_codword <= { 6'h3, i_wb_data[29:0] }; - end else if (!o_wb_cyc) - begin - // Send a new address confirmation at the beginning of any - // read - o_stb <= (i_valid && !o_busy && - (i_codword[35:34] == 2'b11) && r_new_addr); - o_codword <= { 4'h2, wide_addr }; - end else begin - // Otherwise, while the bus is active, we send either a - // bus error indication, read return, or write ack - o_stb <= (i_wb_err)||(i_wb_ack); - - o_codword <= { 3'h7, i_wb_data[31:30], r_inc, i_wb_data[29:0] }; - - if (i_wb_err) // Bus Error - o_codword[35:30] <= 6'h5; - else if (o_wb_we) // Write ack - o_codword[35:30] <= 6'h2; - else // Read data on ack - o_codword[35:33] <= 3'h7; - end - // }}} - - // Make Verilator happy - // {{{ - // Verilator lint_off UNUSED - // wire unused; - // assign unused = &{ 1'b0 }; - // Verilator lint_on UNUSED - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - localparam F_LGDEPTH = 10; - reg f_past_valid; - wire [F_LGDEPTH-1:0] f_nreqs, f_nacks, f_outstanding; - reg [35:0] f_last_codword; - reg f_codword_rcvd; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin - // assert(!o_wb_cyc); - // assert(!o_wb_stb); - - if (!f_past_valid) - assert(!o_stb); - else - assert(o_stb); - assert(r_new_addr); - end - - //////////////////////////////////////////////////////////////////////// - // - // Input codeword assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assume(!i_valid); - else if ($past(i_valid && o_busy)) - begin - assume(i_valid); - assume($stable(i_codword)); - end - - always @(posedge i_clk) - if (i_valid && !o_busy) - f_last_codword <= i_codword; - - always @(posedge i_clk) - if (!i_reset && i_valid) - casez(i_codword[35:30]) - 6'b0000??: begin end // Normal address update - 6'b001??0: assume(0); // DISALLOWED: Address shorthand - 6'b001??1: begin end // Differential address update - 6'b010???: assume(0); // DISALLOWED: Write table - 6'b011???: begin end // Write with value - 6'b101110: begin end // End of write - 6'b1?????: begin // Vector read request - assume(i_codword[35:31] == 5'b11000); - assume(i_codword[29:10] == 20'h00); - assume(i_codword[9:0] > 0); - end - default: assume(0); - endcase - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Wishbone bus properties that we must meet - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - fwb_master #(.AW(AW), .DW(DW), .F_MAX_STALL(0), .F_MAX_ACK_DELAY(0), - .F_MAX_REQUESTS(1024), .F_LGDEPTH(F_LGDEPTH), - .F_OPT_RMW_BUS_OPTION(1), .F_OPT_DISCONTINUOUS(1)) - fwb(i_clk, i_reset, - o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, 4'hf, - i_wb_ack, i_wb_stall, i_wb_data, i_wb_err, - f_nreqs, f_nacks, f_outstanding); - // }}} - //////////////////////////////////////////////////////////////////////// - // - // - //////////////////////////////////////////////////////////////////////// - // - // - always @(*) - assert(zero_acks == (r_acks_needed == 0)); - - always @(*) - if (!OPT_COUNT_FIFO && (f_outstanding == 0)&&(!o_wb_we)) - assert(o_wb_stb || !o_wb_cyc); - - always @(*) - if (o_wb_stb && !o_wb_we) - assert(last_read_request == (r_len <= 8'h01)); - - always @(*) - case(wb_state) - WB_IDLE: begin - // {{{ - assert(!o_wb_cyc); - assert(r_len == 0); - assert(!r_busy); - end - // }}} - WB_READ_REQUEST: begin - // {{{ - // - // Read logic - // - assert(o_wb_cyc); - assert(!o_wb_we); - assert(f_last_codword[35:34] == 2'b11); - assert(r_len <= f_last_codword[9:0]); - if (o_wb_stb) - assert(last_read_request == (r_len == 1)); - assert(f_nreqs == f_last_codword[9:0] - r_len); - assert(f_nreqs <= f_last_codword[9:0] + (o_wb_stb ? 1:0)); - assert(r_acks_needed == f_outstanding); - assert(o_busy); - - assert(wb_state == WB_READ_REQUEST); - - assert(f_nacks <= f_nreqs); - assert(f_nacks < f_last_codword[9:0]); - - assert(r_inc == f_last_codword[30]); - assert(last_ack == (f_nacks >= (f_last_codword[9:0]-1))); - assert(r_busy); - - if (r_len == 0) - assert(!o_wb_stb); - assert(!r_new_addr); - end - // }}} - WB_WRITE_REQUEST: begin - // {{{ - assert(o_wb_cyc); - assert(o_wb_we); - assert(r_len == 0); - assert(!r_new_addr); - end - // }}} - WB_FLUSH_WRITE_REQUESTS: begin - // {{{ - assert(!o_wb_cyc); - assert(!o_wb_stb); - assert(o_wb_we); - assert(r_busy); - assert(r_len == 0); - assert(r_acks_needed == 0); - assert(!r_new_addr); - end - // }}} - endcase - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && !i_wb_err - && r_len > ((o_wb_stb && !i_wb_stall) ? 1:0) - && space_available)) - assert(o_wb_stb); - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && o_wb_cyc && !o_wb_we)) - begin - // - // Temporal read logic - // - if ($past(i_wb_ack)) - begin - assert(o_stb); - assert(o_codword == $past( - { 3'h7, i_wb_data[31:30], r_inc, - i_wb_data[29:0] })); - end else if ($past(i_wb_err)) - begin - assert(wb_state == WB_IDLE); - assert(!o_wb_cyc); - assert(o_stb); - assert(o_codword[35:30] == 6'h5); - end else - assert(!o_stb); - end - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && i_valid && !o_busy && i_codword[35:34] == 2'b11)) - begin - assert(o_wb_stb && !o_wb_we); - assert(r_len == $past(i_codword[9:0])); - assert(wb_state == WB_READ_REQUEST); - end - - always @(*) - if (o_wb_cyc && o_wb_we) - begin - - assert(f_last_codword[35:34] == WRITE_PREFIX); - - if (o_wb_stb) - begin - assert(o_busy); - assert(wb_state == WB_WRITE_REQUEST); - end - - assert(r_acks_needed == f_outstanding); - - assert(wb_state != WB_READ_REQUEST); - assert(last_ack == (f_outstanding + (o_wb_stb ? 1:0) <= 1)); - - assert(o_wb_data == { f_last_codword[32:31], f_last_codword[29:0] }); - end - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && o_wb_cyc && i_wb_err)) - assert(o_stb && o_codword[35:30] == 6'h5); - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && o_wb_cyc && o_wb_we)) - begin - if ($past(i_wb_ack)) - begin - assert(o_stb); - assert(o_codword[35:30] == 6'h2); - end - end - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && o_wb_cyc) && o_wb_cyc) - assert($stable(o_wb_we)); - - always @(*) - if ((f_last_codword[35:32] == 4'h0)||(f_last_codword[35:33] == 1)) - begin - // Address update - assert(!o_wb_cyc); - assert(!r_busy); - assert(r_new_addr); - if (f_codword_rcvd && f_last_codword[35:32] == 0) - assert(o_wb_addr == f_last_codword[31:0]); - end - - initial f_codword_rcvd = 0; - always @(posedge i_clk) - if (i_reset) - f_codword_rcvd <= 0; - else if (i_valid && !o_busy) - f_codword_rcvd <= 1; - - always @(*) - assert(o_wb_cyc == ((wb_state != WB_IDLE) - &&(wb_state != WB_FLUSH_WRITE_REQUESTS))); - - // Bus aborts on reset or bus error only - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset || i_wb_err)) - begin - if (f_nreqs != f_nacks) - assert(o_wb_cyc); - end - - always @(*) - if (wb_state == WB_IDLE) - assert(!r_busy); - - always @(posedge i_clk) - if (o_wb_cyc && !r_busy && wb_state == WB_WRITE_REQUEST) - assert(i_valid && i_codword[35:34] == WRITE_PREFIX); - - always @(posedge i_clk) - if (f_past_valid && $past(!i_reset && (!o_wb_cyc || !i_wb_err) - && i_valid&& !o_busy && i_codword[35:34] == WRITE_PREFIX)) - assert(o_wb_stb && o_wb_we); - - always @(*) - assert(wb_state <= WB_FLUSH_WRITE_REQUESTS); - - //////////////////////////////////////////////////////////////////////// - // - // Contract properties - // - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_COUNT_FIFO) - begin : F_COUNT_FIFO - // {{{ - wire [LGFIFO:0] fifo_fill; - - assign fifo_fill = (1<= (1< 0); - // }}} - end else begin : F_NO_FIFO - // {{{ - always @(*) - assume(!i_fifo_rd); - always @(*) - assert(space_available); - // }}} - end endgenerate - -`ifdef VERIFIC - // - // Address command - assert property (@(posedge i_clk) - disable iff (i_reset) - i_valid && !o_busy && i_codword[35:34] == 2'b00 - |-> wb_state == WB_IDLE - ##1 r_new_addr && (wb_state == WB_IDLE) && !r_busy [*0:$] - ##1 !r_new_addr && o_wb_cyc && (o_wb_we || - (o_stb && o_codword == { 4'h2, wide_addr }))); - - assert property (@(posedge i_clk) - disable iff (i_reset) - r_new_addr && i_valid && !o_busy && i_codword[35:34] == 2'b11 - |=> o_stb && o_codword == { 4'h2, o_wb_addr } - && o_wb_stb && !o_wb_we); - - assert property (@(posedge i_clk) - disable iff (i_reset) - r_new_addr && !o_wb_cyc |-> r_new_addr); - - // - // Write command - assert property (@(posedge i_clk) - !i_reset && i_valid && !o_busy && i_codword[35:34] == 2'b01 - && (wb_state != WB_FLUSH_WRITE_REQUESTS) - && (!i_wb_err || !o_wb_cyc) - |=> o_wb_stb && o_wb_we && o_wb_data == $past(w_cod_data[31:0]) - && wb_state == WB_WRITE_REQUEST - ); - - // Write return - assert property (@(posedge i_clk) - !i_reset && o_wb_cyc && o_wb_we && i_wb_ack - |=> o_stb && o_codword[35:30] == 6'h2); - - - // Return to idle from write - - // Stay in write unless there's a request - assert property (@(posedge i_clk) - !i_reset && (!o_wb_stb || !i_wb_stall) && !i_wb_err - && (wb_state == WB_WRITE_REQUEST) - && (f_outstanding + (o_wb_stb ? 1:0)== (i_wb_ack ? 1:0)) - && (!i_valid || i_codword[35:34] != WRITE_PREFIX) - |-> o_wb_cyc && o_busy && o_wb_we - ##1 !o_wb_cyc && !r_busy && wb_state == WB_IDLE); - - // On a further write request, send that request - assert property (@(posedge i_clk) - !i_reset && (!o_wb_stb || !i_wb_stall) - && (wb_state == WB_WRITE_REQUEST) - && i_valid && o_busy - && (i_codword[35:34] == 2'b01) - && (!i_wb_err) - |=> o_wb_cyc && !r_busy && wb_state == WB_WRITE_REQUEST); - - // On a request for anything else, leave the write request state - assert property (@(posedge i_clk) - !i_reset && (!o_wb_stb || !i_wb_stall) - && (wb_state == WB_WRITE_REQUEST) - && i_valid && !o_wb_stb && o_busy && zero_acks - && (i_codword[35:34] != 2'b01) - |=> !o_wb_cyc && !r_busy && wb_state == WB_IDLE); - - - // - // Read command - assert property (@(posedge i_clk) - !i_reset && i_valid && !o_busy && i_codword[35:34] == 2'b11 - |=> o_wb_stb && !o_wb_we - && wb_state == WB_READ_REQUEST - && r_len == $past(i_codword[9:0])); - - assert property (@(posedge i_clk) - disable iff (i_reset || (o_wb_cyc && i_wb_err)) - o_wb_stb && !o_wb_we - |-> (r_len > 0)&&(wb_state == WB_READ_REQUEST) - ##1 (o_wb_cyc && !o_wb_we && r_len > 0) [*0:$] - ##1 (!o_wb_stb && !o_wb_we && r_len == 0)); - - assert property (@(posedge i_clk) - disable iff (i_reset) - o_wb_stb && !o_wb_we && !i_wb_stall && !i_wb_err - |=> (r_len == $past(r_len) - 1)); - - // Read return - assert property (@(posedge i_clk) - disable iff (i_reset) - o_wb_cyc && !o_wb_we && i_wb_ack - |=> o_stb && o_codword == { 3'h7, $past(i_wb_data[31:30]), - r_inc, $past(i_wb_data[29:0]) }); - - // Bus error returns - assert property (@(posedge i_clk) - !i_reset && o_wb_cyc && i_wb_err - |=> !o_wb_cyc && o_stb && o_codword[35:30] == 6'h5); - -`else - initial begin - $display("This design requires Verific to verify\n"); - $stop(); - end -`endif - //////////////////////////////////////////////////////////////////////// - // - // Cover properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - reg [4:0] f_count_writes, f_count_reads, - f_read_bursts; - - initial r_inc = 0; - - initial f_count_writes = 0; - initial f_read_bursts = 0; - always @(posedge i_clk) - if (i_reset || r_new_addr || (o_wb_cyc && i_wb_err) - || (i_valid && (i_codword[35:34] == 2'b11) - && (i_codword[9:0] < 10'h3))) - f_read_bursts <= 0; - else if (i_valid && !o_busy && (i_codword[35:34] == 2'b11)) - f_read_bursts <= f_read_bursts + 1; - - initial f_count_reads = 0; - always @(posedge i_clk) - if (i_reset || r_new_addr || (o_wb_cyc && i_wb_err)) - f_count_reads <= 0; - else if (o_wb_cyc && !o_wb_we && i_wb_ack) - f_count_reads <= f_count_reads + 1; - - initial f_count_writes = 0; - always @(posedge i_clk) - if (i_reset || r_new_addr || (o_wb_cyc && i_wb_err)) - f_count_writes <= 0; - else if (o_wb_cyc && o_wb_we && i_wb_ack) - f_count_writes <= f_count_writes + 1; - - always @(*) - cover(!i_reset && (f_outstanding > 10) && o_wb_we); - - always @(*) - if (!i_reset) - begin - cover((f_read_bursts > 3)&&(f_count_reads > 16) - && (wb_state == WB_IDLE) - && r_inc && (o_wb_addr == 32'hdad1beef)); - cover((f_count_writes > 10)&&(r_inc) - && (o_wb_addr == 32'hdeadbeef) - && (wb_state == WB_IDLE)); - cover((f_count_writes > 10)&&(!r_inc) - && (o_wb_addr == 32'hdeadbeef) - && (wb_state == WB_IDLE)); - end - // }}} - //////////////////////////////////////////////////////////////////////// - // - // "Careless" Assumptions - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // }}} -`endif // FORMAL -// }}} -endmodule diff --git a/delete_later/rtl/wbubus/wbufifo.v b/delete_later/rtl/wbubus/wbufifo.v deleted file mode 100644 index afd1454..0000000 --- a/delete_later/rtl/wbubus/wbufifo.v +++ /dev/null @@ -1,354 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbufifo.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This was once a FIFO for a UART ... but now it works as a -// synchronous FIFO for JTAG-wishbone conversion 36-bit codewords. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbufifo #( - parameter BW=66, LGFLEN=10 - ) ( - // {{{ - input wire i_clk, i_reset, - input wire i_wr, - input wire [(BW-1):0] i_data, - input wire i_rd, - output reg [(BW-1):0] o_data, - output reg o_empty_n, - output wire o_err - // }}} - ); - - // Local declarations - // {{{ - localparam FLEN=(1< 1) - assert(o_empty_n); - always @(*) - assert(will_underflow == (f_fifo_fill == 0)); - always @(*) - f_fifo_fill = r_wrptr - r_rdptr; - - always @(*) - assert(f_fifo_fill <= (1< 0); - if (fifo[f_first_addr[LGFLEN-1:0]] != f_first) - f_first_in_fifo = 0; - - if ((o_data == f_first)&&(r_rdptr == f_second_addr) - &&(o_empty_n)) - f_first_in_fifo = 1; - end - - always @(*) - begin - f_distance_to_second = (f_second_addr - r_rdptr); - f_second_in_fifo = (f_distance_to_second < f_fifo_fill) - &&(f_fifo_fill > 0); - if (fifo[f_second_addr[LGFLEN-1:0]] != f_second) - f_second_in_fifo = 0; - - if ((o_data == f_second)&&(r_rdptr == f_third_addr) - &&(o_empty_n)) - f_second_in_fifo = 1; - end - - initial f_state = 0; - always @(posedge i_clk) - if (i_reset || o_err) - f_state <= 0; - else case(f_state) - 2'b00: begin - if (w_write && r_wrptr == f_first_addr) - f_state <= 1; - end - 2'b01: begin - if (i_rd) - f_state <= 0; - else if (w_write && r_wrptr == f_second_addr) - f_state <= 2'b10; - end - 2'b10: begin - if (w_read && r_rdptr == f_second_addr) - f_state <= 2'b11; - end - 2'b11: begin - if (i_rd) - f_state <= 2'b00; - end - endcase - -// always @(*) -// if (!o_empty_n) -// assert(o_data == fifo[r_rdptr]); - - always @(*) - case(f_state) - 2'b00: begin end - 2'b01: begin - assert(f_first_in_fifo); - if (r_rdptr == f_second_addr) - assert(o_data == f_first && o_empty_n); - else - assert(r_empty_n); - assert(fifo[f_first_addr[LGFLEN-1:0]] == f_first - ||(r_rdptr == f_second_addr)); - end - 2'b10: begin - assert(f_first_in_fifo); - assert(o_empty_n); - assert(r_empty_n); - assert((fifo[f_first_addr[LGFLEN-1:0]] == f_first) - ||(o_data == f_first)); - if (r_rdptr == f_second_addr) - assert(o_data == f_first); - - assert(f_second_in_fifo); - assert(fifo[f_second_addr[LGFLEN-1:0]] == f_second); - // assert(o_data == f_first); - end - 2'b11: begin - assert(o_empty_n); - assert(r_rdptr == f_third_addr); - assert(f_second_in_fifo); - // assert(fifo[f_second_addr[LGFLEN-1:0]] == f_second); - assert(o_data == f_second); - end - endcase - - always @(posedge i_clk) - if (f_past_valid && i_wr && will_overflow && !i_rd) - assert(o_err); - - always @(posedge i_clk) - if (i_rd && !o_empty_n) - assert(o_err); - -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wbubus/wbuidleint.v b/delete_later/rtl/wbubus/wbuidleint.v deleted file mode 100644 index 52c6948..0000000 --- a/delete_later/rtl/wbubus/wbuidleint.v +++ /dev/null @@ -1,197 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbuidleint.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Creates an output for the interface, inserting idle words and -// words indicating an interrupt has taken place into the output -// stream. Henceforth, the output means more than just bus transaction -// results. It may mean there is no bus transaction result to report, -// or that an interrupt has taken place. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbuidleint( - // {{{ - input wire i_clk, i_reset, - // From the FIFO following the bus executor - input wire i_stb, - input wire [35:0] i_codword, - // From the rest of the board - input wire i_cyc, i_busy, i_int, - // To the next stage - output reg o_stb, - output reg [35:0] o_codword, - output reg o_busy, - // Is the next stage busy? - input wire i_tx_busy - // }}} - ); - - // Local declarations - // {{{ - localparam CW_INTERRUPT = { 6'h4, 30'h0000 }; // interrupt codeword - localparam CW_BUSBUSY = { 6'h1, 30'h0000 }; // bus busy, ow idle - localparam CW_IDLE = { 6'h0, 30'h0000 }; // idle codeword -`ifdef VERILATOR - localparam IDLEBITS = 22; -`else - localparam IDLEBITS = 31; -`endif - - reg int_request, int_sent; - wire idle_expired; - reg idle_state; - reg [IDLEBITS-1:0] idle_counter; - // }}} - - // int_request - // {{{ - initial int_request = 1'b0; - always @(posedge i_clk) - if (i_reset) - int_request <= 0; - else if (i_int) - int_request <= 1; - else if((o_stb)&&(!i_tx_busy)&&(o_codword[35:30]==CW_INTERRUPT[35:30])) - int_request <= 0; - // }}} - - // idle_counter - // {{{ - // Now, for the idle counter - initial idle_counter = 0; - always @(posedge i_clk) - if (i_reset||i_stb||o_stb||i_busy) - idle_counter <= 0; - else if (!idle_counter[IDLEBITS-1]) - idle_counter <= idle_counter + 1; - // }}} - - // idle_state - // {{{ - initial idle_state = 1'b0; - always @(posedge i_clk) - if (i_reset) - // We are now idle, and can rest - idle_state <= 1'b1; - else if ((o_stb)&&(!i_tx_busy)&&(o_codword[35:30]==CW_IDLE[35:30])) - // We are now idle, and can rest - idle_state <= 1'b1; - else if (!idle_counter[IDLEBITS-1]) - // We became active, and can rest no longer - idle_state <= 1'b0; - // }}} - - assign idle_expired = (!idle_state)&&(idle_counter[IDLEBITS-1]); - - // o_stb, o_codword - // {{{ - initial o_stb = 1'b0; - always @(posedge i_clk) - begin - if(!o_stb || !i_tx_busy) - begin - if (i_stb) - begin - // On a valid output, just send it out - // We'll open this strobe, even if the - // transmitter is busy, just 'cause we might - // otherwise lose it - o_stb <= 1'b1; - o_codword <= i_codword; - end else begin - // Our indicators take a clock to reset, hence - // we'll idle for one clock before sending - // either an interrupt or an idle indicator. - // The bus busy indicator is really only ever - // used to let us know that something's broken. - o_stb <= (!o_stb)&&((int_request&&!int_sent) - || idle_expired); - - if (int_request && !int_sent) - o_codword[35:30] <= CW_INTERRUPT[35:30]; - else begin - o_codword[35:30] <= CW_IDLE[35:30]; - if (i_cyc) - o_codword[35:30] <= CW_BUSBUSY[35:30]; - end - end - end - - if (i_reset) - o_stb <= 1'b0; - end - // }}} - - always @(*) - o_busy = o_stb; - - // int_sent - // {{{ - initial int_sent = 1'b0; - always @(posedge i_clk) - if (i_reset) - int_sent <= 1'b0; - else if ((int_request)&&((!o_stb)&&(!o_busy)&&(!i_stb))) - int_sent <= 1'b1; - else if (!i_int) - int_sent <= 1'b0; - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assert(!o_stb); - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset)) - begin - if ($past(o_stb && i_tx_busy)) - assert(o_stb && $stable(o_codword)); - - if ($past(i_stb && !o_busy)) - assert(o_stb && o_codword == $past(i_codword)); - end -`endif -// }}} -endmodule diff --git a/delete_later/rtl/wbubus/wbuinput.v b/delete_later/rtl/wbubus/wbuinput.v deleted file mode 100644 index 13d0c90..0000000 --- a/delete_later/rtl/wbubus/wbuinput.v +++ /dev/null @@ -1,137 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbuinput.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Coordinates the receiption of bytes, which are then translated -// into codewords describing postential bus transactions. This -// includes turning the human readable bytes into more compact bits, -// forming those bits into codewords, and decompressing any that reference -// addresses within a compression table. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbuinput #( - parameter OPT_COMPRESSION = 1'b1 - ) ( - // {{{ - input wire i_clk, i_reset, - i_stb, - output wire o_busy, - input wire [7:0] i_byte, - output wire o_soft_reset, - output wire o_stb, - input wire i_busy, - output wire [35:0] o_codword, - output wire o_active - // }}} - ); - - // Local declarations - // {{{ - wire hx_stb, hx_valid; - wire [5:0] hx_hexbits; - - wire cw_stb, cw_busy, cw_active; - wire [35:0] cw_word; - - wire cod_busy, cod_active; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Turn our human-readable characters to raw 6-bit words - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wbutohex - tobits( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_stb(i_stb), .o_busy(o_busy), .i_byte(i_byte), - .o_soft_reset(o_soft_reset), - .o_stb(hx_stb), .o_valid(hx_valid), .i_busy(cw_busy), - .o_hexbits(hx_hexbits) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Assemble the 6-bit words into 36-bit code words - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wbureadcw - formcw( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_stb(hx_stb), .o_busy(cw_busy), - .i_valid(hx_valid), .i_hexbits(hx_hexbits), - .o_stb(cw_stb), .i_busy(cod_busy), .o_codword(cw_word), - .o_active(cw_active) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // If using compression, uncompress the sent word - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_COMPRESSION) - begin : GEN_COMPRESSION - - wbudecompress - unpack( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - // - .i_stb(cw_stb), .o_busy(cod_busy), .i_word(cw_word), - .o_stb(o_stb), .i_busy(i_busy), .o_word(o_codword), - .o_active(cod_active) - // }}} - ); - - end else begin : NO_COMPRESSION - // {{{ - assign o_stb = cw_stb; - assign o_codword = cw_word; - assign cod_busy = i_busy; - // }}} - end endgenerate - // }}} - - assign o_active = i_stb || hx_stb || cw_active || cod_active; -endmodule diff --git a/delete_later/rtl/wbubus/wbuoutput.v b/delete_later/rtl/wbubus/wbuoutput.v deleted file mode 100644 index e0c611b..0000000 --- a/delete_later/rtl/wbubus/wbuoutput.v +++ /dev/null @@ -1,213 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbuoutput.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Converts 36-bit codewords into bytes to be placed on the serial -// output port. The codewords themselves are the results of bus -// transactions, which are then (hopefully) compressed within here and -// carefully arranged into "lines" for visual viewing (if necessary). -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbuoutput #( - parameter [0:0] OPT_COMPRESSION = 1'b1, - parameter [0:0] OPT_IDLES = 1'b1 - ) ( - // {{{ - input wire i_clk, i_reset, i_soft_reset, - input wire i_stb, - output wire o_busy, - input wire [35:0] i_codword, - // Not Idle indicators - input wire i_wb_cyc, i_int, i_bus_busy, - // Outputs to our UART transmitter - output wire o_stb, o_active, - output wire [7:0] o_char, - // - input wire i_tx_busy - // }}} - ); - - // Local declarations - // {{{ - wire dw_busy; - - wire cw_stb, cw_busy, cp_stb, dw_stb, ln_stb, ln_busy, - cp_busy, byte_busy; - wire cp_active, dw_active, ln_active; - wire [35:0] cw_codword, cp_word; - wire [6:0] dw_bits, ln_bits; - - reg r_active; - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Insert interrupt notifications and idle words - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - generate if (OPT_IDLES) - begin : GEN_IDLES - wbuidleint - buildcw( - // {{{ - .i_clk(i_clk), .i_reset(i_soft_reset), - .i_stb(i_stb), .i_codword(i_codword), - .i_cyc(i_wb_cyc), .i_busy(i_bus_busy), .i_int(i_int), - .o_stb(cw_stb), .o_codword(cw_codword), - .o_busy(cw_busy), .i_tx_busy(cp_stb && cp_busy) - // }}} - ); - - assign o_busy = cw_busy; - - end else begin : NO_IDLE_INSERTION - - assign cw_stb = i_stb; - assign cw_codword = i_codword; - assign o_busy = cp_busy; - assign cw_busy = cp_busy; - - // Verilator lint_off UNUSED - wire unused_idle; - assign unused_idle = &{ 1'b0, i_int }; - // Verilator lint_on UNUSED - end endgenerate - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Compression - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - // - // cw_busy & cw_stb, not cp_stb, but dw_busy - // - - generate if (OPT_COMPRESSION) - begin : GEN_COMPRESSION - - wbucompress - packit( - // {{{ - .i_clk(i_clk), .i_reset(i_soft_reset), - .i_stb(cw_stb), .i_codword(cw_codword), - .i_busy(dw_busy), .o_active(cp_active), - .o_stb(cp_stb), .o_cword(cp_word), .o_busy(cp_busy) - // }}} - ); - - end else begin : NO_COMPRESSION - - assign cp_stb = cw_stb; - assign cp_word = cw_codword; - assign cp_busy = dw_busy; - assign cp_active = cw_stb; - - end endgenerate - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Split the 36-bits words into a stream of 6 bit serial words - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wbudeword - deword( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_stb(cp_stb), .i_word(cp_word), .i_tx_busy(ln_busy), - .o_stb(dw_stb), .o_nl_hexbits(dw_bits), .o_busy(dw_busy), - .o_active(dw_active) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Remove line feeds, compacting things into 80-char lines - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wbucompactlines - linepacker( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_stb(dw_stb), .i_nl_hexbits(dw_bits), - .o_stb(ln_stb), .o_nl_hexbits(ln_bits), - .o_active(ln_active), - .i_bus_busy(i_wb_cyc||i_bus_busy||cw_busy), - .i_tx_busy(byte_busy), .o_busy(ln_busy) - // }}} - ); - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Convert the binary outputs to readable characters - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - wbusixchar - mkbytes( - // {{{ - .i_clk(i_clk), .i_reset(i_reset), - .i_stb(ln_stb), .i_bits(ln_bits), - .o_stb(o_stb), .o_char(o_char), .o_busy(byte_busy), - .i_busy(i_tx_busy) - // }}} - ); - - // }}} - - // Try to determine the last value: - // o_last = o_stb || !r_active - always @(posedge i_clk) - if (i_reset) - r_active <= 0; - else if (i_stb || dw_active || cp_active || cw_stb || cp_stb || dw_stb - || ln_active) - r_active <= 1; - else if (!i_tx_busy) - r_active <= 0; - - assign o_active = r_active || ln_stb; -endmodule diff --git a/delete_later/rtl/wbubus/wbureadcw.v b/delete_later/rtl/wbubus/wbureadcw.v deleted file mode 100644 index 1283c3e..0000000 --- a/delete_later/rtl/wbubus/wbureadcw.v +++ /dev/null @@ -1,335 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbureadcw.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Read bytes from a serial port (i.e. the jtagser) and translate -// those bytes into a 6-byte codeword. This codeword may specify -// a number of values to be read, the value to be written, or an address -// to read/write from, or perhaps the end of a write sequence. -// -// See the encoding documentation file for more information. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// -// Goal: single clock pipeline, 50 slices or less -// }}} -module wbureadcw #( - parameter OPT_SKIDBUFFER = 1'b0 - ) ( - // {{{ - input wire i_clk, i_reset, i_stb, - output wire o_busy, - input wire i_valid, - input wire [5:0] i_hexbits, - output reg o_stb, - input wire i_busy, - output reg [35:0] o_codword, - output wire o_active - // }}} - ); - - // Local declarations - // {{{ - // Timing: - // Clock 0: i_stb is high, i_valid is low - // Clock 1: shiftreg[5:0] is valid, cw_len is valid - // r_len = 1 - // Clock 2: o_stb = 1, for cw_len = 1; - // o_codword is 1-byte valid - // i_stb may go high again on this clock as well. - // Clock 3: o_stb = 0 (cw_len=1), - // cw_len = 0, - // r_len = 0 (unless i_stb) - // Ready for next word - reg [2:0] r_len, cw_len; - reg [1:0] lastcw; - - wire w_stb; - reg [35:0] shiftreg; - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // A quick skid buffer - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - wire skd_stb, skd_valid; - wire [5:0] skd_hexbits; - reg skd_busy; - - generate if (OPT_SKIDBUFFER) - begin : GEN_SKIDBUFFER - // {{{ - reg skd_full; - reg [6:0] skd_data, skd_result; - - initial skd_full = 1'b0; - always @(posedge i_clk) - if (i_reset) - skd_full <= 1'b0; - else if (i_stb && !o_busy && skd_stb && skd_busy) - skd_full <= 1'b1; - else if (!skd_busy) - skd_full <= 1'b0; - - always @(posedge i_clk) - if (skd_stb && skd_busy) - skd_data <= { i_valid, i_hexbits }; - - always @(*) - if (skd_full) - skd_result = skd_data; - else - skd_result = { i_valid, i_hexbits }; - - assign { skd_valid, skd_hexbits } = skd_result; - assign skd_stb = skd_full || i_stb; - assign o_busy = skd_full; - // }}} - end else begin : NO_SKIDBUFFER - // {{{ - assign skd_stb = i_stb; - assign { skd_valid, skd_hexbits } = { i_valid, i_hexbits }; - assign o_busy = skd_busy; - // }}} - end endgenerate - // }}} - - // w_stb will be true if o_stb is about to be true on the next clock - assign w_stb = ((r_len == cw_len)&&(cw_len != 0)) - ||( skd_stb && !skd_busy && !skd_valid &&(lastcw == 2'b01)); - - always @(*) - begin - skd_busy = o_stb && i_busy && (r_len == cw_len && cw_len != 0); - - if (o_stb && i_busy && !skd_valid && lastcw == 2'b01) - skd_busy = 1'b1; - if (!skd_valid && lastcw == 2'b01 && cw_len != 0 && r_len == cw_len) - skd_busy = 1'b1; - end - - // r_len - // {{{ - // r_len is the length of the codeword as it exists - // in our register - initial r_len = 3'h0; - always @(posedge i_clk) - if (i_reset) - r_len <= 0; - else if (!o_stb || !i_busy || !w_stb) - begin - if (skd_stb && !skd_busy && !skd_valid) // Newline reset - r_len <= 0; - else if (r_len == cw_len && cw_len != 0) - // We've achieved a full length code word. - // reset/restart or counter w/o the newline - r_len <= (skd_stb && !skd_busy) ? 3'h1 : 0; - else if (skd_stb && !skd_busy) //in middle of word - r_len <= r_len + 3'h1; - end - // }}} - - // shiftreg -- assemble a code word, 6-bits at a time - // {{{ - initial shiftreg = 0; - always @(posedge i_clk) - if (skd_stb && !skd_busy) - begin - if (r_len == cw_len && cw_len != 0) - shiftreg[35:30] <= skd_hexbits; - else case(r_len) - 3'b000: shiftreg[35:30] <= skd_hexbits; - 3'b001: shiftreg[29:24] <= skd_hexbits; - 3'b010: shiftreg[23:18] <= skd_hexbits; - 3'b011: shiftreg[17:12] <= skd_hexbits; - 3'b100: shiftreg[11: 6] <= skd_hexbits; - 3'b101: shiftreg[ 5: 0] <= skd_hexbits; - default: begin end - endcase - end - // }}} - - // lastcw - // {{{ - initial lastcw = 2'b00; - always @(posedge i_clk) - if (i_reset) - lastcw <= 2'b00; - else if (o_stb && !i_busy) - lastcw <= o_codword[35:34]; - // }}} - - // o_codword - // {{{ - always @(posedge i_clk) - if (!o_stb || !i_busy) - begin - o_codword <= shiftreg; - - if (skd_stb && !skd_busy && !skd_valid && lastcw == 2'b01) - // End of write signal - o_codword[35:30] <= 6'h2e; - end - // }}} - - // cw_len - // {{{ - // How long do we expect this codeword to be? - initial cw_len = 3'b000; - always @(posedge i_clk) - if (i_reset) - cw_len <= 0; - else if (skd_stb && !skd_busy && !skd_valid) - cw_len <= 0; - else if (skd_stb && !skd_busy && ((cw_len == 0)|| w_stb)) - begin - if (skd_hexbits[5:4] == 2'b11) // 2b vector read - cw_len <= 3'h2; - else if (skd_hexbits[5:4] == 2'b10) // 1b vector read - cw_len <= 3'h1; - else if (skd_hexbits[5:3] == 3'b010) // 2b compressed wr - cw_len <= 3'h2; - else if (skd_hexbits[5:3] == 3'b001) // 2b compressed addr - cw_len <= 3'b010 + { 1'b0, skd_hexbits[2:1] }; - else // long write or set address - cw_len <= 3'h6; - end else if ((!o_stb || !i_busy) && (r_len == cw_len) && (cw_len != 0)) - cw_len <= 0; - // }}} - - // o_stb - // {{{ - initial o_stb = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_stb <= 1'b0; - else if (!o_stb || !i_busy) - o_stb <= w_stb; - // }}} - - assign o_active = skd_stb || r_len > 0; -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - //////////////////////////////////////////////////////////////////////// - // - // Stream properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assume(!skd_stb); - else if ($past(skd_stb && skd_busy)) - begin - assume(skd_stb); - assume($stable(skd_valid)); - assume($stable(skd_hexbits)); - end - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assume(!o_stb); - else if ($past(o_stb && i_busy)) - begin - assume(o_stb); - assume($stable(o_codword)); - end - - // }}} - //////////////////////////////////////////////////////////////////////// - // - // Contract properties - // {{{ - //////////////////////////////////////////////////////////////////////// - // - // - - always @(*) - if (o_stb && i_busy && w_stb) - assert(skd_busy); - - always @(*) - assert(r_len <= 6); - - always @(*) - assert(r_len <= cw_len); - - always @(*) - if (r_len > 0) - begin - casez(shiftreg[35:30]) - 6'b11????: assert(cw_len == 3'h2); - 6'b10????: assert(cw_len == 3'h1); - 6'b010???: assert(cw_len == 3'h2); - 6'b001???: assert(cw_len == 3'h2 + { 1'b0, shiftreg[32:31] }); - default: assert(cw_len == 3'h6); - endcase - end else - assert(cw_len == 0); - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin end - else if ($past(skd_stb && !skd_busy && !skd_valid && lastcw == 2'b01)) - assert(o_stb && o_codword[35:30] == 6'h2e); - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - begin end - else if ($past(!o_stb || !i_busy) && $past(cw_len > 0 && r_len == cw_len)) - assert(o_stb && o_codword == $past(shiftreg)); - -`endif -// }}} -endmodule - diff --git a/delete_later/rtl/wbubus/wbusixchar.v b/delete_later/rtl/wbubus/wbusixchar.v deleted file mode 100644 index c3fa5b0..0000000 --- a/delete_later/rtl/wbubus/wbusixchar.v +++ /dev/null @@ -1,160 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbusixchar.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Supports a conversion from a six digit bus to a printable -// ASCII character representing those six bits. The encoding is -// as follows: -// -// 0-9 -> 0-9 -// A-Z -> 10-35 -// a-z -> 36-61 -// @ -> 62 -// % -> 63 -// -// Note that decoding is stateless, yet requires one clock. -// -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbusixchar( - // {{{ - input wire i_clk, i_reset, - input wire i_stb, - input wire [6:0] i_bits, - output reg o_stb, - output reg [7:0] o_char, - output wire o_busy, - input wire i_busy - // }}} - ); - - // Local declarations - // {{{ - reg [6:0] remap [0:127]; - reg [6:0] newv; - // }}} - - // o_stb - // {{{ - initial o_stb = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_stb <= 1'b0; - else if (!o_stb || !i_busy) - o_stb <= i_stb; - // }}} - - // newv - // {{{ - integer k; - always @(*) begin - for(k=0; k<128; k=k+1) - begin - newv = 0; - // verilator lint_off WIDTH - if (k >= 64) - newv = 7'h0a; - else if (k <= 6'h09) // A digit, WORKS - newv = "0" + { 3'h0, k[3:0] }; - else if (k[5:0] <= 6'd35) // Upper case - newv[6:0] = 7'h41 + { 1'h0, k[5:0] } - 7'd10; // -'A'+10 - else if (k[5:0] <= 6'd61) - newv = 7'h61 + { 1'h0, k[5:0] } - 7'd36;// -'a'+(10+26) - // verilator lint_on WIDTH - else if (k[5:0] == 6'd62) // An '@' sign - newv = 7'h40; - else // if (i_char == 6'h63) // A '%' sign - newv = 7'h25; - - remap[k] = newv; - end - end - // }}} - - // o_char - // {{{ - initial o_char = 8'h00; - always @(posedge i_clk) - if (!o_busy) - o_char <= { 1'b0, remap[i_bits] }; - // }}} - - assign o_busy = o_stb && i_busy; -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg [7:0] f_char; - - reg f_past_valid; - initial f_past_valid = 0; - always @(posedge i_clk) - f_past_valid <= 1; - - // - // Here's the old encoding that "worked" - // - initial f_char = 8'h00; - always @(posedge i_clk) - if ((i_stb)&&(!o_busy)) - begin - if (i_bits[6]) - f_char <= 8'h0a; - else if (i_bits[5:0] <= 6'h09) // A digit, WORKS - f_char <= "0" + { 4'h0, i_bits[3:0] }; - else if (i_bits[5:0] <= 6'd35) // Upper case - f_char <= "A" + { 2'h0, i_bits[5:0] } - 8'd10; // -'A'+10 - else if (i_bits[5:0] <= 6'd61) - f_char <= "a" + { 2'h0, i_bits[5:0] } - 8'd36;// -'a'+(10+26) - else if (i_bits[5:0] == 6'd62) // An '@' sign - f_char <= 8'h40; - else // if (i_char == 6'h63) // A '%' sign - f_char <= 8'h25; - end - - // - // Now let's prove that the two encodings are equivalent - always @(*) - if (o_stb) - assert(f_char == o_char); - - always @(posedge i_clk) - if (f_past_valid && $past(o_stb && i_busy)) - assert($stable(o_char)); -`endif -// }}} -endmodule - diff --git a/delete_later/rtl/wbubus/wbutohex.v b/delete_later/rtl/wbubus/wbutohex.v deleted file mode 100644 index 88a580e..0000000 --- a/delete_later/rtl/wbubus/wbutohex.v +++ /dev/null @@ -1,213 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: wbutohex.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: Supports a printable character conversion from a printable -// ASCII character to six bits of valid data. The encoding is -// as follows: -// -// 0-9 -> 0-9 -// A-Z -> 10-35 -// a-z -> 36-61 -// @ -> 62 -// % -> 63 -// -// Note that decoding is stateless, yet requires one clock. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// }}} -module wbutohex ( - // {{{ - input wire i_clk, i_reset, i_stb, - output wire o_busy, - input wire [7:0] i_byte, - output reg o_soft_reset, - output reg o_stb, o_valid, - input wire i_busy, - output reg [5:0] o_hexbits - // }}} - ); - - // Local declarations - // {{{ - reg [6:0] remap [0:127]; - integer k; - reg [6:0] newv; - // }}} - - assign o_busy = o_stb && i_busy; - - // o_stb - // {{{ - initial o_stb = 1'b0; - always @(posedge i_clk) - if (i_reset) - o_stb <= 1'b0; - else if (!o_stb || !i_busy) - o_stb <= i_stb; - // }}} - - // newv, remap - // {{{ - always @(*) - // initial - begin - for(k=0; k<128; k=k+1) - begin - newv = 7'h40; - // verilator lint_off WIDTH - if ((k >= 48)&&(k <= 57)) // A digit - begin - newv = k; - newv[6:4] = 3'b100; - end else if ((k >= 65)&&(k <= 90)) // Upper case - begin - newv[5:0] = ((k&8'h3f) + 6'h09);// -'A'+10 - newv[6] = 1'b1; - end else if ((k >= 97)&&(k <= 122)) - newv[5:0] = ((k&8'h3f) + 6'h03); // -'a'+(10+26) - // verilator lint_on WIDTH - else if (k == 64) // An '@' sign - newv[5:0] = 6'h3e; - else if (k == 37) // A '%' sign - newv[5:0] = 6'h3f; - else - newv = 0; - - remap[k] = newv; - end - end - // }}} - - // o_valid - // {{{ - always @(posedge i_clk) - if (!o_stb || !i_busy) - begin - { o_valid, o_hexbits } <= remap[i_byte[6:0]]; - if (i_byte[7]) - o_valid <= 0; - end - // }}} - - // o_soft_reset - // {{{ - initial o_soft_reset = 1'b1; - always @(posedge i_clk) - if (i_reset) - o_soft_reset <= 1; - else if (!o_stb || !i_busy) - o_soft_reset <= i_stb && (i_byte[6:0] == 7'h3); - // }}} -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -// -// Formal properties -// {{{ -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -//////////////////////////////////////////////////////////////////////////////// -`ifdef FORMAL - reg f_past_valid; - reg f_valid; - reg [5:0] f_hexbits; - - initial f_past_valid = 1'b0; - always @(posedge i_clk) - f_past_valid <= 1'b1; - - always @(*) - if (!f_past_valid) - assume(i_reset); - - // always @(*) - // assume((i_byte >= 8'h30) && (i_byte <= 8'h39)); - - initial f_valid = 1'b0; - always @(posedge i_clk) - if (i_reset) - begin - f_valid <= 1'b0; - f_hexbits <= 6'h0; - end else if (!o_stb || !i_busy) - begin - // These are the defaults, to be overwridden by the ifs below - f_valid <= 1'b1; - f_hexbits <= 6'h00; - - if ((i_byte >= 8'h30)&&(i_byte <= 8'h39)) // A digit - f_hexbits <= { 2'b0, i_byte[3:0] }; - else if ((i_byte >= 8'h41)&&(i_byte <= 8'h5a)) // Upper case - f_hexbits <= (i_byte[5:0] - 6'h01 + 6'h0a);// -'A'+10 - else if ((i_byte >= 8'h61)&&(i_byte <= 8'h7a)) - f_hexbits <= (i_byte[5:0] +6'h03); // -'a'+(10+26) - else if (i_byte == 8'h40) // An '@' sign - f_hexbits <= 6'h3e; - else if (i_byte == 8'h25) // A '%' sign - f_hexbits <= 6'h3f; - else - f_valid <= 1'b0; - end - - always @(*) - if (o_stb) - begin - assert(f_valid == o_valid); - if (o_valid) - assert(f_hexbits == o_hexbits); - end - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assume(!i_stb); - else if ($past(i_stb && o_busy)) - begin - assume(i_stb); - assume($stable(i_byte)); - end - - always @(posedge i_clk) - if (f_past_valid && !$past(i_reset) && $past(i_stb && !o_busy)) - assert(o_stb); - - always @(posedge i_clk) - if (!f_past_valid || $past(i_reset)) - assert(!o_stb); - else if ($past(o_stb && i_busy)) - begin - assert(o_stb); - assert($stable(o_valid)); - assert($stable(o_hexbits)); - end - -`endif -// }}} -endmodule - diff --git a/delete_later/rtl/xgenclk.v b/delete_later/rtl/xgenclk.v deleted file mode 100644 index 12b98e3..0000000 --- a/delete_later/rtl/xgenclk.v +++ /dev/null @@ -1,137 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// Filename: xgenclk.v -// {{{ -// Project: 10Gb Ethernet switch -// -// Purpose: This module works in conjunction with the genclk module to -// generate clock with an arbitrary frequency. The genclk -// module creates an 8-bit word. -// -// The module is nominally designed for a 100MHz clock input. Using a -// 100 MHz clock input, the maximum clock speed that can be created is -// about 166MHz. -// -// Creator: Dan Gisselquist, Ph.D. -// Gisselquist Technology, LLC -// -//////////////////////////////////////////////////////////////////////////////// -// }}} -// Copyright (C) 2023, Gisselquist Technology, LLC -// {{{ -// This file is part of the ETH10G project. -// -// The ETH10G project contains free software and gateware, licensed under the -// Apache License, Version 2.0 (the "License"). You may not use this project, -// or this file, except in compliance with the License. You may obtain a copy -// of the License at -// }}} -// http://www.apache.org/licenses/LICENSE-2.0 -// {{{ -// Unless required by applicable law or agreed to in writing, files -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -// License for the specific language governing permissions and limitations -// under the License. -// -//////////////////////////////////////////////////////////////////////////////// -// -`default_nettype none -// -// `define DIFFERENTIAL -// }}} -module xgenclk #( - parameter [0:0] OPT_LCLCLOCK = 1'b0 - ) ( - // {{{ - input wire i_clk, i_ce, - input wire i_hsclk, // @ 4x i_clk frequency - input wire [7:0] i_word, - output wire [1:0] o_pin, - output wire o_clk - // }}} - ); - - // Local declarations - // {{{ - wire [5:0] ignored_data; - wire [1:0] slave_to_master; - - wire pll_input, w_pin, high_z; - reg [7:0] r_word; - reg [1:0] r_ce; - // }}} - - initial r_ce = 2'b00; - always @(posedge i_clk) - r_ce <= { r_ce[0], i_ce }; - always @(posedge i_clk) - r_word <= i_word; - - OSERDESE2 #( - // {{{ - .DATA_RATE_OQ("DDR"), // DDR goes up to 950MHz, SDR only to 600 - .DATA_RATE_TQ("SDR"), - .DATA_WIDTH(8), - .SERDES_MODE("MASTER"), - .TRISTATE_WIDTH(1) // Really ... this is unused - // }}} - ) u_lowserdes( - // {{{ - // Verilator lint_off PINCONNECTEMPTY - .OCE(r_ce[1]), - .TCE(1'b1), .TFB(), .TQ(high_z), - .CLK(i_hsclk), // HS clock - .CLKDIV(i_clk), // Divided clock input (lowspeed clock) - .OQ(w_pin), // Data path to IOB *only* - .OFB(), // Data path output feedback to ISERDESE2 or ODELAYE2 - .D1(r_word[7]), - .D2(r_word[6]), - .D3(r_word[5]), - .D4(r_word[4]), - .D5(r_word[3]), - .D6(r_word[2]), - .D7(r_word[1]), - .D8(r_word[0]), - .RST(1'b0), // .RST(!r_ce[1]), - .TBYTEIN(1'b0), .TBYTEOUT(), - .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), - .SHIFTIN1(), .SHIFTIN2(), - .SHIFTOUT1(), .SHIFTOUT2() - // Verilator lint_on PINCONNECTEMPTY - // }}} - ); - - generate if (OPT_LCLCLOCK) - begin : GEN_CLK_REFLECTION - // {{{ - wire w_clk; - - // IOBUFDS - // u_genclkio( - // .T(high_z),.I(w_pin),.IO(o_pin[1]), .IOB(o_pin[0]), - // .O(w_clk) - // ); - - IOBUF u_genclkio_p(.T(high_z),.I(w_pin),.IO(o_pin[1]), - .O(w_clk)); - // OBUF u_genclkio_n(.T(high_z),.I(w_pin),.IO(!o_pin[0])); - assign o_pin[0] = 1'b0; - // OBUF u_genclkio_n(.T(high_z),.I(w_pin),.IO(!o_pin[0])); - - // BUFG clkgen_buf(.I(w_clk), .O(o_clk)); - // BUFR #(.BUFR_DIVIDE("BYPASS"), .SIM_DEVICE("7SERIES")) clkgen_buf(.I(w_clk), .O(o_clk)); - // BUFH clkgen_buf(.I(w_clk), .O(o_clk)); - // wire tmp; BUFMR clkgen_buf(.I(w_clk), .O(tmp)); BUFR aux(.I(tmp), .O(o_clk)); - assign o_clk = w_clk; - // }}} - end else begin : NO_REFLECTION - OBUFDS - u_genclkio( - .I(w_pin), .O(o_pin[1]), .OB(o_pin[0]) - ); - - assign o_clk = 1'b0; - end endgenerate - -endmodule