diff --git a/ddr3_dimm_micron_sim_behav.wcfg b/ddr3_dimm_micron_sim_behav.wcfg index 59ff71b..d951913 100644 --- a/ddr3_dimm_micron_sim_behav.wcfg +++ b/ddr3_dimm_micron_sim_behav.wcfg @@ -11,30 +11,49 @@ - - - + + + - - + + - + - - + + + + + Model File label + + sync_rst + sync_rst + + + o_controller_idelayctrl_rdy + o_controller_idelayctrl_rdy + + + idelayctrl_rdy + idelayctrl_rdy + + + dci_locked + dci_locked + clk_locked clk_locked @@ -162,10 +181,25 @@ ba_addr[2:0] UNSIGNEDDECRADIX - - dq[63:0] - dq[63:0] - HEXRADIX + + o_ddr3_odt + o_ddr3_odt + + + i_controller_dqs_tri_control + i_controller_dqs_tri_control + + + i_controller_dq_tri_control + i_controller_dq_tri_control + + + i_controller_dqs_tri_control + i_controller_dqs_tri_control + + + i_controller_dq_tri_control + i_controller_dq_tri_control i_controller_clk @@ -179,23 +213,20 @@ i_ddr3_clk_90 i_ddr3_clk_90 - - dqs[7:0] - dqs[7:0] - - - - dq[7:0] - dq[7:0] - - - dqs[0:0] - dqs[0:0] - dqs_n[7:0] dqs_n[7:0] + + lane[2:0] + lane[2:0] + UNSIGNEDDECRADIX + + + read_lane_data[63:0] + read_lane_data[63:0] + HEXRADIX + o_ddr3_clk_p o_ddr3_clk_p @@ -224,6 +255,7 @@ read_data_store[511:0] read_data_store[511:0] + HEXRADIX o_wb_data[511:0] @@ -248,10 +280,324 @@ toggle_dqs_q toggle_dqs_q + + read_lane_data[63:0] + read_lane_data[63:0] + HEXRADIX + - Bank Track + test label + + cmd_odt_q + cmd_odt_q + + + cmd_odt + cmd_odt + + + write_calib_odt + write_calib_odt + + + i_controller_clk + i_controller_clk + + + stage2_pending + stage2_pending + + + stage2_we + stage2_we + + + stage2_col[9:0] + stage2_col[9:0] + UNSIGNEDDECRADIX + + + stage2_bank[2:0] + stage2_bank[2:0] + UNSIGNEDDECRADIX + + + stage2_row[15:0] + stage2_row[15:0] + UNSIGNEDDECRADIX + + + delay_before_write_counter_q[7:0][3:0] + delay_before_write_counter_q[7:0][3:0] + + + delay_before_write_counter_d[7:0][3:0] + delay_before_write_counter_d[7:0][3:0] + + + ba_addr[2:0] + ba_addr[2:0] + UNSIGNEDDECRADIX + + + addr[15:0] + addr[15:0] + UNSIGNEDDECRADIX + + + label + [0] + [0] + cs + #FF0080 + true + + + stage1_pending + stage1_pending + + + stage2_pending + stage2_pending + + + cmd_d[3:0][25:0] + cmd_d[3:0][25:0] + BINARYRADIX + + + [3][25:0] + [3][25:0] + BINARYRADIX + + + [2][25:0] + [2][25:0] + BINARYRADIX + + + [1][25:0] + [1][25:0] + BINARYRADIX + + + [0][25:0] + [0][25:0] + BINARYRADIX + + + [3][25:0] + [3][25:0] + + + [2][25:0] + [2][25:0] + + + [1][25:0] + [1][25:0] + + + [0][25:0] + [0][25:0] + + + + stage2_update + stage2_update + + + o_ddr3_cs_n + o_ddr3_cs_n + + + instruction_address[4:0] + instruction_address[4:0] + UNSIGNEDDECRADIX + + + command_used[23:0] + command_used[23:0] + ASCIIRADIX + #FFD700 + true + + + calib_addr[25:0] + calib_addr[25:0] + UNSIGNEDDECRADIX + + + stage1_col[9:0] + stage1_col[9:0] + UNSIGNEDDECRADIX + + + stage2_col[9:0] + stage2_col[9:0] + UNSIGNEDDECRADIX + + + o_wb_stall_q + o_wb_stall_q + + + stage2_stall + stage2_stall + + + stage1_stall + stage1_stall + + + o_wb_stall + o_wb_stall + + + o_phy_dqs_tri_control + o_phy_dqs_tri_control + + + o_phy_dq_tri_control + o_phy_dq_tri_control + + + cmd_odt + cmd_odt + + + i_controller_clk + i_controller_clk + + + o_ddr3_odt + o_ddr3_odt + + + o_ddr3_clk_p + o_ddr3_clk_p + + + dqs[7:0] + dqs[7:0] + + + + dq[63:0] + dq[63:0] + HEXRADIX + + + o_wb_data[511:0] + o_wb_data[511:0] + HEXRADIX + #FF00FF + true + + + read_data_store[511:0] + read_data_store[511:0] + HEXRADIX + + + o_aux[15:0] + o_aux[15:0] + #800080 + true + + + lane[2:0] + lane[2:0] + UNSIGNEDDECRADIX + + + state_calibrate[5:0] + state_calibrate[5:0] + UNSIGNEDDECRADIX + + + o_wb_stall_q + o_wb_stall_q + + + o_wb_stall + o_wb_stall + + + o_wb2_stall + o_wb2_stall + + + stage2_stall + stage2_stall + + + stage1_stall + stage1_stall + + + o_wb_stall_d + o_wb_stall_d + + + calib_stb + calib_stb + #FFA500 + true + + + i_wb_stb + i_wb_stb + #FFA500 + true + + + calib_aux[15:0] + calib_aux[15:0] + + + calib_we + calib_we + + + calib_data[511:0] + calib_data[511:0] + + + read_test_address_counter[25:0] + read_test_address_counter[25:0] + + + write_test_address_counter[25:0] + write_test_address_counter[25:0] + + + check_test_address_counter[25:0] + check_test_address_counter[25:0] + + + correct_read_data[31:0] + correct_read_data[31:0] + + + wrong_read_data[31:0] + wrong_read_data[31:0] + + + bank track + label + + + state_calibrate[5:0] + state_calibrate[5:0] + + + read_data_store[511:0] + read_data_store[511:0] + HEXRADIX + delay_before_read_counter_q[7:0][3:0] delay_before_read_counter_q[7:0][3:0] @@ -292,18 +638,6 @@ stage2_we stage2_we - - write_calib_stb - write_calib_stb - - - write_calib_aux[15:0] - write_calib_aux[15:0] - - - write_calib_we - write_calib_we - o_wb_ack_read_q[15:0][16:0] o_wb_ack_read_q[15:0][16:0] @@ -328,6 +662,102 @@ stage1_next_row[15:0] stage1_next_row[15:0] + + idelay_data_cntvaluein[7:0][4:0] + idelay_data_cntvaluein[7:0][4:0] + + + [7][4:0] + [7][4:0] + UNSIGNEDDECRADIX + + + [6][4:0] + [6][4:0] + UNSIGNEDDECRADIX + + + [5][4:0] + [5][4:0] + UNSIGNEDDECRADIX + + + [4][4:0] + [4][4:0] + UNSIGNEDDECRADIX + + + [3][4:0] + [3][4:0] + UNSIGNEDDECRADIX + + + [2][4:0] + [2][4:0] + UNSIGNEDDECRADIX + + + [1][4:0] + [1][4:0] + UNSIGNEDDECRADIX + + + [0][4:0] + [0][4:0] + UNSIGNEDDECRADIX + + + + idelay_data_cntvaluein_prev[4:0] + idelay_data_cntvaluein_prev[4:0] + + + + idelay_dqs_cntvaluein[7:0][4:0] + idelay_dqs_cntvaluein[7:0][4:0] + UNSIGNEDDECRADIX + + + [7][4:0] + [7][4:0] + UNSIGNEDDECRADIX + + + [6][4:0] + [6][4:0] + UNSIGNEDDECRADIX + + + [5][4:0] + [5][4:0] + UNSIGNEDDECRADIX + + + [4][4:0] + [4][4:0] + UNSIGNEDDECRADIX + + + [3][4:0] + [3][4:0] + UNSIGNEDDECRADIX + + + [2][4:0] + [2][4:0] + UNSIGNEDDECRADIX + + + [1][4:0] + [1][4:0] + UNSIGNEDDECRADIX + + + [0][4:0] + [0][4:0] + UNSIGNEDDECRADIX + + stage1_stall stage1_stall @@ -356,14 +786,24 @@ DDR3 Controller label + + prev_write_level_feedback + prev_write_level_feedback + - state_calibrate[4:0] - state_calibrate[4:0] + state_calibrate[5:0] + state_calibrate[5:0] + + + delay_before_write_level_feedback[4:0] + delay_before_write_level_feedback[4:0] + UNSIGNEDDECRADIX lane[2:0] lane[2:0] UNSIGNEDDECRADIX + instruction_address[4:0] @@ -378,14 +818,16 @@ dqs_start_index[5:0] dqs_start_index[5:0] + UNSIGNEDDECRADIX dqs_target_index[5:0] dqs_target_index[5:0] + UNSIGNEDDECRADIX - dq_target_index[5:0] - dq_target_index[5:0] + dq_target_index[7:0][5:0] + dq_target_index[7:0][5:0] UNSIGNEDDECRADIX @@ -405,6 +847,38 @@ data_start_index[7:0][6:0] data_start_index[7:0][6:0] + + [56] + [56] + + + [48] + [48] + + + [32] + [32] + + + [40] + [40] + + + [24] + [24] + + + [16] + [16] + + + [8] + [8] + + + [0] + [0] + i_phy_iserdes_dqs[63:0] i_phy_iserdes_dqs[63:0] @@ -415,6 +889,80 @@ i_phy_iserdes_dqs[63:0] BINARYRADIX + + i_phy_iserdes_dqs_lane2 + label + BINARYRADIX + + [15] + [15] + + + [14] + [14] + + + [13] + [13] + + + [12] + [12] + + + [11] + [11] + + + [10] + [10] + + + [9] + [9] + + + [8] + [8] + + + + lane0 + label + BINARYRADIX + + [7] + [7] + + + [6] + [6] + + + [5] + [5] + + + [4] + [4] + + + [3] + [3] + + + [2] + [2] + + + [1] + [1] + + + [0] + [0] + + i_phy_iserdes_dqs_lane1 label @@ -493,6 +1041,30 @@ [0] + + data_lane01 + label + BINARYRADIX + true + VirtualBus[] + VirtualBus[] + + [0] + [0] + + + [1] + [1] + + + [64] + [64] + + + [65] + [65] + + i_phy_iserdes_bitslip_reference[63:0] i_phy_iserdes_bitslip_reference[63:0] @@ -545,8 +1117,8 @@ BINARYRADIX - train_delay[1:0] - train_delay[1:0] + train_delay[3:0] + train_delay[3:0] i_phy_iserdes_bitslip_reference[63:0] @@ -754,8 +1326,8 @@ dqs_target_index_orig[5:0] - dq_target_index[5:0] - dq_target_index[5:0] + dq_target_index[7:0][5:0] + dq_target_index[7:0][5:0] dqs_target_index_value[5:0] @@ -779,8 +1351,8 @@ i_controller_clk - state_calibrate[4:0] - state_calibrate[4:0] + state_calibrate[5:0] + state_calibrate[5:0] instruction_address[4:0] diff --git a/formal.gtkw b/formal.gtkw index 5edeb85..5e2c47f 100644 --- a/formal.gtkw +++ b/formal.gtkw @@ -1,12 +1,15 @@ [*] [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Sun Jul 9 01:37:07 2023 +[*] Thu Sep 14 06:23:44 2023 [*] - +[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd" +[dumpfile_mtime] "Thu Sep 14 06:21:18 2023" +[dumpfile_size] 165043 +[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal.gtkw" [timestart] 0 [size] 1848 1126 [pos] -1 -1 -*-5.075655 63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-4.925239 67 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] ddr3_controller. [treeopen] ddr3_controller.wb_properties. [sst_width] 391 @@ -20,28 +23,25 @@ ddr3_controller.i_controller_clk ddr3_controller.i_rst_n ddr3_controller.reset_done @24 -ddr3_controller.state_calibrate[4:0] ddr3_controller.instruction_address[4:0] ddr3_controller.delay_counter[15:0] @28 ddr3_controller.o_wb_stall_q ddr3_controller.i_wb_cyc -@200 -- +@22 +ddr3_controller.stage2_aux[15:0] @28 -ddr3_controller.f_read_fifo -ddr3_controller.f_write_fifo -ddr3_controller.o_wb_stall -ddr3_controller.i_wb_stb -ddr3_controller.stage1_pending -ddr3_controller.stage2_pending -@200 -- +ddr3_controller.pause_counter +@24 +ddr3_controller.state_calibrate[5:0] @28 +ddr3_controller.past_sync_rst_controller +ddr3_controller.sync_rst_controller +@29 +{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0] -@c00028 +@c00029 +{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0] -@28 +@29 (0)ddr3_controller.cmd_d<1>[23:0] (1)ddr3_controller.cmd_d<1>[23:0] (2)ddr3_controller.cmd_d<1>[23:0] @@ -66,11 +66,11 @@ ddr3_controller.stage2_pending (21)ddr3_controller.cmd_d<1>[23:0] (22)ddr3_controller.cmd_d<1>[23:0] (23)ddr3_controller.cmd_d<1>[23:0] -@1401200 +@1401201 -group_end -@c00028 +@c00029 +{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0] -@28 +@29 (0)ddr3_controller.cmd_d<2>[23:0] (1)ddr3_controller.cmd_d<2>[23:0] (2)ddr3_controller.cmd_d<2>[23:0] @@ -95,12 +95,110 @@ ddr3_controller.stage2_pending (21)ddr3_controller.cmd_d<2>[23:0] (22)ddr3_controller.cmd_d<2>[23:0] (23)ddr3_controller.cmd_d<2>[23:0] -@1401200 +@1401201 -group_end -@28 +@29 +{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0] -ddr3_controller.stage1_issue_command -ddr3_controller.stage2_issue_command +@28 +ddr3_controller.f_aux_ack_pipe_after_stage2<0>[16:0] +ddr3_controller.f_aux_ack_pipe_after_stage2<1>[16:0] +ddr3_controller.f_aux_ack_pipe_after_stage2<2>[16:0] +ddr3_controller.f_aux_ack_pipe_after_stage2<3>[16:0] +ddr3_controller.f_aux_ack_pipe_after_stage2<4>[16:0] +ddr3_controller.f_aux_ack_pipe_after_stage2<5>[16:0] +ddr3_controller.f_aux_ack_pipe_after_stage2<6>[16:0] +@22 +ddr3_controller.o_wb_ack_read_q<0>[16:0] +ddr3_controller.o_wb_ack_read_q<1>[16:0] +ddr3_controller.o_wb_ack_read_q<2>[16:0] +ddr3_controller.o_wb_ack_read_q<3>[16:0] +ddr3_controller.o_wb_ack_read_q<4>[16:0] +ddr3_controller.o_wb_ack_read_q<5>[16:0] +ddr3_controller.o_wb_ack_read_q<6>[16:0] +ddr3_controller.o_wb_ack_read_q<7>[16:0] +ddr3_controller.o_wb_ack_read_q<8>[16:0] +ddr3_controller.o_wb_ack_read_q<9>[16:0] +ddr3_controller.o_wb_ack_read_q[16:0] +ddr3_controller.o_wb_ack_read_q[16:0] +ddr3_controller.o_wb_ack_read_q[16:0] +ddr3_controller.o_wb_ack_read_q[16:0] +ddr3_controller.o_wb_ack_read_q[16:0] +ddr3_controller.o_wb_ack_read_q[16:0] +@24 +ddr3_controller.f_sum_of_pending_acks[15:0] +@28 +ddr3_controller.stage1_pending +ddr3_controller.stage2_pending +@22 +ddr3_controller.o_wb_ack_read_q<0>[16:0] +ddr3_controller.o_wb_ack_read_q<1>[16:0] +ddr3_controller.o_wb_ack_read_q<2>[16:0] +ddr3_controller.calib_addr[23:0] +ddr3_controller.calib_addr_plus_anticipate[23:0] +ddr3_controller.calib_aux[15:0] +ddr3_controller.calib_data[511:0] +ddr3_controller.calib_sel[63:0] +@28 +ddr3_controller.calib_stb +ddr3_controller.calib_we +@200 +- +@28 +ddr3_controller.wb_properties.i_wb_cyc +@22 +ddr3_controller.wb_properties.f_outstanding[3:0] +ddr3_controller.wb_properties.f_nacks[3:0] +ddr3_controller.wb_properties.f_nreqs[3:0] +@28 +ddr3_controller.wb_properties.i_wb_ack +ddr3_controller.wb_properties.i_wb_err +@200 +- +@28 +ddr3_controller.fifo_1.empty +@24 +ddr3_controller.fifo_1.fifo_reg<0>[24:0] +ddr3_controller.fifo_1.fifo_reg<1>[24:0] +@28 +ddr3_controller.fifo_1.full +ddr3_controller.fifo_1.i_clk +ddr3_controller.fifo_1.i_rst_n +@22 +ddr3_controller.fifo_1.read_data[24:0] +ddr3_controller.fifo_1.read_data_next[24:0] +@28 +ddr3_controller.fifo_1.read_fifo +ddr3_controller.fifo_1.read_pointer +@22 +ddr3_controller.fifo_1.write_data[24:0] +@28 +ddr3_controller.fifo_1.write_fifo +ddr3_controller.fifo_1.write_pointer +@200 +- +@28 +ddr3_controller.f_read_fifo +ddr3_controller.f_write_fifo +ddr3_controller.o_wb_stall +ddr3_controller.i_wb_stb +ddr3_controller.stage1_pending +ddr3_controller.stage2_pending +@200 +- +@28 +ddr3_controller.f_empty +@22 +ddr3_controller.calib_aux[15:0] +ddr3_controller.calib_data[511:0] +ddr3_controller.calib_sel[63:0] +@28 +ddr3_controller.calib_stb +ddr3_controller.calib_we +@24 +ddr3_controller.calib_addr[23:0] +@28 +ddr3_controller.bank_status_q[7:0] +ddr3_controller.f_bank_status[7:0] @200 - @22 @@ -128,12 +226,7 @@ ddr3_controller.f_sum_of_pending_acks[15:0] ddr3_controller.wb_properties.f_ackwait_count[3:0] @28 ddr3_controller.f_ack_pipe_after_stage2[6:0] -@22 -ddr3_controller.f_stall_count[4:0] -@28 ddr3_controller.delay_counter_is_zero -ddr3_controller.write_calib_stb -ddr3_controller.write_calib_we @200 - @28 @@ -214,7 +307,6 @@ ddr3_controller.wb_properties.i_wb_cyc @200 - @28 -ddr3_controller.wb_properties.i_slave_busy ddr3_controller.i_wb_stb ddr3_controller.o_wb_stall ddr3_controller.i_wb_cyc @@ -361,12 +453,6 @@ ddr3_controller.o_wb_ack_read_q<6>[16:0] ddr3_controller.o_wb_ack_read_q<7>[16:0] ddr3_controller.o_wb_ack_read_q<8>[16:0] ddr3_controller.o_wb_ack_read_q<9>[16:0] -ddr3_controller.o_wb_ack_read_q<10>[16:0] -ddr3_controller.o_wb_ack_read_q<11>[16:0] -ddr3_controller.o_wb_ack_read_q<12>[16:0] -ddr3_controller.o_wb_ack_read_q<13>[16:0] -ddr3_controller.o_wb_ack_read_q<14>[16:0] -ddr3_controller.o_wb_ack_read_q<15>[16:0] @24 ddr3_controller.added_read_pipe_max[3:0] @28 @@ -398,7 +484,6 @@ ddr3_controller.o_aux[15:0] ddr3_controller.stage1_aux[15:0] ddr3_controller.stage2_aux[15:0] ddr3_controller.write_pattern[127:0] -ddr3_controller.read_ack_width[31:0] ddr3_controller.o_wb_ack_read_q<0>[16:0] ddr3_controller.o_wb_ack_read_q<1>[16:0] ddr3_controller.shift_reg_read_pipe_q<0>[16:0] @@ -414,8 +499,6 @@ ddr3_controller.shift_reg_read_pipe_d<3>[16:0] - @28 ddr3_controller.fifo_1.i_rst_n -ddr3_controller.write_calib_stb -ddr3_controller.write_calib_we @200 - @28 @@ -440,8 +523,6 @@ ddr3_controller.i_wb_cyc ddr3_controller.f_empty ddr3_controller.fifo_1.empty ddr3_controller.f_full -ddr3_controller.write_calib_stb -ddr3_controller.write_calib_we @200 - @24