From d6f9614295b63b60d0ce22806fabf69ad603be0c Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Thu, 29 Jun 2023 13:03:08 +0800 Subject: [PATCH] update gtkw --- formal_cover_3.gtkw | 950 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 815 insertions(+), 135 deletions(-) diff --git a/formal_cover_3.gtkw b/formal_cover_3.gtkw index a259299..8aae927 100644 --- a/formal_cover_3.gtkw +++ b/formal_cover_3.gtkw @@ -1,18 +1,18 @@ [*] [*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Fri Jun 23 13:27:15 2023 +[*] Wed Jun 28 13:01:03 2023 [*] [dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd" -[dumpfile_mtime] "Fri Jun 23 13:26:30 2023" -[dumpfile_size] 318610 +[dumpfile_mtime] "Wed Jun 28 12:58:52 2023" +[dumpfile_size] 318856 [savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal_cover_3.gtkw" [timestart] 0 [size] 1848 1126 [pos] -1 -1 -*-5.917290 156 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-5.617290 175 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] ddr3_controller. [sst_width] 391 -[signals_width] 541 +[signals_width] 350 [sst_expanded] 1 [sst_vpaned_height] 743 @420 @@ -24,154 +24,699 @@ ddr3_controller.reset_done @24 ddr3_controller.state_calibrate[4:0] ddr3_controller.instruction_address[4:0] -@25 ddr3_controller.delay_counter[15:0] @200 - @28 +ddr3_controller.fifo_1.read_pointer +ddr3_controller.fifo_1.write_pointer +ddr3_controller.wb_properties.i_slave_busy +ddr3_controller.f_read_fifo +@22 +ddr3_controller.f_read_data[616:0] +@c00028 +ddr3_controller.f_write_data[616:0] +@28 +(0)ddr3_controller.f_write_data[616:0] +(1)ddr3_controller.f_write_data[616:0] +(2)ddr3_controller.f_write_data[616:0] +(3)ddr3_controller.f_write_data[616:0] +(4)ddr3_controller.f_write_data[616:0] +(5)ddr3_controller.f_write_data[616:0] +(6)ddr3_controller.f_write_data[616:0] +(7)ddr3_controller.f_write_data[616:0] +(8)ddr3_controller.f_write_data[616:0] +(9)ddr3_controller.f_write_data[616:0] +(10)ddr3_controller.f_write_data[616:0] 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+(613)ddr3_controller.f_write_data[616:0] +(614)ddr3_controller.f_write_data[616:0] +(615)ddr3_controller.f_write_data[616:0] +(616)ddr3_controller.f_write_data[616:0] +@1401200 +-group_end +@28 +ddr3_controller.f_write_fifo ddr3_controller.wb_properties.i_wb_cyc @24 -ddr3_controller.wb_properties.f_nacks[3:0] -ddr3_controller.wb_properties.f_nreqs[3:0] ddr3_controller.wb_properties.f_outstanding[3:0] -ddr3_controller.f_sum_of_pending_acks[15:0] @28 ddr3_controller.i_wb_stb ddr3_controller.o_wb_stall ddr3_controller.i_wb_cyc ddr3_controller.o_wb_ack -@200 -- -@22 -ddr3_controller.stage1_aux[15:0] -ddr3_controller.stage2_aux[15:0] -ddr3_controller.write_calib_aux[15:0] -@28 -ddr3_controller.write_calib_stb -ddr3_controller.write_calib_we -@200 -- -@28 -ddr3_controller.pipe_stall -ddr3_controller.stage1_pending -ddr3_controller.stage2_pending -ddr3_controller.shift_reg_read_pipe_q<4>[16:0] -ddr3_controller.shift_reg_read_pipe_q<3>[16:0] -@c00028 -ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -@28 -(0)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(1)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(2)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(3)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(4)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(5)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(6)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(7)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(8)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(9)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(10)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(11)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(12)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(13)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(14)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(15)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(16)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -@1401200 --group_end -@c00028 -ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -@28 -(0)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(1)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(2)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(3)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(4)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(5)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(6)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(7)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(8)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(9)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(10)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(11)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(12)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(13)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(14)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(15)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(16)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -@1401200 --group_end -@28 -ddr3_controller.shift_reg_read_pipe_q<0>[16:0] -ddr3_controller.o_wb_ack_read_q<1>[16:0] -ddr3_controller.o_wb_ack_read_q<0>[16:0] -@24 -ddr3_controller.added_read_pipe_max[3:0] -@28 -ddr3_controller.wb_properties.i_check_assert -@200 -- -@28 -ddr3_controller.f_read_fifo_2 -ddr3_controller.f_write_fifo_2 -@22 -ddr3_controller.i_aux[15:0] -ddr3_controller.o_aux[15:0] -@200 -- -@22 -ddr3_controller.stage1_aux[15:0] -ddr3_controller.stage2_aux[15:0] -ddr3_controller.write_pattern[127:0] -ddr3_controller.read_ack_width[31:0] -ddr3_controller.o_wb_ack_read_q<0>[16:0] -ddr3_controller.o_wb_ack_read_q<1>[16:0] -ddr3_controller.shift_reg_read_pipe_q<0>[16:0] -ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -ddr3_controller.shift_reg_read_pipe_q<3>[16:0] -ddr3_controller.shift_reg_read_pipe_q<4>[16:0] -ddr3_controller.shift_reg_read_pipe_d<0>[16:0] -ddr3_controller.shift_reg_read_pipe_d<1>[16:0] -ddr3_controller.shift_reg_read_pipe_d<2>[16:0] -ddr3_controller.shift_reg_read_pipe_d<3>[16:0] -@200 -- -@28 -ddr3_controller.fifo_1.i_rst_n -ddr3_controller.write_calib_stb -ddr3_controller.write_calib_we -@200 -- -@28 -ddr3_controller.pipe_stall -ddr3_controller.o_wb_stall ddr3_controller.o_wb_stall_d -ddr3_controller.i_wb_cyc -ddr3_controller.i_wb_stb -ddr3_controller.i_wb_we -@24 -ddr3_controller.o_wb_ack +ddr3_controller.o_wb_stall_q +ddr3_controller.delay_counter_is_zero @200 - -@24 -ddr3_controller.f_activate_slot[1:0] -ddr3_controller.f_precharge_slot[1:0] -ddr3_controller.f_read_slot[1:0] -ddr3_controller.f_write_slot[1:0] @28 -ddr3_controller.f_read_fifo -ddr3_controller.f_write_fifo -ddr3_controller.i_wb_cyc -ddr3_controller.f_empty -ddr3_controller.fifo_1.empty -ddr3_controller.f_full -ddr3_controller.write_calib_stb -ddr3_controller.write_calib_we +ddr3_controller.stage1_stall +ddr3_controller.stage1_pending +ddr3_controller.stage1_we +@22 +ddr3_controller.stage1_aux[15:0] +@24 +ddr3_controller.stage1_bank[2:0] +@22 +ddr3_controller.stage1_col[9:0] +ddr3_controller.stage1_row[13:0] @200 - +@28 +ddr3_controller.stage2_stall +ddr3_controller.stage2_pending +ddr3_controller.stage2_update +ddr3_controller.stage2_we +@c00022 +ddr3_controller.stage2_aux[15:0] +@28 +(0)ddr3_controller.stage2_aux[15:0] +(1)ddr3_controller.stage2_aux[15:0] +(2)ddr3_controller.stage2_aux[15:0] +(3)ddr3_controller.stage2_aux[15:0] +(4)ddr3_controller.stage2_aux[15:0] +(5)ddr3_controller.stage2_aux[15:0] +(6)ddr3_controller.stage2_aux[15:0] +(7)ddr3_controller.stage2_aux[15:0] +(8)ddr3_controller.stage2_aux[15:0] +(9)ddr3_controller.stage2_aux[15:0] +(10)ddr3_controller.stage2_aux[15:0] +(11)ddr3_controller.stage2_aux[15:0] +(12)ddr3_controller.stage2_aux[15:0] +(13)ddr3_controller.stage2_aux[15:0] +(14)ddr3_controller.stage2_aux[15:0] +(15)ddr3_controller.stage2_aux[15:0] +@1401200 +-group_end @24 -ddr3_controller.delay_counter[15:0] +ddr3_controller.stage2_bank[2:0] +@22 +ddr3_controller.stage2_col[9:0] +ddr3_controller.stage2_row[13:0] +@200 +- @28 +{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0] @c00028 @@ -234,7 +779,143 @@ ddr3_controller.delay_counter[15:0] -group_end @28 +{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0] +@200 +- @24 +ddr3_controller.wb_properties.f_nacks[3:0] +ddr3_controller.wb_properties.f_nreqs[3:0] +ddr3_controller.f_outstanding[3:0] +@23 +ddr3_controller.f_sum_of_pending_acks[31:0] +@200 +- +@28 +ddr3_controller.stage1_pending +ddr3_controller.stage2_pending +ddr3_controller.stage2_update +ddr3_controller.shift_reg_read_pipe_q<4>[16:0] +ddr3_controller.shift_reg_read_pipe_q<3>[16:0] +@c00028 +ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +@28 +(0)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(1)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(2)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(3)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(4)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(5)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(6)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(7)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(8)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(9)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(10)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(11)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(12)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(13)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(14)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(15)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +(16)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +@1401200 +-group_end +@c00028 +ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +@28 +(0)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(1)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(2)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(3)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(4)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(5)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(6)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(7)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(8)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(9)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(10)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(11)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(12)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(13)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(14)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(15)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +(16)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +@1401200 +-group_end +@28 +ddr3_controller.shift_reg_read_pipe_q<0>[16:0] +ddr3_controller.o_wb_ack_read_q<1>[16:0] +ddr3_controller.o_wb_ack_read_q<0>[16:0] +ddr3_controller.o_wb_ack +ddr3_controller.fifo_1.empty +ddr3_controller.fifo_1.full +ddr3_controller.fifo_1.empty +ddr3_controller.fifo_1.full +ddr3_controller.fifo_1.read_fifo +ddr3_controller.fifo_1.write_fifo +ddr3_controller.fifo_1.read_pointer +ddr3_controller.fifo_1.write_pointer +@200 +- +@24 +ddr3_controller.added_read_pipe_max[3:0] +@200 +- +@22 +ddr3_controller.i_aux[15:0] +ddr3_controller.o_aux[15:0] +@200 +- +@22 +ddr3_controller.f_sum_of_pending_acks[31:0] +ddr3_controller.stage1_aux[15:0] +ddr3_controller.stage2_aux[15:0] +ddr3_controller.write_pattern[127:0] +ddr3_controller.read_ack_width[31:0] +ddr3_controller.o_wb_ack_read_q<0>[16:0] +ddr3_controller.o_wb_ack_read_q<1>[16:0] +ddr3_controller.shift_reg_read_pipe_q<0>[16:0] +ddr3_controller.shift_reg_read_pipe_q<1>[16:0] +ddr3_controller.shift_reg_read_pipe_q<2>[16:0] +ddr3_controller.shift_reg_read_pipe_q<3>[16:0] +ddr3_controller.shift_reg_read_pipe_q<4>[16:0] +ddr3_controller.shift_reg_read_pipe_d<0>[16:0] +ddr3_controller.shift_reg_read_pipe_d<1>[16:0] +ddr3_controller.shift_reg_read_pipe_d<2>[16:0] +ddr3_controller.shift_reg_read_pipe_d<3>[16:0] +@200 +- +@28 +ddr3_controller.fifo_1.i_rst_n +ddr3_controller.write_calib_stb +ddr3_controller.write_calib_we +@200 +- +@28 +ddr3_controller.o_wb_stall +ddr3_controller.o_wb_stall_d +ddr3_controller.i_wb_cyc +ddr3_controller.i_wb_stb +ddr3_controller.i_wb_we +@24 +ddr3_controller.o_wb_ack +@200 +- +@24 +ddr3_controller.f_activate_slot[1:0] +ddr3_controller.f_precharge_slot[1:0] +ddr3_controller.f_read_slot[1:0] +ddr3_controller.f_write_slot[1:0] +@28 +ddr3_controller.f_read_fifo +ddr3_controller.f_write_fifo +ddr3_controller.i_wb_cyc +ddr3_controller.f_empty +ddr3_controller.fifo_1.empty +ddr3_controller.f_full +ddr3_controller.write_calib_stb +ddr3_controller.write_calib_we +@200 +- +@24 +ddr3_controller.delay_counter[15:0] ddr3_controller.stage1_bank[2:0] ddr3_controller.stage2_bank[2:0] @28 @@ -302,7 +983,6 @@ ddr3_controller.cmd_odt @24 ddr3_controller.instruction_address[4:0] @28 -ddr3_controller.pipe_stall ddr3_controller.stage1_pending ddr3_controller.stage1_we ddr3_controller.stage2_pending