diff --git a/ddr3_dimm_micron_sim_behav.wcfg b/ddr3_dimm_micron_sim_behav.wcfg
index d4b805f..95527c9 100644
--- a/ddr3_dimm_micron_sim_behav.wcfg
+++ b/ddr3_dimm_micron_sim_behav.wcfg
@@ -11,15 +11,15 @@
-
-
-
+
+
+
-
+
-
+
@@ -28,8 +28,8 @@
-
+
Model File
@@ -263,10 +263,6 @@
stage1_next_bank[2:0]
stage1_next_bank[2:0]
-
- stage1_next_col[9:0]
- stage1_next_col[9:0]
-
stage1_next_row[13:0]
stage1_next_row[13:0]
@@ -304,8 +300,8 @@
state_calibrate[4:0]
- lane[5:0]
- lane[5:0]
+ lane[2:0]
+ lane[2:0]
UNSIGNEDDECRADIX
@@ -484,4 +480,101 @@
o_phy_idelay_dqs_ld[7:0]
+
+ WB2 Registers
+ label
+
+
+ i_controller_clk
+ i_controller_clk
+
+
+ state_calibrate[4:0]
+ state_calibrate[4:0]
+
+
+ instruction_address[4:0]
+ instruction_address[4:0]
+
+
+ added_read_pipe_max[3:0]
+ added_read_pipe_max[3:0]
+
+
+ added_read_pipe[7:0][3:0]
+ added_read_pipe[7:0][3:0]
+
+
+ dqs_store[39:0]
+ dqs_store[39:0]
+
+
+ i_phy_iserdes_bitslip_reference[63:0]
+ i_phy_iserdes_bitslip_reference[63:0]
+
+
+ read_data_store[511:0]
+ read_data_store[511:0]
+
+
+ write_pattern[127:0]
+ write_pattern[127:0]
+
+
+ odelay_data_cntvaluein[7:0][4:0]
+ odelay_data_cntvaluein[7:0][4:0]
+ UNSIGNEDDECRADIX
+
+
+ odelay_dqs_cntvaluein[7:0][4:0]
+ odelay_dqs_cntvaluein[7:0][4:0]
+ UNSIGNEDDECRADIX
+
+
+ idelay_data_cntvaluein[7:0][4:0]
+ idelay_data_cntvaluein[7:0][4:0]
+ UNSIGNEDDECRADIX
+
+
+ idelay_dqs_cntvaluein[7:0][4:0]
+ idelay_dqs_cntvaluein[7:0][4:0]
+ UNSIGNEDDECRADIX
+
+
+ i_wb2_addr[31:0]
+ i_wb2_addr[31:0]
+ BINARYRADIX
+
+
+ i_wb2_cyc
+ i_wb2_cyc
+
+
+ i_wb2_data[31:0]
+ i_wb2_data[31:0]
+
+
+ i_wb2_sel[3:0]
+ i_wb2_sel[3:0]
+
+
+ i_wb2_stb
+ i_wb2_stb
+
+
+ i_wb2_we
+ i_wb2_we
+
+
+ o_wb2_ack
+ o_wb2_ack
+
+
+ o_wb2_data[31:0]
+ o_wb2_data[31:0]
+
+
+ o_wb2_stall
+ o_wb2_stall
+