diff --git a/testbench/ddr3_dimm_micron_sim_behav.wcfg b/testbench/ddr3_dimm_micron_sim_behav.wcfg index d951913..6d83606 100644 --- a/testbench/ddr3_dimm_micron_sim_behav.wcfg +++ b/testbench/ddr3_dimm_micron_sim_behav.wcfg @@ -11,52 +11,22 @@ - - - + + + - + - - - - - - - - - - - - - - - + - Model File + Clocks and Reset label - - sync_rst - sync_rst - - - o_controller_idelayctrl_rdy - o_controller_idelayctrl_rdy - - - idelayctrl_rdy - idelayctrl_rdy - - - dci_locked - dci_locked - - - clk_locked - clk_locked + + i_rst_n + i_rst_n i_controller_clk @@ -74,75 +44,9 @@ i_ref_clk i_ref_clk - - i_rst_n - i_rst_n - - - i_wb_cyc - i_wb_cyc - - - i_wb_stb - i_wb_stb - - - o_aux[15:0] - o_aux[15:0] - BINARYRADIX - - - i_aux[15:0] - i_aux[15:0] - BINARYRADIX - - - o_wb_ack - o_wb_ack - - - i_wb_sel[63:0] - i_wb_sel[63:0] - - - o_ddr3_dm[7:0] - o_ddr3_dm[7:0] - - - - i_wb_we - i_wb_we - - - i_wb_addr[25:0] - i_wb_addr[25:0] - - - i_wb_data[511:0] - i_wb_data[511:0] - - - o_wb_stall - o_wb_stall - - - o_wb_data[511:0] - o_wb_data[511:0] - HEXRADIX - - - o_wb_data_q[1:0][511:0] - o_wb_data_q[1:0][511:0] - HEXRADIX - - - - ck_en[1:0] - ck_en[1:0] - - - odt[1:0] - odt[1:0] + + Internal Logic + label command_used[23:0] @@ -151,1294 +55,139 @@ #FFD700 true - - cs_n[1:0] - cs_n[1:0] - - - - ras_n - ras_n - - - cas_n - cas_n - - - we_n - we_n - - - reset_n - reset_n - - - addr[15:0] - addr[15:0] - - - ba_addr[2:0] - ba_addr[2:0] - UNSIGNEDDECRADIX - - - o_ddr3_odt - o_ddr3_odt - - - i_controller_dqs_tri_control - i_controller_dqs_tri_control - - - i_controller_dq_tri_control - i_controller_dq_tri_control - - - i_controller_dqs_tri_control - i_controller_dqs_tri_control - - - i_controller_dq_tri_control - i_controller_dq_tri_control - - - i_controller_clk - i_controller_clk - - - i_ddr3_clk - i_ddr3_clk - - - i_ddr3_clk_90 - i_ddr3_clk_90 - - - dqs_n[7:0] - dqs_n[7:0] - - - lane[2:0] - lane[2:0] - UNSIGNEDDECRADIX - - - read_lane_data[63:0] - read_lane_data[63:0] - HEXRADIX - - - o_ddr3_clk_p - o_ddr3_clk_p - #FF00FF - true - - - o_ddr3_clk_n - o_ddr3_clk_n - #FF00FF - true - instruction_address[4:0] instruction_address[4:0] UNSIGNEDDECRADIX - - stage1_pending - stage1_pending - - - stage2_pending - stage2_pending - - - read_data_store[511:0] - read_data_store[511:0] - HEXRADIX - - - o_wb_data[511:0] - o_wb_data[511:0] - HEXRADIX - - - i_controller_data[511:0] - i_controller_data[511:0] - HEXRADIX - - - oserdes_data[63:0] - oserdes_data[63:0] - HEXRADIX - - - i_controller_toggle_dqs - i_controller_toggle_dqs - - - toggle_dqs_q - toggle_dqs_q - - - read_lane_data[63:0] - read_lane_data[63:0] - HEXRADIX - - - test - label - - - cmd_odt_q - cmd_odt_q - - - cmd_odt - cmd_odt - - - write_calib_odt - write_calib_odt - - - i_controller_clk - i_controller_clk - - - stage2_pending - stage2_pending - - - stage2_we - stage2_we - - - stage2_col[9:0] - stage2_col[9:0] - UNSIGNEDDECRADIX - - - stage2_bank[2:0] - stage2_bank[2:0] - UNSIGNEDDECRADIX - - - stage2_row[15:0] - stage2_row[15:0] - UNSIGNEDDECRADIX - - - delay_before_write_counter_q[7:0][3:0] - delay_before_write_counter_q[7:0][3:0] - - - delay_before_write_counter_d[7:0][3:0] - delay_before_write_counter_d[7:0][3:0] - - - ba_addr[2:0] - ba_addr[2:0] - UNSIGNEDDECRADIX - - - addr[15:0] - addr[15:0] - UNSIGNEDDECRADIX - - - label - [0] - [0] - cs - #FF0080 - true - - - stage1_pending - stage1_pending - - - stage2_pending - stage2_pending - - - cmd_d[3:0][25:0] - cmd_d[3:0][25:0] - BINARYRADIX - - - [3][25:0] - [3][25:0] - BINARYRADIX - - - [2][25:0] - [2][25:0] - BINARYRADIX - - - [1][25:0] - [1][25:0] - BINARYRADIX - - - [0][25:0] - [0][25:0] - BINARYRADIX - - - [3][25:0] - [3][25:0] - - - [2][25:0] - [2][25:0] - - - [1][25:0] - [1][25:0] - - - [0][25:0] - [0][25:0] - - - - stage2_update - stage2_update - - - o_ddr3_cs_n - o_ddr3_cs_n - - - instruction_address[4:0] - instruction_address[4:0] - UNSIGNEDDECRADIX - - - command_used[23:0] - command_used[23:0] - ASCIIRADIX - #FFD700 - true - - - calib_addr[25:0] - calib_addr[25:0] - UNSIGNEDDECRADIX - - - stage1_col[9:0] - stage1_col[9:0] - UNSIGNEDDECRADIX - - - stage2_col[9:0] - stage2_col[9:0] - UNSIGNEDDECRADIX - - - o_wb_stall_q - o_wb_stall_q - - - stage2_stall - stage2_stall - - - stage1_stall - stage1_stall - - - o_wb_stall - o_wb_stall - - - o_phy_dqs_tri_control - o_phy_dqs_tri_control - - - o_phy_dq_tri_control - o_phy_dq_tri_control - - - cmd_odt - cmd_odt - - - i_controller_clk - i_controller_clk - - - o_ddr3_odt - o_ddr3_odt - - - o_ddr3_clk_p - o_ddr3_clk_p - - - dqs[7:0] - dqs[7:0] - - - - dq[63:0] - dq[63:0] - HEXRADIX - - - o_wb_data[511:0] - o_wb_data[511:0] - HEXRADIX - #FF00FF - true - - - read_data_store[511:0] - read_data_store[511:0] - HEXRADIX - - - o_aux[15:0] - o_aux[15:0] - #800080 - true - - - lane[2:0] - lane[2:0] - UNSIGNEDDECRADIX - state_calibrate[5:0] state_calibrate[5:0] UNSIGNEDDECRADIX - - o_wb_stall_q - o_wb_stall_q - - - o_wb_stall - o_wb_stall - - - o_wb2_stall - o_wb2_stall - - - stage2_stall - stage2_stall - - - stage1_stall - stage1_stall - - - o_wb_stall_d - o_wb_stall_d - - - calib_stb - calib_stb - #FFA500 - true - - - i_wb_stb - i_wb_stb - #FFA500 - true - - - calib_aux[15:0] - calib_aux[15:0] - - - calib_we - calib_we - - - calib_data[511:0] - calib_data[511:0] + + lane[0:0] + lane[0:0] + UNSIGNEDDECRADIX read_test_address_counter[25:0] read_test_address_counter[25:0] + UNSIGNEDDECRADIX - write_test_address_counter[25:0] - write_test_address_counter[25:0] - - - check_test_address_counter[25:0] - check_test_address_counter[25:0] + write_test_address_counter[31:0] + write_test_address_counter[31:0] + UNSIGNEDDECRADIX correct_read_data[31:0] correct_read_data[31:0] + UNSIGNEDDECRADIX wrong_read_data[31:0] wrong_read_data[31:0] + UNSIGNEDDECRADIX - - bank track + + WIshbone Interface label - - state_calibrate[5:0] - state_calibrate[5:0] + + i_wb_cyc + i_wb_cyc - - read_data_store[511:0] - read_data_store[511:0] - HEXRADIX + + i_wb_stb + i_wb_stb - - delay_before_read_counter_q[7:0][3:0] - delay_before_read_counter_q[7:0][3:0] + + i_wb_we + i_wb_we - - delay_before_precharge_counter_q[7:0][3:0] - delay_before_precharge_counter_q[7:0][3:0] + + i_wb_addr[25:0] + i_wb_addr[25:0] - - delay_before_activate_counter_q[7:0][3:0] - delay_before_activate_counter_q[7:0][3:0] + + i_wb_data[127:0] + i_wb_data[127:0] - - delay_before_write_counter_q[7:0][3:0] - delay_before_write_counter_q[7:0][3:0] + + i_wb_sel[15:0] + i_wb_sel[15:0] - - bank_status_q[7:0] - bank_status_q[7:0] + + o_wb_stall + o_wb_stall - - bank_active_row_q[7:0][15:0] - bank_active_row_q[7:0][15:0] + + o_wb_ack + o_wb_ack - - stage1_pending - stage1_pending + + o_wb_data[127:0] + o_wb_data[127:0] - - stage2_pending - stage2_pending - - - stage1_we - stage1_we - - - stage2_we - stage2_we - - - o_wb_ack_read_q[15:0][16:0] - o_wb_ack_read_q[15:0][16:0] - - - o_wb_stall_q - o_wb_stall_q - - - stage1_aux[15:0] - stage1_aux[15:0] - - - stage1_bank[2:0] - stage1_bank[2:0] - - - stage1_next_bank[2:0] - stage1_next_bank[2:0] - - - stage1_next_row[15:0] - stage1_next_row[15:0] - - - idelay_data_cntvaluein[7:0][4:0] - idelay_data_cntvaluein[7:0][4:0] - - - [7][4:0] - [7][4:0] - UNSIGNEDDECRADIX - - - [6][4:0] - [6][4:0] - UNSIGNEDDECRADIX - - - [5][4:0] - [5][4:0] - UNSIGNEDDECRADIX - - - [4][4:0] - [4][4:0] - UNSIGNEDDECRADIX - - - [3][4:0] - [3][4:0] - UNSIGNEDDECRADIX - - - [2][4:0] - [2][4:0] - UNSIGNEDDECRADIX - - - [1][4:0] - [1][4:0] - UNSIGNEDDECRADIX - - - [0][4:0] - [0][4:0] - UNSIGNEDDECRADIX - - - - idelay_data_cntvaluein_prev[4:0] - idelay_data_cntvaluein_prev[4:0] - - - - idelay_dqs_cntvaluein[7:0][4:0] - idelay_dqs_cntvaluein[7:0][4:0] - UNSIGNEDDECRADIX - - - [7][4:0] - [7][4:0] - UNSIGNEDDECRADIX - - - [6][4:0] - [6][4:0] - UNSIGNEDDECRADIX - - - [5][4:0] - [5][4:0] - UNSIGNEDDECRADIX - - - [4][4:0] - [4][4:0] - UNSIGNEDDECRADIX - - - [3][4:0] - [3][4:0] - UNSIGNEDDECRADIX - - - [2][4:0] - [2][4:0] - UNSIGNEDDECRADIX - - - [1][4:0] - [1][4:0] - UNSIGNEDDECRADIX - - - [0][4:0] - [0][4:0] - UNSIGNEDDECRADIX - - - - stage1_stall - stage1_stall - - - stage1_we - stage1_we - - - stage2_aux[15:0] - stage2_aux[15:0] - - - stage2_bank[2:0] - stage2_bank[2:0] - - - stage2_stall - stage2_stall - - - stage2_update - stage2_update - - - DDR3 Controller + + DDR3 Interface label - - prev_write_level_feedback - prev_write_level_feedback + + o_ddr3_cke + o_ddr3_cke - - state_calibrate[5:0] - state_calibrate[5:0] + + o_ddr3_cs_n + o_ddr3_cs_n - - delay_before_write_level_feedback[4:0] - delay_before_write_level_feedback[4:0] - UNSIGNEDDECRADIX + + o_ddr3_ras_n + o_ddr3_ras_n - - lane[2:0] - lane[2:0] - UNSIGNEDDECRADIX - + + o_ddr3_cas_n + o_ddr3_cas_n - - instruction_address[4:0] - instruction_address[4:0] - UNSIGNEDDECRADIX + + o_ddr3_we_n + o_ddr3_we_n - - dqs_store[39:0] - dqs_store[39:0] - BINARYRADIX + + o_ddr3_addr[15:0] + o_ddr3_addr[15:0] - - dqs_start_index[5:0] - dqs_start_index[5:0] - UNSIGNEDDECRADIX + + o_ddr3_ba_addr[2:0] + o_ddr3_ba_addr[2:0] - - dqs_target_index[5:0] - dqs_target_index[5:0] - UNSIGNEDDECRADIX + + io_ddr3_dq[15:0] + io_ddr3_dq[15:0] - - dq_target_index[7:0][5:0] - dq_target_index[7:0][5:0] - UNSIGNEDDECRADIX + + io_ddr3_dqs[1:0] + io_ddr3_dqs[1:0] - - dqs_target_index_orig[5:0] - dqs_target_index_orig[5:0] + + io_ddr3_dqs_n[1:0] + io_ddr3_dqs_n[1:0] - - dqs_start_index_repeat[0:0] - dqs_start_index_repeat[0:0] + + o_ddr3_dm[1:0] + o_ddr3_dm[1:0] - - i_phy_iserdes_data[511:0] - i_phy_iserdes_data[511:0] - HEXRADIX + + o_ddr3_odt + o_ddr3_odt - - data_start_index[7:0][6:0] - data_start_index[7:0][6:0] + + o_ddr3_debug_read_dqs_p[1:0] + o_ddr3_debug_read_dqs_p[1:0] - - [56] - [56] - - - [48] - [48] - - - [32] - [32] - - - [40] - [40] - - - [24] - [24] - - - [16] - [16] - - - [8] - [8] - - - [0] - [0] - - - i_phy_iserdes_dqs[63:0] - i_phy_iserdes_dqs[63:0] - BINARYRADIX - - - i_phy_iserdes_dqs[63:0] - i_phy_iserdes_dqs[63:0] - BINARYRADIX - - - i_phy_iserdes_dqs_lane2 - label - BINARYRADIX - - [15] - [15] - - - [14] - [14] - - - [13] - [13] - - - [12] - [12] - - - [11] - [11] - - - [10] - [10] - - - [9] - [9] - - - [8] - [8] - - - - lane0 - label - BINARYRADIX - - [7] - [7] - - - [6] - [6] - - - [5] - [5] - - - [4] - [4] - - - [3] - [3] - - - [2] - [2] - - - [1] - [1] - - - [0] - [0] - - - - i_phy_iserdes_dqs_lane1 - label - BINARYRADIX - #FF00FF - true - - [15] - [15] - - - [14] - [14] - - - [13] - [13] - - - [12] - [12] - - - [11] - [11] - - - [10] - [10] - - - [9] - [9] - - - [8] - [8] - - - - i_phy_iserdes_dqs_lane0 - label - BINARYRADIX - #FF00FF - true - - [7] - [7] - - - [6] - [6] - - - [5] - [5] - - - [4] - [4] - - - [3] - [3] - - - [2] - [2] - - - [1] - [1] - - - [0] - [0] - - - - data_lane01 - label - BINARYRADIX - true - VirtualBus[] - VirtualBus[] - - [0] - [0] - - - [1] - [1] - - - [64] - [64] - - - [65] - [65] - - - - i_phy_iserdes_bitslip_reference[63:0] - i_phy_iserdes_bitslip_reference[63:0] - BINARYRADIX - - - i_phy_idelayctrl_rdy - i_phy_idelayctrl_rdy - - - idelay_dqs[7:0] - idelay_dqs[7:0] - - - - i_controller_clk - i_controller_clk - - - i_ddr3_clk - i_ddr3_clk - - - idelay_data[63:0] - idelay_data[63:0] - HEXRADIX - - - odelay_data[63:0] - odelay_data[63:0] - ASCIIRADIX - - - odelay_dqs[7:0] - odelay_dqs[7:0] - HEXRADIX - - - i_controller_bitslip[7:0] - i_controller_bitslip[7:0] - - - o_controller_iserdes_dqs[63:0] - o_controller_iserdes_dqs[63:0] - BINARYRADIX - - - i_phy_iserdes_dqs[63:0] - i_phy_iserdes_dqs[63:0] - BINARYRADIX - - - train_delay[3:0] - train_delay[3:0] - - - i_phy_iserdes_bitslip_reference[63:0] - i_phy_iserdes_bitslip_reference[63:0] - BINARYRADIX - - - i_phy_iserdes_bitref_lane1 - label - BINARYRADIX - - [15] - [15] - - - [14] - [14] - - - [13] - [13] - - - [12] - [12] - - - [11] - [11] - - - [10] - [10] - - - [9] - [9] - - - [8] - [8] - - - - i_phy_iserdes_bitref_lane0 - label - BINARYRADIX - - [7] - [7] - - - [6] - [6] - - - [5] - [5] - - - [4] - [4] - - - [3] - [3] - - - [2] - [2] - - - [1] - [1] - - - [0] - [0] - - - - i_controller_bitslip[7:0] - i_controller_bitslip[7:0] - - - - CMD - label - - - i_controller_clk - i_controller_clk - - - i_ddr3_clk - i_ddr3_clk - - - cmd_d[3:0][25:0] - cmd_d[3:0][25:0] - - BINARYRADIX - - - label - [23] - [23] - oserdes - - - label - [23] - [23] - cmd - - - DQS - label - - - write_dqs_d - write_dqs_d - - - write_dqs[2:0] - write_dqs[2:0] - BINARYRADIX - #00FF00 - true - - - write_dqs_val[2:0] - write_dqs_val[2:0] - BINARYRADIX - #FFA500 - true - - - oserdes_dqs[7:0] - oserdes_dqs[7:0] - - - odelay_dqs[7:0] - odelay_dqs[7:0] - HEXRADIX - - - - DELAYS - label - - - o_phy_odelay_data_cntvaluein[4:0] - o_phy_odelay_data_cntvaluein[4:0] - UNSIGNEDDECRADIX - - - o_phy_odelay_dqs_cntvaluein[4:0] - o_phy_odelay_dqs_cntvaluein[4:0] - UNSIGNEDDECRADIX - - - o_phy_idelay_data_cntvaluein[4:0] - o_phy_idelay_data_cntvaluein[4:0] - UNSIGNEDDECRADIX - - - idelay_data_cntvaluein_prev[4:0] - idelay_data_cntvaluein_prev[4:0] - UNSIGNEDDECRADIX - - - o_phy_idelay_dqs_cntvaluein[4:0] - o_phy_idelay_dqs_cntvaluein[4:0] - UNSIGNEDDECRADIX - - - o_phy_odelay_data_ld[7:0] - o_phy_odelay_data_ld[7:0] - - - o_phy_odelay_dqs_ld[7:0] - o_phy_odelay_dqs_ld[7:0] - - - o_phy_idelay_data_ld[7:0] - o_phy_idelay_data_ld[7:0] - - - - o_phy_idelay_dqs_ld[7:0] - o_phy_idelay_dqs_ld[7:0] - - - - WB2 Registers - label - - - dqs_target_index[5:0] - dqs_target_index[5:0] - - - dqs_target_index_orig[5:0] - dqs_target_index_orig[5:0] - - - dq_target_index[7:0][5:0] - dq_target_index[7:0][5:0] - - - dqs_target_index_value[5:0] - dqs_target_index_value[5:0] - - - i_phy_iserdes_dqs[63:0] - i_phy_iserdes_dqs[63:0] - BINARYRADIX - - - o_phy_dq_tri_control - o_phy_dq_tri_control - - - o_phy_dqs_tri_control - o_phy_dqs_tri_control - - - i_controller_clk - i_controller_clk - - - state_calibrate[5:0] - state_calibrate[5:0] - - - instruction_address[4:0] - instruction_address[4:0] - - - added_read_pipe_max[3:0] - added_read_pipe_max[3:0] - - - added_read_pipe[7:0][3:0] - added_read_pipe[7:0][3:0] - - - dqs_store[39:0] - dqs_store[39:0] - - - i_phy_iserdes_bitslip_reference[63:0] - i_phy_iserdes_bitslip_reference[63:0] - - - read_data_store[511:0] - read_data_store[511:0] - - - write_pattern[127:0] - write_pattern[127:0] - - - odelay_data_cntvaluein[7:0][4:0] - odelay_data_cntvaluein[7:0][4:0] - UNSIGNEDDECRADIX - - - odelay_dqs_cntvaluein[7:0][4:0] - odelay_dqs_cntvaluein[7:0][4:0] - UNSIGNEDDECRADIX - - - idelay_data_cntvaluein[7:0][4:0] - idelay_data_cntvaluein[7:0][4:0] - UNSIGNEDDECRADIX - - - - idelay_dqs_cntvaluein[7:0][4:0] - idelay_dqs_cntvaluein[7:0][4:0] - UNSIGNEDDECRADIX - - - - i_wb2_addr[31:0] - i_wb2_addr[31:0] - BINARYRADIX - - - i_wb2_cyc - i_wb2_cyc - - - i_wb2_data[31:0] - i_wb2_data[31:0] - - - i_wb2_sel[3:0] - i_wb2_sel[3:0] - - - i_wb2_stb - i_wb2_stb - - - i_wb2_we - i_wb2_we - - - o_wb2_ack - o_wb2_ack - - - o_wb2_data[31:0] - o_wb2_data[31:0] - - - o_wb2_stall - o_wb2_stall + + o_ddr3_debug_read_dqs_n[1:0] + o_ddr3_debug_read_dqs_n[1:0]