From b2fd0bf4fe4796c3728f0a5288a04087cc8e8b64 Mon Sep 17 00:00:00 2001
From: AngeloJacobo <jacobo.angeloECE@gmail.com>
Date: Thu, 13 Jul 2023 19:18:35 +0800
Subject: [PATCH] add formal gtkw files

---
 formal.gtkw     | 582 ++++++++++++++++++++++++++++++++++++++++++++++++
 formal_wb2.gtkw | 163 ++++++++++++++
 2 files changed, 745 insertions(+)
 create mode 100644 formal.gtkw
 create mode 100644 formal_wb2.gtkw

diff --git a/formal.gtkw b/formal.gtkw
new file mode 100644
index 0000000..1d42c88
--- /dev/null
+++ b/formal.gtkw
@@ -0,0 +1,582 @@
+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Sun Jul  9 01:37:07 2023
+[*]
+[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd"
+[dumpfile_mtime] "Sun Jul  9 01:34:04 2023"
+[dumpfile_size] 114453
+[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal_cover_3.gtkw"
+[timestart] 0
+[size] 1848 1126
+[pos] -1 -1
+*-5.075655 63 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddr3_controller.
+[treeopen] ddr3_controller.wb_properties.
+[sst_width] 391
+[signals_width] 541
+[sst_expanded] 1
+[sst_vpaned_height] 743
+@420
+smt_step
+@28
+ddr3_controller.i_controller_clk
+ddr3_controller.i_rst_n
+ddr3_controller.reset_done
+@24
+ddr3_controller.state_calibrate[4:0]
+ddr3_controller.instruction_address[4:0]
+ddr3_controller.delay_counter[15:0]
+@28
+ddr3_controller.o_wb_stall_q
+ddr3_controller.i_wb_cyc
+@200
+-
+@28
+ddr3_controller.f_read_fifo
+ddr3_controller.f_write_fifo
+ddr3_controller.o_wb_stall
+ddr3_controller.i_wb_stb
+ddr3_controller.stage1_pending
+ddr3_controller.stage2_pending
+@200
+-
+@28
++{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
+@c00028
++{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
+@28
+(0)ddr3_controller.cmd_d<1>[23:0]
+(1)ddr3_controller.cmd_d<1>[23:0]
+(2)ddr3_controller.cmd_d<1>[23:0]
+(3)ddr3_controller.cmd_d<1>[23:0]
+(4)ddr3_controller.cmd_d<1>[23:0]
+(5)ddr3_controller.cmd_d<1>[23:0]
+(6)ddr3_controller.cmd_d<1>[23:0]
+(7)ddr3_controller.cmd_d<1>[23:0]
+(8)ddr3_controller.cmd_d<1>[23:0]
+(9)ddr3_controller.cmd_d<1>[23:0]
+(10)ddr3_controller.cmd_d<1>[23:0]
+(11)ddr3_controller.cmd_d<1>[23:0]
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+(13)ddr3_controller.cmd_d<1>[23:0]
+(14)ddr3_controller.cmd_d<1>[23:0]
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+(16)ddr3_controller.cmd_d<1>[23:0]
+(17)ddr3_controller.cmd_d<1>[23:0]
+(18)ddr3_controller.cmd_d<1>[23:0]
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+(21)ddr3_controller.cmd_d<1>[23:0]
+(22)ddr3_controller.cmd_d<1>[23:0]
+(23)ddr3_controller.cmd_d<1>[23:0]
+@1401200
+-group_end
+@c00028
++{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
+@28
+(0)ddr3_controller.cmd_d<2>[23:0]
+(1)ddr3_controller.cmd_d<2>[23:0]
+(2)ddr3_controller.cmd_d<2>[23:0]
+(3)ddr3_controller.cmd_d<2>[23:0]
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+(6)ddr3_controller.cmd_d<2>[23:0]
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+(14)ddr3_controller.cmd_d<2>[23:0]
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+(22)ddr3_controller.cmd_d<2>[23:0]
+(23)ddr3_controller.cmd_d<2>[23:0]
+@1401200
+-group_end
+@28
++{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
+ddr3_controller.stage1_issue_command
+ddr3_controller.stage2_issue_command
+@200
+-
+@22
+ddr3_controller.delay_before_activate_counter_q<1>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
+ddr3_controller.delay_before_read_counter_q<1>[3:0]
+ddr3_controller.delay_before_write_counter_q<1>[3:0]
+@200
+-
+@24
+ddr3_controller.stage1_bank[2:0]
+ddr3_controller.stage2_bank[2:0]
+@c00024
+ddr3_controller.stage1_next_bank[2:0]
+@28
+(0)ddr3_controller.stage1_next_bank[2:0]
+(1)ddr3_controller.stage1_next_bank[2:0]
+(2)ddr3_controller.stage1_next_bank[2:0]
+@1401200
+-group_end
+@200
+-
+@24
+ddr3_controller.f_sum_of_pending_acks[15:0]
+ddr3_controller.wb_properties.f_ackwait_count[3:0]
+@28
+ddr3_controller.f_ack_pipe_after_stage2[6:0]
+@22
+ddr3_controller.f_stall_count[4:0]
+@28
+ddr3_controller.delay_counter_is_zero
+ddr3_controller.write_calib_stb
+ddr3_controller.write_calib_we
+@200
+-
+@28
+ddr3_controller.stage1_pending
+ddr3_controller.stage2_pending
+ddr3_controller.shift_reg_read_pipe_q<4>[16:0]
+ddr3_controller.shift_reg_read_pipe_q<3>[16:0]
+@c00028
+ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+@28
+(0)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(1)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(2)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(3)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(4)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(5)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(6)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(7)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(8)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(9)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(10)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(11)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(12)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(13)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(14)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(15)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+(16)ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+@1401200
+-group_end
+@c00028
+ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+@28
+(0)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(1)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(2)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(3)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(4)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(5)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(6)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(7)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(8)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(9)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(10)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(11)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(12)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(13)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(14)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(15)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+(16)ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+@1401200
+-group_end
+@28
+ddr3_controller.shift_reg_read_pipe_q<0>[16:0]
+@22
+ddr3_controller.o_wb_ack_read_q<1>[16:0]
+ddr3_controller.o_wb_ack_read_q<0>[16:0]
+@200
+-
+@28
+ddr3_controller.f_bank_status[7:0]
+ddr3_controller.bank_status_q[7:0]
+@22
+ddr3_controller.bank[31:0]
+@200
+-
+@22
+ddr3_controller.bank[31:0]
+@200
+-
+@28
+ddr3_controller.fifo_1.read_pointer
+ddr3_controller.fifo_1.write_pointer
+@24
+ddr3_controller.wb_properties.f_outstanding[3:0]
+ddr3_controller.f_sum_of_pending_acks[15:0]
+@28
+ddr3_controller.wb_properties.i_wb_cyc
+@200
+-
+@28
+ddr3_controller.wb_properties.i_slave_busy
+ddr3_controller.i_wb_stb
+ddr3_controller.o_wb_stall
+ddr3_controller.i_wb_cyc
+ddr3_controller.o_wb_ack
+ddr3_controller.o_wb_stall_d
+ddr3_controller.o_wb_stall_q
+ddr3_controller.delay_counter_is_zero
+@200
+-
+@28
+ddr3_controller.stage1_stall
+ddr3_controller.stage1_pending
+ddr3_controller.stage1_we
+@22
+ddr3_controller.stage1_aux[15:0]
+@24
+ddr3_controller.stage1_bank[2:0]
+@22
+ddr3_controller.stage1_col[9:0]
+ddr3_controller.stage1_row[13:0]
+@200
+-
+@28
+ddr3_controller.stage2_stall
+ddr3_controller.stage2_pending
+ddr3_controller.stage2_update
+ddr3_controller.stage2_we
+@c00022
+ddr3_controller.stage2_aux[15:0]
+@28
+(0)ddr3_controller.stage2_aux[15:0]
+(1)ddr3_controller.stage2_aux[15:0]
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+(7)ddr3_controller.stage2_aux[15:0]
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+(13)ddr3_controller.stage2_aux[15:0]
+(14)ddr3_controller.stage2_aux[15:0]
+(15)ddr3_controller.stage2_aux[15:0]
+@1401200
+-group_end
+@24
+ddr3_controller.stage2_bank[2:0]
+@22
+ddr3_controller.stage2_col[9:0]
+ddr3_controller.stage2_row[13:0]
+@200
+-
+@28
++{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
+@c00028
++{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
+@28
+(0)ddr3_controller.cmd_d<1>[23:0]
+(1)ddr3_controller.cmd_d<1>[23:0]
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+(10)ddr3_controller.cmd_d<1>[23:0]
+(11)ddr3_controller.cmd_d<1>[23:0]
+(12)ddr3_controller.cmd_d<1>[23:0]
+(13)ddr3_controller.cmd_d<1>[23:0]
+(14)ddr3_controller.cmd_d<1>[23:0]
+(15)ddr3_controller.cmd_d<1>[23:0]
+(16)ddr3_controller.cmd_d<1>[23:0]
+(17)ddr3_controller.cmd_d<1>[23:0]
+(18)ddr3_controller.cmd_d<1>[23:0]
+(19)ddr3_controller.cmd_d<1>[23:0]
+(20)ddr3_controller.cmd_d<1>[23:0]
+(21)ddr3_controller.cmd_d<1>[23:0]
+(22)ddr3_controller.cmd_d<1>[23:0]
+(23)ddr3_controller.cmd_d<1>[23:0]
+@1401200
+-group_end
+@c00028
++{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
+@28
+(0)ddr3_controller.cmd_d<2>[23:0]
+(1)ddr3_controller.cmd_d<2>[23:0]
+(2)ddr3_controller.cmd_d<2>[23:0]
+(3)ddr3_controller.cmd_d<2>[23:0]
+(4)ddr3_controller.cmd_d<2>[23:0]
+(5)ddr3_controller.cmd_d<2>[23:0]
+(6)ddr3_controller.cmd_d<2>[23:0]
+(7)ddr3_controller.cmd_d<2>[23:0]
+(8)ddr3_controller.cmd_d<2>[23:0]
+(9)ddr3_controller.cmd_d<2>[23:0]
+(10)ddr3_controller.cmd_d<2>[23:0]
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+(15)ddr3_controller.cmd_d<2>[23:0]
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+(20)ddr3_controller.cmd_d<2>[23:0]
+(21)ddr3_controller.cmd_d<2>[23:0]
+(22)ddr3_controller.cmd_d<2>[23:0]
+(23)ddr3_controller.cmd_d<2>[23:0]
+@1401200
+-group_end
+@28
++{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
+@200
+-
+@24
+ddr3_controller.wb_properties.f_nacks[3:0]
+ddr3_controller.wb_properties.f_nreqs[3:0]
+@28
+ddr3_controller.stage2_update
+@200
+-
+-
+@22
+ddr3_controller.f_aux_ack_pipe_after_stage2<0>[16:0]
+ddr3_controller.f_aux_ack_pipe_after_stage2<1>[16:0]
+ddr3_controller.f_aux_ack_pipe_after_stage2<2>[16:0]
+ddr3_controller.f_aux_ack_pipe_after_stage2<3>[16:0]
+ddr3_controller.f_aux_ack_pipe_after_stage2<4>[16:0]
+ddr3_controller.f_aux_ack_pipe_after_stage2<5>[16:0]
+ddr3_controller.f_aux_ack_pipe_after_stage2<6>[16:0]
+@200
+-
+@22
+ddr3_controller.o_wb_ack_read_q<2>[16:0]
+ddr3_controller.o_wb_ack_read_q<3>[16:0]
+ddr3_controller.o_wb_ack_read_q<4>[16:0]
+ddr3_controller.o_wb_ack_read_q<5>[16:0]
+ddr3_controller.o_wb_ack_read_q<6>[16:0]
+ddr3_controller.o_wb_ack_read_q<7>[16:0]
+ddr3_controller.o_wb_ack_read_q<8>[16:0]
+ddr3_controller.o_wb_ack_read_q<9>[16:0]
+ddr3_controller.o_wb_ack_read_q<10>[16:0]
+ddr3_controller.o_wb_ack_read_q<11>[16:0]
+ddr3_controller.o_wb_ack_read_q<12>[16:0]
+ddr3_controller.o_wb_ack_read_q<13>[16:0]
+ddr3_controller.o_wb_ack_read_q<14>[16:0]
+ddr3_controller.o_wb_ack_read_q<15>[16:0]
+@24
+ddr3_controller.added_read_pipe_max[3:0]
+@28
+ddr3_controller.o_wb_ack
+@200
+-
+@28
+ddr3_controller.o_wb_ack
+ddr3_controller.fifo_1.empty
+ddr3_controller.fifo_1.full
+ddr3_controller.fifo_1.empty
+ddr3_controller.fifo_1.full
+ddr3_controller.fifo_1.read_fifo
+ddr3_controller.fifo_1.write_fifo
+ddr3_controller.fifo_1.read_pointer
+ddr3_controller.fifo_1.write_pointer
+@200
+-
+@24
+ddr3_controller.added_read_pipe_max[3:0]
+@200
+-
+@22
+ddr3_controller.i_aux[15:0]
+ddr3_controller.o_aux[15:0]
+@200
+-
+@22
+ddr3_controller.stage1_aux[15:0]
+ddr3_controller.stage2_aux[15:0]
+ddr3_controller.write_pattern[127:0]
+ddr3_controller.read_ack_width[31:0]
+ddr3_controller.o_wb_ack_read_q<0>[16:0]
+ddr3_controller.o_wb_ack_read_q<1>[16:0]
+ddr3_controller.shift_reg_read_pipe_q<0>[16:0]
+ddr3_controller.shift_reg_read_pipe_q<1>[16:0]
+ddr3_controller.shift_reg_read_pipe_q<2>[16:0]
+ddr3_controller.shift_reg_read_pipe_q<3>[16:0]
+ddr3_controller.shift_reg_read_pipe_q<4>[16:0]
+ddr3_controller.shift_reg_read_pipe_d<0>[16:0]
+ddr3_controller.shift_reg_read_pipe_d<1>[16:0]
+ddr3_controller.shift_reg_read_pipe_d<2>[16:0]
+ddr3_controller.shift_reg_read_pipe_d<3>[16:0]
+@200
+-
+@28
+ddr3_controller.fifo_1.i_rst_n
+ddr3_controller.write_calib_stb
+ddr3_controller.write_calib_we
+@200
+-
+@28
+ddr3_controller.o_wb_stall
+ddr3_controller.o_wb_stall_d
+ddr3_controller.i_wb_cyc
+ddr3_controller.i_wb_stb
+ddr3_controller.i_wb_we
+@24
+ddr3_controller.o_wb_ack
+@200
+-
+@24
+ddr3_controller.f_activate_slot[1:0]
+ddr3_controller.f_precharge_slot[1:0]
+ddr3_controller.f_read_slot[1:0]
+ddr3_controller.f_write_slot[1:0]
+@28
+ddr3_controller.f_read_fifo
+ddr3_controller.f_write_fifo
+ddr3_controller.i_wb_cyc
+ddr3_controller.f_empty
+ddr3_controller.fifo_1.empty
+ddr3_controller.f_full
+ddr3_controller.write_calib_stb
+ddr3_controller.write_calib_we
+@200
+-
+@24
+ddr3_controller.delay_counter[15:0]
+ddr3_controller.stage1_bank[2:0]
+ddr3_controller.stage2_bank[2:0]
+@28
+ddr3_controller.stage1_we
+ddr3_controller.stage2_we
+ddr3_controller.issue_read_command
+ddr3_controller.issue_write_command
+@200
+-
+@28
+ddr3_controller.bank_status_q[7:0]
+@22
+ddr3_controller.delay_before_write_counter_q<1>[3:0]
+ddr3_controller.delay_before_read_counter_q<7>[3:0]
+ddr3_controller.delay_before_write_counter_q<7>[3:0]
+ddr3_controller.delay_before_activate_counter_q<7>[3:0]
+ddr3_controller.delay_before_write_counter_q<7>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
+@200
+-
+@22
+ddr3_controller.delay_before_activate_counter_q<0>[3:0]
+ddr3_controller.delay_before_activate_counter_q<1>[3:0]
+ddr3_controller.delay_before_activate_counter_q<2>[3:0]
+ddr3_controller.delay_before_activate_counter_q<3>[3:0]
+ddr3_controller.delay_before_activate_counter_q<4>[3:0]
+ddr3_controller.delay_before_activate_counter_q<5>[3:0]
+ddr3_controller.delay_before_activate_counter_q<6>[3:0]
+ddr3_controller.delay_before_activate_counter_q<7>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<3>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<5>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<6>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
+ddr3_controller.delay_before_read_counter_q<0>[3:0]
+ddr3_controller.delay_before_read_counter_q<1>[3:0]
+ddr3_controller.delay_before_read_counter_q<2>[3:0]
+ddr3_controller.delay_before_read_counter_q<3>[3:0]
+ddr3_controller.delay_before_read_counter_q<4>[3:0]
+ddr3_controller.delay_before_read_counter_q<5>[3:0]
+ddr3_controller.delay_before_read_counter_q<6>[3:0]
+ddr3_controller.delay_before_read_counter_q<7>[3:0]
+ddr3_controller.delay_before_write_counter_q<0>[3:0]
+ddr3_controller.delay_before_write_counter_q<1>[3:0]
+ddr3_controller.delay_before_write_counter_q<2>[3:0]
+ddr3_controller.delay_before_write_counter_q<3>[3:0]
+ddr3_controller.delay_before_write_counter_q<4>[3:0]
+ddr3_controller.delay_before_write_counter_q<5>[3:0]
+ddr3_controller.delay_before_write_counter_q<6>[3:0]
+ddr3_controller.delay_before_write_counter_q<7>[3:0]
+@200
+-
+@22
+ddr3_controller.delay_before_activate_counter_q<4>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
+ddr3_controller.delay_before_read_counter_q<4>[3:0]
+ddr3_controller.delay_before_write_counter_q<4>[3:0]
+@200
+-
+@28
+ddr3_controller.cmd_odt
+@24
+ddr3_controller.instruction_address[4:0]
+@28
+ddr3_controller.stage1_pending
+ddr3_controller.stage1_we
+ddr3_controller.stage2_pending
+ddr3_controller.stage2_we
+@24
+ddr3_controller.stage1_bank[2:0]
+ddr3_controller.stage2_bank[2:0]
+@22
+ddr3_controller.delay_before_write_counter_q<4>[3:0]
+ddr3_controller.delay_before_read_counter_q<4>[3:0]
+@28
+ddr3_controller.o_wb_stall_d
+@24
+ddr3_controller.stage1_col[9:0]
+ddr3_controller.stage1_row[13:0]
+ddr3_controller.stage2_row[13:0]
+ddr3_controller.stage1_next_bank[2:0]
+@c00024
+ddr3_controller.stage1_next_row[13:0]
+@28
+(0)ddr3_controller.stage1_next_row[13:0]
+(1)ddr3_controller.stage1_next_row[13:0]
+(2)ddr3_controller.stage1_next_row[13:0]
+(3)ddr3_controller.stage1_next_row[13:0]
+(4)ddr3_controller.stage1_next_row[13:0]
+(5)ddr3_controller.stage1_next_row[13:0]
+(6)ddr3_controller.stage1_next_row[13:0]
+(7)ddr3_controller.stage1_next_row[13:0]
+(8)ddr3_controller.stage1_next_row[13:0]
+(9)ddr3_controller.stage1_next_row[13:0]
+(10)ddr3_controller.stage1_next_row[13:0]
+(11)ddr3_controller.stage1_next_row[13:0]
+(12)ddr3_controller.stage1_next_row[13:0]
+(13)ddr3_controller.stage1_next_row[13:0]
+@1401200
+-group_end
+@200
+-
+@22
+ddr3_controller.delay_before_activate_counter_q<0>[3:0]
+ddr3_controller.delay_before_activate_counter_q<1>[3:0]
+@200
+-
+@22
+ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
+@200
+-
+@22
+ddr3_controller.delay_before_read_counter_q<0>[3:0]
+ddr3_controller.delay_before_read_counter_q<1>[3:0]
+@200
+-
+@24
+ddr3_controller.bank_active_row_q<0>[13:0]
+ddr3_controller.bank_active_row_q<1>[13:0]
+ddr3_controller.bank_active_row_q<2>[13:0]
+ddr3_controller.bank_active_row_q<3>[13:0]
+ddr3_controller.bank_active_row_q<4>[13:0]
+ddr3_controller.bank_active_row_q<5>[13:0]
+ddr3_controller.bank_active_row_q<6>[13:0]
+ddr3_controller.bank_active_row_q<7>[13:0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/formal_wb2.gtkw b/formal_wb2.gtkw
new file mode 100644
index 0000000..63db9b2
--- /dev/null
+++ b/formal_wb2.gtkw
@@ -0,0 +1,163 @@
+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Tue Jul 11 12:39:11 2023
+[*]
+[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd"
+[dumpfile_mtime] "Tue Jul 11 12:37:05 2023"
+[dumpfile_size] 144494
+[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/wb2.gtkw"
+[timestart] 0
+[size] 1848 1126
+[pos] -1 -1
+*-4.757294 10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ddr3_controller.
+[sst_width] 297
+[signals_width] 395
+[sst_expanded] 1
+[sst_vpaned_height] 743
+@28
+ddr3_controller.i_controller_clk
+ddr3_controller.i_rst_n
+@24
+ddr3_controller.state_calibrate[4:0]
+@200
+-
+@28
+ddr3_controller.wb2_properties.i_wb_cyc
+@22
+ddr3_controller.wb2_properties.f_nacks[3:0]
+ddr3_controller.wb2_properties.f_nreqs[3:0]
+ddr3_controller.wb2_properties.f_outstanding[3:0]
+ddr3_controller.f_outstanding_2[3:0]
+@200
+-
+-
+@28
+ddr3_controller.i_wb2_addr[31:0]
+[color] 2
+ddr3_controller.i_wb2_cyc
+ddr3_controller.i_wb2_data[31:0]
+[color] 2
+ddr3_controller.i_wb2_stb
+[color] 2
+ddr3_controller.i_wb2_we
+[color] 2
+ddr3_controller.o_wb2_ack
+ddr3_controller.o_wb2_data[31:0]
+ddr3_controller.o_wb2_stall
+@200
+-
+@28
+[color] 4
+ddr3_controller.f_delay_ld[7:0]
+[color] 4
+ddr3_controller.o_phy_idelay_data_ld[7:0]
+[color] 4
+ddr3_controller.o_phy_idelay_dqs_ld[7:0]
+[color] 4
+ddr3_controller.o_phy_odelay_data_ld[7:0]
+[color] 4
+ddr3_controller.o_phy_odelay_dqs_ld[7:0]
+ddr3_controller.o_phy_idelay_data_cntvaluein[4:0]
+ddr3_controller.o_phy_idelay_dqs_cntvaluein[4:0]
+ddr3_controller.o_phy_odelay_data_cntvaluein[4:0]
+ddr3_controller.o_phy_odelay_dqs_cntvaluein[4:0]
+@200
+-
+@22
+ddr3_controller.odelay_data_cntvaluein<0>[4:0]
+ddr3_controller.odelay_data_cntvaluein<1>[4:0]
+ddr3_controller.odelay_data_cntvaluein<2>[4:0]
+ddr3_controller.odelay_data_cntvaluein<3>[4:0]
+ddr3_controller.odelay_data_cntvaluein<4>[4:0]
+ddr3_controller.odelay_data_cntvaluein<5>[4:0]
+@28
+ddr3_controller.odelay_data_cntvaluein<6>[4:0]
+@22
+ddr3_controller.odelay_data_cntvaluein<7>[4:0]
+@200
+-
+@28
+[color] 4
+ddr3_controller.wb2_addr[31:0]
+[color] 4
+ddr3_controller.wb2_data[31:0]
+@22
+[color] 4
+ddr3_controller.wb2_phy_idelay_data_cntvaluein[4:0]
+@28
+[color] 4
+ddr3_controller.wb2_phy_idelay_data_ld[7:0]
+@22
+[color] 4
+ddr3_controller.wb2_phy_idelay_dqs_cntvaluein[4:0]
+@c00028
+[color] 4
+ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+@28
+(0)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+(1)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+(2)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+(3)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+(4)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+(5)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+(6)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+(7)ddr3_controller.wb2_phy_idelay_dqs_ld[7:0]
+@1401200
+-group_end
+@22
+[color] 4
+ddr3_controller.wb2_phy_odelay_data_cntvaluein[4:0]
+@28
+[color] 4
+ddr3_controller.wb2_phy_odelay_data_ld[7:0]
+@c00028
+[color] 4
+ddr3_controller.f_delay_ld[7:0]
+@28
+(0)ddr3_controller.f_delay_ld[7:0]
+(1)ddr3_controller.f_delay_ld[7:0]
+(2)ddr3_controller.f_delay_ld[7:0]
+(3)ddr3_controller.f_delay_ld[7:0]
+(4)ddr3_controller.f_delay_ld[7:0]
+(5)ddr3_controller.f_delay_ld[7:0]
+(6)ddr3_controller.f_delay_ld[7:0]
+(7)ddr3_controller.f_delay_ld[7:0]
+@1401200
+-group_end
+@22
+[color] 4
+ddr3_controller.wb2_phy_odelay_dqs_cntvaluein[4:0]
+@28
+[color] 4
+ddr3_controller.wb2_phy_odelay_dqs_ld[7:0]
+[color] 2
+ddr3_controller.wb2_stb
+[color] 4
+ddr3_controller.wb2_update
+[color] 2
+ddr3_controller.wb2_we
+[color] 4
+ddr3_controller.wb2_write_lane[2:0]
+[color] 2
+ddr3_controller.f_o_wb2_ack_q
+ddr3_controller.f_read_data_2[12:0]
+ddr3_controller.f_read_data_2_q[12:0]
+@200
+-
+@28
+ddr3_controller.fifo_2.read_fifo
+ddr3_controller.f_read_fifo_2
+[color] 2
+ddr3_controller.fifo_2.write_fifo
+[color] 2
+ddr3_controller.fifo_2.empty
+[color] 2
+ddr3_controller.fifo_2.full
+@29
+ddr3_controller.f_full_2
+@28
+ddr3_controller.fifo_2.read_pointer
+ddr3_controller.fifo_2.write_pointer
+[pattern_trace] 1
+[pattern_trace] 0