From b02e66b7d8f2cbc64002bac9e82e86a8bbccbabe Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Sun, 16 Mar 2025 12:29:48 +0800 Subject: [PATCH] revert changes in shiftin and iodelay_group string name since openxc7 now works on them --- rtl/ddr3_phy.v | 34 +++++++--------------------------- 1 file changed, 7 insertions(+), 27 deletions(-) diff --git a/rtl/ddr3_phy.v b/rtl/ddr3_phy.v index 704dc36..7b200d2 100644 --- a/rtl/ddr3_phy.v +++ b/rtl/ddr3_phy.v @@ -211,10 +211,8 @@ module ddr3_phy #( .D7(), .D8(), // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T1(0), .T2(0), @@ -263,10 +261,8 @@ module ddr3_phy #( .D7(), .D8(), // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T1(0), .T2(0), @@ -339,10 +335,8 @@ module ddr3_phy #( .TFB(), // 1-bit output: 3-state control .TQ(), // 1-bit output: 3-state control // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T1(0), .T2(0), @@ -357,7 +351,7 @@ module ddr3_phy #( //Delay the DQ // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps - (* IODELAY_GROUP = 0 *) + (* IODELAY_GROUP="DDR3-GROUP" *) ODELAYE2 #( .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN) .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE") @@ -483,10 +477,8 @@ module ddr3_phy #( .TBYTEOUT(), // 1-bit output: Byte group tristate .TFB(), // 1-bit output: 3-state control // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T2(0), .T3(0), @@ -502,7 +494,7 @@ module ddr3_phy #( //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US //Delay the DQ // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps - (* IODELAY_GROUP = 0 *) + (* IODELAY_GROUP="DDR3-GROUP" *) ODELAYE2 #( .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN) .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE") @@ -601,10 +593,8 @@ module ddr3_phy #( .TBYTEOUT(), // 1-bit output: Byte group tristate .TFB(), // 1-bit output: 3-state control // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T2(0), .T3(0), @@ -633,7 +623,7 @@ module ddr3_phy #( // IDELAYE2: Input Fixed or Variable Delay Element // 7 Series // Xilinx HDL Libraries Guide, version 13.4 - (* IODELAY_GROUP = 0 *) + (* IODELAY_GROUP="DDR3-GROUP" *) IDELAYE2 #( .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN) .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE") @@ -767,10 +757,8 @@ module ddr3_phy #( .TFB(), // 1-bit output: 3-state control .TQ(), // 1-bit output: 3-state control // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T1(0), .T2(0), @@ -787,7 +775,7 @@ module ddr3_phy #( //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US //Delay the DQ // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps - (* IODELAY_GROUP = 0 *) + (* IODELAY_GROUP="DDR3-GROUP" *) ODELAYE2 #( .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN) .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE") @@ -859,10 +847,8 @@ module ddr3_phy #( .TFB(), // 1-bit output: 3-state control .TQ(), // 1-bit output: 3-state control // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T1(0), .T2(0), @@ -927,10 +913,8 @@ module ddr3_phy #( .TBYTEOUT(), // 1-bit output: Byte group tristate .TFB(), // 1-bit output: 3-state control // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T2(0), .T3(0), @@ -945,7 +929,7 @@ module ddr3_phy #( // 7 Series // Xilinx HDL Libraries Guide, version 13.4 //Delay the DQ - (* IODELAY_GROUP = 0 *) + (* IODELAY_GROUP="DDR3-GROUP" *) ODELAYE2 #( .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN) .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE") @@ -1048,10 +1032,8 @@ module ddr3_phy #( .TBYTEOUT(), // 1-bit output: Byte group tristate .TFB(), // 1-bit output: 3-state control // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T2(0), .T3(0), @@ -1082,7 +1064,7 @@ module ddr3_phy #( // IDELAYE2: Input Fixed or Variable Delay Element // 7 Series // Xilinx HDL Libraries Guide, version 13.4 - (* IODELAY_GROUP = 0 *) + (* IODELAY_GROUP="DDR3-GROUP" *) IDELAYE2 #( .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN) .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE") @@ -1300,10 +1282,8 @@ module ddr3_phy #( .TFB(), // 1-bit output: 3-state control .TQ(), // 1-bit output: 3-state control // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) - `ifndef YOSYS // openxc7 run fails if this is connected to ground .SHIFTIN1(0), .SHIFTIN2(0), - `endif // T1 - T4: 1-bit (each) input: Parallel 3-state inputs .T1(0), .T2(0), @@ -1324,7 +1304,7 @@ module ddr3_phy #( // IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control // 7 Series // Xilinx HDL Libraries Guide, version 13.4 - (* IODELAY_GROUP = 0 *) + (* IODELAY_GROUP="DDR3-GROUP" *) IDELAYCTRL IDELAYCTRL_inst ( .RDY(idelayctrl_rdy), // 1-bit output: Ready output .REFCLK(i_ref_clk), // 1-bit input: Reference clock input.The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.