diff --git a/example_demo/arty_s7/arty_ddr3.v b/example_demo/arty_s7/arty_ddr3.v
index 3d6e2d3..e6cba3a 100644
--- a/example_demo/arty_s7/arty_ddr3.v
+++ b/example_demo/arty_s7/arty_ddr3.v
@@ -180,14 +180,16 @@
         .COL_BITS(10), //width of column address
         .BA_BITS(3), //width of bank address
         .BYTE_LANES(2), //number of DDR3 modules to be controlled
-        .AUX_WIDTH(16), //width of aux line (must be >= 4) 
+        .AUX_WIDTH(4), //width of aux line (must be >= 4) 
         .WB2_ADDR_BITS(32), //width of 2nd wishbone address bus 
         .WB2_DATA_BITS(32), //width of 2nd wishbone data bus
         .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
         .ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
         .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed 
         .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
-        .WB_ERROR(0) // set to 1 to support Wishbone error (asserts at ECC double bit error)
+        .WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+        .BIST_MODE(1), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+        .SPEED_BIN(1) // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
         ) ddr3_top
         (
             //clock and reset
diff --git a/example_demo/arty_s7/arty_ddr3_openxc7.bit b/example_demo/arty_s7/arty_ddr3_openxc7.bit
index 0934e48..eef956d 100644
Binary files a/example_demo/arty_s7/arty_ddr3_openxc7.bit and b/example_demo/arty_s7/arty_ddr3_openxc7.bit differ
diff --git a/example_demo/arty_s7/clk_wiz.v b/example_demo/arty_s7/clk_wiz.v
index 7ce38cc..2b18760 100644
--- a/example_demo/arty_s7/clk_wiz.v
+++ b/example_demo/arty_s7/clk_wiz.v
@@ -22,18 +22,18 @@ module clk_wiz
     .COMPENSATION         ("INTERNAL"),
     .STARTUP_WAIT         ("FALSE"),
     .DIVCLK_DIVIDE        (1),
-    .CLKFBOUT_MULT        (10), // 100 MHz * 10 = 1000 MHz
+    .CLKFBOUT_MULT        (12), // 100 MHz * 12 = 1200 MHz
     .CLKFBOUT_PHASE       (0.000),
-    .CLKOUT0_DIVIDE       (12), // 1000 MHz / 12 = 83.333 MHz
+    .CLKOUT0_DIVIDE       (12), // 1200 MHz / 12 = 100 MHz
     .CLKOUT0_PHASE        (0.000),
     .CLKOUT0_DUTY_CYCLE   (0.500),
-    .CLKOUT1_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz
+    .CLKOUT1_DIVIDE       (3), // 1200 MHz / 3 = 400 MHz
     .CLKOUT1_PHASE        (0.000),
     .CLKOUT1_DUTY_CYCLE   (0.500),
-    .CLKOUT2_DIVIDE       (5), // 1000 MHz / 5 = 200 MHz
+    .CLKOUT2_DIVIDE       (6), // 1200 MHz / 6 = 200 MHz
     .CLKOUT2_PHASE        (0.000),
     .CLKOUT2_DUTY_CYCLE   (0.500),
-    .CLKOUT3_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
+    .CLKOUT3_DIVIDE       (3), // 1200 MHz / 3 = 400 MHz, 90 phase
     .CLKOUT3_PHASE        (90.000),
     .CLKOUT3_DUTY_CYCLE   (0.500),
     .CLKIN1_PERIOD        (10.000) // 100 MHz input