diff --git a/example_demo/alinx_ax7103b/ax7103_ddr3.bit b/example_demo/alinx_ax7103b/ax7103_ddr3.bit index fe5726b..5538091 100644 Binary files a/example_demo/alinx_ax7103b/ax7103_ddr3.bit and b/example_demo/alinx_ax7103b/ax7103_ddr3.bit differ diff --git a/example_demo/alinx_ax7325b/ax7325b_ddr3.bit b/example_demo/alinx_ax7325b/ax7325b_ddr3.bit index e26be39..8bc0b20 100644 Binary files a/example_demo/alinx_ax7325b/ax7325b_ddr3.bit and b/example_demo/alinx_ax7325b/ax7325b_ddr3.bit differ diff --git a/example_demo/arty_s7/arty_ddr3.bit b/example_demo/arty_s7/arty_ddr3.bit index 42b6373..543599b 100644 Binary files a/example_demo/arty_s7/arty_ddr3.bit and b/example_demo/arty_s7/arty_ddr3.bit differ diff --git a/example_demo/enclustra_kx2_st1/Makefile b/example_demo/enclustra_kx2_st1/Makefile index 841b9b8..dc5ee40 100644 --- a/example_demo/enclustra_kx2_st1/Makefile +++ b/example_demo/enclustra_kx2_st1/Makefile @@ -27,7 +27,7 @@ TOP_VERILOG ?= ${TOP}.v PNR_DEBUG ?= # --verbose --debug BOARD ?= UNKNOWN -JTAG_LINK ?= --board ${BOARD} +JTAG_LINK ?= -c digilent_hs2 XDC ?= ${PROJECT}.xdc diff --git a/example_demo/enclustra_kx2_st1/enclustra_ddr3.bit b/example_demo/enclustra_kx2_st1/enclustra_ddr3.bit index d0a54b8..c4a1734 100644 Binary files a/example_demo/enclustra_kx2_st1/enclustra_ddr3.bit and b/example_demo/enclustra_kx2_st1/enclustra_ddr3.bit differ diff --git a/example_demo/orangecrab_ecp5/orangecrab_ecp5_ddr3.dfu b/example_demo/orangecrab_ecp5/orangecrab_ecp5_ddr3.dfu new file mode 100644 index 0000000..2b160a4 Binary files /dev/null and b/example_demo/orangecrab_ecp5/orangecrab_ecp5_ddr3.dfu differ diff --git a/example_demo/qmtech_kintex_7/qmtech_kintex7_ddr3.bit b/example_demo/qmtech_kintex_7/qmtech_kintex7_ddr3.bit index 260e5b7..9664e81 100644 Binary files a/example_demo/qmtech_kintex_7/qmtech_kintex7_ddr3.bit and b/example_demo/qmtech_kintex_7/qmtech_kintex7_ddr3.bit differ diff --git a/example_demo/qmtech_wukong/wukong_ddr3.bit b/example_demo/qmtech_wukong/wukong_ddr3.bit index bcf2499..6d50f8b 100644 Binary files a/example_demo/qmtech_wukong/wukong_ddr3.bit and b/example_demo/qmtech_wukong/wukong_ddr3.bit differ diff --git a/example_demo/run_make_all.sh b/example_demo/run_make_all.sh new file mode 100755 index 0000000..87bf4cf --- /dev/null +++ b/example_demo/run_make_all.sh @@ -0,0 +1,23 @@ +#!/bin/bash + +# Create a logs directory to store all log files +mkdir -p build_logs + +# Loop through each item in the current directory +for dir in */; do + # Check if it's a directory and contains a Makefile + if [ -d "$dir" ] && [ -f "$dir/Makefile" ]; then + log_file="build_logs/${dir%/}.log" + echo "Building $dir... Logging to $log_file" + { + echo "===== $(date) - Building $dir =====" + cd "$dir" + make clean + make + cd .. + echo "===== Finished $dir =====" + } &> "$log_file" + else + echo "Skipping $dir (no Makefile found)" + fi +done diff --git a/testbench/ddr3_dimm_micron_sim.sv b/testbench/ddr3_dimm_micron_sim.sv index 12b6d8d..88e530c 100644 --- a/testbench/ddr3_dimm_micron_sim.sv +++ b/testbench/ddr3_dimm_micron_sim.sv @@ -66,7 +66,7 @@ module ddr3_dimm_micron_sim; TEST_SELF_REFRESH = 0, SECOND_WISHBONE = 0, BIST_MODE = 2, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w) - DLL_OFF = 1; + DLL_OFF = 0; reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90; reg i_rst_n; diff --git a/testbench/ddr3_dimm_micron_sim_behav.wcfg b/testbench/ddr3_dimm_micron_sim_behav.wcfg deleted file mode 100644 index 884422d..0000000 --- a/testbench/ddr3_dimm_micron_sim_behav.wcfg +++ /dev/null @@ -1,805 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Clocks and Reset - label - - - i_rst_n - i_rst_n - - - i_controller_clk - i_controller_clk - - - i_ddr3_clk - i_ddr3_clk - - - i_ddr3_clk_90 - i_ddr3_clk_90 - - - i_ref_clk - i_ref_clk - - - i_rst_n - i_rst_n - - - sync_rst - sync_rst - - - Self-refresh - label - - - i_user_self_refresh - i_user_self_refresh - - - user_self_refresh_q - user_self_refresh_q - - - o_ddr3_cke[0:0] - o_ddr3_cke[0:0] - - - - refresh_counter[8:0] - refresh_counter[8:0] - UNSIGNEDDECRADIX - - - o_wb_stall - o_wb_stall - - - i_wb_stb - i_wb_stb - - - cmd_ck_en[0:0] - cmd_ck_en[0:0] - - - [0] - [0] - #FF0080 - true - - - - prev_cmd_ck_en[0:0] - prev_cmd_ck_en[0:0] - - - [0] - [0] - #FFA500 - true - - - - i_controller_cmd[103:0] - i_controller_cmd[103:0] - - [103] - [103] - - - [102] - [102] - - - [101] - [101] - - - [100] - [100] - - - [99] - [99] - - - [98] - [98] - #FF0080 - true - - - [97] - [97] - - - [96] - [96] - - - [95] - [95] - - - [94] - [94] - - - [93] - [93] - - - [92] - [92] - - - [91] - [91] - - - [90] - [90] - - - [89] - [89] - - - [88] - [88] - - - [87] - [87] - - - [86] - [86] - - - [85] - [85] - - - [84] - [84] - - - [83] - [83] - - - [82] - [82] - - - [81] - [81] - - - [80] - [80] - - - [79] - [79] - - - [78] - [78] - - - [77] - [77] - - - [76] - [76] - - - [75] - [75] - - - [74] - [74] - - - [73] - [73] - - - [72] - [72] - #FF0080 - true - - - [71] - [71] - - - [70] - [70] - - - [69] - [69] - - - [68] - [68] - - - [67] - [67] - - - [66] - [66] - - - [65] - [65] - - - [64] - [64] - - - [63] - [63] - - - [62] - [62] - - - [61] - [61] - - - [60] - [60] - - - [59] - [59] - - - [58] - [58] - - - [57] - [57] - - - [56] - [56] - - - [55] - [55] - - - [54] - [54] - - - [53] - [53] - - - [52] - [52] - - - [51] - [51] - - - [50] - [50] - - - [49] - [49] - - - [48] - [48] - - - [47] - [47] - - - [46] - [46] - #FF0080 - true - - - [45] - [45] - - - [44] - [44] - - - [43] - [43] - - - [42] - [42] - - - [41] - [41] - - - [40] - [40] - - - [39] - [39] - - - [38] - [38] - - - [37] - [37] - - - [36] - [36] - - - [35] - [35] - - - [34] - [34] - - - [33] - [33] - - - [32] - [32] - - - [31] - [31] - - - [30] - [30] - - - [29] - [29] - - - [28] - [28] - - - [27] - [27] - - - [26] - [26] - - - [25] - [25] - - - [24] - [24] - - - [23] - [23] - - - [22] - [22] - - - [21] - [21] - - - [20] - [20] - #FF00FF - true - - - [19] - [19] - - - [18] - [18] - - - [17] - [17] - - - [16] - [16] - - - [15] - [15] - - - [14] - [14] - - - [13] - [13] - - - [12] - [12] - - - [11] - [11] - - - [10] - [10] - - - [9] - [9] - - - [8] - [8] - - - [7] - [7] - - - [6] - [6] - - - [5] - [5] - - - [4] - [4] - - - [3] - [3] - - - [2] - [2] - - - [1] - [1] - - - [0] - [0] - - - - Calibration - label - - - odelay_cntvalue_halfway - odelay_cntvalue_halfway - - - write_level_fail[7:0] - write_level_fail[7:0] - - - prev_write_level_feedback - prev_write_level_feedback - - - stored_write_level_feedback - stored_write_level_feedback - - - sample_clk_repeat[3:0] - sample_clk_repeat[3:0] - - - initial_calibration_done - initial_calibration_done - - - state_calibrate[4:0] - state_calibrate[4:0] - UNSIGNEDDECRADIX - - - instruction_address[4:0] - instruction_address[4:0] - - - calibration_state[319:0] - calibration_state[319:0] - ASCIIRADIX - - - command_used[23:0] - command_used[23:0] - ASCIIRADIX - #FFD700 - true - - - o_phy_odelay_dqs_cntvaluein[4:0] - o_phy_odelay_dqs_cntvaluein[4:0] - UNSIGNEDDECRADIX - - - o_phy_idelay_dqs_cntvaluein[4:0] - o_phy_idelay_dqs_cntvaluein[4:0] - UNSIGNEDDECRADIX - - - i_ddr3_clk - i_ddr3_clk - - - o_ddr3_clk_n[0:0] - o_ddr3_clk_n[0:0] - - - o_ddr3_clk_p[0:0] - o_ddr3_clk_p[0:0] - - - [0] - [0] - #FF0080 - true - - - - io_ddr3_dqs[7:0] - io_ddr3_dqs[7:0] - - - [7] - [7] - - - [6] - [6] - - - [5] - [5] - - - [4] - [4] - - - [3] - [3] - - - [2] - [2] - - - [1] - [1] - #FFFF00 - true - - - [0] - [0] - #FF0080 - true - - - - io_ddr3_dqs_n[7:0] - io_ddr3_dqs_n[7:0] - - - io_ddr3_dq[63:0] - io_ddr3_dq[63:0] - - - idelay_dqs[7:0] - idelay_dqs[7:0] - - - lane[2:0] - lane[2:0] - UNSIGNEDDECRADIX - #FF00FF - true - - - instruction_address[4:0] - instruction_address[4:0] - UNSIGNEDDECRADIX - - - read_test_address_counter[25:0] - read_test_address_counter[25:0] - UNSIGNEDDECRADIX - - - write_test_address_counter[31:0] - write_test_address_counter[31:0] - UNSIGNEDDECRADIX - - - correct_read_data[31:0] - correct_read_data[31:0] - UNSIGNEDDECRADIX - - - wrong_read_data[31:0] - wrong_read_data[31:0] - UNSIGNEDDECRADIX - - - WIshbone Interface - label - - - i_controller_clk - i_controller_clk - - - calibration_state[319:0] - calibration_state[319:0] - ASCIIRADIX - - - i_wb_cyc - i_wb_cyc - - - i_wb_stb - i_wb_stb - - - i_wb_we - i_wb_we - - - i_wb_addr[25:0] - i_wb_addr[25:0] - - - i_wb_data[511:0] - i_wb_data[511:0] - - - i_wb_sel[63:0] - i_wb_sel[63:0] - - - o_wb_stall - o_wb_stall - - - o_wb_ack - o_wb_ack - - - o_wb_data[511:0] - o_wb_data[511:0] - - - DDR3 Interface - label - - - o_ddr3_cke[0:0] - o_ddr3_cke[0:0] - - - o_ddr3_cs_n[0:0] - o_ddr3_cs_n[0:0] - - - o_ddr3_ras_n - o_ddr3_ras_n - - - o_ddr3_cas_n - o_ddr3_cas_n - - - o_ddr3_we_n - o_ddr3_we_n - - - o_ddr3_addr[15:0] - o_ddr3_addr[15:0] - - - o_ddr3_ba_addr[2:0] - o_ddr3_ba_addr[2:0] - - - io_ddr3_dq[63:0] - io_ddr3_dq[63:0] - - - io_ddr3_dqs[7:0] - io_ddr3_dqs[7:0] - - - - io_ddr3_dqs_n[7:0] - io_ddr3_dqs_n[7:0] - - - o_ddr3_dm[7:0] - o_ddr3_dm[7:0] - - - o_ddr3_odt[0:0] - o_ddr3_odt[0:0] - -