From 9b99dbfe77f4c2f2f74bafc3e0ded8536663d68c Mon Sep 17 00:00:00 2001
From: AngeloJacobo <jacobo.angeloECE@gmail.com>
Date: Sun, 28 Jul 2024 17:30:35 +0800
Subject: [PATCH] add ECC parameters

---
 example_demo/arty_s7/arty_ddr3.v                | 12 +++++++-----
 example_demo/enclustra_kx2_st1/enclustra_ddr3.v |  6 ++++--
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/example_demo/arty_s7/arty_ddr3.v b/example_demo/arty_s7/arty_ddr3.v
index bfa5dc9..105db4b 100644
--- a/example_demo/arty_s7/arty_ddr3.v
+++ b/example_demo/arty_s7/arty_ddr3.v
@@ -66,11 +66,10 @@
      wire tx_full;
      wire o_wb_ack;
      wire[7:0] o_wb_data;
-     wire o_aux;
      wire[7:0] rd_data;
      wire o_wb_stall;
      reg i_wb_stb = 0, i_wb_we;
-     wire[63:0] o_debug1;
+     wire[31:0] o_debug1;
      reg[7:0] i_wb_data;
      reg[7:0] i_wb_addr;
      // o_debug1 taps on value of state_calibrate (can be traced inside ddr3_controller module)
@@ -140,12 +139,14 @@
         .COL_BITS(10), //width of column address
         .BA_BITS(3), //width of bank address
         .BYTE_LANES(2), //number of DDR3 modules to be controlled
-        .AUX_WIDTH(4), //width of aux line (must be >= 4) 
+        .AUX_WIDTH(16), //width of aux line (must be >= 4) 
         .WB2_ADDR_BITS(32), //width of 2nd wishbone address bus 
         .WB2_DATA_BITS(32), //width of 2nd wishbone data bus
         .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
         .ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
-        .SECOND_WISHBONE(0) //set to 1 if 2nd wishbone is needed 
+        .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed 
+        .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+        .WB_ERROR(0) // set to 1 to support Wishbone error (asserts at ECC double bit error)
         ) ddr3_top
         (
             //clock and reset
@@ -165,8 +166,9 @@
             // Wishbone outputs
             .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
             .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+            .o_wb_err(), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
             .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
-            .o_aux(o_aux),
+            .o_aux(),
             // Wishbone 2 (PHY) inputs
             .i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
             .i_wb2_stb(), //request a transfer
diff --git a/example_demo/enclustra_kx2_st1/enclustra_ddr3.v b/example_demo/enclustra_kx2_st1/enclustra_ddr3.v
index aaa11fc..7feddf2 100644
--- a/example_demo/enclustra_kx2_st1/enclustra_ddr3.v
+++ b/example_demo/enclustra_kx2_st1/enclustra_ddr3.v
@@ -138,12 +138,14 @@
         .COL_BITS(10), //width of column address
         .BA_BITS(3), //width of bank address
         .BYTE_LANES(8), //number of DDR3 modules to be controlled
-        .AUX_WIDTH(4), //width of aux line (must be >= 4) 
+        .AUX_WIDTH(16), //width of aux line (must be >= 4) 
         .WB2_ADDR_BITS(32), //width of 2nd wishbone address bus 
         .WB2_DATA_BITS(32), //width of 2nd wishbone data bus
         .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
         .ODELAY_SUPPORTED(1), //set to 1 when ODELAYE2 is supported
-        .SECOND_WISHBONE(0) //set to 1 if 2nd wishbone is needed 
+        .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed 
+        .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+        .WB_ERROR(0) // set to 1 to support Wishbone error (asserts at ECC double bit error)
         ) ddr3_top
         (
             //clock and reset