From 9a0b0cde3682564eedcd5850e5cc63a2d272ade7 Mon Sep 17 00:00:00 2001
From: Angelo Jacobo <jacobo.angeloECE@gmail.com>
Date: Thu, 6 Apr 2023 19:45:09 +0800
Subject: [PATCH] Add files via upload

---
 formal_cover.gtkw | 141 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 141 insertions(+)
 create mode 100644 formal_cover.gtkw

diff --git a/formal_cover.gtkw b/formal_cover.gtkw
new file mode 100644
index 0000000..4f0c807
--- /dev/null
+++ b/formal_cover.gtkw
@@ -0,0 +1,141 @@
+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Thu Apr  6 11:31:18 2023
+[*]
+[dumpfile] "/home/angelo/Videos/DDR3_Controller/ddr3_controller/engine_0/trace0.vcd"
+[dumpfile_mtime] "Thu Apr  6 11:30:02 2023"
+[dumpfile_size] 69448
+[savefile] "/home/angelo/Videos/DDR3_Controller/formal_cover.gtkw"
+[timestart] 0
+[size] 1848 1126
+[pos] -51 -51
+*-5.094873 174 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 43
+[signals_width] 468
+[sst_expanded] 0
+[sst_vpaned_height] 743
+@28
+ddr3_controller.i_clk
+ddr3_controller.i_rst_n
+ddr3_controller.i_wb_cyc
+ddr3_controller.o_wb_stall
+ddr3_controller.i_wb_stb
+ddr3_controller.i_wb_we
+@c00022
+ddr3_controller.f_index[4:0]
+@28
+(0)ddr3_controller.f_index[4:0]
+(1)ddr3_controller.f_index[4:0]
+(2)ddr3_controller.f_index[4:0]
+(3)ddr3_controller.f_index[4:0]
+(4)ddr3_controller.f_index[4:0]
+@1401200
+-group_end
+@200
+-
+@22
+ddr3_controller.i_wb_addr[23:0]
+ddr3_controller.i_wb_data[511:0]
+ddr3_controller.i_wb_sel[63:0]
+@28
+ddr3_controller.o_wb_ack
+@200
+-
+@28
+ddr3_controller.bank_status_q[7:0]
+@22
+ddr3_controller.bank_active_row_q<0>[13:0]
+ddr3_controller.bank_active_row_q<1>[13:0]
+@24
+ddr3_controller.bank_active_row_q<2>[13:0]
+@22
+ddr3_controller.bank_active_row_q<3>[13:0]
+ddr3_controller.bank_active_row_q<4>[13:0]
+ddr3_controller.bank_active_row_q<5>[13:0]
+ddr3_controller.bank_active_row_q<6>[13:0]
+ddr3_controller.bank_active_row_q<7>[13:0]
+@200
+-
+-[0] = WR , [1] = ACT, [2] = RD, [3] = PRE
+@22
+ddr3_controller.cmd_q<0>[20:0]
+ddr3_controller.cmd_q<1>[20:0]
+ddr3_controller.cmd_q<2>[20:0]
+ddr3_controller.cmd_q<3>[20:0]
+@200
+-
+@28
+ddr3_controller.stage1_pending
+ddr3_controller.stage1_bank[2:0]
+@22
+ddr3_controller.stage1_row[13:0]
+ddr3_controller.stage1_col[9:0]
+@28
+ddr3_controller.stage1_next_bank[2:0]
+@22
+ddr3_controller.stage1_next_row[13:0]
+@28
+ddr3_controller.stage1_we
+@200
+-
+@28
+ddr3_controller.stage2_pending
+ddr3_controller.stage2_bank[2:0]
+@22
+ddr3_controller.stage2_row[13:0]
+ddr3_controller.stage2_col[9:0]
+@28
+ddr3_controller.stage2_we
+@200
+-
+@28
+ddr3_controller.reset_done
+@200
+-
+-DELAYS
+@22
+ddr3_controller.delay_before_precharge_counter_q<0>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<3>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<4>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<5>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<6>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<7>[3:0]
+@200
+-
+@22
+ddr3_controller.delay_before_activate_counter_q<0>[3:0]
+ddr3_controller.delay_before_activate_counter_q<1>[3:0]
+ddr3_controller.delay_before_activate_counter_q<2>[3:0]
+ddr3_controller.delay_before_activate_counter_q<3>[3:0]
+ddr3_controller.delay_before_activate_counter_q<4>[3:0]
+ddr3_controller.delay_before_activate_counter_q<5>[3:0]
+ddr3_controller.delay_before_activate_counter_q<6>[3:0]
+ddr3_controller.delay_before_activate_counter_q<7>[3:0]
+@200
+-
+@22
+ddr3_controller.delay_before_read_counter_q<0>[3:0]
+ddr3_controller.delay_before_read_counter_q<1>[3:0]
+ddr3_controller.delay_before_read_counter_q<2>[3:0]
+ddr3_controller.delay_before_read_counter_q<3>[3:0]
+ddr3_controller.delay_before_read_counter_q<4>[3:0]
+ddr3_controller.delay_before_read_counter_q<5>[3:0]
+ddr3_controller.delay_before_read_counter_q<6>[3:0]
+ddr3_controller.delay_before_read_counter_q<7>[3:0]
+@200
+-
+@22
+ddr3_controller.delay_before_write_counter_q<0>[3:0]
+ddr3_controller.delay_before_write_counter_q<1>[3:0]
+ddr3_controller.delay_before_write_counter_q<2>[3:0]
+ddr3_controller.delay_before_write_counter_q<3>[3:0]
+ddr3_controller.delay_before_write_counter_q<4>[3:0]
+ddr3_controller.delay_before_write_counter_q<5>[3:0]
+ddr3_controller.delay_before_write_counter_q<6>[3:0]
+ddr3_controller.delay_before_write_counter_q<7>[3:0]
+@200
+-
+[pattern_trace] 1
+[pattern_trace] 0