diff --git a/.gitignore.swp b/.gitignore.swp deleted file mode 100644 index 586d71e..0000000 Binary files a/.gitignore.swp and /dev/null differ diff --git a/.vivado_sim.sh.swp b/.vivado_sim.sh.swp deleted file mode 100644 index 694615c..0000000 Binary files a/.vivado_sim.sh.swp and /dev/null differ diff --git a/README.txt b/README.txt deleted file mode 100644 index b8b8563..0000000 --- a/README.txt +++ /dev/null @@ -1,83 +0,0 @@ -################################################################################ -# Vivado (TM) v2021.2 (64-bit) -# -# README.txt: Please read the sections below to understand the steps required -# to simulate the design for a simulator, the directory structure -# and the generated exported files. -# -################################################################################ - -1. Simulate Design - -To simulate design, cd to the simulator directory and execute the script. - -For example:- - -% cd questa -% ./top.sh - -The export simulation flow requires the Xilinx pre-compiled simulation library -components for the target simulator. These components are referred using the -'-lib_map_path' switch. If this switch is specified, then the export simulation -will automatically set this library path in the generated script and update, -copy the simulator setup file(s) in the exported directory. - -If '-lib_map_path' is not specified, then the pre-compiled simulation library -information will not be included in the exported scripts and that may cause -simulation errors when running this script. Alternatively, you can provide the -library information using this switch while executing the generated script. - -For example:- - -% ./top.sh -lib_map_path /design/questa/clibs - -Please refer to the generated script header 'Prerequisite' section for more details. - -2. Directory Structure - -By default, if the -directory switch is not specified, export_simulation will -create the following directory structure:- - -/export_sim/ - -For example, if the current working directory is /tmp/test, export_simulation -will create the following directory path:- - -/tmp/test/export_sim/questa - -If -directory switch is specified, export_simulation will create a simulator -sub-directory under the specified directory path. - -For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' -command will create the following directory:- - -/tmp/test/my_test_area/func_sim/questa - -By default, if -simulator is not specified, export_simulation will create a -simulator sub-directory for each simulator and export the files for each simulator -in this sub-directory respectively. - -IMPORTANT: Please note that the simulation library path must be specified manually -in the generated script for the respective simulator. Please refer to the generated -script header 'Prerequisite' section for more details. - -3. Exported script and files - -Export simulation will create the driver shell script, setup files and copy the -design sources in the output directory path. - -By default, when the -script_name switch is not specified, export_simulation will -create the following script name:- - -.sh (Unix) -When exporting the files for an IP using the -of_objects switch, export_simulation -will create the following script name:- - -.sh (Unix) -Export simulation will create the setup files for the target simulator specified -with the -simulator switch. - -For example, if the target simulator is "xcelium", export_simulation will create the -'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' -file. - diff --git a/out b/out deleted file mode 100755 index c61ba43..0000000 --- a/out +++ /dev/null @@ -1,5576 +0,0 @@ -#! /home/angelo/oss-cad-suite/bin/vvp -:ivl_version "12.0 (devel)" "(s20150603-1319-g027c4828e)"; -:ivl_delay_selection "TYPICAL"; -:vpi_time_precision + 0; -:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/system.vpi"; -:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/vhdl_sys.vpi"; -:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/vhdl_textio.vpi"; -:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/v2005_math.vpi"; -:vpi_module "/home/angelo/oss-cad-suite/lib/ivl/va_math.vpi"; -S_0x555555cfe490 .scope module, "ddr3_controller" "ddr3_controller" 2 37; - .timescale 0 0; - .port_info 0 /INPUT 1 "i_controller_clk"; - .port_info 1 /INPUT 1 "i_rst_n"; - .port_info 2 /INPUT 1 "i_wb_cyc"; - .port_info 3 /INPUT 1 "i_wb_stb"; - .port_info 4 /INPUT 1 "i_wb_we"; - .port_info 5 /INPUT 26 "i_wb_addr"; - .port_info 6 /INPUT 512 "i_wb_data"; - .port_info 7 /INPUT 64 "i_wb_sel"; - .port_info 8 /INPUT 16 "i_aux"; - .port_info 9 /OUTPUT 1 "o_wb_stall"; - .port_info 10 /OUTPUT 1 "o_wb_ack"; - .port_info 11 /OUTPUT 512 "o_wb_data"; - .port_info 12 /OUTPUT 16 "o_aux"; - .port_info 13 /INPUT 1 "i_wb2_cyc"; - .port_info 14 /INPUT 1 "i_wb2_stb"; - .port_info 15 /INPUT 1 "i_wb2_we"; - .port_info 16 /INPUT 32 "i_wb2_addr"; - .port_info 17 /INPUT 4 "i_wb2_sel"; - .port_info 18 /INPUT 32 "i_wb2_data"; - .port_info 19 /OUTPUT 1 "o_wb2_stall"; - .port_info 20 /OUTPUT 1 "o_wb2_ack"; - .port_info 21 /OUTPUT 32 "o_wb2_data"; - .port_info 22 /INPUT 512 "i_phy_iserdes_data"; - .port_info 23 /INPUT 64 "i_phy_iserdes_dqs"; - .port_info 24 /INPUT 64 "i_phy_iserdes_bitslip_reference"; - .port_info 25 /INPUT 1 "i_phy_idelayctrl_rdy"; - .port_info 26 /OUTPUT 104 "o_phy_cmd"; - .port_info 27 /OUTPUT 1 "o_phy_dqs_tri_control"; - .port_info 28 /OUTPUT 1 "o_phy_dq_tri_control"; - .port_info 29 /OUTPUT 1 "o_phy_toggle_dqs"; - .port_info 30 /OUTPUT 512 "o_phy_data"; - .port_info 31 /OUTPUT 64 "o_phy_dm"; - .port_info 32 /OUTPUT 5 "o_phy_odelay_data_cntvaluein"; - .port_info 33 /OUTPUT 5 "o_phy_odelay_dqs_cntvaluein"; - .port_info 34 /OUTPUT 5 "o_phy_idelay_data_cntvaluein"; - .port_info 35 /OUTPUT 5 "o_phy_idelay_dqs_cntvaluein"; - .port_info 36 /OUTPUT 8 "o_phy_odelay_data_ld"; - .port_info 37 /OUTPUT 8 "o_phy_odelay_dqs_ld"; - .port_info 38 /OUTPUT 8 "o_phy_idelay_data_ld"; - .port_info 39 /OUTPUT 8 "o_phy_idelay_dqs_ld"; - .port_info 40 /OUTPUT 8 "o_phy_bitslip"; -P_0x555555d8d2e0 .param/l "A10_CONTROL" 1 2 122, +C4<00000000000000000000000000011001>; -P_0x555555d8d320 .param/l "ACTIVATE_SLOT" 1 2 142, C4<00>; -P_0x555555d8d360 .param/l "ACTIVATE_TO_PRECHARGE_DELAY" 1 2 215, C4<0011>; -P_0x555555d8d3a0 .param/l "ACTIVATE_TO_READ_DELAY" 1 2 217, C4<0000>; -P_0x555555d8d3e0 .param/l "ACTIVATE_TO_WRITE_DELAY" 1 2 216, C4<0000>; -P_0x555555d8d420 .param/l "AL" 1 2 296, C4<00>; -P_0x555555d8d460 .param/l "ANALYZE_DATA" 1 2 263, +C4<00000000000000000000000000001101>; -P_0x555555d8d4a0 .param/l "ANALYZE_DQS" 1 2 254, +C4<00000000000000000000000000000100>; -P_0x555555d8d4e0 .param/l "ASR" 1 2 275, C4<1>; -P_0x555555d8d520 .param/l "AUX_WIDTH" 0 2 45, C4<00000000000000000000000000010000>; -P_0x555555d8d560 .param/l "BA_BITS" 0 2 42, C4<00000000000000000000000000000011>; -P_0x555555d8d5a0 .param/l "BITSLIP_DQS_TRAIN_1" 1 2 251, +C4<00000000000000000000000000000001>; -P_0x555555d8d5e0 .param/l "BITSLIP_DQS_TRAIN_2" 1 2 256, +C4<00000000000000000000000000000110>; -P_0x555555d8d620 .param/l "BL" 1 2 306, C4<00>; -P_0x555555d8d660 .param/l "CALIBRATE_DQS" 1 2 255, +C4<00000000000000000000000000000101>; -P_0x555555d8d6a0 .param/l "CALIBRATION_DELAY" 1 2 202, +C4<00000000000000000000000000000010>; -P_0x555555d8d6e0 .param/l "CL" 1 2 307, C4<0100>; -P_0x555555d8d720 .param/l "CLOCK_EN" 1 2 123, +C4<00000000000000000000000000011000>; -P_0x555555d8d760 .param/l "CL_nCK" 1 2 198, +C4<00000000000000000000000000000110>; -P_0x555555d8d7a0 .param/l "CMD_ACT" 1 2 112, C4<0011>; -P_0x555555d8d7e0 .param/l "CMD_ADDRESS_START" 1 2 138, C4<000000000000000000000000000001111>; -P_0x555555d8d820 .param/l "CMD_BANK_START" 1 2 137, C4<0000000000000000000000000000010010>; -P_0x555555d8d860 .param/l "CMD_CAS_N" 1 2 132, C4<000000000000000000000000000000010111>; -P_0x555555d8d8a0 .param/l "CMD_CKE" 1 2 135, C4<000000000000000000000000000000010100>; -P_0x555555d8d8e0 .param/l "CMD_CS_N" 1 2 130, C4<000000000000000000000000000000011001>; -P_0x555555d8d920 .param/l "CMD_DES" 1 2 116, C4<1000>; -P_0x555555d8d960 .param/l "CMD_MRS" 1 2 109, C4<0000>; -P_0x555555d8d9a0 .param/l "CMD_NOP" 1 2 115, C4<0111>; -P_0x555555d8d9e0 .param/l "CMD_ODT" 1 2 134, C4<000000000000000000000000000000010101>; -P_0x555555d8da20 .param/l "CMD_PRE" 1 2 111, C4<0010>; -P_0x555555d8da60 .param/l "CMD_RAS_N" 1 2 131, C4<000000000000000000000000000000011000>; -P_0x555555d8daa0 .param/l "CMD_RD" 1 2 114, C4<0101>; -P_0x555555d8dae0 .param/l "CMD_REF" 1 2 110, C4<0001>; -P_0x555555d8db20 .param/l "CMD_RESET_N" 1 2 136, C4<000000000000000000000000000000010011>; -P_0x555555d8db60 .param/l "CMD_WE_N" 1 2 133, C4<000000000000000000000000000000010110>; -P_0x555555d8dba0 .param/l "CMD_WR" 1 2 113, C4<0100>; -P_0x555555d8dbe0 .param/l "CMD_ZQC" 1 2 117, C4<0110>; -P_0x555555d8dc20 .param/l "COLLECT_DQS" 1 2 253, +C4<00000000000000000000000000000011>; -P_0x555555d8dc60 .param/l "COL_BITS" 0 2 41, C4<00000000000000000000000000001010>; -P_0x555555d8dca0 .param/real "CONTROLLER_CLK_PERIOD" 0 2 38, Cr; value=10.0000 -P_0x555555d8dce0 .param/l "CWL" 1 2 274, C4<000>; -P_0x555555d8dd20 .param/l "CWL_nCK" 1 2 199, +C4<00000000000000000000000000000101>; -P_0x555555d8dd60 .param/l "DATA_INITIAL_IDELAY_TAP" 1 2 158, +C4<00000000000000000000000000000000>; -P_0x555555d8dda0 .param/l "DATA_INITIAL_ODELAY_TAP" 1 2 147, +C4<00000000000000000000000000000000>; -P_0x555555d8dde0 .param/real "DDR3_CLK_PERIOD" 0 2 39, Cr; value=2.50000 -P_0x555555d8de20 .param/l "DDR3_CMD_END" 1 2 126, +C4<00000000000000000000000000010011>; -P_0x555555d8de60 .param/l "DDR3_CMD_START" 1 2 125, +C4<00000000000000000000000000010110>; -P_0x555555d8dea0 .param/l "DELAY_BEFORE_WRITE_LEVEL_FEEDBACK" 1 2 244, C4<00000000000000000000000000000000001101>; -P_0x555555d8dee0 .param/l "DELAY_COUNTER_WIDTH" 1 2 201, +C4<00000000000000000000000000010000>; -P_0x555555d8df20 .param/l "DELAY_MAX_VALUE" 1 2 200, C4<0001100001101010000>; -P_0x555555d8df60 .param/l "DELAY_SLOT_WIDTH" 1 2 164, +C4<00000000000000000000000000010011>; -P_0x555555d8dfa0 .param/l "DIC" 1 2 292, C4<00>; -P_0x555555d8dfe0 .param/l "DLL_EN" 1 2 291, C4<0>; -P_0x555555d8e020 .param/l "DLL_RST" 1 2 309, C4<1>; -P_0x555555d8e060 .param/l "DONE_CALIBRATE" 1 2 264, +C4<00000000000000000000000000001110>; -P_0x555555d8e0a0 .param/l "DQS_INITIAL_IDELAY_TAP" 1 2 159, +C4<00000000000000000000000000001000>; -P_0x555555d8e0e0 .param/l "DQS_INITIAL_ODELAY_TAP" 1 2 155, +C4<00000000000000000000000000001000>; -P_0x555555d8e120 .param/l "DQ_BITS" 0 2 43, C4<00000000000000000000000000001000>; -P_0x555555d8e160 .param/l "IDLE" 1 2 250, +C4<00000000000000000000000000000000>; -P_0x555555d8e1a0 .param/l "INITIAL_CKE_LOW" 1 2 166, +C4<00000000000001111010000100100000>; -P_0x555555d8e1e0 .param/l "INITIAL_RESET_INSTRUCTION" 1 2 317, C4<0100001110000000000000000101>; -P_0x555555d8e220 .param/l "ISSUE_READ" 1 2 261, +C4<00000000000000000000000000001011>; -P_0x555555d8e260 .param/l "ISSUE_WRITE_1" 1 2 259, +C4<00000000000000000000000000001001>; -P_0x555555d8e2a0 .param/l "ISSUE_WRITE_2" 1 2 260, +C4<00000000000000000000000000001010>; -P_0x555555d8e2e0 .param/l "LANES" 0 2 44, C4<00000000000000000000000000001000>; -P_0x555555d8e320 .param/l "MARGIN_BEFORE_ANTICIPATE" 1 2 231, C4<000101>; -P_0x555555d8e360 .param/l "MAX_ADDED_READ_ACK_DELAY" 1 2 242, +C4<00000000000000000000000000010000>; -P_0x555555d8e3a0 .param/l "MPR_DIS" 1 2 284, C4<0>; -P_0x555555d8e3e0 .param/l "MPR_EN" 1 2 283, C4<1>; -P_0x555555d8e420 .param/l "MPR_LOC" 1 2 282, C4<00>; -P_0x555555d8e460 .param/l "MPR_READ" 1 2 252, +C4<00000000000000000000000000000010>; -P_0x555555d8e4a0 .param/l "MR0" 1 2 315, C4<0000000011100100000>; -P_0x555555d8e4e0 .param/l "MR0_SEL" 1 2 314, C4<000>; -P_0x555555d8e520 .param/l "MR1_SEL" 1 2 301, C4<001>; -P_0x555555d8e560 .param/l "MR1_WL_DIS" 1 2 303, C4<0010000100001000100>; -P_0x555555d8e5a0 .param/l "MR1_WL_EN" 1 2 302, C4<0010000100011000100>; -P_0x555555d8e5e0 .param/l "MR2" 1 2 279, C4<0100000000001000000>; -P_0x555555d8e620 .param/l "MR2_SEL" 1 2 278, C4<010>; -P_0x555555d8e660 .param/l "MR3_MPR_DIS" 1 2 287, C4<0110000000000000000>; -P_0x555555d8e6a0 .param/l "MR3_MPR_EN" 1 2 286, C4<0110000000000000100>; -P_0x555555d8e6e0 .param/l "MR3_RD_ADDR" 1 2 288, C4<0000000000000000000>; -P_0x555555d8e720 .param/l "MR3_SEL" 1 2 285, C4<011>; -P_0x555555d8e760 .param/l "MRS_BANK_START" 1 2 127, +C4<00000000000000000000000000010010>; -P_0x555555d8e7a0 .param/l "OPT_BUS_ABORT" 0 2 49, C4<1>; -P_0x555555d8e7e0 .param/l "OPT_LOWPOWER" 0 2 48, C4<1>; -P_0x555555d8e820 .param/l "PASR" 1 2 273, C4<000>; -P_0x555555d8e860 .param/l "POWER_ON_RESET_HIGH" 1 2 165, +C4<00000000000000110000110101000000>; -P_0x555555d8e8a0 .param/l "PPD" 1 2 313, C4<0>; -P_0x555555d8e8e0 .param/l "PRECHARGE_SLOT" 1 2 143, C4<01>; -P_0x555555d8e920 .param/l "PRECHARGE_TO_ACTIVATE_DELAY" 1 2 214, C4<0001>; -P_0x555555d8e960 .param/l "PRE_REFRESH_DELAY" 1 2 203, C4<000000000000000000000000000000101>; -P_0x555555d8e9a0 .param/l "QOFF" 1 2 300, C4<0>; -P_0x555555d8e9e0 .param/l "RBT" 1 2 308, C4<0>; -P_0x555555d8ea20 .param/l "READ_ACK_PIPE_WIDTH" 1 2 241, +C4<000000000000000000000000000000000110>; -P_0x555555d8ea60 .param/l "READ_DATA" 1 2 262, +C4<00000000000000000000000000001100>; -P_0x555555d8eaa0 .param/l "READ_DELAY" 1 2 240, +C4<00000000000000000000000000000001>; -P_0x555555d8eae0 .param/l "READ_SLOT" 1 2 140, C4<10>; -P_0x555555d8eb20 .param/l "READ_TO_PRECHARGE_DELAY" 1 2 220, C4<0001>; -P_0x555555d8eb60 .param/l "READ_TO_READ_DELAY" 1 2 219, C4<0000>; -P_0x555555d8eba0 .param/l "READ_TO_WRITE_DELAY" 1 2 218, C4<0001>; -P_0x555555d8ebe0 .param/l "REF_IDLE" 1 2 120, +C4<00000000000000000000000000011011>; -P_0x555555d8ec20 .param/l "REPEAT_DQS_ANALYZE" 1 2 266, +C4<00000000000000000000000000000001>; -P_0x555555d8ec60 .param/l "RESET_N" 1 2 124, +C4<00000000000000000000000000010111>; -P_0x555555d8eca0 .param/l "ROW_BITS" 0 2 40, C4<00000000000000000000000000010000>; -P_0x555555d8ece0 .param/l "RST_DONE" 1 2 119, +C4<00000000000000000000000000011011>; -P_0x555555d8ed20 .param/l "RTT_NOM" 1 2 293, C4<011>; -P_0x555555d8ed60 .param/l "RTT_WR" 1 2 277, C4<00>; -P_0x555555d8eda0 .param/l "SRT" 1 2 276, C4<0>; -P_0x555555d8ede0 .param/l "STAGE2_DATA_DEPTH" 1 2 232, C4<000000000000000000000000000000000010>; -P_0x555555d8ee20 .param/l "START_WRITE_LEVEL" 1 2 257, +C4<00000000000000000000000000000111>; -P_0x555555d8ee60 .param/l "STORED_DQS_SIZE" 1 2 265, +C4<00000000000000000000000000000101>; -P_0x555555d8eea0 .param/l "TDQS" 1 2 297, C4<1>; -P_0x555555d8eee0 .param/l "USE_TIMER" 1 2 121, +C4<00000000000000000000000000011010>; -P_0x555555d8ef20 .param/l "WAIT_FOR_FEEDBACK" 1 2 258, +C4<00000000000000000000000000001000>; -P_0x555555d8ef60 .param/l "WB2_ADDR_BITS" 0 2 46, C4<00000000000000000000000000100000>; -P_0x555555d8efa0 .param/l "WB2_DATA_BITS" 0 2 47, C4<00000000000000000000000000100000>; -P_0x555555d8efe0 .param/l "WL_DIS" 1 2 295, C4<0>; -P_0x555555d8f020 .param/l "WL_EN" 1 2 294, C4<1>; -P_0x555555d8f060 .param/l "WR" 1 2 311, C4<011>; -P_0x555555d8f0a0 .param/l "WRITE_SLOT" 1 2 141, C4<11>; -P_0x555555d8f0e0 .param/l "WRITE_TO_PRECHARGE_DELAY" 1 2 223, C4<0100>; -P_0x555555d8f120 .param/l "WRITE_TO_READ_DELAY" 1 2 222, C4<0011>; -P_0x555555d8f160 .param/l "WRITE_TO_WRITE_DELAY" 1 2 221, C4<0000>; -P_0x555555d8f1a0 .param/l "cmd_len" 0 2 58, C4<00000000000000000000000000000011010>; -P_0x555555d8f1e0 .param/l "serdes_ratio" 0 2 52, +C4<00000000000000000000000000000100>; -P_0x555555d8f220 .param/l "tCCD" 1 2 193, +C4<00000000000000000000000000000100>; -P_0x555555d8f260 .param/l "tMOD" 1 2 195, C4<0000000000000000011>; -P_0x555555d8f2a0 .param/l "tMRD" 1 2 185, +C4<00000000000000000000000000000100>; -P_0x555555d8f2e0 .param/l "tRAS" 1 2 170, +C4<00000000000000000000000000100011>; -P_0x555555d8f320 .param/real "tRCD" 1 2 168, Cr; value=13.7500 -P_0x555555d8f360 .param/l "tREFI" 1 2 182, +C4<00000000000000000001111001111000>; -P_0x555555d8f3a0 .param/real "tRFC" 1 2 180, Cr; value=350.000 -P_0x555555d8f3e0 .param/real "tRP" 1 2 169, Cr; value=13.7500 -P_0x555555d8f420 .param/l "tRTP" 1 2 191, +C4<00000000000000000000000000001010>; -P_0x555555d8f460 .param/l "tWLMRD" 1 2 188, C4<0000000000000001010>; -P_0x555555d8f4a0 .param/real "tWLO" 1 2 189, Cr; value=7.50000 -P_0x555555d8f4e0 .param/l "tWLOE" 1 2 190, +C4<00000000000000000000000000000010>; -P_0x555555d8f520 .param/real "tWR" 1 2 186, Cr; value=15.0000 -P_0x555555d8f560 .param/l "tWTR" 1 2 187, +C4<00000000000000000000000000001010>; -P_0x555555d8f5a0 .param/l "tXPR" 1 2 184, +C4<00000000000000000000000101101000>; -P_0x555555d8f5e0 .param/l "tZQinit" 1 2 196, C4<0000000000010000000>; -P_0x555555d8f620 .param/l "wb2_sel_bits" 0 2 56, C4<00000000000000000000000000000100>; -P_0x555555d8f660 .param/l "wb_addr_bits" 0 2 53, C4<00000000000000000000000000000011010>; -P_0x555555d8f6a0 .param/l "wb_data_bits" 0 2 54, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000>; -P_0x555555d8f6e0 .param/l "wb_sel_bits" 0 2 55, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000>; -v0x555555db2260_1 .array/port v0x555555db2260, 1; -L_0x555555d13d90 .functor BUFZ 512, v0x555555db2260_1, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>; -v0x555555db2460_1 .array/port v0x555555db2460, 1; -L_0x555555d211c0 .functor BUFZ 64, v0x555555db2460_1, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>, C4<0000000000000000000000000000000000000000000000000000000000000000>; -L_0x555555d539f0 .functor AND 1, L_0x555555db62a0, L_0x555555dc6540, C4<1>, C4<1>; -L_0x555555d61dc0 .functor BUFZ 512, L_0x555555dc6880, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>, C4<00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000>; -L_0x555555dc6f20 .functor BUFZ 5, L_0x555555dc72e0, C4<00000>, C4<00000>, C4<00000>; -L_0x555555d6eaf0 .functor BUFZ 5, L_0x555555dc7600, C4<00000>, C4<00000>, C4<00000>; -L_0x555555dc7c20 .functor BUFZ 5, L_0x555555dc7990, C4<00000>, C4<00000>, C4<00000>; -L_0x555555dc7e40 .functor BUFZ 5, L_0x555555dc7810, C4<00000>, C4<00000>, C4<00000>; -v0x555555da9120_0 .net *"_ivl_15", 0 0, L_0x555555db62a0; 1 drivers -v0x555555da9220_0 .net *"_ivl_16", 31 0, L_0x555555db63a0; 1 drivers -L_0x7eff80b5c018 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x555555da9300_0 .net *"_ivl_19", 26 0, L_0x7eff80b5c018; 1 drivers -L_0x7eff80b5c060 .functor BUFT 1, C4<00000000000000000000000000001110>, C4<0>, C4<0>, C4<0>; -v0x555555da93c0_0 .net/2u *"_ivl_20", 31 0, L_0x7eff80b5c060; 1 drivers -v0x555555da94a0_0 .net *"_ivl_22", 0 0, L_0x555555dc6540; 1 drivers -v0x555555da95b0_0 .net *"_ivl_29", 511 0, L_0x555555dc6880; 1 drivers -v0x555555da9690_0 .net *"_ivl_31", 2 0, L_0x555555dc6920; 1 drivers -L_0x7eff80b5c0a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; -v0x555555da9770_0 .net *"_ivl_34", 1 0, L_0x7eff80b5c0a8; 1 drivers -v0x555555da9850_0 .net *"_ivl_38", 0 0, L_0x555555dc6b30; 1 drivers -v0x555555da99c0_0 .net *"_ivl_42", 0 0, L_0x555555dc6d80; 1 drivers -v0x555555da9aa0_0 .net *"_ivl_45", 31 0, L_0x555555dc6f90; 1 drivers -L_0x7eff80b5c0f0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>; -v0x555555da9b80_0 .net *"_ivl_48", 26 0, L_0x7eff80b5c0f0; 1 drivers -L_0x7eff80b5c138 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>; -v0x555555da9c60_0 .net/2u *"_ivl_49", 31 0, L_0x7eff80b5c138; 1 drivers -v0x555555da9d40_0 .net *"_ivl_55", 4 0, L_0x555555dc72e0; 1 drivers -v0x555555da9e20_0 .net *"_ivl_57", 4 0, L_0x555555dc73b0; 1 drivers -L_0x7eff80b5c1c8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; -v0x555555da9f00_0 .net *"_ivl_60", 1 0, L_0x7eff80b5c1c8; 1 drivers -v0x555555da9fe0_0 .net *"_ivl_63", 4 0, L_0x555555dc7600; 1 drivers -v0x555555daa0c0_0 .net *"_ivl_65", 4 0, L_0x555555dc76d0; 1 drivers -L_0x7eff80b5c210 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; -v0x555555daa1a0_0 .net *"_ivl_68", 1 0, L_0x7eff80b5c210; 1 drivers -v0x555555daa280_0 .net *"_ivl_71", 4 0, L_0x555555dc7990; 1 drivers -v0x555555daa360_0 .net *"_ivl_73", 4 0, L_0x555555dc7a30; 1 drivers -L_0x7eff80b5c258 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; -v0x555555daa440_0 .net *"_ivl_76", 1 0, L_0x7eff80b5c258; 1 drivers -v0x555555daa520_0 .net *"_ivl_79", 4 0, L_0x555555dc7810; 1 drivers -v0x555555daa600_0 .net *"_ivl_81", 4 0, L_0x555555dc7c90; 1 drivers -L_0x7eff80b5c2a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; -v0x555555daa6e0_0 .net *"_ivl_84", 1 0, L_0x7eff80b5c2a0; 1 drivers -v0x555555daa7c0_0 .net *"_ivl_88", 0 0, L_0x555555dc7f50; 1 drivers -L_0x7eff80b5c2e8 .functor BUFT 1, C4<000010>, C4<0>, C4<0>, C4<0>; -v0x555555daa8a0_0 .net/2u *"_ivl_89", 5 0, L_0x7eff80b5c2e8; 1 drivers -v0x555555daa980_0 .net *"_ivl_91", 5 0, L_0x555555dc8050; 1 drivers -L_0x7eff80b5c330 .functor BUFT 1, C4<000001>, C4<0>, C4<0>, C4<0>; -v0x555555daaa60_0 .net/2u *"_ivl_93", 5 0, L_0x7eff80b5c330; 1 drivers -v0x555555daab40_0 .net *"_ivl_95", 5 0, L_0x555555dc8300; 1 drivers -v0x555555daac20_0 .var "activate_slot_busy", 0 0; -v0x555555daace0 .array "added_read_pipe", 0 7, 3 0; -v0x555555daada0_0 .var "added_read_pipe_max", 3 0; -v0x555555daae80 .array "bank_active_row_d", 0 7, 15 0; -v0x555555dab040 .array "bank_active_row_q", 0 7, 15 0; -v0x555555dab250_0 .var "bank_status_d", 7 0; -v0x555555dab330_0 .var "bank_status_q", 7 0; -v0x555555dab410_0 .var "cmd_ck_en", 0 0; -v0x555555dab4d0 .array "cmd_d", 0 3, 25 0; -v0x555555dab610_0 .var "cmd_odt", 0 0; -v0x555555dab6d0_0 .var "cmd_odt_q", 0 0; -v0x555555dab790 .array "cmd_q", 0 3, 25 0; -v0x555555dab850_0 .var "cmd_reset_n", 0 0; -v0x555555dab910 .array "data_start_index", 0 7, 6 0; -v0x555555dab9d0 .array "delay_before_activate_counter_d", 0 7, 3 0; -v0x555555daba90 .array "delay_before_activate_counter_q", 0 7, 3 0; -v0x555555dabca0 .array "delay_before_precharge_counter_d", 0 7, 3 0; -v0x555555dabd60 .array "delay_before_precharge_counter_q", 0 7, 3 0; -v0x555555dabf70 .array "delay_before_read_counter_d", 0 7, 3 0; -v0x555555dac180 .array "delay_before_read_counter_q", 0 7, 3 0; -v0x555555dac390_0 .var "delay_before_read_data", 3 0; -v0x555555dac470 .array "delay_before_write_counter_d", 0 7, 3 0; -v0x555555dac680 .array "delay_before_write_counter_q", 0 7, 3 0; -v0x555555dac890_0 .var "delay_before_write_level_feedback", 4 0; -v0x555555dac970_0 .var "delay_counter", 15 0; -v0x555555daca50_0 .var "delay_counter_is_zero", 0 0; -v0x555555dacb10 .array "delay_read_pipe", 0 1, 15 0; -v0x555555dacbd0_0 .var "dq_target_index", 5 0; -v0x555555daccb0_0 .var "dqs_bitslip_arrangement", 15 0; -v0x555555dacd90_0 .var "dqs_count_repeat", 3 0; -v0x555555dace70_0 .var "dqs_start_index", 5 0; -v0x555555dacf50_0 .var "dqs_start_index_repeat", 0 0; -v0x555555dad030_0 .var "dqs_start_index_stored", 5 0; -v0x555555dad110_0 .var "dqs_store", 39 0; -v0x555555dad1f0_0 .var "dqs_target_index", 5 0; -v0x555555dad2d0_0 .var "dqs_target_index_orig", 5 0; -v0x555555dad3b0_0 .net "dqs_target_index_value", 5 0, L_0x555555dc83f0; 1 drivers -o0x7eff80ba6c38 .functor BUFZ 16, C4; HiZ drive -v0x555555dad490_0 .net "i_aux", 15 0, o0x7eff80ba6c38; 0 drivers -o0x7eff80ba6c68 .functor BUFZ 1, C4; HiZ drive -v0x555555dad570_0 .net "i_controller_clk", 0 0, o0x7eff80ba6c68; 0 drivers -o0x7eff80ba6c98 .functor BUFZ 1, C4; HiZ drive -v0x555555dad630_0 .net "i_phy_idelayctrl_rdy", 0 0, o0x7eff80ba6c98; 0 drivers -o0x7eff80ba6cc8 .functor BUFZ 64, C4; HiZ drive -v0x555555dad6f0_0 .net "i_phy_iserdes_bitslip_reference", 63 0, o0x7eff80ba6cc8; 0 drivers -o0x7eff80ba6cf8 .functor BUFZ 512, C4; HiZ drive -v0x555555dad7d0_0 .net "i_phy_iserdes_data", 511 0, o0x7eff80ba6cf8; 0 drivers -o0x7eff80ba6d28 .functor BUFZ 64, C4; HiZ drive -v0x555555dad8b0_0 .net "i_phy_iserdes_dqs", 63 0, o0x7eff80ba6d28; 0 drivers -o0x7eff80ba6d58 .functor BUFZ 1, C4; HiZ drive -v0x555555dad990_0 .net "i_rst_n", 0 0, o0x7eff80ba6d58; 0 drivers -o0x7eff80ba6d88 .functor BUFZ 32, C4; HiZ drive -v0x555555dada50_0 .net "i_wb2_addr", 31 0, o0x7eff80ba6d88; 0 drivers -o0x7eff80ba6db8 .functor BUFZ 1, C4; HiZ drive -v0x555555dadb30_0 .net "i_wb2_cyc", 0 0, o0x7eff80ba6db8; 0 drivers -o0x7eff80ba6de8 .functor BUFZ 32, C4; HiZ drive -v0x555555dadbf0_0 .net "i_wb2_data", 31 0, o0x7eff80ba6de8; 0 drivers -o0x7eff80ba6e18 .functor BUFZ 4, C4; HiZ drive -v0x555555dadcd0_0 .net "i_wb2_sel", 3 0, o0x7eff80ba6e18; 0 drivers -o0x7eff80ba6e48 .functor BUFZ 1, C4; HiZ drive -v0x555555daddb0_0 .net "i_wb2_stb", 0 0, o0x7eff80ba6e48; 0 drivers -o0x7eff80ba6e78 .functor BUFZ 1, C4; HiZ drive -v0x555555dade70_0 .net "i_wb2_we", 0 0, o0x7eff80ba6e78; 0 drivers -o0x7eff80ba6ea8 .functor BUFZ 26, C4; HiZ drive -v0x555555dadf30_0 .net "i_wb_addr", 25 0, o0x7eff80ba6ea8; 0 drivers -o0x7eff80ba6ed8 .functor BUFZ 1, C4; HiZ drive -v0x555555dae010_0 .net "i_wb_cyc", 0 0, o0x7eff80ba6ed8; 0 drivers -o0x7eff80ba6f08 .functor BUFZ 512, C4; HiZ drive -v0x555555dae0d0_0 .net "i_wb_data", 511 0, o0x7eff80ba6f08; 0 drivers -o0x7eff80ba6f38 .functor BUFZ 64, C4; HiZ drive -v0x555555dae1b0_0 .net "i_wb_sel", 63 0, o0x7eff80ba6f38; 0 drivers -o0x7eff80ba6f68 .functor BUFZ 1, C4; HiZ drive -v0x555555dae290_0 .net "i_wb_stb", 0 0, o0x7eff80ba6f68; 0 drivers -o0x7eff80ba6f98 .functor BUFZ 1, C4; HiZ drive -v0x555555dae350_0 .net "i_wb_we", 0 0, o0x7eff80ba6f98; 0 drivers -v0x555555dae410 .array "idelay_data_cntvaluein", 0 7, 4 0; -v0x555555dae4d0_0 .var "idelay_data_cntvaluein_prev", 4 0; -v0x555555dae5b0 .array "idelay_dqs_cntvaluein", 0 7, 4 0; -v0x555555dae670_0 .var/i "index", 31 0; -v0x555555dae750_0 .var "index_read_pipe", 0 0; -v0x555555dae810_0 .var "index_wb_data", 0 0; -v0x555555dae8d0_0 .var "initial_dqs", 0 0; -v0x555555dae990_0 .var "instruction", 27 0; -v0x555555daea70_0 .var "instruction_address", 4 0; -v0x555555daeb50_0 .net "issue_read_command", 0 0, L_0x555555dc7120; 1 drivers -L_0x7eff80b5c180 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>; -v0x555555daec10_0 .net "issue_write_command", 0 0, L_0x7eff80b5c180; 1 drivers -v0x555555daecd0_0 .var "lane", 2 0; -v0x555555daedb0_0 .net "o_aux", 15 0, L_0x555555dc6750; 1 drivers -v0x555555daee90_0 .var "o_phy_bitslip", 7 0; -v0x555555daef70_0 .net "o_phy_cmd", 103 0, L_0x555555db60e0; 1 drivers -v0x555555daf050_0 .net "o_phy_data", 511 0, L_0x555555d13d90; 1 drivers -v0x555555daf130_0 .net "o_phy_dm", 63 0, L_0x555555d211c0; 1 drivers -v0x555555daf210_0 .net "o_phy_dq_tri_control", 0 0, L_0x555555dc6e50; 1 drivers -v0x555555daf2d0_0 .net "o_phy_dqs_tri_control", 0 0, L_0x555555dc6c00; 1 drivers -v0x555555daf390_0 .net "o_phy_idelay_data_cntvaluein", 4 0, L_0x555555dc7c20; 1 drivers -v0x555555daf470_0 .var "o_phy_idelay_data_ld", 7 0; -v0x555555daf550_0 .net "o_phy_idelay_dqs_cntvaluein", 4 0, L_0x555555dc7e40; 1 drivers -v0x555555daf630_0 .var "o_phy_idelay_dqs_ld", 7 0; -v0x555555daf710_0 .net "o_phy_odelay_data_cntvaluein", 4 0, L_0x555555dc6f20; 1 drivers -v0x555555daf7f0_0 .var "o_phy_odelay_data_ld", 7 0; -v0x555555daf8d0_0 .net "o_phy_odelay_dqs_cntvaluein", 4 0, L_0x555555d6eaf0; 1 drivers -v0x555555daf9b0_0 .var "o_phy_odelay_dqs_ld", 7 0; -v0x555555dafa90_0 .net "o_phy_toggle_dqs", 0 0, L_0x555555db5f50; 1 drivers -v0x555555dafb50_0 .var "o_wb2_ack", 0 0; -v0x555555dafc10_0 .var "o_wb2_data", 31 0; -v0x555555dafcf0_0 .var "o_wb2_stall", 0 0; -v0x555555dafdb0_0 .net "o_wb_ack", 0 0, L_0x555555d539f0; 1 drivers -v0x555555dafe70 .array "o_wb_ack_read_q", 0 15, 16 0; -v0x555555db0130_0 .net "o_wb_data", 511 0, L_0x555555d61dc0; 1 drivers -v0x555555db0210 .array "o_wb_data_q", 0 1, 511 0; -v0x555555db02d0_0 .var "o_wb_stall", 0 0; -v0x555555db0390_0 .var "o_wb_stall_d", 0 0; -v0x555555db0450_0 .var "o_wb_stall_q", 0 0; -v0x555555db0510 .array "odelay_data_cntvaluein", 0 7, 4 0; -v0x555555db05d0 .array "odelay_dqs_cntvaluein", 0 7, 4 0; -v0x555555db0690_0 .var "pause_counter", 0 0; -v0x555555db0750_0 .var "precharge_slot_busy", 0 0; -v0x555555db0810_0 .var "prev_write_level_feedback", 0 0; -v0x555555db10e0_0 .var "read_data_store", 511 0; -v0x555555db11c0_0 .var "reset_done", 0 0; -v0x555555db1280 .array "shift_reg_read_pipe_d", 0 5, 16 0; -v0x555555db1340 .array "shift_reg_read_pipe_q", 0 5, 16 0; -v0x555555db14c0_0 .var "stage1_aux", 15 0; -v0x555555db15a0_0 .var "stage1_bank", 2 0; -v0x555555db1680_0 .var "stage1_col", 9 0; -v0x555555db1760_0 .var "stage1_data", 511 0; -v0x555555db1840_0 .var "stage1_dm", 63 0; -v0x555555db1920_0 .var "stage1_issue_command", 0 0; -v0x555555db1a00_0 .var "stage1_next_bank", 2 0; -v0x555555db1ae0_0 .var "stage1_next_col", 9 0; -v0x555555db1bc0_0 .var "stage1_next_row", 15 0; -v0x555555db1ca0_0 .var "stage1_pending", 0 0; -v0x555555db1d60_0 .var "stage1_row", 15 0; -v0x555555db1e40_0 .var "stage1_stall", 0 0; -v0x555555db1f00_0 .var "stage1_we", 0 0; -v0x555555db1fc0_0 .var "stage2_aux", 15 0; -v0x555555db20a0_0 .var "stage2_bank", 2 0; -v0x555555db2180_0 .var "stage2_col", 9 0; -v0x555555db2260 .array "stage2_data", 0 1, 511 0; -v0x555555db2380_0 .var "stage2_data_unaligned", 511 0; -v0x555555db2460 .array "stage2_dm", 0 1, 63 0; -v0x555555db2580_0 .var "stage2_dm_unaligned", 63 0; -v0x555555db2660_0 .var "stage2_issue_command", 0 0; -v0x555555db2740_0 .var "stage2_pending", 0 0; -v0x555555db2800_0 .var "stage2_row", 15 0; -v0x555555db28e0_0 .var "stage2_stall", 0 0; -v0x555555db29a0_0 .var "stage2_update", 0 0; -v0x555555db2a60_0 .var "stage2_we", 0 0; -v0x555555db2b20_0 .var "state_calibrate", 4 0; -v0x555555db2c00_0 .var "train_delay", 1 0; -v0x555555db2ce0 .array "unaligned_data", 0 7, 63 0; -v0x555555db2da0 .array "unaligned_dm", 0 7, 7 0; -v0x555555db2e60_0 .var "wb2_addr", 31 0; -v0x555555db2f40_0 .var "wb2_data", 31 0; -v0x555555db3020_0 .var "wb2_phy_idelay_data_cntvaluein", 4 0; -v0x555555db3100_0 .var "wb2_phy_idelay_data_ld", 7 0; -v0x555555db31e0_0 .var "wb2_phy_idelay_dqs_cntvaluein", 4 0; -v0x555555db32c0_0 .var "wb2_phy_idelay_dqs_ld", 7 0; -v0x555555db33a0_0 .var "wb2_phy_odelay_data_cntvaluein", 4 0; -v0x555555db3480_0 .var "wb2_phy_odelay_data_ld", 7 0; -v0x555555db3560_0 .var "wb2_phy_odelay_dqs_cntvaluein", 4 0; -v0x555555db3640_0 .var "wb2_phy_odelay_dqs_ld", 7 0; -v0x555555db3720_0 .var "wb2_sel", 3 0; -v0x555555db3800_0 .var "wb2_stb", 0 0; -v0x555555db38c0_0 .var "wb2_update", 0 0; -v0x555555db3980_0 .var "wb2_we", 0 0; -v0x555555db3a40_0 .var "wb2_write_lane", 2 0; -v0x555555db3b20_0 .var "write_calib_aux", 15 0; -v0x555555db3c00_0 .var "write_calib_col", 9 0; -v0x555555db3ce0_0 .var "write_calib_data", 511 0; -v0x555555db3dc0_0 .var "write_calib_dq", 0 0; -v0x555555db3e80_0 .var "write_calib_dqs", 0 0; -v0x555555db3f40_0 .var "write_calib_odt", 0 0; -v0x555555db4000_0 .var "write_calib_stb", 0 0; -v0x555555db40c0_0 .var "write_calib_we", 0 0; -v0x555555db4180_0 .var "write_dq", 3 0; -v0x555555db4260_0 .var "write_dq_d", 0 0; -v0x555555db4320_0 .var "write_dq_q", 0 0; -v0x555555db43e0_0 .var "write_dqs", 2 0; -v0x555555db44c0_0 .var "write_dqs_d", 0 0; -v0x555555db4580_0 .var "write_dqs_q", 1 0; -v0x555555db4660_0 .var "write_dqs_val", 2 0; -v0x555555db4740_0 .var "write_pattern", 127 0; -E_0x555555cb9a50/0 .event negedge, v0x555555dad990_0; -E_0x555555cb9a50/1 .event posedge, v0x555555dad570_0; -E_0x555555cb9a50 .event/or E_0x555555cb9a50/0, E_0x555555cb9a50/1; -E_0x555555ba4230/0 .event anyedge, v0x555555dab6d0_0, v0x555555db3f40_0, v0x555555dae990_0, v0x555555db3e80_0; -v0x555555dab040_0 .array/port v0x555555dab040, 0; -v0x555555dab040_1 .array/port v0x555555dab040, 1; -E_0x555555ba4230/1 .event anyedge, v0x555555db3dc0_0, v0x555555dab330_0, v0x555555dab040_0, v0x555555dab040_1; -v0x555555dab040_2 .array/port v0x555555dab040, 2; -v0x555555dab040_3 .array/port v0x555555dab040, 3; -v0x555555dab040_4 .array/port v0x555555dab040, 4; -v0x555555dab040_5 .array/port v0x555555dab040, 5; -E_0x555555ba4230/2 .event anyedge, v0x555555dab040_2, v0x555555dab040_3, v0x555555dab040_4, v0x555555dab040_5; -v0x555555dab040_6 .array/port v0x555555dab040, 6; -v0x555555dab040_7 .array/port v0x555555dab040, 7; -E_0x555555ba4230/3 .event anyedge, v0x555555dab040_6, v0x555555dab040_7, v0x555555daca50_0, v0x555555dab610_0; -E_0x555555ba4230/4 .event anyedge, v0x555555daeb50_0, v0x555555dab410_0, v0x555555dab850_0, v0x555555daec10_0; -v0x555555dabd60_0 .array/port v0x555555dabd60, 0; -v0x555555dabd60_1 .array/port v0x555555dabd60, 1; -v0x555555dabd60_2 .array/port v0x555555dabd60, 2; -v0x555555dabd60_3 .array/port v0x555555dabd60, 3; -E_0x555555ba4230/5 .event anyedge, v0x555555dabd60_0, v0x555555dabd60_1, v0x555555dabd60_2, v0x555555dabd60_3; -v0x555555dabd60_4 .array/port v0x555555dabd60, 4; -v0x555555dabd60_5 .array/port v0x555555dabd60, 5; -v0x555555dabd60_6 .array/port v0x555555dabd60, 6; -v0x555555dabd60_7 .array/port v0x555555dabd60, 7; -E_0x555555ba4230/6 .event anyedge, v0x555555dabd60_4, v0x555555dabd60_5, v0x555555dabd60_6, v0x555555dabd60_7; -v0x555555daba90_0 .array/port v0x555555daba90, 0; -v0x555555daba90_1 .array/port v0x555555daba90, 1; -v0x555555daba90_2 .array/port v0x555555daba90, 2; -v0x555555daba90_3 .array/port v0x555555daba90, 3; -E_0x555555ba4230/7 .event anyedge, v0x555555daba90_0, v0x555555daba90_1, v0x555555daba90_2, v0x555555daba90_3; -v0x555555daba90_4 .array/port v0x555555daba90, 4; -v0x555555daba90_5 .array/port v0x555555daba90, 5; -v0x555555daba90_6 .array/port v0x555555daba90, 6; -v0x555555daba90_7 .array/port v0x555555daba90, 7; -E_0x555555ba4230/8 .event anyedge, v0x555555daba90_4, v0x555555daba90_5, v0x555555daba90_6, v0x555555daba90_7; -v0x555555dac680_0 .array/port v0x555555dac680, 0; -v0x555555dac680_1 .array/port v0x555555dac680, 1; -v0x555555dac680_2 .array/port v0x555555dac680, 2; -v0x555555dac680_3 .array/port v0x555555dac680, 3; -E_0x555555ba4230/9 .event anyedge, v0x555555dac680_0, v0x555555dac680_1, v0x555555dac680_2, v0x555555dac680_3; -v0x555555dac680_4 .array/port v0x555555dac680, 4; -v0x555555dac680_5 .array/port v0x555555dac680, 5; -v0x555555dac680_6 .array/port v0x555555dac680, 6; -v0x555555dac680_7 .array/port v0x555555dac680, 7; -E_0x555555ba4230/10 .event anyedge, v0x555555dac680_4, v0x555555dac680_5, v0x555555dac680_6, v0x555555dac680_7; -v0x555555dac180_0 .array/port v0x555555dac180, 0; -v0x555555dac180_1 .array/port v0x555555dac180, 1; -v0x555555dac180_2 .array/port v0x555555dac180, 2; -v0x555555dac180_3 .array/port v0x555555dac180, 3; -E_0x555555ba4230/11 .event anyedge, v0x555555dac180_0, v0x555555dac180_1, v0x555555dac180_2, v0x555555dac180_3; -v0x555555dac180_4 .array/port v0x555555dac180, 4; -v0x555555dac180_5 .array/port v0x555555dac180, 5; -v0x555555dac180_6 .array/port v0x555555dac180, 6; -v0x555555dac180_7 .array/port v0x555555dac180, 7; -E_0x555555ba4230/12 .event anyedge, v0x555555dac180_4, v0x555555dac180_5, v0x555555dac180_6, v0x555555dac180_7; -v0x555555db1340_0 .array/port v0x555555db1340, 0; -v0x555555db1340_1 .array/port v0x555555db1340, 1; -v0x555555db1340_2 .array/port v0x555555db1340, 2; -v0x555555db1340_3 .array/port v0x555555db1340, 3; -E_0x555555ba4230/13 .event anyedge, v0x555555db1340_0, v0x555555db1340_1, v0x555555db1340_2, v0x555555db1340_3; -v0x555555db1340_4 .array/port v0x555555db1340, 4; -v0x555555db1340_5 .array/port v0x555555db1340, 5; -E_0x555555ba4230/14 .event anyedge, v0x555555db1340_4, v0x555555db1340_5, v0x555555db2740_0, v0x555555db20a0_0; -E_0x555555ba4230/15 .event anyedge, v0x555555db2800_0, v0x555555db2a60_0, v0x555555db1fc0_0, v0x555555db2180_0; -E_0x555555ba4230/16 .event anyedge, v0x555555db1ca0_0, v0x555555db1a00_0, v0x555555db1bc0_0, v0x555555db0750_0; -v0x555555dabf70_0 .array/port v0x555555dabf70, 0; -v0x555555dabf70_1 .array/port v0x555555dabf70, 1; -v0x555555dabf70_2 .array/port v0x555555dabf70, 2; -E_0x555555ba4230/17 .event anyedge, v0x555555daac20_0, v0x555555dabf70_0, v0x555555dabf70_1, v0x555555dabf70_2; -v0x555555dabf70_3 .array/port v0x555555dabf70, 3; -v0x555555dabf70_4 .array/port v0x555555dabf70, 4; -v0x555555dabf70_5 .array/port v0x555555dabf70, 5; -v0x555555dabf70_6 .array/port v0x555555dabf70, 6; -E_0x555555ba4230/18 .event anyedge, v0x555555dabf70_3, v0x555555dabf70_4, v0x555555dabf70_5, v0x555555dabf70_6; -v0x555555dabf70_7 .array/port v0x555555dabf70, 7; -v0x555555daae80_0 .array/port v0x555555daae80, 0; -E_0x555555ba4230/19 .event anyedge, v0x555555dabf70_7, v0x555555db15a0_0, v0x555555dab250_0, v0x555555daae80_0; -v0x555555daae80_1 .array/port v0x555555daae80, 1; -v0x555555daae80_2 .array/port v0x555555daae80, 2; -v0x555555daae80_3 .array/port v0x555555daae80, 3; -v0x555555daae80_4 .array/port v0x555555daae80, 4; -E_0x555555ba4230/20 .event anyedge, v0x555555daae80_1, v0x555555daae80_2, v0x555555daae80_3, v0x555555daae80_4; -v0x555555daae80_5 .array/port v0x555555daae80, 5; -v0x555555daae80_6 .array/port v0x555555daae80, 6; -v0x555555daae80_7 .array/port v0x555555daae80, 7; -E_0x555555ba4230/21 .event anyedge, v0x555555daae80_5, v0x555555daae80_6, v0x555555daae80_7, v0x555555db1d60_0; -v0x555555dac470_0 .array/port v0x555555dac470, 0; -v0x555555dac470_1 .array/port v0x555555dac470, 1; -v0x555555dac470_2 .array/port v0x555555dac470, 2; -E_0x555555ba4230/22 .event anyedge, v0x555555db1f00_0, v0x555555dac470_0, v0x555555dac470_1, v0x555555dac470_2; -v0x555555dac470_3 .array/port v0x555555dac470, 3; -v0x555555dac470_4 .array/port v0x555555dac470, 4; -v0x555555dac470_5 .array/port v0x555555dac470, 5; -v0x555555dac470_6 .array/port v0x555555dac470, 6; -E_0x555555ba4230/23 .event anyedge, v0x555555dac470_3, v0x555555dac470_4, v0x555555dac470_5, v0x555555dac470_6; -v0x555555dac470_7 .array/port v0x555555dac470, 7; -E_0x555555ba4230/24 .event anyedge, v0x555555dac470_7, v0x555555db0450_0, v0x555555db28e0_0, v0x555555dae290_0; -E_0x555555ba4230/25 .event anyedge, v0x555555db1e40_0, v0x555555dae010_0; -E_0x555555ba4230 .event/or E_0x555555ba4230/0, E_0x555555ba4230/1, E_0x555555ba4230/2, E_0x555555ba4230/3, E_0x555555ba4230/4, E_0x555555ba4230/5, E_0x555555ba4230/6, E_0x555555ba4230/7, E_0x555555ba4230/8, E_0x555555ba4230/9, E_0x555555ba4230/10, E_0x555555ba4230/11, E_0x555555ba4230/12, E_0x555555ba4230/13, E_0x555555ba4230/14, E_0x555555ba4230/15, E_0x555555ba4230/16, E_0x555555ba4230/17, E_0x555555ba4230/18, E_0x555555ba4230/19, E_0x555555ba4230/20, E_0x555555ba4230/21, E_0x555555ba4230/22, E_0x555555ba4230/23, E_0x555555ba4230/24, E_0x555555ba4230/25; -L_0x555555db5f50 .part v0x555555db4660_0, 0, 1; -v0x555555dab4d0_0 .array/port v0x555555dab4d0, 0; -v0x555555dab4d0_1 .array/port v0x555555dab4d0, 1; -v0x555555dab4d0_2 .array/port v0x555555dab4d0, 2; -v0x555555dab4d0_3 .array/port v0x555555dab4d0, 3; -L_0x555555db60e0 .concat [ 26 26 26 26], v0x555555dab4d0_0, v0x555555dab4d0_1, v0x555555dab4d0_2, v0x555555dab4d0_3; -v0x555555dafe70_0 .array/port v0x555555dafe70, 0; -L_0x555555db62a0 .part v0x555555dafe70_0, 0, 1; -L_0x555555db63a0 .concat [ 5 27 0 0], v0x555555db2b20_0, L_0x7eff80b5c018; -L_0x555555dc6540 .cmp/eq 32, L_0x555555db63a0, L_0x7eff80b5c060; -L_0x555555dc6750 .part v0x555555dafe70_0, 1, 16; -L_0x555555dc6880 .array/port v0x555555db0210, L_0x555555dc6920; -L_0x555555dc6920 .concat [ 1 2 0 0], v0x555555dae810_0, L_0x7eff80b5c0a8; -L_0x555555dc6b30 .part v0x555555db43e0_0, 2, 1; -L_0x555555dc6c00 .reduce/nor L_0x555555dc6b30; -L_0x555555dc6d80 .part v0x555555db4180_0, 3, 1; -L_0x555555dc6e50 .reduce/nor L_0x555555dc6d80; -L_0x555555dc6f90 .concat [ 5 27 0 0], v0x555555db2b20_0, L_0x7eff80b5c0f0; -L_0x555555dc7120 .cmp/eq 32, L_0x555555dc6f90, L_0x7eff80b5c138; -L_0x555555dc72e0 .array/port v0x555555db0510, L_0x555555dc73b0; -L_0x555555dc73b0 .concat [ 3 2 0 0], v0x555555daecd0_0, L_0x7eff80b5c1c8; -L_0x555555dc7600 .array/port v0x555555db05d0, L_0x555555dc76d0; -L_0x555555dc76d0 .concat [ 3 2 0 0], v0x555555daecd0_0, L_0x7eff80b5c210; -L_0x555555dc7990 .array/port v0x555555dae410, L_0x555555dc7a30; -L_0x555555dc7a30 .concat [ 3 2 0 0], v0x555555daecd0_0, L_0x7eff80b5c258; -L_0x555555dc7810 .array/port v0x555555dae5b0, L_0x555555dc7c90; -L_0x555555dc7c90 .concat [ 3 2 0 0], v0x555555daecd0_0, L_0x7eff80b5c2a0; -L_0x555555dc7f50 .part v0x555555dad030_0, 0, 1; -L_0x555555dc8050 .arith/sum 6, v0x555555dad030_0, L_0x7eff80b5c2e8; -L_0x555555dc8300 .arith/sum 6, v0x555555dad030_0, L_0x7eff80b5c330; -L_0x555555dc83f0 .functor MUXZ 6, L_0x555555dc8300, L_0x555555dc8050, L_0x555555dc7f50, C4<>; -S_0x555555d03780 .scope function.vec4.s3, "WRA_mode_register_value" "WRA_mode_register_value" 2 1690, 2 1690 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555d2a0b0_0 .var/i "WRA", 31 0; -; Variable WRA_mode_register_value is vec4 return value of scope S_0x555555d03780 -TD_ddr3_controller.WRA_mode_register_value ; - %load/vec4 v0x555555d2a0b0_0; - %addi 1, 0, 32; - %dup/vec4; - %pushi/vec4 1, 0, 32; - %cmp/u; - %jmp/1 T_0.0, 6; - %dup/vec4; - %pushi/vec4 2, 0, 32; - %cmp/u; - %jmp/1 T_0.1, 6; - %dup/vec4; - %pushi/vec4 3, 0, 32; - %cmp/u; - %jmp/1 T_0.2, 6; - %dup/vec4; - %pushi/vec4 4, 0, 32; - %cmp/u; - %jmp/1 T_0.3, 6; - %dup/vec4; - %pushi/vec4 5, 0, 32; - %cmp/u; - %jmp/1 T_0.4, 6; - %dup/vec4; - %pushi/vec4 6, 0, 32; - %cmp/u; - %jmp/1 T_0.5, 6; - %dup/vec4; - %pushi/vec4 7, 0, 32; - %cmp/u; - %jmp/1 T_0.6, 6; - %dup/vec4; - %pushi/vec4 8, 0, 32; - %cmp/u; - %jmp/1 T_0.7, 6; - %dup/vec4; - %pushi/vec4 9, 0, 32; - %cmp/u; - %jmp/1 T_0.8, 6; - %dup/vec4; - %pushi/vec4 10, 0, 32; - %cmp/u; - %jmp/1 T_0.9, 6; - %dup/vec4; - %pushi/vec4 11, 0, 32; - %cmp/u; - %jmp/1 T_0.10, 6; - %dup/vec4; - %pushi/vec4 12, 0, 32; - %cmp/u; - %jmp/1 T_0.11, 6; - %dup/vec4; - %pushi/vec4 13, 0, 32; - %cmp/u; - %jmp/1 T_0.12, 6; - %dup/vec4; - %pushi/vec4 14, 0, 32; - %cmp/u; - %jmp/1 T_0.13, 6; - %dup/vec4; - %pushi/vec4 15, 0, 32; - %cmp/u; - %jmp/1 T_0.14, 6; - %dup/vec4; - %pushi/vec4 16, 0, 32; - %cmp/u; - %jmp/1 T_0.15, 6; - %pushi/vec4 0, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.0 ; - %pushi/vec4 1, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.1 ; - %pushi/vec4 1, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.2 ; - %pushi/vec4 1, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.3 ; - %pushi/vec4 1, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.4 ; - %pushi/vec4 1, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.5 ; - %pushi/vec4 2, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.6 ; - %pushi/vec4 3, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.7 ; - %pushi/vec4 4, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.8 ; - %pushi/vec4 5, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.9 ; - %pushi/vec4 5, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.10 ; - %pushi/vec4 6, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.11 ; - %pushi/vec4 6, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.12 ; - %pushi/vec4 7, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.13 ; - %pushi/vec4 7, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.14 ; - %pushi/vec4 0, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.15 ; - %pushi/vec4 0, 0, 3; - %ret/vec4 0, 0, 3; Assign to WRA_mode_register_value (store_vec4_to_lval) - %jmp T_0.17; -T_0.17 ; - %pop/vec4 1; - %end; -S_0x555555da6970 .scope function.vec4.s4, "find_delay" "find_delay" 2 1767, 2 1767 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555d472f0_0 .var/i "delay_nCK", 31 0; -v0x555555d474d0_0 .var "end_slot", 1 0; -; Variable find_delay is vec4 return value of scope S_0x555555da6970 -v0x555555d64a10_0 .var/i "k", 31 0; -v0x555555d64ab0_0 .var "start_slot", 1 0; -TD_ddr3_controller.find_delay ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555d64a10_0, 0, 32; -T_1.18 ; - %pushi/vec4 4, 0, 32; - %load/vec4 v0x555555d64ab0_0; - %pad/u 32; - %sub; - %load/vec4 v0x555555d474d0_0; - %pad/u 32; - %add; - %load/vec4 v0x555555d64a10_0; - %muli 4, 0, 32; - %add; - %load/vec4 v0x555555d472f0_0; - %cmp/u; - %jmp/0xz T_1.19, 5; - %load/vec4 v0x555555d64a10_0; - %addi 1, 0, 32; - %store/vec4 v0x555555d64a10_0, 0, 32; - %jmp T_1.18; -T_1.19 ; - %load/vec4 v0x555555d64a10_0; - %parti/s 4, 0, 2; - %ret/vec4 0, 0, 4; Assign to find_delay (store_vec4_to_lval) - %end; -S_0x555555da6ce0 .scope generate, "genblk1" "genblk1" 2 1233, 2 1233 0, S_0x555555cfe490; - .timescale 0 0; -S_0x555555da6ec0 .scope function.vec4.s2, "get_slot" "get_slot" 2 1708, 2 1708 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555da70a0_0 .var "anticipate_activate_slot", 1 0; -v0x555555da7180_0 .var "anticipate_precharge_slot", 1 0; -v0x555555da7260_0 .var "cmd", 3 0; -v0x555555da7320_0 .var/i "delay", 31 0; -; Variable get_slot is vec4 return value of scope S_0x555555da6ec0 -v0x555555da7530_0 .var "read_slot", 1 0; -v0x555555da7610_0 .var "slot_number", 1 0; -v0x555555da76f0_0 .var "write_slot", 1 0; -TD_ddr3_controller.get_slot ; - %pushi/vec4 6, 0, 32; - %store/vec4 v0x555555da7320_0, 0, 32; - %pushi/vec4 0, 0, 2; - %store/vec4 v0x555555da7610_0, 0, 2; -T_2.20 ; - %load/vec4 v0x555555da7320_0; - %cmpi/ne 0, 0, 32; - %jmp/0xz T_2.21, 4; - %load/vec4 v0x555555da7610_0; - %subi 1, 0, 2; - %store/vec4 v0x555555da7610_0, 0, 2; - %load/vec4 v0x555555da7320_0; - %subi 1, 0, 32; - %store/vec4 v0x555555da7320_0, 0, 32; - %jmp T_2.20; -T_2.21 ; - %load/vec4 v0x555555da7610_0; - %store/vec4 v0x555555da7530_0, 0, 2; - %pushi/vec4 5, 0, 32; - %store/vec4 v0x555555da7320_0, 0, 32; - %pushi/vec4 0, 0, 2; - %store/vec4 v0x555555da7610_0, 0, 2; -T_2.22 ; - %load/vec4 v0x555555da7320_0; - %cmpi/ne 0, 0, 32; - %jmp/0xz T_2.23, 4; - %load/vec4 v0x555555da7610_0; - %subi 1, 0, 2; - %store/vec4 v0x555555da7610_0, 0, 2; - %load/vec4 v0x555555da7320_0; - %subi 1, 0, 32; - %store/vec4 v0x555555da7320_0, 0, 32; - %jmp T_2.22; -T_2.23 ; - %load/vec4 v0x555555da7610_0; - %store/vec4 v0x555555da76f0_0, 0, 2; - %load/vec4 v0x555555da7530_0; - %store/vec4 v0x555555da7610_0, 0, 2; - %pushi/vec4 13, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %store/vec4 v0x555555da7320_0, 0, 32; - %load/vec4 v0x555555da7610_0; - %store/vec4 v0x555555da7610_0, 0, 2; -T_2.24 ; - %load/vec4 v0x555555da7320_0; - %cmpi/ne 0, 0, 32; - %jmp/0xz T_2.25, 4; - %load/vec4 v0x555555da7610_0; - %subi 1, 0, 2; - %store/vec4 v0x555555da7610_0, 0, 2; - %load/vec4 v0x555555da7320_0; - %subi 1, 0, 32; - %store/vec4 v0x555555da7320_0, 0, 32; - %jmp T_2.24; -T_2.25 ; - %load/vec4 v0x555555da7610_0; - %store/vec4 v0x555555da70a0_0, 0, 2; -T_2.26 ; - %load/vec4 v0x555555da70a0_0; - %load/vec4 v0x555555da76f0_0; - %cmp/e; - %jmp/1 T_2.28, 4; - %flag_mov 8, 4; - %load/vec4 v0x555555da70a0_0; - %load/vec4 v0x555555da7530_0; - %cmp/e; - %flag_or 4, 8; -T_2.28; - %jmp/0xz T_2.27, 4; - %load/vec4 v0x555555da70a0_0; - %subi 1, 0, 2; - %store/vec4 v0x555555da70a0_0, 0, 2; - %jmp T_2.26; -T_2.27 ; - %pushi/vec4 0, 0, 2; - %store/vec4 v0x555555da7180_0, 0, 2; -T_2.29 ; - %load/vec4 v0x555555da7180_0; - %load/vec4 v0x555555da76f0_0; - %cmp/e; - %jmp/1 T_2.32, 4; - %flag_mov 8, 4; - %load/vec4 v0x555555da7180_0; - %load/vec4 v0x555555da7530_0; - %cmp/e; - %flag_or 4, 8; -T_2.32; - %jmp/1 T_2.31, 4; - %flag_mov 8, 4; - %load/vec4 v0x555555da7180_0; - %load/vec4 v0x555555da70a0_0; - %cmp/e; - %flag_or 4, 8; -T_2.31; - %jmp/0xz T_2.30, 4; - %load/vec4 v0x555555da7180_0; - %subi 1, 0, 2; - %store/vec4 v0x555555da7180_0, 0, 2; - %jmp T_2.29; -T_2.30 ; - %load/vec4 v0x555555da7260_0; - %dup/vec4; - %pushi/vec4 5, 0, 4; - %cmp/u; - %jmp/1 T_2.33, 6; - %dup/vec4; - %pushi/vec4 4, 0, 4; - %cmp/u; - %jmp/1 T_2.34, 6; - %dup/vec4; - %pushi/vec4 3, 0, 4; - %cmp/u; - %jmp/1 T_2.35, 6; - %dup/vec4; - %pushi/vec4 2, 0, 4; - %cmp/u; - %jmp/1 T_2.36, 6; - %jmp T_2.38; -T_2.33 ; - %load/vec4 v0x555555da7530_0; - %ret/vec4 0, 0, 2; Assign to get_slot (store_vec4_to_lval) - %jmp T_2.38; -T_2.34 ; - %load/vec4 v0x555555da76f0_0; - %ret/vec4 0, 0, 2; Assign to get_slot (store_vec4_to_lval) - %jmp T_2.38; -T_2.35 ; - %load/vec4 v0x555555da70a0_0; - %ret/vec4 0, 0, 2; Assign to get_slot (store_vec4_to_lval) - %jmp T_2.38; -T_2.36 ; - %load/vec4 v0x555555da7180_0; - %ret/vec4 0, 0, 2; Assign to get_slot (store_vec4_to_lval) - %jmp T_2.38; -T_2.38 ; - %pop/vec4 1; - %end; -S_0x555555da77d0 .scope function.vec4.u32, "max" "max" 2 1683, 2 1683 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555da7a00_0 .var/i "a", 31 0; -v0x555555da7b00_0 .var/i "b", 31 0; -; Variable max is vec4 return value of scope S_0x555555da77d0 -TD_ddr3_controller.max ; - %load/vec4 v0x555555da7b00_0; - %load/vec4 v0x555555da7a00_0; - %cmp/s; - %flag_or 5, 4; - %jmp/0xz T_3.39, 5; - %load/vec4 v0x555555da7a00_0; - %ret/vec4 0, 0, 32; Assign to max (store_vec4_to_lval) - %jmp T_3.40; -T_3.39 ; - %load/vec4 v0x555555da7b00_0; - %ret/vec4 0, 0, 32; Assign to max (store_vec4_to_lval) -T_3.40 ; - %end; -S_0x555555da7ca0 .scope function.vec4.s19, "nCK_to_cycles" "nCK_to_cycles" 2 1655, 2 1655 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555da7e80_0 .var/i "nCK", 31 0; -; Variable nCK_to_cycles is vec4 return value of scope S_0x555555da7ca0 -v0x555555da8060_0 .var/i "result", 31 0; -TD_ddr3_controller.nCK_to_cycles ; - %load/vec4 v0x555555da7e80_0; - %cvt/rv/s; - %pushi/real 1073741824, 4066; load=1.00000 - %mul/wr; - %pushi/vec4 4, 0, 32; - %cvt/rv/s; - %div/wr; - %vpi_func/r 2 1658 "$ceil", W<0,r> {0 1 0}; - %vpi_func 2 1658 "$rtoi" 32, W<0,r> {0 1 0}; - %store/vec4 v0x555555da8060_0, 0, 32; - %load/vec4 v0x555555da8060_0; - %parti/s 19, 0, 2; - %ret/vec4 0, 0, 19; Assign to nCK_to_cycles (store_vec4_to_lval) - %end; -S_0x555555da8120 .scope function.vec4.u32, "nCK_to_ns" "nCK_to_ns" 2 1674, 2 1674 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555da8300_0 .var/i "nCK", 31 0; -; Variable nCK_to_ns is vec4 return value of scope S_0x555555da8120 -TD_ddr3_controller.nCK_to_ns ; - %load/vec4 v0x555555da8300_0; - %cvt/rv/s; - %pushi/real 1073741824, 4066; load=1.00000 - %mul/wr; - %pushi/real 1342177280, 4067; load=2.50000 - %mul/wr; - %vpi_func/r 2 1675 "$ceil", W<0,r> {0 1 0}; - %vpi_func 2 1675 "$rtoi" 32, W<0,r> {0 1 0}; - %ret/vec4 0, 0, 32; Assign to nCK_to_ns (store_vec4_to_lval) - %end; -S_0x555555da84e0 .scope function.vec4.s19, "ns_to_cycles" "ns_to_cycles" 2 1646, 2 1646 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555da86c0_0 .var/i "ns", 31 0; -; Variable ns_to_cycles is vec4 return value of scope S_0x555555da84e0 -v0x555555da88a0_0 .var/i "result", 31 0; -TD_ddr3_controller.ns_to_cycles ; - %load/vec4 v0x555555da86c0_0; - %cvt/rv/s; - %pushi/real 1073741824, 4066; load=1.00000 - %mul/wr; - %pushi/real 1342177280, 4069; load=10.0000 - %div/wr; - %vpi_func/r 2 1649 "$ceil", W<0,r> {0 1 0}; - %vpi_func 2 1649 "$rtoi" 32, W<0,r> {0 1 0}; - %store/vec4 v0x555555da88a0_0, 0, 32; - %load/vec4 v0x555555da88a0_0; - %parti/s 19, 0, 2; - %ret/vec4 0, 0, 19; Assign to ns_to_cycles (store_vec4_to_lval) - %end; -S_0x555555da8960 .scope function.vec4.u32, "ns_to_nCK" "ns_to_nCK" 2 1665, 2 1665 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555da8bd0_0 .var/i "ns", 31 0; -; Variable ns_to_nCK is vec4 return value of scope S_0x555555da8960 -TD_ddr3_controller.ns_to_nCK ; - %load/vec4 v0x555555da8bd0_0; - %cvt/rv/s; - %pushi/real 1073741824, 4066; load=1.00000 - %mul/wr; - %pushi/real 1342177280, 4067; load=2.50000 - %div/wr; - %vpi_func/r 2 1666 "$ceil", W<0,r> {0 1 0}; - %vpi_func 2 1666 "$rtoi" 32, W<0,r> {0 1 0}; - %ret/vec4 0, 0, 32; Assign to ns_to_nCK (store_vec4_to_lval) - %end; -S_0x555555da8db0 .scope function.vec4.s28, "read_rom_instruction" "read_rom_instruction" 2 508, 2 508 0, S_0x555555cfe490; - .timescale 0 0; -v0x555555da8f40_0 .var "instruction_address", 4 0; -; Variable read_rom_instruction is vec4 return value of scope S_0x555555da8db0 -TD_ddr3_controller.read_rom_instruction ; - %load/vec4 v0x555555da8f40_0; - %dup/vec4; - %pushi/vec4 0, 0, 5; - %cmp/u; - %jmp/1 T_8.41, 6; - %dup/vec4; - %pushi/vec4 1, 0, 5; - %cmp/u; - %jmp/1 T_8.42, 6; - %dup/vec4; - %pushi/vec4 2, 0, 5; - %cmp/u; - %jmp/1 T_8.43, 6; - %dup/vec4; - %pushi/vec4 3, 0, 5; - %cmp/u; - %jmp/1 T_8.44, 6; - %dup/vec4; - %pushi/vec4 4, 0, 5; - %cmp/u; - %jmp/1 T_8.45, 6; - %dup/vec4; - %pushi/vec4 5, 0, 5; - %cmp/u; - %jmp/1 T_8.46, 6; - %dup/vec4; - %pushi/vec4 6, 0, 5; - %cmp/u; - %jmp/1 T_8.47, 6; - %dup/vec4; - %pushi/vec4 7, 0, 5; - %cmp/u; - %jmp/1 T_8.48, 6; - %dup/vec4; - %pushi/vec4 8, 0, 5; - %cmp/u; - %jmp/1 T_8.49, 6; - %dup/vec4; - %pushi/vec4 9, 0, 5; - %cmp/u; - %jmp/1 T_8.50, 6; - %dup/vec4; - %pushi/vec4 10, 0, 5; - %cmp/u; - %jmp/1 T_8.51, 6; - %dup/vec4; - %pushi/vec4 11, 0, 5; - %cmp/u; - %jmp/1 T_8.52, 6; - %dup/vec4; - %pushi/vec4 12, 0, 5; - %cmp/u; - %jmp/1 T_8.53, 6; - %dup/vec4; - %pushi/vec4 13, 0, 5; - %cmp/u; - %jmp/1 T_8.54, 6; - %dup/vec4; - %pushi/vec4 14, 0, 5; - %cmp/u; - %jmp/1 T_8.55, 6; - %dup/vec4; - %pushi/vec4 15, 0, 5; - %cmp/u; - %jmp/1 T_8.56, 6; - %dup/vec4; - %pushi/vec4 16, 0, 5; - %cmp/u; - %jmp/1 T_8.57, 6; - %dup/vec4; - %pushi/vec4 17, 0, 5; - %cmp/u; - %jmp/1 T_8.58, 6; - %dup/vec4; - %pushi/vec4 18, 0, 5; - %cmp/u; - %jmp/1 T_8.59, 6; - %dup/vec4; - %pushi/vec4 19, 0, 5; - %cmp/u; - %jmp/1 T_8.60, 6; - %dup/vec4; - %pushi/vec4 20, 0, 5; - %cmp/u; - %jmp/1 T_8.61, 6; - %dup/vec4; - %pushi/vec4 21, 0, 5; - %cmp/u; - %jmp/1 T_8.62, 6; - %dup/vec4; - %pushi/vec4 22, 0, 5; - %cmp/u; - %jmp/1 T_8.63, 6; - %pushi/vec4 28835840, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.41 ; - %pushi/vec4 8, 0, 5; - %concati/vec4 7, 0, 4; - %pushi/vec4 200, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %concat/vec4; draw_concat_vec4 - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.42 ; - %pushi/vec4 9, 0, 5; - %concati/vec4 7, 0, 4; - %pushi/vec4 500, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %concat/vec4; draw_concat_vec4 - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.43 ; - %pushi/vec4 11, 0, 5; - %concati/vec4 7, 0, 4; - %pushi/vec4 360, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %concat/vec4; draw_concat_vec4 - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.44 ; - %pushi/vec4 25296960, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.45 ; - %pushi/vec4 25362432, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.46 ; - %pushi/vec4 25233476, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.47 ; - %pushi/vec4 58722080, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.48 ; - %pushi/vec4 95944707, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.49 ; - %pushi/vec4 128974976, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.50 ; - %pushi/vec4 15, 0, 5; - %concati/vec4 2, 0, 4; - %pushi/vec4 14, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %concat/vec4; draw_concat_vec4 - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.51 ; - %pushi/vec4 25362436, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.52 ; - %pushi/vec4 95944707, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.53 ; - %pushi/vec4 95944706, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.54 ; - %pushi/vec4 25362432, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.55 ; - %pushi/vec4 25233604, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.56 ; - %pushi/vec4 95944714, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.57 ; - %pushi/vec4 95944706, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.58 ; - %pushi/vec4 25233476, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.59 ; - %pushi/vec4 95944707, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.60 ; - %pushi/vec4 15, 0, 5; - %concati/vec4 2, 0, 4; - %pushi/vec4 14, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %concat/vec4; draw_concat_vec4 - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.61 ; - %pushi/vec4 11, 0, 5; - %concati/vec4 1, 0, 4; - %pushi/vec4 350, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %concat/vec4; draw_concat_vec4 - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.62 ; - %pushi/vec4 27, 0, 5; - %concati/vec4 7, 0, 4; - %pushi/vec4 7800, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %concat/vec4; draw_concat_vec4 - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.63 ; - %pushi/vec4 95944709, 0, 28; - %ret/vec4 0, 0, 28; Assign to read_rom_instruction (store_vec4_to_lval) - %jmp T_8.65; -T_8.65 ; - %pop/vec4 1; - %end; -S_0x555555d02bb0 .scope module, "mini_fifo" "mini_fifo" 2 3346; - .timescale 0 0; - .port_info 0 /INPUT 1 "i_clk"; - .port_info 1 /INPUT 1 "i_rst_n"; - .port_info 2 /INPUT 1 "read_fifo"; - .port_info 3 /INPUT 1 "write_fifo"; - .port_info 4 /OUTPUT 1 "empty"; - .port_info 5 /OUTPUT 1 "full"; - .port_info 6 /INPUT 8 "write_data"; - .port_info 7 /OUTPUT 8 "read_data"; - .port_info 8 /OUTPUT 8 "read_data_next"; -P_0x555555b810b0 .param/l "DATA_WIDTH" 0 2 3348, +C4<00000000000000000000000000001000>; -P_0x555555b810f0 .param/l "FIFO_WIDTH" 0 2 3347, +C4<00000000000000000000000000000001>; -L_0x555555dc80f0 .functor BUFZ 8, L_0x555555dc8660, C4<00000000>, C4<00000000>, C4<00000000>; -L_0x555555dc8c40 .functor BUFZ 8, L_0x555555dc8890, C4<00000000>, C4<00000000>, C4<00000000>; -v0x555555db4d80_0 .net *"_ivl_0", 7 0, L_0x555555dc8660; 1 drivers -v0x555555db4e80_0 .net *"_ivl_11", 0 0, L_0x555555dc8960; 1 drivers -v0x555555db4f40_0 .net *"_ivl_12", 2 0, L_0x555555dc8ab0; 1 drivers -L_0x7eff80b5c3c0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; -v0x555555db5030_0 .net *"_ivl_15", 1 0, L_0x7eff80b5c3c0; 1 drivers -v0x555555db5110_0 .net *"_ivl_2", 2 0, L_0x555555dc8700; 1 drivers -L_0x7eff80b5c378 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; -v0x555555db5240_0 .net *"_ivl_5", 1 0, L_0x7eff80b5c378; 1 drivers -v0x555555db5320_0 .net *"_ivl_8", 7 0, L_0x555555dc8890; 1 drivers -v0x555555db5400_0 .var "empty", 0 0; -v0x555555db54c0 .array "fifo_reg", 0 1, 7 0; -v0x555555db5610_0 .var "full", 0 0; -o0x7eff80ba9008 .functor BUFZ 1, C4; HiZ drive -v0x555555db56d0_0 .net "i_clk", 0 0, o0x7eff80ba9008; 0 drivers -o0x7eff80ba9038 .functor BUFZ 1, C4; HiZ drive -v0x555555db5790_0 .net "i_rst_n", 0 0, o0x7eff80ba9038; 0 drivers -v0x555555db5850_0 .net "read_data", 7 0, L_0x555555dc80f0; 1 drivers -v0x555555db5930_0 .net "read_data_next", 7 0, L_0x555555dc8c40; 1 drivers -o0x7eff80ba90c8 .functor BUFZ 1, C4; HiZ drive -v0x555555db5a10_0 .net "read_fifo", 0 0, o0x7eff80ba90c8; 0 drivers -v0x555555db5ad0_0 .var "read_pointer", 0 0; -o0x7eff80ba9128 .functor BUFZ 8, C4; HiZ drive -v0x555555db5bb0_0 .net "write_data", 7 0, o0x7eff80ba9128; 0 drivers -o0x7eff80ba9158 .functor BUFZ 1, C4; HiZ drive -v0x555555db5c90_0 .net "write_fifo", 0 0, o0x7eff80ba9158; 0 drivers -v0x555555db5d50_0 .var "write_pointer", 0 0; -E_0x555555d8c690/0 .event negedge, v0x555555db5790_0; -E_0x555555d8c690/1 .event posedge, v0x555555db56d0_0; -E_0x555555d8c690 .event/or E_0x555555d8c690/0, E_0x555555d8c690/1; -L_0x555555dc8660 .array/port v0x555555db54c0, L_0x555555dc8700; -L_0x555555dc8700 .concat [ 1 2 0 0], v0x555555db5ad0_0, L_0x7eff80b5c378; -L_0x555555dc8890 .array/port v0x555555db54c0, L_0x555555dc8ab0; -L_0x555555dc8960 .reduce/nor v0x555555db5ad0_0; -L_0x555555dc8ab0 .concat [ 1 2 0 0], L_0x555555dc8960, L_0x7eff80b5c3c0; - .scope S_0x555555cfe490; -T_9 ; - %pushi/vec4 0, 0, 5; - %store/vec4 v0x555555daea70_0, 0, 5; - %pushi/vec4 70778885, 0, 28; - %store/vec4 v0x555555dae990_0, 0, 28; - %pushi/vec4 5, 0, 16; - %store/vec4 v0x555555dac970_0, 0, 16; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555daca50_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db11c0_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db0690_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db1ca0_0, 0, 1; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x555555db14c0_0, 0, 16; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db1f00_0, 0, 1; - %pushi/vec4 0, 0, 512; - %store/vec4 v0x555555db1760_0, 0, 512; - %pushi/vec4 0, 0, 64; - %store/vec4 v0x555555db1840_0, 0, 64; - %pushi/vec4 0, 0, 10; - %store/vec4 v0x555555db1680_0, 0, 10; - %pushi/vec4 0, 0, 3; - %store/vec4 v0x555555db15a0_0, 0, 3; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x555555db1d60_0, 0, 16; - %pushi/vec4 0, 0, 10; - %store/vec4 v0x555555db1ae0_0, 0, 10; - %pushi/vec4 0, 0, 3; - %store/vec4 v0x555555db1a00_0, 0, 3; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x555555db1bc0_0, 0, 16; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db2740_0, 0, 1; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x555555db1fc0_0, 0, 16; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db2a60_0, 0, 1; - %pushi/vec4 0, 0, 64; - %store/vec4 v0x555555db2580_0, 0, 64; - %pushi/vec4 0, 0, 512; - %store/vec4 v0x555555db2380_0, 0, 512; - %pushi/vec4 0, 0, 10; - %store/vec4 v0x555555db2180_0, 0, 10; - %pushi/vec4 0, 0, 3; - %store/vec4 v0x555555db20a0_0, 0, 3; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x555555db2800_0, 0, 16; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555dab6d0_0, 0, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db0450_0, 0, 1; - %pushi/vec4 0, 0, 40; - %store/vec4 v0x555555dad110_0, 0, 40; - %pushi/vec4 0, 0, 4; - %store/vec4 v0x555555dacd90_0, 0, 4; - %pushi/vec4 0, 0, 6; - %store/vec4 v0x555555dace70_0, 0, 6; - %pushi/vec4 0, 0, 6; - %store/vec4 v0x555555dad030_0, 0, 6; - %pushi/vec4 0, 0, 6; - %store/vec4 v0x555555dad1f0_0, 0, 6; - %pushi/vec4 0, 0, 6; - %store/vec4 v0x555555dad2d0_0, 0, 6; - %pushi/vec4 0, 0, 6; - %store/vec4 v0x555555dacbd0_0, 0, 6; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555dacf50_0, 0, 1; - %pushi/vec4 0, 0, 4; - %store/vec4 v0x555555dac390_0, 0, 4; - %pushi/vec4 0, 0, 5; - %store/vec4 v0x555555dac890_0, 0, 5; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555dae8d0_0, 0, 1; - %pushi/vec4 0, 0, 3; - %store/vec4 v0x555555daecd0_0, 0, 3; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x555555daccb0_0, 0, 16; - %pushi/vec4 0, 0, 4; - %store/vec4 v0x555555daada0_0, 0, 4; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db4000_0, 0, 1; - %pushi/vec4 0, 0, 16; - %store/vec4 v0x555555db3b20_0, 0, 16; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db40c0_0, 0, 1; - %pushi/vec4 0, 0, 10; - %store/vec4 v0x555555db3c00_0, 0, 10; - %pushi/vec4 0, 0, 512; - %store/vec4 v0x555555db3ce0_0, 0, 512; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db3f40_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db3e80_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db3dc0_0, 0, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db0810_0, 0, 1; - %pushi/vec4 0, 0, 512; - %store/vec4 v0x555555db10e0_0, 0, 512; - %pushi/vec4 0, 0, 128; - %store/vec4 v0x555555db4740_0, 0, 128; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db3800_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db38c0_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db3980_0, 0, 1; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555db2e60_0, 0, 32; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555db2f40_0, 0, 32; - %pushi/vec4 0, 0, 4; - %store/vec4 v0x555555db3720_0, 0, 4; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db29a0_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db28e0_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db1e40_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db1920_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db2660_0, 0, 1; - %end; - .thread T_9; - .scope S_0x555555cfe490; -T_10 ; - %pushi/vec4 0, 0, 8; - %store/vec4 v0x555555daee90_0, 0, 8; - %end; - .thread T_10; - .scope S_0x555555cfe490; -T_11 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_11.0 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_11.1, 5; - %pushi/vec4 0, 0, 1; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4 v0x555555dab330_0, 4, 1; - %pushi/vec4 0, 0, 1; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4 v0x555555dab250_0, 4, 1; - %pushi/vec4 0, 0, 16; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dab040, 4, 0; - %pushi/vec4 0, 0, 16; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555daae80, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_11.0; -T_11.1 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_11.2 ; - %load/vec4 v0x555555dae670_0; - %pad/u 36; - %cmpi/u 2, 0, 36; - %jmp/0xz T_11.3, 5; - %pushi/vec4 0, 0, 512; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555db2260, 4, 0; - %pushi/vec4 0, 0, 64; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555db2460, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_11.2; -T_11.3 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_11.4 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_11.5, 5; - %pushi/vec4 0, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dabd60, 4, 0; - %pushi/vec4 0, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555daba90, 4, 0; - %pushi/vec4 0, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dac680, 4, 0; - %pushi/vec4 0, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dac180, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_11.4; -T_11.5 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_11.6 ; - %load/vec4 v0x555555dae670_0; - %pad/s 36; - %cmpi/s 6, 0, 36; - %jmp/0xz T_11.7, 5; - %pushi/vec4 0, 0, 17; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555db1340, 4, 0; - %pushi/vec4 0, 0, 17; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555db1280, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_11.6; -T_11.7 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_11.8 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 4, 0, 32; - %jmp/0xz T_11.9, 5; - %pushi/vec4 67108863, 0, 26; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dab790, 4, 0; - %pushi/vec4 67108863, 0, 26; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dab4d0, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_11.8; -T_11.9 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_11.10 ; - %load/vec4 v0x555555dae670_0; - %cmpi/u 8, 0, 32; - %jmp/0xz T_11.11, 5; - %pushi/vec4 0, 0, 5; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555db0510, 4, 0; - %pushi/vec4 8, 0, 5; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555db05d0, 4, 0; - %pushi/vec4 0, 0, 5; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dae410, 4, 0; - %pushi/vec4 8, 0, 5; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dae5b0, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_11.10; -T_11.11 ; - %end; - .thread T_11; - .scope S_0x555555cfe490; -T_12 ; - %wait E_0x555555cb9a50; - %load/vec4 v0x555555dad990_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_12.0, 8; - %pushi/vec4 0, 0, 5; - %assign/vec4 v0x555555daea70_0, 0; - %pushi/vec4 70778885, 0, 28; - %assign/vec4 v0x555555dae990_0, 0; - %pushi/vec4 5, 0, 16; - %assign/vec4 v0x555555dac970_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555daca50_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db11c0_0, 0; - %jmp T_12.1; -T_12.0 ; - %load/vec4 v0x555555daca50_0; - %flag_set/vec4 8; - %jmp/0xz T_12.2, 8; - %load/vec4 v0x555555dae990_0; - %parti/s 16, 0, 2; - %assign/vec4 v0x555555dac970_0, 0; - %jmp T_12.3; -T_12.2 ; - %load/vec4 v0x555555dae990_0; - %parti/s 1, 26, 6; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_12.6, 9; - %load/vec4 v0x555555db0690_0; - %nor/r; - %and; -T_12.6; - %flag_set/vec4 8; - %jmp/0xz T_12.4, 8; - %load/vec4 v0x555555dac970_0; - %subi 1, 0, 16; - %assign/vec4 v0x555555dac970_0, 0; -T_12.4 ; -T_12.3 ; - %load/vec4 v0x555555dac970_0; - %pad/u 32; - %cmpi/e 1, 0, 32; - %jmp/1 T_12.9, 4; - %flag_mov 8, 4; - %load/vec4 v0x555555dae990_0; - %parti/s 1, 26, 6; - %nor/r; - %flag_set/vec4 9; - %flag_or 9, 8; - %flag_mov 4, 9; -T_12.9; - %jmp/0xz T_12.7, 4; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555daca50_0, 0; - %load/vec4 v0x555555daea70_0; - %store/vec4 v0x555555da8f40_0, 0, 5; - %callf/vec4 TD_ddr3_controller.read_rom_instruction, S_0x555555da8db0; - %assign/vec4 v0x555555dae990_0, 0; - %load/vec4 v0x555555daea70_0; - %cmpi/e 22, 0, 5; - %flag_mov 8, 4; - %jmp/0 T_12.10, 8; - %pushi/vec4 19, 0, 5; - %jmp/1 T_12.11, 8; -T_12.10 ; End of true expr. - %load/vec4 v0x555555daea70_0; - %addi 1, 0, 5; - %jmp/0 T_12.11, 8; - ; End of false expr. - %blend; -T_12.11; - %assign/vec4 v0x555555daea70_0, 0; - %jmp T_12.8; -T_12.7 ; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555daca50_0, 0; -T_12.8 ; - %load/vec4 v0x555555dae990_0; - %parti/s 1, 27, 6; - %flag_set/vec4 8; - %jmp/0 T_12.12, 8; - %pushi/vec4 1, 0, 1; - %jmp/1 T_12.13, 8; -T_12.12 ; End of true expr. - %load/vec4 v0x555555db11c0_0; - %jmp/0 T_12.13, 8; - ; End of false expr. - %blend; -T_12.13; - %assign/vec4 v0x555555db11c0_0, 0; -T_12.1 ; - %jmp T_12; - .thread T_12; - .scope S_0x555555cfe490; -T_13 ; - %wait E_0x555555cb9a50; - %load/vec4 v0x555555dad990_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_13.0, 8; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db02d0_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db0450_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db1ca0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db1f00_0, 0; - %pushi/vec4 0, 0, 10; - %assign/vec4 v0x555555db1680_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555db15a0_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x555555db1d60_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555db1a00_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x555555db1bc0_0, 0; - %pushi/vec4 0, 0, 10; - %assign/vec4 v0x555555db1ae0_0, 0; - %pushi/vec4 0, 0, 512; - %assign/vec4 v0x555555db1760_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db2740_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db2a60_0, 0; - %pushi/vec4 0, 0, 10; - %assign/vec4 v0x555555db2180_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555db20a0_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x555555db2800_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dab6d0_0, 0; - %pushi/vec4 0, 0, 512; - %assign/vec4 v0x555555db2380_0, 0; - %pushi/vec4 0, 0, 64; - %assign/vec4 v0x555555db2580_0, 0; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.2 ; - %load/vec4 v0x555555dae670_0; - %cmpi/u 8, 0, 32; - %jmp/0xz T_13.3, 5; - %pushi/vec4 0, 0, 64; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db2ce0, 0, 4; - %pushi/vec4 0, 0, 8; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db2da0, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.2; -T_13.3 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.4 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_13.5, 5; - %pushi/vec4 0, 0, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dabd60, 0, 4; - %pushi/vec4 0, 0, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555daba90, 0, 4; - %pushi/vec4 0, 0, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dac680, 0, 4; - %pushi/vec4 0, 0, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dac180, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.4; -T_13.5 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.6 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_13.7, 5; - %pushi/vec4 0, 0, 1; - %ix/load 5, 0, 0; - %ix/getv/s 4, v0x555555dae670_0; - %assign/vec4/off/d v0x555555dab330_0, 4, 5; - %pushi/vec4 0, 0, 16; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dab040, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.6; -T_13.7 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.8 ; - %load/vec4 v0x555555dae670_0; - %pad/u 36; - %cmpi/u 2, 0, 36; - %jmp/0xz T_13.9, 5; - %pushi/vec4 0, 0, 512; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db2260, 0, 4; - %pushi/vec4 0, 0, 64; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db2460, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.8; -T_13.9 ; - %jmp T_13.1; -T_13.0 ; - %load/vec4 v0x555555db11c0_0; - %flag_set/vec4 8; - %jmp/0xz T_13.10, 8; - %load/vec4 v0x555555db0390_0; - %flag_set/vec4 8; - %flag_get/vec4 8; - %jmp/1 T_13.12, 8; - %load/vec4 v0x555555db2b20_0; - %pad/u 32; - %pushi/vec4 14, 0, 32; - %cmp/ne; - %flag_get/vec4 4; - %or; -T_13.12; - %assign/vec4 v0x555555db02d0_0, 0; - %load/vec4 v0x555555db0390_0; - %assign/vec4 v0x555555db0450_0, 0; - %load/vec4 v0x555555dab610_0; - %assign/vec4 v0x555555dab6d0_0, 0; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.13 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_13.14, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dabca0, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dabd60, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dab9d0, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555daba90, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dac470, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dac680, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dabf70, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dac180, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.13; -T_13.14 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.15 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 4, 0, 32; - %jmp/0xz T_13.16, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dab4d0, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dab790, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.15; -T_13.16 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.17 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_13.18, 5; - %load/vec4 v0x555555dab250_0; - %load/vec4 v0x555555dae670_0; - %part/s 1; - %ix/load 5, 0, 0; - %ix/getv/s 4, v0x555555dae670_0; - %assign/vec4/off/d v0x555555dab330_0, 4, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555daae80, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dab040, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.17; -T_13.18 ; - %load/vec4 v0x555555daea70_0; - %pad/u 32; - %cmpi/e 20, 0, 32; - %jmp/0xz T_13.19, 4; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dab6d0_0, 0; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.21 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_13.22, 5; - %pushi/vec4 0, 0, 1; - %ix/load 5, 0, 0; - %ix/getv/s 4, v0x555555dae670_0; - %assign/vec4/off/d v0x555555dab330_0, 4, 5; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.21; -T_13.22 ; -T_13.19 ; - %load/vec4 v0x555555dae990_0; - %parti/s 1, 27, 6; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_13.23, 8; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db02d0_0, 0; -T_13.23 ; - %load/vec4 v0x555555db0450_0; - %nor/r; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_13.27, 9; - %load/vec4 v0x555555db29a0_0; - %and; -T_13.27; - %flag_set/vec4 8; - %jmp/0xz T_13.25, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db1ca0_0, 0; - %load/vec4 v0x555555db1ca0_0; - %assign/vec4 v0x555555db2740_0, 0; - %load/vec4 v0x555555db14c0_0; - %assign/vec4 v0x555555db1fc0_0, 0; - %load/vec4 v0x555555db1f00_0; - %assign/vec4 v0x555555db2a60_0, 0; - %load/vec4 v0x555555db1840_0; - %inv; - %assign/vec4 v0x555555db2580_0, 0; - %load/vec4 v0x555555db1680_0; - %assign/vec4 v0x555555db2180_0, 0; - %load/vec4 v0x555555db15a0_0; - %assign/vec4 v0x555555db20a0_0, 0; - %load/vec4 v0x555555db1d60_0; - %assign/vec4 v0x555555db2800_0, 0; - %load/vec4 v0x555555db1760_0; - %assign/vec4 v0x555555db2380_0, 0; -T_13.25 ; - %load/vec4 v0x555555dae010_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_13.30, 9; - %load/vec4 v0x555555db02d0_0; - %nor/r; - %and; -T_13.30; - %flag_set/vec4 8; - %jmp/0xz T_13.28, 8; - %load/vec4 v0x555555dae290_0; - %assign/vec4 v0x555555db1ca0_0, 0; - %load/vec4 v0x555555dad490_0; - %assign/vec4 v0x555555db14c0_0, 0; - %load/vec4 v0x555555dae350_0; - %assign/vec4 v0x555555db1f00_0, 0; - %load/vec4 v0x555555dae1b0_0; - %assign/vec4 v0x555555db1840_0, 0; - %load/vec4 v0x555555dadf30_0; - %parti/s 7, 0, 2; - %concati/vec4 0, 0, 3; - %assign/vec4 v0x555555db1680_0, 0; - %load/vec4 v0x555555dadf30_0; - %parti/s 3, 7, 4; - %assign/vec4 v0x555555db15a0_0, 0; - %load/vec4 v0x555555dadf30_0; - %parti/s 16, 10, 5; - %assign/vec4 v0x555555db1d60_0, 0; - %load/vec4 v0x555555dadf30_0; - %addi 5, 0, 26; - %split/vec4 7; - %ix/load 4, 3, 0; - %ix/load 5, 0, 0; - %flag_set/imm 4, 0; - %assign/vec4/off/d v0x555555db1ae0_0, 4, 5; - %split/vec4 3; - %assign/vec4 v0x555555db1a00_0, 0; - %assign/vec4 v0x555555db1bc0_0, 0; - %load/vec4 v0x555555dae0d0_0; - %assign/vec4 v0x555555db1760_0, 0; - %jmp T_13.29; -T_13.28 ; - %load/vec4 v0x555555db2b20_0; - %pad/u 32; - %cmpi/ne 14, 0, 32; - %jmp/0xz T_13.31, 4; - %load/vec4 v0x555555db4000_0; - %assign/vec4 v0x555555db1ca0_0, 0; - %load/vec4 v0x555555db40c0_0; - %assign/vec4 v0x555555db1f00_0, 0; - %pushi/vec4 0, 0, 64; - %assign/vec4 v0x555555db1840_0, 0; - %load/vec4 v0x555555db3b20_0; - %assign/vec4 v0x555555db14c0_0, 0; - %load/vec4 v0x555555db3c00_0; - %assign/vec4 v0x555555db1680_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555db15a0_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x555555db1d60_0, 0; - %pushi/vec4 0, 0, 26; - %split/vec4 7; - %ix/load 4, 3, 0; - %ix/load 5, 0, 0; - %flag_set/imm 4, 0; - %assign/vec4/off/d v0x555555db1ae0_0, 4, 5; - %split/vec4 3; - %assign/vec4 v0x555555db1a00_0, 0; - %assign/vec4 v0x555555db1bc0_0, 0; - %load/vec4 v0x555555db3ce0_0; - %assign/vec4 v0x555555db1760_0, 0; -T_13.31 ; -T_13.29 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.33 ; - %load/vec4 v0x555555dae670_0; - %cmpi/u 8, 0, 32; - %jmp/0xz T_13.34, 5; - %load/vec4 v0x555555db2380_0; - %pushi/vec4 448, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %load/vec4 v0x555555db2380_0; - %pushi/vec4 384, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2380_0; - %pushi/vec4 320, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2380_0; - %pushi/vec4 256, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2380_0; - %pushi/vec4 192, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2380_0; - %pushi/vec4 128, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2380_0; - %pushi/vec4 64, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2380_0; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %pad/u 128; - %ix/getv/s 5, v0x555555dae670_0; - %load/vec4a v0x555555dab910, 5; - %ix/vec4 4; - %shiftl 4; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555db2ce0, 4; - %pad/u 128; - %or; - %split/vec4 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2260, 5, 6; - %split/vec4 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 64, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2260, 5, 6; - %split/vec4 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 128, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2260, 5, 6; - %split/vec4 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 192, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2260, 5, 6; - %split/vec4 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 256, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2260, 5, 6; - %split/vec4 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 320, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2260, 5, 6; - %split/vec4 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 384, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2260, 5, 6; - %split/vec4 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 448, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2260, 5, 6; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db2ce0, 0, 4; - %load/vec4 v0x555555db2580_0; - %pushi/vec4 56, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %part/u 1; - %load/vec4 v0x555555db2580_0; - %pushi/vec4 48, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %part/u 1; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2580_0; - %pushi/vec4 40, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %part/u 1; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2580_0; - %pushi/vec4 32, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %part/u 1; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2580_0; - %pushi/vec4 24, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %part/u 1; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2580_0; - %pushi/vec4 16, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %part/u 1; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2580_0; - %pushi/vec4 8, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %part/u 1; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2580_0; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %part/u 1; - %concat/vec4; draw_concat_vec4 - %pad/u 16; - %ix/getv/s 5, v0x555555dae670_0; - %load/vec4a v0x555555dab910, 5; - %ix/load 5, 3, 0; - %flag_set/imm 4, 0; - %shiftr 5; - %ix/vec4 4; - %shiftl 4; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555db2da0, 4; - %pad/u 16; - %or; - %split/vec4 1; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2460, 5, 6; - %split/vec4 1; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 8, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2460, 5, 6; - %split/vec4 1; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 16, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2460, 5, 6; - %split/vec4 1; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 24, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2460, 5, 6; - %split/vec4 1; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 32, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2460, 5, 6; - %split/vec4 1; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 40, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2460, 5, 6; - %split/vec4 1; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 48, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2460, 5, 6; - %split/vec4 1; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 56, 0, 32; - %load/vec4 v0x555555dae670_0; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db2460, 5, 6; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db2da0, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.33; -T_13.34 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_13.35 ; - %load/vec4 v0x555555dae670_0; - %pad/u 36; - %cmpi/u 1, 0, 36; - %jmp/0xz T_13.36, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555db2260, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %ix/vec4/s 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db2260, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555db2460, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %ix/vec4/s 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db2460, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_13.35; -T_13.36 ; - %load/vec4 v0x555555dae010_0; - %nor/r; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_13.39, 9; - %load/vec4 v0x555555db2b20_0; - %pad/u 32; - %pushi/vec4 14, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_13.39; - %flag_set/vec4 8; - %jmp/0xz T_13.37, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db2740_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db1ca0_0, 0; -T_13.37 ; -T_13.10 ; -T_13.1 ; - %jmp T_13; - .thread T_13; - .scope S_0x555555cfe490; -T_14 ; - %wait E_0x555555ba4230; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db1920_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db2660_0, 0, 1; - %load/vec4 v0x555555dab6d0_0; - %flag_set/vec4 8; - %flag_get/vec4 8; - %jmp/1 T_14.0, 8; - %load/vec4 v0x555555db3f40_0; - %or; -T_14.0; - %store/vec4 v0x555555dab610_0, 0, 1; - %load/vec4 v0x555555dae990_0; - %parti/s 1, 24, 6; - %store/vec4 v0x555555dab410_0, 0, 1; - %load/vec4 v0x555555dae990_0; - %parti/s 1, 23, 6; - %store/vec4 v0x555555dab850_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db1e40_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db28e0_0, 0, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db29a0_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db0390_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db0750_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555daac20_0, 0, 1; - %load/vec4 v0x555555db3e80_0; - %store/vec4 v0x555555db44c0_0, 0, 1; - %load/vec4 v0x555555db3dc0_0; - %store/vec4 v0x555555db4260_0, 0, 1; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_14.1 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_14.2, 5; - %load/vec4 v0x555555dab330_0; - %load/vec4 v0x555555dae670_0; - %part/s 1; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4 v0x555555dab250_0, 4, 1; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dab040, 4; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555daae80, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_14.1; -T_14.2 ; - %load/vec4 v0x555555daca50_0; - %nor/r; - %load/vec4 v0x555555dae990_0; - %parti/s 3, 19, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dae990_0; - %parti/s 1, 24, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dae990_0; - %parti/s 1, 23, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dae990_0; - %parti/s 3, 16, 6; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dae990_0; - %parti/s 16, 0, 2; - %concat/vec4; draw_concat_vec4 - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %load/vec4 v0x555555dae990_0; - %parti/s 1, 25, 6; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 10, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %load/vec4 v0x555555daeb50_0; - %nor/r; - %concati/vec4 5, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 19; - %ix/load 4, 2, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %load/vec4 v0x555555daec10_0; - %nor/r; - %concati/vec4 4, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 19; - %ix/load 4, 3, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %pushi/vec4 1, 0, 1; - %concati/vec4 3, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 19; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_14.3 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_14.4, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dabd60, 4; - %pad/u 32; - %cmpi/e 0, 0, 32; - %flag_mov 8, 4; - %jmp/0 T_14.5, 8; - %pushi/vec4 0, 0, 4; - %jmp/1 T_14.6, 8; -T_14.5 ; End of true expr. - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dabd60, 4; - %subi 1, 0, 4; - %jmp/0 T_14.6, 8; - ; End of false expr. - %blend; -T_14.6; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dabca0, 4, 0; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555daba90, 4; - %pad/u 32; - %cmpi/e 0, 0, 32; - %flag_mov 8, 4; - %jmp/0 T_14.7, 8; - %pushi/vec4 0, 0, 4; - %jmp/1 T_14.8, 8; -T_14.7 ; End of true expr. - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555daba90, 4; - %subi 1, 0, 4; - %jmp/0 T_14.8, 8; - ; End of false expr. - %blend; -T_14.8; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dab9d0, 4, 0; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dac680, 4; - %pad/u 32; - %cmpi/e 0, 0, 32; - %flag_mov 8, 4; - %jmp/0 T_14.9, 8; - %pushi/vec4 0, 0, 4; - %jmp/1 T_14.10, 8; -T_14.9 ; End of true expr. - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dac680, 4; - %subi 1, 0, 4; - %jmp/0 T_14.10, 8; - ; End of false expr. - %blend; -T_14.10; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dac470, 4, 0; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dac180, 4; - %pad/u 32; - %cmpi/e 0, 0, 32; - %flag_mov 8, 4; - %jmp/0 T_14.11, 8; - %pushi/vec4 0, 0, 4; - %jmp/1 T_14.12, 8; -T_14.11 ; End of true expr. - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dac180, 4; - %subi 1, 0, 4; - %jmp/0 T_14.12, 8; - ; End of false expr. - %blend; -T_14.12; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dabf70, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_14.3; -T_14.4 ; - %pushi/vec4 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_14.13 ; - %load/vec4 v0x555555dae670_0; - %pad/s 36; - %cmpi/s 6, 0, 36; - %jmp/0xz T_14.14, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555db1340, 4; - %load/vec4 v0x555555dae670_0; - %subi 1, 0, 32; - %ix/vec4/s 4; - %store/vec4a v0x555555db1280, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_14.13; -T_14.14 ; - %pushi/vec4 0, 0, 17; - %ix/load 4, 5, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555db1280, 4, 0; - %load/vec4 v0x555555db2740_0; - %flag_set/vec4 8; - %jmp/0xz T_14.15, 8; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db28e0_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db29a0_0, 0, 1; - %load/vec4 v0x555555dab330_0; - %load/vec4 v0x555555db20a0_0; - %part/u 1; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.19, 9; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dab040, 4; - %load/vec4 v0x555555db2800_0; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.19; - %flag_set/vec4 8; - %jmp/0xz T_14.17, 8; - %load/vec4 v0x555555db2a60_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.22, 9; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dac680, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.22; - %flag_set/vec4 8; - %jmp/0xz T_14.20, 8; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db28e0_0, 0, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db29a0_0, 0, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555dab610_0, 0, 1; - %load/vec4 v0x555555db1fc0_0; - %concati/vec4 1, 0, 1; - %ix/load 4, 5, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555db1280, 4, 0; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dabd60, 4; - %cmpi/u 4, 0, 4; - %flag_or 5, 4; - %jmp/0xz T_14.23, 5; - %pushi/vec4 4, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dabca0, 4, 0; -T_14.23 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_14.25 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 8, 0, 32; - %jmp/0xz T_14.26, 5; - %pushi/vec4 3, 0, 4; - %ix/getv/s 4, v0x555555dae670_0; - %store/vec4a v0x555555dabf70, 4, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_14.25; -T_14.26 ; - %pushi/vec4 3, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dabf70, 4, 0; - %pushi/vec4 0, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dac470, 4, 0; - %pushi/vec4 0, 0, 1; - %concati/vec4 4, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db20a0_0; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 5; - %concati/vec4 0, 0, 1; - %load/vec4 v0x555555db2180_0; - %concat/vec4; draw_concat_vec4 - %ix/load 4, 3, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %load/vec4 v0x555555dab610_0; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 21, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %load/vec4 v0x555555dab610_0; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 21, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %load/vec4 v0x555555dab610_0; - %ix/load 4, 2, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 21, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %load/vec4 v0x555555dab610_0; - %ix/load 4, 3, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 21, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db44c0_0, 0, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db4260_0, 0, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db2660_0, 0, 1; - %jmp T_14.21; -T_14.20 ; - %load/vec4 v0x555555db2a60_0; - %nor/r; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.29, 9; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dac180, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.29; - %flag_set/vec4 8; - %jmp/0xz T_14.27, 8; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db28e0_0, 0, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db29a0_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555dab610_0, 0, 1; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dabd60, 4; - %cmpi/u 1, 0, 4; - %flag_or 5, 4; - %jmp/0xz T_14.30, 5; - %pushi/vec4 1, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dabca0, 4, 0; -T_14.30 ; - %pushi/vec4 0, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dabf70, 4, 0; - %pushi/vec4 1, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dac470, 4, 0; - %load/vec4 v0x555555db1fc0_0; - %concati/vec4 1, 0, 1; - %ix/load 4, 5, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555db1280, 4, 0; - %pushi/vec4 0, 0, 1; - %concati/vec4 5, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db20a0_0; - %concat/vec4; draw_concat_vec4 - %concati/vec4 0, 0, 5; - %concati/vec4 0, 0, 1; - %load/vec4 v0x555555db2180_0; - %concat/vec4; draw_concat_vec4 - %ix/load 4, 2, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %load/vec4 v0x555555dab610_0; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 21, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %load/vec4 v0x555555dab610_0; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 21, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %load/vec4 v0x555555dab610_0; - %ix/load 4, 2, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 21, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %load/vec4 v0x555555dab610_0; - %ix/load 4, 3, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %ix/load 5, 21, 0; - %flag_set/imm 4, 0; - %flag_or 4, 8; - %store/vec4a v0x555555dab4d0, 4, 5; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db2660_0, 0, 1; -T_14.27 ; -T_14.21 ; - %jmp T_14.18; -T_14.17 ; - %load/vec4 v0x555555dab330_0; - %load/vec4 v0x555555db20a0_0; - %part/u 1; - %nor/r; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.34, 9; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555daba90, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.34; - %flag_set/vec4 8; - %jmp/0xz T_14.32, 8; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555daac20_0, 0, 1; - %pushi/vec4 3, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dabca0, 4, 0; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dac180, 4; - %cmpi/u 0, 0, 4; - %flag_or 5, 4; - %jmp/0xz T_14.35, 5; - %pushi/vec4 0, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dabf70, 4, 0; -T_14.35 ; - %pushi/vec4 0, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dac470, 4, 0; - %pushi/vec4 0, 0, 1; - %concati/vec4 3, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db20a0_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db2800_0; - %concat/vec4; draw_concat_vec4 - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %pushi/vec4 1, 0, 1; - %ix/getv 4, v0x555555db20a0_0; - %store/vec4 v0x555555dab250_0, 4, 1; - %load/vec4 v0x555555db2800_0; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555daae80, 4, 0; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db2660_0, 0, 1; - %jmp T_14.33; -T_14.32 ; - %load/vec4 v0x555555dab330_0; - %load/vec4 v0x555555db20a0_0; - %part/u 1; - %flag_set/vec4 10; - %flag_get/vec4 10; - %jmp/0 T_14.40, 10; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dab040, 4; - %load/vec4 v0x555555db2800_0; - %cmp/ne; - %flag_get/vec4 4; - %and; -T_14.40; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.39, 9; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dabd60, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.39; - %flag_set/vec4 8; - %jmp/0xz T_14.37, 8; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db0750_0, 0, 1; - %pushi/vec4 1, 0, 4; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dab9d0, 4, 0; - %pushi/vec4 0, 0, 1; - %concati/vec4 2, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db20a0_0; - %concat/vec4; draw_concat_vec4 - %pushi/vec4 0, 0, 5; - %concati/vec4 0, 0, 1; - %load/vec4 v0x555555db2800_0; - %parti/s 10, 0, 2; - %concat/vec4; draw_concat_vec4 - %concat/vec4; draw_concat_vec4 - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %pushi/vec4 0, 0, 1; - %ix/getv 4, v0x555555db20a0_0; - %store/vec4 v0x555555dab250_0, 4, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db2660_0, 0, 1; -T_14.37 ; -T_14.33 ; -T_14.18 ; -T_14.15 ; - %load/vec4 v0x555555db1ca0_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.43, 9; - %load/vec4 v0x555555db1a00_0; - %load/vec4 v0x555555db20a0_0; - %cmp/e; - %flag_get/vec4 4; - %jmp/0 T_14.44, 4; - %load/vec4 v0x555555db2740_0; - %and; -T_14.44; - %nor/r; - %and; -T_14.43; - %flag_set/vec4 8; - %jmp/0xz T_14.41, 8; - %load/vec4 v0x555555dab330_0; - %load/vec4 v0x555555db1a00_0; - %part/u 1; - %flag_set/vec4 11; - %flag_get/vec4 11; - %jmp/0 T_14.49, 11; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dab040, 4; - %load/vec4 v0x555555db1bc0_0; - %cmp/ne; - %flag_get/vec4 4; - %and; -T_14.49; - %flag_set/vec4 10; - %flag_get/vec4 10; - %jmp/0 T_14.48, 10; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dabd60, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.48; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.47, 9; - %load/vec4 v0x555555db0750_0; - %nor/r; - %and; -T_14.47; - %flag_set/vec4 8; - %jmp/0xz T_14.45, 8; - %pushi/vec4 1, 0, 4; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dab9d0, 4, 0; - %pushi/vec4 0, 0, 1; - %concati/vec4 2, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db1a00_0; - %concat/vec4; draw_concat_vec4 - %pushi/vec4 0, 0, 5; - %concati/vec4 0, 0, 1; - %load/vec4 v0x555555db1bc0_0; - %parti/s 10, 0, 2; - %concat/vec4; draw_concat_vec4 - %concat/vec4; draw_concat_vec4 - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %pushi/vec4 0, 0, 1; - %ix/getv 4, v0x555555db1a00_0; - %store/vec4 v0x555555dab250_0, 4, 1; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db1920_0, 0, 1; - %jmp T_14.46; -T_14.45 ; - %load/vec4 v0x555555dab330_0; - %load/vec4 v0x555555db1a00_0; - %part/u 1; - %nor/r; - %flag_set/vec4 10; - %flag_get/vec4 10; - %jmp/0 T_14.53, 10; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555daba90, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.53; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.52, 9; - %load/vec4 v0x555555daac20_0; - %nor/r; - %and; -T_14.52; - %flag_set/vec4 8; - %jmp/0xz T_14.50, 8; - %pushi/vec4 3, 0, 4; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dabca0, 4, 0; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dabf70, 4; - %cmpi/u 0, 0, 4; - %flag_or 5, 4; - %jmp/0xz T_14.54, 5; - %pushi/vec4 0, 0, 4; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dabf70, 4, 0; -T_14.54 ; - %pushi/vec4 0, 0, 4; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555dac470, 4, 0; - %pushi/vec4 0, 0, 1; - %concati/vec4 3, 0, 3; - %load/vec4 v0x555555dab610_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab410_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555dab850_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db1a00_0; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db1bc0_0; - %concat/vec4; draw_concat_vec4 - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %store/vec4a v0x555555dab4d0, 4, 0; - %pushi/vec4 1, 0, 1; - %ix/getv 4, v0x555555db1a00_0; - %store/vec4 v0x555555dab250_0, 4, 1; - %load/vec4 v0x555555db1bc0_0; - %load/vec4 v0x555555db1a00_0; - %pad/u 5; - %ix/vec4 4; - %store/vec4a v0x555555daae80, 4, 0; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db1920_0, 0, 1; -T_14.50 ; -T_14.46 ; -T_14.41 ; - %load/vec4 v0x555555db1ca0_0; - %flag_set/vec4 8; - %jmp/0xz T_14.56, 8; - %load/vec4 v0x555555dab250_0; - %load/vec4 v0x555555db15a0_0; - %part/u 1; - %nor/r; - %flag_set/vec4 8; - %jmp/1 T_14.60, 8; - %load/vec4 v0x555555dab250_0; - %load/vec4 v0x555555db15a0_0; - %part/u 1; - %flag_set/vec4 10; - %flag_get/vec4 10; - %jmp/0 T_14.61, 10; - %load/vec4 v0x555555db15a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555daae80, 4; - %load/vec4 v0x555555db1d60_0; - %cmp/ne; - %flag_get/vec4 4; - %and; -T_14.61; - %flag_set/vec4 9; - %flag_or 8, 9; -T_14.60; - %jmp/0xz T_14.58, 8; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db1e40_0, 0, 1; - %jmp T_14.59; -T_14.58 ; - %load/vec4 v0x555555db1f00_0; - %nor/r; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.64, 9; - %load/vec4 v0x555555db15a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dabf70, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/ne; - %flag_get/vec4 4; - %and; -T_14.64; - %flag_set/vec4 8; - %jmp/0xz T_14.62, 8; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db1e40_0, 0, 1; - %jmp T_14.63; -T_14.62 ; - %load/vec4 v0x555555db1f00_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.67, 9; - %load/vec4 v0x555555db15a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dac470, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/ne; - %flag_get/vec4 4; - %and; -T_14.67; - %flag_set/vec4 8; - %jmp/0xz T_14.65, 8; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db1e40_0, 0, 1; -T_14.65 ; -T_14.63 ; -T_14.59 ; -T_14.56 ; - %load/vec4 v0x555555db2740_0; - %flag_set/vec4 8; - %jmp/0xz T_14.68, 8; - %load/vec4 v0x555555dab250_0; - %load/vec4 v0x555555db20a0_0; - %part/u 1; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.72, 9; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555daae80, 4; - %load/vec4 v0x555555db2800_0; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.72; - %flag_set/vec4 8; - %jmp/0xz T_14.70, 8; - %load/vec4 v0x555555db2a60_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.75, 9; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dac470, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.75; - %flag_set/vec4 8; - %jmp/0xz T_14.73, 8; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db28e0_0, 0, 1; - %jmp T_14.74; -T_14.73 ; - %load/vec4 v0x555555db2a60_0; - %nor/r; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_14.78, 9; - %load/vec4 v0x555555db20a0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dabf70, 4; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_14.78; - %flag_set/vec4 8; - %jmp/0xz T_14.76, 8; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db28e0_0, 0, 1; -T_14.76 ; -T_14.74 ; -T_14.70 ; -T_14.68 ; - %load/vec4 v0x555555db0450_0; - %flag_set/vec4 8; - %jmp/0xz T_14.79, 8; - %load/vec4 v0x555555db28e0_0; - %store/vec4 v0x555555db0390_0, 0, 1; - %jmp T_14.80; -T_14.79 ; - %load/vec4 v0x555555dae290_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_14.81, 8; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db0390_0, 0, 1; - %jmp T_14.82; -T_14.81 ; - %load/vec4 v0x555555db1ca0_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_14.83, 8; - %load/vec4 v0x555555db28e0_0; - %store/vec4 v0x555555db0390_0, 0, 1; - %jmp T_14.84; -T_14.83 ; - %load/vec4 v0x555555db1e40_0; - %store/vec4 v0x555555db0390_0, 0, 1; -T_14.84 ; -T_14.82 ; -T_14.80 ; - %load/vec4 v0x555555dae010_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_14.85, 8; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db0390_0, 0, 1; -T_14.85 ; - %jmp T_14; - .thread T_14, $push; - .scope S_0x555555cfe490; -T_15 ; - %wait E_0x555555cb9a50; - %load/vec4 v0x555555dad990_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_15.0, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dae750_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dae810_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555db4660_0, 0; - %pushi/vec4 0, 0, 2; - %assign/vec4 v0x555555db4580_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555db43e0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db4320_0, 0; - %pushi/vec4 0, 0, 4; - %assign/vec4 v0x555555db4180_0, 0; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.2 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 2, 0, 32; - %jmp/0xz T_15.3, 5; - %pushi/vec4 0, 0, 16; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dacb10, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.2; -T_15.3 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.4 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 2, 0, 32; - %jmp/0xz T_15.5, 5; - %pushi/vec4 0, 0, 512; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db0210, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.4; -T_15.5 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.6 ; - %load/vec4 v0x555555dae670_0; - %pad/s 36; - %cmpi/s 6, 0, 36; - %jmp/0xz T_15.7, 5; - %pushi/vec4 0, 0, 17; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db1340, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.6; -T_15.7 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.8 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 16, 0, 32; - %jmp/0xz T_15.9, 5; - %pushi/vec4 0, 0, 17; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dafe70, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.8; -T_15.9 ; - %jmp T_15.1; -T_15.0 ; - %load/vec4 v0x555555db44c0_0; - %flag_set/vec4 8; - %flag_get/vec4 8; - %jmp/1 T_15.10, 8; - %load/vec4 v0x555555db4580_0; - %parti/s 1, 0, 2; - %or; -T_15.10; - %ix/load 4, 0, 0; - %ix/load 5, 0, 0; - %flag_set/imm 4, 0; - %assign/vec4/off/d v0x555555db4660_0, 4, 5; - %load/vec4 v0x555555db44c0_0; - %ix/load 4, 0, 0; - %ix/load 5, 0, 0; - %flag_set/imm 4, 0; - %assign/vec4/off/d v0x555555db4580_0, 4, 5; - %load/vec4 v0x555555db4580_0; - %parti/s 1, 0, 2; - %ix/load 4, 1, 0; - %ix/load 5, 0, 0; - %flag_set/imm 4, 0; - %assign/vec4/off/d v0x555555db4580_0, 4, 5; - %load/vec4 v0x555555db44c0_0; - %flag_set/vec4 8; - %jmp/1 T_15.12, 8; - %load/vec4 v0x555555db4580_0; - %parti/s 1, 1, 2; - %flag_set/vec4 9; - %flag_or 8, 9; -T_15.12; - %flag_get/vec4 8; - %jmp/1 T_15.11, 8; - %load/vec4 v0x555555db4580_0; - %parti/s 1, 0, 2; - %or; -T_15.11; - %ix/load 4, 0, 0; - %ix/load 5, 0, 0; - %flag_set/imm 4, 0; - %assign/vec4/off/d v0x555555db43e0_0, 4, 5; - %load/vec4 v0x555555db4260_0; - %assign/vec4 v0x555555db4320_0, 0; - %load/vec4 v0x555555db4260_0; - %flag_set/vec4 8; - %flag_get/vec4 8; - %jmp/1 T_15.13, 8; - %load/vec4 v0x555555db4320_0; - %or; -T_15.13; - %ix/load 4, 0, 0; - %ix/load 5, 0, 0; - %flag_set/imm 4, 0; - %assign/vec4/off/d v0x555555db4180_0, 4, 5; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.14 ; - %load/vec4 v0x555555dae670_0; - %pad/u 36; - %cmpi/u 2, 0, 36; - %jmp/0xz T_15.15, 5; - %load/vec4 v0x555555db43e0_0; - %load/vec4 v0x555555dae670_0; - %part/s 1; - %ix/load 5, 0, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %ix/vec4/s 4; - %assign/vec4/off/d v0x555555db43e0_0, 4, 5; - %load/vec4 v0x555555db4660_0; - %load/vec4 v0x555555dae670_0; - %part/s 1; - %ix/load 5, 0, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %ix/vec4/s 4; - %assign/vec4/off/d v0x555555db4660_0, 4, 5; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.14; -T_15.15 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.16 ; - %load/vec4 v0x555555dae670_0; - %pad/u 36; - %cmpi/u 3, 0, 36; - %jmp/0xz T_15.17, 5; - %load/vec4 v0x555555db4180_0; - %load/vec4 v0x555555dae670_0; - %part/s 1; - %ix/load 5, 0, 0; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %ix/vec4/s 4; - %assign/vec4/off/d v0x555555db4180_0, 4, 5; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.16; -T_15.17 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.18 ; - %load/vec4 v0x555555dae670_0; - %pad/s 36; - %cmpi/s 6, 0, 36; - %jmp/0xz T_15.19, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555db1280, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db1340, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.18; -T_15.19 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.20 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 2, 0, 32; - %jmp/0xz T_15.21, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dacb10, 4; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %shiftr 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dacb10, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.20; -T_15.21 ; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %load/vec4a v0x555555db1340, 4; - %parti/s 1, 0, 2; - %flag_set/vec4 8; - %jmp/0xz T_15.22, 8; - %load/vec4 v0x555555dae750_0; - %nor/r; - %assign/vec4 v0x555555dae750_0, 0; - %pushi/vec4 1, 0, 1; - %load/vec4 v0x555555dae750_0; - %pad/u 3; - %ix/vec4 4; - %flag_mov 8, 4; - %ix/getv 5, v0x555555daada0_0; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555dacb10, 5, 6; -T_15.22 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.24 ; - %load/vec4 v0x555555dae670_0; - %cmpi/u 8, 0, 32; - %jmp/0xz T_15.25, 5; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %load/vec4a v0x555555dacb10, 4; - %pushi/vec4 0, 0, 3; - %load/vec4 v0x555555daada0_0; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555daace0, 4; - %cmp/ne; - %flag_get/vec4 4; - %concat/vec4; draw_concat_vec4 - %part/u 1; - %flag_set/vec4 8; - %jmp/0xz T_15.26, 8; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 64, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 64, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 128, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 128, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 192, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 192, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 256, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 256, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 320, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 320, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 384, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 384, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 448, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 448, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; -T_15.26 ; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %load/vec4a v0x555555dacb10, 4; - %pushi/vec4 0, 0, 3; - %load/vec4 v0x555555daada0_0; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555daace0, 4; - %cmp/ne; - %flag_get/vec4 4; - %concat/vec4; draw_concat_vec4 - %part/u 1; - %flag_set/vec4 8; - %jmp/0xz T_15.28, 8; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 64, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 64, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 128, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 128, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 192, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 192, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 256, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 256, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 320, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 320, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 384, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 384, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; - %load/vec4 v0x555555dad7d0_0; - %pushi/vec4 448, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %part/u 8; - %ix/load 4, 1, 0; - %flag_set/imm 4, 0; - %flag_mov 8, 4; - %pushi/vec4 448, 0, 32; - %load/vec4 v0x555555dae670_0; - %muli 8, 0, 32; - %add; - %ix/vec4 5; - %flag_or 8, 4; - %ix/load 6, 0, 0; Constant delay - %ix/mov 3, 4; - %flag_mov 4, 8; - %assign/vec4/a/d v0x555555db0210, 5, 6; -T_15.28 ; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.24; -T_15.25 ; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %load/vec4a v0x555555dafe70, 4; - %parti/s 1, 0, 2; - %flag_set/vec4 8; - %jmp/0xz T_15.30, 8; - %load/vec4 v0x555555dae810_0; - %nor/r; - %assign/vec4 v0x555555dae810_0, 0; -T_15.30 ; - %pushi/vec4 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.32 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 16, 0, 32; - %jmp/0xz T_15.33, 5; - %ix/getv/s 4, v0x555555dae670_0; - %load/vec4a v0x555555dafe70, 4; - %load/vec4 v0x555555dae670_0; - %subi 1, 0, 32; - %ix/vec4/s 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dafe70, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.32; -T_15.33 ; - %pushi/vec4 0, 0, 17; - %ix/load 3, 15, 0; - %flag_set/imm 4, 0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dafe70, 0, 4; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %load/vec4a v0x555555db1340, 4; - %load/vec4 v0x555555daada0_0; - %pad/u 6; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dafe70, 0, 4; - %load/vec4 v0x555555dae010_0; - %nor/r; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_15.36, 9; - %load/vec4 v0x555555db2b20_0; - %pad/u 32; - %pushi/vec4 14, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_15.36; - %flag_set/vec4 8; - %jmp/0xz T_15.34, 8; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.37 ; - %load/vec4 v0x555555dae670_0; - %cmpi/s 16, 0, 32; - %jmp/0xz T_15.38, 5; - %pushi/vec4 0, 0, 17; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dafe70, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.37; -T_15.38 ; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_15.39 ; - %load/vec4 v0x555555dae670_0; - %pad/s 36; - %cmpi/s 6, 0, 36; - %jmp/0xz T_15.40, 5; - %pushi/vec4 0, 0, 17; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db1340, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_15.39; -T_15.40 ; -T_15.34 ; -T_15.1 ; - %jmp T_15; - .thread T_15; - .scope S_0x555555cfe490; -T_16 ; - %wait E_0x555555cb9a50; - %load/vec4 v0x555555dad990_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_16.0, 8; - %pushi/vec4 0, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %pushi/vec4 0, 0, 2; - %assign/vec4 v0x555555db2c00_0, 0; - %pushi/vec4 0, 0, 40; - %assign/vec4 v0x555555dad110_0, 0; - %pushi/vec4 0, 0, 4; - %assign/vec4 v0x555555dacd90_0, 0; - %pushi/vec4 0, 0, 6; - %assign/vec4 v0x555555dace70_0, 0; - %pushi/vec4 0, 0, 6; - %assign/vec4 v0x555555dad1f0_0, 0; - %pushi/vec4 0, 0, 6; - %assign/vec4 v0x555555dad2d0_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555daee90_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555dae8d0_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555daecd0_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x555555daccb0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3e80_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3dc0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3f40_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db0810_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db4000_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x555555db3b20_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db40c0_0, 0; - %pushi/vec4 0, 0, 10; - %assign/vec4 v0x555555db3c00_0, 0; - %pushi/vec4 0, 0, 512; - %assign/vec4 v0x555555db3ce0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db0690_0, 0; - %pushi/vec4 0, 0, 512; - %assign/vec4 v0x555555db10e0_0, 0; - %pushi/vec4 0, 0, 128; - %assign/vec4 v0x555555db4740_0, 0; - %pushi/vec4 0, 0, 4; - %assign/vec4 v0x555555daada0_0, 0; - %pushi/vec4 0, 0, 6; - %assign/vec4 v0x555555dad030_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dacf50_0, 0; - %pushi/vec4 0, 0, 5; - %assign/vec4 v0x555555dac890_0, 0; - %pushi/vec4 0, 0, 4; - %assign/vec4 v0x555555dac390_0, 0; - %pushi/vec4 0, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; -T_16.2 ; - %load/vec4 v0x555555dae670_0; - %cmpi/u 8, 0, 32; - %jmp/0xz T_16.3, 5; - %pushi/vec4 0, 0, 4; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555daace0, 0, 4; - %pushi/vec4 0, 0, 7; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dab910, 0, 4; - %pushi/vec4 0, 0, 5; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db0510, 0, 4; - %pushi/vec4 8, 0, 5; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db05d0, 0, 4; - %pushi/vec4 0, 0, 5; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dae410, 0, 4; - %pushi/vec4 8, 0, 5; - %ix/getv/s 3, v0x555555dae670_0; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dae5b0, 0, 4; - %load/vec4 v0x555555dae670_0; - %addi 1, 0, 32; - %store/vec4 v0x555555dae670_0, 0, 32; - %jmp T_16.2; -T_16.3 ; - %jmp T_16.1; -T_16.0 ; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db4000_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x555555db3b20_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db40c0_0, 0; - %pushi/vec4 0, 0, 10; - %assign/vec4 v0x555555db3c00_0, 0; - %pushi/vec4 0, 0, 512; - %assign/vec4 v0x555555db3ce0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3e80_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3dc0_0, 0; - %load/vec4 v0x555555db2c00_0; - %pad/u 32; - %cmpi/e 0, 0, 32; - %flag_mov 8, 4; - %jmp/0 T_16.4, 8; - %pushi/vec4 0, 0, 2; - %jmp/1 T_16.5, 8; -T_16.4 ; End of true expr. - %load/vec4 v0x555555db2c00_0; - %subi 1, 0, 2; - %jmp/0 T_16.5, 8; - ; End of false expr. - %blend; -T_16.5; - %assign/vec4 v0x555555db2c00_0, 0; - %load/vec4 v0x555555dac390_0; - %pad/u 32; - %cmpi/e 0, 0, 32; - %flag_mov 8, 4; - %jmp/0 T_16.6, 8; - %pushi/vec4 0, 0, 4; - %jmp/1 T_16.7, 8; -T_16.6 ; End of true expr. - %load/vec4 v0x555555dac390_0; - %subi 1, 0, 4; - %jmp/0 T_16.7, 8; - ; End of false expr. - %blend; -T_16.7; - %assign/vec4 v0x555555dac390_0, 0; - %load/vec4 v0x555555dac890_0; - %pad/u 32; - %cmpi/e 0, 0, 32; - %flag_mov 8, 4; - %jmp/0 T_16.8, 8; - %pushi/vec4 0, 0, 5; - %jmp/1 T_16.9, 8; -T_16.8 ; End of true expr. - %load/vec4 v0x555555dac890_0; - %subi 1, 0, 5; - %jmp/0 T_16.9, 8; - ; End of false expr. - %blend; -T_16.9; - %assign/vec4 v0x555555dac890_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555daee90_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555daf7f0_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555daf9b0_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555daf470_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555daf630_0, 0; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae410, 4; - %assign/vec4 v0x555555dae4d0_0, 0; - %load/vec4 v0x555555db38c0_0; - %flag_set/vec4 8; - %jmp/0xz T_16.10, 8; - %load/vec4 v0x555555db3480_0; - %load/vec4 v0x555555db3a40_0; - %part/u 1; - %flag_set/vec4 8; - %jmp/0 T_16.12, 8; - %load/vec4 v0x555555db33a0_0; - %jmp/1 T_16.13, 8; -T_16.12 ; End of true expr. - %load/vec4 v0x555555db3a40_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555db0510, 4; - %jmp/0 T_16.13, 8; - ; End of false expr. - %blend; -T_16.13; - %load/vec4 v0x555555db3a40_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db0510, 0, 4; - %load/vec4 v0x555555db3640_0; - %load/vec4 v0x555555db3a40_0; - %part/u 1; - %flag_set/vec4 8; - %jmp/0 T_16.14, 8; - %load/vec4 v0x555555db3560_0; - %jmp/1 T_16.15, 8; -T_16.14 ; End of true expr. - %load/vec4 v0x555555db3a40_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555db05d0, 4; - %jmp/0 T_16.15, 8; - ; End of false expr. - %blend; -T_16.15; - %load/vec4 v0x555555db3a40_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db05d0, 0, 4; - %load/vec4 v0x555555db3100_0; - %load/vec4 v0x555555db3a40_0; - %part/u 1; - %flag_set/vec4 8; - %jmp/0 T_16.16, 8; - %load/vec4 v0x555555db3020_0; - %jmp/1 T_16.17, 8; -T_16.16 ; End of true expr. - %load/vec4 v0x555555db3a40_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae410, 4; - %jmp/0 T_16.17, 8; - ; End of false expr. - %blend; -T_16.17; - %load/vec4 v0x555555db3a40_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dae410, 0, 4; - %load/vec4 v0x555555db32c0_0; - %load/vec4 v0x555555db3a40_0; - %part/u 1; - %flag_set/vec4 8; - %jmp/0 T_16.18, 8; - %load/vec4 v0x555555db31e0_0; - %jmp/1 T_16.19, 8; -T_16.18 ; End of true expr. - %load/vec4 v0x555555db3a40_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae5b0, 4; - %jmp/0 T_16.19, 8; - ; End of false expr. - %blend; -T_16.19; - %load/vec4 v0x555555db3a40_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dae5b0, 0, 4; - %load/vec4 v0x555555db3480_0; - %assign/vec4 v0x555555daf7f0_0, 0; - %load/vec4 v0x555555db3640_0; - %assign/vec4 v0x555555daf9b0_0, 0; - %load/vec4 v0x555555db3100_0; - %assign/vec4 v0x555555daf470_0, 0; - %load/vec4 v0x555555db32c0_0; - %assign/vec4 v0x555555daf630_0, 0; - %load/vec4 v0x555555db3a40_0; - %assign/vec4 v0x555555daecd0_0, 0; - %jmp T_16.11; -T_16.10 ; - %load/vec4 v0x555555db2b20_0; - %pad/u 32; - %cmpi/ne 14, 0, 32; - %jmp/0xz T_16.20, 4; - %load/vec4 v0x555555daf7f0_0; - %load/vec4 v0x555555daecd0_0; - %part/u 1; - %flag_set/vec4 8; - %jmp/0 T_16.22, 8; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555db0510, 4; - %addi 1, 0, 5; - %jmp/1 T_16.23, 8; -T_16.22 ; End of true expr. - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555db0510, 4; - %jmp/0 T_16.23, 8; - ; End of false expr. - %blend; -T_16.23; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db0510, 0, 4; - %load/vec4 v0x555555daf9b0_0; - %load/vec4 v0x555555daecd0_0; - %part/u 1; - %flag_set/vec4 8; - %jmp/0 T_16.24, 8; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555db05d0, 4; - %addi 1, 0, 5; - %jmp/1 T_16.25, 8; -T_16.24 ; End of true expr. - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555db05d0, 4; - %jmp/0 T_16.25, 8; - ; End of false expr. - %blend; -T_16.25; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db05d0, 0, 4; - %load/vec4 v0x555555daf470_0; - %load/vec4 v0x555555daecd0_0; - %part/u 1; - %flag_set/vec4 8; - %jmp/0 T_16.26, 8; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae410, 4; - %addi 1, 0, 5; - %jmp/1 T_16.27, 8; -T_16.26 ; End of true expr. - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae410, 4; - %jmp/0 T_16.27, 8; - ; End of false expr. - %blend; -T_16.27; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dae410, 0, 4; - %load/vec4 v0x555555daf630_0; - %load/vec4 v0x555555daecd0_0; - %part/u 1; - %flag_set/vec4 8; - %jmp/0 T_16.28, 8; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae5b0, 4; - %addi 1, 0, 5; - %jmp/1 T_16.29, 8; -T_16.28 ; End of true expr. - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae5b0, 4; - %jmp/0 T_16.29, 8; - ; End of false expr. - %blend; -T_16.29; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dae5b0, 0, 4; -T_16.20 ; -T_16.11 ; - %load/vec4 v0x555555dae8d0_0; - %flag_set/vec4 8; - %jmp/0xz T_16.30, 8; - %load/vec4 v0x555555dad3b0_0; - %assign/vec4 v0x555555dad1f0_0, 0; - %load/vec4 v0x555555dad3b0_0; - %assign/vec4 v0x555555dacbd0_0, 0; - %load/vec4 v0x555555dad3b0_0; - %assign/vec4 v0x555555dad2d0_0, 0; -T_16.30 ; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae5b0, 4; - %pad/u 32; - %cmpi/e 0, 0, 32; - %jmp/0xz T_16.32, 4; - %load/vec4 v0x555555dad2d0_0; - %subi 2, 0, 6; - %assign/vec4 v0x555555dad1f0_0, 0; -T_16.32 ; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae410, 4; - %pad/u 32; - %cmpi/e 0, 0, 32; - %flag_get/vec4 4; - %jmp/0 T_16.36, 4; - %load/vec4 v0x555555dae4d0_0; - %pad/u 32; - %pushi/vec4 31, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_16.36; - %flag_set/vec4 8; - %jmp/0xz T_16.34, 8; - %load/vec4 v0x555555dad2d0_0; - %subi 2, 0, 6; - %assign/vec4 v0x555555dacbd0_0, 0; -T_16.34 ; - %load/vec4 v0x555555db2b20_0; - %dup/vec4; - %pushi/vec4 0, 0, 5; - %cmp/u; - %jmp/1 T_16.37, 6; - %dup/vec4; - %pushi/vec4 1, 0, 5; - %cmp/u; - %jmp/1 T_16.38, 6; - %dup/vec4; - %pushi/vec4 2, 0, 5; - %cmp/u; - %jmp/1 T_16.39, 6; - %dup/vec4; - %pushi/vec4 3, 0, 5; - %cmp/u; - %jmp/1 T_16.40, 6; - %dup/vec4; - %pushi/vec4 4, 0, 5; - %cmp/u; - %jmp/1 T_16.41, 6; - %dup/vec4; - %pushi/vec4 5, 0, 5; - %cmp/u; - %jmp/1 T_16.42, 6; - %dup/vec4; - %pushi/vec4 6, 0, 5; - %cmp/u; - %jmp/1 T_16.43, 6; - %dup/vec4; - %pushi/vec4 7, 0, 5; - %cmp/u; - %jmp/1 T_16.44, 6; - %dup/vec4; - %pushi/vec4 8, 0, 5; - %cmp/u; - %jmp/1 T_16.45, 6; - %dup/vec4; - %pushi/vec4 9, 0, 5; - %cmp/u; - %jmp/1 T_16.46, 6; - %dup/vec4; - %pushi/vec4 10, 0, 5; - %cmp/u; - %jmp/1 T_16.47, 6; - %dup/vec4; - %pushi/vec4 11, 0, 5; - %cmp/u; - %jmp/1 T_16.48, 6; - %dup/vec4; - %pushi/vec4 12, 0, 5; - %cmp/u; - %jmp/1 T_16.49, 6; - %dup/vec4; - %pushi/vec4 13, 0, 5; - %cmp/u; - %jmp/1 T_16.50, 6; - %dup/vec4; - %pushi/vec4 14, 0, 5; - %cmp/u; - %jmp/1 T_16.51, 6; - %jmp T_16.52; -T_16.37 ; - %load/vec4 v0x555555dad630_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_16.55, 9; - %load/vec4 v0x555555daea70_0; - %pad/u 32; - %pushi/vec4 13, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_16.55; - %flag_set/vec4 8; - %jmp/0xz T_16.53, 8; - %pushi/vec4 1, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555daecd0_0, 0; - %pushi/vec4 255, 0, 8; - %assign/vec4 v0x555555daf7f0_0, 0; - %pushi/vec4 255, 0, 8; - %assign/vec4 v0x555555daf9b0_0, 0; - %pushi/vec4 255, 0, 8; - %assign/vec4 v0x555555daf470_0, 0; - %pushi/vec4 255, 0, 8; - %assign/vec4 v0x555555daf630_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db0690_0, 0; - %jmp T_16.54; -T_16.53 ; - %load/vec4 v0x555555daea70_0; - %pad/u 32; - %cmpi/e 13, 0, 32; - %jmp/0xz T_16.56, 4; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db0690_0, 0; -T_16.56 ; -T_16.54 ; - %jmp T_16.52; -T_16.38 ; - %load/vec4 v0x555555db2c00_0; - %pad/u 32; - %cmpi/e 0, 0, 32; - %jmp/0xz T_16.58, 4; - %load/vec4 v0x555555dad6f0_0; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %part/u 8; - %cmpi/e 120, 0, 8; - %jmp/0xz T_16.60, 4; - %pushi/vec4 2, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555dae8d0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dacf50_0, 0; - %pushi/vec4 0, 0, 6; - %assign/vec4 v0x555555dad030_0, 0; - %jmp T_16.61; -T_16.60 ; - %pushi/vec4 1, 0, 1; - %ix/load 5, 0, 0; - %ix/getv 4, v0x555555daecd0_0; - %assign/vec4/off/d v0x555555daee90_0, 4, 5; - %pushi/vec4 3, 0, 2; - %assign/vec4 v0x555555db2c00_0, 0; -T_16.61 ; -T_16.58 ; - %jmp T_16.52; -T_16.39 ; - %pushi/vec4 5, 0, 4; - %assign/vec4 v0x555555dac390_0, 0; - %pushi/vec4 3, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %pushi/vec4 0, 0, 4; - %assign/vec4 v0x555555dacd90_0, 0; - %jmp T_16.52; -T_16.40 ; - %load/vec4 v0x555555dac390_0; - %pad/u 32; - %cmpi/e 0, 0, 32; - %jmp/0xz T_16.62, 4; - %load/vec4 v0x555555dad8b0_0; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %part/u 8; - %load/vec4 v0x555555dad110_0; - %parti/s 32, 8, 5; - %concat/vec4; draw_concat_vec4 - %assign/vec4 v0x555555dad110_0, 0; - %load/vec4 v0x555555dacd90_0; - %addi 1, 0, 4; - %assign/vec4 v0x555555dacd90_0, 0; - %load/vec4 v0x555555dacd90_0; - %pad/u 32; - %cmpi/e 5, 0, 32; - %jmp/0xz T_16.64, 4; - %pushi/vec4 4, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %load/vec4 v0x555555dace70_0; - %assign/vec4 v0x555555dad030_0, 0; - %pushi/vec4 0, 0, 6; - %assign/vec4 v0x555555dace70_0, 0; -T_16.64 ; -T_16.62 ; - %jmp T_16.52; -T_16.41 ; - %load/vec4 v0x555555dad110_0; - %load/vec4 v0x555555dace70_0; - %part/u 10; - %cmpi/e 340, 0, 10; - %jmp/0xz T_16.66, 4; - %load/vec4 v0x555555dace70_0; - %load/vec4 v0x555555dad030_0; - %cmp/e; - %flag_mov 8, 4; - %jmp/0 T_16.68, 8; - %load/vec4 v0x555555dacf50_0; - %pad/u 2; - %addi 1, 0, 2; - %jmp/1 T_16.69, 8; -T_16.68 ; End of true expr. - %pushi/vec4 0, 0, 2; - %jmp/0 T_16.69, 8; - ; End of false expr. - %blend; -T_16.69; - %pad/u 1; - %assign/vec4 v0x555555dacf50_0, 0; - %load/vec4 v0x555555dacf50_0; - %pad/u 32; - %cmpi/e 1, 0, 32; - %jmp/0xz T_16.70, 4; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dae8d0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dacf50_0, 0; - %pushi/vec4 5, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %jmp T_16.71; -T_16.70 ; - %pushi/vec4 2, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; -T_16.71 ; - %jmp T_16.67; -T_16.66 ; - %load/vec4 v0x555555dace70_0; - %addi 1, 0, 6; - %assign/vec4 v0x555555dace70_0, 0; -T_16.67 ; - %jmp T_16.52; -T_16.42 ; - %load/vec4 v0x555555dad030_0; - %load/vec4 v0x555555dad1f0_0; - %cmp/e; - %jmp/0xz T_16.72, 4; - %load/vec4 v0x555555dacbd0_0; - %parti/s 3, 3, 3; - %pad/u 4; - %pushi/vec4 0, 0, 3; - %pushi/vec4 5, 0, 32; - %load/vec4 v0x555555dacbd0_0; - %parti/s 3, 0, 2; - %pad/u 32; - %cmp/u; - %flag_get/vec4 4; - %flag_get/vec4 5; - %or; - %concat/vec4; draw_concat_vec4 - %add; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555daace0, 0, 4; - %pushi/vec4 15420, 0, 16; - %load/vec4 v0x555555dacbd0_0; - %parti/s 3, 0, 2; - %ix/vec4 4; - %shiftr 4; - %assign/vec4 v0x555555daccb0_0, 0; - %pushi/vec4 6, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %jmp T_16.73; -T_16.72 ; - %pushi/vec4 1, 0, 1; - %ix/load 5, 0, 0; - %ix/getv 4, v0x555555daecd0_0; - %assign/vec4/off/d v0x555555daf470_0, 4, 5; - %pushi/vec4 1, 0, 1; - %ix/load 5, 0, 0; - %ix/getv 4, v0x555555daecd0_0; - %assign/vec4/off/d v0x555555daf630_0, 4, 5; - %pushi/vec4 2, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; -T_16.73 ; - %jmp T_16.52; -T_16.43 ; - %load/vec4 v0x555555db2c00_0; - %pad/u 32; - %cmpi/e 0, 0, 32; - %jmp/0xz T_16.74, 4; - %load/vec4 v0x555555dad6f0_0; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %part/u 8; - %load/vec4 v0x555555daccb0_0; - %parti/s 8, 0, 2; - %cmp/e; - %jmp/0xz T_16.76, 4; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %cmpi/e 4294967295, 0, 32; - %jmp/0xz T_16.78, 4; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db0690_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555daecd0_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db0810_0, 0; - %pushi/vec4 7, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %jmp T_16.79; -T_16.78 ; - %load/vec4 v0x555555daecd0_0; - %addi 1, 0, 3; - %assign/vec4 v0x555555daecd0_0, 0; - %pushi/vec4 1, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; -T_16.79 ; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555daace0, 4; - %load/vec4 v0x555555daada0_0; - %cmp/u; - %flag_mov 8, 5; - %jmp/0 T_16.80, 8; - %load/vec4 v0x555555daada0_0; - %jmp/1 T_16.81, 8; -T_16.80 ; End of true expr. - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555daace0, 4; - %jmp/0 T_16.81, 8; - ; End of false expr. - %blend; -T_16.81; - %assign/vec4 v0x555555daada0_0, 0; - %jmp T_16.77; -T_16.76 ; - %pushi/vec4 1, 0, 1; - %ix/load 5, 0, 0; - %ix/getv 4, v0x555555daecd0_0; - %assign/vec4/off/d v0x555555daee90_0, 4, 5; - %pushi/vec4 3, 0, 2; - %assign/vec4 v0x555555db2c00_0, 0; -T_16.77 ; -T_16.74 ; - %jmp T_16.52; -T_16.44 ; - %load/vec4 v0x555555daea70_0; - %pad/u 32; - %cmpi/e 17, 0, 32; - %jmp/0xz T_16.82, 4; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db3e80_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db3f40_0, 0; - %pushi/vec4 13, 0, 5; - %assign/vec4 v0x555555dac890_0, 0; - %pushi/vec4 8, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db0690_0, 0; -T_16.82 ; - %jmp T_16.52; -T_16.45 ; - %load/vec4 v0x555555dac890_0; - %pad/u 32; - %cmpi/e 0, 0, 32; - %jmp/0xz T_16.84, 4; - %load/vec4 v0x555555dad7d0_0; - %parti/s 1, 0, 2; - %assign/vec4 v0x555555db0810_0, 0; - %load/vec4 v0x555555db0810_0; - %load/vec4 v0x555555dad7d0_0; - %parti/s 1, 0, 2; - %concat/vec4; draw_concat_vec4 - %cmpi/e 1, 0, 2; - %jmp/0xz T_16.86, 4; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %cmpi/e 4294967295, 0, 32; - %jmp/0xz T_16.88, 4; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3f40_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db0690_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555daecd0_0, 0; - %pushi/vec4 9, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %jmp T_16.89; -T_16.88 ; - %load/vec4 v0x555555daecd0_0; - %addi 1, 0, 3; - %assign/vec4 v0x555555daecd0_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db0810_0, 0; - %pushi/vec4 7, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; -T_16.89 ; - %jmp T_16.87; -T_16.86 ; - %pushi/vec4 1, 0, 1; - %ix/load 5, 0, 0; - %ix/getv 4, v0x555555daecd0_0; - %assign/vec4/off/d v0x555555daf7f0_0, 4, 5; - %pushi/vec4 1, 0, 1; - %ix/load 5, 0, 0; - %ix/getv 4, v0x555555daecd0_0; - %assign/vec4/off/d v0x555555daf9b0_0, 4, 5; - %pushi/vec4 7, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; -T_16.87 ; -T_16.84 ; - %jmp T_16.52; -T_16.46 ; - %load/vec4 v0x555555daea70_0; - %pad/u 32; - %cmpi/e 22, 0, 32; - %flag_get/vec4 4; - %jmp/0 T_16.92, 4; - %load/vec4 v0x555555db0450_0; - %nor/r; - %and; -T_16.92; - %flag_set/vec4 8; - %jmp/0xz T_16.90, 8; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db4000_0, 0; - %pushi/vec4 1, 0, 16; - %assign/vec4 v0x555555db3b20_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db40c0_0, 0; - %pushi/vec4 0, 0, 10; - %assign/vec4 v0x555555db3c00_0, 0; - %pushi/vec4 2442236305, 0, 32; - %concati/vec4 2442236305, 0, 32; - %concati/vec4 4008636142, 0, 33; - %concati/vec4 4008636142, 0, 32; - %concati/vec4 2762253476, 0, 33; - %concati/vec4 2762253478, 0, 32; - %concati/vec4 3368601800, 0, 34; - %concati/vec4 3368601805, 0, 32; - %concati/vec4 3503345872, 0, 36; - %concati/vec4 3503345837, 0, 32; - %concati/vec4 2913840557, 0, 32; - %concati/vec4 2913840465, 0, 32; - %concati/vec4 2728567458, 0, 33; - %concati/vec4 2728567683, 0, 32; - %concati/vec4 2206434179, 0, 32; - %concati/vec4 4309441, 0, 23; - %assign/vec4 v0x555555db3ce0_0, 0; - %pushi/vec4 10, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; -T_16.90 ; - %jmp T_16.52; -T_16.47 ; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db4000_0, 0; - %pushi/vec4 1, 0, 16; - %assign/vec4 v0x555555db3b20_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db40c0_0, 0; - %pushi/vec4 8, 0, 10; - %assign/vec4 v0x555555db3c00_0, 0; - %pushi/vec4 2155905152, 0, 32; - %concati/vec4 2155905152, 0, 32; - %concati/vec4 3688618971, 0, 32; - %concati/vec4 3688618971, 0, 32; - %concati/vec4 3486502863, 0, 32; - %concati/vec4 3486502863, 0, 32; - %concati/vec4 3537031890, 0, 32; - %concati/vec4 3537031890, 0, 32; - %concati/vec4 3941264106, 0, 33; - %concati/vec4 3941264107, 0, 32; - %concati/vec4 3823363043, 0, 32; - %concati/vec4 3823363042, 0, 32; - %concati/vec4 2964369584, 0, 33; - %concati/vec4 2964369584, 0, 32; - %concati/vec4 4109694196, 0, 32; - %concati/vec4 1027423549, 0, 30; - %assign/vec4 v0x555555db3ce0_0, 0; - %pushi/vec4 11, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %jmp T_16.52; -T_16.48 ; - %load/vec4 v0x555555db0450_0; - %nor/r; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_16.95, 9; - %load/vec4 v0x555555db4000_0; - %pad/u 32; - %pushi/vec4 0, 0, 32; - %cmp/e; - %flag_get/vec4 4; - %and; -T_16.95; - %flag_set/vec4 8; - %jmp/0xz T_16.93, 8; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db4000_0, 0; - %pushi/vec4 0, 0, 16; - %assign/vec4 v0x555555db3b20_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db40c0_0, 0; - %pushi/vec4 12, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; -T_16.93 ; - %jmp T_16.52; -T_16.49 ; - %ix/load 4, 0, 0; - %flag_set/imm 4, 0; - %load/vec4a v0x555555dafe70, 4; - %cmpi/e 1, 0, 17; - %jmp/0xz T_16.96, 4; - %load/vec4 v0x555555db0130_0; - %assign/vec4 v0x555555db10e0_0, 0; - %pushi/vec4 13, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %pushi/vec4 0, 0, 7; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dab910, 0, 4; - %pushi/vec4 2161889234, 0, 32; - %concati/vec4 3957479547, 0, 33; - %concati/vec4 2344176742, 0, 34; - %concati/vec4 279794113, 0, 29; - %assign/vec4 v0x555555db4740_0, 0; -T_16.96 ; - %jmp T_16.52; -T_16.50 ; - %load/vec4 v0x555555db4740_0; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dab910, 4; - %part/u 64; - %load/vec4 v0x555555db10e0_0; - %pushi/vec4 448, 0, 32; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %add; - %part/u 8; - %load/vec4 v0x555555db10e0_0; - %pushi/vec4 384, 0, 32; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db10e0_0; - %pushi/vec4 320, 0, 32; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db10e0_0; - %pushi/vec4 256, 0, 32; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db10e0_0; - %pushi/vec4 192, 0, 32; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db10e0_0; - %pushi/vec4 128, 0, 32; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db10e0_0; - %pushi/vec4 64, 0, 32; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %load/vec4 v0x555555db10e0_0; - %pushi/vec4 0, 0, 32; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %muli 8, 0, 32; - %add; - %part/u 8; - %concat/vec4; draw_concat_vec4 - %cmp/e; - %jmp/0xz T_16.98, 4; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %cmpi/e 4294967295, 0, 32; - %jmp/0xz T_16.100, 4; - %pushi/vec4 14, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %jmp T_16.101; -T_16.100 ; - %load/vec4 v0x555555daecd0_0; - %addi 1, 0, 3; - %assign/vec4 v0x555555daecd0_0, 0; - %pushi/vec4 0, 0, 7; - %load/vec4 v0x555555daecd0_0; - %pad/u 32; - %addi 1, 0, 32; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dab910, 0, 4; -T_16.101 ; - %jmp T_16.99; -T_16.98 ; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dab910, 4; - %addi 8, 0, 7; - %load/vec4 v0x555555daecd0_0; - %pad/u 5; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555dab910, 0, 4; -T_16.99 ; - %jmp T_16.52; -T_16.51 ; - %pushi/vec4 14, 0, 5; - %assign/vec4 v0x555555db2b20_0, 0; - %load/vec4 v0x555555daea70_0; - %pad/u 32; - %cmpi/e 19, 0, 32; - %jmp/0xz T_16.102, 4; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db0690_0, 0; - %load/vec4 v0x555555db1ca0_0; - %nor/r; - %flag_set/vec4 10; - %flag_get/vec4 10; - %jmp/0 T_16.107, 10; - %load/vec4 v0x555555db2740_0; - %nor/r; - %and; -T_16.107; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_16.106, 9; - %load/vec4 v0x555555db02d0_0; - %and; -T_16.106; - %flag_set/vec4 8; - %jmp/0xz T_16.104, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db0690_0, 0; -T_16.104 ; -T_16.102 ; - %jmp T_16.52; -T_16.52 ; - %pop/vec4 1; -T_16.1 ; - %jmp T_16; - .thread T_16; - .scope S_0x555555cfe490; -T_17 ; - %wait E_0x555555cb9a50; - %load/vec4 v0x555555dad990_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_17.0, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3800_0, 0; - %jmp T_17.1; -T_17.0 ; - %load/vec4 v0x555555dadb30_0; - %flag_set/vec4 9; - %flag_get/vec4 9; - %jmp/0 T_17.4, 9; - %load/vec4 v0x555555dafcf0_0; - %nor/r; - %and; -T_17.4; - %flag_set/vec4 8; - %jmp/0xz T_17.2, 8; - %load/vec4 v0x555555daddb0_0; - %assign/vec4 v0x555555db3800_0, 0; - %load/vec4 v0x555555dade70_0; - %assign/vec4 v0x555555db3980_0, 0; - %load/vec4 v0x555555dada50_0; - %assign/vec4 v0x555555db2e60_0, 0; - %load/vec4 v0x555555dadbf0_0; - %assign/vec4 v0x555555db2f40_0, 0; - %load/vec4 v0x555555dadcd0_0; - %assign/vec4 v0x555555db3720_0, 0; - %jmp T_17.3; -T_17.2 ; - %load/vec4 v0x555555dafcf0_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_17.5, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3800_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db3980_0, 0; - %pushi/vec4 0, 0, 32; - %assign/vec4 v0x555555db2e60_0, 0; - %pushi/vec4 0, 0, 32; - %assign/vec4 v0x555555db2f40_0, 0; - %pushi/vec4 0, 0, 4; - %assign/vec4 v0x555555db3720_0, 0; -T_17.5 ; -T_17.3 ; -T_17.1 ; - %jmp T_17; - .thread T_17; - .scope S_0x555555cfe490; -T_18 ; - %wait E_0x555555cb9a50; - %load/vec4 v0x555555dad990_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_18.0, 8; - %pushi/vec4 0, 0, 5; - %assign/vec4 v0x555555db33a0_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555db3480_0, 0; - %pushi/vec4 0, 0, 5; - %assign/vec4 v0x555555db3560_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555db3640_0, 0; - %pushi/vec4 0, 0, 5; - %assign/vec4 v0x555555db3020_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555db3100_0, 0; - %pushi/vec4 0, 0, 5; - %assign/vec4 v0x555555db31e0_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555db32c0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db38c0_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555db3a40_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555dafb50_0, 0; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555dafcf0_0, 0; - %jmp T_18.1; -T_18.0 ; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555db3480_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555db3640_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555db3100_0, 0; - %pushi/vec4 0, 0, 8; - %assign/vec4 v0x555555db32c0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db38c0_0, 0; - %pushi/vec4 0, 0, 3; - %assign/vec4 v0x555555db3a40_0, 0; - %load/vec4 v0x555555db3800_0; - %flag_set/vec4 8; - %flag_get/vec4 8; - %jmp/0 T_18.2, 8; - %load/vec4 v0x555555dadb30_0; - %and; -T_18.2; - %assign/vec4 v0x555555dafb50_0, 0; - %load/vec4 v0x555555db2b20_0; - %pad/u 32; - %pushi/vec4 14, 0, 32; - %cmp/ne; - %flag_get/vec4 4; - %assign/vec4 v0x555555dafcf0_0, 0; - %load/vec4 v0x555555db3800_0; - %flag_set/vec4 8; - %jmp/0xz T_18.3, 8; - %load/vec4 v0x555555db2e60_0; - %parti/s 4, 0, 2; - %dup/vec4; - %pushi/vec4 0, 0, 4; - %cmp/u; - %jmp/1 T_18.5, 6; - %dup/vec4; - %pushi/vec4 1, 0, 4; - %cmp/u; - %jmp/1 T_18.6, 6; - %dup/vec4; - %pushi/vec4 2, 0, 4; - %cmp/u; - %jmp/1 T_18.7, 6; - %dup/vec4; - %pushi/vec4 3, 0, 4; - %cmp/u; - %jmp/1 T_18.8, 6; - %load/vec4 v0x555555db3980_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_18.11, 8; - %pushi/vec4 2863311530, 0, 32; - %assign/vec4 v0x555555dafc10_0, 0; -T_18.11 ; - %jmp T_18.10; -T_18.5 ; - %load/vec4 v0x555555db3980_0; - %flag_set/vec4 8; - %jmp/0xz T_18.13, 8; - %load/vec4 v0x555555db2f40_0; - %parti/s 5, 0, 2; - %assign/vec4 v0x555555db33a0_0, 0; - %pushi/vec4 1, 0, 8; - %load/vec4 v0x555555db2f40_0; - %parti/s 3, 5, 4; - %ix/vec4 4; - %shiftl 4; - %assign/vec4 v0x555555db3480_0, 0; - %load/vec4 v0x555555db3720_0; - %parti/s 1, 0, 2; - %assign/vec4 v0x555555db38c0_0, 0; - %jmp T_18.14; -T_18.13 ; - %pushi/vec4 0, 0, 27; - %load/vec4 v0x555555db2e60_0; - %parti/s 3, 4, 4; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555db0510, 4; - %concat/vec4; draw_concat_vec4 - %assign/vec4 v0x555555dafc10_0, 0; -T_18.14 ; - %jmp T_18.10; -T_18.6 ; - %load/vec4 v0x555555db3980_0; - %flag_set/vec4 8; - %jmp/0xz T_18.15, 8; - %load/vec4 v0x555555db2f40_0; - %parti/s 5, 0, 2; - %assign/vec4 v0x555555db3560_0, 0; - %pushi/vec4 1, 0, 8; - %load/vec4 v0x555555db2f40_0; - %parti/s 3, 5, 4; - %ix/vec4 4; - %shiftl 4; - %assign/vec4 v0x555555db3640_0, 0; - %load/vec4 v0x555555db3720_0; - %parti/s 1, 0, 2; - %assign/vec4 v0x555555db38c0_0, 0; - %jmp T_18.16; -T_18.15 ; - %pushi/vec4 0, 0, 27; - %load/vec4 v0x555555db2e60_0; - %parti/s 3, 4, 4; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555db05d0, 4; - %concat/vec4; draw_concat_vec4 - %assign/vec4 v0x555555dafc10_0, 0; -T_18.16 ; - %jmp T_18.10; -T_18.7 ; - %load/vec4 v0x555555db3980_0; - %flag_set/vec4 8; - %jmp/0xz T_18.17, 8; - %load/vec4 v0x555555db2f40_0; - %parti/s 5, 0, 2; - %assign/vec4 v0x555555db3020_0, 0; - %pushi/vec4 1, 0, 8; - %load/vec4 v0x555555db2f40_0; - %parti/s 3, 5, 4; - %ix/vec4 4; - %shiftl 4; - %assign/vec4 v0x555555db3100_0, 0; - %load/vec4 v0x555555db3720_0; - %parti/s 1, 0, 2; - %assign/vec4 v0x555555db38c0_0, 0; - %jmp T_18.18; -T_18.17 ; - %pushi/vec4 0, 0, 27; - %load/vec4 v0x555555db2e60_0; - %parti/s 3, 4, 4; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae410, 4; - %concat/vec4; draw_concat_vec4 - %assign/vec4 v0x555555dafc10_0, 0; -T_18.18 ; - %jmp T_18.10; -T_18.8 ; - %load/vec4 v0x555555db3980_0; - %flag_set/vec4 8; - %jmp/0xz T_18.19, 8; - %load/vec4 v0x555555db2f40_0; - %parti/s 5, 0, 2; - %assign/vec4 v0x555555db31e0_0, 0; - %pushi/vec4 1, 0, 8; - %load/vec4 v0x555555db2f40_0; - %parti/s 3, 5, 4; - %ix/vec4 4; - %shiftl 4; - %assign/vec4 v0x555555db32c0_0, 0; - %load/vec4 v0x555555db3720_0; - %parti/s 1, 0, 2; - %assign/vec4 v0x555555db38c0_0, 0; - %jmp T_18.20; -T_18.19 ; - %pushi/vec4 0, 0, 27; - %load/vec4 v0x555555db2e60_0; - %parti/s 3, 4, 4; - %pad/u 5; - %ix/vec4 4; - %load/vec4a v0x555555dae5b0, 4; - %concat/vec4; draw_concat_vec4 - %assign/vec4 v0x555555dafc10_0, 0; -T_18.20 ; - %jmp T_18.10; -T_18.10 ; - %pop/vec4 1; - %load/vec4 v0x555555db2f40_0; - %parti/s 3, 5, 4; - %assign/vec4 v0x555555db3a40_0, 0; -T_18.3 ; -T_18.1 ; - %jmp T_18; - .thread T_18; - .scope S_0x555555cfe490; -T_19 ; - %vpi_call 2 1786 "$display", "TEST FUNCTIONS\012-----------------------------\012" {0 0 0}; - %vpi_call 2 1787 "$display", "Test ns_to_cycles() function:" {0 0 0}; - %pushi/vec4 15, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %vpi_call 2 1788 "$display", "\011ns_to_cycles(15) = %0d [exact]", S<0,vec4,u19> {1 0 0}; - %pushi/vec4 15, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %vpi_call 2 1789 "$display", "\011ns_to_cycles(14.5) = %0d [round-off]", S<0,vec4,u19> {1 0 0}; - %pushi/vec4 11, 0, 32; - %store/vec4 v0x555555da86c0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_cycles, S_0x555555da84e0; - %vpi_call 2 1790 "$display", "\011ns_to_cycles(11) = %0d [round-up]\012", S<0,vec4,u19> {1 0 0}; - %vpi_call 2 1792 "$display", "Test nCK_to_cycles() function:" {0 0 0}; - %pushi/vec4 16, 0, 32; - %store/vec4 v0x555555da7e80_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_cycles, S_0x555555da7ca0; - %vpi_call 2 1793 "$display", "\011ns_to_cycles(16) = %0d [exact]", S<0,vec4,u19> {1 0 0}; - %pushi/vec4 15, 0, 32; - %store/vec4 v0x555555da7e80_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_cycles, S_0x555555da7ca0; - %vpi_call 2 1794 "$display", "\011ns_to_cycles(15) = %0d [round-off]", S<0,vec4,u19> {1 0 0}; - %pushi/vec4 13, 0, 32; - %store/vec4 v0x555555da7e80_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_cycles, S_0x555555da7ca0; - %vpi_call 2 1795 "$display", "\011ns_to_cycles(13) = %0d [round-up]\012", S<0,vec4,u19> {1 0 0}; - %vpi_call 2 1797 "$display", "Test ns_to_nCK() function:" {0 0 0}; - %pushi/vec4 15, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %vpi_call 2 1798 "$display", "\011ns_to_cycles(15) = %0d [exact]", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 15, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %vpi_call 2 1799 "$display", "\011ns_to_cycles(14.875) = %0d [round-off]", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 14, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %vpi_call 2 1800 "$display", "\011ns_to_cycles(13.875) = %0d [round-up] \012", S<0,vec4,s32> {1 0 0}; - %vpi_call 2 1802 "$display", "Test nCK_to_ns() function:" {0 0 0}; - %pushi/vec4 4, 0, 32; - %store/vec4 v0x555555da8300_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120; - %vpi_call 2 1803 "$display", "\011ns_to_cycles(4) = %0d [exact]", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 3, 0, 32; - %store/vec4 v0x555555da8300_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120; - %vpi_call 2 1804 "$display", "\011ns_to_cycles(14.875) = %0d [round-off]", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 5, 0, 32; - %store/vec4 v0x555555da8300_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120; - %vpi_call 2 1805 "$display", "\011ns_to_cycles(13.875) = %0d [round-up]\012", S<0,vec4,s32> {1 0 0}; - %vpi_call 2 1807 "$display", "Test nCK_to_ns() function:" {0 0 0}; - %pushi/vec4 4, 0, 32; - %store/vec4 v0x555555da8300_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120; - %vpi_call 2 1808 "$display", "\011ns_to_cycles(4) = %0d [exact]", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 3, 0, 32; - %store/vec4 v0x555555da8300_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120; - %vpi_call 2 1809 "$display", "\011ns_to_cycles(14.875) = %0d [round-off]", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 5, 0, 32; - %store/vec4 v0x555555da8300_0, 0, 32; - %callf/vec4 TD_ddr3_controller.nCK_to_ns, S_0x555555da8120; - %vpi_call 2 1810 "$display", "\011ns_to_cycles(13.875) = %0d [round-up]\012", S<0,vec4,s32> {1 0 0}; - %vpi_call 2 1812 "$display", "Test $floor() function:" {0 0 0}; - %pushi/real 1073741824, 4067; load=2.00000 - %vpi_call 2 1813 "$display", "\011$floor(5/2) = %0d", W<0,r> {0 1 0}; - %pushi/real 1073741824, 4067; load=2.00000 - %vpi_call 2 1814 "$display", "\011$floor(9/4) = %0d", W<0,r> {0 1 0}; - %pushi/real 1073741824, 4067; load=2.00000 - %vpi_call 2 1815 "$display", "\011$floor(9/4) = %0d", W<0,r> {0 1 0}; - %pushi/real 1073741824, 4066; load=1.00000 - %vpi_call 2 1816 "$display", "\011$floor(9/5) = %0d\012", W<0,r> {0 1 0}; - %vpi_call 2 1818 "$display", "\012DISPLAY CONTROLLER PARAMETERS\012-----------------------------\012" {0 0 0}; - %vpi_call 2 1819 "$display", "DELAY_COUNTER_WIDTH = %0d", P_0x555555d8dee0 {0 0 0}; - %vpi_call 2 1820 "$display", "DELAY_SLOT_WIDTH = %0d", P_0x555555d8df60 {0 0 0}; - %vpi_call 2 1823 "$display", "serdes_ratio = %0d", P_0x555555d8f1e0 {0 0 0}; - %vpi_call 2 1824 "$display", "wb_addr_bits = %0d", P_0x555555d8f660 {0 0 0}; - %vpi_call 2 1825 "$display", "wb_data_bits = %0d", P_0x555555d8f6a0 {0 0 0}; - %vpi_call 2 1826 "$display", "wb_sel_bits = %0d\012\012", P_0x555555d8f6e0 {0 0 0}; - %vpi_call 2 1831 "$display", "READ_SLOT = %0d", P_0x555555d8eae0 {0 0 0}; - %vpi_call 2 1832 "$display", "WRITE_SLOT = %0d", P_0x555555d8f0a0 {0 0 0}; - %vpi_call 2 1833 "$display", "ACTIVATE_SLOT = %0d", P_0x555555d8d320 {0 0 0}; - %vpi_call 2 1834 "$display", "PRECHARGE_SLOT = %0d", P_0x555555d8e8e0 {0 0 0}; - %vpi_call 2 1836 "$display", "\012\012DELAYS:" {0 0 0}; - %pushi/vec4 14, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %vpi_call 2 1837 "$display", "\011ns_to_nCK(tRCD): %0d", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 14, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %vpi_call 2 1838 "$display", "\011ns_to_nCK(tRP): %0d", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 10, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %vpi_call 2 1839 "$display", "\011ns_to_nCK(tRTP): %0d", S<0,vec4,s32> {1 0 0}; - %vpi_call 2 1840 "$display", "\011tCCD: %0d", P_0x555555d8f220 {0 0 0}; - %vpi_call 2 1841 "$display", "\011(CL_nCK + tCCD + 2 - CWL_nCK): %0d", 32'sb00000000000000000000000000000111 {0 0 0}; - %pushi/vec4 9, 0, 32; - %pushi/vec4 15, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %add; - %vpi_call 2 1842 "$display", "\011(CWL_nCK + 4 + ns_to_nCK(tWR)): %0d", S<0,vec4,s32> {1 0 0}; - %pushi/vec4 9, 0, 32; - %pushi/vec4 10, 0, 32; - %store/vec4 v0x555555da8bd0_0, 0, 32; - %callf/vec4 TD_ddr3_controller.ns_to_nCK, S_0x555555da8960; - %add; - %vpi_call 2 1843 "$display", "\011(CWL_nCK + 4 + ns_to_nCK(tWTR)): %0d", S<0,vec4,s32> {1 0 0}; - %vpi_call 2 1845 "$display", "\012\012PRECHARGE_TO_ACTIVATE_DELAY = %0d", P_0x555555d8e920 {0 0 0}; - %vpi_call 2 1846 "$display", "ACTIVATE_TO_WRITE_DELAY = %0d", P_0x555555d8d3e0 {0 0 0}; - %vpi_call 2 1847 "$display", "ACTIVATE_TO_READ_DELAY = %0d", P_0x555555d8d3a0 {0 0 0}; - %vpi_call 2 1848 "$display", "READ_TO_WRITE_DELAY = %0d", P_0x555555d8eba0 {0 0 0}; - %vpi_call 2 1849 "$display", "READ_TO_READ_DELAY = %0d", P_0x555555d8eb60 {0 0 0}; - %vpi_call 2 1850 "$display", "READ_TO_PRECHARGE_DELAY = %0d", P_0x555555d8eb20 {0 0 0}; - %vpi_call 2 1851 "$display", "WRITE_TO_WRITE_DELAY = %0d", P_0x555555d8f160 {0 0 0}; - %vpi_call 2 1852 "$display", "WRITE_TO_READ_DELAY = %0d", P_0x555555d8f120 {0 0 0}; - %vpi_call 2 1853 "$display", "WRITE_TO_PRECHARGE_DELAY = %0d", P_0x555555d8f0e0 {0 0 0}; - %vpi_call 2 1854 "$display", "STAGE2_DATA_DEPTH = %0d", P_0x555555d8ede0 {0 0 0}; - %vpi_call 2 1855 "$display", "READ_ACK_PIPE_WIDTH = %0d", P_0x555555d8ea20 {0 0 0}; - %end; - .thread T_19; - .scope S_0x555555d02bb0; -T_20 ; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db5d50_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db5ad0_0, 0, 1; - %end; - .thread T_20; - .scope S_0x555555d02bb0; -T_21 ; - %pushi/vec4 1, 0, 1; - %store/vec4 v0x555555db5400_0, 0, 1; - %pushi/vec4 0, 0, 1; - %store/vec4 v0x555555db5610_0, 0, 1; - %end; - .thread T_21; - .scope S_0x555555d02bb0; -T_22 ; - %wait E_0x555555d8c690; - %load/vec4 v0x555555db5790_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_22.0, 8; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db5400_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db5610_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db5ad0_0, 0; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db5d50_0, 0; - %jmp T_22.1; -T_22.0 ; - %load/vec4 v0x555555db5a10_0; - %flag_set/vec4 8; - %jmp/0xz T_22.2, 8; - %load/vec4 v0x555555db5c90_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_22.4, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db5610_0, 0; -T_22.4 ; - %load/vec4 v0x555555db5ad0_0; - %pad/u 2; - %addi 1, 0, 2; - %pad/u 1; - %assign/vec4 v0x555555db5ad0_0, 0; - %load/vec4 v0x555555db5ad0_0; - %addi 1, 0, 1; - %load/vec4 v0x555555db5d50_0; - %cmp/e; - %flag_get/vec4 4; - %jmp/0 T_22.8, 4; - %load/vec4 v0x555555db5c90_0; - %nor/r; - %and; -T_22.8; - %flag_set/vec4 8; - %jmp/0xz T_22.6, 8; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db5400_0, 0; -T_22.6 ; -T_22.2 ; - %load/vec4 v0x555555db5c90_0; - %flag_set/vec4 8; - %jmp/0xz T_22.9, 8; - %load/vec4 v0x555555db5a10_0; - %nor/r; - %flag_set/vec4 8; - %jmp/0xz T_22.11, 8; - %pushi/vec4 0, 0, 1; - %assign/vec4 v0x555555db5400_0, 0; -T_22.11 ; - %load/vec4 v0x555555db5bb0_0; - %load/vec4 v0x555555db5d50_0; - %pad/u 3; - %ix/vec4 3; - %ix/load 4, 0, 0; Constant delay - %assign/vec4/a/d v0x555555db54c0, 0, 4; - %load/vec4 v0x555555db5d50_0; - %pad/u 2; - %addi 1, 0, 2; - %pad/u 1; - %assign/vec4 v0x555555db5d50_0, 0; - %load/vec4 v0x555555db5d50_0; - %addi 1, 0, 1; - %load/vec4 v0x555555db5ad0_0; - %cmp/e; - %flag_get/vec4 4; - %jmp/0 T_22.15, 4; - %load/vec4 v0x555555db5a10_0; - %nor/r; - %and; -T_22.15; - %flag_set/vec4 8; - %jmp/0xz T_22.13, 8; - %pushi/vec4 1, 0, 1; - %assign/vec4 v0x555555db5610_0, 0; -T_22.13 ; -T_22.9 ; -T_22.1 ; - %jmp T_22; - .thread T_22; -# The file index is used to find the file name in the following table. -:file_names 3; - "N/A"; - ""; - "rtl/ddr3_controller.v"; diff --git a/rtl/.ddr3_controller.v.swo b/rtl/.ddr3_controller.v.swo deleted file mode 100644 index 33b8e11..0000000 Binary files a/rtl/.ddr3_controller.v.swo and /dev/null differ diff --git a/rtl/.ddr3_controller.v.swp b/rtl/.ddr3_controller.v.swp deleted file mode 100644 index 67fdd59..0000000 Binary files a/rtl/.ddr3_controller.v.swp and /dev/null differ diff --git a/rtl/.ddr3_phy.v.swp b/rtl/.ddr3_phy.v.swp deleted file mode 100644 index 0f388eb..0000000 Binary files a/rtl/.ddr3_phy.v.swp and /dev/null differ diff --git a/rtl/.ddr3_top.v.swp b/rtl/.ddr3_top.v.swp deleted file mode 100644 index 8db8640..0000000 Binary files a/rtl/.ddr3_top.v.swp and /dev/null differ diff --git a/rtl/ddr3_controller.v~ b/rtl/ddr3_controller.v~ deleted file mode 100644 index 5a4323c..0000000 --- a/rtl/ddr3_controller.v~ +++ /dev/null @@ -1,3419 +0,0 @@ -// Background: -// This DDR3 controller will be used with a DDR3-1600 with Kintex 7 FPGA Board (XC7K160T-3FFG676E). -// The goal will be to: -// - Run this at 1600Mbps (Maximum Physical Interface (PHY) Rate for a 4:1 -// memory controller based on "DC and AC Switching Characteristics" for Kintex 7) -// - Parameterize everything -// - Interface should be (nearly) bus agnostic -// - High (sustained) data throughput. Sequential writes should be able to continue without interruption - -`define MICRON_SIM //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW) -//`define FORMAL_COVER //change delay in reset sequence to fit in cover statement -//`define COVER_DELAY 1 //fixed delay used in formal cover for reset sequence -`default_nettype none - - -// THESE DEFINES WILL BE MODIFIED AS PARAMETERS LATER ON -`define DDR3_1600_11_11_11 // DDR3-1600 (11-11-11) speed bin -`define RAM_8Gb //DDR3 Capacity -//`define RAM_2Gb -//`define RAM_4Gb -//`define RAM_8Gb -`define x8 //DDR3 organization (DQ bus width) -//`define x4 -//`define x16 - -//NOTE IN FORMAL INDUCTION: Make formal induction finish in shorter time by lowering the delays between commands. -//A good basis on the formal depth is the value of PRE_STALL_DELAY. -//The value of prestall delay is the longest possible -//clock cycles needed to finish 2 requests. Since the -//fifo used in the formal induction has 2 locations -//only (pertains to the request stored on the two -// pipeline stages of bank access), we need to flush -// those two requests on the fifo first, and the max -// time for two request is also the value of -// PRE_STALL_DELAY - -module ddr3_controller #( - parameter real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module - DDR3_CLK_PERIOD = 2.5, //ns, period of clock input to DDR3 RAM device - parameter[31:0]ROW_BITS = 16, //width of row address - COL_BITS = 10, //width of column address - BA_BITS = 3, //width of bank address - DQ_BITS = 8, //width of DQ - LANES = 8, //8 lanes of DQ - AUX_WIDTH = 16, - WB2_ADDR_BITS = 32, - WB2_DATA_BITS = 32, - parameter[0:0] OPT_LOWPOWER = 1, //1 = low power, 0 = low logic - OPT_BUS_ABORT = 1, //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction) - - parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration - serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD), - wb_addr_bits = ROW_BITS + COL_BITS + BA_BITS - $clog2(DQ_BITS*(serdes_ratio)*2 / 8), - wb_data_bits = DQ_BITS*LANES*serdes_ratio*2, - wb_sel_bits = wb_data_bits / 8, - wb2_sel_bits = WB2_DATA_BITS / 8, - //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits - cmd_len = 4 + 3 + BA_BITS + ROW_BITS - ) - ( - input wire i_controller_clk, //i_controller_clk has period of CONTROLLER_CLK_PERIOD - input wire i_rst_n, //200MHz input clock - // Wishbone inputs - input wire i_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) - input wire i_wb_stb, //request a transfer - input wire i_wb_we, //write-enable (1 = write, 0 = read) - input wire[wb_addr_bits - 1:0] i_wb_addr, //burst-addressable {row,bank,col} - input wire[wb_data_bits - 1:0] i_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device - input wire[wb_sel_bits - 1:0] i_wb_sel, //byte strobe for write (1 = write the byte) - input wire[AUX_WIDTH - 1:0] i_aux, //for AXI-interface compatibility (given upon strobe) - // Wishbone outputs - output reg o_wb_stall, //1 = busy, cannot accept requests - output wire o_wb_ack, //1 = read/write request has completed - output wire[wb_data_bits - 1:0] o_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device - output wire[AUX_WIDTH - 1:0] o_aux, //for AXI-interface compatibility (returned upon ack) - // - // Wishbone 2 (PHY) inputs - input wire i_wb2_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) - input wire i_wb2_stb, //request a transfer - input wire i_wb2_we, //write-enable (1 = write, 0 = read) - input wire[WB2_ADDR_BITS - 1:0] i_wb2_addr, //memory-mapped register to be accessed - input wire[wb2_sel_bits - 1:0] i_wb2_sel, //byte strobe for write (1 = write the byte) - input wire[WB2_DATA_BITS - 1:0] i_wb2_data, //write data - // Wishbone 2 (Controller) outputs - output reg o_wb2_stall, //1 = busy, cannot accept requests - output reg o_wb2_ack, //1 = read/write request has completed - output reg[WB2_DATA_BITS - 1:0] o_wb2_data, //read data - // - // PHY interface - input wire[DQ_BITS*LANES*8-1:0] i_phy_iserdes_data, - input wire[LANES*8-1:0] i_phy_iserdes_dqs, - input wire[LANES*8-1:0] i_phy_iserdes_bitslip_reference, - input wire i_phy_idelayctrl_rdy, - output wire[cmd_len*serdes_ratio-1:0] o_phy_cmd, - output wire o_phy_dqs_tri_control, o_phy_dq_tri_control, - output wire o_phy_toggle_dqs, - output wire[wb_data_bits-1:0] o_phy_data, - output wire[wb_sel_bits-1:0] o_phy_dm, - output wire[4:0] o_phy_odelay_data_cntvaluein, o_phy_odelay_dqs_cntvaluein, - output wire[4:0] o_phy_idelay_data_cntvaluein, o_phy_idelay_dqs_cntvaluein, - output reg[LANES-1:0] o_phy_odelay_data_ld, o_phy_odelay_dqs_ld, - output reg[LANES-1:0] o_phy_idelay_data_ld, o_phy_idelay_dqs_ld, - output reg[LANES-1:0] o_phy_bitslip - ); - - - /************************************************************* Command Parameters *************************************************************/ - //DDR3 commands {cs_n, ras_n, cas_n, we_n} (JEDEC DDR3 doc pg. 33 ) - localparam[3:0]CMD_MRS = 4'b0000, // Mode Register Set - CMD_REF = 4'b0001, // Refresh - CMD_PRE = 4'b0010, // Precharge (A10-AP: 0 = Single Bank Precharge, 1 = Precharge All Banks) - CMD_ACT = 4'b0011, // Bank Activate - CMD_WR = 4'b0100, // Write (A10-AP: 0 = no Auto-Precharge) (A12-BC#: 1 = Burst Length 8) - CMD_RD = 4'b0101, //Read (A10-AP: 0 = no Auto-Precharge) (A12-BC#: 1 = Burst Length 8) - CMD_NOP = 4'b0111, // No Operation - CMD_DES = 4'b1000, // Deselect command performs the same function as No Operation command (JEDEC DDR3 doc pg. 34 NOTE 11) - CMD_ZQC = 4'b0110; // ZQ Calibration (A10-AP: 0 = ZQ Calibration Short, 1 = ZQ Calibration Long) - - localparam RST_DONE = 27, // Command bit that determines if reset seqeunce had aready finished. non-persistent (only needs to be toggled once), - REF_IDLE = 27, // No refresh is about to start and no ongoing refresh. (same bit as RST_DONE) - USE_TIMER = 26, // Command bit that determines if timer will be used (if delay is zero, USE_TIMER must be LOW) - A10_CONTROL = 25, //Command bit that determines if A10 AutoPrecharge will be high - CLOCK_EN = 24, //Clock-enable to DDR3 - RESET_N = 23, //Reset_n to DDR3 - DDR3_CMD_START = 22, //Start of DDR3 command slot - DDR3_CMD_END = 19, //end of DDR3 command slot - MRS_BANK_START = 18; //start of bank value in MRS value - - // ddr3 command partitioning - localparam CMD_CS_N = cmd_len - 1, - CMD_RAS_N = cmd_len - 2, - CMD_CAS_N= cmd_len - 3, - CMD_WE_N = cmd_len - 4, - CMD_ODT = cmd_len - 5, - CMD_CKE = cmd_len - 6, - CMD_RESET_N = cmd_len - 7, - CMD_BANK_START = BA_BITS + ROW_BITS - 1, - CMD_ADDRESS_START = ROW_BITS - 1; - - localparam READ_SLOT = get_slot(CMD_RD), - WRITE_SLOT = get_slot(CMD_WR), - ACTIVATE_SLOT = get_slot(CMD_ACT), - PRECHARGE_SLOT = get_slot(CMD_PRE); - - // Data does not have to be delayed (DQS is the on that has to be - // delayed and center-aligned to the center eye of data) - localparam DATA_INITIAL_ODELAY_TAP = 0; - - //DQS needs to be edge-aligned to the center eye of the data. - //This means DQS needs to be delayed by a quarter of the ddr3 - //clk period relative to the data. Subtract by 600ps to include - //the IODELAY insertion delay. Divide by a delay resolution of - //78.125ps per tap to get the needed tap value. Then add the tap - //value used in data to have the delay relative to the data. - localparam DQS_INITIAL_ODELAY_TAP = $rtoi(((DDR3_CLK_PERIOD*1000/4))/78.125 + DATA_INITIAL_ODELAY_TAP); - - //Incoming DQS should be 90 degree delayed relative to incoming data - localparam DATA_INITIAL_IDELAY_TAP = 0; //600ps delay - localparam DQS_INITIAL_IDELAY_TAP = $rtoi(((DDR3_CLK_PERIOD*1000/4))/78.125 + DATA_INITIAL_IDELAY_TAP); - /*********************************************************************************************************************************************/ - - - /********************************************************** Timing Parameters ***********************************************************************************/ - localparam DELAY_SLOT_WIDTH = 19; //Bitwidth of the delay slot and mode register slot on the reset/refresh rom will be at the same size as the Mode Register - localparam POWER_ON_RESET_HIGH = 200_000; // 200us reset must be active at initialization - localparam INITIAL_CKE_LOW = 500_000; // 500us cke must be low before activating - `ifdef DDR3_1600_11_11_11 //DDR3-1600 (11-11-11) speed bin - localparam tRCD = 13.750; // ns Active to Read/Write command time - localparam tRP = 13.750; // ns Precharge command period - localparam tRAS = 35; // ns ACT to PRE command period - `endif - - `ifdef RAM_1Gb - localparam tRFC = 110.0; // ns Refresh command to ACT or REF - `elsif RAM_2Gb - localparam tRFC = 160.0; // ns Refresh command to ACT or REF - `elsif RAM_4Gb - localparam tRFC = 300.0; // ns Refresh command to ACT or REF - `else - localparam tRFC = 350.0; // ns Refresh command to ACT or REF - `endif - localparam tREFI = 7800; //ns Average periodic refresh interval - /* verilator lint_off REALCVT */ - localparam tXPR = max(5*DDR3_CLK_PERIOD, tRFC+10); // ns Exit Reset from CKE HIGH to a valid command - localparam tMRD = 4; // nCK Mode Register Set command cycle time - localparam tWR = 15.0; // ns Write Recovery Time - localparam tWTR = max(nCK_to_ns(4), 7.5); //ns Delay from start of internal write transaction to internal read command - localparam[DELAY_SLOT_WIDTH - 1:0] tWLMRD = nCK_to_cycles(40); // nCK First DQS/DQS# rising edge after write leveling mode is programmed - localparam tWLO = 7.5; //ns Write leveling output delay - localparam tWLOE = 2; - localparam tRTP = max(nCK_to_ns(4), 7.5); //ns Internal Command to PRECHARGE Command delay - /* verilator lint_on REALCVT */ - localparam tCCD = 4; //nCK CAS to CAS command delay - /* verilator lint_off WIDTH */ - localparam[DELAY_SLOT_WIDTH - 1:0] tMOD = max(nCK_to_cycles(12), ns_to_cycles(15)); //cycles (controller) Mode Register Set command update delay - localparam[DELAY_SLOT_WIDTH - 1:0] tZQinit = max(nCK_to_cycles(512), ns_to_cycles(640));//cycles (controller) Power-up and RESET calibration time - /* verilator lint_on WIDTH */ - localparam CL_nCK = 6; //create a function for this - localparam CWL_nCK = 5; //create a function for this - localparam DELAY_MAX_VALUE = ns_to_cycles(INITIAL_CKE_LOW); //Largest possible delay needed by the reset and refresh sequence - localparam DELAY_COUNTER_WIDTH= $clog2(DELAY_MAX_VALUE); //Bitwidth needed by the maximum possible delay, this will be the delay counter width - localparam CALIBRATION_DELAY = 2; - localparam PRE_REFRESH_DELAY = WRITE_TO_PRECHARGE_DELAY + 1; - //localparam PRE_STALL_DELAY = ((PRECHARGE_TO_ACTIVATE_DELAY+1) + (ACTIVATE_TO_WRITE_DELAY+1) + (WRITE_TO_PRECHARGE_DELAY+1) + 1)*2; - //worst case scenario: two consecutive writes at same bank but different row - //delay will be: PRECHARGE -> PRECHARGE_TO_ACTIVATE_DELAY -> ACTIVATE -> ACTIVATE_TO_WRITE_DELAY -> WRITE -> WRITE_TO_PRECHARGE_DELAY -> - //PRECHARGE -> PRECHARGE_TO_ACTIVATE_DELAY -> ACTIVATE -> ACTIVATE_TO_WRITE_DELAY -> WRITE -> WRITE_TO_PRECHARGE_DELAY - - /*********************************************************************************************************************************************/ - - - /********************************************************** Computed Delay Parameters **********************************************************/ - /* verilator lint_off REALCVT */ - localparam[3:0] PRECHARGE_TO_ACTIVATE_DELAY = find_delay(ns_to_nCK(tRP), PRECHARGE_SLOT, ACTIVATE_SLOT); //3 - localparam[3:0] ACTIVATE_TO_PRECHARGE_DELAY = find_delay(ns_to_nCK(tRAS), ACTIVATE_SLOT, PRECHARGE_SLOT); - localparam[3:0] ACTIVATE_TO_WRITE_DELAY = find_delay(ns_to_nCK(tRCD), ACTIVATE_SLOT, WRITE_SLOT); //3 - localparam[3:0] ACTIVATE_TO_READ_DELAY = find_delay(ns_to_nCK(tRCD), ACTIVATE_SLOT, READ_SLOT); //2 - localparam[3:0] READ_TO_WRITE_DELAY = find_delay((CL_nCK + tCCD + 2 - CWL_nCK), READ_SLOT, WRITE_SLOT); //2 - localparam[3:0] READ_TO_READ_DELAY = 0; - localparam[3:0] READ_TO_PRECHARGE_DELAY = find_delay(ns_to_nCK(tRTP), READ_SLOT, PRECHARGE_SLOT); //1 - localparam[3:0] WRITE_TO_WRITE_DELAY = 0; - localparam[3:0] WRITE_TO_READ_DELAY = find_delay((CWL_nCK + 4 + ns_to_nCK(tWTR)), WRITE_SLOT, READ_SLOT); //4 - localparam[3:0] WRITE_TO_PRECHARGE_DELAY = find_delay((CWL_nCK + 4 + ns_to_nCK(tWR)), WRITE_SLOT, PRECHARGE_SLOT); //5 - /* verilator lint_on REALCVT */ - //MARGIN_BEFORE_ANTICIPATE is the number of columns before the column - //end when the anticipate can start - //the worst case scenario is when the anticipated bank needs to be precharged - //thus the margin must satisfy tRP (for precharge) and tRCD (for activate). - //Also, worscase is when the anticipated bank still has the leftover of the - //WRITE_TO_PRECHARGE_DELAY thus consider also this. - localparam MARGIN_BEFORE_ANTICIPATE = PRECHARGE_TO_ACTIVATE_DELAY + ACTIVATE_TO_WRITE_DELAY + WRITE_TO_PRECHARGE_DELAY; - localparam STAGE2_DATA_DEPTH = (CWL_nCK - (3 - WRITE_SLOT + 1))/4 + 1; //this is always >= 1 (5 - (3 - 3 + 1))/4.0 -> floor(1) + 1 = floor(4 - `ifdef FORMAL - wire stage2_data_depth; - assign stage2_data_depth = STAGE2_DATA_DEPTH; - always @* begin - assert(STAGE2_DATA_DEPTH-2 >= 0); - end - `endif - localparam READ_DELAY = $rtoi($floor((CL_nCK - (3 - READ_SLOT + 1))/4.0 )); - localparam READ_ACK_PIPE_WIDTH = READ_DELAY + 1 + 2 + 1 + 1; - localparam MAX_ADDED_READ_ACK_DELAY = 16; - /* verilator lint_off REALCVT */ - localparam DELAY_BEFORE_WRITE_LEVEL_FEEDBACK = STAGE2_DATA_DEPTH + ns_to_cycles(tWLO+tWLOE) + 10; //plus 10 controller clocks for possible bus latency and - /* verilator lint_on REALCVT */ //the delay for receiving feedback DQ from IOBUF -> IDELAY -> ISERDES - /*********************************************************************************************************************************************/ - - - /********************************************************** Read/Write Calibration Parameters **********************************************************/ - localparam IDLE = 0, - BITSLIP_DQS_TRAIN_1 = 1, - MPR_READ = 2, - COLLECT_DQS = 3, - ANALYZE_DQS = 4, - CALIBRATE_DQS = 5, - BITSLIP_DQS_TRAIN_2 = 6, - START_WRITE_LEVEL = 7, - WAIT_FOR_FEEDBACK = 8, - ISSUE_WRITE_1 = 9, - ISSUE_WRITE_2 = 10, - ISSUE_READ = 11, - READ_DATA = 12, - ANALYZE_DATA = 13, - DONE_CALIBRATE = 14; - localparam STORED_DQS_SIZE = 5, //must be >= 2 - REPEAT_DQS_ANALYZE = 1; // repeat DQS read to find the accurate starting position of DQS - - /*********************************************************************************************************************************************/ - - - /************************************************************* Set Mode Registers Parameters *************************************************************/ - // MR2 (JEDEC DDR3 doc pg. 30) - localparam[2:0] PASR = 3'b000; //Partial Array Self-Refresh: Full Array - localparam[2:0] CWL = 3'b000; //CAS write Latency: 8 (1.5 ns > tCK(avg) >= 1.25 ns) CREATE A FUNCTION FOR THIS - localparam[0:0] ASR = 1'b1; //Auto Self-Refresh: on - localparam[0:0] SRT = 1'b0; //Self-Refresh Temperature Range:0 (If ASR = 1, SRT bit must be set to 0) - localparam[1:0] RTT_WR = 2'b00; //Dynamic ODT: off - localparam[2:0] MR2_SEL = 3'b010; //Selected Mode Register - localparam[18:0] MR2 = {MR2_SEL, 5'b00000, RTT_WR, 1'b0, SRT, ASR, CWL, PASR}; - - // MR3 (JEDEC DDR3 doc pg. 32) - localparam[1:0] MPR_LOC = 2'b00; //Data location for MPR Reads: Predefined Pattern 0_1_0_1_0_1_0_1 - localparam[0:0] MPR_EN = 1'b1; //MPR Enable: Enable MPR reads and calibration during initialization - localparam[0:0] MPR_DIS = 1'b0; //MPR Enable: Enable MPR reads and calibration during initialization - localparam[2:0] MR3_SEL = 3'b011; //MPR Selected - localparam[18:0] MR3_MPR_EN = {MR3_SEL, 13'b0_0000_0000_0000, MPR_EN, MPR_LOC}; - localparam[18:0] MR3_MPR_DIS = {MR3_SEL, 13'b0_0000_0000_0000, MPR_DIS, MPR_LOC}; - localparam[ROW_BITS+BA_BITS-1:0] MR3_RD_ADDR = 0; - - // MR1 (JEDEC DDR3 doc pg. 27) - localparam DLL_EN = 1'b0; //DLL Enable/Disable: Enabled(0) - localparam[1:0] DIC = 2'b00; //Output Driver Impedance Control (IS THIS THE SAME WITH RTT_NOM???????????? Search later) - localparam[2:0] RTT_NOM = 3'b011; //RTT Nominal: 40ohms (RQZ/6) is the impedance of the PCB trace - localparam[0:0] WL_EN = 1'b1; //Write Leveling Enable: Disabled - localparam[0:0] WL_DIS = 1'b0; //Write Leveling Enable: Disabled - localparam[1:0] AL = 2'b00; //Additive Latency: Disabled - localparam[0:0] TDQS = 1'b1; //Termination Data Strobe: Disabled (provides additional termination resistance outputs. - //When the TDQS function is disabled, the DM function is provided (vice-versa).TDQS function is only - //available for X8 DRAM and must be disabled for X4 and X16. - localparam[0:0] QOFF = 1'b0; //Output Buffer Control: Enabled - localparam[2:0] MR1_SEL = 3'b001; //Selected Mode Register - localparam[18:0] MR1_WL_EN = {MR1_SEL, 3'b000, QOFF, TDQS, 1'b0, RTT_NOM[2], 1'b0, WL_EN, RTT_NOM[1], DIC[1], AL, RTT_NOM[0], DIC[0], DLL_EN}; - localparam[18:0] MR1_WL_DIS = {MR1_SEL, 3'b000, QOFF, TDQS, 1'b0, RTT_NOM[2], 1'b0, WL_DIS, RTT_NOM[1], DIC[1], AL, RTT_NOM[0], DIC[0], DLL_EN}; - - //MR0 (JEDEC DDR3 doc pg. 24) - localparam[1:0] BL = 2'b00; //Burst Length: 8 (Fixed) - localparam[3:0] CL = 4'b0100; //CAS Read Latency: 10, can support DDR-1600 speedbin 8-8-8, 9-9-9, and 10-10-10 (Check JEDEC DDR doc pg. 162) CREATE A FUNCTION FOR THIS - localparam[0:0] RBT = 1'b0; //Read Burst Type: Nibble Sequential - localparam[0:0] DLL_RST = 1'b1; //DLL Reset: Yes (this is self-clearing and must be applied after DLL enable) - /* verilator lint_off REALCVT */ - localparam[2:0] WR = WRA_mode_register_value($ceil(tWR/DDR3_CLK_PERIOD)); //Write recovery for autoprecharge ( - /* verilator lint_on REALCVT */ - localparam[0:0] PPD = 1'b0; //DLL Control for Precharge PD: Slow exit (DLL off) - localparam[2:0] MR0_SEL = 3'b000; - localparam[18:0] MR0 = {MR0_SEL, 3'b000, PPD, WR, DLL_RST, 1'b0, CL[3:1], RBT, CL[0], BL}; - /*********************************************************************************************************************************************/ - localparam INITIAL_RESET_INSTRUCTION = {5'b01000 , CMD_NOP , { {(DELAY_SLOT_WIDTH-3){1'b0}} , 3'd5} }; - - /************************************************************* Registers and Wires *************************************************************/ - integer index; - reg[4:0] instruction_address = 0; //address for accessing rom instruction - reg[27:0] instruction = INITIAL_RESET_INSTRUCTION; //instruction retrieved from reset instruction rom - reg[ DELAY_COUNTER_WIDTH - 1:0] delay_counter = INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0]; //counter used for delays - reg delay_counter_is_zero = (INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0] == 0); //counter is now zero so retrieve next delay - reg reset_done = 0; //high if reset has already finished - reg pause_counter = 0; - wire issue_read_command; - wire issue_write_command; - reg[(1< `COVER_DELAY) delay_counter <= `COVER_DELAY; - else delay_counter <= instruction[DELAY_COUNTER_WIDTH - 1:0] ; //use delay from rom if that is smaller than the COVER_DELAY macro - `else - delay_counter <= instruction[DELAY_COUNTER_WIDTH - 1:0]; //retrieve delay value of current instruction, we count to zero thus minus 1 - `endif - end - - //else: decrement delay counter when current instruction needs delay - //don't decrement (has infinite time) when last bit of - //delay_counter is 1 (for r/w calibration and prestall delay) - //address will only move forward for these kinds of delay only - //when skip_reset_seq_delay is toggled - else if(instruction[USE_TIMER] /*&& delay_counter != {(DELAY_COUNTER_WIDTH){1'b1}}*/ && !pause_counter) delay_counter <= delay_counter - 1; - - //delay_counter of 1 means we will need to update the delay_counter next clock cycle (delay_counter of zero) so we need to retrieve - //now the next instruction. The same thing needs to be done when current instruction does not need the timer delay. - if(delay_counter == 1 || !instruction[USE_TIMER]/* || skip_reset_seq_delay*/) begin - delay_counter_is_zero <= 1; - instruction <= read_rom_instruction(instruction_address); - instruction_address <= (instruction_address == 5'd22)? 5'd19:instruction_address+1; //wrap back of address to repeat refresh sequence - end - //we are now on the middle of a delay - else delay_counter_is_zero <=0; - //instruction[RST_DONE] is non-persistent thus we need to register it once it goes high - reset_done <= instruction[RST_DONE]? 1'b1:reset_done; - end - end - /*********************************************************************************************************************************************/ - - - /******************************************************* Track Bank Status and Issue Command *******************************************************/ - //process request transaction - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n ) begin - o_wb_stall <= 1'b1; - o_wb_stall_q <= 1'b1; - //set stage 1 to 0 - stage1_pending <= 0; - stage1_we <= 0; - stage1_col <= 0; - stage1_bank <= 0; - stage1_row <= 0; - stage1_next_bank <= 0; - stage1_next_row <= 0; - stage1_next_col <= 0; - stage1_data <= 0; - //set stage2 to 0 - stage2_pending <= 0; - stage2_we <= 0; - stage2_col <= 0; - stage2_bank <= 0; - stage2_row <= 0; - cmd_odt_q <= 0; - stage2_data_unaligned <= 0; - stage2_dm_unaligned <= 0; - for(index=0; index shiftreg(CWL) -> OSERDES(DDR) -> ODELAY -> RAM - end - - // when not in refresh, transaction can only be processed when i_wb_cyc is high and not stall - if(i_wb_cyc && !o_wb_stall) begin - //stage1 will not do the request (pending low) when the - //request is on the same bank as the current request. This - //will ensure stage1 bank will be different from stage2 bank - stage1_pending <= i_wb_stb;//actual request flag - stage1_aux <= i_aux; //aux ID for AXI compatibility - stage1_we <= i_wb_we; //write-enable - stage1_dm <= i_wb_sel; //byte selection - stage1_col <= { i_wb_addr[(COL_BITS- $clog2(serdes_ratio*2)-1):0], {{$clog2(serdes_ratio*2)}{1'b0}} }; //column address (n-burst word-aligned) - stage1_bank <= i_wb_addr[(BA_BITS + COL_BITS- $clog2(serdes_ratio*2) - 1) : (COL_BITS- $clog2(serdes_ratio*2))]; //bank_address - stage1_row <= i_wb_addr[ (ROW_BITS + BA_BITS + COL_BITS- $clog2(serdes_ratio*2) - 1) : (BA_BITS + COL_BITS- $clog2(serdes_ratio*2)) ]; //row_address - //stage1_next_bank will not increment unless stage1_next_col - //overwraps due to MARGIN_BEFORE_ANTICIPATE. Thus, anticipated - //precharge and activate will happen only at the end of the - //current column with a margin dictated by - //MARGIN_BEFORE_ANTICIPATE - /* verilator lint_off WIDTH */ - {stage1_next_row , stage1_next_bank, stage1_next_col[COL_BITS-1:$clog2(serdes_ratio*2)] } <= i_wb_addr + MARGIN_BEFORE_ANTICIPATE; //anticipated next row and bank to be accessed - /* verilator lint_on WIDTH */ - stage1_data <= i_wb_data; - end - else if(state_calibrate != DONE_CALIBRATE) begin - stage1_pending <= write_calib_stb;//actual request flag - stage1_we <= write_calib_we; //write-enable - stage1_dm <= 0; - stage1_aux <= write_calib_aux; //aux ID for AXI compatibility - stage1_col <= write_calib_col; //column address (n-burst word-aligned) - stage1_bank <= 0; //bank_address - stage1_row <= 0; //row_address - {stage1_next_row , stage1_next_bank, stage1_next_col[COL_BITS-1:$clog2(serdes_ratio*2)] } <= 0; //anticipated next row and bank to be accessed - stage1_data <= write_calib_data; - end - - for(index = 0; index < LANES; index = index + 1) begin - /* verilator lint_off WIDTH */ - {unaligned_data[index], { - stage2_data[0][((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*6 + 8*index) +: 8], - stage2_data[0][((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*4 + 8*index) +: 8], - stage2_data[0][((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*2 + 8*index) +: 8], - stage2_data[0][((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data[0][((DQ_BITS*LANES)*0 + 8*index) +: 8] }} - <= ( { stage2_data_unaligned[((DQ_BITS*LANES)*7 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*6 + 8*index) +: 8], - stage2_data_unaligned[((DQ_BITS*LANES)*5 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*4 + 8*index) +: 8], - stage2_data_unaligned[((DQ_BITS*LANES)*3 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*2 + 8*index) +: 8], - stage2_data_unaligned[((DQ_BITS*LANES)*1 + 8*index) +: 8], stage2_data_unaligned[((DQ_BITS*LANES)*0 + 8*index) +: 8] } - << data_start_index[index]) | unaligned_data[index]; - - {unaligned_dm[index], { - stage2_dm[0][LANES*7 + index], stage2_dm[0][LANES*6 + index], - stage2_dm[0][LANES*5 + index], stage2_dm[0][LANES*4 + index], - stage2_dm[0][LANES*3 + index], stage2_dm[0][LANES*2 + index], - stage2_dm[0][LANES*1 + index], stage2_dm[0][LANES*0 + index] }} - <= ( { stage2_dm_unaligned[LANES*7 + index], stage2_dm_unaligned[LANES*6 + index], - stage2_dm_unaligned[LANES*5 + index], stage2_dm_unaligned[LANES*4 + index], - stage2_dm_unaligned[LANES*3 + index], stage2_dm_unaligned[LANES*2 + index], - stage2_dm_unaligned[LANES*1 + index], stage2_dm_unaligned[LANES*0 + index] } - << (data_start_index[index]>>3)) | unaligned_dm[index]; - /* verilator lint_on WIDTH */ - end - for(index = 0; index < STAGE2_DATA_DEPTH-1; index = index+1) begin - stage2_data[index+1] <= stage2_data[index]; - stage2_dm[index+1] <= stage2_dm[index]; - end - - //abort any outgoing ack when cyc is low - if(!i_wb_cyc && state_calibrate == DONE_CALIBRATE) begin - stage2_pending <= 0; - stage1_pending <= 0; - end - end - end - assign o_phy_data = stage2_data[STAGE2_DATA_DEPTH-1]; - assign o_phy_dm = stage2_dm[STAGE2_DATA_DEPTH-1]; - // DIAGRAM FOR ALL RELEVANT TIMING PARAMETERS: - // - // tRTP - // ------------------------------------------------------------- - // | tCCD | - // | -----> Read ---------> Read - // v | ^ | - // Precharge ------> Activate -------->| | tWTR | tRTW - // ^ tRP tRCD | | v - // | ------> Write -------> Write - // | tCCD | - // ------------------------------------------------------------- - // tWR (after data burst) - //note: all delays after write counts only after the data burst (except for write-to-write tCCD) - // - //Pipeline Stages: - // wishbone inputs --> stage1 --> stage2 --> cmd - reg stage2_update = 1; - reg stage2_stall = 0; - reg stage1_stall = 0; - (*keep*) reg stage1_issue_command = 0; - (*keep*) reg stage2_issue_command = 0; - always @* begin - stage1_issue_command = 0; - stage2_issue_command = 0; - cmd_odt = cmd_odt_q || write_calib_odt; - cmd_ck_en = instruction[CLOCK_EN]; - cmd_reset_n = instruction[RESET_N]; - stage1_stall = 1'b0; - stage2_stall = 1'b0; - stage2_update = 1'b1; //always update stage 2 UNLESS it has a pending request (stage2_pending high) - o_wb_stall_d = 1'b0; //wb_stall going high is determined on stage 1 (higher priority), wb_stall going low is determined at stage2 (lower priority) - precharge_slot_busy = 0; //flag that determines if stage 2 is issuing precharge (thus stage 1 cannot issue precharge) - activate_slot_busy = 0; //flag that determines if stage 2 is issuing activate (thus stage 1 cannot issue activate) - write_dqs_d = write_calib_dqs; - write_dq_d = write_calib_dq; - for(index=0; index < (1<> 1); - end - if(shift_reg_read_pipe_q[1][0]) begin //delay is over and data is now starting to release from iserdes BUT NOT YET ALIGNED - index_read_pipe <= !index_read_pipe; //control which delay_read_pipe would get updated (we have 3 pipe to store read data)ss - delay_read_pipe[index_read_pipe][added_read_pipe_max] <= 1'b1; //update delay_read_pipe - end - for(index = 0; index < LANES; index = index + 1) begin - if(delay_read_pipe[0][{3'd0, added_read_pipe_max != added_read_pipe[index]}]) begin //same lane - o_wb_data_q[0][((DQ_BITS*LANES)*0 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*0 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*1 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*1 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*2 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*2 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*3 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*3 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*4 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*4 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*5 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*5 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*6 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*6 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[0][((DQ_BITS*LANES)*7 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*7 + 8*index) +: 8]; //update each lane of the burst - end - if(delay_read_pipe[1][{3'd0, added_read_pipe_max != added_read_pipe[index]}]) begin - o_wb_data_q[1][((DQ_BITS*LANES)*0 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*0 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*1 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*1 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*2 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*2 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*3 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*3 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*4 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*4 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*5 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*5 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*6 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*6 + 8*index) +: 8]; //update each lane of the burst - o_wb_data_q[1][((DQ_BITS*LANES)*7 + 8*index) +: 8] <= i_phy_iserdes_data[((DQ_BITS*LANES)*7 + 8*index) +: 8]; //update each lane of the burst - end - end - if(o_wb_ack_read_q[0][0]) begin - index_wb_data <= !index_wb_data; - end - for(index = 1; index < MAX_ADDED_READ_ACK_DELAY; index = index + 1) begin - o_wb_ack_read_q[index-1] <= o_wb_ack_read_q[index]; - end - o_wb_ack_read_q[MAX_ADDED_READ_ACK_DELAY-1] <= 0; - o_wb_ack_read_q[added_read_pipe_max] <= shift_reg_read_pipe_q[0]; - - //abort any outgoing ack when cyc is low - if(!i_wb_cyc && state_calibrate == DONE_CALIBRATE) begin - for(index = 0; index < MAX_ADDED_READ_ACK_DELAY; index = index + 1) begin - o_wb_ack_read_q[index] <= 0; - end - for(index = 0; index < READ_ACK_PIPE_WIDTH; index = index + 1) begin - shift_reg_read_pipe_q[index] <= 0; - end - end - end - end - assign o_wb_ack = o_wb_ack_read_q[0][0] && state_calibrate == DONE_CALIBRATE; - //o_wb_ack_read_q[0][0] is needed internally for write calibration but it must not go outside (since it is not an actual user wb request unless we are in DONE_CALIBRATE) - assign o_aux = o_wb_ack_read_q[0][AUX_WIDTH:1]; - assign o_wb_data = o_wb_data_q[index_wb_data]; - assign o_phy_dqs_tri_control = !write_dqs[STAGE2_DATA_DEPTH]; - assign o_phy_dq_tri_control = !write_dq[STAGE2_DATA_DEPTH+1]; - generate - if(STAGE2_DATA_DEPTH - 2 >= 0) - assign o_phy_toggle_dqs = write_dqs_val[STAGE2_DATA_DEPTH-2]; - else - assign o_phy_toggle_dqs = write_dqs_d || write_dqs_q[0]; - endgenerate - /*********************************************************************************************************************************************/ - - - /******************************************************* Read/Write Calibration Sequence *******************************************************/ - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - state_calibrate <= IDLE; - train_delay <= 0; - dqs_store <= 0; - dqs_count_repeat <= 0; - dqs_start_index <= 0; - dqs_target_index <= 0; - dqs_target_index_orig <= 0; - o_phy_bitslip <= 0; - initial_dqs <= 1; - lane <= 0; - dqs_bitslip_arrangement <= 0; - write_calib_dqs <= 0; - write_calib_dq <= 0; - write_calib_odt <= 0; - prev_write_level_feedback <= 1; - write_calib_stb <= 0;//actual request flag - write_calib_aux <= 0; //AUX ID - write_calib_we <= 0; //write-enable - write_calib_col <= 0; - write_calib_data <= 0; - pause_counter <= 0; - read_data_store <= 0; - write_pattern <= 0; - added_read_pipe_max <= 0; - dqs_start_index_stored <= 0; - dqs_start_index_repeat <= 0; - delay_before_write_level_feedback <= 0; - delay_before_read_data <= 0; - for(index = 0; index < LANES; index = index + 1) begin - added_read_pipe[index] <= 0; - data_start_index[index] <= 0; - odelay_data_cntvaluein[index] <= DATA_INITIAL_ODELAY_TAP[4:0]; - odelay_dqs_cntvaluein[index] <= DQS_INITIAL_ODELAY_TAP[4:0]; - idelay_data_cntvaluein[index] <= DATA_INITIAL_IDELAY_TAP[4:0]; - idelay_dqs_cntvaluein[index] <= DQS_INITIAL_IDELAY_TAP[4:0]; - end - end - else begin - write_calib_stb <= 0;//actual request flag - write_calib_aux <= 0; //AUX ID - write_calib_we <= 0; //write-enable - write_calib_col <= 0; - write_calib_data <= 0; - write_calib_dqs <= 0; - write_calib_dq <= 0; - train_delay <= (train_delay==0)? 0:(train_delay - 1); - delay_before_read_data <= (delay_before_read_data == 0)? 0: delay_before_read_data - 1; - delay_before_write_level_feedback <= (delay_before_write_level_feedback == 0)? 0: delay_before_write_level_feedback - 1; - o_phy_bitslip <= 0; - o_phy_odelay_data_ld <= 0; - o_phy_odelay_dqs_ld <= 0; - o_phy_idelay_data_ld <= 0; - o_phy_idelay_dqs_ld <= 0; - idelay_data_cntvaluein_prev <= idelay_data_cntvaluein[lane]; - - if(wb2_update) begin - odelay_data_cntvaluein[wb2_write_lane] <= wb2_phy_odelay_data_ld[wb2_write_lane]? wb2_phy_odelay_data_cntvaluein : odelay_data_cntvaluein[wb2_write_lane]; - odelay_dqs_cntvaluein[wb2_write_lane] <= wb2_phy_odelay_dqs_ld[wb2_write_lane]? wb2_phy_odelay_dqs_cntvaluein : odelay_dqs_cntvaluein[wb2_write_lane]; - idelay_data_cntvaluein[wb2_write_lane] <= wb2_phy_idelay_data_ld[wb2_write_lane]? wb2_phy_idelay_data_cntvaluein : idelay_data_cntvaluein[wb2_write_lane]; - idelay_dqs_cntvaluein[wb2_write_lane] <= wb2_phy_idelay_dqs_ld[wb2_write_lane]? wb2_phy_idelay_dqs_cntvaluein : idelay_dqs_cntvaluein[wb2_write_lane]; - o_phy_odelay_data_ld <= wb2_phy_odelay_data_ld; - o_phy_odelay_dqs_ld <= wb2_phy_odelay_dqs_ld; - o_phy_idelay_data_ld <= wb2_phy_idelay_data_ld; - o_phy_idelay_dqs_ld <= wb2_phy_idelay_dqs_ld; - lane <= wb2_write_lane; - end - else if(state_calibrate != DONE_CALIBRATE) begin - // increase cntvalue every load to prepare for possible next load - odelay_data_cntvaluein[lane] <= o_phy_odelay_data_ld[lane]? odelay_data_cntvaluein[lane] + 1: odelay_data_cntvaluein[lane]; - odelay_dqs_cntvaluein[lane] <= o_phy_odelay_dqs_ld[lane]? odelay_dqs_cntvaluein[lane] + 1: odelay_dqs_cntvaluein[lane]; - idelay_data_cntvaluein[lane] <= o_phy_idelay_data_ld[lane]? idelay_data_cntvaluein[lane] + 1: idelay_data_cntvaluein[lane]; - idelay_dqs_cntvaluein[lane] <= o_phy_idelay_dqs_ld[lane]? idelay_dqs_cntvaluein[lane] + 1: idelay_dqs_cntvaluein[lane]; - end - if(initial_dqs) begin - dqs_target_index <= dqs_target_index_value; - dq_target_index <= dqs_target_index_value; - dqs_target_index_orig <= dqs_target_index_value; - end - if(idelay_dqs_cntvaluein[lane] == 0) begin //go back to previous odd - dqs_target_index <= dqs_target_index_orig - 2; - end - if(idelay_data_cntvaluein[lane] == 0 && idelay_data_cntvaluein_prev == 31) begin - dq_target_index <= dqs_target_index_orig - 2; - end - - // FSM - case(state_calibrate) - IDLE: if(i_phy_idelayctrl_rdy && instruction_address == 13) begin //we are now inside instruction 15 with maximum delay - state_calibrate <= BITSLIP_DQS_TRAIN_1; - lane <= 0; - o_phy_odelay_data_ld <= {LANES{1'b1}}; - o_phy_odelay_dqs_ld <= {LANES{1'b1}}; - o_phy_idelay_data_ld <= {LANES{1'b1}}; - o_phy_idelay_dqs_ld <= {LANES{1'b1}}; - pause_counter <= 1; //pause instruction address @13 until read calibration finishes - end - else if(instruction_address == 13) begin - pause_counter <= 1; //pause instruction address @13 until read calibration finishes - end - BITSLIP_DQS_TRAIN_1: if(train_delay == 0) begin - /* Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip must be - deasserted for at least one CLKDIV cycle between two Bitslip assertions.The user - logic should wait for at least two CLKDIV cycles in SDR mode or three CLKDIV cycles - in DDR mode, before analyzing the received data pattern and potentially issuing - another Bitslip command. If the ISERDESE2 is reset, the Bitslip logic is also reset - and returns back to its initial state. - */ - if(i_phy_iserdes_bitslip_reference[lane*LANES +: 8] == 8'b0111_1000) begin //initial arrangement - state_calibrate <= MPR_READ; - initial_dqs <= 1; - dqs_start_index_repeat <= 0; - dqs_start_index_stored <= 0; - end - else begin - o_phy_bitslip[lane] <= 1; - train_delay <= 3; - end - end - - MPR_READ: begin //align the incoming DQS during reads to the controller clock - //issue_read_command = 1; - /* verilator lint_off WIDTH */ - delay_before_read_data <= READ_DELAY + 1 + 2 + 1; ///1=issue command delay (OSERDES delay), 2 = ISERDES delay - /* verilator lint_on WIDTH */ - state_calibrate <= COLLECT_DQS; - dqs_count_repeat <= 0; - end - - COLLECT_DQS: if(delay_before_read_data == 0) begin - dqs_store <= {i_phy_iserdes_dqs[LANES*lane +: 8], dqs_store[(STORED_DQS_SIZE*8-1):8]}; - dqs_count_repeat <= dqs_count_repeat + 1; - if(dqs_count_repeat == STORED_DQS_SIZE - 1) begin - state_calibrate <= ANALYZE_DQS; - dqs_start_index_stored <= dqs_start_index; - dqs_start_index <= 0; - end - end - - ANALYZE_DQS: if(dqs_store[dqs_start_index +: 10] == 10'b01_01_01_01_00) begin - dqs_start_index_repeat <= (dqs_start_index == dqs_start_index_stored)? dqs_start_index_repeat + 1: 0; //increase dqs_start_index_repeat when index is the same as before - if(dqs_start_index_repeat == REPEAT_DQS_ANALYZE) begin //the same index appeared REPEAT_DQS_ANALYZE times in a row, thus can proceed to CALIBRATE_DQS - initial_dqs <= 0; - dqs_start_index_repeat <= 0; - - state_calibrate <= CALIBRATE_DQS; - end - else begin - state_calibrate <= MPR_READ; - end - end - else begin - dqs_start_index <= dqs_start_index + 1; - end - - CALIBRATE_DQS: if(dqs_start_index_stored == dqs_target_index) begin - added_read_pipe[lane] <= dq_target_index[$clog2(STORED_DQS_SIZE*8)-1:3] + { {($clog2(STORED_DQS_SIZE*8)-3){1'b0}} , (dq_target_index[2:0] >= 5)}; - dqs_bitslip_arrangement <= 16'b0011_1100_0011_1100 >> dq_target_index[2:0]; - state_calibrate <= BITSLIP_DQS_TRAIN_2; - end - else begin - o_phy_idelay_data_ld[lane] <= 1; - o_phy_idelay_dqs_ld[lane] <= 1; - state_calibrate <= MPR_READ; - end - - BITSLIP_DQS_TRAIN_2: if(train_delay == 0) begin //train again the ISERDES to capture the DQ correctly - if(i_phy_iserdes_bitslip_reference[lane*LANES +: 8] == dqs_bitslip_arrangement[7:0]) begin - /* verilator lint_off WIDTH */ - if(lane == LANES - 1) begin - /* verilator lint_on WIDTH */ - pause_counter <= 0; //read calibration now complete so continue the reset instruction sequence - lane <= 0; - prev_write_level_feedback <= 1'b1; - state_calibrate <= START_WRITE_LEVEL; - end - else begin - lane <= lane + 1; - state_calibrate <= BITSLIP_DQS_TRAIN_1; - end - added_read_pipe_max <= added_read_pipe_max > added_read_pipe[lane]? added_read_pipe_max:added_read_pipe[lane]; - end - else begin - o_phy_bitslip[lane] <= 1; - train_delay <= 3; - end - end - - START_WRITE_LEVEL: if(instruction_address == 17) begin - write_calib_dqs <= 1'b1; - write_calib_odt <= 1'b1; - delay_before_write_level_feedback <= DELAY_BEFORE_WRITE_LEVEL_FEEDBACK[$clog2(DELAY_BEFORE_WRITE_LEVEL_FEEDBACK):0]; - state_calibrate <= WAIT_FOR_FEEDBACK; - pause_counter <= 1; // pause instruction address @17 until write calibration finishes - end - - WAIT_FOR_FEEDBACK: if(delay_before_write_level_feedback == 0) begin - /* verilator lint_off WIDTH */ //_verilator warning: Bit extraction of var[511:0] requires 9 bit index, not 3 bits (but [lane<<3] is much simpler and cleaner) - prev_write_level_feedback <= i_phy_iserdes_data[lane<<3]; - if({prev_write_level_feedback, i_phy_iserdes_data[lane<<3]} == 2'b01) begin - /* verilator lint_on WIDTH */ - /* verilator lint_off WIDTH */ - if(lane == LANES - 1) begin - /* verilator lint_on WIDTH */ - write_calib_odt <= 0; - pause_counter <= 0; //write calibration now complete so continue the reset instruction sequence - lane <= 0; - state_calibrate <= ISSUE_WRITE_1; - end - else begin - lane <= lane + 1; - prev_write_level_feedback <= 1'b1; - state_calibrate <= START_WRITE_LEVEL; - end - end - else begin - o_phy_odelay_data_ld[lane] <= 1; - o_phy_odelay_dqs_ld[lane] <= 1; - state_calibrate <= START_WRITE_LEVEL; - end - end - ISSUE_WRITE_1: if(instruction_address == 22 && !o_wb_stall_q) begin - write_calib_stb <= 1;//actual request flag - write_calib_aux <= 1; //AUX ID to determine later if ACK is for read or write - write_calib_we <= 1; //write-enable - write_calib_col <= 0; - write_calib_data <= { {LANES{8'h91}}, {LANES{8'h77}}, {LANES{8'h29}}, {LANES{8'h8c}}, {LANES{8'hd0}}, {LANES{8'had}}, {LANES{8'h51}}, {LANES{8'hc1}} }; - state_calibrate <= ISSUE_WRITE_2; - end - ISSUE_WRITE_2: begin - write_calib_stb <= 1;//actual request flag - write_calib_aux <= 1; //AUX ID to determine later if ACK is for read or write - write_calib_we <= 1; //write-enable - write_calib_col <= 8; - write_calib_data <= { {LANES{8'h80}}, {LANES{8'hdb}}, {LANES{8'hcf}}, {LANES{8'hd2}}, {LANES{8'h75}}, {LANES{8'hf1}}, {LANES{8'h2c}}, {LANES{8'h3d}} }; - state_calibrate <= ISSUE_READ; - end - ISSUE_READ: if(!o_wb_stall_q && write_calib_stb == 0) begin - write_calib_stb <= 1;//actual request flag - write_calib_aux <= 0; //AUX ID to determine later if ACK is for read or write - write_calib_we <= 0; //write-enable - state_calibrate <= READ_DATA; - end - - READ_DATA: if(o_wb_ack_read_q[0] == {{(AUX_WIDTH){1'b0}}, 1'b1}) begin //wait for the read ack (which has UAX ID of 0} - read_data_store <= o_wb_data; - state_calibrate <= ANALYZE_DATA; - data_start_index[lane] <= 0; - // Possible Patterns (strong autocorrel stat) - //0x80dbcfd275f12c3d - //0x9177298cd0ad51c1 - //0x01b79fa4ebe2587b - //0x22ee5319a15aa382 - write_pattern <= 128'h80dbcfd275f12c3d_9177298cd0ad51c1; - end - - //ANALYZE_DATA: if(write_pattern[data_start_index[lane] +: 64] == read_data_store[lane*DQ_BITS*8 +: DQ_BITS*8]) begin - ANALYZE_DATA: if(write_pattern[data_start_index[lane] +: 64] == {read_data_store[((DQ_BITS*LANES)*7 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*6 + 8*lane) +: 8], - read_data_store[((DQ_BITS*LANES)*5 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*4 + 8*lane) +: 8], read_data_store[((DQ_BITS*LANES)*3 + 8*lane) +: 8], - read_data_store[((DQ_BITS*LANES)*2 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*1 + 8*lane) +: 8],read_data_store[((DQ_BITS*LANES)*0 + 8*lane) +: 8] }) begin - /* verilator lint_off WIDTH */ - if(lane == LANES - 1) begin - /* verilator lint_on WIDTH */ - state_calibrate <= DONE_CALIBRATE; - end - else begin - lane <= lane + 1; - data_start_index[lane+1] <= 0; - end - end - else begin - data_start_index[lane] <= data_start_index[lane] + 8; - end - DONE_CALIBRATE: begin - state_calibrate <= DONE_CALIBRATE; - if(instruction_address == 19) begin //pre-stall delay to finish all remaining requests - pause_counter <= 1; // pause instruction address until pre-stall delay before refresh sequence finishes - //skip to instruction address 20 (precharge all before refresh) when no pending requests anymore - //toggle it for 1 clk cycle only - if(!stage1_pending && !stage2_pending && o_wb_stall) begin - pause_counter <= 0; // pre-stall delay done since all remaining requests are completed - end - end - end - - endcase - `ifdef FORMAL_COVER - state_calibrate <= DONE_CALIBRATE; - `endif - end - end - assign issue_read_command = (state_calibrate == MPR_READ); - assign issue_write_command = 0; - assign o_phy_odelay_data_cntvaluein = odelay_data_cntvaluein[lane]; - assign o_phy_odelay_dqs_cntvaluein = odelay_dqs_cntvaluein[lane]; - assign o_phy_idelay_data_cntvaluein = idelay_data_cntvaluein[lane]; - assign o_phy_idelay_dqs_cntvaluein = idelay_dqs_cntvaluein[lane]; - assign dqs_target_index_value = dqs_start_index_stored[0]? dqs_start_index_stored + 2: dqs_start_index_stored + 1; - - /*********************************************************************************************************************************************/ - - - /******************************************************* Wishbone 2 (PHY) Interface *******************************************************/ - - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - wb2_stb <= 0; - end - else begin - if(i_wb2_cyc && !o_wb2_stall) begin - wb2_stb <= i_wb2_stb; - wb2_we <= i_wb2_we; //data to be written which must have high i_wb2_sel are: {LANE_NUMBER, CNTVALUEIN} - wb2_addr <= i_wb2_addr; - wb2_data <= i_wb2_data; - wb2_sel <= i_wb2_sel; - end - else if(!o_wb2_stall) begin - wb2_stb <= 0; - wb2_we <= 0; - wb2_addr <= 0; - wb2_data <= 0; - wb2_sel <= 0; - end - end - end - - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - wb2_phy_odelay_data_cntvaluein <= 0; - wb2_phy_odelay_data_ld <= 0; - wb2_phy_odelay_dqs_cntvaluein <= 0; - wb2_phy_odelay_dqs_ld <= 0; - wb2_phy_idelay_data_cntvaluein <= 0; - wb2_phy_idelay_data_ld <= 0; - wb2_phy_idelay_dqs_cntvaluein <= 0; - wb2_phy_idelay_dqs_ld <= 0; - wb2_update <= 0; - wb2_write_lane <= 0; - o_wb2_ack <= 0; - o_wb2_stall <= 1; - end - else begin - wb2_phy_odelay_data_ld <= 0; - wb2_phy_odelay_dqs_ld <= 0; - wb2_phy_idelay_data_ld <= 0; - wb2_phy_idelay_dqs_ld <= 0; - wb2_update <= 0; - wb2_write_lane <= 0; - o_wb2_ack <= wb2_stb && i_wb2_cyc; //always ack right after request - o_wb2_stall <= state_calibrate != DONE_CALIBRATE; //low stall only after calibration - if(wb2_stb) begin - case(wb2_addr[3:0]) - //read/write odelay cntvalue for DQ line - 0: if(wb2_we) begin - wb2_phy_odelay_data_cntvaluein <= wb2_data[4:0]; //save first 5 bits as CNTVALUEIN for the ODELAYE2 for DQ - wb2_phy_odelay_data_ld <= 1 << (wb2_data[5 +: $clog2(LANES)]); //raise the lane to be loaded with new cntvaluein - wb2_update <= wb2_sel[$rtoi($ceil( ($clog2(LANES) + 5)/8 )) - 1:0]; //only update when sel bit is high (data is valid) - end - else begin - o_wb2_data <= { {(WB2_DATA_BITS-5){1'b0}} , odelay_data_cntvaluein[wb2_addr[4 +: $clog2(LANES)]] };//use next bits of address as lane number to be read - end - - //read/write odelay cntvalue for DQS line - 1: if(wb2_we) begin - wb2_phy_odelay_dqs_cntvaluein <= wb2_data[4:0]; //save first 5 bits as CNTVALUEIN for the ODELAYE2 for DQS - wb2_phy_odelay_dqs_ld <= 1 << (wb2_data[5 +: $clog2(LANES)]); //raise the lane to be loaded with new cntvaluein - wb2_update <= wb2_sel[$rtoi($ceil( ($clog2(LANES) + 5)/8 )) - 1:0]; //only update when sel bit is high (data is valid) - end - else begin - o_wb2_data <= { {(WB2_DATA_BITS-5){1'b0}} , odelay_dqs_cntvaluein[wb2_addr[4 +: $clog2(LANES)]] };//use next bits of address as lane number to be read - end - - //read/write idelay cntvalue for DQ line - 2: if(wb2_we) begin - wb2_phy_idelay_data_cntvaluein <= wb2_data[4:0]; //save first 5 bits as CNTVALUEIN for the IDELAYE2 for DQ - wb2_phy_idelay_data_ld <= 1 << (wb2_data[5 +: $clog2(LANES)]); //save next 5 bits for lane number to be loaded with new delay - wb2_update <= wb2_sel[$rtoi($ceil( ($clog2(LANES) + 5)/8 )) - 1:0]; //only update when sel bit is high (data is valid) - end - else begin - o_wb2_data <= { {(WB2_DATA_BITS-5){1'b0}} , idelay_data_cntvaluein[wb2_addr[4 +: $clog2(LANES)]] }; //use next bits of address as lane number to be read - end - - //read/write idelay cntvalue for DQS line - 3: if(wb2_we) begin - wb2_phy_idelay_dqs_cntvaluein <= wb2_data[4:0]; //save first 5 bits as CNTVALUEIN for the IDELAYE2 for DQS - wb2_phy_idelay_dqs_ld <= 1 << (wb2_data[5 +: $clog2(LANES)]); //save next 5 bits for lane number to be loaded with new delay - wb2_update <= wb2_sel[$rtoi($ceil( ($clog2(LANES) + 5)/8 )) - 1:0]; //only update when sel bit is high (data is valid) - end - else begin - o_wb2_data <= { {(WB2_DATA_BITS-5){1'b0}} , idelay_dqs_cntvaluein[wb2_addr[4 +: $clog2(LANES)]] }; //use next bits of address as lane number to be read - end - - default: if(!wb2_we) begin //read - o_wb2_data <= {(WB2_DATA_BITS/2){2'b10}}; //return alternating 1s and 0s when address to be read is invalid - end - endcase - - wb2_write_lane <= wb2_data[5 +: $clog2(LANES)]; //save next 5 bits for lane number to be loaded with new delay - end //end of if(wb2_stb) - end//end of else - end//end of always - - /*********************************************************************************************************************************************/ - - - /******************************************************* Functions *******************************************************/ - //`define SUPPORT_REAL - //convert nanoseconds time input to number of controller clock cycles (referenced to CONTROLLER_CLK_PERIOD) - //output is set at same length as a MRS command (19 bits) to maximize the time slot - function [DELAY_SLOT_WIDTH - 1:0] ns_to_cycles (`ifdef SUPPORT_REAL input real ns `else input integer ns `endif); - integer result; - begin - result = $rtoi($ceil(ns*1.0/CONTROLLER_CLK_PERIOD)); //Without $rtoi: YOSYS ERROR: Non-constant expression in constant function - ns_to_cycles = result[DELAY_SLOT_WIDTH - 1:0]; - end - endfunction - - //convert nCK input (number of DDR3 clock cycles) to number of controller clock cycles (referenced to serdes_ratio) - function [DELAY_SLOT_WIDTH - 1:0] nCK_to_cycles (`ifdef SUPPORT_REAL input real nCK `else input integer nCK `endif); - integer result; - begin - result = $rtoi($ceil(nCK*1.0/serdes_ratio)); - nCK_to_cycles = result[DELAY_SLOT_WIDTH - 1:0]; - end - endfunction - - - //convert nanoseconds time input to number of DDR clock cycles (referenced to DDR3_CLK_PERIOD) - function integer ns_to_nCK (`ifdef SUPPORT_REAL input real ns `else input integer ns `endif); - ns_to_nCK = $rtoi($ceil(ns*1.0/DDR3_CLK_PERIOD)); - endfunction - - //convert DDR clock cycles to nanoseconds (referenced to DDR3_CLK_PERIOD) - `ifdef SUPPORT_REAL - function real nCK_to_ns (input real nCK); - nCK_to_ns = $ceil(nCK*1.0*DDR3_CLK_PERIOD); - `else - function integer nCK_to_ns (input integer nCK); - nCK_to_ns = $rtoi($ceil(nCK*1.0*DDR3_CLK_PERIOD)); - `endif - endfunction - - // functions used to infer some localparam values - `ifdef SUPPORT_REAL - function real max(input real a, input real b); - `else - function integer max(input integer a, input integer b); - `endif - if(a >= b) max = a; - else max = b; - endfunction - - //Find the 3-bit value for the Mode Register 0 WR (Write recovery for auto-precharge) - function[2:0] WRA_mode_register_value(input integer WRA); - //WR_min (write recovery for autoprecharge) in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next integer. - //The WR value in the mode register must be programmed to be equal or larger than WRmin. - case(WRA+1) - 1,2,3,4,5: WRA_mode_register_value = 3'b001; - 6: WRA_mode_register_value = 3'b010; - 7: WRA_mode_register_value = 3'b011; - 8: WRA_mode_register_value = 3'b100; - 9,10: WRA_mode_register_value = 3'b101; - 11,12: WRA_mode_register_value = 3'b110; - 13,14: WRA_mode_register_value = 3'b111; - 15,16: WRA_mode_register_value = 3'b000; - default: begin - WRA_mode_register_value = 3'b000; //defaulting to largest write recovery cycles: 16 cycles - end - endcase - endfunction - - function[1:0] get_slot (input[3:0] cmd); //cmd can either be CMD_PRE,CMD_ACT, CMD_WR, CMD_RD - integer delay; - reg[1:0] slot_number, read_slot, write_slot, anticipate_activate_slot, anticipate_precharge_slot; - begin - // find read command slot number - delay = CL_nCK; - for(slot_number = 0 ; delay != 0 ; delay = delay - 1) begin - slot_number = slot_number - 1'b1; - end - read_slot = slot_number; - - // find write command slot number - delay = CWL_nCK; - for(slot_number = 0 ; delay != 0; delay = delay - 1) begin - slot_number = slot_number - 1'b1; - end - write_slot = slot_number; - - // find anticipate activate command slot number - if(CL_nCK > CWL_nCK) slot_number = read_slot; - else slot_number = write_slot; - `ifdef SUPPORT_REAL - delay = ns_to_nCK(tRCD); - `else - delay = ns_to_nCK($rtoi(tRCD)); - `endif - for(slot_number = slot_number; delay != 0; delay = delay - 1) begin - slot_number = slot_number - 1'b1; - end - anticipate_activate_slot = slot_number; - // if computed anticipate_activate_slot is same with either write_slot or read_slot, decrement slot number until - while(anticipate_activate_slot == write_slot || anticipate_activate_slot == read_slot) begin - anticipate_activate_slot = anticipate_activate_slot - 1'b1; - end - - //the remaining slot will be for precharge command - anticipate_precharge_slot = 0; - while(anticipate_precharge_slot == write_slot || anticipate_precharge_slot == read_slot || anticipate_precharge_slot == anticipate_activate_slot) begin - anticipate_precharge_slot = anticipate_precharge_slot - 1'b1; - end - case(cmd) - CMD_RD: get_slot = read_slot; - CMD_WR: get_slot = write_slot; - CMD_ACT: get_slot = anticipate_activate_slot; - CMD_PRE: get_slot = anticipate_precharge_slot; - default: begin - `ifdef FORMAL - assert(0); //force FORMAL to fail if this is ever reached - `endif - end - endcase - end - endfunction - - //find the delay to be used by delay_before_xxxx_counter. - // - delay_nCK = delay required between the two commands in DDR3 clock cycles - // - start_slot = slot number of the first command - // - end_slot = slot number of the second command - // returns the number of controller clock cycles to satisfy the delay required between the two commands - function [3:0] find_delay(input integer delay_nCK, input reg[1:0] start_slot, input reg[1:0] end_slot); - integer k; //error: variable declaration assignments are only allowed at the module level - begin - k = 0; - /* verilator lint_off WIDTH */ - while( ((4 - start_slot) + end_slot + 4*k) < delay_nCK) begin - /* verilator lint_on WIDTH */ - k = k + 1; - end - find_delay = k[3:0]; - end - endfunction - /*********************************************************************************************************************************************/ - - -`ifndef YOSYS - ///YOSYS: System task `$display' called with invalid/unsupported format specifier - initial begin - /* verilator lint_off REALCVT */ - $display("TEST FUNCTIONS\n-----------------------------\n"); - $display("Test ns_to_cycles() function:"); - $display("\tns_to_cycles(15) = %0d [exact]", ns_to_cycles(15) ); - $display("\tns_to_cycles(14.5) = %0d [round-off]", ns_to_cycles(14.5) ); - $display("\tns_to_cycles(11) = %0d [round-up]\n", ns_to_cycles(11) ); - - $display("Test nCK_to_cycles() function:"); - $display("\tns_to_cycles(16) = %0d [exact]", nCK_to_cycles(16) ); - $display("\tns_to_cycles(15) = %0d [round-off]", nCK_to_cycles(15) ); - $display("\tns_to_cycles(13) = %0d [round-up]\n", nCK_to_cycles(13) ); - - $display("Test ns_to_nCK() function:"); - $display("\tns_to_cycles(15) = %0d [exact]", ns_to_nCK(15) ); - $display("\tns_to_cycles(14.875) = %0d [round-off]", ns_to_nCK(14.875) ); - $display("\tns_to_cycles(13.875) = %0d [round-up] \n", ns_to_nCK(13.875) ); - - $display("Test nCK_to_ns() function:"); - $display("\tns_to_cycles(4) = %0d [exact]", nCK_to_ns(4) ); - $display("\tns_to_cycles(14.875) = %0d [round-off]", nCK_to_ns(3) ); - $display("\tns_to_cycles(13.875) = %0d [round-up]\n", nCK_to_ns(5) ); - - $display("Test nCK_to_ns() function:"); - $display("\tns_to_cycles(4) = %0d [exact]", nCK_to_ns(4) ); - $display("\tns_to_cycles(14.875) = %0d [round-off]", nCK_to_ns(3) ); - $display("\tns_to_cycles(13.875) = %0d [round-up]\n", nCK_to_ns(5) ); - - $display("Test $floor() function:"); - $display("\t$floor(5/2) = %0d", $floor(5/2) ); - $display("\t$floor(9/4) = %0d", $floor(9/4) ); - $display("\t$floor(9/4) = %0d", $floor(8/4) ); - $display("\t$floor(9/5) = %0d\n", $floor(9/5) ); - - $display("\nDISPLAY CONTROLLER PARAMETERS\n-----------------------------\n"); - $display("DELAY_COUNTER_WIDTH = %0d", DELAY_COUNTER_WIDTH); - $display("DELAY_SLOT_WIDTH = %0d", DELAY_SLOT_WIDTH); - - //$display("$bits(instruction):%0d - $bits(CMD_MRS):%0d - $bits(MR0):%0d = 5 = %0d", $bits(instruction), $bits(CMD_MRS) , $bits(MR0), ($bits(instruction) - $bits(CMD_MRS) - $bits(MR0))); - $display("serdes_ratio = %0d",serdes_ratio); - $display("wb_addr_bits = %0d",wb_addr_bits); - $display("wb_data_bits = %0d",wb_data_bits); - $display("wb_sel_bits = %0d\n\n",wb_sel_bits); - //$display("request_row_width = %0d = %0d", ROW_BITS, $bits(i_wb_addr[ (ROW_BITS + BA_BITS + COL_BITS- $clog2(serdes_ratio*2) - 1) : (BA_BITS + COL_BITS- $clog2(serdes_ratio*2)) ])); - //$display("request_col_width = %0d = %0d", COL_BITS, $bits({ i_wb_addr[(COL_BITS- $clog2(serdes_ratio*2)-1):0], {{$clog2(serdes_ratio*2)}{1'b0}} })); - //$display("request_bank_width = %0d = %0d", BA_BITS, $bits(i_wb_addr[(BA_BITS + COL_BITS- $clog2(serdes_ratio*2) - 1) : (COL_BITS- $clog2(serdes_ratio*2))])); - - $display("READ_SLOT = %0d", READ_SLOT); - $display("WRITE_SLOT = %0d", WRITE_SLOT); - $display("ACTIVATE_SLOT = %0d", ACTIVATE_SLOT); - $display("PRECHARGE_SLOT = %0d", PRECHARGE_SLOT); - - $display("\n\nDELAYS:"); - $display("\tns_to_nCK(tRCD): %0d", ns_to_nCK(tRCD)); - $display("\tns_to_nCK(tRP): %0d", ns_to_nCK(tRP)); - $display("\tns_to_nCK(tRTP): %0d", ns_to_nCK(tRTP)); - $display("\ttCCD: %0d", tCCD); - $display("\t(CL_nCK + tCCD + 2 - CWL_nCK): %0d", (CL_nCK + tCCD + 2 - CWL_nCK)); - $display("\t(CWL_nCK + 4 + ns_to_nCK(tWR)): %0d", (CWL_nCK + 4 + ns_to_nCK(tWR))); - $display("\t(CWL_nCK + 4 + ns_to_nCK(tWTR)): %0d", (CWL_nCK + 4 + ns_to_nCK(tWTR))); - - $display("\n\nPRECHARGE_TO_ACTIVATE_DELAY = %0d", PRECHARGE_TO_ACTIVATE_DELAY); - $display("ACTIVATE_TO_WRITE_DELAY = %0d", ACTIVATE_TO_WRITE_DELAY); - $display("ACTIVATE_TO_READ_DELAY = %0d", ACTIVATE_TO_READ_DELAY); - $display("READ_TO_WRITE_DELAY = %0d", READ_TO_WRITE_DELAY); - $display("READ_TO_READ_DELAY = %0d", READ_TO_READ_DELAY); - $display("READ_TO_PRECHARGE_DELAY = %0d", READ_TO_PRECHARGE_DELAY); - $display("WRITE_TO_WRITE_DELAY = %0d", WRITE_TO_WRITE_DELAY); - $display("WRITE_TO_READ_DELAY = %0d", WRITE_TO_READ_DELAY); - $display("WRITE_TO_PRECHARGE_DELAY = %0d", WRITE_TO_PRECHARGE_DELAY); - $display("STAGE2_DATA_DEPTH = %0d", STAGE2_DATA_DEPTH); - $display("READ_ACK_PIPE_WIDTH = %0d", READ_ACK_PIPE_WIDTH); - /* verilator lint_on REALCVT */ - end -`endif - - -`ifdef FORMAL - `define TEST_CONTROLLER_PIPELINE - - `ifdef FORMAL_COVER - initial assume(!i_rst_n); - reg[24:0] f_wb_inputs[31:0]; - reg[9:0] f_reset_counter = 0; - reg[4:0] f_index = 0; - reg f_past_valid = 0; - initial begin - /* - // Sequential read to row 0 then jump to row 2 - f_wb_inputs[0] = {1'b0, {14'd0,3'd1, 7'd0}}; //read - f_wb_inputs[1] = {1'b0, {14'd0,3'd1, 7'd1}}; //read on same bank (tCCD) - f_wb_inputs[2] = {1'b0, {14'd0,3'd1, 7'd2}}; //write on same bank (tRTW) - f_wb_inputs[3] = {1'b0, {14'd0,3'd1, 7'd3}}; //write on same bank (tCCD) - f_wb_inputs[4] = {1'b0, {14'd0,3'd1, 7'd4}}; //read on different bank - f_wb_inputs[5] = {1'b0, {14'd0,3'd1, 7'd5}}; //write on same bank (tRTW) - f_wb_inputs[6] = {1'b0, {14'd2,3'd1, 7'd6}}; //write on different bank (already activated) - f_wb_inputs[7] = {1'b0, {14'd2,3'd1, 7'd7}}; //write (tCCD) - f_wb_inputs[8] = {1'b0, {14'd2,3'd1, 7'd8}}; //write on different bank (already activated but wrong row) - f_wb_inputs[9] = {1'b0, {14'd2,3'd1, 7'd9}}; //write (tCCD) - f_wb_inputs[10] = {1'b0, {14'd3,3'd1, 7'd10}}; //write (tCCD) - f_wb_inputs[11] = {1'b0, {14'd3,3'd1, 7'd11}}; //read (same bank but wrong row so precharge first) - f_wb_inputs[12] = {1'b0, {14'd3,3'd1, 7'd12}}; //read (tCCD) - f_wb_inputs[13] = {1'b0, {14'd3,3'd1, 7'd13}}; //read (tCCD) - */ - - f_wb_inputs[0] = {1'b0, {14'd0,3'd1, 7'd0}}; //read - f_wb_inputs[1] = {1'b0, {14'd0,3'd1, 7'd1}}; //read on same bank (tCCD) - f_wb_inputs[2] = {1'b1, {14'd0,3'd1, 7'd2}}; //write on same bank (tRTW) - f_wb_inputs[3] = {1'b1, {14'd0,3'd1, 7'd3}}; //write on same bank (tCCD) - f_wb_inputs[4] = {1'b0, {14'd0,3'd2, 7'd0}}; //read on different bank - f_wb_inputs[5] = {1'b1, {14'd0,3'd2, 7'd1}}; //write on same bank (tRTW) - f_wb_inputs[6] = {1'b1, {14'd0,3'd1, 7'd4}}; //write on different bank (already activated) - f_wb_inputs[7] = {1'b1, {14'd0,3'd1, 7'd5}}; //write (tCCD) - f_wb_inputs[8] = {1'b1, {14'd1,3'd2, 7'd0}}; //write on different bank (already activated but wrong row) - f_wb_inputs[9] = {1'b1, {14'd1,3'd2, 7'd1}}; //write (tCCD) - f_wb_inputs[10] = {1'b1, {14'd1,3'd2, 7'd2}}; //write (tCCD) - f_wb_inputs[11] = {1'b0, {14'd2,3'd2, 7'd0}}; //read (same bank but wrong row so precharge first) - f_wb_inputs[12] = {1'b0, {14'd2,3'd2, 7'd1}}; //read (tCCD) - f_wb_inputs[13] = {1'b0, {14'd2,3'd2, 7'd2}}; //read (tCCD) - /* - f_wb_inputs[0] = {1'b0, {14'd0,3'd1, 7'd0}}; //read - f_wb_inputs[1] = {1'b0, {14'd0,3'd1, 7'd1}}; //read on same bank (tCCD) - f_wb_inputs[2] = {1'b1, {14'd0,3'd2, 7'd0}}; //write on the anticipated bank - f_wb_inputs[3] = {1'b1, {14'd0,3'd2, 7'd1}}; //write on same bank (tCCD) - f_wb_inputs[4] = {1'b0, {14'd0,3'd3, 7'd0}}; //read on the anticipated bank - f_wb_inputs[5] = {1'b0, {14'd0,3'd3, 7'd1}}; //read on same bank (tCCD) - f_wb_inputs[6] = {1'b1, {14'd0,3'd7, 7'd0}}; //write on the un-anticipated idle bank (activate first) - f_wb_inputs[7] = {1'b1, {14'd0,3'd1, 7'd1}}; //write on the un-anticipated active bank and row (write) - f_wb_inputs[8] = {1'b1, {14'd1,3'd7, 7'd0}}; //write on the un-anticipated active bank but wrong row (precharge first) - */ - /* - f_wb_inputs[0] = {1'b0, {14'd0,3'd1, 7'd0}}; //read - f_wb_inputs[1] = {1'b0, {14'd0,3'd1, 7'd1}}; //read - f_wb_inputs[2] = {1'b0, {14'd0,3'd1, 7'd2}}; //read - f_wb_inputs[3] = {1'b0, {14'd0,3'd1, 7'd3}}; //read - f_wb_inputs[4] = {1'b0, {14'd0,3'd1, 7'd4}}; //read - f_wb_inputs[5] = {1'b0, {14'd0,3'd1, 7'd5}}; //read - f_wb_inputs[6] = {1'b0, {14'd0,3'd1, 7'd6}}; //write - f_wb_inputs[7] = {1'b0, {14'd0,3'd1, 7'd7}}; //write - f_wb_inputs[8] = {1'b0, {14'd0,3'd1, 7'd8}}; //write - f_wb_inputs[9] = {1'b0, {14'd0,3'd1, 7'd9}}; //write - f_wb_inputs[10] = {1'b0, {14'd0,3'd1, 7'd10}}; //write - f_wb_inputs[11] = {1'b0, {14'd0,3'd1, 7'd11}}; //write - */ - /* - f_wb_inputs[0] = {1'b0, {14'd1,3'd1, 7'd120}}; //write on same bank (tRTW) - f_wb_inputs[1] = {1'b0, {14'd1,3'd1, 7'd121}}; //write on different bank (already activated) - f_wb_inputs[2] = {1'b0, {14'd1,3'd1, 7'd122}}; //write (tCCD) - f_wb_inputs[3] = {1'b0, {14'd1,3'd1, 7'd123}}; //write on different bank (already activated but wrong row) - f_wb_inputs[4] = {1'b0, {14'd1,3'd1, 7'd124}}; //write (tCCD) - f_wb_inputs[5] = {1'b0, {14'd1,3'd1, 7'd125}}; //write (tCCD) - f_wb_inputs[6] = {1'b0, {14'd1,3'd1, 7'd126}}; //read (same bank but wrong row so precharge first) - f_wb_inputs[7] = {1'b0, {14'd1,3'd1, 7'd127}}; //read (tCCD) - f_wb_inputs[8] = {1'b0, {14'd1,3'd2, 7'd0}}; //read (tCCD) - f_wb_inputs[9] = {1'b0, {14'd1,3'd2, 7'd1}}; //read (tCCD) - f_wb_inputs[10] = {1'b0, {14'd1,3'd2, 7'd2}}; //read (tCCD) - */ - end - initial begin - f_reset_counter = 0; - end - always @(posedge i_controller_clk) begin - if(!o_wb_stall) begin - f_index <= f_index + 1; //number of requests accepted - end - f_reset_counter <= f_reset_counter + 1; - end - - always @(posedge i_controller_clk) begin - assume(i_wb_cyc == 1); - assume(i_wb_stb == 1); - if(f_past_valid) begin - assume(i_rst_n); - end - assume(i_wb_we == f_wb_inputs[f_index][24]); - assume(i_wb_addr == f_wb_inputs[f_index][23:0]); - cover(f_index == 10); - if(f_index != 0) begin - assume(i_rst_n); //dont reset just to skip a request forcefully - end - end - `endif //endif for FORMAL_COVER - - - `ifdef TEST_TIME_PARAMETERS - // Test time parameter violations - reg[6:0] f_precharge_time_stamp[(1<= tCCD); - end - - if(cmd_d[READ_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0101) begin //READ - f_read_time_stamp[cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] <= f_timer + READ_SLOT; - //Check tCCD (read-to-read delay) - assert((f_timer+READ_SLOT) - f_read_time_stamp[bank_const] >= tCCD); - end - end - end - - always @* begin - // make sure saved time stamp is valid - assert(f_precharge_time_stamp[bank_const] <= f_timer); - assert(f_activate_time_stamp[bank_const] <= f_timer); - assert(f_read_time_stamp[bank_const] <= f_timer); - assert(f_write_time_stamp[bank_const] <= f_timer); - - // Check tRTP (Internal READ Command to PRECHARGE Command delay in SAME BANK) - if(f_precharge_time_stamp[bank_const] > f_read_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_read_time_stamp[bank_const]) >= ns_to_nCK(10)); - end - - // Check tWTR (Delay from start of internal write transaction to internal read command) - if(f_read_time_stamp[bank_const] > f_write_time_stamp[bank_const]) begin - assert((f_read_time_stamp[bank_const] - f_write_time_stamp[bank_const]) >= (CWL_nCK + 3'd4 + ns_to_nCK(tWTR))); - end - - // Check tRCD (ACT to internal read delay time) - if(f_read_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_read_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRCD)); - end - - // Check tRCD (ACT to internal write delay time) - if(f_write_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_write_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRCD)); - end - - // Check tRP (PRE command period) - if(f_activate_time_stamp[bank_const] > f_precharge_time_stamp[bank_const]) begin - assert((f_activate_time_stamp[bank_const] - f_precharge_time_stamp[bank_const]) >= ns_to_nCK(tRP)); - end - - // Check tRAS (ACTIVE to PRECHARGE command period) - if(f_precharge_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRAS)); - end - - // Check tWR (WRITE recovery time for write-to-precharge) - if(f_precharge_time_stamp[bank_const] > f_write_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_write_time_stamp[bank_const]) >= (CWL_nCK + 3'd4 + ns_to_nCK(tWR))); - end - - // Check delay from read-to-write - if(f_write_time_stamp[bank_const] > f_read_time_stamp[bank_const]) begin - assert((f_write_time_stamp[bank_const] - f_read_time_stamp[bank_const]) >= (CL_nCK + tCCD + 3'd2 - CWL_nCK)); - end - - end - - // extra assertions to make sure engine starts properly - always @* begin - assert(instruction_address <= 22); - assert(state_calibrate <= DONE_CALIBRATE); - - if(!o_wb_stall) begin - assert(state_calibrate == DONE_CALIBRATE); - assert(instruction_address == 22 || (instruction_address == 19 && delay_counter == 0)); - end - - if(instruction_address == 19 && delay_counter != 0 && state_calibrate == DONE_CALIBRATE) begin - if(stage1_pending || stage2_pending) begin - assert(pause_counter); - end - end - - if(stage1_pending || stage2_pending) begin - assert(state_calibrate > ISSUE_WRITE_1); - assert(instruction_address == 22 || instruction_address == 19); - end - - if(instruction_address < 13) begin - assert(state_calibrate == IDLE); - end - - if(state_calibrate > IDLE && state_calibrate <= BITSLIP_DQS_TRAIN_2) begin - assert(instruction_address == 13); - assert(pause_counter); - end - - - if(state_calibrate > START_WRITE_LEVEL && state_calibrate <= WAIT_FOR_FEEDBACK) begin - assert(instruction_address == 17); - assert(pause_counter); - end - - if(pause_counter) begin - assert(delay_counter != 0); - end - - if(state_calibrate > ISSUE_WRITE_1 && state_calibrate < DONE_CALIBRATE) begin - assume(instruction_address == 22); //write-then-read calibration will not take more than tREFI (7.8us, delay a address 22) - assert(reset_done); - end - - if(state_calibrate == DONE_CALIBRATE) begin - assert(reset_done); - assert(instruction_address >= 19); - end - - if(reset_done) begin - assert(instruction_address >= 19); - end - - if(!reset_done) begin - assert(!stage1_pending && !stage2_pending); - assert(o_wb_stall); - end - if(reset_done) begin - assert(instruction_address >= 19 && instruction_address <= 22); - end - //delay_counter is zero at first clock of new instruction address, the actual delay_clock wil start at next clock cycle - if(instruction_address == 19 && delay_counter != 0) begin - assert(o_wb_stall); - end - - if(instruction_address == 19 && pause_counter) begin //pre-stall delay to finish all remaining requests - assert(delay_counter == PRE_REFRESH_DELAY); - assert(reset_done); - assert(DONE_CALIBRATE); - end - end - - /* - always @(posedge i_controller_clk) begin - if(f_past_valid) begin - if($past(instruction_address) == 22 && instruction_address == 19) begin - assert(state_calibrate == DONE_CALIBRATE); - end - end - end - */ - `endif //endif for TEST_TIME_PARAMETERS - - - `ifdef TEST_CONTROLLER_PIPELINE - // wires and registers used in this formal section - `ifdef TEST_DATA - localparam F_TEST_CMD_DATA_WIDTH = $bits(i_wb_data) + $bits(i_wb_sel) + $bits(i_aux) + $bits(i_wb_addr) + $bits(i_wb_we); - `else - localparam F_TEST_CMD_DATA_WIDTH = $bits(i_wb_addr) + $bits(i_wb_we); - `endif - localparam F_MAX_STALL = max(WRITE_TO_PRECHARGE_DELAY,READ_TO_PRECHARGE_DELAY) + 1 + PRECHARGE_TO_ACTIVATE_DELAY + 1 + max(ACTIVATE_TO_WRITE_DELAY,ACTIVATE_TO_READ_DELAY) + 1 ; - //worst case delay (Precharge -> Activate-> R/W) - //add 1 to each delay since they end at zero - localparam F_MAX_ACK_DELAY = F_MAX_STALL + (READ_ACK_PIPE_WIDTH + 2); //max_stall + size of shift_reg_read_pipe_q + o_wb_ack_read_q (assume to be two via read_pipe_max) - - (*keep*) wire[3:0] f_max_stall, f_max_ack_delay; - assign f_max_stall = F_MAX_STALL; - assign f_max_ack_delay = F_MAX_ACK_DELAY; - - reg f_past_valid = 0; - reg[$bits(instruction_address) - 1: 0] f_addr = 0, f_read = 0 ; - reg[$bits(instruction) - 1:0] f_read_inst = INITIAL_RESET_INSTRUCTION; - reg[3:0] f_count_refreshes = 0; //count how many refresh cycles had already passed - reg[24:0] f_wb_inputs[31:0]; - reg[4:0] f_index = 0; - reg[5:0] f_counter = 0; - - reg[4:0] f_index_1 = 0; - reg[4:0] f_index_2 = 0; - reg[F_TEST_CMD_DATA_WIDTH - 1:0] f_write_data; - reg f_write_fifo = 0, f_read_fifo = 0; - reg[ROW_BITS-1:0] f_bank_active_row[(1< nCK_to_cycles(tDLLK)); //Initialization sequence requires that tDLLK is satisfied after MRS to mode register 0 and ZQ calibration - assert(MR0[18] != 1'b1); //last Mode Register bit should never be zero - assert(MR1_WL_EN[18] != 1'b1); //(as this is used for A10-AP control for non-MRS - assert(MR1_WL_DIS[18] != 1'b1); //(as this is used for A10-AP control for non-MRS - assert(MR2[18] != 1'b1); //commands in the reset sequence) - assert(MR3_MPR_EN[18] != 1'b1); - assert(MR3_MPR_DIS[18] != 1'b1); - assert(DELAY_COUNTER_WIDTH <= $bits(MR0)); //bitwidth of mode register should be enough for the delay counter - //sanity checking to ensure 5 bits is allotted for extra instruction {reset_finished, use_timer , stay_command , cke , reset_n } - assert(($bits(instruction) - $bits(CMD_MRS) - $bits(MR0)) == 5 ); - assert(DELAY_SLOT_WIDTH >= DELAY_COUNTER_WIDTH); //width occupied by delay timer slot on the reset rom must be able to occupy the maximum possible delay value on the reset sequence - end - - always @(posedge i_controller_clk) f_past_valid <= 1; - - - //The idea below is sourced from https://zipcpu.com/formal/2019/11/18/genuctrlr.html - //We will form a packet of information describing each instruction as it goes through the pipeline and make assertions along the way. - //2-stage Pipeline: f_addr (update address) -> f_read (read instruction from rom) - - //pipeline stage logic: f_addr (update address) -> f_read (read instruction from rom) - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - f_addr <= 0; - f_read <= 0; - end - //move the pipeline forward when counter is about to go zero and we are not yet at end of reset sequence - else if((delay_counter == 1 || !instruction[USE_TIMER])) begin - f_addr <= (f_addr == 22)? 19:f_addr + 1; - f_read <= f_addr; - end - end - - // assert f_addr and f_read as shadows of next and current instruction address - always @* begin - assert(f_addr == instruction_address); //f_addr is the shadow of instruction_address (thus f_addr is the address of NEXT instruction) - f_read_inst = read_rom_instruction(f_read); //f_read is the address of CURRENT instruction - assert(f_read_inst == read_rom_instruction(f_read)); // needed for induction to make sure the engine will not create his own instruction - if(f_addr == 0) begin - f_read_inst = INITIAL_RESET_INSTRUCTION; //will only happen at the very start: f_addr (0) -> f_read (0) where we are reading the initial reset instruction and not the rom - end - assert(f_read_inst == instruction); // f_read_inst is the shadow of current instruction - end - - // main assertions for the reset sequence - always @(posedge i_controller_clk) begin - if(!i_rst_n || !$past(i_rst_n)) begin - assert(f_addr == 0); - assert(f_read == 0); - assert(instruction_address == 0); - assert(delay_counter == (INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0])); - assert(delay_counter_is_zero == (INITIAL_RESET_INSTRUCTION[DELAY_COUNTER_WIDTH - 1:0] == 0)); - end - else if(f_past_valid) begin - //if counter is zero previously and current instruction needs timer delay, then this cycle should now have the new updated counter value - if( $past(delay_counter_is_zero) && $past(f_read_inst[USE_TIMER]) ) begin - assert(delay_counter == f_read_inst[DELAY_COUNTER_WIDTH - 1:0]); - end - //delay_counter_is_zero can be high when counter is zero and current instruction needs delay - if($past(f_read_inst[USE_TIMER]) && !$past(pause_counter) ) begin - assert( delay_counter_is_zero == (delay_counter == 0) ); - end - //delay_counter_is_zero will go high this cycle when we received a don't-use-timer instruction - else if(!$past(f_read_inst[USE_TIMER]) && !$past(pause_counter)) begin - assert(delay_counter_is_zero); - end - - //we are on the middle of a delay thus all values must remain constant while only delay_counter changes (decrement) - if(!delay_counter_is_zero) begin - assert(f_addr == $past(f_addr)); - assert(f_read == $past(f_read)); - assert(f_read_inst == $past(f_read_inst)); - end - - //if delay is not yet zero and timer delay is enabled, then delay_counter should decrement - if(!$past(delay_counter_is_zero) && $past(f_read_inst[USE_TIMER]) && !$past(pause_counter) ) begin - assert(delay_counter == $past(delay_counter) - 1); - assert(delay_counter < $past(delay_counter) ); //just to make sure delay_counter will never overflow back to all 1's - end - - //sanity checking for the comment "delay_counter will be zero AT NEXT CLOCK CYCLE when counter is now one" - if($past(delay_counter) == 1) begin - assert(delay_counter == 0 && delay_counter_is_zero); - end - //assert the relationship between the stages FOR RESET SEQUENCE - if(!reset_done) begin - if(f_addr == 0) begin - assert(f_read == 0); //will only happen at the very start: f_addr (0) -> f_read (0) - end - else if(f_read == 0) begin - assert(f_addr <= 1); //will only happen at the very first two cycles: f_addr (1) -> f_read (0) or f_addr (0) -> f_read (0) - end - //else if($past(reset_done)) assert(f_read == $past(f_read)); //reset instruction does not repeat after reaching end address thus it must saturate when pipeline reaches end - else begin - assert(f_read + 1 == f_addr); //address increments continuously - end - assert($past(f_read) < 21); //only instruction address 0-to-13 is for reset sequence (reset_done is asserted at address 14) - end - - //assert the relationship between the stages FOR REFRESH SEQUENCE - else begin - if(f_read == 22) begin - assert(f_addr == 19); //if current instruction is 22, then next instruction must be at 19 (instruction address wraps from 15 to 12) - end - else if(f_addr == 19) begin - assert(f_read == 22); //if next instruction is at 12, then current instruction must be at 15 (instruction address wraps from 15 to 12) - end - else begin - assert(f_read + 1 == f_addr); //if there is no need to wrap around, then instruction address must increment - end - assert((f_read >= 19 && f_read <= 22) ); //refresh sequence is only on instruction address 19,20,21,22 - end - - // reset_done must retain high when it was already asserted once - if($past(reset_done)) begin - assert(reset_done); - end - - // reset is already done at address 21 and up - if($past(f_read) >= 21 ) begin - assert(reset_done); - end - - //if reset is done, the REF_IDLE must only be high at instruction address 14 (on the middle of tREFI) - if(reset_done && f_read_inst[REF_IDLE]) begin - assert(f_read == 21); - end - - end - - end - - - // assertions on the instructions stored on the rom - always @* begin - //there MUST BE no instruction which USE_TIMER is high but delay is zero since it can cause the logic to lock-up (delay must be at least 1) - if(a[USE_TIMER]) begin - assert( a[DELAY_COUNTER_WIDTH - 1:0] > 0); - end - end - - // assertion on FSM calibration - always @* begin - if(instruction_address < 13) begin - assert(state_calibrate == IDLE); - end - - if(state_calibrate > IDLE && state_calibrate <= BITSLIP_DQS_TRAIN_2) begin - assert(instruction_address == 13); - assert(pause_counter); - end - - - if(state_calibrate > START_WRITE_LEVEL && state_calibrate <= WAIT_FOR_FEEDBACK) begin - assert(instruction_address == 17); - assert(pause_counter); - end - - if(pause_counter) begin - assert(delay_counter != 0); - end - - if(state_calibrate > ISSUE_WRITE_1 && state_calibrate < DONE_CALIBRATE) begin - assume(instruction_address == 22); //write-then-read calibration will not take more than tREFI (7.8us, delay a address 22) - assert(reset_done); - end - - if(state_calibrate == DONE_CALIBRATE) begin - assert(reset_done); - assert(instruction_address >= 19); - end - - if(reset_done) begin - assert(instruction_address >= 19); - end - end - - always @* begin - //make sure each command has distinct slot number (except for read/write which can have the same or different slot number) - //assert((WRITE_SLOT != ACTIVATE_SLOT != PRECHARGE_SLOT) && (READ_SLOT != ACTIVATE_SLOT != PRECHARGE_SLOT) ); - assert(WRITE_SLOT != ACTIVATE_SLOT); - assert(WRITE_SLOT != PRECHARGE_SLOT); - assert(READ_SLOT != ACTIVATE_SLOT); - assert(READ_SLOT != PRECHARGE_SLOT); - //make sure slot number for read command is correct - end - //create a formal assertion that says during refresh ack should be low always - //make an assertion that there will be no request pending before actual refresh starts at instruction 4'd12 - - - mini_fifo #( - .FIFO_WIDTH(1), //the fifo will have 2**FIFO_WIDTH positions - .DATA_WIDTH(F_TEST_CMD_DATA_WIDTH) //each FIFO position can store DATA_WIDTH bits - ) fifo_1 ( - .i_clk(i_controller_clk), - .i_rst_n(i_rst_n && i_wb_cyc), //reset outstanding request at reset or when cyc goes low - .read_fifo(f_read_fifo), - .write_fifo(f_write_fifo), - .empty(f_empty), - .full(f_full), - .write_data(f_write_data), - .read_data(f_read_data), - .read_data_next(f_read_data_next) - ); - - always @* begin - if(state_calibrate == DONE_CALIBRATE && i_wb_cyc) begin - if(f_full) begin - assert(stage1_pending && stage2_pending);//there are 2 contents - end - if(stage1_pending && stage2_pending) begin - assert(f_full); - end - - if(!f_empty && !f_full) begin - assert(stage1_pending ^ stage2_pending);//there is 1 content - end - if(stage1_pending ^ stage2_pending) begin - assert(!f_empty && !f_full); - end - - if(f_empty) begin - assert(stage1_pending == 0 && stage2_pending==0); //there is 0 content - end - if(stage1_pending == 0 && stage2_pending == 0) begin - assert(f_empty); - end - end - - if(state_calibrate < ISSUE_WRITE_1) begin - assert(!stage1_pending && !stage2_pending); - end - if(stage1_pending && state_calibrate == ISSUE_READ) begin - assert(stage1_we); - end - if(stage2_pending && state_calibrate == ISSUE_READ) begin - assert(stage2_we); - end - if(state_calibrate == ANALYZE_DATA) begin - assert(!stage1_pending && !stage2_pending); - end - end - - always @(posedge i_controller_clk) begin - if(f_past_valid) begin - //switch from calibrate to done - if(state_calibrate == DONE_CALIBRATE && $past(state_calibrate) != DONE_CALIBRATE) begin - assert($past(state_calibrate) == ANALYZE_DATA); - assert(f_empty); - assert(!stage1_pending); - assert(!stage2_pending); - //assert(f_bank_status == 1); //only first bank is activated - //assert(bank_status_q == 1); - end - if(stage1_pending && $past(state_calibrate) == READ_DATA && state_calibrate == READ_DATA) begin - assert(!stage1_we); - end - if(instruction_address == 21 || ($past(instruction_address) == 20 && $past(instruction_address,2) == 19) || instruction_address < 19) begin //not inside active or calibration - assert(f_bank_status == 0); - assert(bank_status_q == 0); - end - if(state_calibrate != DONE_CALIBRATE) begin - assert(f_bank_status == 0 || f_bank_status == 1); //only first bank is activated - assert(bank_status_q == 0 || f_bank_status == 1); - end - end - end - - //wishbone request should have a corresponding DDR3 command at the output - //wishbone request will be written to fifo, then once a DDR3 command is - //issued the fifo will be read to check if the DDR3 command matches the - //corresponding wishbone request - reg[ROW_BITS-1:0] f_read_data_col; - reg[BA_BITS-1:0] f_read_data_bank; - reg[AUX_WIDTH-1:0] f_read_data_aux; - reg[wb_sel_bits-1:0] f_read_data_wb_sel; - always @* begin - //write the wb request to fifo - if(i_wb_stb && i_wb_cyc && !o_wb_stall && state_calibrate == DONE_CALIBRATE) begin - f_write_fifo = 1; - `ifdef TEST_DATA - f_write_data = {i_wb_data, i_wb_sel, i_aux, i_wb_addr,i_wb_we}; - `else - f_write_data = {i_wb_addr,i_wb_we}; - `endif - end - else begin - f_write_fifo = 0; - end - f_read_fifo = 0; - //check if a DDR3 command is issued - if(i_wb_cyc) begin //only if already done calibrate and controller can accept wb request - - if(cmd_d[WRITE_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0100) begin //WRITE - if(state_calibrate == DONE_CALIBRATE) begin - assert(f_bank_status[cmd_d[WRITE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == 1'b1); //the bank that will be written must initially be active - f_read_data_col = {f_read_data[1 +: COL_BITS - $clog2(serdes_ratio*2)], 3'b000}; //column address must match - assert(cmd_d[WRITE_SLOT][CMD_ADDRESS_START:0] == f_read_data_col); - - f_read_data_bank = f_read_data[(COL_BITS - $clog2(serdes_ratio*2)) + 1 +: BA_BITS]; //bank must match - assert(cmd_d[WRITE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1] == f_read_data_bank); - - `ifdef TEST_DATA - f_read_data_aux = f_read_data[$bits(i_wb_addr) + 1 +: AUX_WIDTH]; //UAX ID must match - assert(stage2_aux == f_read_data_aux); - - f_read_data_wb_sel = (f_read_data[$bits(i_wb_addr) + AUX_WIDTH + 1 +: $bits(i_wb_sel)]); - assert(stage2_dm_unaligned == ~f_read_data_wb_sel); //data mask mst match inverse of wb sel - assert(stage2_data_unaligned == f_read_data[$bits(i_wb_sel) + $bits(i_wb_addr) + AUX_WIDTH + 1 +: $bits(i_wb_data)]); //actual data must match - `endif - - assert(f_read_data[0]); //i_wb_we must be high - f_read_fifo = 1; //advance read pointer to prepare for next read - end - else if(state_calibrate > ISSUE_WRITE_1) begin - assert(stage2_aux == 1); - end - //assert(f_bank_active_row[cmd_d[WRITE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == current_row); //column to be written must be the current active row - end - - if(cmd_d[READ_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0101) begin //READ - if(state_calibrate == DONE_CALIBRATE) begin - assert(f_bank_status[cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == 1'b1); //the bank that will be read must initially be active - f_read_data_col = {f_read_data[1 +: COL_BITS - $clog2(serdes_ratio*2)], 3'b000}; //column address must match - assert(cmd_d[READ_SLOT][CMD_ADDRESS_START:0] == f_read_data_col); - - f_read_data_bank = f_read_data[(COL_BITS - $clog2(serdes_ratio*2)) + 1 +: BA_BITS]; //bank must match - assert(cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1] == f_read_data_bank); - - `ifdef TEST_DATA - f_read_data_aux = f_read_data[$bits(i_wb_addr) + 1 +: AUX_WIDTH]; //UAX ID must match - assert(stage2_aux == f_read_data_aux); - `endif - - assert(!f_read_data[0]); //i_wb_we must be low - f_read_fifo = 1; //advance read pointer to prepare for next read - end - else if(state_calibrate > ISSUE_WRITE_1) begin - assert(stage2_aux == 0); - end - //assert(f_bank_active_row[cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == current_row);//column to be written must be the current active row - end - - if(cmd_d[PRECHARGE_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0010) begin //PRECHARGE - if(state_calibrate == DONE_CALIBRATE && (instruction_address == 22 || instruction_address == 19)) begin - assert(f_bank_status[cmd_d[PRECHARGE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == 1'b1); //the bank that should be precharged must initially be active - end - end - - if(cmd_d[ACTIVATE_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0011) begin //ACTIVATE - if(state_calibrate == DONE_CALIBRATE) begin - assert(f_bank_status[cmd_d[ACTIVATE_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] == 1'b0); //the bank that should be activated must initially be precharged - end - end - - if(reset_done) begin - assert(cmd_d[PRECHARGE_SLOT][CMD_CKE] && cmd_d[PRECHARGE_SLOT][CMD_RESET_N]); //cke and rst_n should stay high when reset sequence is already done - assert(cmd_d[ACTIVATE_SLOT][CMD_CKE] && cmd_d[ACTIVATE_SLOT][CMD_RESET_N]); //cke and rst_n should stay high when reset sequence is already done - assert(cmd_d[READ_SLOT][CMD_CKE] && cmd_d[READ_SLOT][CMD_RESET_N]); //cke and rst_n should stay high when reset sequence is already done - assert(cmd_d[WRITE_SLOT][CMD_CKE] && cmd_d[WRITE_SLOT][CMD_RESET_N]); //cke and rst_n should stay high when reset sequence is already done - end - end - if(state_calibrate == DONE_CALIBRATE) begin - assert(reset_done); - end - if(state_calibrate != DONE_CALIBRATE) begin - assert(o_wb_stall); //if not yet finished calibrating, stall should never go low - end - if(state_calibrate != DONE_CALIBRATE) begin - assert(f_empty); //if not yet finished calibrating, stall should never go low - end - if(!f_empty) begin - assert(state_calibrate == DONE_CALIBRATE); - end - end - - //`ifdef UNDER_CONSTRUCTION - //make assertions on what is inside the fifo - always @* begin - if(!f_empty && !f_full) begin //make assertion when there is only 1 data on the pipe - if(stage1_pending) begin //request is still on stage1 - assert(stage1_bank == f_read_data[(COL_BITS - $clog2(serdes_ratio*2)) + 1 +: BA_BITS]); //bank must match - assert(stage1_col == {f_read_data[1 +: COL_BITS - $clog2(serdes_ratio*2)], 3'b000}); //column address must match - assert(stage1_we == f_read_data[0]); //i_wb_we must be high - end - if(stage2_pending) begin //request is now on stage2 - assert(stage2_bank == f_read_data[(COL_BITS - $clog2(serdes_ratio*2)) + 1 +: BA_BITS]); //bank must match - assert(stage2_col == {f_read_data[1 +: COL_BITS - $clog2(serdes_ratio*2)], 3'b000}); //column address must match - assert(stage2_we == f_read_data[0]); //i_wb_we must be high - end - end - if(f_full) begin //both stages have request - //stage2 is the request on the tip of the fifo - assert(stage2_bank == f_read_data[(COL_BITS - $clog2(serdes_ratio*2)) + 1 +: BA_BITS]); //bank must match - assert(stage2_col == {f_read_data[1 +: COL_BITS - $clog2(serdes_ratio*2)], 3'b000}); //column address must match - assert(stage2_we == f_read_data[0]); //i_wb_we must be high - //stage1 is the request on the other element of the fifo - //(since the fifo only has 2 elements, the other element that - //is not the tip will surely be the 2nd request that is being - //handles by stage1) - assert(stage1_bank == f_read_data_next[(COL_BITS - $clog2(serdes_ratio*2)) + 1 +: BA_BITS]); //bank must match - assert(stage1_col == {f_read_data_next[1 +: COL_BITS - $clog2(serdes_ratio*2)], 3'b000}); //column address must match - assert(stage1_we == f_read_data_next[0]); //i_wb_we must be high - end - end - - //`endif - - always @* begin - assert(f_bank_status == bank_status_q); - end - - (*keep*) reg[31:0] bank; - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - //reset bank status and active row - for(index=0; index < (1< ISSUE_WRITE_1 && state_calibrate < DONE_CALIBRATE) begin - if(stage1_pending) begin - assert(stage1_we == stage1_aux); //if write, then aux id must be 1 else 0 - end - if(stage2_pending) begin - assert(stage2_we == stage2_aux); //if write, then aux id must be 1 else 0 - end - end - - assert(state_calibrate <= DONE_CALIBRATE); - end - - wire[3:0] f_nreqs, f_nacks, f_outstanding, f_ackwait_count, f_stall_count; - wire[3:0] f_nreqs_2, f_nacks_2, f_outstanding_2; - reg[READ_ACK_PIPE_WIDTH+1:0] f_ack_pipe_after_stage2; - reg[AUX_WIDTH:0] f_aux_ack_pipe_after_stage2[READ_ACK_PIPE_WIDTH+1:0]; - integer f_ack_pipe_marker; - - integer f_sum_of_pending_acks = 0; - always @* begin - if(!i_rst_n) begin - assume(f_nreqs == 0); - assume(f_nacks == 0); - end - - if(state_calibrate != IDLE) assume(added_read_pipe_max == 1); - f_sum_of_pending_acks = stage1_pending + stage2_pending; - for(index = 0; index < READ_ACK_PIPE_WIDTH; index = index + 1) begin - f_sum_of_pending_acks = f_sum_of_pending_acks + shift_reg_read_pipe_q[index][0] + 0; - end - for(index = 0; index < 2; index = index + 1) begin //since added_read_pipe_max is assumed to be one, only the first two bits of o_wb_ack_read_q is relevant - f_sum_of_pending_acks = f_sum_of_pending_acks + o_wb_ack_read_q[index][0] + 0; - end - - //the remaining o_wb_ack_read_q (>2) should stay zero at - //all instance - for(index = 2; index < MAX_ADDED_READ_ACK_DELAY ; index = index + 1) begin - assert(o_wb_ack_read_q[index] == 0); - end - f_aux_ack_pipe_after_stage2[READ_ACK_PIPE_WIDTH+1] = o_wb_ack_read_q[0]; //last stage of f_aux_ack_pipe_after_stage2 is also the last ack stage - f_aux_ack_pipe_after_stage2[READ_ACK_PIPE_WIDTH] = o_wb_ack_read_q[1]; - for(index = 0; index < READ_ACK_PIPE_WIDTH; index = index + 1) begin - f_aux_ack_pipe_after_stage2[READ_ACK_PIPE_WIDTH - 1 - index] = shift_reg_read_pipe_q[index]; - end - f_ack_pipe_after_stage2 = { - o_wb_ack_read_q[0][0], - o_wb_ack_read_q[1][0], - shift_reg_read_pipe_q[0][0], - shift_reg_read_pipe_q[1][0], - shift_reg_read_pipe_q[2][0], - shift_reg_read_pipe_q[3][0], - shift_reg_read_pipe_q[4][0] - }; - - if(f_ackwait_count > F_MAX_STALL) begin - assert(|f_ack_pipe_after_stage2[(READ_ACK_PIPE_WIDTH+1) : (f_ackwait_count - F_MAX_STALL - 1)]); //at least one stage must be high - end - - - if(i_rst_n && state_calibrate == DONE_CALIBRATE) begin - assert(f_outstanding == f_sum_of_pending_acks || !i_wb_cyc); - end - else if(!i_rst_n) begin - assert(f_sum_of_pending_acks == 0); - end - if(state_calibrate != DONE_CALIBRATE && i_rst_n) begin - assert(f_outstanding == 0 || !i_wb_cyc); - end - if(state_calibrate <= ISSUE_WRITE_1 && i_rst_n) begin - //not inside tREFI, prestall delay, nor precharge - assert(f_outstanding == 0 || !i_wb_cyc); - assert(f_sum_of_pending_acks == 0); - end - if(state_calibrate == READ_DATA && i_rst_n) begin - assert(f_outstanding == 0 || !i_wb_cyc); - assert(f_sum_of_pending_acks <= 3); - - if((f_sum_of_pending_acks > 1) && o_wb_ack_read_q[0]) begin - assert(o_wb_ack_read_q[0] == {1, 1'b1}); - end - - f_ack_pipe_marker = 0; - for(index = 0; index < READ_ACK_PIPE_WIDTH + 2; index = index + 1) begin //check each ack stage starting from last stage - if(f_aux_ack_pipe_after_stage2[index][0]) begin //if ack is high - if(f_aux_ack_pipe_after_stage2[index][AUX_WIDTH:1] == 0) begin //ack for read - assert(f_ack_pipe_marker == 0); //read ack must be the last ack on the pipe(f_pipe_marker must still be zero) - f_ack_pipe_marker = f_ack_pipe_marker + 1; - assert(!stage1_pending && !stage2_pending); //a single read request must be the last request on this calibration - end - else begin //ack for write - assert(f_aux_ack_pipe_after_stage2[index][AUX_WIDTH:1] == 1); - f_ack_pipe_marker = f_ack_pipe_marker + 1; - end - end - end - assert(f_ack_pipe_marker <= 3); - end - - if(state_calibrate == ANALYZE_DATA && i_rst_n) begin - assert(f_outstanding == 0 || !i_wb_cyc); - assert(f_sum_of_pending_acks == 0); - end - if(state_calibrate != DONE_CALIBRATE && i_rst_n) begin //if not yet done calibration, no request should be accepted - assert(f_nreqs == 0); - assert(f_nacks == 0); - assert(f_outstanding == 0 || !i_wb_cyc); - end - - if(state_calibrate == ISSUE_WRITE_2 || state_calibrate == ISSUE_READ) begin - if(write_calib_stb == 1) begin - assert(write_calib_aux == 1); - assert(write_calib_we == 1); - end - end - if(!stage1_pending) begin - assert(!stage1_stall); - end - - if(!stage2_pending) begin - assert(!stage2_stall); - end - end - always @(posedge i_controller_clk) begin - if(f_past_valid) begin - if(instruction_address != 22 && instruction_address != 19 && $past(i_wb_cyc) && i_rst_n) begin - assert(f_nreqs == $past(f_nreqs)); - end - if(state_calibrate == DONE_CALIBRATE && $past(state_calibrate) != DONE_CALIBRATE && i_rst_n) begin//just started DONE_CALBRATION - assert(f_nreqs == 0); - assert(f_nacks == 0); - assert(f_outstanding == 0); - assert(f_sum_of_pending_acks == 0); - end - if((!stage1_pending || !stage2_pending) && $past(state_calibrate) == DONE_CALIBRATE && state_calibrate == DONE_CALIBRATE - && instruction_address == 22 && $past(instruction_address == 22)) begin - assert(!o_wb_stall);//if even 1 of the stage is empty, o_wb_stall must be low - end - end - end - - //test the delay_before* - always @* begin - for(index=0; index< (1<= tCCD); - end - - if(cmd_d[READ_SLOT][CMD_CS_N:CMD_WE_N] == 4'b0101) begin //READ - f_read_time_stamp[cmd_d[READ_SLOT][CMD_BANK_START:CMD_ADDRESS_START+1]] <= f_timer + READ_SLOT; - //Check tCCD (read-to-read delay) - assert((f_timer+READ_SLOT) - f_read_time_stamp[bank_const] >= tCCD); - end - end - end - - always @* begin - // make sure saved time stamp is valid - assert(f_precharge_time_stamp[bank_const] <= f_timer); - assert(f_activate_time_stamp[bank_const] <= f_timer); - assert(f_read_time_stamp[bank_const] <= f_timer); - assert(f_write_time_stamp[bank_const] <= f_timer); - - // Check tRTP (Internal READ Command to PRECHARGE Command delay in SAME BANK) - if(f_precharge_time_stamp[bank_const] > f_read_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_read_time_stamp[bank_const]) >= ns_to_nCK(10)); - end - - // Check tWTR (Delay from start of internal write transaction to internal read command) - if(f_read_time_stamp[bank_const] > f_write_time_stamp[bank_const]) begin - assert((f_read_time_stamp[bank_const] - f_write_time_stamp[bank_const]) >= (CWL_nCK + 3'd4 + ns_to_nCK(tWTR))); - end - - // Check tRCD (ACT to internal read delay time) - if(f_read_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_read_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRCD)); - end - - // Check tRCD (ACT to internal write delay time) - if(f_write_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_write_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRCD)); - end - - // Check tRP (PRE command period) - if(f_activate_time_stamp[bank_const] > f_precharge_time_stamp[bank_const]) begin - assert((f_activate_time_stamp[bank_const] - f_precharge_time_stamp[bank_const]) >= ns_to_nCK(tRP)); - end - - // Check tRAS (ACTIVE to PRECHARGE command period) - if(f_precharge_time_stamp[bank_const] > f_activate_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_activate_time_stamp[bank_const]) >= ns_to_nCK(tRAS)); - end - - // Check tWR (WRITE recovery time for write-to-precharge) - if(f_precharge_time_stamp[bank_const] > f_write_time_stamp[bank_const]) begin - assert((f_precharge_time_stamp[bank_const] - f_write_time_stamp[bank_const]) >= (CWL_nCK + 3'd4 + ns_to_nCK(tWR))); - end - - // Check delay from read-to-write - if(f_write_time_stamp[bank_const] > f_read_time_stamp[bank_const]) begin - assert((f_write_time_stamp[bank_const] - f_read_time_stamp[bank_const]) >= (CL_nCK + tCCD + 3'd2 - CWL_nCK)); - end - - end - - // extra assertions to make sure engine starts properly - always @* begin - assert(instruction_address <= 22); - assert(state_calibrate <= DONE_CALIBRATE); - - if(!o_wb_stall) begin - assert(state_calibrate == DONE_CALIBRATE); - assert(instruction_address == 22 || (instruction_address == 19 && delay_counter == 0)); - end - - if(instruction_address == 19 && delay_counter != 0 && state_calibrate == DONE_CALIBRATE) begin - if(stage1_pending || stage2_pending) begin - assert(pause_counter); - end - end - - if(stage1_pending || stage2_pending) begin - assert(state_calibrate > ISSUE_WRITE_1); - assert(instruction_address == 22 || instruction_address == 19); - end - - if(instruction_address < 13) begin - assert(state_calibrate == IDLE); - end - - if(state_calibrate > IDLE && state_calibrate <= BITSLIP_DQS_TRAIN_2) begin - assert(instruction_address == 13); - assert(pause_counter); - end - - - if(state_calibrate > START_WRITE_LEVEL && state_calibrate <= WAIT_FOR_FEEDBACK) begin - assert(instruction_address == 17); - assert(pause_counter); - end - - if(pause_counter) begin - assert(delay_counter != 0); - end - - if(state_calibrate > ISSUE_WRITE_1 && state_calibrate < DONE_CALIBRATE) begin - assume(instruction_address == 22); //write-then-read calibration will not take more than tREFI (7.8us, delay a address 22) - assert(reset_done); - end - - if(state_calibrate == DONE_CALIBRATE) begin - assert(reset_done); - assert(instruction_address >= 19); - end - - if(reset_done) begin - assert(instruction_address >= 19); - end - - if(!reset_done) begin - assert(!stage1_pending && !stage2_pending); - assert(o_wb_stall); - end - if(reset_done) begin - assert(instruction_address >= 19 && instruction_address <= 22); - end - //delay_counter is zero at first clock of new instruction address, the actual delay_clock wil start at next clock cycle - if(instruction_address == 19 && delay_counter != 0) begin - assert(o_wb_stall); - end - - if(instruction_address == 19 && pause_counter) begin //pre-stall delay to finish all remaining requests - assert(delay_counter == PRE_REFRESH_DELAY); - assert(reset_done); - assert(DONE_CALIBRATE); - end - end - - // verify the wishbone 2 - localparam F_TEST_WB2_DATA_WIDTH = wb2_sel_bits + 5 + $clog2(LANES) + 4 + 1; //WB2_SEL + CNTVALUEIN + LANE_NUMBER + MEMORY_MAPPED_ADDRESS + REQUEST_TYPE - reg f_read_fifo_2, f_write_fifo_2; - wire f_empty_2, f_full_2; - reg[F_TEST_WB2_DATA_WIDTH - 1:0] f_write_data_2 = 0; - reg[F_TEST_WB2_DATA_WIDTH - 1:0] f_read_data_2, f_read_data_2_q; - reg f_o_wb2_ack_q = 0; //registered o_wb2_ack - (*keep*) reg[LANES-1:0] f_delay_ld = 0; - - //accept request - always @* begin - if(state_calibrate != DONE_CALIBRATE) begin //not yet done calibrating - assert(!o_wb2_ack); - assert(!wb2_stb); - assert(o_wb2_stall); - assert(!wb2_update); - end - if(f_empty_2 && i_wb2_cyc) begin - assert(!wb2_stb && !o_wb2_ack); - end - if(!wb2_stb && !o_wb2_ack) begin - assert(f_empty_2); - end - f_write_data_2 = 0; - f_write_fifo_2 = 0; - if(i_wb2_stb && !o_wb2_stall && i_wb2_cyc) begin //if there is request - if(i_wb2_we) begin - f_write_data_2 = {i_wb2_sel, i_wb2_data[4:0], i_wb2_data[5 +: $clog2(LANES)], i_wb2_addr[3:0], i_wb2_we}; //CNTVALUEIN + LANE_NUMBER + MEMORY_MAPPED_ADDRESS + REQUEST_TYPE - end - else begin //read request - f_write_data_2 = {i_wb2_addr[4 +: $clog2(LANES)], i_wb2_addr[3:0], i_wb2_we}; //LANE_NUMBER + MEMORY_MAPPED_ADDRESS + REQUEST_TYPE - end - f_write_fifo_2 = 1; - end - end - - //verify outcome of request - always @(posedge i_controller_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - f_o_wb2_ack_q <= 0; - f_read_data_2_q <= 0; - end - else begin - f_o_wb2_ack_q <= o_wb2_ack && f_read_data_2[0] && i_wb2_cyc; - f_read_data_2_q <= f_read_data_2; - end - end - always @* begin - if(i_rst_n) begin - if(wb2_stb && o_wb2_ack) begin - assert(f_full_2 || !i_wb2_cyc); - end - if(f_full_2) begin - assert(wb2_stb && o_wb2_ack); - assert(f_outstanding_2 == 2 || !i_wb2_cyc); - end - if(f_outstanding_2 == 2) begin - assert(f_full_2 || !i_wb2_cyc); - end - if(f_empty_2) begin - assert(f_outstanding_2 == 0 || !i_wb2_cyc); - end - if(f_outstanding_2 == 0) begin - assert(f_empty_2 || !i_wb2_cyc); - end - end - assert(f_outstanding_2 <= 2); - f_read_fifo_2 = 0; - if(f_o_wb2_ack_q && i_rst_n && (&f_read_data_2_q[5 + $clog2(LANES) + 4 + 1 +: $rtoi($ceil( ($clog2(LANES) + 5)/8 ))])) begin //write request (the sel bits must be high) - case(f_read_data_2_q[4:1]) //memory-mapped address - 0: begin - assert(o_phy_odelay_data_ld == (1 << f_read_data_2_q[5 +: $clog2(LANES)])); //the phy lane to be loaded must be high - assert(o_phy_odelay_data_cntvaluein == f_read_data_2_q[(5 + $clog2(LANES)) +: 5]); //the phy interface for cntvalue must already be updated - end - 1: begin - assert(o_phy_odelay_dqs_ld == (1 << f_read_data_2_q[5 +: $clog2(LANES)])); //the phy lane to be loaded must be high - assert(o_phy_odelay_dqs_cntvaluein == f_read_data_2_q[(5 + $clog2(LANES)) +: 5]); //the phy interface for cntvalue must already be updated - end - 2: begin - assert(o_phy_idelay_data_ld == (1 << f_read_data_2_q[5 +: $clog2(LANES)])); //the phy lane to be loaded must be high - assert(o_phy_idelay_data_cntvaluein == f_read_data_2_q[(5 + $clog2(LANES)) +: 5]); //the phy interface for cntvalue must already be updated - end - 3: begin - assert(o_phy_idelay_dqs_ld == (1 << f_read_data_2_q[5 +: $clog2(LANES)])); //the phy lane to be loaded must be high - assert(o_phy_idelay_dqs_cntvaluein == f_read_data_2_q[(5 + $clog2(LANES)) +: 5]); //the phy interface for cntvalue must already be updated - end - endcase - end - if(o_wb2_ack && !f_read_data_2[0] && i_rst_n) begin //read request - f_read_fifo_2 = 1; - end - - if(o_wb2_ack && f_read_data_2[0] && i_rst_n) begin - f_read_fifo_2 = 1; - end - end - wire[2:0] f_read_data_2_lane; - assign f_read_data_2_lane = f_read_data_2[5 +: $clog2(LANES)]; - always @(posedge i_controller_clk) begin - //read request - if(o_wb2_ack && !f_read_data_2[0] && i_rst_n && i_wb2_cyc && !(f_o_wb2_ack_q && f_read_data_2_q[1 +: (4 + $clog2(LANES))] == f_read_data_2[1 +: (4 + $clog2(LANES))] )) begin - case(f_read_data_2[4:1]) //memory-mapped address - 0: begin - assert(o_wb2_data == odelay_data_cntvaluein[f_read_data_2[5 +: $clog2(LANES)]]); //the stored delay must match the wb2 output - end - 1: begin - assert(o_wb2_data == odelay_dqs_cntvaluein[f_read_data_2[5 +: $clog2(LANES)]]); //the stored delay must match the wb2 output - end - 2: begin - assert(o_wb2_data == idelay_data_cntvaluein[f_read_data_2[5 +: $clog2(LANES)]]); //the stored delay must match the wb2 output - end - 3: begin - assert(o_wb2_data == idelay_dqs_cntvaluein[f_read_data_2[5 +: $clog2(LANES)]]); //the stored delay must match the wb2 output - end - endcase - end - if(f_past_valid) begin - for(index = 0; index < LANES; index = index + 1) begin - if(o_phy_bitslip[index]) begin - /* Bitslip cannot be asserted for two consecutive CLKDIV cycles; Bitslip must be - deasserted for at least one CLKDIV cycle between two Bitslip assertions. - */ - assert(!$past(o_phy_bitslip[index])); - end - end - end - end - - mini_fifo #( - .FIFO_WIDTH(1), //the fifo will have 2**FIFO_WIDTH positions - .DATA_WIDTH(F_TEST_WB2_DATA_WIDTH) //each FIFO position can store DATA_WIDTH bits - ) fifo_2 ( - .i_clk(i_controller_clk), - .i_rst_n(i_rst_n && i_wb2_cyc), //reset outstanding request at reset or when cyc goes low - .read_fifo(f_read_fifo_2), - .write_fifo(f_write_fifo_2), - .empty(f_empty_2), - .full(f_full_2), - .write_data(f_write_data_2), - .read_data(f_read_data_2) - ); - - //assumption on when to do request (so as not to violate the - //F_MAX_STALL property of fwb_slave) - always @* begin - if(!(state_calibrate == DONE_CALIBRATE && instruction_address == 22)) begin //if in initialization/refresh sequence, no request should come in to the controller wishbone - assume(!i_wb_stb); - end - if(!(state_calibrate == DONE_CALIBRATE)) begin //if not yet done calibrating, no request should come in to the phy wishbone - assume(!i_wb2_stb); - end - end - fwb_slave #( - // {{{ - .AW(wb_addr_bits), - .DW(wb_data_bits), - .F_MAX_STALL(F_MAX_STALL), - .F_MAX_ACK_DELAY(F_MAX_ACK_DELAY), - .F_LGDEPTH(4), - .F_MAX_REQUESTS(10), - // OPT_BUS_ABORT: If true, the master can drop CYC at any time - // and must drop CYC following any bus error - .OPT_BUS_ABORT(1), - // - // If true, allow the bus to be kept open when there are no - // outstanding requests. This is useful for any master that - // might execute a read modify write cycle, such as an atomic - // add. - .F_OPT_RMW_BUS_OPTION(1), - // - // - // If true, allow the bus to issue multiple discontinuous - // requests. - // Unlike F_OPT_RMW_BUS_OPTION, these requests may be issued - // while other requests are outstanding - .F_OPT_DISCONTINUOUS(1), - // - // - // If true, insist that there be a minimum of a single clock - // delay between request and response. This defaults to off - // since the wishbone specification specifically doesn't - // require this. However, some interfaces do, so we allow it - // as an option here. - .F_OPT_MINCLOCK_DELAY(1), - // }}} - ) wb_properties ( - // {{{ - .i_clk(i_controller_clk), - .i_reset(!i_rst_n), - // The Wishbone bus - .i_wb_cyc(i_wb_cyc), - .i_wb_stb(i_wb_stb), - .i_wb_we(i_wb_we), - .i_wb_addr(i_wb_addr), - .i_wb_data(i_wb_data), - .i_wb_sel(i_wb_sel), - // - .i_wb_ack(o_wb_ack), - .i_wb_stall(o_wb_stall), - .i_wb_idata(o_wb_data), - .i_wb_err(1'b0), - // Some convenience output parameters - .f_nreqs(f_nreqs), - .f_nacks(f_nacks), - .f_outstanding(f_outstanding), - .f_ackwait_count(f_ackwait_count), - .f_stall_count(f_stall_count) - // }}} - // }}} - ); - - fwb_slave #( - // {{{ - .AW(WB2_ADDR_BITS), - .DW(WB2_DATA_BITS), - .F_MAX_STALL(2), - .F_MAX_ACK_DELAY(2), - .F_LGDEPTH(4), - .F_MAX_REQUESTS(10), - // OPT_BUS_ABORT: If true, the master can drop CYC at any time - // and must drop CYC following any bus error - .OPT_BUS_ABORT(1), - // - // If true, allow the bus to be kept open when there are no - // outstanding requests. This is useful for any master that - // might execute a read modify write cycle, such as an atomic - // add. - .F_OPT_RMW_BUS_OPTION(1), - // - // - // If true, allow the bus to issue multiple discontinuous - // requests. - // Unlike F_OPT_RMW_BUS_OPTION, these requests may be issued - // while other requests are outstanding - .F_OPT_DISCONTINUOUS(1), - // - // - // If true, insist that there be a minimum of a single clock - // delay between request and response. This defaults to off - // since the wishbone specification specifically doesn't - // require this. However, some interfaces do, so we allow it - // as an option here. - .F_OPT_MINCLOCK_DELAY(1), - // }}} - ) wb2_properties ( - // {{{ - .i_clk(i_controller_clk), - .i_reset(!i_rst_n), - // The Wishbone bus - .i_wb_cyc(i_wb2_cyc), - .i_wb_stb(i_wb2_stb), - .i_wb_we(i_wb2_we), - .i_wb_addr(i_wb2_addr), - .i_wb_data(i_wb2_data), - .i_wb_sel(i_wb2_sel), - // - .i_wb_ack(o_wb2_ack), - .i_wb_stall(o_wb2_stall), - .i_wb_idata(o_wb2_data), - .i_wb_err(1'b0), - // Some convenience output parameters - .f_nreqs(f_nreqs_2), - .f_nacks(f_nacks_2), - .f_outstanding(f_outstanding_2), - // }}} - // }}} - ); - `endif //endif for TEST_CONTROLLER_PIPELINE -`endif //endif for FORMAL -endmodule - -//FiFO with only 2 elements for verifying the contents of the controller -//2-stage pipeline -module mini_fifo #( - parameter FIFO_WIDTH = 1, //the fifo will have 2**FIFO_WIDTH positions - parameter DATA_WIDTH = 8 //each FIFO position can store DATA_WIDTH bits - )( - input wire i_clk, i_rst_n, - input wire read_fifo, write_fifo, - output reg empty, full, - input wire[DATA_WIDTH - 1:0] write_data, - output wire[DATA_WIDTH - 1:0] read_data, - output wire[DATA_WIDTH - 1:0] read_data_next - ); - reg[FIFO_WIDTH-1:0] write_pointer=0, read_pointer=0; - reg[DATA_WIDTH - 1:0] fifo_reg[2**FIFO_WIDTH-1:0]; - initial begin - empty = 1; - full = 0; - end - - always @(posedge i_clk, negedge i_rst_n) begin - if(!i_rst_n) begin - empty <= 1; - full <=0; - read_pointer <= 0; - write_pointer <= 0; - end - else begin - if(read_fifo) begin - `ifdef FORMAL - assert(!empty); - `endif - if(!write_fifo) full <= 0; - //advance read pointer - read_pointer <= read_pointer + 1; - if(read_pointer + 1'b1 == write_pointer && !write_fifo) empty <= 1; - end - if(write_fifo) begin - `ifdef FORMAL - if(!read_fifo) assert(!full); - `endif - if(!read_fifo) empty <= 0; - //write to FiFo - fifo_reg[write_pointer] <= write_data; - //advance read pointer - write_pointer <= write_pointer + 1; - if(write_pointer + 1'b1 == read_pointer && !read_fifo) full <= 1'b1; //fifo should never be full - end - end - end - assign read_data = fifo_reg[read_pointer]; - assign read_data_next = fifo_reg[!read_pointer]; //data after current pointer - - `ifdef FORMAL - //mini-FiFo assertions - always @* begin - if(empty || full) begin - assert(write_pointer == read_pointer); - end - if(write_pointer == read_pointer) begin - assert(empty || full); - end - assert(!(empty && full)); - //TASK ADD MORE ASSERTIONS - end - `endif - -endmodule - -