From 8f3d673e3d685b1b17b014f81c84d10511943d58 Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Tue, 22 Aug 2023 16:40:44 +0800 Subject: [PATCH] fixed bug when issue write calibration has to be repeated --- rtl/ddr3_controller.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/rtl/ddr3_controller.v b/rtl/ddr3_controller.v index c01ec09..1e603f6 100644 --- a/rtl/ddr3_controller.v +++ b/rtl/ddr3_controller.v @@ -436,7 +436,7 @@ module ddr3_controller #( reg prev_write_level_feedback = 1; reg[wb_data_bits-1:0] read_data_store = 0; reg[127:0] write_pattern = 0; - reg[$clog2(64):0] data_start_index[LANES-1:0]; + (* mark_debug = "true" *) reg[$clog2(64):0] data_start_index[LANES-1:0]; reg[4:0] odelay_data_cntvaluein[LANES-1:0]; reg[4:0] odelay_dqs_cntvaluein[LANES-1:0]; reg[4:0] idelay_data_cntvaluein[LANES-1:0]; @@ -1519,6 +1519,7 @@ module ddr3_controller #( else begin data_start_index[lane] <= data_start_index[lane] + 8; if(data_start_index[lane] == 56) begin + data_start_index[lane] <= 0; state_calibrate <= ISSUE_WRITE_1; end end