From 42b42023dd1aa9577f4f112cca166441f3eda622 Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Sun, 9 Mar 2025 10:13:07 +0800 Subject: [PATCH 1/2] Update README.md updated link for micron model file --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index fb395c5..1c6cb9e 100644 --- a/README.md +++ b/README.md @@ -145,7 +145,7 @@ Last is the [Symbiyosys Formal Verification](https://symbiyosys.readthedocs.io/e # Simulation -For simulation, the DDR3 SDRAM Verilog [Model from Micron](https://www.micron.com/search-results?searchRequest=%7B%22term%22%3A%22DDR3%20model%22%7D) is used. Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado. [`ddr3_dimm_micron_sim.sv`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/testbench/ddr3_dimm_micron_sim.sv) is the top-level module which instantiates both the DDR3 memory controller and the Micron DDR3 model. This module issues read and write requests to the controller via the wishbone bus, then the returned data from read requests are verified if it matches the data written. Both sequential and random accesses are tested. +For simulation, the DDR3 SDRAM Verilog [Model from Micron](https://www.micron.com/search-results?searchRequest=DDR3+SDRAM+Verilog+Model&SelectedValues=%2Fsim-model--%2Fsim-model%2Fbdsl--%2Fsim-model%2Fbfm--%2Fsim-model%2Fcadence-dml--%2Fsim-model%2Fhspice--%2Fsim-model%2Fhyperlynx--%2Fsim-model%2Fibis--%2Fsim-model%2Fibis-ami--%2Fsim-model%2Fmentor-icx--%2Fsim-model%2Fs-parameter--%2Fsim-model%2Fspice--%2Fsim-model%2Fsisoft--%2Fsim-model%2Fsystem-c--%2Fsim-model%2Fsystem-verilog--%2Fsim-model%2Fthermal--%2Fsim-model%2Fverilog#accordion-db73c0b4db-item-4671aec5a3) is used. Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado. [`ddr3_dimm_micron_sim.sv`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/testbench/ddr3_dimm_micron_sim.sv) is the top-level module which instantiates both the DDR3 memory controller and the Micron DDR3 model. This module issues read and write requests to the controller via the wishbone bus, then the returned data from read requests are verified if it matches the data written. Both sequential and random accesses are tested. Currently, there are 2 general options for running the simulation and is defined by a `define` directive on the `ddr3_dimm_micron_sim.sv` file: `TWO_LANES_x8` and `EIGHT_LANES_x8`. `TWO_LANES_x8` simulates an Arty-S7 FPGA board which has an x16 DDR3, meanwhile `EIGHT_LANES_x8` simulates 8-lanes of x8 DDR3 module. **Make sure to change the organization via a `define` directive under [ddr3.sv](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/testbench/ddr3.sv)** (`TWO_LANES_x8` must use `define x8` while `EIGHT_LANES_x8` must use `define x16`). From 47067f6903d6e062ccbcc0da872864de97afca5d Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Sun, 9 Mar 2025 10:57:43 +0800 Subject: [PATCH 2/2] remove xadc define and uncomment INTERNAL_VREF to make this work in openxc7 (openxc7 still fails due to shiftout ports) --- example_demo/arty_s7/arty_ddr3.v | 4 ++-- example_demo/arty_s7/arty_ddr3.xdc | 4 +++- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/example_demo/arty_s7/arty_ddr3.v b/example_demo/arty_s7/arty_ddr3.v index 765a14c..29bd70e 100644 --- a/example_demo/arty_s7/arty_ddr3.v +++ b/example_demo/arty_s7/arty_ddr3.v @@ -146,14 +146,14 @@ .uart_rx_data(rd_data) // The recieved data. ); - `define XADC + // `define XADC `ifdef XADC xadc_wiz_0 xadc_inst ( .dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port .user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output ); `else - user_temp_alarm_out = 1'b0; + assign user_temp_alarm_out = 1'b0; `endif // UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used) diff --git a/example_demo/arty_s7/arty_ddr3.xdc b/example_demo/arty_s7/arty_ddr3.xdc index ca60931..447251c 100755 --- a/example_demo/arty_s7/arty_ddr3.xdc +++ b/example_demo/arty_s7/arty_ddr3.xdc @@ -260,6 +260,8 @@ set_property CONFIG_MODE SPIx4 [current_design] ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being ## used the internal reference is set to half that value (i.e. 0.675v). Note that ## this property must be set even if SW3 is not used in the design. - set_property INTERNAL_VREF 0.675 [get_iobanks 34] + +## COMMENT THIS OUT IF RUNNING IN OPENXC7 (OTHERWISE UNCOMMENT THIS) +# set_property INTERNAL_VREF 0.675 [get_iobanks 34]