From 88a4f9afa79291dc498b68818220f49f3f15c9fd Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Mon, 24 Jun 2024 17:19:04 +0800 Subject: [PATCH] add ecc files --- run_compile.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/run_compile.sh b/run_compile.sh index 56f644d..9891ec3 100755 --- a/run_compile.sh +++ b/run_compile.sh @@ -1,6 +1,6 @@ # run verilator lint echo -e "\e[32mRun Verilator Lint:\e[0m" -verilator --lint-only rtl/ddr3_controller.v -Irtl/ -Wall +verilator --lint-only rtl/ddr3_controller.v rtl/ecc/ecc_dec.sv rtl/ecc/ecc_enc.sv -Irtl/ -Wall echo "DONE!" @@ -9,7 +9,7 @@ echo "" echo "" echo -e "\e[32mRun Yosys Compile:\e[0m" yosys -q -p " - read_verilog -sv ./rtl/ddr3_controller.v; + read_verilog -sv ./rtl/ddr3_controller.v rtl/ecc/ecc_dec.sv rtl/ecc/ecc_enc.sv; synth -top ddr3_controller" # run iverilog compile