From 69768da1c8507f7d259e72a8448e8036847afd28 Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Fri, 4 Aug 2023 16:37:10 +0800 Subject: [PATCH] added files for kintex switch project (autofpga files, xdc, wbscope cpp) --- kintex_switch_files/ddr3.txt | 315 ++++++++++++++++++++ kintex_switch_files/ddr3scope1.cpp | 113 ++++++++ kintex_switch_files/ddr3scope2.cpp | 117 ++++++++ kintex_switch_files/kluster.xdc | 451 +++++++++++++++++++++++++++++ 4 files changed, 996 insertions(+) create mode 100644 kintex_switch_files/ddr3.txt create mode 100644 kintex_switch_files/ddr3scope1.cpp create mode 100644 kintex_switch_files/ddr3scope2.cpp create mode 100644 kintex_switch_files/kluster.xdc diff --git a/kintex_switch_files/ddr3.txt b/kintex_switch_files/ddr3.txt new file mode 100644 index 0000000..c1f067b --- /dev/null +++ b/kintex_switch_files/ddr3.txt @@ -0,0 +1,315 @@ +################################################################################ +## +## Filename: ddr3.txt +## {{{ +## Project: 10Gb Ethernet switch +## +## Purpose: To describe how to provide access to an SDRAM controller +## from the Wishbone bus, where such SDRAM controller uses a +## different clock from the Wishbone bus itself. +## +## Creator: Dan Gisselquist, Ph.D. +## Gisselquist Technology, LLC +## +################################################################################ +## }}} +## Copyright (C) 2023, Gisselquist Technology, LLC +## {{{ +## This file is part of the ETH10G project. +## +## The ETH10G project contains free software and gateware, licensed under the +## Apache License, Version 2.0 (the "License"). You may not use this project, +## or this file, except in compliance with the License. You may obtain a copy +## of the License at +## }}} +## http://www.apache.org/licenses/LICENSE-2.0 +## {{{ +## Unless required by applicable law or agreed to in writing, files +## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +## License for the specific language governing permissions and limitations +## under the License. +## +################################################################################ +## +## }}} + +# Wishbone 1 +@PREFIX=ddr3_controller +@DEVID=DDR3_CONTROLLER +@ACCESS=@$(DEVID)_ACCESS +## LGMEMSZ is the size of the SDRAM in bytes. For a 1GB DDR3 RAM: 30 => 1GB +@$LGMEMSZ=30 +@LGMEMSZ.FORMAT=%d +@$NADDR=(1<< @$(LGMEMSZ))/(@$(SLAVE.BUS.WIDTH)/8) +@$NBYTES=(1<<(@$LGMEMSZ)) +@NBYTES.FORMAT=0x%08x +@$MADDR= @$(REGBASE) +@MADDR.FORMAT=0x%08x +@$NLANES=@$(SLAVE.BUS.WIDTH)/64 +@SLAVE.TYPE=MEMORY +@SLAVE.BUS=wbwide +@BUS=wbwide +@LD.PERM=wx +# +@REGS.N=1 +@REGS.0= 0 R_@$(DEVID) @$(DEVID) +@REGDEFS.H.DEFNS= +#define @$(DEVID)BASE @$[0x%08x](REGBASE) +#define @$(DEVID)LEN @$(NBYTES) +@BDEF.OSDEF=_BOARD_HAS_@$(DEVID) +@BDEF.OSVAL=extern char _@$(PREFIX)[@$NBYTES]; + +@TOP.PORTLIST= + // DDR3 I/O port wires + o_ddr3_reset_n, o_ddr3_cke, o_ddr3_clk_p, o_ddr3_clk_n, + o_ddr3_s_n, o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n, + o_ddr3_ba, o_ddr3_a, + o_ddr3_odt, o_ddr3_dm, + io_ddr3_dqs_p, io_ddr3_dqs_n, io_ddr3_dq + + +@TOP.PARAM= + localparam real @$(DEVID)CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module + DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device + localparam @$(DEVID)ROW_BITS = 14, // width of row address + @$(DEVID)COL_BITS = 10, // width of column address + @$(DEVID)BA_BITS = 3, // width of bank address + @$(DEVID)DQ_BITS = 8, // Size of one octet + @$(DEVID)LANES = @$(NLANES), //8 lanes of DQ + @$(DEVID)AUX_WIDTH = 1, + @$(DEVID)SERDES_RATIO = $rtoi(@$(DEVID)CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD), + //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits + @$(DEVID)CMD_LEN = 4 + 3 + @$(DEVID)BA_BITS + @$(DEVID)ROW_BITS; + + +@TOP.IODECL= + // I/O declarations for the DDR3 SDRAM + // {{{ + output wire o_ddr3_reset_n; + output wire [1:0] o_ddr3_cke; + output wire [0:0] o_ddr3_clk_p, o_ddr3_clk_n; + output wire [1:0] o_ddr3_s_n; // o_ddr3_s_n[1] is set to 0 since controller only support single rank + output wire [0:0] o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n; + output wire [@$(DEVID)BA_BITS-1:0] o_ddr3_ba; + output wire [15:0] o_ddr3_a; //set to max of 16 bits, but only ROW_BITS bits are relevant + output wire [1:0] o_ddr3_odt; + output wire [@$(DEVID)LANES-1:0] o_ddr3_dm; + inout wire [(@$(DEVID)DQ_BITS*@$(DEVID)LANES)/8-1:0] io_ddr3_dqs_p, io_ddr3_dqs_n; + inout wire [(@$(DEVID)DQ_BITS*@$(DEVID)LANES)-1:0] io_ddr3_dq; + // }}} + + +@TOP.DEFNS= + // Wires connected to PHY interface of DDR3 controller + // {{{ + genvar @$(PREFIX)gen_index; + + wire [@$(DEVID)DQ_BITS*@$(DEVID)LANES*8-1:0] @$(PREFIX)_iserdes_data; + wire [@$(DEVID)LANES*8-1:0] @$(PREFIX)_iserdes_dqs; + wire [@$(DEVID)LANES*8-1:0] @$(PREFIX)_iserdes_bitslip_reference; + wire @$(PREFIX)_idelayctrl_rdy; + wire [@$(DEVID)CMD_LEN*@$(DEVID)SERDES_RATIO-1:0] @$(PREFIX)_cmd; + wire @$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control; + wire @$(PREFIX)_toggle_dqs; + wire [@$(SLAVE.BUS.WIDTH)-1:0] @$(PREFIX)_data; + wire [@$(SLAVE.BUS.WIDTH)/8-1:0] @$(PREFIX)_dm; + wire [4:0] @$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein; + wire [4:0] @$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein; + wire [@$(DEVID)LANES-1:0] @$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld; + wire [@$(DEVID)LANES-1:0] @$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld; + wire [@$(DEVID)LANES-1:0] @$(PREFIX)_bitslip; + // }}} +@TOP.MAIN= + // DDR3 Controller-PHY Interface + @$(PREFIX)_iserdes_data, @$(PREFIX)_iserdes_dqs, + @$(PREFIX)_iserdes_bitslip_reference, + @$(PREFIX)_idelayctrl_rdy, + @$(PREFIX)_cmd, + @$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control, + @$(PREFIX)_toggle_dqs, @$(PREFIX)_data, @$(PREFIX)_dm, + @$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein, + @$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein, + @$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld, + @$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld, + @$(PREFIX)_bitslip +@TOP.INSERT= + // DDR3 PHY Instantiation + ddr3_phy #( + .ROW_BITS(@$(DEVID)ROW_BITS), //width of row address + .BA_BITS(@$(DEVID)BA_BITS), //width of bank address + .DQ_BITS(@$(DEVID)DQ_BITS), //width of DQ + .LANES(@$(DEVID)LANES), //8 lanes of DQ + .CONTROLLER_CLK_PERIOD(@$(DEVID)CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module + .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD) //ns, period of clock input to DDR3 RAM device + ) ddr3_phy_inst ( + // clock and reset + .i_controller_clk(s_clk), + .i_ddr3_clk(s_clk4x), + .i_ref_clk(s_clk200), + .i_rst_n(!s_reset), + // Controller Interface + .i_controller_cmd(@$(PREFIX)_cmd), + .i_controller_dqs_tri_control(@$(PREFIX)_dqs_tri_control), + .i_controller_dq_tri_control(@$(PREFIX)_dq_tri_control), + .i_controller_toggle_dqs(@$(PREFIX)_toggle_dqs), + .i_controller_data(@$(PREFIX)_data), + .i_controller_dm(@$(PREFIX)_dm), + .i_controller_odelay_data_cntvaluein(@$(PREFIX)_odelay_data_cntvaluein), + .i_controller_odelay_dqs_cntvaluein(@$(PREFIX)_odelay_dqs_cntvaluein), + .i_controller_idelay_data_cntvaluein(@$(PREFIX)_idelay_data_cntvaluein), + .i_controller_idelay_dqs_cntvaluein(@$(PREFIX)_idelay_dqs_cntvaluein), + .i_controller_odelay_data_ld(@$(PREFIX)_odelay_data_ld), + .i_controller_odelay_dqs_ld(@$(PREFIX)_odelay_dqs_ld), + .i_controller_idelay_data_ld(@$(PREFIX)_idelay_data_ld), + .i_controller_idelay_dqs_ld(@$(PREFIX)_idelay_dqs_ld), + .i_controller_bitslip(@$(PREFIX)_bitslip), + .o_controller_iserdes_data(@$(PREFIX)_iserdes_data), + .o_controller_iserdes_dqs(@$(PREFIX)_iserdes_dqs), + .o_controller_iserdes_bitslip_reference(@$(PREFIX)_iserdes_bitslip_reference), + .o_controller_idelayctrl_rdy(@$(PREFIX)_idelayctrl_rdy), + // DDR3 I/O Interface + .o_ddr3_clk_p(o_ddr3_clk_p), + .o_ddr3_clk_n(o_ddr3_clk_n), + .o_ddr3_reset_n(o_ddr3_reset_n), + .o_ddr3_cke(o_ddr3_cke[0]), // CKE + .o_ddr3_cs_n(o_ddr3_s_n[0]), // chip select signal (controls rank 1 only) + .o_ddr3_ras_n(o_ddr3_ras_n), // RAS# + .o_ddr3_cas_n(o_ddr3_cas_n), // CAS# + .o_ddr3_we_n(o_ddr3_we_n), // WE# + .o_ddr3_addr(o_ddr3_a[@$(DEVID)ROW_BITS-1:0]), + .o_ddr3_ba_addr(o_ddr3_ba), + .io_ddr3_dq(io_ddr3_dq), + .io_ddr3_dqs(io_ddr3_dqs_p), + .io_ddr3_dqs_n(io_ddr3_dqs_n), + .o_ddr3_dm(o_ddr3_dm), + .o_ddr3_odt(o_ddr3_odt[0]) // on-die termination + ); + + assign o_ddr3_s_n[1] = 1; // set to 1 (disabled) since controller only supports single rank + assign o_ddr3_cke[1] = 0; // set to 0 (disabled) since controller only supports single rank + assign o_ddr3_odt[1] = 0; // set to 0 (disabled) since controller only supports single rank + generate for(@$(PREFIX)gen_index = @$(DEVID)ROW_BITS; + @$(PREFIX)gen_index < 16; + @$(PREFIX)gen_index = @$(PREFIX)gen_index + 1) + begin : GEN_UNUSED_@$(DEVID)_ASSIGN + assign o_ddr3_a[@$(PREFIX)gen_index] = 0; + end endgenerate + +@MAIN.PORTLIST= + // DDR3 Controller Interface + i_@$(PREFIX)_iserdes_data, i_@$(PREFIX)_iserdes_dqs, + i_@$(PREFIX)_iserdes_bitslip_reference, + i_@$(PREFIX)_idelayctrl_rdy, + o_@$(PREFIX)_cmd, + o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control, + o_@$(PREFIX)_toggle_dqs, o_@$(PREFIX)_data, o_@$(PREFIX)_dm, + o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein, + o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein, + o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld, + o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld, + o_@$(PREFIX)_bitslip +@MAIN.PARAM=@$(TOP.PARAM) +@MAIN.IODECL= + // DDR3 Controller I/O declarations + // {{{ + input wire [@$(DEVID)DQ_BITS*@$(DEVID)LANES*8-1:0] i_@$(PREFIX)_iserdes_data; + input wire [@$(DEVID)LANES*8-1:0] i_@$(PREFIX)_iserdes_dqs; + input wire [@$(DEVID)LANES*8-1:0] i_@$(PREFIX)_iserdes_bitslip_reference; + input wire i_@$(PREFIX)_idelayctrl_rdy; + output wire [@$(DEVID)CMD_LEN*@$(DEVID)SERDES_RATIO-1:0] o_@$(PREFIX)_cmd; + output wire o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control; + output wire o_@$(PREFIX)_toggle_dqs; + output wire [@$(SLAVE.BUS.WIDTH)-1:0] o_@$(PREFIX)_data; + output wire [@$(SLAVE.BUS.WIDTH)/8-1:0] o_@$(PREFIX)_dm; + output wire [4:0] o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein; + output wire [4:0] o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein; + output wire [@$(DEVID)LANES-1:0] o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld; + output wire [@$(DEVID)LANES-1:0] o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld; + output wire [@$(DEVID)LANES-1:0] o_@$(PREFIX)_bitslip; + // }}} +@MAIN.DEFNS= + // Verilator lint_off UNUSED + wire [@$(DEVID)AUX_WIDTH-1:0] @$(PREFIX)_aux_out; + wire [31:0] @$(PREFIX)_debug1, @$(PREFIX)_debug2; + // Verilator lint_on UNUSED +@MAIN.INSERT= + //////////////////////////////////////////////////////////////////////// + // + // DDR3 Controller instantiation + // {{{ + ddr3_controller #( + .CONTROLLER_CLK_PERIOD(@$(DEVID)CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module + .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device + .ROW_BITS(@$(DEVID)ROW_BITS), //width of row address + .COL_BITS(@$(DEVID)COL_BITS), //width of column address + .BA_BITS(@$(DEVID)BA_BITS), //width of bank address + .DQ_BITS(@$(DEVID)DQ_BITS), //width of DQ + .LANES(@$(DEVID)LANES), //8 lanes of DQ + .AUX_WIDTH(@$(DEVID)AUX_WIDTH), // + .OPT_LOWPOWER(1), //1 = low power, 0 = low logic + .OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction) + ) ddr3_controller_inst ( + .i_controller_clk(i_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD + .i_rst_n(!i_reset), //200MHz input clock + // Wishbone 1 (Controller) + @$(SLAVE.ANSIPORTLIST), + .i_aux(0), + .o_aux(@$(PREFIX)_aux_out), // Leaving this empty would've caused a Verilator warning + // Wishbone 2 (PHY) + @$(ddr3_phy.SLAVE.ANSIPORTLIST), + // + // PHY interface + .i_phy_iserdes_data(i_@$(PREFIX)_iserdes_data), + .i_phy_iserdes_dqs(i_@$(PREFIX)_iserdes_dqs), + .i_phy_iserdes_bitslip_reference(i_@$(PREFIX)_iserdes_bitslip_reference), + .i_phy_idelayctrl_rdy(i_@$(PREFIX)_idelayctrl_rdy), + .o_phy_cmd(o_@$(PREFIX)_cmd), + .o_phy_dqs_tri_control(o_@$(PREFIX)_dqs_tri_control), + .o_phy_dq_tri_control(o_@$(PREFIX)_dq_tri_control), + .o_phy_toggle_dqs(o_@$(PREFIX)_toggle_dqs), + .o_phy_data(o_@$(PREFIX)_data), + .o_phy_dm(o_@$(PREFIX)_dm), + .o_phy_odelay_data_cntvaluein(o_@$(PREFIX)_odelay_data_cntvaluein), + .o_phy_odelay_dqs_cntvaluein(o_@$(PREFIX)_odelay_dqs_cntvaluein), + .o_phy_idelay_data_cntvaluein(o_@$(PREFIX)_idelay_data_cntvaluein), + .o_phy_idelay_dqs_cntvaluein(o_@$(PREFIX)_idelay_dqs_cntvaluein), + .o_phy_odelay_data_ld(o_@$(PREFIX)_odelay_data_ld), + .o_phy_odelay_dqs_ld(o_@$(PREFIX)_odelay_dqs_ld), + .o_phy_idelay_data_ld(o_@$(PREFIX)_idelay_data_ld), + .o_phy_idelay_dqs_ld(o_@$(PREFIX)_idelay_dqs_ld), + .o_phy_bitslip(o_@$(PREFIX)_bitslip), + // Debug port + .o_debug1(@$(PREFIX)_debug1), + .o_debug2(@$(PREFIX)_debug2) + ); + // }}} +## +## +@PREFIX=ddr3_phy +@DEVID=DDR3_PHY +@ACCESS=@$(DEVID)_ACCESS +@$NADDR=128 +@SLAVE.TYPE=OTHER +@SLAVE.BUS=wb32 +@SLAVE.ANSPREFIX=wb2_ +# +@REGS.N=1 +@REGS.0= 0 R_@$(DEVID) @$(DEVID) +@BDEF.DEFN= + +## Define the structure of your PHY controller here. How are the bits all +## layout out? What register names do you have? That should all go here. + +typedef struct @$(DEVID)_S { + unsigned ph_something; +} @$(DEVID); + +@BDEF.IONAME=_@$(PREFIX) +@BDEF.IOTYPE=@$(DEVID) +@BDEF.OSDEF=_BOARD_HAS_@$(DEVID) +@BDEF.OSVAL=static volatile @$(BDEF.IOTYPE) *const @$(BDEF.IONAME) = ((@$(BDEF.IOTYPE) *)@$[0x%08x](REGBASE)); + +@RTL.MAKE.GROUP= DDR3 +@RTL.MAKE.SUBD=ddr3 +@RTL.MAKE.FILES= ddr3_controller.v ddr3_phy.v diff --git a/kintex_switch_files/ddr3scope1.cpp b/kintex_switch_files/ddr3scope1.cpp new file mode 100644 index 0000000..75a5109 --- /dev/null +++ b/kintex_switch_files/ddr3scope1.cpp @@ -0,0 +1,113 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Filename: ddr3scope.cpp +// {{{ +// Project: 10Gb Ethernet switch +// +// Purpose: This file decodes the debug bits produced by the SMI IP and +// stored in a (compressed) WB scope. It is useful for determining +// if the SMI IP is working, or even if/how the RPi is toggling the +// associated SMI bits. +// +// Creator: Dan Gisselquist, Ph.D. +// Gisselquist Technology, LLC +// +//////////////////////////////////////////////////////////////////////////////// +// }}} +// Copyright (C) 2023, Gisselquist Technology, LLC +// {{{ +// This file is part of the ETH10G project. +// +// The ETH10G project contains free software and gateware, licensed under the +// Apache License, Version 2.0 (the "License"). You may not use this project, +// or this file, except in compliance with the License. You may obtain a copy +// of the License at +// }}} +// http://www.apache.org/licenses/LICENSE-2.0 +// {{{ +// Unless required by applicable law or agreed to in writing, files +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +// License for the specific language governing permissions and limitations +// under the License. +// +//////////////////////////////////////////////////////////////////////////////// +// +// }}} +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regdefs.h" +#include "devbus.h" +#include "scopecls.h" + +#ifndef R_DDR3SCOPE1 +int main(int argc, char **argv) { + printf("This design was not built with a NET scope within it.\n"); +} +#else + +#define WBSCOPE R_DDR3SCOPE1 +#define WBSCOPEDATA R_DDR3SCOPE1D + +DEVBUS *m_fpga; +void closeup(int v) { + m_fpga->kill(); + exit(0); +} + +class DDR3SCOPE1 : public SCOPE { +public: + DDR3SCOPE1(DEVBUS *fpga, unsigned addr, bool vecread = true) + : SCOPE(fpga, addr, true, vecread) {}; + ~DDR3SCOPE1(void) {} + + virtual void decode(DEVBUS::BUSW val) const { + int trigger; + + trigger = (val>>31)&1; + + printf("%6s", (trigger) ? "TRIGGERED at state_calibrate == MPR_READ! ":""); + } + + virtual void define_traces(void) { + /* + assign o_debug1 = {debug_trigger, o_wb2_stall, lane[2:0], dqs_start_index_stored[2:0], dqs_target_index[2:0], delay_before_read_data[2:0], + o_phy_idelay_dqs_ld[lane], state_calibrate[4:0], dqs_store[11:0]}; + */ + register_trace("o_wb2_stall",1,30); + register_trace("lane",3,27); + register_trace("dqs_start_index_stored",3,24); + register_trace("dqs_target_index",3,21); + register_trace("delay_before_read_data",3,18); + register_trace("o_phy_idelay_dqs_ld",1,17); + register_trace("state_calibrate",5,12); + register_trace("dqs_store",12,0); + } +}; + +int main(int argc, char **argv) { + m_fpga = connect_devbus(NULL); + + signal(SIGSTOP, closeup); + signal(SIGHUP, closeup); + + DDR3SCOPE1 *scope = new DDR3SCOPE1(m_fpga, WBSCOPE); + // scope->set_clkfreq_hz(ENETCLKFREQHZ); + scope->set_clkfreq_hz(100000000); + if (!scope->ready()) { + printf("Scope is not yet ready:\n"); + scope->decode_control(); + } else { + scope->print(); + scope->writevcd("ddr3scope1.vcd"); + } +} + +#endif diff --git a/kintex_switch_files/ddr3scope2.cpp b/kintex_switch_files/ddr3scope2.cpp new file mode 100644 index 0000000..4b23e0e --- /dev/null +++ b/kintex_switch_files/ddr3scope2.cpp @@ -0,0 +1,117 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Filename: ddr3scope.cpp +// {{{ +// Project: 10Gb Ethernet switch +// +// Purpose: This file decodes the debug bits produced by the SMI IP and +// stored in a (compressed) WB scope. It is useful for determining +// if the SMI IP is working, or even if/how the RPi is toggling the +// associated SMI bits. +// +// Creator: Dan Gisselquist, Ph.D. +// Gisselquist Technology, LLC +// +//////////////////////////////////////////////////////////////////////////////// +// }}} +// Copyright (C) 2023, Gisselquist Technology, LLC +// {{{ +// This file is part of the ETH10G project. +// +// The ETH10G project contains free software and gateware, licensed under the +// Apache License, Version 2.0 (the "License"). You may not use this project, +// or this file, except in compliance with the License. You may obtain a copy +// of the License at +// }}} +// http://www.apache.org/licenses/LICENSE-2.0 +// {{{ +// Unless required by applicable law or agreed to in writing, files +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +// License for the specific language governing permissions and limitations +// under the License. +// +//////////////////////////////////////////////////////////////////////////////// +// +// }}} +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regdefs.h" +#include "devbus.h" +#include "scopecls.h" + +#ifndef R_DDR3SCOPE2 +int main(int argc, char **argv) { + printf("This design was not built with a NET scope within it.\n"); +} +#else + +#define WBSCOPE R_DDR3SCOPE2 +#define WBSCOPEDATA R_DDR3SCOPE2D + +DEVBUS *m_fpga; +void closeup(int v) { + m_fpga->kill(); + exit(0); +} + +class DDR3SCOPE2 : public SCOPE { +public: + DDR3SCOPE2(DEVBUS *fpga, unsigned addr, bool vecread = true) + : SCOPE(fpga, addr, true, vecread) {}; + ~DDR3SCOPE2(void) {} + + virtual void decode(DEVBUS::BUSW val) const { + int trigger; + + trigger = (val>>31)&1; + + printf("%6s", (trigger) ? "TRIGGERED at state_calibrate == MPR_READ! ":""); + } + + virtual void define_traces(void) { + /* + assign o_debug2 = {debug_trigger, idelay_dqs_cntvaluein[lane][4:0], idelay_data_cntvaluein[lane][4:0], i_phy_iserdes_dqs[15:0], + o_phy_dqs_tri_control, o_phy_dq_tri_control, + (i_phy_iserdes_data == {(DQ_BITS*LANES*8){1'b0}}), (i_phy_iserdes_data == {(DQ_BITS*LANES*8){1'b1}}), (i_phy_iserdes_data < { {(DQ_BITS*LANES*4){1'b0}}, {(DQ_BITS*LANES*4){1'b1}} } ) + }; + */ + + register_trace("idelay_dqs_cntvaluein",5,26); + register_trace("idelay_data_cntvaluein",5,21); + register_trace("i_phy_iserdes_dqs_lane1",8,13); + register_trace("i_phy_iserdes_dqs_lane0",8,5); + register_trace("o_phy_dqs_tri_control",1,4); + register_trace("o_phy_dq_tri_control",1,3); + register_trace("i_phy_iserdes_data_is_zero",1,2); + register_trace("i_phy_iserdes_data_all_1s",1,1); + register_trace("i_phy_iserdes_data_less_than_half",1,0); + } +}; + +int main(int argc, char **argv) { + m_fpga = connect_devbus(NULL); + + signal(SIGSTOP, closeup); + signal(SIGHUP, closeup); + + DDR3SCOPE2 *scope = new DDR3SCOPE2(m_fpga, WBSCOPE); + // scope->set_clkfreq_hz(ENETCLKFREQHZ); + scope->set_clkfreq_hz(100000000); + if (!scope->ready()) { + printf("Scope is not yet ready:\n"); + scope->decode_control(); + } else { + scope->print(); + scope->writevcd("ddr3scope2.vcd"); + } +} + +#endif diff --git a/kintex_switch_files/kluster.xdc b/kintex_switch_files/kluster.xdc new file mode 100644 index 0000000..2bda12e --- /dev/null +++ b/kintex_switch_files/kluster.xdc @@ -0,0 +1,451 @@ +## Define our clocks +## {{{ +set_property -dict { PACKAGE_PIN AC9 IOSTANDARD DIFF_SSTL15 } [get_ports i_clk_200mhz_p] +set_property -dict { PACKAGE_PIN AD9 IOSTANDARD DIFF_SSTL15 } [get_ports i_clk_200mhz_n] +create_clock -period 5.0 -name SYSCLK -waveform { 0.0 2.50 } -add [get_ports i_clk_200mhz_p] + +#set_property -dict { PACKAGE_PIN F6 } [get_ports i_clk_150mhz_p] +#set_property -dict { PACKAGE_PIN F5 } [get_ports i_clk_150mhz_n] +#create_clock -period 6.6666 -name SATAREF -waveform { 0.0 3.3333 } -add [get_ports i_clk_150mhz_p] + +#set_property -dict { PACKAGE_PIN H6 } [get_ports i_clk_156mhz_p] +#set_property -dict { PACKAGE_PIN H5 } [get_ports i_clk_156mhz_n] +#create_clock -period 6.4 -name NETREF -waveform { 0.0 3.4 } -add [get_ports i_clk_156mhz_p] + +#set_property -dict { PACKAGE_PIN K6 } [get_ports i_clk_si_p] +#set_property -dict { PACKAGE_PIN K5 } [get_ports i_clk_si_n] +#create_clock -period 5.2 -name SIREF -waveform { 0.0 2.6 } -add [get_ports i_clk_si_p] + +#set_property -dict { PACKAGE_PIN B26 } [get_ports i_emcclk] +#create_clock -period 15.0 -name EMCCLK -waveform { 0.0 7.5 } -add [get_ports i_emcclk] + +#set_property -dict { PACKAGE_PIN B26 IOSTANDARD LVCMOS18 } [get_ports i_clk_66mhz_p] +#create_clock -period 15.0 -name INITREF -waveform { 0.0 7.5 } -add [get_ports i_clk_66mhz_p] + +#set_property -dict { PACKAGE_PIN R21 IOSTANDARD TMDS_33 } [get_ports o_siref_clk_p] +#set_property -dict { PACKAGE_PIN P21 IOSTANDARD TMDS_33 } [get_ports o_siref_clk_n] + +#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports io_siref_clk_p] +#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports io_siref_clk_n] + +## }}} + +## UART +## {{{ +#set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports o_wbu_uart_tx] +#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports i_wbu_uart_rx] +#set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports i_wbu_uart_rts_n] +#set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports o_wbu_uart_cts_n] +## }}} + +## Switches +## {{{ +#set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports i_sw[0]] +#set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports i_sw[1]] +#set_property -dict {PACKAGE_PIN D25 IOSTANDARD LVCMOS18} [get_ports i_sw[2]] +#set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports i_sw[3]] +#set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports i_sw[4]] +#set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports i_sw[5]] +#set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports i_sw[6]] +#set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS18} [get_ports i_sw[7]] +## #set_property -dict {PACKAGE_PIN J25 IOSTANDARD LVCMOS18} [get_ports i_sw[8]] +## }}} + +## Buttons +## {{{ +#set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS18} [get_ports i_nbtn_u] +#set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports i_nbtn_l] +#set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVCMOS18} [get_ports i_nbtn_c] +#set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports i_nbtn_r] +#set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports i_nbtn_d] +## }}} + +## LEDs +## {{{ +#set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS18} [get_ports o_led[0]] +#set_property -dict {PACKAGE_PIN J26 IOSTANDARD LVCMOS18} [get_ports o_led[1]] +#set_property -dict {PACKAGE_PIN G26 IOSTANDARD LVCMOS18} [get_ports o_led[2]] +#set_property -dict {PACKAGE_PIN H26 IOSTANDARD LVCMOS18} [get_ports o_led[3]] +#set_property -dict {PACKAGE_PIN G25 IOSTANDARD LVCMOS18} [get_ports o_led[4]] +#set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS18} [get_ports o_led[5]] +#set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports o_led[6]] +#set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports o_led[7]] +## }}} + +## FAN control +## {{{ +#set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS33} [get_ports i_fan_tach] +#set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports o_fan_pwm] +#set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports o_fan_sys] +## }}} + +## External resets +## {{{ +#set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports i_pi_reset_n] +#set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports i_soft_reset] +## }}} + +## I2C +## {{{ +#set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS18} [get_ports o_i2c_mxrst_n] +#set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS18} [get_ports io_i2c_scl] +#set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS18} [get_ports io_i2c_sda] +#set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS18} [get_ports io_temp_scl] +#set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS18} [get_ports io_temp_sda] +#set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS18} [get_ports i_si5324_int] +#set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS18} [get_ports o_si5324_rst] +## }}} + +## ETH10G +## {{{ +## LOS +#set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS33} [get_ports i_gnet_los[0]] +#set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports i_gnet_los[1]] +#set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports i_gnet_los[2]] +#set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS33} [get_ports i_gnet_los[3]] + +## TX Disable +#set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports o_gnettx_disable[0]] +#set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports o_gnettx_disable[1]] +#set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports o_gnettx_disable[2]] +#set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports o_gnettx_disable[3]] + +## LinkUp LEDs +#set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports o_gnet_linkup[0]] +#set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports o_gnet_linkup[1]] +#set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports o_gnet_linkup[2]] +#set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports o_gnet_linkup[3]] + +## Activity LEDs +#set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports o_gnet_activity[0]] +#set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports o_gnet_activity[1]] +#set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports o_gnet_activity[2]] +#set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports o_gnet_activity[3]] + +## Network transmit/outputs +#set_property -dict {PACKAGE_PIN P2} [get_ports o_gnet_p[0]] +#set_property -dict {PACKAGE_PIN P1} [get_ports o_gnet_n[0]] +#set_property -dict {PACKAGE_PIN M2} [get_ports o_gnet_p[1]] +#set_property -dict {PACKAGE_PIN M1} [get_ports o_gnet_n[1]] +#set_property -dict {PACKAGE_PIN K2} [get_ports o_gnet_p[2]] +#set_property -dict {PACKAGE_PIN K1} [get_ports o_gnet_n[2]] +#set_property -dict {PACKAGE_PIN H2} [get_ports o_gnet_p[3]] +#set_property -dict {PACKAGE_PIN H1} [get_ports o_gnet_n[3]] + +## Network receive/input +#set_property -dict {PACKAGE_PIN R4} [get_ports i_gnet_p[0]] +#set_property -dict {PACKAGE_PIN R3} [get_ports i_gnet_n[0]] +#set_property -dict {PACKAGE_PIN N4} [get_ports i_gnet_p[1]] +#set_property -dict {PACKAGE_PIN N3} [get_ports i_gnet_n[1]] +#set_property -dict {PACKAGE_PIN L4} [get_ports i_gnet_p[2]] +#set_property -dict {PACKAGE_PIN L3} [get_ports i_gnet_n[2]] +#set_property -dict {PACKAGE_PIN J4} [get_ports i_gnet_p[3]] +#set_property -dict {PACKAGE_PIN J3} [get_ports i_gnet_n[3]] + +## }}} + +## SMI +## {{{ +#set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports i_smi_oen] +#set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS18} [get_ports i_smi_wen] + +#set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[0]] +#set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[1]] +#set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[2]] +#set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[3]] +#set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[4]] +#set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS18} [get_ports i_smi_sa[5]] + +#set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[0]] +#set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[1]] +#set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[2]] +#set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[3]] +#set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[4]] +#set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[5]] +#set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[6]] +#set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[7]] +#set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[8]] +#set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[9]] +#set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[10]] +#set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[11]] +#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[12]] +#set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[13]] +#set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[14]] +#set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[15]] +#set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[16]] +#set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports io_smi_sd[17]] +## }}} + +## uSD +## {{{ +#set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS18} [get_ports i_sdcard_cd_n] +#set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS18} [get_ports o_sdcard_clk] + +#set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVCMOS18} [get_ports io_sdcard_cmd] +#set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS18} [get_ports io_sdcard_dat[0]] +#set_property -dict {PACKAGE_PIN AC21 IOSTANDARD LVCMOS18} [get_ports io_sdcard_dat[1]] +#set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS18} [get_ports io_sdcard_dat[2]] +#set_property -dict {PACKAGE_PIN AB21 IOSTANDARD LVCMOS18} [get_ports io_sdcard_dat[3]] +## }}} + +## Flash +## {{{ +#set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports o_flash_sel] +## The flash clock pin is CCLK_0 +#set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports o_flash_cs_n] + +#set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports io_flash_dat[0]] +#set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports io_flash_dat[1]] +#set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports io_flash_dat[2]] +#set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports io_flash_dat[3]] +## }}} + +## eMMC +## {{{ +#set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports o_emmc_clk] +#set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports io_emmc_cmd] + +#set_property -dict {PACKAGE_PIN B24 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[0]] +#set_property -dict {PACKAGE_PIN A25 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[1]] +#set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[2]] +#set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[3]] +#set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[4]] +#set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[5]] +#set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[6]] +#set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports io_emmc_dat[7]] +#set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports i_emmc_ds] +## }}} + +## SATA +## {{{ +#set_property -dict {PACKAGE_PIN B2} [get_ports o_sata_p] +#set_property -dict {PACKAGE_PIN B1} [get_ports o_sata_n] +#set_property -dict {PACKAGE_PIN C4} [get_ports i_sata_p] +#set_property -dict {PACKAGE_PIN C3} [get_ports i_sata_n] +## }}} + +## DDR3 +## {{{ +#set_property -dict {PACKAGE_PIN V11 IOSTANDARD SSTL15} [get_ports o_ddr3_reset_n] +#set_property -dict {PACKAGE_PIN AB11 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_p] +#set_property -dict {PACKAGE_PIN AC11 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_n] +#set_property -dict {PACKAGE_PIN AA9 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_p_1[1]] +#set_property -dict {PACKAGE_PIN AB9 IOSTANDARD DIFF_SSTL15} [get_ports o_ddr3_clk_n_1[1]] +#set_property -dict {PACKAGE_PIN Y10 IOSTANDARD SSTL15} [get_ports o_ddr3_cke[0]] +#set_property -dict {PACKAGE_PIN W9 IOSTANDARD SSTL15} [get_ports o_ddr3_cke[1]] + +#set_property -dict {PACKAGE_PIN AA10 IOSTANDARD SSTL15} [get_ports o_ddr3_ras_n] +#set_property -dict {PACKAGE_PIN AA7 IOSTANDARD SSTL15} [get_ports o_ddr3_cas_n] +#set_property -dict {PACKAGE_PIN Y7 IOSTANDARD SSTL15} [get_ports o_ddr3_we_n] +#set_property -dict {PACKAGE_PIN Y8 IOSTANDARD SSTL15} [get_ports o_ddr3_s_n[0]] +#set_property -dict {PACKAGE_PIN V7 IOSTANDARD SSTL15} [get_ports o_ddr3_s_n[1]] +#set_property -dict {PACKAGE_PIN AA8 IOSTANDARD SSTL15} [get_ports o_ddr3_odt[0]] +#set_property -dict {PACKAGE_PIN V9 IOSTANDARD SSTL15} [get_ports o_ddr3_odt[1]] +#set_property -dict {PACKAGE_PIN W10 IOSTANDARD SSTL15} [get_ports i_ddr3_event] + +### Address lines +### {{{ +#set_property -dict {PACKAGE_PIN AC7 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[0]] +#set_property -dict {PACKAGE_PIN V8 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[1]] +#set_property -dict {PACKAGE_PIN AC13 IOSTANDARD SSTL15} [get_ports o_ddr3_ba[2]] + +#set_property -dict {PACKAGE_PIN AF7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[0]] +#set_property -dict {PACKAGE_PIN AD8 IOSTANDARD SSTL15} [get_ports o_ddr3_a[1]] +#set_property -dict {PACKAGE_PIN AB10 IOSTANDARD SSTL15} [get_ports o_ddr3_a[2]] +#set_property -dict {PACKAGE_PIN AC8 IOSTANDARD SSTL15} [get_ports o_ddr3_a[3]] +#set_property -dict {PACKAGE_PIN W11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[4]] +#set_property -dict {PACKAGE_PIN AA12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[5]] +#set_property -dict {PACKAGE_PIN AC12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[6]] +#set_property -dict {PACKAGE_PIN AD13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[7]] + +#set_property -dict {PACKAGE_PIN AB12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[8]] +#set_property -dict {PACKAGE_PIN AD11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[9]] +#set_property -dict {PACKAGE_PIN AE7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[10]] +#set_property -dict {PACKAGE_PIN Y11 IOSTANDARD SSTL15} [get_ports o_ddr3_a[11]] +#set_property -dict {PACKAGE_PIN AA13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[12]] +#set_property -dict {PACKAGE_PIN AB7 IOSTANDARD SSTL15} [get_ports o_ddr3_a[13]] +#set_property -dict {PACKAGE_PIN Y13 IOSTANDARD SSTL15} [get_ports o_ddr3_a[14]] +#set_property -dict {PACKAGE_PIN Y12 IOSTANDARD SSTL15} [get_ports o_ddr3_a[15]] +### }}} + +### Byte lane #0 +### {{{ +#set_property -dict {PACKAGE_PIN AB17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[0]] +#set_property -dict {PACKAGE_PIN AC18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[1]] +#set_property -dict {PACKAGE_PIN AC17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[2]] +#set_property -dict {PACKAGE_PIN AD19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[3]] +#set_property -dict {PACKAGE_PIN AA19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[4]] +#set_property -dict {PACKAGE_PIN AA20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[5]] +#set_property -dict {PACKAGE_PIN AD18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[6]] +#set_property -dict {PACKAGE_PIN AC16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[7]] +#set_property -dict {PACKAGE_PIN AD20 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[0]] +#set_property -dict {PACKAGE_PIN AE20 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[0]] +#set_property -dict {PACKAGE_PIN AC19 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[0]] +### }}} + +### Byte lane #1 +### {{{ +#set_property -dict {PACKAGE_PIN V16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[8]] +#set_property -dict {PACKAGE_PIN V18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[9]] +#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[10]] +#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[11]] +#set_property -dict {PACKAGE_PIN W15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[12]] +#set_property -dict {PACKAGE_PIN V19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[13]] +#set_property -dict {PACKAGE_PIN W16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[14]] +#set_property -dict {PACKAGE_PIN Y17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[15]] +#set_property -dict {PACKAGE_PIN W18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[1]] +#set_property -dict {PACKAGE_PIN W19 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[1]] +#set_property -dict {PACKAGE_PIN V17 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[1]] +### }}} + +### Byte lane #2 +### {{{ +#set_property -dict {PACKAGE_PIN AF19 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[16]] +#set_property -dict {PACKAGE_PIN AE17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[17]] +#set_property -dict {PACKAGE_PIN AE15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[18]] +#set_property -dict {PACKAGE_PIN AF15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[19]] +#set_property -dict {PACKAGE_PIN AF20 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[20]] +#set_property -dict {PACKAGE_PIN AD16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[21]] +#set_property -dict {PACKAGE_PIN AD15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[22]] +#set_property -dict {PACKAGE_PIN AF14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[23]] +#set_property -dict {PACKAGE_PIN AE18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[2]] +#set_property -dict {PACKAGE_PIN AF18 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[2]] +#set_property -dict {PACKAGE_PIN AF17 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[2]] +### }}} + +### Byte lane #3 +### {{{ +#set_property -dict {PACKAGE_PIN AA15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[24]] +#set_property -dict {PACKAGE_PIN AB16 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[25]] +#set_property -dict {PACKAGE_PIN AD14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[26]] +#set_property -dict {PACKAGE_PIN AB14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[27]] +#set_property -dict {PACKAGE_PIN AA18 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[28]] +#set_property -dict {PACKAGE_PIN AA17 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[29]] +#set_property -dict {PACKAGE_PIN AB15 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[30]] +#set_property -dict {PACKAGE_PIN AC14 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[31]] +#set_property -dict {PACKAGE_PIN Y15 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[3]] +#set_property -dict {PACKAGE_PIN Y16 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[3]] +#set_property -dict {PACKAGE_PIN AA14 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[3]] +### }}} + +### Byte lane #4 +### {{{ +#set_property -dict {PACKAGE_PIN AD6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[32]] +#set_property -dict {PACKAGE_PIN AC6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[33]] +#set_property -dict {PACKAGE_PIN AC3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[34]] +#set_property -dict {PACKAGE_PIN AB4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[35]] +#set_property -dict {PACKAGE_PIN AB6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[36]] +#set_property -dict {PACKAGE_PIN Y6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[37]] +#set_property -dict {PACKAGE_PIN Y5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[38]] +#set_property -dict {PACKAGE_PIN AA4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[39]] +#set_property -dict {PACKAGE_PIN AA5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[4]] +#set_property -dict {PACKAGE_PIN AB5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[4]] +#set_property -dict {PACKAGE_PIN AC4 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[4]] +### }}} + +### Byte lane #5 +### {{{ +#set_property -dict {PACKAGE_PIN AF3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[40]] +#set_property -dict {PACKAGE_PIN AE3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[41]] +#set_property -dict {PACKAGE_PIN AE2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[42]] +#set_property -dict {PACKAGE_PIN AE1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[43]] +#set_property -dict {PACKAGE_PIN AE6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[44]] +#set_property -dict {PACKAGE_PIN AE5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[45]] +#set_property -dict {PACKAGE_PIN AD4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[46]] +#set_property -dict {PACKAGE_PIN AD1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[47]] +#set_property -dict {PACKAGE_PIN AF5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[5]] +#set_property -dict {PACKAGE_PIN AF4 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[5]] +#set_property -dict {PACKAGE_PIN AF2 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[5]] +### }}} + +### Byte lane #6 +### {{{ +#set_property -dict {PACKAGE_PIN W3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[48]] +#set_property -dict {PACKAGE_PIN V4 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[49]] +#set_property -dict {PACKAGE_PIN U2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[50]] +#set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[51]] +#set_property -dict {PACKAGE_PIN V6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[52]] +#set_property -dict {PACKAGE_PIN V3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[53]] +#set_property -dict {PACKAGE_PIN U1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[54]] +#set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[55]] +#set_property -dict {PACKAGE_PIN W6 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[6]] +#set_property -dict {PACKAGE_PIN W5 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[6]] +#set_property -dict {PACKAGE_PIN U7 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[6]] +### }}} + +### Byte lane #7 +### {{{ +#set_property -dict {PACKAGE_PIN AB2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[56]] +#set_property -dict {PACKAGE_PIN AA3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[57]] +#set_property -dict {PACKAGE_PIN W1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[58]] +#set_property -dict {PACKAGE_PIN V2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[59]] +#set_property -dict {PACKAGE_PIN AC2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[60]] +#set_property -dict {PACKAGE_PIN Y3 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[61]] +#set_property -dict {PACKAGE_PIN Y2 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[62]] +#set_property -dict {PACKAGE_PIN V1 IOSTANDARD SSTL15} [get_ports io_ddr3_dq[63]] +#set_property -dict {PACKAGE_PIN AB1 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_p[7]] +#set_property -dict {PACKAGE_PIN AC1 IOSTANDARD DIFF_SSTL15} [get_ports io_ddr3_dqs_n[7]] +#set_property -dict {PACKAGE_PIN Y1 IOSTANDARD SSTL15} [get_ports o_ddr3_dm[7]] +### }}} + +## }}} + +## HDMI +## {{{ +#set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports io_hdmirx_cec] +#set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS33} [get_ports o_hdmirx_hpd_n] +#set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports io_hdmirx_scl] +#set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS33} [get_ports io_hdmirx_sda] + +#set_property -dict {PACKAGE_PIN P24 IOSTANDARD TMDS_33} [get_ports i_hdmirx_p[0]] +#set_property -dict {PACKAGE_PIN N24 IOSTANDARD TMDS_33} [get_ports i_hdmirx_n[0]] +#set_property -dict {PACKAGE_PIN R26 IOSTANDARD TMDS_33} [get_ports i_hdmirx_p[1]] +#set_property -dict {PACKAGE_PIN P26 IOSTANDARD TMDS_33} [get_ports i_hdmirx_n[1]] +#set_property -dict {PACKAGE_PIN R25 IOSTANDARD TMDS_33} [get_ports i_hdmirx_p[2]] +#set_property -dict {PACKAGE_PIN P25 IOSTANDARD TMDS_33} [get_ports i_hdmirx_n[2]] +#set_property -dict {PACKAGE_PIN M24 IOSTANDARD TMDS_33} [get_ports i_hdmirx_clk_p] +#set_property -dict {PACKAGE_PIN L24 IOSTANDARD TMDS_33} [get_ports i_hdmirx_clk_n] + +#set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports io_hdmitx_cec] +#set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports i_hdmitx_hpd_n] + +#set_property -dict {PACKAGE_PIN P19 IOSTANDARD TMDS_33} [get_ports o_hdmitx_p[0]] +#set_property -dict {PACKAGE_PIN P20 IOSTANDARD TMDS_33} [get_ports o_hdmitx_n[0]] +#set_property -dict {PACKAGE_PIN K25 IOSTANDARD TMDS_33} [get_ports o_hdmitx_p[1]] +#set_property -dict {PACKAGE_PIN K26 IOSTANDARD TMDS_33} [get_ports o_hdmitx_n[1]] +#set_property -dict {PACKAGE_PIN M25 IOSTANDARD TMDS_33} [get_ports o_hdmitx_p[2]] +#set_property -dict {PACKAGE_PIN L25 IOSTANDARD TMDS_33} [get_ports o_hdmitx_n[2]] +#set_property -dict {PACKAGE_PIN N19 IOSTANDARD TMDS_33} [get_ports o_hdmitx_clk_p] +#set_property -dict {PACKAGE_PIN M20 IOSTANDARD TMDS_33} [get_ports o_hdmitx_clk_n] +## }}} + +## PCIe +## {{{ +#set_property -dict { PACKAGE_PIN D6 IOSTANDARD DIFF_HSTL_I_10 } [get_ports o_pcie_clk_p] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD DIFF_HSTL_I_10 } [get_ports o_pcie_clk_n] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD DIFF_HSTL_I_10 } [get_ports o_pcie_perst_n] + +#set_property -dict {PACKAGE_PIN A4 IOSTANDARD DIFF_HSTL_I_10 [get_ports o_pcie_p] +#set_property -dict {PACKAGE_PIN A3 IOSTANDARD DIFF_HSTL_I_10 [get_ports o_pcie_n] +#set_property -dict {PACKAGE_PIN B6 IOSTANDARD DIFF_HSTL_I_10 [get_ports i_pcie_p] +#set_property -dict {PACKAGE_PIN B5 IOSTANDARD DIFF_HSTL_I_10 [get_ports i_pcie_n] +## }}} + +## CRUVI +## {{{ +## }}} + +## Hard test points +## {{{ +#set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports o_tp[0]] +#set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS33} [get_ports o_tp[1]] +#set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS33} [get_ports o_tp[2]] +#set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports o_tp[3]] +## }}} + +## Bitstream options +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 26 [current_design] +set_property CONFIG_VOLTAGE 2.5 [current_design] +set_property CFGBVS VCCO [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]