diff --git a/example_demo/arty_s7/arty_ddr3.v b/example_demo/arty_s7/arty_ddr3.v
index 765a14c..29bd70e 100644
--- a/example_demo/arty_s7/arty_ddr3.v
+++ b/example_demo/arty_s7/arty_ddr3.v
@@ -146,14 +146,14 @@
         .uart_rx_data(rd_data)   // The recieved data.
     );
     
-    `define XADC
+    // `define XADC
      `ifdef XADC
          xadc_wiz_0 xadc_inst (
               .dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port
               .user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output
             );
       `else
-            user_temp_alarm_out = 1'b0;
+            assign user_temp_alarm_out = 1'b0;
     `endif
 
     // UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used)
diff --git a/example_demo/arty_s7/arty_ddr3.xdc b/example_demo/arty_s7/arty_ddr3.xdc
index ca60931..447251c 100755
--- a/example_demo/arty_s7/arty_ddr3.xdc
+++ b/example_demo/arty_s7/arty_ddr3.xdc
@@ -260,6 +260,8 @@ set_property CONFIG_MODE SPIx4 [current_design]
 ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
 ## used the internal reference is set to half that value (i.e. 0.675v). Note that
 ## this property must be set even if SW3 is not used in the design.
- set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+
+## COMMENT THIS OUT IF RUNNING IN OPENXC7 (OTHERWISE UNCOMMENT THIS)
+#  set_property INTERNAL_VREF 0.675 [get_iobanks 34]