From 426a4e626bf8da827e32cfe3b66f2ba70a8d25f1 Mon Sep 17 00:00:00 2001 From: AngeloJacobo Date: Sun, 25 May 2025 13:15:13 +0800 Subject: [PATCH] revert back current_design (test gocd) --- example_demo/arty_s7/arty_ddr3.xdc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/example_demo/arty_s7/arty_ddr3.xdc b/example_demo/arty_s7/arty_ddr3.xdc index a614ccd..e29317b 100755 --- a/example_demo/arty_s7/arty_ddr3.xdc +++ b/example_demo/arty_s7/arty_ddr3.xdc @@ -248,11 +248,11 @@ set_property PACKAGE_PIN T4 [get_ports ddr3_clk_n] ## Configuration options, can be used for all designs -# set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] -# set_property CONFIG_VOLTAGE 3.3 [current_design] -# set_property CFGBVS VCCO [current_design] -# set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -# set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property CONFIG_MODE SPIx4 [current_design] ## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as ## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage