diff --git a/example_demo/arty_s7/arty_ddr3.v b/example_demo/arty_s7/arty_ddr3.v
index ef299c3..765a14c 100644
--- a/example_demo/arty_s7/arty_ddr3.v
+++ b/example_demo/arty_s7/arty_ddr3.v
@@ -72,11 +72,13 @@
      wire[31:0] o_debug1;
      reg[7:0] i_wb_data;
      reg[7:0] i_wb_addr;
+     wire user_temp_alarm_out; // asserts if XADC detects internal temp to be above user temp alarm
+     
      // o_debug1 taps on value of state_calibrate (can be traced inside ddr3_controller module)
      assign led[0] = (o_debug1[4:0] != 23); //light up if not at DONE_CALIBRATE
-     assign led[1] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
-     assign led[2] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
-     assign led[3] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
+     assign led[1] = (o_debug1[4:0] == 23 && !user_temp_alarm_out); //light up if at DONE_CALIBRATE
+     assign led[2] = (o_debug1[4:0] == 23 && !user_temp_alarm_out); //light up if at DONE_CALIBRATE
+     assign led[3] = (o_debug1[4:0] == 23 && !user_temp_alarm_out); //light up if at DONE_CALIBRATE
      
     always @(posedge i_controller_clk) begin
         begin
@@ -144,6 +146,15 @@
         .uart_rx_data(rd_data)   // The recieved data.
     );
     
+    `define XADC
+     `ifdef XADC
+         xadc_wiz_0 xadc_inst (
+              .dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port
+              .user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output
+            );
+      `else
+            user_temp_alarm_out = 1'b0;
+    `endif
 
     // UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used)
     //    uart #(.DATA_WIDTH(8)) uart_m
@@ -184,7 +195,7 @@
             .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
             .i_ref_clk(i_ref_clk),
             .i_ddr3_clk_90(i_ddr3_clk_90),
-            .i_rst_n(!i_rst && clk_locked), 
+            .i_rst_n(!i_rst && clk_locked && !user_temp_alarm_out), 
             // Wishbone inputs
             .i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
             .i_wb_stb(i_wb_stb), //request a transfer
@@ -227,9 +238,7 @@
             .io_ddr3_dqs_n(ddr3_dqs_n),
             .o_ddr3_dm(ddr3_dm),
             .o_ddr3_odt(ddr3_odt), // on-die termination
-            .o_debug1(o_debug1),
-            .o_debug2(),
-            .o_debug3()
+            .o_debug1(o_debug1)
         );
 
 endmodule
diff --git a/example_demo/arty_s7/arty_ddr3.xdc b/example_demo/arty_s7/arty_ddr3.xdc
index 7e05394..ca60931 100755
--- a/example_demo/arty_s7/arty_ddr3.xdc
+++ b/example_demo/arty_s7/arty_ddr3.xdc
@@ -260,6 +260,6 @@ set_property CONFIG_MODE SPIx4 [current_design]
 ## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
 ## used the internal reference is set to half that value (i.e. 0.675v). Note that
 ## this property must be set even if SW3 is not used in the design.
-# set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+ set_property INTERNAL_VREF 0.675 [get_iobanks 34]
 
 
diff --git a/rtl/spd/clk_wiz.v b/rtl/spd/spd_clk_wiz.v
similarity index 100%
rename from rtl/spd/clk_wiz.v
rename to rtl/spd/spd_clk_wiz.v
diff --git a/testbench/ddr3.sv b/testbench/ddr3.sv
index db292bf..c6f1fba 100644
--- a/testbench/ddr3.sv
+++ b/testbench/ddr3.sv
@@ -96,7 +96,7 @@
 `timescale 1ps / 1ps
 `define den8192Mb
 `define sg125
-`define x8
+`define x16
 `default_nettype wire
 
 module ddr3 (
diff --git a/testbench/ddr3_dimm_micron_sim.sv b/testbench/ddr3_dimm_micron_sim.sv
index a89b564..6938dda 100644
--- a/testbench/ddr3_dimm_micron_sim.sv
+++ b/testbench/ddr3_dimm_micron_sim.sv
@@ -31,9 +31,10 @@
 `define sg125
 `define x16
 //`define USE_CLOCK_WIZARD
-//`define TWO_LANES_x8
-`define EIGHT_LANES_x8
+`define TWO_LANES_x8
+//`define EIGHT_LANES_x8
 `define RAM_8Gb
+`define XADC
 
 module ddr3_dimm_micron_sim;
 `ifdef den1024Mb
@@ -65,9 +66,9 @@ module ddr3_dimm_micron_sim;
             DDR3_CLK_PERIOD = 2500,//ps, period of clock input to DDR3 RAM device 
             AUX_WIDTH = 16, // AUX lines
             ECC_ENABLE = 0, // ECC enable
-            SELF_REFRESH = 2'b11,
-            DUAL_RANK_DIMM = 1,
-            TEST_SELF_REFRESH = 1;
+            SELF_REFRESH = 2'b00,
+            DUAL_RANK_DIMM = 0,
+            TEST_SELF_REFRESH = 0;
         
 
  reg i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
@@ -114,6 +115,9 @@ module ddr3_dimm_micron_sim;
   // User enabled self-refresh
   reg i_user_self_refresh;
   wire clk_locked;
+  // temperature
+  wire user_temp_alarm_out;
+  
   
   `ifdef USE_CLOCK_WIZARD
       // Use clock wizard
@@ -179,7 +183,7 @@ ddr3_top #(
         .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
         .i_ref_clk(i_ref_clk),
         .i_ddr3_clk_90(i_ddr3_clk_90),
-        .i_rst_n(i_rst_n && clk_locked), 
+        .i_rst_n(i_rst_n && clk_locked && !user_temp_alarm_out), 
         // Wishbone inputs
         .i_wb_cyc(i_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
         .i_wb_stb(i_wb_stb), //request a transfer
@@ -274,6 +278,14 @@ ddr3_top #(
                    o_ddr3_clk_n[1]=0; 
         end
     endgenerate
+    
+ `endif
+ 
+ `ifdef XADC
+     xadc_wiz_0 xadc_inst (
+              .dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port
+              .user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output
+        );
  `endif
  
  
diff --git a/testbench/design.txt b/testbench/design.txt
new file mode 100644
index 0000000..085dac1
--- /dev/null
+++ b/testbench/design.txt
@@ -0,0 +1,9 @@
+TIME TEMP 
+0       25
+30000   50
+35000  51
+50000  48
+70000  51
+80000  48
+
+