diff --git a/new_formal.gtkw b/new_formal.gtkw
new file mode 100644
index 0000000..c974707
--- /dev/null
+++ b/new_formal.gtkw
@@ -0,0 +1,90 @@
+[*]
+[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI
+[*] Tue Jun 27 09:57:53 2023
+[*]
+[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace0.vcd"
+[dumpfile_mtime] "Tue Jun 27 08:16:33 2023"
+[dumpfile_size] 370354
+[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/new_formal.gtkw"
+[timestart] 167
+[size] 1848 1126
+[pos] -51 -51
+*-4.943873 244 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 369
+[signals_width] 430
+[sst_expanded] 1
+[sst_vpaned_height] 743
+@420
+smt_step
+@28
+ddr3_controller.i_controller_clk
+ddr3_controller.i_rst_n
+@24
+ddr3_controller.state_calibrate[3:0]
+ddr3_controller.instruction_address[4:0]
+@28
+ddr3_controller.reset_done
+@200
+-
+-WB Interface
+@28
+ddr3_controller.i_wb_cyc
+ddr3_controller.o_wb_stall
+ddr3_controller.i_wb_stb
+ddr3_controller.i_wb_we
+@22
+ddr3_controller.i_wb_addr[23:0]
+ddr3_controller.i_wb_data[511:0]
+ddr3_controller.i_wb_sel[63:0]
+@28
+ddr3_controller.o_wb_ack
+@200
+-
+-Internals
+@28
+ddr3_controller.stage1_pending
+ddr3_controller.stage1_we
+@24
+ddr3_controller.stage1_bank[2:0]
+ddr3_controller.stage1_col[9:0]
+@25
+ddr3_controller.stage1_row[13:0]
+@24
+ddr3_controller.stage1_stall
+@204
+-
+@24
+ddr3_controller.stage2_pending
+ddr3_controller.stage2_we
+ddr3_controller.stage2_bank[2:0]
+ddr3_controller.stage2_col[9:0]
+ddr3_controller.stage2_row[13:0]
+ddr3_controller.stage2_stall
+@200
+-
+@28
+ddr3_controller.bank_status_q[7:0]
+@22
+ddr3_controller.delay_before_precharge_counter_q<1>[3:0]
+ddr3_controller.delay_before_precharge_counter_q<2>[3:0]
+ddr3_controller.delay_before_activate_counter_q<1>[3:0]
+ddr3_controller.delay_before_activate_counter_q<2>[3:0]
+ddr3_controller.delay_before_read_counter_q<1>[3:0]
+ddr3_controller.delay_before_read_counter_q<2>[3:0]
+ddr3_controller.delay_before_write_counter_q<1>[3:0]
+ddr3_controller.delay_before_write_counter_q<2>[3:0]
+@200
+-
+-CMD
+@28
++{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0]
++{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0]
++{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0]
++{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0]
+@200
+-
+-Formal
+@24
+ddr3_controller.f_index[4:0]
+[pattern_trace] 1
+[pattern_trace] 0