From 26af4960e98d287cd7de348d431bb8b0add7a329 Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Thu, 1 Jun 2023 19:15:36 +0800 Subject: [PATCH] fixed display for prev_cmd and time difference --- rtl/DDR3 SDRAM Verilog Model/ddr3.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/DDR3 SDRAM Verilog Model/ddr3.v b/rtl/DDR3 SDRAM Verilog Model/ddr3.v index c0236f1..1b1077e 100644 --- a/rtl/DDR3 SDRAM Verilog Model/ddr3.v +++ b/rtl/DDR3 SDRAM Verilog Model/ddr3.v @@ -1440,7 +1440,7 @@ module ddr3 ( end if (DEBUG) begin $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr); - $display("\n\nprev_cmd=%s, prev_time=%0d ps, difference=%0d ps\n\n", prev_cmd,prev_time, $time-prev_time); + $display("\tprev_cmd=%s, prev_time=%0d ps, difference=%0d ps", prev_cmd,prev_time, $time-prev_time); prev_time = $time; prev_cmd = cmd_string[cmd]; @@ -1506,7 +1506,7 @@ module ddr3 ( end if (DEBUG) begin $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]); - $display("\n\nprev_cmd=%s, prev_time=%0d ps, difference=%0d ps\n\n", prev_cmd,prev_time, $time-prev_time); + $display("\tprev_cmd=%s, prev_time=%0d ps, difference=%0d ps", prev_cmd,prev_time, $time-prev_time); prev_time = $time; prev_cmd = cmd_string[cmd]; end @@ -1566,7 +1566,7 @@ module ddr3 ( end if (DEBUG) begin $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]); - $display("\n\nprev_cmd=%s, prev_time=%0d ps, difference=%0d ps\n\n", prev_cmd,prev_time, $time-prev_time); + $display("\tprev_cmd=%s, prev_time=%0d ps, difference=%0d ps", prev_cmd,prev_time, $time-prev_time); prev_time = $time; prev_cmd = cmd_string[cmd]; end