diff --git a/testbench/ARTY_S7/arty_ddr3.v b/testbench/ARTY_S7/arty_ddr3.v index 0156710..242e225 100644 --- a/testbench/ARTY_S7/arty_ddr3.v +++ b/testbench/ARTY_S7/arty_ddr3.v @@ -2,7 +2,8 @@ module arty_ddr3 ( - input wire i_clk, i_rst, + input wire i_clk, + input wire i_rst, // DDR3 I/O Interface output wire ddr3_clk_p, ddr3_clk_n, output wire ddr3_reset_n, @@ -13,15 +14,15 @@ output wire ddr3_we_n, // WE# output wire[14-1:0] ddr3_addr, output wire[3-1:0] ddr3_ba, - inout wire[(8*2)-1:0] ddr3_dq, - inout wire[(8*2)/8-1:0] ddr3_dqs_p, ddr3_dqs_n, + inout wire[16-1:0] ddr3_dq, + inout wire[2-1:0] ddr3_dqs_p, ddr3_dqs_n, output wire[2-1:0] ddr3_dm, output wire ddr3_odt, // on-die termination // UART line input wire rx, output wire tx, //Debug LEDs - output wire[2:0] led + output wire[3:0] led ); wire i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90; @@ -35,13 +36,15 @@ wire o_wb_stall; reg i_wb_stb = 0, i_wb_we; wire[63:0] o_debug1; - reg[7:0] i_wb_addr, i_wb_data; - assign led[0] = (o_debug1[5:1] == 12); - assign led[1] = (o_debug1[5:1] == 13); - assign led[2] = (o_debug1[5:1] == 14); //light up if at DONE_CALIBRATE + reg[7:0] i_wb_data; + reg[7:0] i_wb_addr; + assign led[0] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE + assign led[1] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE + assign led[2] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE + assign led[3] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE - always @(posedge i_controller_clk) begin + always @(posedge i_controller_clk) begin begin i_wb_stb <= 0; i_wb_we <= 0; @@ -51,104 +54,48 @@ if(rd_data >= 97 && rd_data <= 122) begin //write i_wb_stb <= 1; i_wb_we <= 1; - i_wb_addr <= rd_data; + i_wb_addr <= ~rd_data ; i_wb_data <= rd_data; end else if(rd_data >= 65 && rd_data <= 90) begin //read i_wb_stb <= 1; //make request i_wb_we <= 0; //read - i_wb_addr <= rd_data + 8'd32; + i_wb_addr <= ~(rd_data + 8'd32); end - /* - case(rd_data) - 97: begin //a - i_wb_stb <= 1; - i_wb_we <= 1; - i_wb_addr <= 0; - i_wb_data <= 8'h31; //write "1" - end - 98: begin //b - i_wb_stb <= 1; //make request - i_wb_we <= 0; //read - i_wb_addr <= 0; - end - 99: begin //c - i_wb_stb <= 1; - i_wb_we <= 1; - i_wb_addr <= 1; - i_wb_data <= 8'h32; //write "2" - end - 100: begin //d - i_wb_stb <= 1; //make request - i_wb_we <= 0; //read - i_wb_addr <= 1; - end - 101: begin //e - i_wb_stb <= 1; - i_wb_we <= 1; - i_wb_addr <= 2; - i_wb_data <= 8'h39; //write "9" - end - 102: begin //f - i_wb_stb <= 1; //make request - i_wb_we <= 0; //read - i_wb_addr <= 2; - end - endcase - */ - end + end end - end + end - - wire clk_locked; - clk_wiz_0 clk_wiz_inst - ( - // Clock out ports - .clk_out1(i_controller_clk), //83.333 Mhz - .clk_out2(i_ddr3_clk), // 333.333 MHz - .clk_out3(i_ref_clk), //200MHz - .clk_out4(i_ddr3_clk_90), - // Status and control signals - .reset(i_rst), - .locked(clk_locked), - // Clock in ports - .clk_in1(i_clk) - ); - - /* - uart #(.DBIT(8),.SB_TICK(16),.DVSR(638),.DVSR_WIDTH(10),.FIFO_W(2)) m0 //DBIT=databits , SB_TICK=stop_bits tick(16 per bit) , DVSR= clk/(16*BaudRate) , DVSR_WIDTH=array size needed by DVSR,FIFO_WIDTH+fifo size(2^x) ) - ( - .clk(i_controller_clk), - .rst_n(!i_rst), - .rd_uart(!rx_empty), - .wr_uart(o_wb_ack && !o_aux), - .wr_data(o_wb_data), - .rx(rx), - .tx(tx), - .rd_data(rd_data), - .rx_empty(rx_empty), - .tx_full(tx_full) + (* mark_debug = "true" *) wire clk_locked; + clk_wiz_0 clk_wiz_inst + ( + // Clock out ports + .clk_out1(i_controller_clk), //83.333 Mhz + .clk_out2(i_ddr3_clk), // 333.333 MHz + .clk_out3(i_ref_clk), //200MHz + .clk_out4(i_ddr3_clk_90), + // Status and control signals + .reset(i_rst), + .locked(clk_locked), + // Clock in ports + .clk_in1(i_clk) ); - */ - -uart #(.DATA_WIDTH(8)) uart_m -( - .clk(i_controller_clk), - .rst(i_rst), - .s_axis_tdata(o_wb_data), - .s_axis_tvalid(o_wb_ack), - .s_axis_tready(), - .m_axis_tdata(rd_data), - .m_axis_tvalid(m_axis_tvalid), - .m_axis_tready(1), - .rxd(rx), - .txd(tx), - .prescale(1085) -); - - + uart #(.DATA_WIDTH(8)) uart_m + ( + .clk(i_controller_clk), + .rst(i_rst), + .s_axis_tdata(o_wb_data), + .s_axis_tvalid(o_wb_ack), + .s_axis_tready(), + .m_axis_tdata(rd_data), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(1), + .rxd(rx), + .txd(tx), + .prescale(1085) //9600 Baud Rate + ); + // DDR3 Controller ddr3_top #( @@ -165,7 +112,8 @@ uart #(.DATA_WIDTH(8)) uart_m .WB2_DATA_BITS(32), .OPT_LOWPOWER(1), //1 = low power, 0 = low logic .OPT_BUS_ABORT(1), //1 = can abort bus, 0 = no absort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction) - .MICRON_SIM(0) //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW) + .MICRON_SIM(0), //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW) + .TEST_DATAMASK(1) //add test to datamask during calibration ) ddr3_top ( //clock and reset @@ -173,7 +121,7 @@ uart #(.DATA_WIDTH(8)) uart_m .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD .i_ref_clk(i_ref_clk), .i_ddr3_clk_90(i_ddr3_clk_90), - .i_rst_n(!i_rst || clk_locked), + .i_rst_n(!i_rst && clk_locked), // Wishbone inputs .i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled) .i_wb_stb(i_wb_stb), //request a transfer @@ -218,20 +166,5 @@ uart #(.DATA_WIDTH(8)) uart_m .o_debug1(o_debug1) //////////////////////////////////// ); - /* - ila_0 m_ila( - .clk(i_, - .probe0(clk_locked), - .probe1(i_rst), - .probe2, - .probe3, - .probe4, - .probe5, - .probe6, - .probe7, - .probe8 - );*/ - - endmodule