104 lines
3.6 KiB
Coq
104 lines
3.6 KiB
Coq
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`default_nettype none
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`timescale 1ns / 1ps
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module spd_reader (
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// clock and reset
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input wire i_clk,
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input wire i_rst_n,
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// i2c interface
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inout wire i2c_scl,
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inout wire i2c_sda
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// uart interface
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// input uart_rx,
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// output uart_tx
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);
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// byte 2: DRAM Device Type (DDR3 SDRAM = 0x0B)
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// byte 3: Module Type (SO-DIMM = 0x03)
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// byte 4: SDRAM Density and Banks ([6:4] = BA_BITS, [3:0] = SDRAM capacity)
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// byte 5: SDRAM Addressing ([5:3] = Row Addr , [2:0] = Column Addr)
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// byte 7: Module Organization ([5:3] = Ranks , Device Width = [2:0])
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// byte 8: Module Memory Bus Width ([2:0] = Bus Width)
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// byte 10,11: Medium Timebase (MTB) Dividend (0x01), Medium Timebase (MTB) Divisor (0x08 = 0.125ns , 0x10 = 0.0625ns) (tXX = tXX(MTB) * MTB)
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// byte 12: SDRAM Minimum Cycle Time tCK
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localparam I2C_ADDRESS = 7'h30;
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localparam IDLE = 0,
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READ_ADDRESS = 1,
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WAIT_ACK = 2;
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(* mark_debug = "true" *) reg[1:0] state_find_i2c_address;
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(* mark_debug = "true" *) reg find_i2c_address_done;
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(* mark_debug = "true" *) reg[6:0] i2c_address;
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// i2c master interface
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reg enable;
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reg read_write;
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reg[7:0] register_address;
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reg[6:0] device_address;
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wire[7:0] miso_data;
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wire busy;
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wire slave_nack;
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always @(posedge i_clk, negedge i_rst_n) begin
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if(!i_rst_n) begin
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state_find_i2c_address <= IDLE;
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find_i2c_address_done <= 0;
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enable <= 1'b0;
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read_write <= 1'b0;
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register_address <= 8'd0;
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i2c_address <= 7'd0;
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end
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else begin
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// Find I2C Address of SPD
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case(state_find_i2c_address)
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IDLE: if(!find_i2c_address_done) begin
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state_find_i2c_address <= READ_ADDRESS;
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i2c_address <= 7'd0;
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end
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READ_ADDRESS: if(!busy) begin
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enable <= 1'b1;
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read_write <= 1'b1; // read i2c
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register_address <= 8'h00; // just always read byte 0
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device_address <= i2c_address;
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state_find_i2c_address <= WAIT_ACK;
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end
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WAIT_ACK: if(!busy && !enable) begin
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if(slave_nack) begin // if wrong i2c_address
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i2c_address <= i2c_address + 1; // increment i2c address
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state_find_i2c_address <= READ_ADDRESS;
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end
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else begin // I2C acks so i2c_address is correct!
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state_find_i2c_address <= IDLE;
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find_i2c_address_done <= 1'b1;
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end
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end
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else begin
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enable <= 1'b0;
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end
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endcase
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end
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end
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// module instantiations
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i2c_master #(.DATA_WIDTH(8),.REGISTER_WIDTH(8),.ADDRESS_WIDTH(7))
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i2c_master_inst(
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.clock (i_clk),
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.reset_n (i_rst_n),
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.enable (enable),
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.read_write (read_write),
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.mosi_data (8'd0),
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.register_address (register_address),
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.device_address (device_address),
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.divider (249), // 100MHz/(4*(249+1)) = 100KHz
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.miso_data (miso_data),
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.busy (busy),
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.external_serial_data (i2c_sda),
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.external_serial_clock (i2c_scl),
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.slave_nack (slave_nack)
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);
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endmodule
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