[tasks]
prf2lanes_83MHz   prf  opt_2lanes   opt_83MHz   opt_with_ODELAY
prf4lanes_83MHz   prf  opt_4lanes   opt_83MHz   opt_with_ODELAY
prf8lanes_83MHz   prf  opt_8lanes   opt_83MHz   opt_with_ODELAY  opt_WB_ERR
prf2lanes_100MHz  prf  opt_2lanes   opt_100MHz  opt_with_ODELAY  opt_WB_ERR
prf4lanes_100MHz  prf  opt_4lanes   opt_100MHz  opt_with_ODELAY
prf8lanes_100MHz  prf  opt_8lanes   opt_100MHz  opt_with_ODELAY
prf_no_ODELAY     prf  opt_8lanes   opt_100MHz                 

[options]
prf: mode prove
prf: depth  7

[engines]
prf: smtbmc

[script]
read -formal ddr3_controller.v
read -formal fwb_slave.v

--pycode-begin--

# Number of Lanes
if "opt_2lanes" in  tags:
    cmd = "chparam -set LANES 2 ddr3_controller\n"
elif "opt_4lanes" in tags:
    cmd = "chparam -set LANES 4 ddr3_controller\n"
elif "opt_8lanes" in tags:
    cmd = "chparam -set LANES 8 ddr3_controller\n"
else:
    cmd = "chparam -set LANES 8 ddr3_controller\n"

# Clock period
if "opt_83MHz" in tags:
    cmd += "chparam -set CONTROLLER_CLK_PERIOD 12000 ddr3_controller\n"
    cmd += "chparam -set DDR3_CLK_PERIOD 3000 ddr3_controller\n"
elif "opt_100MHz" in tags:
    cmd += "chparam -set CONTROLLER_CLK_PERIOD 10000 ddr3_controller\n"
    cmd += "chparam -set DDR3_CLK_PERIOD 2500 ddr3_controller\n"
else:
    cmd += "chparam -set CONTROLLER_CLK_PERIOD 10000 ddr3_controller\n"
    cmd += "chparam -set DDR3_CLK_PERIOD 2500 ddr3_controller\n"

# ODELAY support
if "opt_with_ODELAY" in tags:
    cmd += "chparam -set ODELAY_SUPPORTED 1 ddr3_controller\n"
else:
    cmd += "chparam -set ODELAY_SUPPORTED 0 ddr3_controller\n"

# Wishbone Error
if "opt_WB_ERR" in  tags:
    cmd += "chparam -set WB_ERROR 1 ddr3_controller\n"
else:
    cmd += "chparam -set WB_ERROR 0 ddr3_controller\n"

output(cmd)
--pycode-end--

prep -top ddr3_controller

[files]
./rtl/ddr3_controller.v
./formal/fwb_slave.v

