ddr3_controller.v,verilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
ddr3_phy.v,verilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
ddr3_top.v,verilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
ddr3.v,systemverilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
ddr3_dimm.v,systemverilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
ddr3_dimm_micron_sim.v,systemverilog,xil_defaultlib,/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v,incdir="/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/rtl"incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"
glbl.v,Verilog,xil_defaultlib,/home/angelo/incdir="/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench"/glbl.v
