--- find_timing_paths endpoint_path_count 5 --- epc 5 paths: 14 reg1/RN slack=9.553728474998024e-9 reg2/RN slack=9.553728474998024e-9 out1 slack=7.881454600067173e-9 out2 slack=7.885596176038234e-9 out1 slack=7.892997366809595e-9 out2 slack=7.895866183105227e-9 out3 slack=7.914771948946964e-9 out3 slack=7.92035237395794e-9 reg1/D slack=8.91273987946306e-9 reg1/D slack=8.91496121369073e-9 reg1/D slack=8.922569350033882e-9 reg1/D slack=8.923859873277706e-9 reg2/D slack=9.865935624020494e-9 reg2/D slack=9.875192219510609e-9 PASS: endpoint_path_count 5 --- find_timing_paths endpoint_path_count 3 group_path_count 10 --- epc 3 gpc 10: 12 PASS: epc 3 gpc 10 --- find_timing_paths min endpoint_path_count 5 --- min epc 5: 14 reg1/RN slack=3.1855806881253557e-10 reg2/RN slack=3.1855806881253557e-10 reg2/D slack=8.220570058004029e-11 reg2/D slack=9.451981558550315e-11 reg1/D slack=1.0395115879191508e-9 reg1/D slack=1.0408024442298824e-9 reg1/D slack=1.0431400188082307e-9 reg1/D slack=1.0453613530359007e-9 out3 slack=2.0796477873119557e-9 out3 slack=2.0852275461891168e-9 out2 slack=2.1041333120308536e-9 out1 slack=2.107002128326485e-9 out2 slack=2.114403319097846e-9 out1 slack=2.118544895068908e-9 PASS: min epc 5 --- find_timing_paths endpoint_path_count 1 --- epc 1: 7 PASS: epc 1 --- -unique_paths_to_endpoint epc 3 --- unique epc 3: 8 PASS: unique epc --- -unique_edges_to_endpoint epc 3 --- unique_edges epc 3: 13 PASS: unique_edges epc --- -sort_by_slack endpoint_path_count 5 --- sorted epc 5: 14 Sorted correctly: 0 PASS: sort_by_slack epc PASS: group_path setup --- find_timing_paths grouped epc 5 --- grouped epc 5: 14 PASS: grouped epc --- report_checks epc 3 -fields --- Warning: search_path_enum_deep.tcl line 1, unknown field nets. Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.89 0.00 0.00 1.00 v in2 (in) 0.00 0.00 1.00 v and1/A2 (AND2_X1) 1 0.88 0.01 0.02 1.02 v and1/ZN (AND2_X1) 0.01 0.00 1.02 v buf1/A (BUF_X1) 1 1.05 0.01 0.02 1.05 v buf1/Z (BUF_X1) 0.01 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time ----------------------------------------------------------------------------- 9.96 data required time -1.05 data arrival time ----------------------------------------------------------------------------- 8.91 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 1 0.87 0.00 0.00 1.00 v in1 (in) 0.00 0.00 1.00 v and1/A1 (AND2_X1) 1 0.88 0.01 0.02 1.02 v and1/ZN (AND2_X1) 0.01 0.00 1.02 v buf1/A (BUF_X1) 1 1.05 0.01 0.02 1.05 v buf1/Z (BUF_X1) 0.01 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time ----------------------------------------------------------------------------- 9.96 data required time -1.05 data arrival time ----------------------------------------------------------------------------- 8.91 slack (MET) Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 1 0.97 0.00 0.00 1.00 ^ in2 (in) 0.00 0.00 1.00 ^ and1/A2 (AND2_X1) 1 0.97 0.01 0.03 1.03 ^ and1/ZN (AND2_X1) 0.01 0.00 1.03 ^ buf1/A (BUF_X1) 1 1.13 0.01 0.02 1.05 ^ buf1/Z (BUF_X1) 0.01 0.00 1.05 ^ reg1/D (DFFR_X1) 1.05 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.03 9.97 library setup time 9.97 data required time ----------------------------------------------------------------------------- 9.97 data required time -1.05 data arrival time ----------------------------------------------------------------------------- 8.92 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: out_grp Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.01 0.00 0.10 ^ buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.00 0.12 ^ out1 (out) 0.12 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time ----------------------------------------------------------------------------- 8.00 data required time -0.12 data arrival time ----------------------------------------------------------------------------- 7.88 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: out_grp Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg2/CK (DFFR_X1) 1 0.97 0.01 0.10 0.10 ^ reg2/Q (DFFR_X1) 0.01 0.00 0.10 ^ buf3/A (BUF_X1) 1 0.00 0.00 0.02 0.11 ^ buf3/Z (BUF_X1) 0.00 0.00 0.11 ^ out2 (out) 0.11 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time ----------------------------------------------------------------------------- 8.00 data required time -0.11 data arrival time ----------------------------------------------------------------------------- 7.89 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: out_grp Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1) 0.01 0.00 0.08 v buf2/A (BUF_X1) 1 0.00 0.00 0.02 0.11 v buf2/Z (BUF_X1) 0.00 0.00 0.11 v out1 (out) 0.11 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time ----------------------------------------------------------------------------- 8.00 data required time -0.11 data arrival time ----------------------------------------------------------------------------- 7.89 slack (MET) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 2 3.56 0.00 0.00 0.50 ^ rst (in) 0.00 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time ----------------------------------------------------------------------------- 10.05 data required time -0.50 data arrival time ----------------------------------------------------------------------------- 9.55 slack (MET) Startpoint: rst (input port clocked by clk) Endpoint: reg2 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 2 3.56 0.00 0.00 0.50 ^ rst (in) 0.00 0.00 0.50 ^ reg2/RN (DFFR_X1) 0.50 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time ----------------------------------------------------------------------------- 10.05 data required time -0.50 data arrival time ----------------------------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.01 0.00 0.10 ^ reg2/D (DFFR_X1) 0.10 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFFR_X1) -0.03 9.97 library setup time 9.97 data required time ----------------------------------------------------------------------------- 9.97 data required time -0.10 data arrival time ----------------------------------------------------------------------------- 9.87 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1) 0.01 0.00 0.08 v reg2/D (DFFR_X1) 0.08 data arrival time 0.00 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time ----------------------------------------------------------------------------- 9.96 data required time -0.08 data arrival time ----------------------------------------------------------------------------- 9.88 slack (MET) PASS: report epc fields --- report_checks epc 3 -format end --- max_delay/setup group in_grp Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg1/D (DFFR_X1) 9.96 1.05 8.91 (MET) reg1/D (DFFR_X1) 9.96 1.05 8.91 (MET) reg1/D (DFFR_X1) 9.97 1.05 8.92 (MET) max_delay/setup group out_grp Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 8.00 0.12 7.88 (MET) out2 (output) 8.00 0.11 7.89 (MET) out1 (output) 8.00 0.11 7.89 (MET) max_delay/setup group asynchronous Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg1/RN (DFFR_X1) 10.05 0.50 9.55 (MET) reg2/RN (DFFR_X1) 10.05 0.50 9.55 (MET) max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ reg2/D (DFFR_X1) 9.97 0.10 9.87 (MET) reg2/D (DFFR_X1) 9.96 0.08 9.88 (MET) PASS: report epc end --- report_checks epc 3 -format summary --- Startpoint Endpoint Slack -------------------------------------------------------------------------------- in2 (input) reg1/D (DFFR_X1) 8.91 in1 (input) reg1/D (DFFR_X1) 8.91 in2 (input) reg1/D (DFFR_X1) 8.92 reg1/Q (search_path_end_types) out1 (output) 7.88 reg2/Q (search_path_end_types) out2 (output) 7.89 reg1/Q (search_path_end_types) out1 (output) 7.89 rst (input) reg1/RN (DFFR_X1) 9.55 rst (input) reg2/RN (DFFR_X1) 9.55 reg1/Q (DFFR_X1) reg2/D (DFFR_X1) 9.87 reg1/Q (DFFR_X1) reg2/D (DFFR_X1) 9.88 PASS: report epc summary --- report_checks min epc 3 --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.92 0.00 0.00 1.00 ^ in1 (in) 0.97 0.01 0.02 1.02 ^ and1/ZN (AND2_X1) 1.13 0.01 0.02 1.04 ^ buf1/Z (BUF_X1) 0.01 0.00 1.04 ^ reg1/D (DFFR_X1) 1.04 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFFR_X1) 0.00 0.00 library hold time 0.00 data required time ----------------------------------------------------------------------- 0.00 data required time -1.04 data arrival time ----------------------------------------------------------------------- 1.04 slack (MET) Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.97 0.00 0.00 1.00 ^ in2 (in) 0.97 0.01 0.03 1.03 ^ and1/ZN (AND2_X1) 1.13 0.01 0.02 1.05 ^ buf1/Z (BUF_X1) 0.01 0.00 1.05 ^ reg1/D (DFFR_X1) 1.05 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFFR_X1) 0.00 0.00 library hold time 0.00 data required time ----------------------------------------------------------------------- 0.00 data required time -1.05 data arrival time ----------------------------------------------------------------------- 1.04 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.87 0.00 0.00 1.00 v in1 (in) 0.88 0.01 0.02 1.02 v and1/ZN (AND2_X1) 1.05 0.01 0.02 1.05 v buf1/Z (BUF_X1) 0.01 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFFR_X1) 0.00 0.00 library hold time 0.00 data required time ----------------------------------------------------------------------- 0.00 data required time -1.05 data arrival time ----------------------------------------------------------------------- 1.04 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: out_grp Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.97 0.01 0.06 0.06 ^ reg1/QN (DFFR_X1) 0.00 0.00 0.02 0.08 ^ buf4/Z (BUF_X1) 0.00 0.00 0.08 ^ out3 (out) 0.08 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time ----------------------------------------------------------------------- -2.00 data required time -0.08 data arrival time ----------------------------------------------------------------------- 2.08 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out3 (output port clocked by clk) Path Group: out_grp Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.88 0.01 0.06 0.06 v reg1/QN (DFFR_X1) 0.00 0.00 0.02 0.09 v buf4/Z (BUF_X1) 0.00 0.00 0.09 v out3 (out) 0.09 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time ----------------------------------------------------------------------- -2.00 data required time -0.09 data arrival time ----------------------------------------------------------------------- 2.09 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: out_grp Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg2/CK (DFFR_X1) 0.88 0.01 0.08 0.08 v reg2/Q (DFFR_X1) 0.00 0.00 0.02 0.10 v buf3/Z (BUF_X1) 0.00 0.00 0.10 v out2 (out) 0.10 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism -2.00 -2.00 output external delay -2.00 data required time ----------------------------------------------------------------------- -2.00 data required time -0.10 data arrival time ----------------------------------------------------------------------- 2.10 slack (MET) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (removal check against rising-edge clock clk) Path Group: asynchronous Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 3.56 0.00 0.00 0.50 ^ rst (in) 0.00 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFFR_X1) 0.18 0.18 library removal time 0.18 data required time ----------------------------------------------------------------------- 0.18 data required time -0.50 data arrival time ----------------------------------------------------------------------- 0.32 slack (MET) Startpoint: rst (input port clocked by clk) Endpoint: reg2 (removal check against rising-edge clock clk) Path Group: asynchronous Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 3.56 0.00 0.00 0.50 ^ rst (in) 0.00 0.00 0.50 ^ reg2/RN (DFFR_X1) 0.50 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFFR_X1) 0.18 0.18 library removal time 0.18 data required time ----------------------------------------------------------------------- 0.18 data required time -0.50 data arrival time ----------------------------------------------------------------------- 0.32 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 1.93 0.01 0.08 0.08 v reg1/Q (DFFR_X1) 0.01 0.00 0.08 v reg2/D (DFFR_X1) 0.08 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFFR_X1) 0.00 0.00 library hold time 0.00 data required time ----------------------------------------------------------------------- 0.00 data required time -0.08 data arrival time ----------------------------------------------------------------------- 0.08 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Cap Slew Delay Time Description ----------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 0.00 ^ reg1/CK (DFFR_X1) 2.10 0.01 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.01 0.00 0.10 ^ reg2/D (DFFR_X1) 0.10 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFFR_X1) 0.01 0.01 library hold time 0.01 data required time ----------------------------------------------------------------------- 0.01 data required time -0.10 data arrival time ----------------------------------------------------------------------- 0.09 slack (MET) PASS: min epc report --- report_checks epc 3 -from -to --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFFR_X1) 1.04 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -1.04 data arrival time --------------------------------------------------------- 8.92 slack (MET) PASS: epc from/to --- report_checks epc 3 -through --- Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in2 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: in_grp Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in2 (in) 0.03 1.03 ^ and1/ZN (AND2_X1) 0.02 1.05 ^ buf1/Z (BUF_X1) 0.00 1.05 ^ reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.03 9.97 library setup time 9.97 data required time --------------------------------------------------------- 9.97 data required time -1.05 data arrival time --------------------------------------------------------- 8.92 slack (MET) PASS: epc through --- find_timing_paths -path_delay max_rise --- max_rise paths: 8 PASS: max_rise --- find_timing_paths -path_delay max_fall --- max_fall paths: 6 PASS: max_fall --- find_timing_paths -path_delay min_rise --- min_rise paths: 8 PASS: min_rise --- find_timing_paths -path_delay min_fall --- min_fall paths: 6 PASS: min_fall --- find_timing_paths -path_delay min_max --- min_max paths: 20 PASS: min_max --- find_timing_paths epc 10 gpc 50 --- big epc: 14 PASS: big epc --- slack_max filtering --- slack <= 0: 0 slack <= 100: 13 PASS: slack_max --- slack_min filtering --- slack >= -100: 13 PASS: slack_min ALL PASSED