Release 2.0 Patches
-------------------
2018/10/23 spash msg embedded quotes seg fault
2018/10/23 read_verilog mod inst with no ports seg fault
2018/11/08 corners > 2 causes internal error
2018/11/09 Verilog ignore attributes (* blah *)
2018/12/24 all_fanout from input port
2018/12/25 liberty pg_types
2019/01/03 liberty 2D bus names
2019/01/07 WritePathSpice don't barf on spice subckts missing liberty cells
2019/01/15 generated clk -divide_by 16384 cycle accting
2019/01/18 write_path_spice ground coupling caps
2019/01/18 write_path_spice do not write zero caps
2019/01/19 write_path_spice tie-offs for demorgan'd nand/nor functs
2019/01/29 write_sdc set_driving_cell omit -library if missing from sdc
2019/01/31 generated clk -divide_by 16384 cycle accting fallout
2019/02/17 report_power internal power accuracy
2019/02/18 write_path_spice first line is comment
2019/02/21 write_path_spice include side load pins