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# Created by write_sdc
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current_design sdc_test2
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# Timing Constraints
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create_clock -name clk1 -period 10.0000 [get_ports {clk1}]
create_clock -name clk2 -period 20.0000 [get_ports {clk2}]
create_clock -name vclk -period 8.0000 
create_clock -name clk1_2x -add -period 5.0000 [get_ports {clk1}]
create_clock -name clk_asym -add -period 12.0000 -waveform {0.0000 3.0000} [get_ports {clk2}]
create_generated_clock -name gclk_div2 -source [get_ports {clk1}] -divide_by 2 [get_pins {reg1/Q}]
set_clock_transition 0.1200 [get_clocks {gclk_div2}]
set_clock_uncertainty -setup 0.1500 gclk_div2
set_clock_uncertainty -hold 0.0800 gclk_div2
set_propagated_clock [get_clocks {gclk_div2}]
create_generated_clock -name gclk_div3 -source [get_ports {clk2}] -divide_by 3 [get_pins {reg3/Q}]
create_generated_clock -name gclk_mul2 -source [get_ports {clk1}] -multiply_by 2 [get_pins {reg2/Q}]
set_clock_transition -rise -max 0.1500 [get_clocks {gclk_mul2}]
set_clock_latency 0.1500 [get_clocks {gclk_div3}]
set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {gclk_div2}]  -setup 0.2000
set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {gclk_div2}]  -setup 0.2000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {gclk_div2}]  -setup 0.2000
set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {gclk_div2}]  -setup 0.2000
set_clock_uncertainty -rise_from [get_clocks {gclk_div2}] -rise_to [get_clocks {clk2}]  -hold 0.1000
set_clock_uncertainty -rise_from [get_clocks {gclk_div2}] -fall_to [get_clocks {clk2}]  -hold 0.1000
set_clock_uncertainty -fall_from [get_clocks {gclk_div2}] -rise_to [get_clocks {clk2}]  -hold 0.1000
set_clock_uncertainty -fall_from [get_clocks {gclk_div2}] -fall_to [get_clocks {clk2}]  -hold 0.1000
set_clock_groups -name genclk_async -asynchronous \
 -group [list [get_clocks {clk2}]\
           [get_clocks {gclk_div3}]]\
 -group [list [get_clocks {clk1}]\
           [get_clocks {clk1_2x}]\
           [get_clocks {gclk_div2}]\
           [get_clocks {gclk_mul2}]]
set_input_delay 3.0000 -clock [get_clocks {gclk_div2}] -add_delay [get_ports {in1}]
set_input_delay 3.5000 -clock [get_clocks {gclk_div2}] -rise -max -add_delay [get_ports {in2}]
set_input_delay 1.5000 -clock [get_clocks {gclk_div2}] -fall -min -add_delay [get_ports {in2}]
set_output_delay 2.0000 -clock [get_clocks {gclk_mul2}] -add_delay [get_ports {out1}]
set_output_delay 2.5000 -clock [get_clocks {gclk_div3}] -add_delay [get_ports {out2}]
set_multicycle_path -setup\
    -from [get_clocks {clk1}]\
    -to [get_clocks {gclk_div2}] 3
set_false_path\
    -from [get_clocks {gclk_div2}]\
    -to [get_clocks {gclk_div3}]
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# Environment
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# Design Rules
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