--- Test 1: write with -remove_cells ---
cells: 2
basic size=194 empty remove size=194
Warning: verilog_remove_cells_basic.tcl line 1, object 'NangateOpenCellLibrary/BUF_X1' not found.
remove BUF_X1 size=194
Warning: verilog_remove_cells_basic.tcl line 1, object 'NangateOpenCellLibrary/DFF_X1' not found.
remove DFF_X1 size=194
Warning: verilog_remove_cells_basic.tcl line 1, object 'NangateOpenCellLibrary/BUF_X1' not found.
Warning: verilog_remove_cells_basic.tcl line 1, object 'NangateOpenCellLibrary/DFF_X1' not found.
remove both size=194
Warning: verilog_remove_cells_basic.tcl line 1, object 'NangateOpenCellLibrary/BUF_X1' not found.
remove+pwr size=194
--- Test 4: read back removed cells ---
Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
roundtrip (buf removed) cells: 2
Warning: ../../test/nangate45/Nangate45_typ.lib line 37, library NangateOpenCellLibrary already exists.
roundtrip basic cells: 2
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in1 (in)
   0.06    0.06 v buf1/Z (BUF_X1)
   0.00    0.06 v reg1/D (DFF_X1)
           0.06   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg1/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.06   data arrival time
---------------------------------------------------------
           9.90   slack (MET)