--- query cells --- cells count: 2 --- query nets --- nets count: 5 --- query pins --- pins count: 12 --- query ports --- ports count: 4 --- create_clock --- --- report_checks --- Startpoint: reset (input port clocked by clk) Endpoint: _1415_ (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ reset (in) 0.00 0.00 ^ _1415_/RESET_B (sky130_fd_sc_hd__dfrtp_1) 0.00 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.23 10.23 library recovery time 10.23 data required time --------------------------------------------------------- 10.23 data required time -0.00 data arrival time --------------------------------------------------------- 10.23 slack (MET) Startpoint: _1415_ (rising edge-triggered flip-flop clocked by clk) Endpoint: _1416_[0] (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.33 0.33 v _1415_/Q (sky130_fd_sc_hd__dfrtp_1) 0.00 0.33 v _1416_[0]/D (sky130_fd_sc_hd__dfrtp_1) 0.33 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ _1416_[0]/CLK (sky130_fd_sc_hd__dfrtp_1) -0.12 9.88 library setup time 9.88 data required time --------------------------------------------------------- 9.88 data required time -0.33 data arrival time --------------------------------------------------------- 9.55 slack (MET) --- report_checks -path_delay min --- Startpoint: reset (input port clocked by clk) Endpoint: _1415_ (removal check against rising-edge clock clk) Path Group: asynchronous Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ reset (in) 0.00 0.00 ^ _1415_/RESET_B (sky130_fd_sc_hd__dfrtp_1) 0.00 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.30 0.30 library removal time 0.30 data required time --------------------------------------------------------- 0.30 data required time -0.00 data arrival time --------------------------------------------------------- -0.30 slack (VIOLATED) Startpoint: in (input port clocked by clk) Endpoint: _1415_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ input external delay 0.00 0.00 ^ in (in) 0.00 0.00 ^ _1415_/D (sky130_fd_sc_hd__dfrtp_1) 0.00 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1) -0.03 -0.03 library hold time -0.03 data required time --------------------------------------------------------- -0.03 data required time -0.00 data arrival time --------------------------------------------------------- 0.03 slack (MET) --- get_cells with filter --- dfrtp cells count: 2 --- report_instance for first cell --- Instance _1415_ Cell: sky130_fd_sc_hd__dfrtp_1 Library: sky130_fd_sc_hd__tt_025C_1v80 Path cells: sky130_fd_sc_hd__dfrtp_1 Input pins: CLK input clk D input in RESET_B input reset Output pins: Q output mid Other pins: IQ internal (unconnected) IQ_N internal (unconnected) VGND ground (unconnected) VNB unknown (unconnected) VPB unknown (unconnected) VPWR power (unconnected) --- report_net mid --- Net mid Pin capacitance: 0.00-0.00 Wire capacitance: 0.00 Total capacitance: 0.00-0.00 Number of drivers: 1 Number of loads: 1 Number of pins: 2 Driver pins _1415_/Q output (sky130_fd_sc_hd__dfrtp_1) Load pins _1416_[0]/D input (sky130_fd_sc_hd__dfrtp_1) 0.00-0.00 --- all_inputs --- all_inputs count: 3 --- all_outputs --- all_outputs count: 1 --- all_clocks --- all_clocks count: 1