Warning: ../../examples/gcd_sky130hd.v line 527, module sky130_fd_sc_hd__tapvpwrvgnd_1 not found. Creating black box for TAP_11.
PASS: design loaded with SPEF
Startpoint: _414_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _418_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _414_/CLK (sky130_fd_sc_hd__dfxtp_4)
   0.32    0.32 v _414_/Q (sky130_fd_sc_hd__dfxtp_4)
   0.12    0.45 v _214_/Y (sky130_fd_sc_hd__nor2b_4)
   0.32    0.77 v _215_/X (sky130_fd_sc_hd__maj3_2)
   0.32    1.10 v _216_/X (sky130_fd_sc_hd__maj3_2)
   0.36    1.46 v _217_/X (sky130_fd_sc_hd__maj3_2)
   0.38    1.83 v _218_/X (sky130_fd_sc_hd__maj3_2)
   0.40    2.23 v _219_/X (sky130_fd_sc_hd__maj3_2)
   0.25    2.48 ^ _222_/Y (sky130_fd_sc_hd__o211ai_4)
   0.16    2.63 v _225_/Y (sky130_fd_sc_hd__a311oi_4)
   0.34    2.97 ^ _228_/Y (sky130_fd_sc_hd__o311ai_4)
   0.17    3.14 v _231_/Y (sky130_fd_sc_hd__a311oi_4)
   0.43    3.58 v _292_/X (sky130_fd_sc_hd__o311a_2)
   0.72    4.30 ^ _295_/Y (sky130_fd_sc_hd__o31ai_4)
   0.37    4.66 ^ split1/X (sky130_fd_sc_hd__buf_4)
   0.11    4.78 v _316_/Y (sky130_fd_sc_hd__a221oi_1)
   0.00    4.78 v _418_/D (sky130_fd_sc_hd__dfxtp_1)
           4.78   data arrival time

   5.00    5.00   clock clk (rise edge)
   0.00    5.00   clock network delay (ideal)
   0.00    5.00   clock reconvergence pessimism
           5.00 ^ _418_/CLK (sky130_fd_sc_hd__dfxtp_1)
  -0.16    4.84   library setup time
           4.84   data required time
---------------------------------------------------------
           4.84   data required time
          -4.78   data arrival time
---------------------------------------------------------
           0.06   slack (MET)


PASS: timing analysis
Startpoint: _412_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _412_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ _412_/CLK (sky130_fd_sc_hd__dfxtp_1)
   0.30    0.30 ^ _412_/Q (sky130_fd_sc_hd__dfxtp_1)
   0.12    0.42 ^ _290_/X (sky130_fd_sc_hd__a32o_1)
   0.00    0.42 ^ _412_/D (sky130_fd_sc_hd__dfxtp_1)
           0.42   data arrival time

   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00   clock reconvergence pessimism
           0.00 ^ _412_/CLK (sky130_fd_sc_hd__dfxtp_1)
  -0.04   -0.04   library hold time
          -0.04   data required time
---------------------------------------------------------
          -0.04   data required time
          -0.42   data arrival time
---------------------------------------------------------
           0.45   slack (MET)


PASS: min path analysis
unique cells: 57
Warning: spice_gcd_path.tcl line 1, port '*' not found.
PASS: SPICE subckt file created for 57 cells
--- write_path_spice max ngspice ---
PASS: write_path_spice max completed
--- write_path_spice min ---
PASS: write_path_spice min completed
--- write_path_spice hspice ---
PASS: write_path_spice hspice completed
--- write_path_spice xyce ---
PASS: write_path_spice xyce completed
--- write_path_spice specific endpoints ---
INFO: write_path_spice specific: Error: spice_gcd_path.tcl line 1, No paths found for -path_args -from req_msg[0] -to resp_msg[0].
PASS: code path exercised
--- write_gate_spice sky130hd cells ---
Warning: spice_gcd_path.tcl line 1, instance '_300_' not found.
INFO: gate sky130_fd_sc_hd__xnor2_1 (_197_): invalid command name "write_gate_spice_cmd"
PASS: gate code path exercised
INFO: gate sky130_fd_sc_hd__inv_1 (_205_): invalid command name "write_gate_spice_cmd"
PASS: gate code path exercised
INFO: gate sky130_fd_sc_hd__nand2_2 (_206_): invalid command name "write_gate_spice_cmd"
PASS: gate code path exercised
PASS: write_gate_spice cells tested: 3
ALL PASSED