--- report_checks baseline ---
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   1.00    1.00 v input external delay
   0.00    1.00 v in1 (in)
   0.06    1.06 v buf1/Z (BUF_X1)
   0.00    1.06 v reg1/D (DFF_X1)
           1.06   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg1/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -1.06   data arrival time
---------------------------------------------------------
           8.90   slack (MET)


PASS: timing analysis completed
PASS: mock SPICE files created
--- write_gate_spice ngspice ---
INFO: write_gate_spice ngspice: invalid command name "write_gate_spice_cmd"
PASS: write_gate_spice ngspice code path exercised
--- write_gate_spice fall ---
INFO: write_gate_spice fall: invalid command name "write_gate_spice_cmd"
PASS: write_gate_spice fall code path exercised
--- write_gate_spice xyce ---
INFO: write_gate_spice xyce: invalid command name "write_gate_spice_cmd"
PASS: write_gate_spice xyce code path exercised
--- write_gate_spice hspice ---
INFO: write_gate_spice hspice: invalid command name "write_gate_spice_cmd"
PASS: write_gate_spice hspice code path exercised
--- write_path_spice max slack ---
PASS: write_path_spice max slack completed
--- write_path_spice min path ---
PASS: write_path_spice min completed
--- write_path_spice hspice ---
PASS: write_path_spice hspice completed
--- write_path_spice xyce ---
PASS: write_path_spice xyce completed
ALL PASSED