--- set_logic_zero in1 --- in1=0 and1/A1=0 Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: clk_gate (rising clock gating-check end-point clocked by clk) Path Group: gated clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ en (in) 0.00 1.00 ^ clk_gate/A2 (AND2_X1) 1.00 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ clk_gate/A1 (AND2_X1) 0.00 10.00 clock gating setup time 10.00 data required time --------------------------------------------------------- 10.00 data required time -1.00 data arrival time --------------------------------------------------------- 9.00 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: logic_zero in1 --- set_logic_zero in2 --- in2=0 and1/A2=0 and1/ZN=0 Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: en (input port clocked by clk) Endpoint: clk_gate (rising clock gating-check end-point clocked by clk) Path Group: gated clock Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ en (in) 0.00 1.00 ^ clk_gate/A2 (AND2_X1) 1.00 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ clk_gate/A1 (AND2_X1) 0.00 10.00 clock gating setup time 10.00 data required time --------------------------------------------------------- 10.00 data required time -1.00 data arrival time --------------------------------------------------------- 9.00 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: logic_zero both --- set_logic_one en --- en=1: clk_gate/A2=1 gated_clk=X Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: logic_one en --- set_logic_one in1 (overwrite) --- in1=1 and1/A1=1 and1/ZN=0 (in1=1,in2=0 -> 0) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: logic_one overwrite --- case_analysis 0 on en --- Warning: propagated logic value 1 differs from constraint value of 0 on pin en. en=0: gated_clk=0 Startpoint: rst (input port clocked by clk) Endpoint: reg2 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg2/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg2/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFFR_X1) 0.10 0.10 ^ reg2/Q (DFFR_X1) 0.02 0.11 ^ buf3/Z (BUF_X1) 0.00 0.11 ^ out2 (out) 0.11 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.11 data arrival time --------------------------------------------------------- 7.89 slack (MET) PASS: case 0 en --- case_analysis 1 on en --- en=1: gated_clk=X Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: case 1 en --- case_analysis rising on rst --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: case rising rst --- case_analysis falling on rst --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: case falling rst --- Constant propagation via case_analysis --- Warning: propagated logic value 1 differs from constraint value of 0 on pin in1. in1=0,in2=0: and1/ZN=0 inv1/ZN=1 Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: constant propagation --- levelize --- PASS: levelize --- report_loops --- PASS: report_loops --- set_propagated_clock --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (propagated) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.02 10.02 clock network delay (propagated) 0.00 10.02 clock reconvergence pessimism 10.02 ^ reg1/CK (DFFR_X1) 0.06 10.08 library recovery time 10.08 data required time --------------------------------------------------------- 10.08 data required time -0.50 data arrival time --------------------------------------------------------- 9.58 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.02 0.02 clock network delay (propagated) 0.00 0.02 ^ reg1/CK (DFFR_X1) 0.10 0.13 ^ reg1/Q (DFFR_X1) 0.02 0.15 ^ buf2/Z (BUF_X1) 0.00 0.15 ^ out1 (out) 0.15 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (propagated) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.15 data arrival time --------------------------------------------------------- 7.85 slack (MET) PASS: propagated clock --- report_clock_skew after propagation --- Clock clk 0.02 source latency reg1/CK ^ 0.00 target latency reg2/CK ^ 0.00 CRPR -------------- 0.02 setup skew Clock clk 0.02 source latency reg1/CK ^ 0.00 target latency reg2/CK ^ 0.00 CRPR -------------- 0.02 hold skew PASS: clock skew propagated --- unset_propagated_clock --- PASS: unset propagated --- set_clock_latency -source --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.20 0.20 clock network delay (ideal) 0.50 0.70 ^ input external delay 0.00 0.70 ^ rst (in) 0.00 0.70 ^ reg1/RN (DFFR_X1) 0.70 data arrival time 10.00 10.00 clock clk (rise edge) 0.20 10.20 clock network delay (ideal) 0.00 10.20 clock reconvergence pessimism 10.20 ^ reg1/CK (DFFR_X1) 0.05 10.25 library recovery time 10.25 data required time --------------------------------------------------------- 10.25 data required time -0.70 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.20 0.20 clock network delay (ideal) 0.00 0.20 ^ reg1/CK (DFFR_X1) 0.10 0.30 ^ reg1/Q (DFFR_X1) 0.02 0.32 ^ buf2/Z (BUF_X1) 0.00 0.32 ^ out1 (out) 0.32 data arrival time 10.00 10.00 clock clk (rise edge) 0.20 10.20 clock network delay (ideal) 0.00 10.20 clock reconvergence pessimism -2.00 8.20 output external delay 8.20 data required time --------------------------------------------------------- 8.20 data required time -0.32 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: clock latency source --- set_clock_latency (network) --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.30 0.30 clock network delay (ideal) 0.50 0.80 ^ input external delay 0.00 0.80 ^ rst (in) 0.00 0.80 ^ reg1/RN (DFFR_X1) 0.80 data arrival time 10.00 10.00 clock clk (rise edge) 0.30 10.30 clock network delay (ideal) 0.00 10.30 clock reconvergence pessimism 10.30 ^ reg1/CK (DFFR_X1) 0.05 10.35 library recovery time 10.35 data required time --------------------------------------------------------- 10.35 data required time -0.80 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.30 0.30 clock network delay (ideal) 0.00 0.30 ^ reg1/CK (DFFR_X1) 0.10 0.40 ^ reg1/Q (DFFR_X1) 0.02 0.42 ^ buf2/Z (BUF_X1) 0.00 0.42 ^ out1 (out) 0.42 data arrival time 10.00 10.00 clock clk (rise edge) 0.30 10.30 clock network delay (ideal) 0.00 10.30 clock reconvergence pessimism -2.00 8.30 output external delay 8.30 data required time --------------------------------------------------------- 8.30 data required time -0.42 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: clock latency network --- unset_clock_latency --- PASS: unset clock latency --- set_clock_latency -source -rise --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.15 0.15 clock network delay (ideal) 0.50 0.65 ^ input external delay 0.00 0.65 ^ rst (in) 0.00 0.65 ^ reg1/RN (DFFR_X1) 0.65 data arrival time 10.00 10.00 clock clk (rise edge) 0.15 10.15 clock network delay (ideal) 0.00 10.15 clock reconvergence pessimism 10.15 ^ reg1/CK (DFFR_X1) 0.05 10.20 library recovery time 10.20 data required time --------------------------------------------------------- 10.20 data required time -0.65 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.15 0.15 clock network delay (ideal) 0.00 0.15 ^ reg1/CK (DFFR_X1) 0.10 0.25 ^ reg1/Q (DFFR_X1) 0.02 0.27 ^ buf2/Z (BUF_X1) 0.00 0.27 ^ out1 (out) 0.27 data arrival time 10.00 10.00 clock clk (rise edge) 0.15 10.15 clock network delay (ideal) 0.00 10.15 clock reconvergence pessimism -2.00 8.15 output external delay 8.15 data required time --------------------------------------------------------- 8.15 data required time -0.27 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: clock latency rise --- set_clock_latency -source -fall --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.15 0.15 clock network delay (ideal) 0.50 0.65 ^ input external delay 0.00 0.65 ^ rst (in) 0.00 0.65 ^ reg1/RN (DFFR_X1) 0.65 data arrival time 10.00 10.00 clock clk (rise edge) 0.15 10.15 clock network delay (ideal) 0.00 10.15 clock reconvergence pessimism 10.15 ^ reg1/CK (DFFR_X1) 0.05 10.20 library recovery time 10.20 data required time --------------------------------------------------------- 10.20 data required time -0.65 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.15 0.15 clock network delay (ideal) 0.00 0.15 ^ reg1/CK (DFFR_X1) 0.10 0.25 ^ reg1/Q (DFFR_X1) 0.02 0.27 ^ buf2/Z (BUF_X1) 0.00 0.27 ^ out1 (out) 0.27 data arrival time 10.00 10.00 clock clk (rise edge) 0.15 10.15 clock network delay (ideal) 0.00 10.15 clock reconvergence pessimism -2.00 8.15 output external delay 8.15 data required time --------------------------------------------------------- 8.15 data required time -0.27 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: clock latency fall --- unset --- PASS: unset clock insertion --- set_clock_uncertainty --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) -0.50 9.50 clock uncertainty 0.00 9.50 clock reconvergence pessimism 9.50 ^ reg1/CK (DFFR_X1) 0.05 9.55 library recovery time 9.55 data required time --------------------------------------------------------- 9.55 data required time -0.50 data arrival time --------------------------------------------------------- 9.05 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) -0.50 9.50 clock uncertainty 0.00 9.50 clock reconvergence pessimism -2.00 7.50 output external delay 7.50 data required time --------------------------------------------------------- 7.50 data required time -0.12 data arrival time --------------------------------------------------------- 7.38 slack (MET) PASS: clock uncertainty --- set_clock_uncertainty -setup --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) -0.30 9.70 clock uncertainty 0.00 9.70 clock reconvergence pessimism 9.70 ^ reg1/CK (DFFR_X1) 0.05 9.75 library recovery time 9.75 data required time --------------------------------------------------------- 9.75 data required time -0.50 data arrival time --------------------------------------------------------- 9.25 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) -0.30 9.70 clock uncertainty 0.00 9.70 clock reconvergence pessimism -2.00 7.70 output external delay 7.70 data required time --------------------------------------------------------- 7.70 data required time -0.12 data arrival time --------------------------------------------------------- 7.58 slack (MET) PASS: clock uncertainty setup --- set_clock_uncertainty -hold --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (removal check against rising-edge clock clk) Path Group: asynchronous Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.20 0.20 clock uncertainty 0.00 0.20 clock reconvergence pessimism 0.20 ^ reg1/CK (DFFR_X1) 0.18 0.38 library removal time 0.38 data required time --------------------------------------------------------- 0.38 data required time -0.50 data arrival time --------------------------------------------------------- 0.12 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.08 0.08 v reg1/Q (DFFR_X1) 0.00 0.08 v reg2/D (DFFR_X1) 0.08 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.20 0.20 clock uncertainty 0.00 0.20 clock reconvergence pessimism 0.20 ^ reg2/CK (DFFR_X1) 0.00 0.20 library hold time 0.20 data required time --------------------------------------------------------- 0.20 data required time -0.08 data arrival time --------------------------------------------------------- -0.12 slack (VIOLATED) PASS: clock uncertainty hold --- unset_clock_uncertainty --- PASS: unset clock uncertainty --- set_max_time_borrow --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: max_time_borrow --- set_min_pulse_width --- PASS: set min pulse width --- report_pulse_width_checks after setting --- Required Actual Pin Width Width Slack ------------------------------------------------------------ reg1/CK (high) 0.06 5.00 4.94 (MET) reg2/CK (high) 0.06 5.00 4.94 (MET) reg2/CK (low) 0.05 5.00 4.95 (MET) reg1/CK (low) 0.05 5.00 4.95 (MET) PASS: pulse width after set --- report_constant --- Warning: propagated logic value 1 differs from constraint value of 0 on pin in1. in1 0 case=0 logic=1 VDD X VSS X A1 0 A2 0 ZN 0 PASS: report_constant --- set_disable_timing port --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: disable port --- set_disable_timing instance --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: disable instance --- CRPR settings --- crpr_enabled: 1 crpr_mode: same_pin Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) crpr_mode: same_transition Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: CRPR settings --- recovery/removal checks --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: recovery/removal --- gated clock checks --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: gated clock checks --- timing_derate --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.11 0.11 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.08 0.08 v reg1/Q (DFFR_X1) 0.00 0.08 v reg2/D (DFFR_X1) 0.08 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 ^ reg2/CK (DFFR_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.08 data arrival time --------------------------------------------------------- 0.08 slack (MET) PASS: timing derate --- tag/group reporting --- tag_count: 0 tag_group_count: 0 clk_info_count: 0 path_count: 0 PASS: tag/group counts --- report internal --- Longest hash bucket length 0 hash=0 0 clk infos Longest hash bucket length 0 hash=0 PASS: internal reports ALL PASSED