--- report_checks max through latch --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- PASS: max path delay with latch --- report_checks min through latch --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch1/G (DLH_X1) 0.05 0.05 ^ latch1/Q (DLH_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.05 slack (MET) PASS: min path delay with latch --- report_checks min_max --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch1/G (DLH_X1) 0.05 0.05 ^ latch1/Q (DLH_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.05 slack (MET) Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- PASS: min_max path delay with latch --- report_checks full_clock through latch --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- PASS: full_clock format with latch --- report_checks full_clock_expanded through latch --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- PASS: full_clock_expanded with latch --- report_checks to latch output --- No paths found. PASS: path to latch output --- report_checks from latch output --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch1/G (DLH_X1) 0.06 0.06 v latch1/Q (DLH_X1) 0.00 0.06 v latch2/D (DLH_X1) 0.06 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 0.06 0.06 time borrowed from endpoint 0.06 data required time --------------------------------------------------------- 0.06 data required time -0.06 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 0.06 -------------------------------------------- PASS: path from latch output --- report_check_types with latch --- Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ latch1/G (DLH_X1) 0.05 0.05 ^ latch1/Q (DLH_X1) 0.00 0.05 ^ reg1/D (DFF_X1) 0.05 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.01 0.01 library hold time 0.01 data required time --------------------------------------------------------- 0.01 data required time -0.05 data arrival time --------------------------------------------------------- 0.05 slack (MET) Startpoint: latch1 (positive level-sensitive latch clocked by clk) Endpoint: latch2 (positive level-sensitive latch clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.05 1.05 time given to startpoint 0.00 1.05 v latch1/D (DLH_X1) 0.06 1.11 v latch1/Q (DLH_X1) 0.00 1.11 v latch2/D (DLH_X1) 1.11 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ latch2/G (DLH_X1) 1.11 1.11 time borrowed from endpoint 1.11 data required time --------------------------------------------------------- 1.11 data required time -1.11 data arrival time --------------------------------------------------------- 0.00 slack (MET) Time Borrowing Information -------------------------------------------- clk pulse width 5.00 library setup time -0.05 -------------------------------------------- max time borrow 4.95 actual time borrow 1.11 -------------------------------------------- max slew Pin latch1/Q v max slew 0.20 slew 0.01 ---------------- Slack 0.19 (MET) max capacitance Pin latch1/Q ^ max capacitance 60.58 capacitance 2.05 ----------------------- Slack 58.52 (MET) Pin: reg1/CK Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 reg1/CK 0.00 open edge arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 reg1/CK 0.00 5.00 clock reconvergence pessimism 5.00 close edge arrival time --------------------------------------------------------- 0.05 required pulse width (high) 5.00 actual pulse width --------------------------------------------------------- 4.95 slack (MET) PASS: check_types with latch --- check_setup with latch --- PASS: check_setup with latch --- report_clock_skew --- Clock clk 0.00 source latency latch1/G ^ 0.00 target latency latch2/G v 0.00 CRPR -------------- 0.00 setup skew Clock clk 0.00 source latency latch1/G ^ 0.00 target latency latch2/G v 0.00 CRPR -------------- 0.00 hold skew PASS: clock_skew with latch --- report_clock_latency --- Clock clk rise -> rise min max 0.00 0.00 source latency 0.00 network latency latch1/G 0.00 network latency latch1/G --------------- 0.00 0.00 latency 0.00 skew fall -> fall min max 0.00 0.00 source latency 0.00 network latency latch1/G 0.00 network latency latch1/G --------------- 0.00 0.00 latency 0.00 skew PASS: clock_latency with latch --- report_pulse_width_checks --- Pin: reg1/CK Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 reg1/CK 0.00 open edge arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 reg1/CK 0.00 5.00 clock reconvergence pessimism 5.00 close edge arrival time --------------------------------------------------------- 0.05 required pulse width (high) 5.00 actual pulse width --------------------------------------------------------- 4.95 slack (MET) Pin: reg1/CK Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 reg1/CK 5.00 open edge arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 reg1/CK 0.00 10.00 clock reconvergence pessimism 10.00 close edge arrival time --------------------------------------------------------- 0.05 required pulse width (low) 5.00 actual pulse width --------------------------------------------------------- 4.95 slack (MET) Pin: latch1/G Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 latch1/G 0.00 open edge arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 latch1/G 0.00 5.00 clock reconvergence pessimism 5.00 close edge arrival time --------------------------------------------------------- 0.04 required pulse width (high) 5.00 actual pulse width --------------------------------------------------------- 4.96 slack (MET) Pin: latch2/G Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 latch2/G 0.00 open edge arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 latch2/G 0.00 5.00 clock reconvergence pessimism 5.00 close edge arrival time --------------------------------------------------------- 0.04 required pulse width (high) 5.00 actual pulse width --------------------------------------------------------- 4.96 slack (MET) PASS: pulse_width_checks with latch --- find_timing_paths through latch --- Found 5 paths path to latch2/D slack=0.0 path to latch2/D slack=0.0 path to latch1/D slack=0.0 path to latch1/D slack=0.0 path to latch1/D slack=0.0 PASS: find_timing_paths with latch --- all_registers with latch --- Register cells: 3 latch1 latch2 reg1 Level-sensitive cells: 2 Edge-triggered cells: 1 Data pins: 3 Clock pins: 3 Output pins: 4 PASS: all_registers with latch --- report_tns/report_wns with latch --- tns max 0.00 wns max 0.00 worst slack max 0.00 worst slack min 0.05 PASS: tns/wns with latch ALL PASSED