--- report_checks -format json (multiple endpoints) --- {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.900e-09 }, { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 7.722e-11, "capacitance": 8.752e-16, "slew": 5.624e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 7.722e-11, "slew": 5.624e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 9.857e-11, "capacitance": 0.000e+00, "slew": 3.903e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 9.857e-11, "slew": 3.903e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 9.857e-11, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.901e-09 }, { "type": "check", "path_group": "clk", "path_type": "max", "startpoint": "in2", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in2", "arrival": 1.000e-09, "capacitance": 8.941e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A2", "net": "in2", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.025e-09, "capacitance": 8.752e-16, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.025e-09, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.048e-09, "capacitance": 1.062e-15, "slew": 5.011e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.048e-09, "slew": 5.011e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.048e-09, "crpr": 0.000e+00, "margin": 3.878e-11, "required_time": 9.961e-09, "slack": 8.913e-09 }, { "type": "check", "path_group": "clk", "path_type": "max", "startpoint": "in1", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in1", "arrival": 1.000e-09, "capacitance": 8.748e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A1", "net": "in1", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.022e-09, "capacitance": 8.752e-16, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.022e-09, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.046e-09, "capacitance": 1.062e-15, "slew": 5.011e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.046e-09, "slew": 5.011e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.046e-09, "crpr": 0.000e+00, "margin": 3.878e-11, "required_time": 9.961e-09, "slack": 8.915e-09 }, { "type": "check", "path_group": "clk", "path_type": "max", "startpoint": "in2", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in2", "arrival": 1.000e-09, "capacitance": 9.746e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A2", "net": "in2", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.026e-09, "capacitance": 9.747e-16, "slew": 7.001e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.026e-09, "slew": 7.001e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.045e-09, "capacitance": 1.140e-15, "slew": 5.947e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.045e-09, "slew": 5.947e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.045e-09, "crpr": 0.000e+00, "margin": 3.073e-11, "required_time": 9.969e-09, "slack": 8.924e-09 } ] } PASS: json format multi-endpoint --- report_checks -format json min --- {"checks": [ { "type": "check", "path_group": "clk", "path_type": "min", "startpoint": "in1", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in1", "arrival": 1.000e-09, "capacitance": 9.181e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A1", "net": "in1", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.024e-09, "capacitance": 9.747e-16, "slew": 7.000e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.024e-09, "slew": 7.000e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.044e-09, "capacitance": 1.140e-15, "slew": 5.947e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.044e-09, "slew": 5.947e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.044e-09, "crpr": -0.000e+00, "margin": 4.894e-12, "required_time": 4.894e-12, "slack": 1.039e-09 } ] } PASS: json format min --- report_checks -format json min_max --- {"checks": [ { "type": "check", "path_group": "clk", "path_type": "min", "startpoint": "in1", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in1", "arrival": 1.000e-09, "capacitance": 9.181e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A1", "net": "in1", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.024e-09, "capacitance": 9.747e-16, "slew": 7.000e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.024e-09, "slew": 7.000e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.044e-09, "capacitance": 1.140e-15, "slew": 5.947e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.044e-09, "slew": 5.947e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.044e-09, "crpr": -0.000e+00, "margin": 4.894e-12, "required_time": 4.894e-12, "slack": 1.039e-09 }, { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.900e-09 } ] } PASS: json format min_max --- report_checks -format json to specific pin --- {"checks": [ { "type": "check", "path_group": "clk", "path_type": "max", "startpoint": "in2", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in2", "arrival": 1.000e-09, "capacitance": 8.941e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A2", "net": "in2", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.025e-09, "capacitance": 8.752e-16, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.025e-09, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.048e-09, "capacitance": 1.062e-15, "slew": 5.011e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.048e-09, "slew": 5.011e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.048e-09, "crpr": 0.000e+00, "margin": 3.878e-11, "required_time": 9.961e-09, "slack": 8.913e-09 } ] } PASS: json format to specific pin --- report_checks -format json from specific port --- {"checks": [ { "type": "check", "path_group": "clk", "path_type": "max", "startpoint": "in1", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in1", "arrival": 1.000e-09, "capacitance": 8.748e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A1", "net": "in1", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.022e-09, "capacitance": 8.752e-16, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.022e-09, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.046e-09, "capacitance": 1.062e-15, "slew": 5.011e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.046e-09, "slew": 5.011e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.046e-09, "crpr": 0.000e+00, "margin": 3.878e-11, "required_time": 9.961e-09, "slack": 8.915e-09 } ] } PASS: json format from port --- report_checks -format json through pin --- {"checks": [ { "type": "check", "path_group": "clk", "path_type": "max", "startpoint": "in2", "endpoint": "reg1/D", "source_clock": "clk", "source_clock_edge": "rise", "source_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in2", "arrival": 1.000e-09, "capacitance": 8.941e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A2", "net": "in2", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.025e-09, "capacitance": 8.752e-16, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.025e-09, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.048e-09, "capacitance": 1.062e-15, "slew": 5.011e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.048e-09, "slew": 5.011e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "target_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "data_arrival_time": 1.048e-09, "crpr": 0.000e+00, "margin": 3.878e-11, "required_time": 9.961e-09, "slack": 8.913e-09 } ] } PASS: json format through pin --- report_checks -unconstrained format full --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) PASS: unconstrained full format --- report_checks -unconstrained format short --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max PASS: unconstrained short format --- report_checks -unconstrained format end --- max_delay/setup group clk Required Actual Endpoint Delay Delay Slack ------------------------------------------------------------ out1 (output) 8.00 0.10 7.90 (MET) PASS: unconstrained end format --- report_checks -unconstrained format slack_only --- Group Slack -------------------------------------------- clk 7.90 PASS: unconstrained slack_only format --- report_path on individual path (json format) --- { "path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ] } { "path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 7.722e-11, "capacitance": 8.752e-16, "slew": 5.624e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 7.722e-11, "slew": 5.624e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 9.857e-11, "capacitance": 0.000e+00, "slew": 3.903e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 9.857e-11, "slew": 3.903e-12 } ] } { "path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "in2", "arrival": 1.000e-09, "capacitance": 8.941e-16, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/A2", "net": "in2", "arrival": 1.000e-09, "slew": 0.000e+00 }, { "instance": "and1", "cell": "AND2_X1", "verilog_src": "", "pin": "and1/ZN", "net": "n1", "arrival": 1.025e-09, "capacitance": 8.752e-16, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/A", "net": "n1", "arrival": 1.025e-09, "slew": 5.258e-12 }, { "instance": "buf1", "cell": "BUF_X1", "verilog_src": "", "pin": "buf1/Z", "net": "n2", "arrival": 1.048e-09, "capacitance": 1.062e-15, "slew": 5.011e-12 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/D", "net": "n2", "arrival": 1.048e-09, "slew": 5.011e-12 } ] } PASS: report_path_cmd json multi --- reportPathFull on a single path --- PASS: report_path full --- json report with full_clock format (for source clock paths) --- {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.900e-09 } ] } PASS: json with clock info --- report_checks -format json -sort_by_slack --- {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.900e-09 } ] } PASS: json sort_by_slack --- report_checks min with fields --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 1 0.92 0.00 0.00 1.00 ^ in1 (in) in1 (net) 0.00 0.00 1.00 ^ and1/A1 (AND2_X1) 1 0.97 0.01 0.02 1.02 ^ and1/ZN (AND2_X1) n1 (net) 0.01 0.00 1.02 ^ buf1/A (BUF_X1) 1 1.14 0.01 0.02 1.04 ^ buf1/Z (BUF_X1) n2 (net) 0.01 0.00 1.04 ^ reg1/D (DFF_X1) 1.04 data arrival time 0.00 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time ----------------------------------------------------------------------------- 0.00 data required time -1.04 data arrival time ----------------------------------------------------------------------------- 1.04 slack (MET) PASS: min with all fields --- report_checks with -digits --- {"checks": [ { "type": "output_delay", "path_group": "clk", "path_type": "max", "startpoint": "reg1/Q", "endpoint": "out1", "source_clock": "clk", "source_clock_edge": "rise", "source_clock_path": [ { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "clk", "arrival": 0.000e+00, "capacitance": 9.497e-16, "slew": 0.000e+00 }, { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/CK", "net": "clk", "arrival": 0.000e+00, "slew": 0.000e+00 } ], "source_path": [ { "instance": "reg1", "cell": "DFF_X1", "verilog_src": "", "pin": "reg1/Q", "net": "n3", "arrival": 8.371e-11, "capacitance": 9.747e-16, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/A", "net": "n3", "arrival": 8.371e-11, "slew": 7.314e-12 }, { "instance": "buf2", "cell": "BUF_X1", "verilog_src": "", "pin": "buf2/Z", "net": "out1", "arrival": 1.003e-10, "capacitance": 0.000e+00, "slew": 3.638e-12 }, { "instance": "", "cell": "search_test1", "verilog_src": "", "pin": "out1", "arrival": 1.003e-10, "slew": 3.638e-12 } ], "target_clock": "clk", "target_clock_edge": "rise", "data_arrival_time": 1.003e-10, "crpr": 0.000e+00, "margin": 2.000e-09, "required_time": 8.000e-09, "slack": 7.900e-09 } ] } PASS: json digits 6 ALL PASSED