--- set_false_path -from port -to pin --- No paths found. PASS: false_path from/to --- remove false path --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) PASS: remove false_path --- set_false_path -through --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: false_path through --- remove false_path through --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: remove false_path through --- set_false_path -setup --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: false_path setup --- remove false_path setup --- PASS: remove false_path setup --- set_false_path -hold --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (removal check against rising-edge clock clk) Path Group: asynchronous Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFFR_X1) 0.18 0.18 library removal time 0.18 data required time --------------------------------------------------------- 0.18 data required time -0.50 data arrival time --------------------------------------------------------- 0.32 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.08 0.08 v reg1/Q (DFFR_X1) 0.00 0.08 v reg2/D (DFFR_X1) 0.08 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFFR_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.08 data arrival time --------------------------------------------------------- 0.08 slack (MET) PASS: false_path hold --- remove false_path hold --- PASS: remove false_path hold --- set_multicycle_path 2 -setup --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 20.00 20.00 clock clk (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg1/CK (DFFR_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -1.05 data arrival time --------------------------------------------------------- 18.91 slack (MET) PASS: multicycle setup 2 --- set_multicycle_path 1 -hold --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFFR_X1) 1.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFFR_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.04 data arrival time --------------------------------------------------------- 1.04 slack (MET) PASS: multicycle hold 1 --- set_multicycle_path 3 -setup with -through --- Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in2 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 30.00 30.00 clock clk (rise edge) 0.00 30.00 clock network delay (ideal) 0.00 30.00 clock reconvergence pessimism 30.00 ^ reg1/CK (DFFR_X1) -0.04 29.96 library setup time 29.96 data required time --------------------------------------------------------- 29.96 data required time -1.05 data arrival time --------------------------------------------------------- 28.91 slack (MET) PASS: multicycle setup 3 through --- remove multicycle through --- PASS: remove multicycle through --- set_max_delay --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 5.00 5.00 max_delay 0.00 5.00 clock reconvergence pessimism -0.04 4.96 library setup time 4.96 data required time --------------------------------------------------------- 4.96 data required time -1.05 data arrival time --------------------------------------------------------- 3.91 slack (MET) PASS: max_delay --- set_min_delay --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFFR_X1) 1.04 data arrival time 0.10 0.10 min_delay 0.00 0.10 clock reconvergence pessimism 0.00 0.10 library hold time 0.10 data required time --------------------------------------------------------- 0.10 data required time -1.04 data arrival time --------------------------------------------------------- 0.94 slack (MET) PASS: min_delay --- remove max/min delay --- Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: remove max/min delay --- set_max_delay -through --- Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in2 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) PASS: max_delay through --- remove max_delay through --- PASS: remove max_delay through --- group_path -name from_in1 --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: from_in1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: group_path from --- group_path -name to_out1 --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: from_in1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: to_out1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFFR_X1) 0.10 0.10 ^ reg2/Q (DFFR_X1) 0.02 0.11 ^ buf3/Z (BUF_X1) 0.00 0.11 ^ out2 (out) 0.11 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.11 data arrival time --------------------------------------------------------- 7.89 slack (MET) PASS: group_path to --- group_path -name through_buf --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: from_in1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) Startpoint: in2 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: through_buf Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in2 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: to_out1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) Startpoint: rst (input port clocked by clk) Endpoint: reg1 (recovery check against rising-edge clock clk) Path Group: asynchronous Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.50 0.50 ^ input external delay 0.00 0.50 ^ rst (in) 0.00 0.50 ^ reg1/RN (DFFR_X1) 0.50 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) 0.05 10.05 library recovery time 10.05 data required time --------------------------------------------------------- 10.05 data required time -0.50 data arrival time --------------------------------------------------------- 9.55 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk) Endpoint: out2 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFFR_X1) 0.10 0.10 ^ reg2/Q (DFFR_X1) 0.02 0.11 ^ buf3/Z (BUF_X1) 0.00 0.11 ^ out2 (out) 0.11 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.11 data arrival time --------------------------------------------------------- 7.89 slack (MET) PASS: group_path through --- report_checks -path_group --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: from_in1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in1 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) 1.05 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism 10.00 ^ reg1/CK (DFFR_X1) -0.04 9.96 library setup time 9.96 data required time --------------------------------------------------------- 9.96 data required time -1.05 data arrival time --------------------------------------------------------- 8.91 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: to_out1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFFR_X1) 0.10 0.10 ^ reg1/Q (DFFR_X1) 0.02 0.12 ^ buf2/Z (BUF_X1) 0.00 0.12 ^ out1 (out) 0.12 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.12 data arrival time --------------------------------------------------------- 7.88 slack (MET) PASS: report_checks path_group --- path_group_names --- Path group names: clk from_in1 through_buf to_out1 asynchronous {path delay} {gated clock} unconstrained PASS: path_group_names --- report_check_types -max_delay --- Group Slack -------------------------------------------- from_in1 8.91 through_buf 8.91 to_out1 7.88 clk 7.89 PASS: report_check_types max_delay --- report_check_types -min_delay --- Group Slack -------------------------------------------- from_in1 1.04 through_buf 1.04 to_out1 2.11 clk 0.08 PASS: report_check_types min_delay --- report_check_types -recovery --- Group Slack -------------------------------------------- asynchronous 9.55 PASS: report_check_types recovery --- report_check_types -removal --- Group Slack -------------------------------------------- asynchronous 0.32 PASS: report_check_types removal --- report_check_types -max_delay -min_delay together --- Group Slack -------------------------------------------- from_in1 1.04 through_buf 1.04 to_out1 2.11 clk 0.08 from_in1 8.91 through_buf 8.91 to_out1 7.88 clk 7.89 PASS: report_check_types max+min --- report_check_types -recovery -removal --- Group Slack -------------------------------------------- asynchronous 0.32 asynchronous 9.55 PASS: report_check_types recovery+removal --- report_check_types -clock_gating_setup --- Group Slack -------------------------------------------- No paths found. PASS: report_check_types clk_gating_setup --- report_check_types -clock_gating_hold --- Group Slack -------------------------------------------- No paths found. PASS: report_check_types clk_gating_hold --- report_check_types -clock_gating_setup -clock_gating_hold --- Group Slack -------------------------------------------- No paths found. PASS: report_check_types clk_gating both --- report_check_types -min_pulse_width --- Required Actual Pin Width Width Slack ------------------------------------------------------------ reg1/CK (high) 0.06 5.00 4.94 (MET) PASS: report_check_types mpw --- report_check_types -min_period --- PASS: report_check_types min_period --- report_check_types -max_skew --- PASS: report_check_types max_skew --- report_check_types -max_slew --- max slew Pin Limit Slew Slack ------------------------------------------------------------ reg1/Q 0.20 0.01 0.19 (MET) PASS: report_check_types max_slew --- report_check_types -max_capacitance --- max capacitance Pin Limit Cap Slack ------------------------------------------------------------ reg1/Q 60.58 2.10 58.47 (MET) PASS: report_check_types max_cap --- report_check_types -max_fanout --- PASS: report_check_types max_fanout --- report_check_types -violators --- Group Slack -------------------------------------------- No paths found. PASS: report_check_types violators --- report_check_types -violators -verbose --- No paths found. PASS: report_check_types violators verbose --- worst_clock_skew -setup --- worst_clock_skew setup: 0.0 PASS: worst_clock_skew setup --- worst_clock_skew -hold --- worst_clock_skew hold: 0.0 PASS: worst_clock_skew hold --- total_negative_slack -max --- tns max: 0.0 PASS: tns max --- total_negative_slack -min --- tns min: 0.0 PASS: tns min --- worst_slack -max --- worst_slack max: 7.881454822969938 PASS: worst_slack max --- worst_slack -min --- worst_slack min: 0.08220570290497634 PASS: worst_slack min --- worst_negative_slack -max --- wns max: 0.0 PASS: wns_max --- endpoint_slack --- endpoint_slack out1 clk max: Inf PASS: endpoint_slack --- report_path -min --- Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFFR_X1) PASS: report_path min --- report_path -max --- Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 v input external delay 0.00 1.00 v in2 (in) 0.02 1.02 v and1/ZN (AND2_X1) 0.02 1.05 v buf1/Z (BUF_X1) 0.00 1.05 v reg1/D (DFFR_X1) PASS: report_path max --- report_arrival --- (clk ^) r 1.04:1.05 f 1.05:1.05 PASS: report_arrival --- report_required --- (clk ^) r 0.00:9.97 f 0.00:9.96 PASS: report_required --- report_slack --- (clk ^) r 1.04:8.92 f 1.04:8.91 PASS: report_slack ALL PASSED