--- check_setup all flags --- Warning: There are 2 input ports missing set_input_delay. in3 in_unconst Warning: There is 1 output port missing set_output_delay. out_unconst Warning: There are 2 unconstrained endpoints. out_unconst reg3/D PASS: check_setup verbose --- check_setup -no_input_delay --- Warning: There are 2 input ports missing set_input_delay. in3 in_unconst PASS: check_setup no_input_delay --- check_setup -no_output_delay --- Warning: There is 1 output port missing set_output_delay. out_unconst PASS: check_setup no_output_delay --- check_setup -no_clock --- PASS: check_setup no_clock --- check_setup -unconstrained_endpoints --- Warning: There are 2 unconstrained endpoints. out_unconst reg3/D PASS: check_setup unconstrained_endpoints --- check_setup -loops --- PASS: check_setup loops --- check_setup -generated_clocks --- PASS: check_setup generated_clocks --- check_setup multiple flags combined --- Warning: There are 2 input ports missing set_input_delay. in3 in_unconst Warning: There is 1 output port missing set_output_delay. out_unconst Warning: There are 2 unconstrained endpoints. out_unconst reg3/D PASS: check_setup combined flags --- report_check_types all --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFF_X1) 1.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.04 data arrival time --------------------------------------------------------- 1.04 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 v reg1/Q (DFF_X1) 0.00 0.08 v reg2/D (DFF_X1) 0.08 data arrival time 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg2/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -0.08 data arrival time --------------------------------------------------------- 0.08 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) max slew Pin reg1/QN v max slew 0.20 slew 0.01 ---------------- Slack 0.19 (MET) max capacitance Pin reg1/Q ^ max capacitance 60.73 capacitance 2.11 ----------------------- Slack 58.62 (MET) Pin: reg1/CK Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 reg1/CK 0.00 open edge arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 reg1/CK 0.00 5.00 clock reconvergence pessimism 5.00 close edge arrival time --------------------------------------------------------- 0.05 required pulse width (high) 5.00 actual pulse width --------------------------------------------------------- 4.95 slack (MET) PASS: report_check_types verbose --- report_check_types individual --- Group Slack -------------------------------------------- clk 7.90 clk2 4.88 Group Slack -------------------------------------------- clk 1.04 clk2 0.08 max slew Pin Limit Slew Slack ------------------------------------------------------------ reg1/QN 0.20 0.01 0.19 (MET) max capacitance Pin Limit Cap Slack ------------------------------------------------------------ reg1/Q 60.73 2.11 58.62 (MET) Required Actual Pin Width Width Slack ------------------------------------------------------------ reg1/CK (high) 0.05 5.00 4.95 (MET) Group Slack -------------------------------------------- No paths found. PASS: report_check_types individual --- set_max_transition and check --- max slew Pin reg1/QN v max slew 0.20 slew 0.01 ---------------- Slack 0.19 (MET) PASS: set_max_transition check --- set_max_capacitance and check --- max capacitance Pin reg1/Q ^ max capacitance 0.05 capacitance 2.11 ----------------------- Slack -2.06 (VIOLATED) PASS: set_max_capacitance check --- set_max_fanout and check --- max fanout Pin reg1/Q max fanout 10 fanout 2 ----------------- Slack 8 (MET) PASS: set_max_fanout check --- report_checks with unconstrained --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) PASS: report_checks unconstrained --- set_clock_groups and check --- Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Endpoint: out2 (output port clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk2 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.02 0.10 ^ buf3/Z (BUF_X1) 0.00 0.10 ^ out2 (out) 0.10 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism -2.00 13.00 output external delay 13.00 data required time --------------------------------------------------------- 13.00 data required time -0.10 data arrival time --------------------------------------------------------- 12.90 slack (MET) Warning: There are 2 input ports missing set_input_delay. in3 in_unconst Warning: There is 1 output port missing set_output_delay. out_unconst Warning: There are 2 unconstrained endpoints. out_unconst reg3/D PASS: clock_groups check --- report_clock_min_period --- clk period_min = 0.00 fmax = inf clk2 period_min = 0.00 fmax = inf clk period_min = 2.10 fmax = 475.37 clk2 period_min = 2.10 fmax = 476.13 clk period_min = 0.00 fmax = inf clk2 period_min = 0.00 fmax = inf PASS: clock_min_period --- Gated clock enable settings --- gated_clk_enable: 1 Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) PASS: gated clock enable settings --- Gated clock check settings --- gated_clk_checks: 1 Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) PASS: gated clock checks --- Recovery/removal checks --- recovery_removal: 1 Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.09 0.09 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: reg2 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg2/D (DFF_X1) 10.08 data arrival time 15.00 15.00 clock clk2 (rise edge) 0.00 15.00 clock network delay (ideal) 0.00 15.00 clock reconvergence pessimism 15.00 ^ reg2/CK (DFF_X1) -0.04 14.96 library setup time 14.96 data required time --------------------------------------------------------- 14.96 data required time -10.08 data arrival time --------------------------------------------------------- 4.88 slack (MET) PASS: recovery/removal settings --- Various STA variable settings --- preset_clr: 1 cond_default: 1 bidirect_inst: 1 bidirect_net: 1 dynamic_loop: 1 default_arrival_clk: 1 PASS: variable settings ALL PASSED