--- report_tns max --- tns max 0.00 --- report_tns min --- tns min 0.00 --- report_wns max --- wns max 0.00 --- report_wns min --- wns min 0.00 --- report_worst_slack max --- worst slack max 7.90 --- report_worst_slack min --- worst slack min 1.04 --- check_setup verbose --- --- check_setup specific flags --- --- check_setup no_clock --- --- check_setup unconstrained --- --- check_setup loops --- --- check_setup generated_clocks --- --- report_check_types verbose --- Startpoint: in1 (input port clocked by clk) Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 1.00 1.00 ^ input external delay 0.00 1.00 ^ in1 (in) 0.02 1.02 ^ and1/ZN (AND2_X1) 0.02 1.04 ^ buf1/Z (BUF_X1) 0.00 1.04 ^ reg1/D (DFF_X1) 1.04 data arrival time 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 clock reconvergence pessimism 0.00 ^ reg1/CK (DFF_X1) 0.00 0.00 library hold time 0.00 data required time --------------------------------------------------------- 0.00 data required time -1.04 data arrival time --------------------------------------------------------- 1.04 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk) Endpoint: out1 (output port clocked by clk) Path Group: clk Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg1/CK (DFF_X1) 0.08 0.08 ^ reg1/Q (DFF_X1) 0.02 0.10 ^ buf2/Z (BUF_X1) 0.00 0.10 ^ out1 (out) 0.10 data arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -2.00 8.00 output external delay 8.00 data required time --------------------------------------------------------- 8.00 data required time -0.10 data arrival time --------------------------------------------------------- 7.90 slack (MET) max slew Pin reg1/QN v max slew 0.20 slew 0.01 ---------------- Slack 0.19 (MET) max capacitance Pin buf1/Z ^ max capacitance 60.65 capacitance 1.14 ----------------------- Slack 59.51 (MET) Pin: reg1/CK Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 reg1/CK 0.00 open edge arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 reg1/CK 0.00 5.00 clock reconvergence pessimism 5.00 close edge arrival time --------------------------------------------------------- 0.05 required pulse width (high) 5.00 actual pulse width --------------------------------------------------------- 4.95 slack (MET) --- report_check_types max_delay --- Group Slack -------------------------------------------- clk 7.90 --- report_check_types min_delay --- Group Slack -------------------------------------------- clk 1.04 --- report_check_types max_slew --- max slew Pin Limit Slew Slack ------------------------------------------------------------ reg1/QN 0.20 0.01 0.19 (MET) --- report_check_types max_fanout --- --- report_check_types max_capacitance --- max capacitance Pin Limit Cap Slack ------------------------------------------------------------ buf1/Z 60.65 1.14 59.51 (MET) --- report_check_types min_pulse_width --- Required Actual Pin Width Width Slack ------------------------------------------------------------ reg1/CK (high) 0.05 5.00 4.95 (MET) --- report_check_types min_period --- --- report_check_types max_skew --- --- report_check_types violators --- Group Slack -------------------------------------------- No paths found. --- report_clock_skew setup --- Clock clk No launch/capture paths found. --- report_clock_skew hold --- Clock clk No launch/capture paths found. --- report_clock_skew -include_internal_latency --- Clock clk No launch/capture paths found. --- report_clock_latency --- Clock clk rise -> rise min max 0.00 0.00 source latency 0.00 network latency reg1/CK 0.00 network latency reg1/CK --------------- 0.00 0.00 latency 0.00 skew fall -> fall min max 0.00 0.00 source latency 0.00 network latency reg1/CK 0.00 network latency reg1/CK --------------- 0.00 0.00 latency 0.00 skew --- report_clock_latency -include_internal_latency --- Clock clk rise -> rise min max 0.00 0.00 source latency 0.00 network latency reg1/CK 0.00 network latency reg1/CK --------------- 0.00 0.00 latency 0.00 skew fall -> fall min max 0.00 0.00 source latency 0.00 network latency reg1/CK 0.00 network latency reg1/CK --------------- 0.00 0.00 latency 0.00 skew --- report_clock_min_period --- clk period_min = 0.00 fmax = inf --- report_clock_min_period -include_port_paths --- clk period_min = 2.10 fmax = 476.13 --- report_clock_properties --- Clock Period Waveform ---------------------------------------------------- clk 10.00 0.00 5.00 --- report_clock_properties clk --- Clock Period Waveform ---------------------------------------------------- clk 10.00 0.00 5.00 --- report_pulse_width_checks --- Required Actual Pin Width Width Slack ------------------------------------------------------------ reg1/CK (high) 0.05 5.00 4.95 (MET) reg1/CK (low) 0.05 5.00 4.95 (MET) --- report_pulse_width_checks verbose --- Pin: reg1/CK Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 reg1/CK 0.00 open edge arrival time 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 reg1/CK 0.00 5.00 clock reconvergence pessimism 5.00 close edge arrival time --------------------------------------------------------- 0.05 required pulse width (high) 5.00 actual pulse width --------------------------------------------------------- 4.95 slack (MET) Pin: reg1/CK Check: sequential_clock_pulse_width Delay Time Description --------------------------------------------------------- 5.00 5.00 clock clk (fall edge) 0.00 5.00 clock network delay (ideal) 0.00 5.00 reg1/CK 5.00 open edge arrival time 10.00 10.00 clock clk (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 reg1/CK 0.00 10.00 clock reconvergence pessimism 10.00 close edge arrival time --------------------------------------------------------- 0.05 required pulse width (low) 5.00 actual pulse width --------------------------------------------------------- 4.95 slack (MET) --- report_pulse_width_checks on pin --- Required Actual Pin Width Width Slack ------------------------------------------------------------ reg1/CK (high) 0.05 5.00 4.95 (MET) reg1/CK (low) 0.05 5.00 4.95 (MET) --- report_disabled_edges --- --- report_constant on instance --- VDD X VSS X A1 X A2 X ZN X --- report_constant on pin --- A1 X --- find_timing_paths max --- Found 1 max paths --- find_timing_paths min --- Found 1 min paths --- find_timing_paths min_max --- Found 2 min_max paths --- find_timing_paths with constraints --- Found 1 paths from in1 --- find_timing_paths -endpoint_path_count --- Found 3 paths with endpoint_path_count 3 --- find_timing_paths -group_path_count --- Found 5 paths with group_path_count 5 --- find_timing_paths -sort_by_slack --- Found 3 sorted paths --- find_timing_paths -unique_paths_to_endpoint --- Found 3 unique paths --- find_timing_paths -slack_max --- Found 1 paths with slack_max 100 --- report_tns with digits --- tns max 0.000000 --- report_wns with digits --- wns max 0.000000 --- report_worst_slack with digits --- worst slack max 7.899714 --- report_arrival --- (clk ^) r 0.08:0.08 f 0.08:0.08 --- report_required --- (clk ^) r 0.00:9.97 f 0.00:9.96 --- report_slack --- (clk ^) r 1.04:8.92 f 1.04:8.91 --- worst_slack hidden cmd --- Worst slack (max): 7.899713995438537 --- worst_slack min --- Worst slack (min): 1.0391781063125174 --- total_negative_slack hidden cmd --- TNS (max): 0.0 --- worst_negative_slack hidden cmd --- WNS (max): 0.0 ALL analysis tests PASSED