PASS: setup Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg3/D (DFF_X1) 10.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg3/CK (DFF_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -10.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) PASS: input transition PASS: set_drive in1 PASS: set_drive in2 rise/fall PASS: set_drive in3 rise/fall min/max Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg3/D (DFF_X1) 10.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg3/CK (DFF_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -10.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) PASS: report after drive resistance PASS: set_driving_cell BUF_X1 PASS: set_driving_cell INV_X1 PASS: set_driving_cell AND2_X1 with from_pin PASS: set_driving_cell BUF_X4 with slews PASS: set_driving_cell with -library PASS: set_driving_cell rise/fall PASS: set_driving_cell min/max Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg3/D (DFF_X1) 10.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg3/CK (DFF_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -10.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) PASS: report after driving cells PASS: write_sdc PASS: write_sdc compatible PASS: set_operating_conditions typical Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg3/D (DFF_X1) 10.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg3/CK (DFF_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -10.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) PASS: report after operating conditions PASS: analysis type single PASS: analysis type bc_wc PASS: analysis type ocv PASS: reset to single PASS: operating conditions analysis_type bc_wc PASS: operating conditions analysis_type single PASS: set_pvt buf1 PASS: set_pvt inv1 PASS: wire_load_model PASS: wire_load_mode enclosed PASS: wire_load_mode top PASS: wire_load_mode segmented PASS: propagate_all_clocks PASS: write_sdc with all environment PASS: write_sdc digits 6 Startpoint: reg2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: out1 (output port clocked by clk1) Path Group: clk1 Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock clk1 (rise edge) 0.00 0.00 clock network delay (ideal) 0.00 0.00 ^ reg2/CK (DFF_X1) 0.08 0.08 ^ reg2/Q (DFF_X1) 0.00 0.08 ^ out1 (out) 0.08 data arrival time 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 clock reconvergence pessimism -3.00 7.00 output external delay 7.00 data required time --------------------------------------------------------- 7.00 data required time -0.08 data arrival time --------------------------------------------------------- 6.92 slack (MET) Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk1) Endpoint: reg3 (rising edge-triggered flip-flop clocked by clk2) Path Group: clk2 Path Type: max Delay Time Description --------------------------------------------------------- 10.00 10.00 clock clk1 (rise edge) 0.00 10.00 clock network delay (ideal) 0.00 10.00 ^ reg1/CK (DFF_X1) 0.08 10.08 v reg1/Q (DFF_X1) 0.00 10.08 v reg3/D (DFF_X1) 10.08 data arrival time 20.00 20.00 clock clk2 (rise edge) 0.00 20.00 clock network delay (ideal) 0.00 20.00 clock reconvergence pessimism 20.00 ^ reg3/CK (DFF_X1) -0.04 19.96 library setup time 19.96 data required time --------------------------------------------------------- 19.96 data required time -10.08 data arrival time --------------------------------------------------------- 9.88 slack (MET) PASS: read_sdc roundtrip PASS: port ext cap PASS: port fanout number PASS: final write_sdc ALL PASSED