PASS: create_clock
PASS: set_input_delay
PASS: set_output_delay
Clock                   Period          Waveform
----------------------------------------------------
clk                      10.00        0.00      5.00
PASS: report_clock_properties
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 ^ reg1/CK (DFF_X1)
   0.08    0.08 ^ reg1/Q (DFF_X1)
   0.00    0.08 ^ out1 (out)
           0.08   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
  -3.00    7.00   output external delay
           7.00   data required time
---------------------------------------------------------
           7.00   data required time
          -0.08   data arrival time
---------------------------------------------------------
           6.92   slack (MET)


PASS: report_checks with SDC constraints
ALL PASSED